Skip to content

Commit abe7810

Browse files
authored
Merge pull request #135 from ch1bo/fix-flushtqueue
io-sim: Fix flushTQueue implementation
2 parents f6919ea + 959ecec commit abe7810

File tree

6 files changed

+42
-3
lines changed

6 files changed

+42
-3
lines changed

io-classes/CHANGELOG.md

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,8 @@
88

99
### Non-breaking changes
1010

11+
* Fixed some module haddock typos.
12+
1113
## 1.3.1.0
1214

1315
### Non-breaking changes

io-classes/src/Control/Concurrent/Class/MonadSTM/TQueue.hs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
{-# LANGUAGE ExplicitNamespaces #-}
22

3-
-- | This module corresponds to `Control.Concurrnet.STM.TVar` in "stm" package
3+
-- | This module corresponds to `Control.Concurrent.STM.TQueue` in "stm" package
44
--
55
module Control.Concurrent.Class.MonadSTM.TQueue
66
( -- * MonadSTM

io-classes/src/Control/Monad/Class/MonadSTM/Internal.hs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -48,7 +48,7 @@ module Control.Monad.Class.MonadSTM.Internal
4848
, isEmptyTMVarDefault
4949
, labelTMVarDefault
5050
, traceTMVarDefault
51-
-- ** Default 'TBQueue' implementation
51+
-- ** Default 'TQueue' implementation
5252
, TQueueDefault (..)
5353
, newTQueueDefault
5454
, writeTQueueDefault

io-sim/CHANGELOG.md

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -9,6 +9,7 @@
99
### Non-breaking changes
1010

1111
* `Alternative` & `MonadPlus` instances for `IOSim`.
12+
* Fixed `flushTQueue` implemetation.
1213

1314
## 1.3.1.0
1415

io-sim/src/Control/Monad/IOSim/STM.hs

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -95,7 +95,10 @@ tryPeekTQueueDefault (TQueue queue) = do
9595
[] -> Nothing
9696

9797
flushTQueueDefault :: MonadSTM m => TQueueDefault m a -> STM m [a]
98-
flushTQueueDefault (TQueue queue) = uncurry (++) <$> readTVar queue
98+
flushTQueueDefault (TQueue queue) = do
99+
(xs, ys) <- readTVar queue
100+
writeTVar queue ([], [])
101+
pure (xs <> reverse ys)
99102

100103
unGetTQueueDefault :: MonadSTM m => TQueueDefault m a -> a -> STM m ()
101104
unGetTQueueDefault (TQueue queue) a = do

io-sim/test/Test/Control/Monad/IOSim.hs

Lines changed: 33 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -176,6 +176,12 @@ tests =
176176
, testProperty "registerDelayCancellable (IO impl)"
177177
prop_registerDelayCancellable_IO
178178
]
179+
, testGroup "MonadSTM"
180+
[ testGroup "flushTQueue"
181+
[ testProperty "empties the queue" prop_flushTQueueEmpties
182+
, testProperty "maintains FIFO order" prop_flushTQueueOrder
183+
]
184+
]
179185
]
180186

181187
--
@@ -1348,6 +1354,33 @@ prop_registerDelayCancellable_IO =
13481354
cancelTimeout
13491355
awaitTimeout
13501356

1357+
-- | Test that 'flushTQueue' empties the queue.
1358+
prop_flushTQueueEmpties :: Property
1359+
prop_flushTQueueEmpties =
1360+
ioProperty emptyQueueAfterFlush
1361+
.&&. runSimOrThrow emptyQueueAfterFlush
1362+
1363+
emptyQueueAfterFlush :: MonadSTM m => m Bool
1364+
emptyQueueAfterFlush = do
1365+
q <- newTQueueIO
1366+
atomically $ do
1367+
writeTQueue q (1 :: Int)
1368+
_ <- flushTQueue q
1369+
isEmptyTQueue q
1370+
1371+
-- | Test that 'flushTQueue' returns values in FIFO order.
1372+
prop_flushTQueueOrder :: [Int] -> Property
1373+
prop_flushTQueueOrder entries =
1374+
ioProperty (writeAndFlushQueue entries >>= \actual -> pure $ actual === entries)
1375+
.&&. runSimOrThrow (writeAndFlushQueue entries) === entries
1376+
1377+
writeAndFlushQueue :: MonadSTM m => [Int] -> m [Int]
1378+
writeAndFlushQueue entries =
1379+
atomically $ do
1380+
q <- newTQueue
1381+
forM_ entries $ writeTQueue q
1382+
flushTQueue q
1383+
13511384
--
13521385
-- Utils
13531386
--

0 commit comments

Comments
 (0)