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at91sam7s512.h
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// ----------------------------------------------------------------------------
// ATMEL Microcontroller Software Support - ROUSSET -
// ----------------------------------------------------------------------------
// Copyright (c) 2006, Atmel Corporation
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// - Redistributions of source code must retain the above copyright notice,
// this list of conditions and the disclaimer below.
//
// Atmel's name may not be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ----------------------------------------------------------------------------
// File Name : AT91SAM7S512.h
// Object : AT91SAM7S512 definitions
// Generated : AT91 SW Application Group 07/07/2008 (16:13:20)
//
// CVS Reference : /AT91SAM7S512.pl/1.6/Wed Aug 30 14:08:44 2006//
// CVS Reference : /SYS_SAM7S.pl/1.2/Thu Feb 3 10:47:39 2005//
// CVS Reference : /MC_SAM7SE.pl/1.10/Thu Feb 16 16:35:28 2006//
// CVS Reference : /PMC_SAM7S_USB.pl/1.4/Tue Feb 8 14:00:19 2005//
// CVS Reference : /RSTC_SAM7S.pl/1.2/Wed Jul 13 15:25:17 2005//
// CVS Reference : /UDP_4ept.pl/1.1/Thu Aug 3 12:26:00 2006//
// CVS Reference : /PWM_SAM7S.pl/1.1/Tue May 10 12:38:54 2005//
// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:21:42 2005//
// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:29:42 2005//
// CVS Reference : /RTTC_6081A.pl/1.2/Thu Nov 4 13:57:22 2004//
// CVS Reference : /PITC_6079A.pl/1.2/Thu Nov 4 13:56:22 2004//
// CVS Reference : /WDTC_6080A.pl/1.3/Thu Nov 4 13:58:52 2004//
// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:40:38 2005//
// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 09:02:11 2005//
// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:54:41 2005//
// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:23:02 2005//
// CVS Reference : /US_6089C.pl/1.1/Mon Jan 31 13:56:02 2005//
// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:10:41 2004//
// CVS Reference : /TWI_6061A.pl/1.2/Fri Oct 27 11:40:48 2006//
// CVS Reference : /TC_6082A.pl/1.7/Wed Mar 9 16:31:51 2005//
// CVS Reference : /ADC_6051C.pl/1.1/Mon Jan 31 13:12:40 2005//
// CVS Reference : /EBI_SAM7SE512.pl/1.22/Fri Nov 18 17:47:47 2005//
// CVS Reference : /SMC_1783A.pl/1.4/Thu Feb 3 10:30:06 2005//
// CVS Reference : /SDRC_SAM7SE512.pl/1.7/Fri Jul 8 07:50:18 2005//
// CVS Reference : /HECC_SAM7SE512.pl/1.8/Tue Jul 12 06:31:42 2005//
// ----------------------------------------------------------------------------
#ifndef AT91SAM7S512_H
#define AT91SAM7S512_H
#ifndef __ASSEMBLY__
typedef volatile unsigned int AT91_REG;// Hardware register definition
#define AT91_CAST(a) (a)
#else
#define AT91_CAST(a)
#endif
// *****************************************************************************
// SOFTWARE API DEFINITION FOR System Peripherals
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_SYS {
AT91_REG AIC_SMR[32]; // Source Mode Register
AT91_REG AIC_SVR[32]; // Source Vector Register
AT91_REG AIC_IVR; // IRQ Vector Register
AT91_REG AIC_FVR; // FIQ Vector Register
AT91_REG AIC_ISR; // Interrupt Status Register
AT91_REG AIC_IPR; // Interrupt Pending Register
AT91_REG AIC_IMR; // Interrupt Mask Register
AT91_REG AIC_CISR; // Core Interrupt Status Register
AT91_REG Reserved0[2]; //
AT91_REG AIC_IECR; // Interrupt Enable Command Register
AT91_REG AIC_IDCR; // Interrupt Disable Command Register
AT91_REG AIC_ICCR; // Interrupt Clear Command Register
AT91_REG AIC_ISCR; // Interrupt Set Command Register
AT91_REG AIC_EOICR; // End of Interrupt Command Register
AT91_REG AIC_SPU; // Spurious Vector Register
AT91_REG AIC_DCR; // Debug Control Register (Protect)
AT91_REG Reserved1[1]; //
AT91_REG AIC_FFER; // Fast Forcing Enable Register
AT91_REG AIC_FFDR; // Fast Forcing Disable Register
AT91_REG AIC_FFSR; // Fast Forcing Status Register
AT91_REG Reserved2[45]; //
AT91_REG DBGU_CR; // Control Register
AT91_REG DBGU_MR; // Mode Register
AT91_REG DBGU_IER; // Interrupt Enable Register
AT91_REG DBGU_IDR; // Interrupt Disable Register
AT91_REG DBGU_IMR; // Interrupt Mask Register
AT91_REG DBGU_CSR; // Channel Status Register
AT91_REG DBGU_RHR; // Receiver Holding Register
AT91_REG DBGU_THR; // Transmitter Holding Register
AT91_REG DBGU_BRGR; // Baud Rate Generator Register
AT91_REG Reserved3[7]; //
AT91_REG DBGU_CIDR; // Chip ID Register
AT91_REG DBGU_EXID; // Chip ID Extension Register
AT91_REG DBGU_FNTR; // Force NTRST Register
AT91_REG Reserved4[45]; //
AT91_REG DBGU_RPR; // Receive Pointer Register
AT91_REG DBGU_RCR; // Receive Counter Register
AT91_REG DBGU_TPR; // Transmit Pointer Register
AT91_REG DBGU_TCR; // Transmit Counter Register
AT91_REG DBGU_RNPR; // Receive Next Pointer Register
AT91_REG DBGU_RNCR; // Receive Next Counter Register
AT91_REG DBGU_TNPR; // Transmit Next Pointer Register
AT91_REG DBGU_TNCR; // Transmit Next Counter Register
AT91_REG DBGU_PTCR; // PDC Transfer Control Register
AT91_REG DBGU_PTSR; // PDC Transfer Status Register
AT91_REG Reserved5[54]; //
AT91_REG PIOA_PER; // PIO Enable Register
AT91_REG PIOA_PDR; // PIO Disable Register
AT91_REG PIOA_PSR; // PIO Status Register
AT91_REG Reserved6[1]; //
AT91_REG PIOA_OER; // Output Enable Register
AT91_REG PIOA_ODR; // Output Disable Registerr
AT91_REG PIOA_OSR; // Output Status Register
AT91_REG Reserved7[1]; //
AT91_REG PIOA_IFER; // Input Filter Enable Register
AT91_REG PIOA_IFDR; // Input Filter Disable Register
AT91_REG PIOA_IFSR; // Input Filter Status Register
AT91_REG Reserved8[1]; //
AT91_REG PIOA_SODR; // Set Output Data Register
AT91_REG PIOA_CODR; // Clear Output Data Register
AT91_REG PIOA_ODSR; // Output Data Status Register
AT91_REG PIOA_PDSR; // Pin Data Status Register
AT91_REG PIOA_IER; // Interrupt Enable Register
AT91_REG PIOA_IDR; // Interrupt Disable Register
AT91_REG PIOA_IMR; // Interrupt Mask Register
AT91_REG PIOA_ISR; // Interrupt Status Register
AT91_REG PIOA_MDER; // Multi-driver Enable Register
AT91_REG PIOA_MDDR; // Multi-driver Disable Register
AT91_REG PIOA_MDSR; // Multi-driver Status Register
AT91_REG Reserved9[1]; //
AT91_REG PIOA_PPUDR; // Pull-up Disable Register
AT91_REG PIOA_PPUER; // Pull-up Enable Register
AT91_REG PIOA_PPUSR; // Pull-up Status Register
AT91_REG Reserved10[1]; //
AT91_REG PIOA_ASR; // Select A Register
AT91_REG PIOA_BSR; // Select B Register
AT91_REG PIOA_ABSR; // AB Select Status Register
AT91_REG Reserved11[9]; //
AT91_REG PIOA_OWER; // Output Write Enable Register
AT91_REG PIOA_OWDR; // Output Write Disable Register
AT91_REG PIOA_OWSR; // Output Write Status Register
AT91_REG Reserved12[469]; //
AT91_REG PMC_SCER; // System Clock Enable Register
AT91_REG PMC_SCDR; // System Clock Disable Register
AT91_REG PMC_SCSR; // System Clock Status Register
AT91_REG Reserved13[1]; //
AT91_REG PMC_PCER; // Peripheral Clock Enable Register
AT91_REG PMC_PCDR; // Peripheral Clock Disable Register
AT91_REG PMC_PCSR; // Peripheral Clock Status Register
AT91_REG Reserved14[1]; //
AT91_REG PMC_MOR; // Main Oscillator Register
AT91_REG PMC_MCFR; // Main Clock Frequency Register
AT91_REG Reserved15[1]; //
AT91_REG PMC_PLLR; // PLL Register
AT91_REG PMC_MCKR; // Master Clock Register
AT91_REG Reserved16[3]; //
AT91_REG PMC_PCKR[3]; // Programmable Clock Register
AT91_REG Reserved17[5]; //
AT91_REG PMC_IER; // Interrupt Enable Register
AT91_REG PMC_IDR; // Interrupt Disable Register
AT91_REG PMC_SR; // Status Register
AT91_REG PMC_IMR; // Interrupt Mask Register
AT91_REG Reserved18[36]; //
AT91_REG RSTC_RCR; // Reset Control Register
AT91_REG RSTC_RSR; // Reset Status Register
AT91_REG RSTC_RMR; // Reset Mode Register
AT91_REG Reserved19[5]; //
AT91_REG RTTC_RTMR; // Real-time Mode Register
AT91_REG RTTC_RTAR; // Real-time Alarm Register
AT91_REG RTTC_RTVR; // Real-time Value Register
AT91_REG RTTC_RTSR; // Real-time Status Register
AT91_REG PITC_PIMR; // Period Interval Mode Register
AT91_REG PITC_PISR; // Period Interval Status Register
AT91_REG PITC_PIVR; // Period Interval Value Register
AT91_REG PITC_PIIR; // Period Interval Image Register
AT91_REG WDTC_WDCR; // Watchdog Control Register
AT91_REG WDTC_WDMR; // Watchdog Mode Register
AT91_REG WDTC_WDSR; // Watchdog Status Register
AT91_REG Reserved20[5]; //
AT91_REG VREG_MR; // Voltage Regulator Mode Register
} AT91S_SYS, *AT91PS_SYS;
#else
#endif
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_AIC {
AT91_REG AIC_SMR[32]; // Source Mode Register
AT91_REG AIC_SVR[32]; // Source Vector Register
AT91_REG AIC_IVR; // IRQ Vector Register
AT91_REG AIC_FVR; // FIQ Vector Register
AT91_REG AIC_ISR; // Interrupt Status Register
AT91_REG AIC_IPR; // Interrupt Pending Register
AT91_REG AIC_IMR; // Interrupt Mask Register
AT91_REG AIC_CISR; // Core Interrupt Status Register
AT91_REG Reserved0[2]; //
AT91_REG AIC_IECR; // Interrupt Enable Command Register
AT91_REG AIC_IDCR; // Interrupt Disable Command Register
AT91_REG AIC_ICCR; // Interrupt Clear Command Register
AT91_REG AIC_ISCR; // Interrupt Set Command Register
AT91_REG AIC_EOICR; // End of Interrupt Command Register
AT91_REG AIC_SPU; // Spurious Vector Register
AT91_REG AIC_DCR; // Debug Control Register (Protect)
AT91_REG Reserved1[1]; //
AT91_REG AIC_FFER; // Fast Forcing Enable Register
AT91_REG AIC_FFDR; // Fast Forcing Disable Register
AT91_REG AIC_FFSR; // Fast Forcing Status Register
} AT91S_AIC, *AT91PS_AIC;
#else
#define AIC_SMR (AT91_CAST(AT91_REG *) 0x00000000) // (AIC_SMR) Source Mode Register
#define AIC_SVR (AT91_CAST(AT91_REG *) 0x00000080) // (AIC_SVR) Source Vector Register
#define AIC_IVR (AT91_CAST(AT91_REG *) 0x00000100) // (AIC_IVR) IRQ Vector Register
#define AIC_FVR (AT91_CAST(AT91_REG *) 0x00000104) // (AIC_FVR) FIQ Vector Register
#define AIC_ISR (AT91_CAST(AT91_REG *) 0x00000108) // (AIC_ISR) Interrupt Status Register
#define AIC_IPR (AT91_CAST(AT91_REG *) 0x0000010C) // (AIC_IPR) Interrupt Pending Register
#define AIC_IMR (AT91_CAST(AT91_REG *) 0x00000110) // (AIC_IMR) Interrupt Mask Register
#define AIC_CISR (AT91_CAST(AT91_REG *) 0x00000114) // (AIC_CISR) Core Interrupt Status Register
#define AIC_IECR (AT91_CAST(AT91_REG *) 0x00000120) // (AIC_IECR) Interrupt Enable Command Register
#define AIC_IDCR (AT91_CAST(AT91_REG *) 0x00000124) // (AIC_IDCR) Interrupt Disable Command Register
#define AIC_ICCR (AT91_CAST(AT91_REG *) 0x00000128) // (AIC_ICCR) Interrupt Clear Command Register
#define AIC_ISCR (AT91_CAST(AT91_REG *) 0x0000012C) // (AIC_ISCR) Interrupt Set Command Register
#define AIC_EOICR (AT91_CAST(AT91_REG *) 0x00000130) // (AIC_EOICR) End of Interrupt Command Register
#define AIC_SPU (AT91_CAST(AT91_REG *) 0x00000134) // (AIC_SPU) Spurious Vector Register
#define AIC_DCR (AT91_CAST(AT91_REG *) 0x00000138) // (AIC_DCR) Debug Control Register (Protect)
#define AIC_FFER (AT91_CAST(AT91_REG *) 0x00000140) // (AIC_FFER) Fast Forcing Enable Register
#define AIC_FFDR (AT91_CAST(AT91_REG *) 0x00000144) // (AIC_FFDR) Fast Forcing Disable Register
#define AIC_FFSR (AT91_CAST(AT91_REG *) 0x00000148) // (AIC_FFSR) Fast Forcing Status Register
#endif
// -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------
#define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level
#define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level
#define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level
#define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type
#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL (0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive
#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL (0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive
#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE (0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered
#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE (0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered
#define AT91C_AIC_SRCTYPE_HIGH_LEVEL (0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive
#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE (0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered
// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------
#define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status
#define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status
// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) --------
#define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode
#define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Peripheral DMA Controller
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_PDC {
AT91_REG PDC_RPR; // Receive Pointer Register
AT91_REG PDC_RCR; // Receive Counter Register
AT91_REG PDC_TPR; // Transmit Pointer Register
AT91_REG PDC_TCR; // Transmit Counter Register
AT91_REG PDC_RNPR; // Receive Next Pointer Register
AT91_REG PDC_RNCR; // Receive Next Counter Register
AT91_REG PDC_TNPR; // Transmit Next Pointer Register
AT91_REG PDC_TNCR; // Transmit Next Counter Register
AT91_REG PDC_PTCR; // PDC Transfer Control Register
AT91_REG PDC_PTSR; // PDC Transfer Status Register
} AT91S_PDC, *AT91PS_PDC;
#else
#define PDC_RPR (AT91_CAST(AT91_REG *) 0x00000000) // (PDC_RPR) Receive Pointer Register
#define PDC_RCR (AT91_CAST(AT91_REG *) 0x00000004) // (PDC_RCR) Receive Counter Register
#define PDC_TPR (AT91_CAST(AT91_REG *) 0x00000008) // (PDC_TPR) Transmit Pointer Register
#define PDC_TCR (AT91_CAST(AT91_REG *) 0x0000000C) // (PDC_TCR) Transmit Counter Register
#define PDC_RNPR (AT91_CAST(AT91_REG *) 0x00000010) // (PDC_RNPR) Receive Next Pointer Register
#define PDC_RNCR (AT91_CAST(AT91_REG *) 0x00000014) // (PDC_RNCR) Receive Next Counter Register
#define PDC_TNPR (AT91_CAST(AT91_REG *) 0x00000018) // (PDC_TNPR) Transmit Next Pointer Register
#define PDC_TNCR (AT91_CAST(AT91_REG *) 0x0000001C) // (PDC_TNCR) Transmit Next Counter Register
#define PDC_PTCR (AT91_CAST(AT91_REG *) 0x00000020) // (PDC_PTCR) PDC Transfer Control Register
#define PDC_PTSR (AT91_CAST(AT91_REG *) 0x00000024) // (PDC_PTSR) PDC Transfer Status Register
#endif
// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register --------
#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable
#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable
#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable
#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable
// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Debug Unit
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_DBGU {
AT91_REG DBGU_CR; // Control Register
AT91_REG DBGU_MR; // Mode Register
AT91_REG DBGU_IER; // Interrupt Enable Register
AT91_REG DBGU_IDR; // Interrupt Disable Register
AT91_REG DBGU_IMR; // Interrupt Mask Register
AT91_REG DBGU_CSR; // Channel Status Register
AT91_REG DBGU_RHR; // Receiver Holding Register
AT91_REG DBGU_THR; // Transmitter Holding Register
AT91_REG DBGU_BRGR; // Baud Rate Generator Register
AT91_REG Reserved0[7]; //
AT91_REG DBGU_CIDR; // Chip ID Register
AT91_REG DBGU_EXID; // Chip ID Extension Register
AT91_REG DBGU_FNTR; // Force NTRST Register
AT91_REG Reserved1[45]; //
AT91_REG DBGU_RPR; // Receive Pointer Register
AT91_REG DBGU_RCR; // Receive Counter Register
AT91_REG DBGU_TPR; // Transmit Pointer Register
AT91_REG DBGU_TCR; // Transmit Counter Register
AT91_REG DBGU_RNPR; // Receive Next Pointer Register
AT91_REG DBGU_RNCR; // Receive Next Counter Register
AT91_REG DBGU_TNPR; // Transmit Next Pointer Register
AT91_REG DBGU_TNCR; // Transmit Next Counter Register
AT91_REG DBGU_PTCR; // PDC Transfer Control Register
AT91_REG DBGU_PTSR; // PDC Transfer Status Register
} AT91S_DBGU, *AT91PS_DBGU;
#else
#define DBGU_CR (AT91_CAST(AT91_REG *) 0x00000000) // (DBGU_CR) Control Register
#define DBGU_MR (AT91_CAST(AT91_REG *) 0x00000004) // (DBGU_MR) Mode Register
#define DBGU_IER (AT91_CAST(AT91_REG *) 0x00000008) // (DBGU_IER) Interrupt Enable Register
#define DBGU_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (DBGU_IDR) Interrupt Disable Register
#define DBGU_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (DBGU_IMR) Interrupt Mask Register
#define DBGU_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (DBGU_CSR) Channel Status Register
#define DBGU_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (DBGU_RHR) Receiver Holding Register
#define DBGU_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (DBGU_THR) Transmitter Holding Register
#define DBGU_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (DBGU_BRGR) Baud Rate Generator Register
//#define DBGU_CIDR (AT91_CAST(AT91_REG *) 0x00000040) // (DBGU_CIDR) Chip ID Register
#define DBGU_EXID (AT91_CAST(AT91_REG *) 0x00000044) // (DBGU_EXID) Chip ID Extension Register
#define DBGU_FNTR (AT91_CAST(AT91_REG *) 0x00000048) // (DBGU_FNTR) Force NTRST Register
#endif
// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------
#define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver
#define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter
#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable
#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable
#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable
#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable
#define AT91C_US_RSTSTA (0x1 << 8) // (DBGU) Reset Status Bits
// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register --------
#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type
#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity
#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity
#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space)
#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark)
#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity
#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode
#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode
#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------
#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt
#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt
#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt
#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt
#define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt
#define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt
#define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt
#define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt
#define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt
#define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt
#define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt
#define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt
// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register --------
// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register --------
// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register --------
// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register --------
#define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Parallel Input Output Controler
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_PIO {
AT91_REG PIO_PER; // PIO Enable Register
AT91_REG PIO_PDR; // PIO Disable Register
AT91_REG PIO_PSR; // PIO Status Register
AT91_REG Reserved0[1]; //
AT91_REG PIO_OER; // Output Enable Register
AT91_REG PIO_ODR; // Output Disable Registerr
AT91_REG PIO_OSR; // Output Status Register
AT91_REG Reserved1[1]; //
AT91_REG PIO_IFER; // Input Filter Enable Register
AT91_REG PIO_IFDR; // Input Filter Disable Register
AT91_REG PIO_IFSR; // Input Filter Status Register
AT91_REG Reserved2[1]; //
AT91_REG PIO_SODR; // Set Output Data Register
AT91_REG PIO_CODR; // Clear Output Data Register
AT91_REG PIO_ODSR; // Output Data Status Register
AT91_REG PIO_PDSR; // Pin Data Status Register
AT91_REG PIO_IER; // Interrupt Enable Register
AT91_REG PIO_IDR; // Interrupt Disable Register
AT91_REG PIO_IMR; // Interrupt Mask Register
AT91_REG PIO_ISR; // Interrupt Status Register
AT91_REG PIO_MDER; // Multi-driver Enable Register
AT91_REG PIO_MDDR; // Multi-driver Disable Register
AT91_REG PIO_MDSR; // Multi-driver Status Register
AT91_REG Reserved3[1]; //
AT91_REG PIO_PPUDR; // Pull-up Disable Register
AT91_REG PIO_PPUER; // Pull-up Enable Register
AT91_REG PIO_PPUSR; // Pull-up Status Register
AT91_REG Reserved4[1]; //
AT91_REG PIO_ASR; // Select A Register
AT91_REG PIO_BSR; // Select B Register
AT91_REG PIO_ABSR; // AB Select Status Register
AT91_REG Reserved5[9]; //
AT91_REG PIO_OWER; // Output Write Enable Register
AT91_REG PIO_OWDR; // Output Write Disable Register
AT91_REG PIO_OWSR; // Output Write Status Register
} AT91S_PIO, *AT91PS_PIO;
#else
#define PIO_PER (AT91_CAST(AT91_REG *) 0x00000000) // (PIO_PER) PIO Enable Register
#define PIO_PDR (AT91_CAST(AT91_REG *) 0x00000004) // (PIO_PDR) PIO Disable Register
#define PIO_PSR (AT91_CAST(AT91_REG *) 0x00000008) // (PIO_PSR) PIO Status Register
#define PIO_OER (AT91_CAST(AT91_REG *) 0x00000010) // (PIO_OER) Output Enable Register
#define PIO_ODR (AT91_CAST(AT91_REG *) 0x00000014) // (PIO_ODR) Output Disable Register
#define PIO_OSR (AT91_CAST(AT91_REG *) 0x00000018) // (PIO_OSR) Output Status Register
#define PIO_IFER (AT91_CAST(AT91_REG *) 0x00000020) // (PIO_IFER) Input Filter Enable Register
#define PIO_IFDR (AT91_CAST(AT91_REG *) 0x00000024) // (PIO_IFDR) Input Filter Disable Register
#define PIO_IFSR (AT91_CAST(AT91_REG *) 0x00000028) // (PIO_IFSR) Input Filter Status Register
#define PIO_SODR (AT91_CAST(AT91_REG *) 0x00000030) // (PIO_SODR) Set Output Data Register
#define PIO_CODR (AT91_CAST(AT91_REG *) 0x00000034) // (PIO_CODR) Clear Output Data Register
#define PIO_ODSR (AT91_CAST(AT91_REG *) 0x00000038) // (PIO_ODSR) Output Data Status Register
#define PIO_PDSR (AT91_CAST(AT91_REG *) 0x0000003C) // (PIO_PDSR) Pin Data Status Register
#define PIO_IER (AT91_CAST(AT91_REG *) 0x00000040) // (PIO_IER) Interrupt Enable Register
#define PIO_IDR (AT91_CAST(AT91_REG *) 0x00000044) // (PIO_IDR) Interrupt Disable Register
#define PIO_IMR (AT91_CAST(AT91_REG *) 0x00000048) // (PIO_IMR) Interrupt Mask Register
#define PIO_ISR (AT91_CAST(AT91_REG *) 0x0000004C) // (PIO_ISR) Interrupt Status Register
#define PIO_MDER (AT91_CAST(AT91_REG *) 0x00000050) // (PIO_MDER) Multi-driver Enable Register
#define PIO_MDDR (AT91_CAST(AT91_REG *) 0x00000054) // (PIO_MDDR) Multi-driver Disable Register
#define PIO_MDSR (AT91_CAST(AT91_REG *) 0x00000058) // (PIO_MDSR) Multi-driver Status Register
#define PIO_PPUDR (AT91_CAST(AT91_REG *) 0x00000060) // (PIO_PPUDR) Pull-up Disable Register
#define PIO_PPUER (AT91_CAST(AT91_REG *) 0x00000064) // (PIO_PPUER) Pull-up Enable Register
#define PIO_PPUSR (AT91_CAST(AT91_REG *) 0x00000068) // (PIO_PPUSR) Pull-up Status Register
#define PIO_ASR (AT91_CAST(AT91_REG *) 0x00000070) // (PIO_ASR) Select A Register
#define PIO_BSR (AT91_CAST(AT91_REG *) 0x00000074) // (PIO_BSR) Select B Register
#define PIO_ABSR (AT91_CAST(AT91_REG *) 0x00000078) // (PIO_ABSR) AB Select Status Register
#define PIO_OWER (AT91_CAST(AT91_REG *) 0x000000A0) // (PIO_OWER) Output Write Enable Register
#define PIO_OWDR (AT91_CAST(AT91_REG *) 0x000000A4) // (PIO_OWDR) Output Write Disable Register
#define PIO_OWSR (AT91_CAST(AT91_REG *) 0x000000A8) // (PIO_OWSR) Output Write Status Register
#endif
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Clock Generator Controler
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_CKGR {
AT91_REG CKGR_MOR; // Main Oscillator Register
AT91_REG CKGR_MCFR; // Main Clock Frequency Register
AT91_REG Reserved0[1]; //
AT91_REG CKGR_PLLR; // PLL Register
} AT91S_CKGR, *AT91PS_CKGR;
#else
#define CKGR_MOR (AT91_CAST(AT91_REG *) 0x00000000) // (CKGR_MOR) Main Oscillator Register
#define CKGR_MCFR (AT91_CAST(AT91_REG *) 0x00000004) // (CKGR_MCFR) Main Clock Frequency Register
#define CKGR_PLLR (AT91_CAST(AT91_REG *) 0x0000000C) // (CKGR_PLLR) PLL Register
#endif
// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register --------
#define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable
#define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass
#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time
// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register --------
#define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency
#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready
// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register --------
#define AT91C_CKGR_DIV (0xFF << 0) // (CKGR) Divider Selected
#define AT91C_CKGR_DIV_0 (0x0) // (CKGR) Divider output is 0
#define AT91C_CKGR_DIV_BYPASS (0x1) // (CKGR) Divider is bypassed
#define AT91C_CKGR_PLLCOUNT (0x3F << 8) // (CKGR) PLL Counter
#define AT91C_CKGR_OUT (0x3 << 14) // (CKGR) PLL Output Frequency Range
#define AT91C_CKGR_OUT_0 (0x0 << 14) // (CKGR) Please refer to the PLL datasheet
#define AT91C_CKGR_OUT_1 (0x1 << 14) // (CKGR) Please refer to the PLL datasheet
#define AT91C_CKGR_OUT_2 (0x2 << 14) // (CKGR) Please refer to the PLL datasheet
#define AT91C_CKGR_OUT_3 (0x3 << 14) // (CKGR) Please refer to the PLL datasheet
#define AT91C_CKGR_MUL (0x7FF << 16) // (CKGR) PLL Multiplier
#define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks
#define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output
#define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
#define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Power Management Controler
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_PMC {
AT91_REG PMC_SCER; // System Clock Enable Register
AT91_REG PMC_SCDR; // System Clock Disable Register
AT91_REG PMC_SCSR; // System Clock Status Register
AT91_REG Reserved0[1]; //
AT91_REG PMC_PCER; // Peripheral Clock Enable Register
AT91_REG PMC_PCDR; // Peripheral Clock Disable Register
AT91_REG PMC_PCSR; // Peripheral Clock Status Register
AT91_REG Reserved1[1]; //
AT91_REG PMC_MOR; // Main Oscillator Register
AT91_REG PMC_MCFR; // Main Clock Frequency Register
AT91_REG Reserved2[1]; //
AT91_REG PMC_PLLR; // PLL Register
AT91_REG PMC_MCKR; // Master Clock Register
AT91_REG Reserved3[3]; //
AT91_REG PMC_PCKR[3]; // Programmable Clock Register
AT91_REG Reserved4[5]; //
AT91_REG PMC_IER; // Interrupt Enable Register
AT91_REG PMC_IDR; // Interrupt Disable Register
AT91_REG PMC_SR; // Status Register
AT91_REG PMC_IMR; // Interrupt Mask Register
} AT91S_PMC, *AT91PS_PMC;
#else
#define PMC_SCER (AT91_CAST(AT91_REG *) 0x00000000) // (PMC_SCER) System Clock Enable Register
#define PMC_SCDR (AT91_CAST(AT91_REG *) 0x00000004) // (PMC_SCDR) System Clock Disable Register
#define PMC_SCSR (AT91_CAST(AT91_REG *) 0x00000008) // (PMC_SCSR) System Clock Status Register
#define PMC_PCER (AT91_CAST(AT91_REG *) 0x00000010) // (PMC_PCER) Peripheral Clock Enable Register
#define PMC_PCDR (AT91_CAST(AT91_REG *) 0x00000014) // (PMC_PCDR) Peripheral Clock Disable Register
#define PMC_PCSR (AT91_CAST(AT91_REG *) 0x00000018) // (PMC_PCSR) Peripheral Clock Status Register
#define PMC_MCKR (AT91_CAST(AT91_REG *) 0x00000030) // (PMC_MCKR) Master Clock Register
#define PMC_PCKR (AT91_CAST(AT91_REG *) 0x00000040) // (PMC_PCKR) Programmable Clock Register
#define PMC_IER (AT91_CAST(AT91_REG *) 0x00000060) // (PMC_IER) Interrupt Enable Register
#define PMC_IDR (AT91_CAST(AT91_REG *) 0x00000064) // (PMC_IDR) Interrupt Disable Register
#define PMC_SR (AT91_CAST(AT91_REG *) 0x00000068) // (PMC_SR) Status Register
#define PMC_IMR (AT91_CAST(AT91_REG *) 0x0000006C) // (PMC_IMR) Interrupt Mask Register
#endif
// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------
#define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock
#define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device Port Clock
#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output
#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output
#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output
// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register --------
// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register --------
// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register --------
// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register --------
// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register --------
// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------
#define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection
#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected
#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected
#define AT91C_PMC_CSS_PLL_CLK (0x3) // (PMC) Clock from PLL is selected
#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler
#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock
#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2
#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4
#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8
#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16
#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32
#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64
// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------
// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register --------
#define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask
#define AT91C_PMC_LOCK (0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask
#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------
// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------
// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Reset Controller Interface
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_RSTC {
AT91_REG RSTC_RCR; // Reset Control Register
AT91_REG RSTC_RSR; // Reset Status Register
AT91_REG RSTC_RMR; // Reset Mode Register
} AT91S_RSTC, *AT91PS_RSTC;
#else
#define RSTC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (RSTC_RCR) Reset Control Register
#define RSTC_RSR (AT91_CAST(AT91_REG *) 0x00000004) // (RSTC_RSR) Reset Status Register
#define RSTC_RMR (AT91_CAST(AT91_REG *) 0x00000008) // (RSTC_RMR) Reset Mode Register
#endif
// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register --------
#define AT91C_RSTC_PROCRST (0x1 << 0) // (RSTC) Processor Reset
#define AT91C_RSTC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset
#define AT91C_RSTC_EXTRST (0x1 << 3) // (RSTC) External Reset
#define AT91C_RSTC_KEY (0xFF << 24) // (RSTC) Password
// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register --------
#define AT91C_RSTC_URSTS (0x1 << 0) // (RSTC) User Reset Status
#define AT91C_RSTC_BODSTS (0x1 << 1) // (RSTC) Brownout Detection Status
#define AT91C_RSTC_RSTTYP (0x7 << 8) // (RSTC) Reset Type
#define AT91C_RSTC_RSTTYP_POWERUP (0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising.
#define AT91C_RSTC_RSTTYP_WAKEUP (0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising.
#define AT91C_RSTC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
#define AT91C_RSTC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software.
#define AT91C_RSTC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low.
#define AT91C_RSTC_RSTTYP_BROWNOUT (0x5 << 8) // (RSTC) Brownout Reset occured.
#define AT91C_RSTC_NRSTL (0x1 << 16) // (RSTC) NRST pin level
#define AT91C_RSTC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress.
// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register --------
#define AT91C_RSTC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable
#define AT91C_RSTC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable
#define AT91C_RSTC_ERSTL (0xF << 8) // (RSTC) User Reset Length
#define AT91C_RSTC_BODIEN (0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_RTTC {
AT91_REG RTTC_RTMR; // Real-time Mode Register
AT91_REG RTTC_RTAR; // Real-time Alarm Register
AT91_REG RTTC_RTVR; // Real-time Value Register
AT91_REG RTTC_RTSR; // Real-time Status Register
} AT91S_RTTC, *AT91PS_RTTC;
#else
#define RTTC_RTMR (AT91_CAST(AT91_REG *) 0x00000000) // (RTTC_RTMR) Real-time Mode Register
#define RTTC_RTAR (AT91_CAST(AT91_REG *) 0x00000004) // (RTTC_RTAR) Real-time Alarm Register
#define RTTC_RTVR (AT91_CAST(AT91_REG *) 0x00000008) // (RTTC_RTVR) Real-time Value Register
#define RTTC_RTSR (AT91_CAST(AT91_REG *) 0x0000000C) // (RTTC_RTSR) Real-time Status Register
#endif
// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register --------
#define AT91C_RTTC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value
#define AT91C_RTTC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable
#define AT91C_RTTC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
#define AT91C_RTTC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart
// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register --------
#define AT91C_RTTC_ALMV (0x0 << 0) // (RTTC) Alarm Value
// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register --------
#define AT91C_RTTC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value
// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register --------
#define AT91C_RTTC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status
#define AT91C_RTTC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_PITC {
AT91_REG PITC_PIMR; // Period Interval Mode Register
AT91_REG PITC_PISR; // Period Interval Status Register
AT91_REG PITC_PIVR; // Period Interval Value Register
AT91_REG PITC_PIIR; // Period Interval Image Register
} AT91S_PITC, *AT91PS_PITC;
#else
#define PITC_PIMR (AT91_CAST(AT91_REG *) 0x00000000) // (PITC_PIMR) Period Interval Mode Register
#define PITC_PISR (AT91_CAST(AT91_REG *) 0x00000004) // (PITC_PISR) Period Interval Status Register
#define PITC_PIVR (AT91_CAST(AT91_REG *) 0x00000008) // (PITC_PIVR) Period Interval Value Register
#define PITC_PIIR (AT91_CAST(AT91_REG *) 0x0000000C) // (PITC_PIIR) Period Interval Image Register
#endif
// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register --------
#define AT91C_PITC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value
#define AT91C_PITC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled
#define AT91C_PITC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register --------
#define AT91C_PITC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status
// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register --------
#define AT91C_PITC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value
#define AT91C_PITC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter
// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_WDTC {
AT91_REG WDTC_WDCR; // Watchdog Control Register
AT91_REG WDTC_WDMR; // Watchdog Mode Register
AT91_REG WDTC_WDSR; // Watchdog Status Register
} AT91S_WDTC, *AT91PS_WDTC;
#else
#define WDTC_WDCR (AT91_CAST(AT91_REG *) 0x00000000) // (WDTC_WDCR) Watchdog Control Register
#define WDTC_WDMR (AT91_CAST(AT91_REG *) 0x00000004) // (WDTC_WDMR) Watchdog Mode Register
#define WDTC_WDSR (AT91_CAST(AT91_REG *) 0x00000008) // (WDTC_WDSR) Watchdog Status Register
#endif
// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register --------
#define AT91C_WDTC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart
#define AT91C_WDTC_KEY (0xFF << 24) // (WDTC) Watchdog KEY Password
// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register --------
#define AT91C_WDTC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart
#define AT91C_WDTC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
#define AT91C_WDTC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable
#define AT91C_WDTC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart
#define AT91C_WDTC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable
#define AT91C_WDTC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value
#define AT91C_WDTC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt
#define AT91C_WDTC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt
// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register --------
#define AT91C_WDTC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow
#define AT91C_WDTC_WDERR (0x1 << 1) // (WDTC) Watchdog Error
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_VREG {
AT91_REG VREG_MR; // Voltage Regulator Mode Register
} AT91S_VREG, *AT91PS_VREG;
#else
#define VREG_MR (AT91_CAST(AT91_REG *) 0x00000000) // (VREG_MR) Voltage Regulator Mode Register
#endif
// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register --------
#define AT91C_VREG_PSTDBY (0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Embedded Flash Controller Interface
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_EFC {
AT91_REG EFC_FMR; // MC Flash Mode Register
AT91_REG EFC_FCR; // MC Flash Command Register
AT91_REG EFC_FSR; // MC Flash Status Register
AT91_REG EFC_VR; // MC Flash Version Register
} AT91S_EFC, *AT91PS_EFC;
#else
#define MC_FMR (AT91_CAST(AT91_REG *) 0x00000000) // (MC_FMR) MC Flash Mode Register
#define MC_FCR (AT91_CAST(AT91_REG *) 0x00000004) // (MC_FCR) MC Flash Command Register
#define MC_FSR (AT91_CAST(AT91_REG *) 0x00000008) // (MC_FSR) MC Flash Status Register
#define MC_VR (AT91_CAST(AT91_REG *) 0x0000000C) // (MC_VR) MC Flash Version Register
#endif
// -------- MC_FMR : (EFC Offset: 0x0) MC Flash Mode Register --------
#define AT91C_MC_FRDY (0x1 << 0) // (EFC) Flash Ready
#define AT91C_MC_LOCKE (0x1 << 2) // (EFC) Lock Error
#define AT91C_MC_PROGE (0x1 << 3) // (EFC) Programming Error
#define AT91C_MC_NEBP (0x1 << 7) // (EFC) No Erase Before Programming
#define AT91C_MC_FWS (0x3 << 8) // (EFC) Flash Wait State
#define AT91C_MC_FWS_0FWS (0x0 << 8) // (EFC) 1 cycle for Read, 2 for Write operations
#define AT91C_MC_FWS_1FWS (0x1 << 8) // (EFC) 2 cycles for Read, 3 for Write operations
#define AT91C_MC_FWS_2FWS (0x2 << 8) // (EFC) 3 cycles for Read, 4 for Write operations
#define AT91C_MC_FWS_3FWS (0x3 << 8) // (EFC) 4 cycles for Read, 4 for Write operations
#define AT91C_MC_FMCN (0xFF << 16) // (EFC) Flash Microsecond Cycle Number
// -------- MC_FCR : (EFC Offset: 0x4) MC Flash Command Register --------
#define AT91C_MC_FCMD (0xF << 0) // (EFC) Flash Command
#define AT91C_MC_FCMD_START_PROG (0x1) // (EFC) Starts the programming of th epage specified by PAGEN.
#define AT91C_MC_FCMD_LOCK (0x2) // (EFC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
#define AT91C_MC_FCMD_PROG_AND_LOCK (0x3) // (EFC) The lock sequence automatically happens after the programming sequence is completed.
#define AT91C_MC_FCMD_UNLOCK (0x4) // (EFC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
#define AT91C_MC_FCMD_ERASE_ALL (0x8) // (EFC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
#define AT91C_MC_FCMD_SET_GP_NVM (0xB) // (EFC) Set General Purpose NVM bits.
#define AT91C_MC_FCMD_CLR_GP_NVM (0xD) // (EFC) Clear General Purpose NVM bits.
#define AT91C_MC_FCMD_SET_SECURITY (0xF) // (EFC) Set Security Bit.
#define AT91C_MC_PAGEN (0x3FF << 8) // (EFC) Page Number
#define AT91C_MC_KEY (0xFF << 24) // (EFC) Writing Protect Key
// -------- MC_FSR : (EFC Offset: 0x8) MC Flash Command Register --------
#define AT91C_MC_SECURITY (0x1 << 4) // (EFC) Security Bit Status
#define AT91C_MC_GPNVM0 (0x1 << 8) // (EFC) Sector 0 Lock Status
#define AT91C_MC_GPNVM1 (0x1 << 9) // (EFC) Sector 1 Lock Status
#define AT91C_MC_GPNVM2 (0x1 << 10) // (EFC) Sector 2 Lock Status
#define AT91C_MC_GPNVM3 (0x1 << 11) // (EFC) Sector 3 Lock Status
#define AT91C_MC_GPNVM4 (0x1 << 12) // (EFC) Sector 4 Lock Status
#define AT91C_MC_GPNVM5 (0x1 << 13) // (EFC) Sector 5 Lock Status
#define AT91C_MC_GPNVM6 (0x1 << 14) // (EFC) Sector 6 Lock Status
#define AT91C_MC_GPNVM7 (0x1 << 15) // (EFC) Sector 7 Lock Status
#define AT91C_MC_LOCKS0 (0x1 << 16) // (EFC) Sector 0 Lock Status
#define AT91C_MC_LOCKS1 (0x1 << 17) // (EFC) Sector 1 Lock Status
#define AT91C_MC_LOCKS2 (0x1 << 18) // (EFC) Sector 2 Lock Status
#define AT91C_MC_LOCKS3 (0x1 << 19) // (EFC) Sector 3 Lock Status
#define AT91C_MC_LOCKS4 (0x1 << 20) // (EFC) Sector 4 Lock Status
#define AT91C_MC_LOCKS5 (0x1 << 21) // (EFC) Sector 5 Lock Status
#define AT91C_MC_LOCKS6 (0x1 << 22) // (EFC) Sector 6 Lock Status
#define AT91C_MC_LOCKS7 (0x1 << 23) // (EFC) Sector 7 Lock Status
#define AT91C_MC_LOCKS8 (0x1 << 24) // (EFC) Sector 8 Lock Status
#define AT91C_MC_LOCKS9 (0x1 << 25) // (EFC) Sector 9 Lock Status
#define AT91C_MC_LOCKS10 (0x1 << 26) // (EFC) Sector 10 Lock Status
#define AT91C_MC_LOCKS11 (0x1 << 27) // (EFC) Sector 11 Lock Status
#define AT91C_MC_LOCKS12 (0x1 << 28) // (EFC) Sector 12 Lock Status
#define AT91C_MC_LOCKS13 (0x1 << 29) // (EFC) Sector 13 Lock Status
#define AT91C_MC_LOCKS14 (0x1 << 30) // (EFC) Sector 14 Lock Status
#define AT91C_MC_LOCKS15 (0x1 << 31) // (EFC) Sector 15 Lock Status
// -------- EFC_VR : (EFC Offset: 0xc) EFC version register --------
#define AT91C_EFC_VERSION (0xFFF << 0) // (EFC) EFC version number
#define AT91C_EFC_MFN (0x7 << 16) // (EFC) EFC MFN
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Memory Controller Interface
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_MC {
AT91_REG MC_RCR; // MC Remap Control Register
AT91_REG MC_ASR; // MC Abort Status Register
AT91_REG MC_AASR; // MC Abort Address Status Register
AT91_REG Reserved0[1]; //
AT91_REG MC_PUIA[16]; // MC Protection Unit Area
AT91_REG MC_PUP; // MC Protection Unit Peripherals
AT91_REG MC_PUER; // MC Protection Unit Enable Register
AT91_REG Reserved1[2]; //
AT91_REG MC0_FMR; // MC Flash Mode Register
AT91_REG MC0_FCR; // MC Flash Command Register
AT91_REG MC0_FSR; // MC Flash Status Register
AT91_REG MC0_VR; // MC Flash Version Register
AT91_REG MC1_FMR; // MC Flash Mode Register
AT91_REG MC1_FCR; // MC Flash Command Register
AT91_REG MC1_FSR; // MC Flash Status Register
AT91_REG MC1_VR; // MC Flash Version Register
} AT91S_MC, *AT91PS_MC;
#else
#define MC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (MC_RCR) MC Remap Control Register
#define MC_ASR (AT91_CAST(AT91_REG *) 0x00000004) // (MC_ASR) MC Abort Status Register
#define MC_AASR (AT91_CAST(AT91_REG *) 0x00000008) // (MC_AASR) MC Abort Address Status Register
#define MC_PUIA (AT91_CAST(AT91_REG *) 0x00000010) // (MC_PUIA) MC Protection Unit Area
#define MC_PUP (AT91_CAST(AT91_REG *) 0x00000050) // (MC_PUP) MC Protection Unit Peripherals
#define MC_PUER (AT91_CAST(AT91_REG *) 0x00000054) // (MC_PUER) MC Protection Unit Enable Register
#endif
// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register --------
#define AT91C_MC_RCB (0x1 << 0) // (MC) Remap Command Bit
// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register --------
#define AT91C_MC_UNDADD (0x1 << 0) // (MC) Undefined Addess Abort Status
#define AT91C_MC_MISADD (0x1 << 1) // (MC) Misaligned Addess Abort Status
#define AT91C_MC_MPU (0x1 << 2) // (MC) Memory protection Unit Abort Status
#define AT91C_MC_ABTSZ (0x3 << 8) // (MC) Abort Size Status
#define AT91C_MC_ABTSZ_BYTE (0x0 << 8) // (MC) Byte
#define AT91C_MC_ABTSZ_HWORD (0x1 << 8) // (MC) Half-word
#define AT91C_MC_ABTSZ_WORD (0x2 << 8) // (MC) Word
#define AT91C_MC_ABTTYP (0x3 << 10) // (MC) Abort Type Status
#define AT91C_MC_ABTTYP_DATAR (0x0 << 10) // (MC) Data Read
#define AT91C_MC_ABTTYP_DATAW (0x1 << 10) // (MC) Data Write
#define AT91C_MC_ABTTYP_FETCH (0x2 << 10) // (MC) Code Fetch
#define AT91C_MC_MST0 (0x1 << 16) // (MC) Master 0 Abort Source
#define AT91C_MC_MST1 (0x1 << 17) // (MC) Master 1 Abort Source
#define AT91C_MC_SVMST0 (0x1 << 24) // (MC) Saved Master 0 Abort Source
#define AT91C_MC_SVMST1 (0x1 << 25) // (MC) Saved Master 1 Abort Source
// -------- MC_PUIA : (MC Offset: 0x10) MC Protection Unit Area --------
#define AT91C_MC_PROT (0x3 << 0) // (MC) Protection
#define AT91C_MC_PROT_PNAUNA (0x0) // (MC) Privilege: No Access, User: No Access
#define AT91C_MC_PROT_PRWUNA (0x1) // (MC) Privilege: Read/Write, User: No Access
#define AT91C_MC_PROT_PRWURO (0x2) // (MC) Privilege: Read/Write, User: Read Only
#define AT91C_MC_PROT_PRWURW (0x3) // (MC) Privilege: Read/Write, User: Read/Write
#define AT91C_MC_SIZE (0xF << 4) // (MC) Internal Area Size
#define AT91C_MC_SIZE_1KB (0x0 << 4) // (MC) Area size 1KByte
#define AT91C_MC_SIZE_2KB (0x1 << 4) // (MC) Area size 2KByte
#define AT91C_MC_SIZE_4KB (0x2 << 4) // (MC) Area size 4KByte
#define AT91C_MC_SIZE_8KB (0x3 << 4) // (MC) Area size 8KByte
#define AT91C_MC_SIZE_16KB (0x4 << 4) // (MC) Area size 16KByte
#define AT91C_MC_SIZE_32KB (0x5 << 4) // (MC) Area size 32KByte
#define AT91C_MC_SIZE_64KB (0x6 << 4) // (MC) Area size 64KByte
#define AT91C_MC_SIZE_128KB (0x7 << 4) // (MC) Area size 128KByte
#define AT91C_MC_SIZE_256KB (0x8 << 4) // (MC) Area size 256KByte
#define AT91C_MC_SIZE_512KB (0x9 << 4) // (MC) Area size 512KByte
#define AT91C_MC_SIZE_1MB (0xA << 4) // (MC) Area size 1MByte
#define AT91C_MC_SIZE_2MB (0xB << 4) // (MC) Area size 2MByte
#define AT91C_MC_SIZE_4MB (0xC << 4) // (MC) Area size 4MByte
#define AT91C_MC_SIZE_8MB (0xD << 4) // (MC) Area size 8MByte
#define AT91C_MC_SIZE_16MB (0xE << 4) // (MC) Area size 16MByte
#define AT91C_MC_SIZE_64MB (0xF << 4) // (MC) Area size 64MByte
#define AT91C_MC_BA (0x3FFFF << 10) // (MC) Internal Area Base Address
// -------- MC_PUP : (MC Offset: 0x50) MC Protection Unit Peripheral --------
// -------- MC_PUER : (MC Offset: 0x54) MC Protection Unit Area --------
#define AT91C_MC_PUEB (0x1 << 0) // (MC) Protection Unit enable Bit
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Serial Parallel Interface
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_SPI {
AT91_REG SPI_CR; // Control Register
AT91_REG SPI_MR; // Mode Register
AT91_REG SPI_RDR; // Receive Data Register
AT91_REG SPI_TDR; // Transmit Data Register
AT91_REG SPI_SR; // Status Register
AT91_REG SPI_IER; // Interrupt Enable Register
AT91_REG SPI_IDR; // Interrupt Disable Register
AT91_REG SPI_IMR; // Interrupt Mask Register
AT91_REG Reserved0[4]; //
AT91_REG SPI_CSR[4]; // Chip Select Register
AT91_REG Reserved1[48]; //
AT91_REG SPI_RPR; // Receive Pointer Register
AT91_REG SPI_RCR; // Receive Counter Register
AT91_REG SPI_TPR; // Transmit Pointer Register
AT91_REG SPI_TCR; // Transmit Counter Register
AT91_REG SPI_RNPR; // Receive Next Pointer Register
AT91_REG SPI_RNCR; // Receive Next Counter Register
AT91_REG SPI_TNPR; // Transmit Next Pointer Register
AT91_REG SPI_TNCR; // Transmit Next Counter Register
AT91_REG SPI_PTCR; // PDC Transfer Control Register
AT91_REG SPI_PTSR; // PDC Transfer Status Register
} AT91S_SPI, *AT91PS_SPI;
#else
#define SPI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SPI_CR) Control Register
#define SPI_MR (AT91_CAST(AT91_REG *) 0x00000004) // (SPI_MR) Mode Register
#define SPI_RDR (AT91_CAST(AT91_REG *) 0x00000008) // (SPI_RDR) Receive Data Register
#define SPI_TDR (AT91_CAST(AT91_REG *) 0x0000000C) // (SPI_TDR) Transmit Data Register
#define SPI_SR (AT91_CAST(AT91_REG *) 0x00000010) // (SPI_SR) Status Register
#define SPI_IER (AT91_CAST(AT91_REG *) 0x00000014) // (SPI_IER) Interrupt Enable Register
#define SPI_IDR (AT91_CAST(AT91_REG *) 0x00000018) // (SPI_IDR) Interrupt Disable Register
#define SPI_IMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SPI_IMR) Interrupt Mask Register
#define SPI_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (SPI_CSR) Chip Select Register
#endif
// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register --------
#define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable
#define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable
#define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset
#define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer
// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register --------
#define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode
#define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select
#define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select
#define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select
#define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode
#define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection
#define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection
#define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection
#define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select
#define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects
// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register --------
#define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data
#define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status
// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register --------
#define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data
#define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status
// -------- SPI_SR : (SPI Offset: 0x10) Status Register --------
#define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full
#define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty
#define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error
#define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status
#define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer
#define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer
#define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt
#define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt
#define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt
#define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt
#define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status
// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register --------
// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register --------
// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register --------
// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register --------
#define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity
#define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase
#define AT91C_SPI_CSAAT (0x1 << 3) // (SPI) Chip Select Active After Transfer
#define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer
#define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer
#define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer
#define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer
#define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer
#define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer
#define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer
#define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer
#define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer
#define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer
#define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate
#define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Delay Before SPCK
#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Analog to Digital Convertor
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_ADC {
AT91_REG ADC_CR; // ADC Control Register
AT91_REG ADC_MR; // ADC Mode Register
AT91_REG Reserved0[2]; //
AT91_REG ADC_CHER; // ADC Channel Enable Register
AT91_REG ADC_CHDR; // ADC Channel Disable Register
AT91_REG ADC_CHSR; // ADC Channel Status Register
AT91_REG ADC_SR; // ADC Status Register
AT91_REG ADC_LCDR; // ADC Last Converted Data Register
AT91_REG ADC_IER; // ADC Interrupt Enable Register
AT91_REG ADC_IDR; // ADC Interrupt Disable Register
AT91_REG ADC_IMR; // ADC Interrupt Mask Register
AT91_REG ADC_CDR[8]; // ADC Channel Data Register
AT91_REG Reserved1[44]; //
AT91_REG ADC_RPR; // Receive Pointer Register
AT91_REG ADC_RCR; // Receive Counter Register
AT91_REG ADC_TPR; // Transmit Pointer Register
AT91_REG ADC_TCR; // Transmit Counter Register
AT91_REG ADC_RNPR; // Receive Next Pointer Register
AT91_REG ADC_RNCR; // Receive Next Counter Register
AT91_REG ADC_TNPR; // Transmit Next Pointer Register
AT91_REG ADC_TNCR; // Transmit Next Counter Register
AT91_REG ADC_PTCR; // PDC Transfer Control Register
AT91_REG ADC_PTSR; // PDC Transfer Status Register
} AT91S_ADC, *AT91PS_ADC;
#else
#define ADC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (ADC_CR) ADC Control Register
#define ADC_MR (AT91_CAST(AT91_REG *) 0x00000004) // (ADC_MR) ADC Mode Register
#define ADC_CHER (AT91_CAST(AT91_REG *) 0x00000010) // (ADC_CHER) ADC Channel Enable Register
#define ADC_CHDR (AT91_CAST(AT91_REG *) 0x00000014) // (ADC_CHDR) ADC Channel Disable Register
#define ADC_CHSR (AT91_CAST(AT91_REG *) 0x00000018) // (ADC_CHSR) ADC Channel Status Register
#define ADC_SR (AT91_CAST(AT91_REG *) 0x0000001C) // (ADC_SR) ADC Status Register
#define ADC_LCDR (AT91_CAST(AT91_REG *) 0x00000020) // (ADC_LCDR) ADC Last Converted Data Register
#define ADC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (ADC_IER) ADC Interrupt Enable Register
#define ADC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (ADC_IDR) ADC Interrupt Disable Register
#define ADC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (ADC_IMR) ADC Interrupt Mask Register
#define ADC_CDR0 (AT91_CAST(AT91_REG *) 0x00000030) // (ADC_CDR0) ADC Channel Data Register 0
#define ADC_CDR1 (AT91_CAST(AT91_REG *) 0x00000034) // (ADC_CDR1) ADC Channel Data Register 1
#define ADC_CDR2 (AT91_CAST(AT91_REG *) 0x00000038) // (ADC_CDR2) ADC Channel Data Register 2
#define ADC_CDR3 (AT91_CAST(AT91_REG *) 0x0000003C) // (ADC_CDR3) ADC Channel Data Register 3