Single-clock Synchronous FIFOs designed in Verilog/System Verilog. The source code includes generic FIFO implementations and FPGA-friendly implementations targetting Block/LUT RAMs.
- Generic
- BlockRAM_based
- fifo_bram - suitable for any depth
- fifo_2n_lram - optimized for 2^N depth
- LUTRAM_based
- fifo_lram - suitable for any depth
- fifo_2n_lram - optimized for 2^N depth
All codes are fully synthesizable and tested. All are open-source codes, free to use, modify and distribute without any conflicts of interest with the original developer.
Mitu Raj, iammituraj@gmail.com