diff --git a/bitstreams/tc_opt_4.bit b/bitstreams/tc_opt_4.bit new file mode 100644 index 0000000..e0a9e65 Binary files /dev/null and b/bitstreams/tc_opt_4.bit differ diff --git a/bitstreams/tc_opt_4.tcl b/bitstreams/tc_opt_4.tcl new file mode 100644 index 0000000..938df78 --- /dev/null +++ b/bitstreams/tc_opt_4.tcl @@ -0,0 +1,1046 @@ + +################################################################ +# This is a generated script based on design: hw_platform +# +# Though there are limitations about the generated script, +# the main purpose of this utility is to make learning +# IP Integrator Tcl commands easier. +################################################################ + +namespace eval _tcl { +proc get_script_folder {} { + set script_path [file normalize [info script]] + set script_folder [file dirname $script_path] + return $script_folder +} +} +variable script_folder +set script_folder [_tcl::get_script_folder] + +################################################################ +# Check if script is running in correct Vivado version. +################################################################ +set scripts_vivado_version 2017.2 +set current_vivado_version [version -short] + +if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { + puts "" + catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} + + return 1 +} + +################################################################ +# START +################################################################ + +# To test this script, run the following commands from Vivado Tcl console: +# source hw_platform_script.tcl + +# If there is no project opened, this script will create a +# project, but make sure you do not have an existing project +# <./myproj/project_1.xpr> in the current working folder. + +set list_projs [get_projects -quiet] +if { $list_projs eq "" } { + create_project project_1 myproj -part xc7z020clg400-1 + set_property BOARD_PART www.digilentinc.com:pynq-z1:part0:1.0 [current_project] +} + + +# CHANGE DESIGN NAME HERE +set design_name hw_platform + +# If you do not already have an existing IP Integrator design open, +# you can create a design using the following command: +# create_bd_design $design_name + +# Creating design if needed +set errMsg "" +set nRet 0 + +set cur_design [current_bd_design -quiet] +set list_cells [get_bd_cells -quiet] + +if { ${design_name} eq "" } { + # USE CASES: + # 1) Design_name not set + + set errMsg "Please set the variable to a non-empty value." + set nRet 1 + +} elseif { ${cur_design} ne "" && ${list_cells} eq "" } { + # USE CASES: + # 2): Current design opened AND is empty AND names same. + # 3): Current design opened AND is empty AND names diff; design_name NOT in project. + # 4): Current design opened AND is empty AND names diff; design_name exists in project. + + if { $cur_design ne $design_name } { + common::send_msg_id "BD_TCL-001" "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." + set design_name [get_property NAME $cur_design] + } + common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..." + +} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { + # USE CASES: + # 5) Current design opened AND has components AND same names. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 1 +} elseif { [get_files -quiet ${design_name}.bd] ne "" } { + # USE CASES: + # 6) Current opened design, has components, but diff names, design_name exists in project. + # 7) No opened design, design_name exists in project. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 2 + +} else { + # USE CASES: + # 8) No opened design, design_name not in project. + # 9) Current opened design, has components, but diff names, design_name not in project. + + common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..." + + create_bd_design $design_name + + common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design." + current_bd_design $design_name + +} + +common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable is equal to \"$design_name\"." + +if { $nRet != 0 } { + catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg} + return $nRet +} + +################################################################## +# DESIGN PROCs +################################################################## + + + +# Procedure to create entire design; Provide argument to make +# procedure reusable. If parentCell is "", will use root. +proc create_root_design { parentCell } { + + variable script_folder + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + + # Create interface ports + set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ] + set FIXED_IO [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO ] + + # Create ports + + # Create instance: axi_smc, and set properties + set axi_smc [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_smc ] + set_property -dict [ list \ +CONFIG.NUM_SI {4} \ + ] $axi_smc + + # Create instance: axi_smc_1, and set properties + set axi_smc_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_smc_1 ] + set_property -dict [ list \ +CONFIG.NUM_SI {4} \ + ] $axi_smc_1 + + # Create instance: axi_smc_2, and set properties + set axi_smc_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_smc_2 ] + set_property -dict [ list \ +CONFIG.NUM_SI {4} \ + ] $axi_smc_2 + + # Create instance: axi_smc_3, and set properties + set axi_smc_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_smc_3 ] + set_property -dict [ list \ +CONFIG.NUM_SI {4} \ + ] $axi_smc_3 + + # Create instance: processing_system7_0, and set properties + set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ] + set_property -dict [ list \ +CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {650.000000} \ +CONFIG.PCW_ACT_CAN0_PERIPHERAL_FREQMHZ {23.8095} \ +CONFIG.PCW_ACT_CAN1_PERIPHERAL_FREQMHZ {23.8095} \ +CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ {10.000000} \ +CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.096154} \ +CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {125.000000} \ +CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ {10.000000} \ +CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {100.000000} \ +CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {10.000000} \ +CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ {10.000000} \ +CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ {10.000000} \ +CONFIG.PCW_ACT_I2C_PERIPHERAL_FREQMHZ {50} \ +CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ {200.000000} \ +CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {200.000000} \ +CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {50.000000} \ +CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ {10.000000} \ +CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ {10.000000} \ +CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ {200.000000} \ +CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ {108.333336} \ +CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ {108.333336} \ +CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ {108.333336} \ +CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ {108.333336} \ +CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ {108.333336} \ +CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ {108.333336} \ +CONFIG.PCW_ACT_TTC_PERIPHERAL_FREQMHZ {50} \ +CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {100.000000} \ +CONFIG.PCW_ACT_USB0_PERIPHERAL_FREQMHZ {60} \ +CONFIG.PCW_ACT_USB1_PERIPHERAL_FREQMHZ {60} \ +CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ {108.333336} \ +CONFIG.PCW_APU_CLK_RATIO_ENABLE {6:2:1} \ +CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {650} \ +CONFIG.PCW_ARMPLL_CTRL_FBDIV {26} \ +CONFIG.PCW_CAN0_BASEADDR {0xE0008000} \ +CONFIG.PCW_CAN0_HIGHADDR {0xE0008FFF} \ +CONFIG.PCW_CAN0_PERIPHERAL_CLKSRC {External} \ +CONFIG.PCW_CAN0_PERIPHERAL_FREQMHZ {-1} \ +CONFIG.PCW_CAN1_BASEADDR {0xE0009000} \ +CONFIG.PCW_CAN1_HIGHADDR {0xE0009FFF} \ +CONFIG.PCW_CAN1_PERIPHERAL_CLKSRC {External} \ +CONFIG.PCW_CAN1_PERIPHERAL_FREQMHZ {-1} \ +CONFIG.PCW_CAN_PERIPHERAL_CLKSRC {IO PLL} \ +CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0 {1} \ +CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1 {1} \ +CONFIG.PCW_CAN_PERIPHERAL_FREQMHZ {100} \ +CONFIG.PCW_CAN_PERIPHERAL_VALID {0} \ +CONFIG.PCW_CLK0_FREQ {100000000} \ +CONFIG.PCW_CLK1_FREQ {10000000} \ +CONFIG.PCW_CLK2_FREQ {10000000} \ +CONFIG.PCW_CLK3_FREQ {10000000} \ +CONFIG.PCW_CORE0_FIQ_INTR {0} \ +CONFIG.PCW_CORE0_IRQ_INTR {0} \ +CONFIG.PCW_CORE1_FIQ_INTR {0} \ +CONFIG.PCW_CORE1_IRQ_INTR {0} \ +CONFIG.PCW_CPU_CPU_6X4X_MAX_RANGE {667} \ +CONFIG.PCW_CPU_CPU_PLL_FREQMHZ {1300.000} \ +CONFIG.PCW_CPU_PERIPHERAL_CLKSRC {ARM PLL} \ +CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0 {2} \ +CONFIG.PCW_CRYSTAL_PERIPHERAL_FREQMHZ {50} \ +CONFIG.PCW_DCI_PERIPHERAL_CLKSRC {DDR PLL} \ +CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0 {52} \ +CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1 {2} \ +CONFIG.PCW_DCI_PERIPHERAL_FREQMHZ {10.159} \ +CONFIG.PCW_DDRPLL_CTRL_FBDIV {21} \ +CONFIG.PCW_DDR_DDR_PLL_FREQMHZ {1050.000} \ +CONFIG.PCW_DDR_HPRLPR_QUEUE_PARTITION {HPR(0)/LPR(32)} \ +CONFIG.PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL {15} \ +CONFIG.PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL {2} \ +CONFIG.PCW_DDR_PERIPHERAL_CLKSRC {DDR PLL} \ +CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0 {2} \ +CONFIG.PCW_DDR_PORT0_HPR_ENABLE {0} \ +CONFIG.PCW_DDR_PORT1_HPR_ENABLE {0} \ +CONFIG.PCW_DDR_PORT2_HPR_ENABLE {0} \ +CONFIG.PCW_DDR_PORT3_HPR_ENABLE {0} \ +CONFIG.PCW_DDR_RAM_BASEADDR {0x00100000} \ +CONFIG.PCW_DDR_RAM_HIGHADDR {0x1FFFFFFF} \ +CONFIG.PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL {2} \ +CONFIG.PCW_DM_WIDTH {4} \ +CONFIG.PCW_DQS_WIDTH {4} \ +CONFIG.PCW_DQ_WIDTH {32} \ +CONFIG.PCW_ENET0_BASEADDR {0xE000B000} \ +CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27} \ +CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1} \ +CONFIG.PCW_ENET0_GRP_MDIO_IO {MIO 52 .. 53} \ +CONFIG.PCW_ENET0_HIGHADDR {0xE000BFFF} \ +CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC {IO PLL} \ +CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0 {8} \ +CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1 {1} \ +CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1} \ +CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ {1000 Mbps} \ +CONFIG.PCW_ENET0_RESET_ENABLE {1} \ +CONFIG.PCW_ENET0_RESET_IO {MIO 9} \ +CONFIG.PCW_ENET1_BASEADDR {0xE000C000} \ +CONFIG.PCW_ENET1_GRP_MDIO_ENABLE {0} \ +CONFIG.PCW_ENET1_HIGHADDR {0xE000CFFF} \ +CONFIG.PCW_ENET1_PERIPHERAL_CLKSRC {IO PLL} \ +CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0 {1} \ +CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1 {1} \ +CONFIG.PCW_ENET1_PERIPHERAL_ENABLE {0} \ +CONFIG.PCW_ENET1_PERIPHERAL_FREQMHZ {1000 Mbps} \ +CONFIG.PCW_ENET1_RESET_ENABLE {0} \ +CONFIG.PCW_ENET_RESET_ENABLE {1} \ +CONFIG.PCW_ENET_RESET_POLARITY {Active Low} \ +CONFIG.PCW_ENET_RESET_SELECT {Share reset pin} \ +CONFIG.PCW_EN_4K_TIMER {0} \ +CONFIG.PCW_EN_CAN0 {0} \ +CONFIG.PCW_EN_CAN1 {0} \ +CONFIG.PCW_EN_CLK0_PORT {1} \ +CONFIG.PCW_EN_CLK1_PORT {0} \ +CONFIG.PCW_EN_CLK2_PORT {0} \ +CONFIG.PCW_EN_CLK3_PORT {0} \ +CONFIG.PCW_EN_CLKTRIG0_PORT {0} \ +CONFIG.PCW_EN_CLKTRIG1_PORT {0} \ +CONFIG.PCW_EN_CLKTRIG2_PORT {0} \ +CONFIG.PCW_EN_CLKTRIG3_PORT {0} \ +CONFIG.PCW_EN_DDR {1} \ +CONFIG.PCW_EN_EMIO_CAN0 {0} \ +CONFIG.PCW_EN_EMIO_CAN1 {0} \ +CONFIG.PCW_EN_EMIO_CD_SDIO0 {0} \ +CONFIG.PCW_EN_EMIO_CD_SDIO1 {0} \ +CONFIG.PCW_EN_EMIO_ENET0 {0} \ +CONFIG.PCW_EN_EMIO_ENET1 {0} \ +CONFIG.PCW_EN_EMIO_GPIO {0} \ +CONFIG.PCW_EN_EMIO_I2C0 {0} \ +CONFIG.PCW_EN_EMIO_I2C1 {0} \ +CONFIG.PCW_EN_EMIO_MODEM_UART0 {0} \ +CONFIG.PCW_EN_EMIO_MODEM_UART1 {0} \ +CONFIG.PCW_EN_EMIO_PJTAG {0} \ +CONFIG.PCW_EN_EMIO_SDIO0 {0} \ +CONFIG.PCW_EN_EMIO_SDIO1 {0} \ +CONFIG.PCW_EN_EMIO_SPI0 {0} \ +CONFIG.PCW_EN_EMIO_SPI1 {0} \ +CONFIG.PCW_EN_EMIO_SRAM_INT {0} \ +CONFIG.PCW_EN_EMIO_TRACE {0} \ +CONFIG.PCW_EN_EMIO_TTC0 {0} \ +CONFIG.PCW_EN_EMIO_TTC1 {0} \ +CONFIG.PCW_EN_EMIO_UART0 {0} \ +CONFIG.PCW_EN_EMIO_UART1 {0} \ +CONFIG.PCW_EN_EMIO_WDT {0} \ +CONFIG.PCW_EN_EMIO_WP_SDIO0 {0} \ +CONFIG.PCW_EN_EMIO_WP_SDIO1 {0} \ +CONFIG.PCW_EN_ENET0 {1} \ +CONFIG.PCW_EN_ENET1 {0} \ +CONFIG.PCW_EN_GPIO {1} \ +CONFIG.PCW_EN_I2C0 {0} \ +CONFIG.PCW_EN_I2C1 {0} \ +CONFIG.PCW_EN_MODEM_UART0 {0} \ +CONFIG.PCW_EN_MODEM_UART1 {0} \ +CONFIG.PCW_EN_PJTAG {0} \ +CONFIG.PCW_EN_PTP_ENET0 {0} \ +CONFIG.PCW_EN_PTP_ENET1 {0} \ +CONFIG.PCW_EN_QSPI {1} \ +CONFIG.PCW_EN_RST0_PORT {1} \ +CONFIG.PCW_EN_RST1_PORT {0} \ +CONFIG.PCW_EN_RST2_PORT {0} \ +CONFIG.PCW_EN_RST3_PORT {0} \ +CONFIG.PCW_EN_SDIO0 {1} \ +CONFIG.PCW_EN_SDIO1 {0} \ +CONFIG.PCW_EN_SMC {0} \ +CONFIG.PCW_EN_SPI0 {0} \ +CONFIG.PCW_EN_SPI1 {0} \ +CONFIG.PCW_EN_TRACE {0} \ +CONFIG.PCW_EN_TTC0 {0} \ +CONFIG.PCW_EN_TTC1 {0} \ +CONFIG.PCW_EN_UART0 {1} \ +CONFIG.PCW_EN_UART1 {0} \ +CONFIG.PCW_EN_USB0 {1} \ +CONFIG.PCW_EN_USB1 {0} \ +CONFIG.PCW_EN_WDT {0} \ +CONFIG.PCW_FCLK0_PERIPHERAL_CLKSRC {IO PLL} \ +CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0 {5} \ +CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1 {2} \ +CONFIG.PCW_FCLK1_PERIPHERAL_CLKSRC {IO PLL} \ +CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0 {1} \ +CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1 {1} \ +CONFIG.PCW_FCLK2_PERIPHERAL_CLKSRC {IO PLL} \ +CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0 {1} \ +CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1 {1} \ +CONFIG.PCW_FCLK3_PERIPHERAL_CLKSRC {IO PLL} \ +CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0 {1} \ +CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1 {1} \ +CONFIG.PCW_FCLK_CLK0_BUF {TRUE} \ +CONFIG.PCW_FCLK_CLK1_BUF {FALSE} \ +CONFIG.PCW_FCLK_CLK2_BUF {FALSE} \ +CONFIG.PCW_FCLK_CLK3_BUF {FALSE} \ +CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100} \ +CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {50} \ +CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {50} \ +CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ {50} \ +CONFIG.PCW_FPGA_FCLK0_ENABLE {1} \ +CONFIG.PCW_FPGA_FCLK1_ENABLE {0} \ +CONFIG.PCW_FPGA_FCLK2_ENABLE {0} \ +CONFIG.PCW_FPGA_FCLK3_ENABLE {0} \ +CONFIG.PCW_GPIO_BASEADDR {0xE000A000} \ +CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {0} \ +CONFIG.PCW_GPIO_EMIO_GPIO_WIDTH {64} \ +CONFIG.PCW_GPIO_HIGHADDR {0xE000AFFF} \ +CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} \ +CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO} \ +CONFIG.PCW_GPIO_PERIPHERAL_ENABLE {0} \ +CONFIG.PCW_I2C0_BASEADDR {0xE0004000} \ +CONFIG.PCW_I2C0_HIGHADDR {0xE0004FFF} \ +CONFIG.PCW_I2C1_BASEADDR {0xE0005000} \ +CONFIG.PCW_I2C1_HIGHADDR {0xE0005FFF} \ +CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ {25} \ +CONFIG.PCW_I2C_RESET_POLARITY {Active Low} \ +CONFIG.PCW_IMPORT_BOARD_PRESET {None} \ +CONFIG.PCW_INCLUDE_ACP_TRANS_CHECK {0} \ +CONFIG.PCW_INCLUDE_TRACE_BUFFER {0} \ +CONFIG.PCW_IOPLL_CTRL_FBDIV {20} \ +CONFIG.PCW_IO_IO_PLL_FREQMHZ {1000.000} \ +CONFIG.PCW_IRQ_F2P_INTR {0} \ +CONFIG.PCW_IRQ_F2P_MODE {DIRECT} \ +CONFIG.PCW_MIO_0_DIRECTION {inout} \ +CONFIG.PCW_MIO_0_IOTYPE {LVCMOS 3.3V} \ +CONFIG.PCW_MIO_0_PULLUP {enabled} \ +CONFIG.PCW_MIO_0_SLEW {slow} \ +CONFIG.PCW_MIO_10_DIRECTION {inout} \ +CONFIG.PCW_MIO_10_IOTYPE {LVCMOS 3.3V} \ +CONFIG.PCW_MIO_10_PULLUP {enabled} \ +CONFIG.PCW_MIO_10_SLEW {slow} \ +CONFIG.PCW_MIO_11_DIRECTION {inout} \ +CONFIG.PCW_MIO_11_IOTYPE {LVCMOS 3.3V} \ +CONFIG.PCW_MIO_11_PULLUP {enabled} \ +CONFIG.PCW_MIO_11_SLEW {slow} \ +CONFIG.PCW_MIO_12_DIRECTION {inout} \ +CONFIG.PCW_MIO_12_IOTYPE {LVCMOS 3.3V} \ +CONFIG.PCW_MIO_12_PULLUP {enabled} \ +CONFIG.PCW_MIO_12_SLEW {slow} \ +CONFIG.PCW_MIO_13_DIRECTION {inout} \ +CONFIG.PCW_MIO_13_IOTYPE {LVCMOS 3.3V} \ +CONFIG.PCW_MIO_13_PULLUP {enabled} \ +CONFIG.PCW_MIO_13_SLEW {slow} \ +CONFIG.PCW_MIO_14_DIRECTION {in} \ +CONFIG.PCW_MIO_14_IOTYPE {LVCMOS 3.3V} \ +CONFIG.PCW_MIO_14_PULLUP {enabled} \ +CONFIG.PCW_MIO_14_SLEW {slow} \ +CONFIG.PCW_MIO_15_DIRECTION {out} \ +CONFIG.PCW_MIO_15_IOTYPE {LVCMOS 3.3V} \ +CONFIG.PCW_MIO_15_PULLUP {enabled} \ +CONFIG.PCW_MIO_15_SLEW {slow} \ +CONFIG.PCW_MIO_16_DIRECTION {out} \ +CONFIG.PCW_MIO_16_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_16_PULLUP {enabled} \ +CONFIG.PCW_MIO_16_SLEW {slow} \ +CONFIG.PCW_MIO_17_DIRECTION {out} \ +CONFIG.PCW_MIO_17_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_17_PULLUP {enabled} \ +CONFIG.PCW_MIO_17_SLEW {slow} \ +CONFIG.PCW_MIO_18_DIRECTION {out} \ +CONFIG.PCW_MIO_18_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_18_PULLUP {enabled} \ +CONFIG.PCW_MIO_18_SLEW {slow} \ +CONFIG.PCW_MIO_19_DIRECTION {out} \ +CONFIG.PCW_MIO_19_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_19_PULLUP {enabled} \ +CONFIG.PCW_MIO_19_SLEW {slow} \ +CONFIG.PCW_MIO_1_DIRECTION {out} \ +CONFIG.PCW_MIO_1_IOTYPE {LVCMOS 3.3V} \ +CONFIG.PCW_MIO_1_PULLUP {enabled} \ +CONFIG.PCW_MIO_1_SLEW {slow} \ +CONFIG.PCW_MIO_20_DIRECTION {out} \ +CONFIG.PCW_MIO_20_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_20_PULLUP {enabled} \ +CONFIG.PCW_MIO_20_SLEW {slow} \ +CONFIG.PCW_MIO_21_DIRECTION {out} \ +CONFIG.PCW_MIO_21_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_21_PULLUP {enabled} \ +CONFIG.PCW_MIO_21_SLEW {slow} \ +CONFIG.PCW_MIO_22_DIRECTION {in} \ +CONFIG.PCW_MIO_22_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_22_PULLUP {enabled} \ +CONFIG.PCW_MIO_22_SLEW {slow} \ +CONFIG.PCW_MIO_23_DIRECTION {in} \ +CONFIG.PCW_MIO_23_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_23_PULLUP {enabled} \ +CONFIG.PCW_MIO_23_SLEW {slow} \ +CONFIG.PCW_MIO_24_DIRECTION {in} \ +CONFIG.PCW_MIO_24_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_24_PULLUP {enabled} \ +CONFIG.PCW_MIO_24_SLEW {slow} \ +CONFIG.PCW_MIO_25_DIRECTION {in} \ +CONFIG.PCW_MIO_25_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_25_PULLUP {enabled} \ +CONFIG.PCW_MIO_25_SLEW {slow} \ +CONFIG.PCW_MIO_26_DIRECTION {in} \ +CONFIG.PCW_MIO_26_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_26_PULLUP {enabled} \ +CONFIG.PCW_MIO_26_SLEW {slow} \ +CONFIG.PCW_MIO_27_DIRECTION {in} \ +CONFIG.PCW_MIO_27_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_27_PULLUP {enabled} \ +CONFIG.PCW_MIO_27_SLEW {slow} \ +CONFIG.PCW_MIO_28_DIRECTION {inout} \ +CONFIG.PCW_MIO_28_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_28_PULLUP {enabled} \ +CONFIG.PCW_MIO_28_SLEW {slow} \ +CONFIG.PCW_MIO_29_DIRECTION {in} \ +CONFIG.PCW_MIO_29_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_29_PULLUP {enabled} \ +CONFIG.PCW_MIO_29_SLEW {slow} \ +CONFIG.PCW_MIO_2_DIRECTION {inout} \ +CONFIG.PCW_MIO_2_IOTYPE {LVCMOS 3.3V} \ +CONFIG.PCW_MIO_2_PULLUP {disabled} \ +CONFIG.PCW_MIO_2_SLEW {slow} \ +CONFIG.PCW_MIO_30_DIRECTION {out} \ +CONFIG.PCW_MIO_30_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_30_PULLUP {enabled} \ +CONFIG.PCW_MIO_30_SLEW {slow} \ +CONFIG.PCW_MIO_31_DIRECTION {in} \ +CONFIG.PCW_MIO_31_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_31_PULLUP {enabled} \ +CONFIG.PCW_MIO_31_SLEW {slow} \ +CONFIG.PCW_MIO_32_DIRECTION {inout} \ +CONFIG.PCW_MIO_32_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_32_PULLUP {enabled} \ +CONFIG.PCW_MIO_32_SLEW {slow} \ +CONFIG.PCW_MIO_33_DIRECTION {inout} \ +CONFIG.PCW_MIO_33_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_33_PULLUP {enabled} \ +CONFIG.PCW_MIO_33_SLEW {slow} \ +CONFIG.PCW_MIO_34_DIRECTION {inout} \ +CONFIG.PCW_MIO_34_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_34_PULLUP {enabled} \ +CONFIG.PCW_MIO_34_SLEW {slow} \ +CONFIG.PCW_MIO_35_DIRECTION {inout} \ +CONFIG.PCW_MIO_35_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_35_PULLUP {enabled} \ +CONFIG.PCW_MIO_35_SLEW {slow} \ +CONFIG.PCW_MIO_36_DIRECTION {in} \ +CONFIG.PCW_MIO_36_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_36_PULLUP {enabled} \ +CONFIG.PCW_MIO_36_SLEW {slow} \ +CONFIG.PCW_MIO_37_DIRECTION {inout} \ +CONFIG.PCW_MIO_37_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_37_PULLUP {enabled} \ +CONFIG.PCW_MIO_37_SLEW {slow} \ +CONFIG.PCW_MIO_38_DIRECTION {inout} \ +CONFIG.PCW_MIO_38_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_38_PULLUP {enabled} \ +CONFIG.PCW_MIO_38_SLEW {slow} \ +CONFIG.PCW_MIO_39_DIRECTION {inout} \ +CONFIG.PCW_MIO_39_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_39_PULLUP {enabled} \ +CONFIG.PCW_MIO_39_SLEW {slow} \ +CONFIG.PCW_MIO_3_DIRECTION {inout} \ +CONFIG.PCW_MIO_3_IOTYPE {LVCMOS 3.3V} \ +CONFIG.PCW_MIO_3_PULLUP {disabled} \ +CONFIG.PCW_MIO_3_SLEW {slow} \ +CONFIG.PCW_MIO_40_DIRECTION {inout} \ +CONFIG.PCW_MIO_40_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_40_PULLUP {enabled} \ +CONFIG.PCW_MIO_40_SLEW {slow} \ +CONFIG.PCW_MIO_41_DIRECTION {inout} \ +CONFIG.PCW_MIO_41_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_41_PULLUP {enabled} \ +CONFIG.PCW_MIO_41_SLEW {slow} \ +CONFIG.PCW_MIO_42_DIRECTION {inout} \ +CONFIG.PCW_MIO_42_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_42_PULLUP {enabled} \ +CONFIG.PCW_MIO_42_SLEW {slow} \ +CONFIG.PCW_MIO_43_DIRECTION {inout} \ +CONFIG.PCW_MIO_43_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_43_PULLUP {enabled} \ +CONFIG.PCW_MIO_43_SLEW {slow} \ +CONFIG.PCW_MIO_44_DIRECTION {inout} \ +CONFIG.PCW_MIO_44_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_44_PULLUP {enabled} \ +CONFIG.PCW_MIO_44_SLEW {slow} \ +CONFIG.PCW_MIO_45_DIRECTION {inout} \ +CONFIG.PCW_MIO_45_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_45_PULLUP {enabled} \ +CONFIG.PCW_MIO_45_SLEW {slow} \ +CONFIG.PCW_MIO_46_DIRECTION {out} \ +CONFIG.PCW_MIO_46_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_46_PULLUP {enabled} \ +CONFIG.PCW_MIO_46_SLEW {slow} \ +CONFIG.PCW_MIO_47_DIRECTION {in} \ +CONFIG.PCW_MIO_47_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_47_PULLUP {enabled} \ +CONFIG.PCW_MIO_47_SLEW {slow} \ +CONFIG.PCW_MIO_48_DIRECTION {inout} \ +CONFIG.PCW_MIO_48_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_48_PULLUP {enabled} \ +CONFIG.PCW_MIO_48_SLEW {slow} \ +CONFIG.PCW_MIO_49_DIRECTION {inout} \ +CONFIG.PCW_MIO_49_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_49_PULLUP {enabled} \ +CONFIG.PCW_MIO_49_SLEW {slow} \ +CONFIG.PCW_MIO_4_DIRECTION {inout} \ +CONFIG.PCW_MIO_4_IOTYPE {LVCMOS 3.3V} \ +CONFIG.PCW_MIO_4_PULLUP {disabled} \ +CONFIG.PCW_MIO_4_SLEW {slow} \ +CONFIG.PCW_MIO_50_DIRECTION {inout} \ +CONFIG.PCW_MIO_50_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_50_PULLUP {enabled} \ +CONFIG.PCW_MIO_50_SLEW {slow} \ +CONFIG.PCW_MIO_51_DIRECTION {inout} \ +CONFIG.PCW_MIO_51_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_51_PULLUP {enabled} \ +CONFIG.PCW_MIO_51_SLEW {slow} \ +CONFIG.PCW_MIO_52_DIRECTION {out} \ +CONFIG.PCW_MIO_52_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_52_PULLUP {enabled} \ +CONFIG.PCW_MIO_52_SLEW {slow} \ +CONFIG.PCW_MIO_53_DIRECTION {inout} \ +CONFIG.PCW_MIO_53_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_53_PULLUP {enabled} \ +CONFIG.PCW_MIO_53_SLEW {slow} \ +CONFIG.PCW_MIO_5_DIRECTION {inout} \ +CONFIG.PCW_MIO_5_IOTYPE {LVCMOS 3.3V} \ +CONFIG.PCW_MIO_5_PULLUP {disabled} \ +CONFIG.PCW_MIO_5_SLEW {slow} \ +CONFIG.PCW_MIO_6_DIRECTION {out} \ +CONFIG.PCW_MIO_6_IOTYPE {LVCMOS 3.3V} \ +CONFIG.PCW_MIO_6_PULLUP {disabled} \ +CONFIG.PCW_MIO_6_SLEW {slow} \ +CONFIG.PCW_MIO_7_DIRECTION {out} \ +CONFIG.PCW_MIO_7_IOTYPE {LVCMOS 3.3V} \ +CONFIG.PCW_MIO_7_PULLUP {disabled} \ +CONFIG.PCW_MIO_7_SLEW {slow} \ +CONFIG.PCW_MIO_8_DIRECTION {out} \ +CONFIG.PCW_MIO_8_IOTYPE {LVCMOS 3.3V} \ +CONFIG.PCW_MIO_8_PULLUP {disabled} \ +CONFIG.PCW_MIO_8_SLEW {slow} \ +CONFIG.PCW_MIO_9_DIRECTION {out} \ +CONFIG.PCW_MIO_9_IOTYPE {LVCMOS 3.3V} \ +CONFIG.PCW_MIO_9_PULLUP {enabled} \ +CONFIG.PCW_MIO_9_SLEW {slow} \ +CONFIG.PCW_MIO_PRIMITIVE {54} \ +CONFIG.PCW_MIO_TREE_PERIPHERALS {GPIO#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO#Quad SPI Flash#ENET Reset#GPIO#GPIO#GPIO#GPIO#UART 0#UART 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#USB Reset#SD 0#GPIO#GPIO#GPIO#GPIO#Enet 0#Enet 0} \ +CONFIG.PCW_MIO_TREE_SIGNALS {gpio[0]#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]#qspi0_sclk#gpio[7]#qspi_fbclk#reset#gpio[10]#gpio[11]#gpio[12]#gpio[13]#rx#tx#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#clk#cmd#data[0]#data[1]#data[2]#data[3]#reset#cd#gpio[48]#gpio[49]#gpio[50]#gpio[51]#mdc#mdio} \ +CONFIG.PCW_M_AXI_GP0_ENABLE_STATIC_REMAP {0} \ +CONFIG.PCW_M_AXI_GP0_ID_WIDTH {12} \ +CONFIG.PCW_M_AXI_GP0_SUPPORT_NARROW_BURST {0} \ +CONFIG.PCW_M_AXI_GP0_THREAD_ID_WIDTH {12} \ +CONFIG.PCW_M_AXI_GP1_ENABLE_STATIC_REMAP {0} \ +CONFIG.PCW_M_AXI_GP1_ID_WIDTH {12} \ +CONFIG.PCW_M_AXI_GP1_SUPPORT_NARROW_BURST {0} \ +CONFIG.PCW_M_AXI_GP1_THREAD_ID_WIDTH {12} \ +CONFIG.PCW_NAND_CYCLES_T_AR {1} \ +CONFIG.PCW_NAND_CYCLES_T_CLR {1} \ +CONFIG.PCW_NAND_CYCLES_T_RC {11} \ +CONFIG.PCW_NAND_CYCLES_T_REA {1} \ +CONFIG.PCW_NAND_CYCLES_T_RR {1} \ +CONFIG.PCW_NAND_CYCLES_T_WC {11} \ +CONFIG.PCW_NAND_CYCLES_T_WP {1} \ +CONFIG.PCW_NAND_GRP_D8_ENABLE {0} \ +CONFIG.PCW_NAND_PERIPHERAL_ENABLE {0} \ +CONFIG.PCW_NOR_CS0_T_CEOE {1} \ +CONFIG.PCW_NOR_CS0_T_PC {1} \ +CONFIG.PCW_NOR_CS0_T_RC {11} \ +CONFIG.PCW_NOR_CS0_T_TR {1} \ +CONFIG.PCW_NOR_CS0_T_WC {11} \ +CONFIG.PCW_NOR_CS0_T_WP {1} \ +CONFIG.PCW_NOR_CS0_WE_TIME {0} \ +CONFIG.PCW_NOR_CS1_T_CEOE {1} \ +CONFIG.PCW_NOR_CS1_T_PC {1} \ +CONFIG.PCW_NOR_CS1_T_RC {11} \ +CONFIG.PCW_NOR_CS1_T_TR {1} \ +CONFIG.PCW_NOR_CS1_T_WC {11} \ +CONFIG.PCW_NOR_CS1_T_WP {1} \ +CONFIG.PCW_NOR_CS1_WE_TIME {0} \ +CONFIG.PCW_NOR_GRP_A25_ENABLE {0} \ +CONFIG.PCW_NOR_GRP_CS0_ENABLE {0} \ +CONFIG.PCW_NOR_GRP_CS1_ENABLE {0} \ +CONFIG.PCW_NOR_GRP_SRAM_CS0_ENABLE {0} \ +CONFIG.PCW_NOR_GRP_SRAM_CS1_ENABLE {0} \ +CONFIG.PCW_NOR_GRP_SRAM_INT_ENABLE {0} \ +CONFIG.PCW_NOR_PERIPHERAL_ENABLE {0} \ +CONFIG.PCW_NOR_SRAM_CS0_T_CEOE {1} \ +CONFIG.PCW_NOR_SRAM_CS0_T_PC {1} \ +CONFIG.PCW_NOR_SRAM_CS0_T_RC {11} \ +CONFIG.PCW_NOR_SRAM_CS0_T_TR {1} \ +CONFIG.PCW_NOR_SRAM_CS0_T_WC {11} \ +CONFIG.PCW_NOR_SRAM_CS0_T_WP {1} \ +CONFIG.PCW_NOR_SRAM_CS0_WE_TIME {0} \ +CONFIG.PCW_NOR_SRAM_CS1_T_CEOE {1} \ +CONFIG.PCW_NOR_SRAM_CS1_T_PC {1} \ +CONFIG.PCW_NOR_SRAM_CS1_T_RC {11} \ +CONFIG.PCW_NOR_SRAM_CS1_T_TR {1} \ +CONFIG.PCW_NOR_SRAM_CS1_T_WC {11} \ +CONFIG.PCW_NOR_SRAM_CS1_T_WP {1} \ +CONFIG.PCW_NOR_SRAM_CS1_WE_TIME {0} \ +CONFIG.PCW_OVERRIDE_BASIC_CLOCK {0} \ +CONFIG.PCW_P2F_CAN0_INTR {0} \ +CONFIG.PCW_P2F_CAN1_INTR {0} \ +CONFIG.PCW_P2F_CTI_INTR {0} \ +CONFIG.PCW_P2F_DMAC0_INTR {0} \ +CONFIG.PCW_P2F_DMAC1_INTR {0} \ +CONFIG.PCW_P2F_DMAC2_INTR {0} \ +CONFIG.PCW_P2F_DMAC3_INTR {0} \ +CONFIG.PCW_P2F_DMAC4_INTR {0} \ +CONFIG.PCW_P2F_DMAC5_INTR {0} \ +CONFIG.PCW_P2F_DMAC6_INTR {0} \ +CONFIG.PCW_P2F_DMAC7_INTR {0} \ +CONFIG.PCW_P2F_DMAC_ABORT_INTR {0} \ +CONFIG.PCW_P2F_ENET0_INTR {0} \ +CONFIG.PCW_P2F_ENET1_INTR {0} \ +CONFIG.PCW_P2F_GPIO_INTR {0} \ +CONFIG.PCW_P2F_I2C0_INTR {0} \ +CONFIG.PCW_P2F_I2C1_INTR {0} \ +CONFIG.PCW_P2F_QSPI_INTR {0} \ +CONFIG.PCW_P2F_SDIO0_INTR {0} \ +CONFIG.PCW_P2F_SDIO1_INTR {0} \ +CONFIG.PCW_P2F_SMC_INTR {0} \ +CONFIG.PCW_P2F_SPI0_INTR {0} \ +CONFIG.PCW_P2F_SPI1_INTR {0} \ +CONFIG.PCW_P2F_UART0_INTR {0} \ +CONFIG.PCW_P2F_UART1_INTR {0} \ +CONFIG.PCW_P2F_USB0_INTR {0} \ +CONFIG.PCW_P2F_USB1_INTR {0} \ +CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY0 {0.223} \ +CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY1 {0.212} \ +CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY2 {0.085} \ +CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY3 {0.092} \ +CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_0 {0.040} \ +CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_1 {0.058} \ +CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_2 {-0.009} \ +CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_3 {-0.033} \ +CONFIG.PCW_PACKAGE_NAME {clg400} \ +CONFIG.PCW_PCAP_PERIPHERAL_CLKSRC {IO PLL} \ +CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0 {5} \ +CONFIG.PCW_PCAP_PERIPHERAL_FREQMHZ {200} \ +CONFIG.PCW_PERIPHERAL_BOARD_PRESET {None} \ +CONFIG.PCW_PLL_BYPASSMODE_ENABLE {0} \ +CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 3.3V} \ +CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} \ +CONFIG.PCW_PS7_SI_REV {PRODUCTION} \ +CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE {1} \ +CONFIG.PCW_QSPI_GRP_FBCLK_IO {MIO 8} \ +CONFIG.PCW_QSPI_GRP_IO1_ENABLE {0} \ +CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {1} \ +CONFIG.PCW_QSPI_GRP_SINGLE_SS_IO {MIO 1 .. 6} \ +CONFIG.PCW_QSPI_GRP_SS1_ENABLE {0} \ +CONFIG.PCW_QSPI_INTERNAL_HIGHADDRESS {0xFCFFFFFF} \ +CONFIG.PCW_QSPI_PERIPHERAL_CLKSRC {IO PLL} \ +CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0 {5} \ +CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1} \ +CONFIG.PCW_QSPI_PERIPHERAL_FREQMHZ {200} \ +CONFIG.PCW_QSPI_QSPI_IO {MIO 1 .. 6} \ +CONFIG.PCW_SD0_GRP_CD_ENABLE {1} \ +CONFIG.PCW_SD0_GRP_CD_IO {MIO 47} \ +CONFIG.PCW_SD0_GRP_POW_ENABLE {0} \ +CONFIG.PCW_SD0_GRP_WP_ENABLE {0} \ +CONFIG.PCW_SD0_PERIPHERAL_ENABLE {1} \ +CONFIG.PCW_SD0_SD0_IO {MIO 40 .. 45} \ +CONFIG.PCW_SD1_GRP_CD_ENABLE {0} \ +CONFIG.PCW_SD1_GRP_POW_ENABLE {0} \ +CONFIG.PCW_SD1_GRP_WP_ENABLE {0} \ +CONFIG.PCW_SD1_PERIPHERAL_ENABLE {0} \ +CONFIG.PCW_SDIO0_BASEADDR {0xE0100000} \ +CONFIG.PCW_SDIO0_HIGHADDR {0xE0100FFF} \ +CONFIG.PCW_SDIO1_BASEADDR {0xE0101000} \ +CONFIG.PCW_SDIO1_HIGHADDR {0xE0101FFF} \ +CONFIG.PCW_SDIO_PERIPHERAL_CLKSRC {IO PLL} \ +CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0 {20} \ +CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {50} \ +CONFIG.PCW_SDIO_PERIPHERAL_VALID {1} \ +CONFIG.PCW_SMC_CYCLE_T0 {NA} \ +CONFIG.PCW_SMC_CYCLE_T1 {NA} \ +CONFIG.PCW_SMC_CYCLE_T2 {NA} \ +CONFIG.PCW_SMC_CYCLE_T3 {NA} \ +CONFIG.PCW_SMC_CYCLE_T4 {NA} \ +CONFIG.PCW_SMC_CYCLE_T5 {NA} \ +CONFIG.PCW_SMC_CYCLE_T6 {NA} \ +CONFIG.PCW_SMC_PERIPHERAL_CLKSRC {IO PLL} \ +CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0 {1} \ +CONFIG.PCW_SMC_PERIPHERAL_FREQMHZ {100} \ +CONFIG.PCW_SMC_PERIPHERAL_VALID {0} \ +CONFIG.PCW_SPI0_BASEADDR {0xE0006000} \ +CONFIG.PCW_SPI0_GRP_SS0_ENABLE {0} \ +CONFIG.PCW_SPI0_GRP_SS1_ENABLE {0} \ +CONFIG.PCW_SPI0_GRP_SS2_ENABLE {0} \ +CONFIG.PCW_SPI0_HIGHADDR {0xE0006FFF} \ +CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {0} \ +CONFIG.PCW_SPI1_BASEADDR {0xE0007000} \ +CONFIG.PCW_SPI1_GRP_SS0_ENABLE {0} \ +CONFIG.PCW_SPI1_GRP_SS1_ENABLE {0} \ +CONFIG.PCW_SPI1_HIGHADDR {0xE0007FFF} \ +CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {0} \ +CONFIG.PCW_SPI_PERIPHERAL_CLKSRC {IO PLL} \ +CONFIG.PCW_SPI_PERIPHERAL_DIVISOR0 {1} \ +CONFIG.PCW_SPI_PERIPHERAL_FREQMHZ {166.666666} \ +CONFIG.PCW_SPI_PERIPHERAL_VALID {0} \ +CONFIG.PCW_S_AXI_ACP_ARUSER_VAL {31} \ +CONFIG.PCW_S_AXI_ACP_AWUSER_VAL {31} \ +CONFIG.PCW_S_AXI_ACP_ID_WIDTH {3} \ +CONFIG.PCW_S_AXI_GP0_ID_WIDTH {6} \ +CONFIG.PCW_S_AXI_GP1_ID_WIDTH {6} \ +CONFIG.PCW_S_AXI_HP0_DATA_WIDTH {64} \ +CONFIG.PCW_S_AXI_HP0_ID_WIDTH {6} \ +CONFIG.PCW_S_AXI_HP1_DATA_WIDTH {64} \ +CONFIG.PCW_S_AXI_HP1_ID_WIDTH {6} \ +CONFIG.PCW_S_AXI_HP2_DATA_WIDTH {64} \ +CONFIG.PCW_S_AXI_HP2_ID_WIDTH {6} \ +CONFIG.PCW_S_AXI_HP3_DATA_WIDTH {64} \ +CONFIG.PCW_S_AXI_HP3_ID_WIDTH {6} \ +CONFIG.PCW_TPIU_PERIPHERAL_CLKSRC {External} \ +CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0 {1} \ +CONFIG.PCW_TPIU_PERIPHERAL_FREQMHZ {200} \ +CONFIG.PCW_TRACE_BUFFER_CLOCK_DELAY {12} \ +CONFIG.PCW_TRACE_BUFFER_FIFO_SIZE {128} \ +CONFIG.PCW_TRACE_PIPELINE_WIDTH {8} \ +CONFIG.PCW_TTC0_BASEADDR {0xE0104000} \ +CONFIG.PCW_TTC0_CLK0_PERIPHERAL_CLKSRC {CPU_1X} \ +CONFIG.PCW_TTC0_CLK0_PERIPHERAL_DIVISOR0 {1} \ +CONFIG.PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ {133.333333} \ +CONFIG.PCW_TTC0_CLK1_PERIPHERAL_CLKSRC {CPU_1X} \ +CONFIG.PCW_TTC0_CLK1_PERIPHERAL_DIVISOR0 {1} \ +CONFIG.PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ {133.333333} \ +CONFIG.PCW_TTC0_CLK2_PERIPHERAL_CLKSRC {CPU_1X} \ +CONFIG.PCW_TTC0_CLK2_PERIPHERAL_DIVISOR0 {1} \ +CONFIG.PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ {133.333333} \ +CONFIG.PCW_TTC0_HIGHADDR {0xE0104fff} \ +CONFIG.PCW_TTC1_BASEADDR {0xE0105000} \ +CONFIG.PCW_TTC1_CLK0_PERIPHERAL_CLKSRC {CPU_1X} \ +CONFIG.PCW_TTC1_CLK0_PERIPHERAL_DIVISOR0 {1} \ +CONFIG.PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ {133.333333} \ +CONFIG.PCW_TTC1_CLK1_PERIPHERAL_CLKSRC {CPU_1X} \ +CONFIG.PCW_TTC1_CLK1_PERIPHERAL_DIVISOR0 {1} \ +CONFIG.PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ {133.333333} \ +CONFIG.PCW_TTC1_CLK2_PERIPHERAL_CLKSRC {CPU_1X} \ +CONFIG.PCW_TTC1_CLK2_PERIPHERAL_DIVISOR0 {1} \ +CONFIG.PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ {133.333333} \ +CONFIG.PCW_TTC1_HIGHADDR {0xE0105fff} \ +CONFIG.PCW_TTC_PERIPHERAL_FREQMHZ {50} \ +CONFIG.PCW_UART0_BASEADDR {0xE0000000} \ +CONFIG.PCW_UART0_BAUD_RATE {115200} \ +CONFIG.PCW_UART0_GRP_FULL_ENABLE {0} \ +CONFIG.PCW_UART0_HIGHADDR {0xE0000FFF} \ +CONFIG.PCW_UART0_PERIPHERAL_ENABLE {1} \ +CONFIG.PCW_UART0_UART0_IO {MIO 14 .. 15} \ +CONFIG.PCW_UART1_BASEADDR {0xE0001000} \ +CONFIG.PCW_UART1_BAUD_RATE {115200} \ +CONFIG.PCW_UART1_GRP_FULL_ENABLE {0} \ +CONFIG.PCW_UART1_HIGHADDR {0xE0001FFF} \ +CONFIG.PCW_UART1_PERIPHERAL_ENABLE {0} \ +CONFIG.PCW_UART_PERIPHERAL_CLKSRC {IO PLL} \ +CONFIG.PCW_UART_PERIPHERAL_DIVISOR0 {10} \ +CONFIG.PCW_UART_PERIPHERAL_FREQMHZ {100} \ +CONFIG.PCW_UART_PERIPHERAL_VALID {1} \ +CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ {525.000000} \ +CONFIG.PCW_UIPARAM_DDR_ADV_ENABLE {0} \ +CONFIG.PCW_UIPARAM_DDR_AL {0} \ +CONFIG.PCW_UIPARAM_DDR_BANK_ADDR_COUNT {3} \ +CONFIG.PCW_UIPARAM_DDR_BL {8} \ +CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.223} \ +CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.212} \ +CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.085} \ +CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.092} \ +CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {16 Bit} \ +CONFIG.PCW_UIPARAM_DDR_CL {7} \ +CONFIG.PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM {25.8} \ +CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH {80.4535} \ +CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY {160} \ +CONFIG.PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM {25.8} \ +CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH {80.4535} \ +CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY {160} \ +CONFIG.PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM {0} \ +CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH {80.4535} \ +CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY {160} \ +CONFIG.PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM {0} \ +CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH {80.4535} \ +CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY {160} \ +CONFIG.PCW_UIPARAM_DDR_CLOCK_STOP_EN {0} \ +CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT {10} \ +CONFIG.PCW_UIPARAM_DDR_CWL {6} \ +CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY {4096 MBits} \ +CONFIG.PCW_UIPARAM_DDR_DQS_0_LENGTH_MM {15.6} \ +CONFIG.PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH {105.056} \ +CONFIG.PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY {160} \ +CONFIG.PCW_UIPARAM_DDR_DQS_1_LENGTH_MM {18.8} \ +CONFIG.PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH {66.904} \ +CONFIG.PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY {160} \ +CONFIG.PCW_UIPARAM_DDR_DQS_2_LENGTH_MM {0} \ +CONFIG.PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH {89.1715} \ +CONFIG.PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY {160} \ +CONFIG.PCW_UIPARAM_DDR_DQS_3_LENGTH_MM {0} \ +CONFIG.PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH {113.63} \ +CONFIG.PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY {160} \ +CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {0.040} \ +CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {0.058} \ +CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {-0.009} \ +CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {-0.033} \ +CONFIG.PCW_UIPARAM_DDR_DQ_0_LENGTH_MM {16.5} \ +CONFIG.PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH {98.503} \ +CONFIG.PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY {160} \ +CONFIG.PCW_UIPARAM_DDR_DQ_1_LENGTH_MM {18} \ +CONFIG.PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH {68.5855} \ +CONFIG.PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY {160} \ +CONFIG.PCW_UIPARAM_DDR_DQ_2_LENGTH_MM {0} \ +CONFIG.PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH {90.295} \ +CONFIG.PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY {160} \ +CONFIG.PCW_UIPARAM_DDR_DQ_3_LENGTH_MM {0} \ +CONFIG.PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH {103.977} \ +CONFIG.PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY {160} \ +CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH {16 Bits} \ +CONFIG.PCW_UIPARAM_DDR_ECC {Disabled} \ +CONFIG.PCW_UIPARAM_DDR_ENABLE {1} \ +CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ {525} \ +CONFIG.PCW_UIPARAM_DDR_HIGH_TEMP {Normal (0-85)} \ +CONFIG.PCW_UIPARAM_DDR_MEMORY_TYPE {DDR 3} \ +CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41J256M16 RE-125} \ +CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT {15} \ +CONFIG.PCW_UIPARAM_DDR_SPEED_BIN {DDR3_1066F} \ +CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE {1} \ +CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE {1} \ +CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL {1} \ +CONFIG.PCW_UIPARAM_DDR_T_FAW {40.0} \ +CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN {35.0} \ +CONFIG.PCW_UIPARAM_DDR_T_RC {48.91} \ +CONFIG.PCW_UIPARAM_DDR_T_RCD {7} \ +CONFIG.PCW_UIPARAM_DDR_T_RP {7} \ +CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF {0} \ +CONFIG.PCW_UIPARAM_GENERATE_SUMMARY {NA} \ +CONFIG.PCW_USB0_BASEADDR {0xE0102000} \ +CONFIG.PCW_USB0_HIGHADDR {0xE0102fff} \ +CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1} \ +CONFIG.PCW_USB0_PERIPHERAL_FREQMHZ {60} \ +CONFIG.PCW_USB0_RESET_ENABLE {1} \ +CONFIG.PCW_USB0_RESET_IO {MIO 46} \ +CONFIG.PCW_USB0_USB0_IO {MIO 28 .. 39} \ +CONFIG.PCW_USB1_BASEADDR {0xE0103000} \ +CONFIG.PCW_USB1_HIGHADDR {0xE0103fff} \ +CONFIG.PCW_USB1_PERIPHERAL_ENABLE {0} \ +CONFIG.PCW_USB1_PERIPHERAL_FREQMHZ {60} \ +CONFIG.PCW_USB_RESET_ENABLE {1} \ +CONFIG.PCW_USB_RESET_POLARITY {Active Low} \ +CONFIG.PCW_USB_RESET_SELECT {Share reset pin} \ +CONFIG.PCW_USE_AXI_FABRIC_IDLE {0} \ +CONFIG.PCW_USE_AXI_NONSECURE {0} \ +CONFIG.PCW_USE_CORESIGHT {0} \ +CONFIG.PCW_USE_CROSS_TRIGGER {0} \ +CONFIG.PCW_USE_CR_FABRIC {1} \ +CONFIG.PCW_USE_DDR_BYPASS {0} \ +CONFIG.PCW_USE_DEBUG {0} \ +CONFIG.PCW_USE_DEFAULT_ACP_USER_VAL {0} \ +CONFIG.PCW_USE_DMA0 {0} \ +CONFIG.PCW_USE_DMA1 {0} \ +CONFIG.PCW_USE_DMA2 {0} \ +CONFIG.PCW_USE_DMA3 {0} \ +CONFIG.PCW_USE_EXPANDED_IOP {0} \ +CONFIG.PCW_USE_EXPANDED_PS_SLCR_REGISTERS {0} \ +CONFIG.PCW_USE_FABRIC_INTERRUPT {0} \ +CONFIG.PCW_USE_HIGH_OCM {0} \ +CONFIG.PCW_USE_M_AXI_GP0 {1} \ +CONFIG.PCW_USE_M_AXI_GP1 {0} \ +CONFIG.PCW_USE_PROC_EVENT_BUS {0} \ +CONFIG.PCW_USE_PS_SLCR_REGISTERS {0} \ +CONFIG.PCW_USE_S_AXI_ACP {0} \ +CONFIG.PCW_USE_S_AXI_GP0 {0} \ +CONFIG.PCW_USE_S_AXI_GP1 {0} \ +CONFIG.PCW_USE_S_AXI_HP0 {1} \ +CONFIG.PCW_USE_S_AXI_HP1 {1} \ +CONFIG.PCW_USE_S_AXI_HP2 {1} \ +CONFIG.PCW_USE_S_AXI_HP3 {1} \ +CONFIG.PCW_USE_TRACE {0} \ +CONFIG.PCW_USE_TRACE_DATA_EDGE_DETECTOR {0} \ +CONFIG.PCW_VALUE_SILVERSION {3} \ +CONFIG.PCW_WDT_PERIPHERAL_CLKSRC {CPU_1X} \ +CONFIG.PCW_WDT_PERIPHERAL_DIVISOR0 {1} \ +CONFIG.PCW_WDT_PERIPHERAL_FREQMHZ {133.333333} \ + ] $processing_system7_0 + + # Create instance: ps7_0_axi_periph, and set properties + set ps7_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps7_0_axi_periph ] + set_property -dict [ list \ +CONFIG.NUM_MI {4} \ + ] $ps7_0_axi_periph + + # Create instance: rst_ps7_0_100M, and set properties + set rst_ps7_0_100M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ps7_0_100M ] + + # Create instance: triangle_counting_0, and set properties + set triangle_counting_0 [ create_bd_cell -type ip -vlnv xilinx.com:hls:triangle_counting:0.001 triangle_counting_0 ] + + # Create instance: triangle_counting_1, and set properties + set triangle_counting_1 [ create_bd_cell -type ip -vlnv xilinx.com:hls:triangle_counting:0.001 triangle_counting_1 ] + + # Create instance: triangle_counting_2, and set properties + set triangle_counting_2 [ create_bd_cell -type ip -vlnv xilinx.com:hls:triangle_counting:0.001 triangle_counting_2 ] + + # Create instance: triangle_counting_3, and set properties + set triangle_counting_3 [ create_bd_cell -type ip -vlnv xilinx.com:hls:triangle_counting:0.001 triangle_counting_3 ] + + # Create interface connections + connect_bd_intf_net -intf_net axi_smc_1_M00_AXI [get_bd_intf_pins axi_smc_1/M00_AXI] [get_bd_intf_pins processing_system7_0/S_AXI_HP1] + connect_bd_intf_net -intf_net axi_smc_2_M00_AXI [get_bd_intf_pins axi_smc_2/M00_AXI] [get_bd_intf_pins processing_system7_0/S_AXI_HP2] + connect_bd_intf_net -intf_net axi_smc_3_M00_AXI [get_bd_intf_pins axi_smc_3/M00_AXI] [get_bd_intf_pins processing_system7_0/S_AXI_HP3] + connect_bd_intf_net -intf_net axi_smc_M00_AXI [get_bd_intf_pins axi_smc/M00_AXI] [get_bd_intf_pins processing_system7_0/S_AXI_HP0] + connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR] + connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_0/FIXED_IO] + connect_bd_intf_net -intf_net processing_system7_0_M_AXI_GP0 [get_bd_intf_pins processing_system7_0/M_AXI_GP0] [get_bd_intf_pins ps7_0_axi_periph/S00_AXI] + connect_bd_intf_net -intf_net ps7_0_axi_periph_M00_AXI [get_bd_intf_pins ps7_0_axi_periph/M00_AXI] [get_bd_intf_pins triangle_counting_0/s_axi_AXILiteS] + connect_bd_intf_net -intf_net ps7_0_axi_periph_M01_AXI [get_bd_intf_pins ps7_0_axi_periph/M01_AXI] [get_bd_intf_pins triangle_counting_1/s_axi_AXILiteS] + connect_bd_intf_net -intf_net ps7_0_axi_periph_M02_AXI [get_bd_intf_pins ps7_0_axi_periph/M02_AXI] [get_bd_intf_pins triangle_counting_2/s_axi_AXILiteS] + connect_bd_intf_net -intf_net ps7_0_axi_periph_M03_AXI [get_bd_intf_pins ps7_0_axi_periph/M03_AXI] [get_bd_intf_pins triangle_counting_3/s_axi_AXILiteS] + connect_bd_intf_net -intf_net triangle_counting_0_m_axi_EDGE_r [get_bd_intf_pins axi_smc_2/S00_AXI] [get_bd_intf_pins triangle_counting_0/m_axi_EDGE_r] + connect_bd_intf_net -intf_net triangle_counting_0_m_axi_NEIGHBOR [get_bd_intf_pins axi_smc/S00_AXI] [get_bd_intf_pins triangle_counting_0/m_axi_NEIGHBOR] + connect_bd_intf_net -intf_net triangle_counting_0_m_axi_OFFSET [get_bd_intf_pins axi_smc_1/S00_AXI] [get_bd_intf_pins triangle_counting_0/m_axi_OFFSET] + connect_bd_intf_net -intf_net triangle_counting_0_m_axi_PROGRESS [get_bd_intf_pins axi_smc_3/S00_AXI] [get_bd_intf_pins triangle_counting_0/m_axi_PROGRESS] + connect_bd_intf_net -intf_net triangle_counting_1_m_axi_EDGE_r [get_bd_intf_pins axi_smc_2/S01_AXI] [get_bd_intf_pins triangle_counting_1/m_axi_EDGE_r] + connect_bd_intf_net -intf_net triangle_counting_1_m_axi_NEIGHBOR [get_bd_intf_pins axi_smc/S01_AXI] [get_bd_intf_pins triangle_counting_1/m_axi_NEIGHBOR] + connect_bd_intf_net -intf_net triangle_counting_1_m_axi_OFFSET [get_bd_intf_pins axi_smc_1/S01_AXI] [get_bd_intf_pins triangle_counting_1/m_axi_OFFSET] + connect_bd_intf_net -intf_net triangle_counting_1_m_axi_PROGRESS [get_bd_intf_pins axi_smc_3/S01_AXI] [get_bd_intf_pins triangle_counting_1/m_axi_PROGRESS] + connect_bd_intf_net -intf_net triangle_counting_2_m_axi_EDGE_r [get_bd_intf_pins axi_smc_2/S02_AXI] [get_bd_intf_pins triangle_counting_2/m_axi_EDGE_r] + connect_bd_intf_net -intf_net triangle_counting_2_m_axi_NEIGHBOR [get_bd_intf_pins axi_smc/S02_AXI] [get_bd_intf_pins triangle_counting_2/m_axi_NEIGHBOR] + connect_bd_intf_net -intf_net triangle_counting_2_m_axi_OFFSET [get_bd_intf_pins axi_smc_1/S02_AXI] [get_bd_intf_pins triangle_counting_2/m_axi_OFFSET] + connect_bd_intf_net -intf_net triangle_counting_2_m_axi_PROGRESS [get_bd_intf_pins axi_smc_3/S02_AXI] [get_bd_intf_pins triangle_counting_2/m_axi_PROGRESS] + connect_bd_intf_net -intf_net triangle_counting_3_m_axi_EDGE_r [get_bd_intf_pins axi_smc_2/S03_AXI] [get_bd_intf_pins triangle_counting_3/m_axi_EDGE_r] + connect_bd_intf_net -intf_net triangle_counting_3_m_axi_NEIGHBOR [get_bd_intf_pins axi_smc/S03_AXI] [get_bd_intf_pins triangle_counting_3/m_axi_NEIGHBOR] + connect_bd_intf_net -intf_net triangle_counting_3_m_axi_OFFSET [get_bd_intf_pins axi_smc_1/S03_AXI] [get_bd_intf_pins triangle_counting_3/m_axi_OFFSET] + connect_bd_intf_net -intf_net triangle_counting_3_m_axi_PROGRESS [get_bd_intf_pins axi_smc_3/S03_AXI] [get_bd_intf_pins triangle_counting_3/m_axi_PROGRESS] + + # Create port connections + connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_pins axi_smc/aclk] [get_bd_pins axi_smc_1/aclk] [get_bd_pins axi_smc_2/aclk] [get_bd_pins axi_smc_3/aclk] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP0_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP1_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP2_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP3_ACLK] [get_bd_pins ps7_0_axi_periph/ACLK] [get_bd_pins ps7_0_axi_periph/M00_ACLK] [get_bd_pins ps7_0_axi_periph/M01_ACLK] [get_bd_pins ps7_0_axi_periph/M02_ACLK] [get_bd_pins ps7_0_axi_periph/M03_ACLK] [get_bd_pins ps7_0_axi_periph/S00_ACLK] [get_bd_pins rst_ps7_0_100M/slowest_sync_clk] [get_bd_pins triangle_counting_0/ap_clk] [get_bd_pins triangle_counting_1/ap_clk] [get_bd_pins triangle_counting_2/ap_clk] [get_bd_pins triangle_counting_3/ap_clk] + connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins processing_system7_0/FCLK_RESET0_N] [get_bd_pins rst_ps7_0_100M/ext_reset_in] + connect_bd_net -net rst_ps7_0_100M_interconnect_aresetn [get_bd_pins ps7_0_axi_periph/ARESETN] [get_bd_pins rst_ps7_0_100M/interconnect_aresetn] + connect_bd_net -net rst_ps7_0_100M_peripheral_aresetn [get_bd_pins axi_smc/aresetn] [get_bd_pins axi_smc_1/aresetn] [get_bd_pins axi_smc_2/aresetn] [get_bd_pins axi_smc_3/aresetn] [get_bd_pins ps7_0_axi_periph/M00_ARESETN] [get_bd_pins ps7_0_axi_periph/M01_ARESETN] [get_bd_pins ps7_0_axi_periph/M02_ARESETN] [get_bd_pins ps7_0_axi_periph/M03_ARESETN] [get_bd_pins ps7_0_axi_periph/S00_ARESETN] [get_bd_pins rst_ps7_0_100M/peripheral_aresetn] [get_bd_pins triangle_counting_0/ap_rst_n] [get_bd_pins triangle_counting_1/ap_rst_n] [get_bd_pins triangle_counting_2/ap_rst_n] [get_bd_pins triangle_counting_3/ap_rst_n] + + # Create address segments + create_bd_addr_seg -range 0x00010000 -offset 0x43C00000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs triangle_counting_0/s_axi_AXILiteS/Reg] SEG_triangle_counting_0_Reg + create_bd_addr_seg -range 0x00010000 -offset 0x43C10000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs triangle_counting_1/s_axi_AXILiteS/Reg] SEG_triangle_counting_1_Reg + create_bd_addr_seg -range 0x00010000 -offset 0x43C20000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs triangle_counting_2/s_axi_AXILiteS/Reg] SEG_triangle_counting_2_Reg + create_bd_addr_seg -range 0x00010000 -offset 0x43C30000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs triangle_counting_3/s_axi_AXILiteS/Reg] SEG_triangle_counting_3_Reg + create_bd_addr_seg -range 0x20000000 -offset 0x00000000 [get_bd_addr_spaces triangle_counting_0/Data_m_axi_NEIGHBOR] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM] SEG_processing_system7_0_HP0_DDR_LOWOCM + create_bd_addr_seg -range 0x20000000 -offset 0x00000000 [get_bd_addr_spaces triangle_counting_0/Data_m_axi_OFFSET] [get_bd_addr_segs processing_system7_0/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_processing_system7_0_HP1_DDR_LOWOCM + create_bd_addr_seg -range 0x20000000 -offset 0x00000000 [get_bd_addr_spaces triangle_counting_0/Data_m_axi_EDGE_r] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM + create_bd_addr_seg -range 0x20000000 -offset 0x00000000 [get_bd_addr_spaces triangle_counting_0/Data_m_axi_PROGRESS] [get_bd_addr_segs processing_system7_0/S_AXI_HP3/HP3_DDR_LOWOCM] SEG_processing_system7_0_HP3_DDR_LOWOCM + create_bd_addr_seg -range 0x20000000 -offset 0x00000000 [get_bd_addr_spaces triangle_counting_1/Data_m_axi_NEIGHBOR] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM] SEG_processing_system7_0_HP0_DDR_LOWOCM + create_bd_addr_seg -range 0x20000000 -offset 0x00000000 [get_bd_addr_spaces triangle_counting_1/Data_m_axi_OFFSET] [get_bd_addr_segs processing_system7_0/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_processing_system7_0_HP1_DDR_LOWOCM + create_bd_addr_seg -range 0x20000000 -offset 0x00000000 [get_bd_addr_spaces triangle_counting_1/Data_m_axi_EDGE_r] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM + create_bd_addr_seg -range 0x20000000 -offset 0x00000000 [get_bd_addr_spaces triangle_counting_1/Data_m_axi_PROGRESS] [get_bd_addr_segs processing_system7_0/S_AXI_HP3/HP3_DDR_LOWOCM] SEG_processing_system7_0_HP3_DDR_LOWOCM + create_bd_addr_seg -range 0x20000000 -offset 0x00000000 [get_bd_addr_spaces triangle_counting_2/Data_m_axi_NEIGHBOR] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM] SEG_processing_system7_0_HP0_DDR_LOWOCM + create_bd_addr_seg -range 0x20000000 -offset 0x00000000 [get_bd_addr_spaces triangle_counting_2/Data_m_axi_OFFSET] [get_bd_addr_segs processing_system7_0/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_processing_system7_0_HP1_DDR_LOWOCM + create_bd_addr_seg -range 0x20000000 -offset 0x00000000 [get_bd_addr_spaces triangle_counting_2/Data_m_axi_EDGE_r] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM + create_bd_addr_seg -range 0x20000000 -offset 0x00000000 [get_bd_addr_spaces triangle_counting_2/Data_m_axi_PROGRESS] [get_bd_addr_segs processing_system7_0/S_AXI_HP3/HP3_DDR_LOWOCM] SEG_processing_system7_0_HP3_DDR_LOWOCM + create_bd_addr_seg -range 0x20000000 -offset 0x00000000 [get_bd_addr_spaces triangle_counting_3/Data_m_axi_NEIGHBOR] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM] SEG_processing_system7_0_HP0_DDR_LOWOCM + create_bd_addr_seg -range 0x20000000 -offset 0x00000000 [get_bd_addr_spaces triangle_counting_3/Data_m_axi_OFFSET] [get_bd_addr_segs processing_system7_0/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_processing_system7_0_HP1_DDR_LOWOCM + create_bd_addr_seg -range 0x20000000 -offset 0x00000000 [get_bd_addr_spaces triangle_counting_3/Data_m_axi_EDGE_r] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM + create_bd_addr_seg -range 0x20000000 -offset 0x00000000 [get_bd_addr_spaces triangle_counting_3/Data_m_axi_PROGRESS] [get_bd_addr_segs processing_system7_0/S_AXI_HP3/HP3_DDR_LOWOCM] SEG_processing_system7_0_HP3_DDR_LOWOCM + + + # Restore current instance + current_bd_instance $oldCurInst + + save_bd_design +} +# End of create_root_design() + + +################################################################## +# MAIN FLOW +################################################################## + +create_root_design "" + + diff --git a/bitstreams/tc_opt_7.bit b/bitstreams/tc_opt_7.bit new file mode 100644 index 0000000..f70a24f Binary files /dev/null and b/bitstreams/tc_opt_7.bit differ diff --git a/bitstreams/tc_opt_7.tcl b/bitstreams/tc_opt_7.tcl new file mode 100644 index 0000000..df1cee2 --- /dev/null +++ b/bitstreams/tc_opt_7.tcl @@ -0,0 +1,1085 @@ + +################################################################ +# This is a generated script based on design: hw_platform +# +# Though there are limitations about the generated script, +# the main purpose of this utility is to make learning +# IP Integrator Tcl commands easier. +################################################################ + +namespace eval _tcl { +proc get_script_folder {} { + set script_path [file normalize [info script]] + set script_folder [file dirname $script_path] + return $script_folder +} +} +variable script_folder +set script_folder [_tcl::get_script_folder] + +################################################################ +# Check if script is running in correct Vivado version. +################################################################ +set scripts_vivado_version 2017.2 +set current_vivado_version [version -short] + +if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { + puts "" + catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} + + return 1 +} + +################################################################ +# START +################################################################ + +# To test this script, run the following commands from Vivado Tcl console: +# source hw_platform_script.tcl + +# If there is no project opened, this script will create a +# project, but make sure you do not have an existing project +# <./myproj/project_1.xpr> in the current working folder. + +set list_projs [get_projects -quiet] +if { $list_projs eq "" } { + create_project project_1 myproj -part xc7z020clg400-1 + set_property BOARD_PART www.digilentinc.com:pynq-z1:part0:1.0 [current_project] +} + + +# CHANGE DESIGN NAME HERE +set design_name hw_platform + +# If you do not already have an existing IP Integrator design open, +# you can create a design using the following command: +# create_bd_design $design_name + +# Creating design if needed +set errMsg "" +set nRet 0 + +set cur_design [current_bd_design -quiet] +set list_cells [get_bd_cells -quiet] + +if { ${design_name} eq "" } { + # USE CASES: + # 1) Design_name not set + + set errMsg "Please set the variable to a non-empty value." + set nRet 1 + +} elseif { ${cur_design} ne "" && ${list_cells} eq "" } { + # USE CASES: + # 2): Current design opened AND is empty AND names same. + # 3): Current design opened AND is empty AND names diff; design_name NOT in project. + # 4): Current design opened AND is empty AND names diff; design_name exists in project. + + if { $cur_design ne $design_name } { + common::send_msg_id "BD_TCL-001" "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." + set design_name [get_property NAME $cur_design] + } + common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..." + +} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { + # USE CASES: + # 5) Current design opened AND has components AND same names. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 1 +} elseif { [get_files -quiet ${design_name}.bd] ne "" } { + # USE CASES: + # 6) Current opened design, has components, but diff names, design_name exists in project. + # 7) No opened design, design_name exists in project. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 2 + +} else { + # USE CASES: + # 8) No opened design, design_name not in project. + # 9) Current opened design, has components, but diff names, design_name not in project. + + common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..." + + create_bd_design $design_name + + common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design." + current_bd_design $design_name + +} + +common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable is equal to \"$design_name\"." + +if { $nRet != 0 } { + catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg} + return $nRet +} + +################################################################## +# DESIGN PROCs +################################################################## + + + +# Procedure to create entire design; Provide argument to make +# procedure reusable. If parentCell is "", will use root. +proc create_root_design { parentCell } { + + variable script_folder + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + + # Create interface ports + set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ] + set FIXED_IO [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO ] + + # Create ports + + # Create instance: axi_smc, and set properties + set axi_smc [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_smc ] + set_property -dict [ list \ +CONFIG.NUM_SI {8} \ + ] $axi_smc + + # Create instance: axi_smc_1, and set properties + set axi_smc_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_smc_1 ] + set_property -dict [ list \ +CONFIG.NUM_SI {8} \ + ] $axi_smc_1 + + # Create instance: axi_smc_2, and set properties + set axi_smc_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_smc_2 ] + set_property -dict [ list \ +CONFIG.NUM_SI {8} \ + ] $axi_smc_2 + + # Create instance: axi_smc_3, and set properties + set axi_smc_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_smc_3 ] + set_property -dict [ list \ +CONFIG.NUM_SI {8} \ + ] $axi_smc_3 + + # Create instance: processing_system7_0, and set properties + set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ] + set_property -dict [ list \ +CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {650.000000} \ +CONFIG.PCW_ACT_CAN0_PERIPHERAL_FREQMHZ {23.8095} \ +CONFIG.PCW_ACT_CAN1_PERIPHERAL_FREQMHZ {23.8095} \ +CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ {10.000000} \ +CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.096154} \ +CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {125.000000} \ +CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ {10.000000} \ +CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {100.000000} \ +CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {10.000000} \ +CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ {10.000000} \ +CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ {10.000000} \ +CONFIG.PCW_ACT_I2C_PERIPHERAL_FREQMHZ {50} \ +CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ {200.000000} \ +CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {200.000000} \ +CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {50.000000} \ +CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ {10.000000} \ +CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ {10.000000} \ +CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ {200.000000} \ +CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ {108.333336} \ +CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ {108.333336} \ +CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ {108.333336} \ +CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ {108.333336} \ +CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ {108.333336} \ +CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ {108.333336} \ +CONFIG.PCW_ACT_TTC_PERIPHERAL_FREQMHZ {50} \ +CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {100.000000} \ +CONFIG.PCW_ACT_USB0_PERIPHERAL_FREQMHZ {60} \ +CONFIG.PCW_ACT_USB1_PERIPHERAL_FREQMHZ {60} \ +CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ {108.333336} \ +CONFIG.PCW_APU_CLK_RATIO_ENABLE {6:2:1} \ +CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {650} \ +CONFIG.PCW_ARMPLL_CTRL_FBDIV {26} \ +CONFIG.PCW_CAN0_BASEADDR {0xE0008000} \ +CONFIG.PCW_CAN0_HIGHADDR {0xE0008FFF} \ +CONFIG.PCW_CAN0_PERIPHERAL_CLKSRC {External} \ +CONFIG.PCW_CAN0_PERIPHERAL_FREQMHZ {-1} \ +CONFIG.PCW_CAN1_BASEADDR {0xE0009000} \ +CONFIG.PCW_CAN1_HIGHADDR {0xE0009FFF} \ +CONFIG.PCW_CAN1_PERIPHERAL_CLKSRC {External} \ +CONFIG.PCW_CAN1_PERIPHERAL_FREQMHZ {-1} \ +CONFIG.PCW_CAN_PERIPHERAL_CLKSRC {IO PLL} \ +CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0 {1} \ +CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1 {1} \ +CONFIG.PCW_CAN_PERIPHERAL_FREQMHZ {100} \ +CONFIG.PCW_CAN_PERIPHERAL_VALID {0} \ +CONFIG.PCW_CLK0_FREQ {100000000} \ +CONFIG.PCW_CLK1_FREQ {10000000} \ +CONFIG.PCW_CLK2_FREQ {10000000} \ +CONFIG.PCW_CLK3_FREQ {10000000} \ +CONFIG.PCW_CORE0_FIQ_INTR {0} \ +CONFIG.PCW_CORE0_IRQ_INTR {0} \ +CONFIG.PCW_CORE1_FIQ_INTR {0} \ +CONFIG.PCW_CORE1_IRQ_INTR {0} \ +CONFIG.PCW_CPU_CPU_6X4X_MAX_RANGE {667} \ +CONFIG.PCW_CPU_CPU_PLL_FREQMHZ {1300.000} \ +CONFIG.PCW_CPU_PERIPHERAL_CLKSRC {ARM PLL} \ +CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0 {2} \ +CONFIG.PCW_CRYSTAL_PERIPHERAL_FREQMHZ {50} \ +CONFIG.PCW_DCI_PERIPHERAL_CLKSRC {DDR PLL} \ +CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0 {52} \ +CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1 {2} \ +CONFIG.PCW_DCI_PERIPHERAL_FREQMHZ {10.159} \ +CONFIG.PCW_DDRPLL_CTRL_FBDIV {21} \ +CONFIG.PCW_DDR_DDR_PLL_FREQMHZ {1050.000} \ +CONFIG.PCW_DDR_HPRLPR_QUEUE_PARTITION {HPR(0)/LPR(32)} \ +CONFIG.PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL {15} \ +CONFIG.PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL {2} \ +CONFIG.PCW_DDR_PERIPHERAL_CLKSRC {DDR PLL} \ +CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0 {2} \ +CONFIG.PCW_DDR_PORT0_HPR_ENABLE {0} \ +CONFIG.PCW_DDR_PORT1_HPR_ENABLE {0} \ +CONFIG.PCW_DDR_PORT2_HPR_ENABLE {0} \ +CONFIG.PCW_DDR_PORT3_HPR_ENABLE {0} \ +CONFIG.PCW_DDR_RAM_BASEADDR {0x00100000} \ +CONFIG.PCW_DDR_RAM_HIGHADDR {0x1FFFFFFF} \ +CONFIG.PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL {2} \ +CONFIG.PCW_DM_WIDTH {4} \ +CONFIG.PCW_DQS_WIDTH {4} \ +CONFIG.PCW_DQ_WIDTH {32} \ +CONFIG.PCW_ENET0_BASEADDR {0xE000B000} \ +CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27} \ +CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1} \ +CONFIG.PCW_ENET0_GRP_MDIO_IO {MIO 52 .. 53} \ +CONFIG.PCW_ENET0_HIGHADDR {0xE000BFFF} \ +CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC {IO PLL} \ +CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0 {8} \ +CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1 {1} \ +CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1} \ +CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ {1000 Mbps} \ +CONFIG.PCW_ENET0_RESET_ENABLE {1} \ +CONFIG.PCW_ENET0_RESET_IO {MIO 9} \ +CONFIG.PCW_ENET1_BASEADDR {0xE000C000} \ +CONFIG.PCW_ENET1_GRP_MDIO_ENABLE {0} \ +CONFIG.PCW_ENET1_HIGHADDR {0xE000CFFF} \ +CONFIG.PCW_ENET1_PERIPHERAL_CLKSRC {IO PLL} \ +CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0 {1} \ +CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1 {1} \ +CONFIG.PCW_ENET1_PERIPHERAL_ENABLE {0} \ +CONFIG.PCW_ENET1_PERIPHERAL_FREQMHZ {1000 Mbps} \ +CONFIG.PCW_ENET1_RESET_ENABLE {0} \ +CONFIG.PCW_ENET_RESET_ENABLE {1} \ +CONFIG.PCW_ENET_RESET_POLARITY {Active Low} \ +CONFIG.PCW_ENET_RESET_SELECT {Share reset pin} \ +CONFIG.PCW_EN_4K_TIMER {0} \ +CONFIG.PCW_EN_CAN0 {0} \ +CONFIG.PCW_EN_CAN1 {0} \ +CONFIG.PCW_EN_CLK0_PORT {1} \ +CONFIG.PCW_EN_CLK1_PORT {0} \ +CONFIG.PCW_EN_CLK2_PORT {0} \ +CONFIG.PCW_EN_CLK3_PORT {0} \ +CONFIG.PCW_EN_CLKTRIG0_PORT {0} \ +CONFIG.PCW_EN_CLKTRIG1_PORT {0} \ +CONFIG.PCW_EN_CLKTRIG2_PORT {0} \ +CONFIG.PCW_EN_CLKTRIG3_PORT {0} \ +CONFIG.PCW_EN_DDR {1} \ +CONFIG.PCW_EN_EMIO_CAN0 {0} \ +CONFIG.PCW_EN_EMIO_CAN1 {0} \ +CONFIG.PCW_EN_EMIO_CD_SDIO0 {0} \ +CONFIG.PCW_EN_EMIO_CD_SDIO1 {0} \ +CONFIG.PCW_EN_EMIO_ENET0 {0} \ +CONFIG.PCW_EN_EMIO_ENET1 {0} \ +CONFIG.PCW_EN_EMIO_GPIO {0} \ +CONFIG.PCW_EN_EMIO_I2C0 {0} \ +CONFIG.PCW_EN_EMIO_I2C1 {0} \ +CONFIG.PCW_EN_EMIO_MODEM_UART0 {0} \ +CONFIG.PCW_EN_EMIO_MODEM_UART1 {0} \ +CONFIG.PCW_EN_EMIO_PJTAG {0} \ +CONFIG.PCW_EN_EMIO_SDIO0 {0} \ +CONFIG.PCW_EN_EMIO_SDIO1 {0} \ +CONFIG.PCW_EN_EMIO_SPI0 {0} \ +CONFIG.PCW_EN_EMIO_SPI1 {0} \ +CONFIG.PCW_EN_EMIO_SRAM_INT {0} \ +CONFIG.PCW_EN_EMIO_TRACE {0} \ +CONFIG.PCW_EN_EMIO_TTC0 {0} \ +CONFIG.PCW_EN_EMIO_TTC1 {0} \ +CONFIG.PCW_EN_EMIO_UART0 {0} \ +CONFIG.PCW_EN_EMIO_UART1 {0} \ +CONFIG.PCW_EN_EMIO_WDT {0} \ +CONFIG.PCW_EN_EMIO_WP_SDIO0 {0} \ +CONFIG.PCW_EN_EMIO_WP_SDIO1 {0} \ +CONFIG.PCW_EN_ENET0 {1} \ +CONFIG.PCW_EN_ENET1 {0} \ +CONFIG.PCW_EN_GPIO {1} \ +CONFIG.PCW_EN_I2C0 {0} \ +CONFIG.PCW_EN_I2C1 {0} \ +CONFIG.PCW_EN_MODEM_UART0 {0} \ +CONFIG.PCW_EN_MODEM_UART1 {0} \ +CONFIG.PCW_EN_PJTAG {0} \ +CONFIG.PCW_EN_PTP_ENET0 {0} \ +CONFIG.PCW_EN_PTP_ENET1 {0} \ +CONFIG.PCW_EN_QSPI {1} \ +CONFIG.PCW_EN_RST0_PORT {1} \ +CONFIG.PCW_EN_RST1_PORT {0} \ +CONFIG.PCW_EN_RST2_PORT {0} \ +CONFIG.PCW_EN_RST3_PORT {0} \ +CONFIG.PCW_EN_SDIO0 {1} \ +CONFIG.PCW_EN_SDIO1 {0} \ +CONFIG.PCW_EN_SMC {0} \ +CONFIG.PCW_EN_SPI0 {0} \ +CONFIG.PCW_EN_SPI1 {0} \ +CONFIG.PCW_EN_TRACE {0} \ +CONFIG.PCW_EN_TTC0 {0} \ +CONFIG.PCW_EN_TTC1 {0} \ +CONFIG.PCW_EN_UART0 {1} \ +CONFIG.PCW_EN_UART1 {0} \ +CONFIG.PCW_EN_USB0 {1} \ +CONFIG.PCW_EN_USB1 {0} \ +CONFIG.PCW_EN_WDT {0} \ +CONFIG.PCW_FCLK0_PERIPHERAL_CLKSRC {IO PLL} \ +CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0 {5} \ +CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1 {2} \ +CONFIG.PCW_FCLK1_PERIPHERAL_CLKSRC {IO PLL} \ +CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0 {1} \ +CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1 {1} \ +CONFIG.PCW_FCLK2_PERIPHERAL_CLKSRC {IO PLL} \ +CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0 {1} \ +CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1 {1} \ +CONFIG.PCW_FCLK3_PERIPHERAL_CLKSRC {IO PLL} \ +CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0 {1} \ +CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1 {1} \ +CONFIG.PCW_FCLK_CLK0_BUF {TRUE} \ +CONFIG.PCW_FCLK_CLK1_BUF {FALSE} \ +CONFIG.PCW_FCLK_CLK2_BUF {FALSE} \ +CONFIG.PCW_FCLK_CLK3_BUF {FALSE} \ +CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100} \ +CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {50} \ +CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {50} \ +CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ {50} \ +CONFIG.PCW_FPGA_FCLK0_ENABLE {1} \ +CONFIG.PCW_FPGA_FCLK1_ENABLE {0} \ +CONFIG.PCW_FPGA_FCLK2_ENABLE {0} \ +CONFIG.PCW_FPGA_FCLK3_ENABLE {0} \ +CONFIG.PCW_GPIO_BASEADDR {0xE000A000} \ +CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {0} \ +CONFIG.PCW_GPIO_EMIO_GPIO_WIDTH {64} \ +CONFIG.PCW_GPIO_HIGHADDR {0xE000AFFF} \ +CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} \ +CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO} \ +CONFIG.PCW_GPIO_PERIPHERAL_ENABLE {0} \ +CONFIG.PCW_I2C0_BASEADDR {0xE0004000} \ +CONFIG.PCW_I2C0_HIGHADDR {0xE0004FFF} \ +CONFIG.PCW_I2C1_BASEADDR {0xE0005000} \ +CONFIG.PCW_I2C1_HIGHADDR {0xE0005FFF} \ +CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ {25} \ +CONFIG.PCW_I2C_RESET_POLARITY {Active Low} \ +CONFIG.PCW_IMPORT_BOARD_PRESET {None} \ +CONFIG.PCW_INCLUDE_ACP_TRANS_CHECK {0} \ +CONFIG.PCW_INCLUDE_TRACE_BUFFER {0} \ +CONFIG.PCW_IOPLL_CTRL_FBDIV {20} \ +CONFIG.PCW_IO_IO_PLL_FREQMHZ {1000.000} \ +CONFIG.PCW_IRQ_F2P_INTR {0} \ +CONFIG.PCW_IRQ_F2P_MODE {DIRECT} \ +CONFIG.PCW_MIO_0_DIRECTION {inout} \ +CONFIG.PCW_MIO_0_IOTYPE {LVCMOS 3.3V} \ +CONFIG.PCW_MIO_0_PULLUP {enabled} \ +CONFIG.PCW_MIO_0_SLEW {slow} \ +CONFIG.PCW_MIO_10_DIRECTION {inout} \ +CONFIG.PCW_MIO_10_IOTYPE {LVCMOS 3.3V} \ +CONFIG.PCW_MIO_10_PULLUP {enabled} \ +CONFIG.PCW_MIO_10_SLEW {slow} \ +CONFIG.PCW_MIO_11_DIRECTION {inout} \ +CONFIG.PCW_MIO_11_IOTYPE {LVCMOS 3.3V} \ +CONFIG.PCW_MIO_11_PULLUP {enabled} \ +CONFIG.PCW_MIO_11_SLEW {slow} \ +CONFIG.PCW_MIO_12_DIRECTION {inout} \ +CONFIG.PCW_MIO_12_IOTYPE {LVCMOS 3.3V} \ +CONFIG.PCW_MIO_12_PULLUP {enabled} \ +CONFIG.PCW_MIO_12_SLEW {slow} \ +CONFIG.PCW_MIO_13_DIRECTION {inout} \ +CONFIG.PCW_MIO_13_IOTYPE {LVCMOS 3.3V} \ +CONFIG.PCW_MIO_13_PULLUP {enabled} \ +CONFIG.PCW_MIO_13_SLEW {slow} \ +CONFIG.PCW_MIO_14_DIRECTION {in} \ +CONFIG.PCW_MIO_14_IOTYPE {LVCMOS 3.3V} \ +CONFIG.PCW_MIO_14_PULLUP {enabled} \ +CONFIG.PCW_MIO_14_SLEW {slow} \ +CONFIG.PCW_MIO_15_DIRECTION {out} \ +CONFIG.PCW_MIO_15_IOTYPE {LVCMOS 3.3V} \ +CONFIG.PCW_MIO_15_PULLUP {enabled} \ +CONFIG.PCW_MIO_15_SLEW {slow} \ +CONFIG.PCW_MIO_16_DIRECTION {out} \ +CONFIG.PCW_MIO_16_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_16_PULLUP {enabled} \ +CONFIG.PCW_MIO_16_SLEW {slow} \ +CONFIG.PCW_MIO_17_DIRECTION {out} \ +CONFIG.PCW_MIO_17_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_17_PULLUP {enabled} \ +CONFIG.PCW_MIO_17_SLEW {slow} \ +CONFIG.PCW_MIO_18_DIRECTION {out} \ +CONFIG.PCW_MIO_18_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_18_PULLUP {enabled} \ +CONFIG.PCW_MIO_18_SLEW {slow} \ +CONFIG.PCW_MIO_19_DIRECTION {out} \ +CONFIG.PCW_MIO_19_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_19_PULLUP {enabled} \ +CONFIG.PCW_MIO_19_SLEW {slow} \ +CONFIG.PCW_MIO_1_DIRECTION {out} \ +CONFIG.PCW_MIO_1_IOTYPE {LVCMOS 3.3V} \ +CONFIG.PCW_MIO_1_PULLUP {enabled} \ +CONFIG.PCW_MIO_1_SLEW {slow} \ +CONFIG.PCW_MIO_20_DIRECTION {out} \ +CONFIG.PCW_MIO_20_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_20_PULLUP {enabled} \ +CONFIG.PCW_MIO_20_SLEW {slow} \ +CONFIG.PCW_MIO_21_DIRECTION {out} \ +CONFIG.PCW_MIO_21_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_21_PULLUP {enabled} \ +CONFIG.PCW_MIO_21_SLEW {slow} \ +CONFIG.PCW_MIO_22_DIRECTION {in} \ +CONFIG.PCW_MIO_22_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_22_PULLUP {enabled} \ +CONFIG.PCW_MIO_22_SLEW {slow} \ +CONFIG.PCW_MIO_23_DIRECTION {in} \ +CONFIG.PCW_MIO_23_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_23_PULLUP {enabled} \ +CONFIG.PCW_MIO_23_SLEW {slow} \ +CONFIG.PCW_MIO_24_DIRECTION {in} \ +CONFIG.PCW_MIO_24_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_24_PULLUP {enabled} \ +CONFIG.PCW_MIO_24_SLEW {slow} \ +CONFIG.PCW_MIO_25_DIRECTION {in} \ +CONFIG.PCW_MIO_25_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_25_PULLUP {enabled} \ +CONFIG.PCW_MIO_25_SLEW {slow} \ +CONFIG.PCW_MIO_26_DIRECTION {in} \ +CONFIG.PCW_MIO_26_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_26_PULLUP {enabled} \ +CONFIG.PCW_MIO_26_SLEW {slow} \ +CONFIG.PCW_MIO_27_DIRECTION {in} \ +CONFIG.PCW_MIO_27_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_27_PULLUP {enabled} \ +CONFIG.PCW_MIO_27_SLEW {slow} \ +CONFIG.PCW_MIO_28_DIRECTION {inout} \ +CONFIG.PCW_MIO_28_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_28_PULLUP {enabled} \ +CONFIG.PCW_MIO_28_SLEW {slow} \ +CONFIG.PCW_MIO_29_DIRECTION {in} \ +CONFIG.PCW_MIO_29_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_29_PULLUP {enabled} \ +CONFIG.PCW_MIO_29_SLEW {slow} \ +CONFIG.PCW_MIO_2_DIRECTION {inout} \ +CONFIG.PCW_MIO_2_IOTYPE {LVCMOS 3.3V} \ +CONFIG.PCW_MIO_2_PULLUP {disabled} \ +CONFIG.PCW_MIO_2_SLEW {slow} \ +CONFIG.PCW_MIO_30_DIRECTION {out} \ +CONFIG.PCW_MIO_30_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_30_PULLUP {enabled} \ +CONFIG.PCW_MIO_30_SLEW {slow} \ +CONFIG.PCW_MIO_31_DIRECTION {in} \ +CONFIG.PCW_MIO_31_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_31_PULLUP {enabled} \ +CONFIG.PCW_MIO_31_SLEW {slow} \ +CONFIG.PCW_MIO_32_DIRECTION {inout} \ +CONFIG.PCW_MIO_32_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_32_PULLUP {enabled} \ +CONFIG.PCW_MIO_32_SLEW {slow} \ +CONFIG.PCW_MIO_33_DIRECTION {inout} \ +CONFIG.PCW_MIO_33_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_33_PULLUP {enabled} \ +CONFIG.PCW_MIO_33_SLEW {slow} \ +CONFIG.PCW_MIO_34_DIRECTION {inout} \ +CONFIG.PCW_MIO_34_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_34_PULLUP {enabled} \ +CONFIG.PCW_MIO_34_SLEW {slow} \ +CONFIG.PCW_MIO_35_DIRECTION {inout} \ +CONFIG.PCW_MIO_35_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_35_PULLUP {enabled} \ +CONFIG.PCW_MIO_35_SLEW {slow} \ +CONFIG.PCW_MIO_36_DIRECTION {in} \ +CONFIG.PCW_MIO_36_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_36_PULLUP {enabled} \ +CONFIG.PCW_MIO_36_SLEW {slow} \ +CONFIG.PCW_MIO_37_DIRECTION {inout} \ +CONFIG.PCW_MIO_37_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_37_PULLUP {enabled} \ +CONFIG.PCW_MIO_37_SLEW {slow} \ +CONFIG.PCW_MIO_38_DIRECTION {inout} \ +CONFIG.PCW_MIO_38_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_38_PULLUP {enabled} \ +CONFIG.PCW_MIO_38_SLEW {slow} \ +CONFIG.PCW_MIO_39_DIRECTION {inout} \ +CONFIG.PCW_MIO_39_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_39_PULLUP {enabled} \ +CONFIG.PCW_MIO_39_SLEW {slow} \ +CONFIG.PCW_MIO_3_DIRECTION {inout} \ +CONFIG.PCW_MIO_3_IOTYPE {LVCMOS 3.3V} \ +CONFIG.PCW_MIO_3_PULLUP {disabled} \ +CONFIG.PCW_MIO_3_SLEW {slow} \ +CONFIG.PCW_MIO_40_DIRECTION {inout} \ +CONFIG.PCW_MIO_40_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_40_PULLUP {enabled} \ +CONFIG.PCW_MIO_40_SLEW {slow} \ +CONFIG.PCW_MIO_41_DIRECTION {inout} \ +CONFIG.PCW_MIO_41_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_41_PULLUP {enabled} \ +CONFIG.PCW_MIO_41_SLEW {slow} \ +CONFIG.PCW_MIO_42_DIRECTION {inout} \ +CONFIG.PCW_MIO_42_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_42_PULLUP {enabled} \ +CONFIG.PCW_MIO_42_SLEW {slow} \ +CONFIG.PCW_MIO_43_DIRECTION {inout} \ +CONFIG.PCW_MIO_43_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_43_PULLUP {enabled} \ +CONFIG.PCW_MIO_43_SLEW {slow} \ +CONFIG.PCW_MIO_44_DIRECTION {inout} \ +CONFIG.PCW_MIO_44_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_44_PULLUP {enabled} \ +CONFIG.PCW_MIO_44_SLEW {slow} \ +CONFIG.PCW_MIO_45_DIRECTION {inout} \ +CONFIG.PCW_MIO_45_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_45_PULLUP {enabled} \ +CONFIG.PCW_MIO_45_SLEW {slow} \ +CONFIG.PCW_MIO_46_DIRECTION {out} \ +CONFIG.PCW_MIO_46_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_46_PULLUP {enabled} \ +CONFIG.PCW_MIO_46_SLEW {slow} \ +CONFIG.PCW_MIO_47_DIRECTION {in} \ +CONFIG.PCW_MIO_47_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_47_PULLUP {enabled} \ +CONFIG.PCW_MIO_47_SLEW {slow} \ +CONFIG.PCW_MIO_48_DIRECTION {inout} \ +CONFIG.PCW_MIO_48_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_48_PULLUP {enabled} \ +CONFIG.PCW_MIO_48_SLEW {slow} \ +CONFIG.PCW_MIO_49_DIRECTION {inout} \ +CONFIG.PCW_MIO_49_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_49_PULLUP {enabled} \ +CONFIG.PCW_MIO_49_SLEW {slow} \ +CONFIG.PCW_MIO_4_DIRECTION {inout} \ +CONFIG.PCW_MIO_4_IOTYPE {LVCMOS 3.3V} \ +CONFIG.PCW_MIO_4_PULLUP {disabled} \ +CONFIG.PCW_MIO_4_SLEW {slow} \ +CONFIG.PCW_MIO_50_DIRECTION {inout} \ +CONFIG.PCW_MIO_50_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_50_PULLUP {enabled} \ +CONFIG.PCW_MIO_50_SLEW {slow} \ +CONFIG.PCW_MIO_51_DIRECTION {inout} \ +CONFIG.PCW_MIO_51_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_51_PULLUP {enabled} \ +CONFIG.PCW_MIO_51_SLEW {slow} \ +CONFIG.PCW_MIO_52_DIRECTION {out} \ +CONFIG.PCW_MIO_52_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_52_PULLUP {enabled} \ +CONFIG.PCW_MIO_52_SLEW {slow} \ +CONFIG.PCW_MIO_53_DIRECTION {inout} \ +CONFIG.PCW_MIO_53_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_53_PULLUP {enabled} \ +CONFIG.PCW_MIO_53_SLEW {slow} \ +CONFIG.PCW_MIO_5_DIRECTION {inout} \ +CONFIG.PCW_MIO_5_IOTYPE {LVCMOS 3.3V} \ +CONFIG.PCW_MIO_5_PULLUP {disabled} \ +CONFIG.PCW_MIO_5_SLEW {slow} \ +CONFIG.PCW_MIO_6_DIRECTION {out} \ +CONFIG.PCW_MIO_6_IOTYPE {LVCMOS 3.3V} \ +CONFIG.PCW_MIO_6_PULLUP {disabled} \ +CONFIG.PCW_MIO_6_SLEW {slow} \ +CONFIG.PCW_MIO_7_DIRECTION {out} \ +CONFIG.PCW_MIO_7_IOTYPE {LVCMOS 3.3V} \ +CONFIG.PCW_MIO_7_PULLUP {disabled} \ +CONFIG.PCW_MIO_7_SLEW {slow} \ +CONFIG.PCW_MIO_8_DIRECTION {out} \ +CONFIG.PCW_MIO_8_IOTYPE {LVCMOS 3.3V} \ +CONFIG.PCW_MIO_8_PULLUP {disabled} \ +CONFIG.PCW_MIO_8_SLEW {slow} \ +CONFIG.PCW_MIO_9_DIRECTION {out} \ +CONFIG.PCW_MIO_9_IOTYPE {LVCMOS 3.3V} \ +CONFIG.PCW_MIO_9_PULLUP {enabled} \ +CONFIG.PCW_MIO_9_SLEW {slow} \ +CONFIG.PCW_MIO_PRIMITIVE {54} \ +CONFIG.PCW_MIO_TREE_PERIPHERALS {GPIO#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO#Quad SPI Flash#ENET Reset#GPIO#GPIO#GPIO#GPIO#UART 0#UART 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#USB Reset#SD 0#GPIO#GPIO#GPIO#GPIO#Enet 0#Enet 0} \ +CONFIG.PCW_MIO_TREE_SIGNALS {gpio[0]#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]#qspi0_sclk#gpio[7]#qspi_fbclk#reset#gpio[10]#gpio[11]#gpio[12]#gpio[13]#rx#tx#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#clk#cmd#data[0]#data[1]#data[2]#data[3]#reset#cd#gpio[48]#gpio[49]#gpio[50]#gpio[51]#mdc#mdio} \ +CONFIG.PCW_M_AXI_GP0_ENABLE_STATIC_REMAP {0} \ +CONFIG.PCW_M_AXI_GP0_ID_WIDTH {12} \ +CONFIG.PCW_M_AXI_GP0_SUPPORT_NARROW_BURST {0} \ +CONFIG.PCW_M_AXI_GP0_THREAD_ID_WIDTH {12} \ +CONFIG.PCW_M_AXI_GP1_ENABLE_STATIC_REMAP {0} \ +CONFIG.PCW_M_AXI_GP1_ID_WIDTH {12} \ +CONFIG.PCW_M_AXI_GP1_SUPPORT_NARROW_BURST {0} \ +CONFIG.PCW_M_AXI_GP1_THREAD_ID_WIDTH {12} \ +CONFIG.PCW_NAND_CYCLES_T_AR {1} \ +CONFIG.PCW_NAND_CYCLES_T_CLR {1} \ +CONFIG.PCW_NAND_CYCLES_T_RC {11} \ +CONFIG.PCW_NAND_CYCLES_T_REA {1} \ +CONFIG.PCW_NAND_CYCLES_T_RR {1} \ +CONFIG.PCW_NAND_CYCLES_T_WC {11} \ +CONFIG.PCW_NAND_CYCLES_T_WP {1} \ +CONFIG.PCW_NAND_GRP_D8_ENABLE {0} \ +CONFIG.PCW_NAND_PERIPHERAL_ENABLE {0} \ +CONFIG.PCW_NOR_CS0_T_CEOE {1} \ +CONFIG.PCW_NOR_CS0_T_PC {1} \ +CONFIG.PCW_NOR_CS0_T_RC {11} \ +CONFIG.PCW_NOR_CS0_T_TR {1} \ +CONFIG.PCW_NOR_CS0_T_WC {11} \ +CONFIG.PCW_NOR_CS0_T_WP {1} \ +CONFIG.PCW_NOR_CS0_WE_TIME {0} \ +CONFIG.PCW_NOR_CS1_T_CEOE {1} \ +CONFIG.PCW_NOR_CS1_T_PC {1} \ +CONFIG.PCW_NOR_CS1_T_RC {11} \ +CONFIG.PCW_NOR_CS1_T_TR {1} \ +CONFIG.PCW_NOR_CS1_T_WC {11} \ +CONFIG.PCW_NOR_CS1_T_WP {1} \ +CONFIG.PCW_NOR_CS1_WE_TIME {0} \ +CONFIG.PCW_NOR_GRP_A25_ENABLE {0} \ +CONFIG.PCW_NOR_GRP_CS0_ENABLE {0} \ +CONFIG.PCW_NOR_GRP_CS1_ENABLE {0} \ +CONFIG.PCW_NOR_GRP_SRAM_CS0_ENABLE {0} \ +CONFIG.PCW_NOR_GRP_SRAM_CS1_ENABLE {0} \ +CONFIG.PCW_NOR_GRP_SRAM_INT_ENABLE {0} \ +CONFIG.PCW_NOR_PERIPHERAL_ENABLE {0} \ +CONFIG.PCW_NOR_SRAM_CS0_T_CEOE {1} \ +CONFIG.PCW_NOR_SRAM_CS0_T_PC {1} \ +CONFIG.PCW_NOR_SRAM_CS0_T_RC {11} \ +CONFIG.PCW_NOR_SRAM_CS0_T_TR {1} \ +CONFIG.PCW_NOR_SRAM_CS0_T_WC {11} \ +CONFIG.PCW_NOR_SRAM_CS0_T_WP {1} \ +CONFIG.PCW_NOR_SRAM_CS0_WE_TIME {0} \ +CONFIG.PCW_NOR_SRAM_CS1_T_CEOE {1} \ +CONFIG.PCW_NOR_SRAM_CS1_T_PC {1} \ +CONFIG.PCW_NOR_SRAM_CS1_T_RC {11} \ +CONFIG.PCW_NOR_SRAM_CS1_T_TR {1} \ +CONFIG.PCW_NOR_SRAM_CS1_T_WC {11} \ +CONFIG.PCW_NOR_SRAM_CS1_T_WP {1} \ +CONFIG.PCW_NOR_SRAM_CS1_WE_TIME {0} \ +CONFIG.PCW_OVERRIDE_BASIC_CLOCK {0} \ +CONFIG.PCW_P2F_CAN0_INTR {0} \ +CONFIG.PCW_P2F_CAN1_INTR {0} \ +CONFIG.PCW_P2F_CTI_INTR {0} \ +CONFIG.PCW_P2F_DMAC0_INTR {0} \ +CONFIG.PCW_P2F_DMAC1_INTR {0} \ +CONFIG.PCW_P2F_DMAC2_INTR {0} \ +CONFIG.PCW_P2F_DMAC3_INTR {0} \ +CONFIG.PCW_P2F_DMAC4_INTR {0} \ +CONFIG.PCW_P2F_DMAC5_INTR {0} \ +CONFIG.PCW_P2F_DMAC6_INTR {0} \ +CONFIG.PCW_P2F_DMAC7_INTR {0} \ +CONFIG.PCW_P2F_DMAC_ABORT_INTR {0} \ +CONFIG.PCW_P2F_ENET0_INTR {0} \ +CONFIG.PCW_P2F_ENET1_INTR {0} \ +CONFIG.PCW_P2F_GPIO_INTR {0} \ +CONFIG.PCW_P2F_I2C0_INTR {0} \ +CONFIG.PCW_P2F_I2C1_INTR {0} \ +CONFIG.PCW_P2F_QSPI_INTR {0} \ +CONFIG.PCW_P2F_SDIO0_INTR {0} \ +CONFIG.PCW_P2F_SDIO1_INTR {0} \ +CONFIG.PCW_P2F_SMC_INTR {0} \ +CONFIG.PCW_P2F_SPI0_INTR {0} \ +CONFIG.PCW_P2F_SPI1_INTR {0} \ +CONFIG.PCW_P2F_UART0_INTR {0} \ +CONFIG.PCW_P2F_UART1_INTR {0} \ +CONFIG.PCW_P2F_USB0_INTR {0} \ +CONFIG.PCW_P2F_USB1_INTR {0} \ +CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY0 {0.223} \ +CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY1 {0.212} \ +CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY2 {0.085} \ +CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY3 {0.092} \ +CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_0 {0.040} \ +CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_1 {0.058} \ +CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_2 {-0.009} \ +CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_3 {-0.033} \ +CONFIG.PCW_PACKAGE_NAME {clg400} \ +CONFIG.PCW_PCAP_PERIPHERAL_CLKSRC {IO PLL} \ +CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0 {5} \ +CONFIG.PCW_PCAP_PERIPHERAL_FREQMHZ {200} \ +CONFIG.PCW_PERIPHERAL_BOARD_PRESET {None} \ +CONFIG.PCW_PLL_BYPASSMODE_ENABLE {0} \ +CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 3.3V} \ +CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} \ +CONFIG.PCW_PS7_SI_REV {PRODUCTION} \ +CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE {1} \ +CONFIG.PCW_QSPI_GRP_FBCLK_IO {MIO 8} \ +CONFIG.PCW_QSPI_GRP_IO1_ENABLE {0} \ +CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {1} \ +CONFIG.PCW_QSPI_GRP_SINGLE_SS_IO {MIO 1 .. 6} \ +CONFIG.PCW_QSPI_GRP_SS1_ENABLE {0} \ +CONFIG.PCW_QSPI_INTERNAL_HIGHADDRESS {0xFCFFFFFF} \ +CONFIG.PCW_QSPI_PERIPHERAL_CLKSRC {IO PLL} \ +CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0 {5} \ +CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1} \ +CONFIG.PCW_QSPI_PERIPHERAL_FREQMHZ {200} \ +CONFIG.PCW_QSPI_QSPI_IO {MIO 1 .. 6} \ +CONFIG.PCW_SD0_GRP_CD_ENABLE {1} \ +CONFIG.PCW_SD0_GRP_CD_IO {MIO 47} \ +CONFIG.PCW_SD0_GRP_POW_ENABLE {0} \ +CONFIG.PCW_SD0_GRP_WP_ENABLE {0} \ +CONFIG.PCW_SD0_PERIPHERAL_ENABLE {1} \ +CONFIG.PCW_SD0_SD0_IO {MIO 40 .. 45} \ +CONFIG.PCW_SD1_GRP_CD_ENABLE {0} \ +CONFIG.PCW_SD1_GRP_POW_ENABLE {0} \ +CONFIG.PCW_SD1_GRP_WP_ENABLE {0} \ +CONFIG.PCW_SD1_PERIPHERAL_ENABLE {0} \ +CONFIG.PCW_SDIO0_BASEADDR {0xE0100000} \ +CONFIG.PCW_SDIO0_HIGHADDR {0xE0100FFF} \ +CONFIG.PCW_SDIO1_BASEADDR {0xE0101000} \ +CONFIG.PCW_SDIO1_HIGHADDR {0xE0101FFF} \ +CONFIG.PCW_SDIO_PERIPHERAL_CLKSRC {IO PLL} \ +CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0 {20} \ +CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {50} \ +CONFIG.PCW_SDIO_PERIPHERAL_VALID {1} \ +CONFIG.PCW_SMC_CYCLE_T0 {NA} \ +CONFIG.PCW_SMC_CYCLE_T1 {NA} \ +CONFIG.PCW_SMC_CYCLE_T2 {NA} \ +CONFIG.PCW_SMC_CYCLE_T3 {NA} \ +CONFIG.PCW_SMC_CYCLE_T4 {NA} \ +CONFIG.PCW_SMC_CYCLE_T5 {NA} \ +CONFIG.PCW_SMC_CYCLE_T6 {NA} \ +CONFIG.PCW_SMC_PERIPHERAL_CLKSRC {IO PLL} \ +CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0 {1} \ +CONFIG.PCW_SMC_PERIPHERAL_FREQMHZ {100} \ +CONFIG.PCW_SMC_PERIPHERAL_VALID {0} \ +CONFIG.PCW_SPI0_BASEADDR {0xE0006000} \ +CONFIG.PCW_SPI0_GRP_SS0_ENABLE {0} \ +CONFIG.PCW_SPI0_GRP_SS1_ENABLE {0} \ +CONFIG.PCW_SPI0_GRP_SS2_ENABLE {0} \ +CONFIG.PCW_SPI0_HIGHADDR {0xE0006FFF} \ +CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {0} \ +CONFIG.PCW_SPI1_BASEADDR {0xE0007000} \ +CONFIG.PCW_SPI1_GRP_SS0_ENABLE {0} \ +CONFIG.PCW_SPI1_GRP_SS1_ENABLE {0} \ +CONFIG.PCW_SPI1_HIGHADDR {0xE0007FFF} \ +CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {0} \ +CONFIG.PCW_SPI_PERIPHERAL_CLKSRC {IO PLL} \ +CONFIG.PCW_SPI_PERIPHERAL_DIVISOR0 {1} \ +CONFIG.PCW_SPI_PERIPHERAL_FREQMHZ {166.666666} \ +CONFIG.PCW_SPI_PERIPHERAL_VALID {0} \ +CONFIG.PCW_S_AXI_ACP_ARUSER_VAL {31} \ +CONFIG.PCW_S_AXI_ACP_AWUSER_VAL {31} \ +CONFIG.PCW_S_AXI_ACP_ID_WIDTH {3} \ +CONFIG.PCW_S_AXI_GP0_ID_WIDTH {6} \ +CONFIG.PCW_S_AXI_GP1_ID_WIDTH {6} \ +CONFIG.PCW_S_AXI_HP0_DATA_WIDTH {64} \ +CONFIG.PCW_S_AXI_HP0_ID_WIDTH {6} \ +CONFIG.PCW_S_AXI_HP1_DATA_WIDTH {64} \ +CONFIG.PCW_S_AXI_HP1_ID_WIDTH {6} \ +CONFIG.PCW_S_AXI_HP2_DATA_WIDTH {64} \ +CONFIG.PCW_S_AXI_HP2_ID_WIDTH {6} \ +CONFIG.PCW_S_AXI_HP3_DATA_WIDTH {64} \ +CONFIG.PCW_S_AXI_HP3_ID_WIDTH {6} \ +CONFIG.PCW_TPIU_PERIPHERAL_CLKSRC {External} \ +CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0 {1} \ +CONFIG.PCW_TPIU_PERIPHERAL_FREQMHZ {200} \ +CONFIG.PCW_TRACE_BUFFER_CLOCK_DELAY {12} \ +CONFIG.PCW_TRACE_BUFFER_FIFO_SIZE {128} \ +CONFIG.PCW_TRACE_PIPELINE_WIDTH {8} \ +CONFIG.PCW_TTC0_BASEADDR {0xE0104000} \ +CONFIG.PCW_TTC0_CLK0_PERIPHERAL_CLKSRC {CPU_1X} \ +CONFIG.PCW_TTC0_CLK0_PERIPHERAL_DIVISOR0 {1} \ +CONFIG.PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ {133.333333} \ +CONFIG.PCW_TTC0_CLK1_PERIPHERAL_CLKSRC {CPU_1X} \ +CONFIG.PCW_TTC0_CLK1_PERIPHERAL_DIVISOR0 {1} \ +CONFIG.PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ {133.333333} \ +CONFIG.PCW_TTC0_CLK2_PERIPHERAL_CLKSRC {CPU_1X} \ +CONFIG.PCW_TTC0_CLK2_PERIPHERAL_DIVISOR0 {1} \ +CONFIG.PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ {133.333333} \ +CONFIG.PCW_TTC0_HIGHADDR {0xE0104fff} \ +CONFIG.PCW_TTC1_BASEADDR {0xE0105000} \ +CONFIG.PCW_TTC1_CLK0_PERIPHERAL_CLKSRC {CPU_1X} \ +CONFIG.PCW_TTC1_CLK0_PERIPHERAL_DIVISOR0 {1} \ +CONFIG.PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ {133.333333} \ +CONFIG.PCW_TTC1_CLK1_PERIPHERAL_CLKSRC {CPU_1X} \ +CONFIG.PCW_TTC1_CLK1_PERIPHERAL_DIVISOR0 {1} \ +CONFIG.PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ {133.333333} \ +CONFIG.PCW_TTC1_CLK2_PERIPHERAL_CLKSRC {CPU_1X} \ +CONFIG.PCW_TTC1_CLK2_PERIPHERAL_DIVISOR0 {1} \ +CONFIG.PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ {133.333333} \ +CONFIG.PCW_TTC1_HIGHADDR {0xE0105fff} \ +CONFIG.PCW_TTC_PERIPHERAL_FREQMHZ {50} \ +CONFIG.PCW_UART0_BASEADDR {0xE0000000} \ +CONFIG.PCW_UART0_BAUD_RATE {115200} \ +CONFIG.PCW_UART0_GRP_FULL_ENABLE {0} \ +CONFIG.PCW_UART0_HIGHADDR {0xE0000FFF} \ +CONFIG.PCW_UART0_PERIPHERAL_ENABLE {1} \ +CONFIG.PCW_UART0_UART0_IO {MIO 14 .. 15} \ +CONFIG.PCW_UART1_BASEADDR {0xE0001000} \ +CONFIG.PCW_UART1_BAUD_RATE {115200} \ +CONFIG.PCW_UART1_GRP_FULL_ENABLE {0} \ +CONFIG.PCW_UART1_HIGHADDR {0xE0001FFF} \ +CONFIG.PCW_UART1_PERIPHERAL_ENABLE {0} \ +CONFIG.PCW_UART_PERIPHERAL_CLKSRC {IO PLL} \ +CONFIG.PCW_UART_PERIPHERAL_DIVISOR0 {10} \ +CONFIG.PCW_UART_PERIPHERAL_FREQMHZ {100} \ +CONFIG.PCW_UART_PERIPHERAL_VALID {1} \ +CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ {525.000000} \ +CONFIG.PCW_UIPARAM_DDR_ADV_ENABLE {0} \ +CONFIG.PCW_UIPARAM_DDR_AL {0} \ +CONFIG.PCW_UIPARAM_DDR_BANK_ADDR_COUNT {3} \ +CONFIG.PCW_UIPARAM_DDR_BL {8} \ +CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.223} \ +CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.212} \ +CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.085} \ +CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.092} \ +CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {16 Bit} \ +CONFIG.PCW_UIPARAM_DDR_CL {7} \ +CONFIG.PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM {25.8} \ +CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH {80.4535} \ +CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY {160} \ +CONFIG.PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM {25.8} \ +CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH {80.4535} \ +CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY {160} \ +CONFIG.PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM {0} \ +CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH {80.4535} \ +CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY {160} \ +CONFIG.PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM {0} \ +CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH {80.4535} \ +CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY {160} \ +CONFIG.PCW_UIPARAM_DDR_CLOCK_STOP_EN {0} \ +CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT {10} \ +CONFIG.PCW_UIPARAM_DDR_CWL {6} \ +CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY {4096 MBits} \ +CONFIG.PCW_UIPARAM_DDR_DQS_0_LENGTH_MM {15.6} \ +CONFIG.PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH {105.056} \ +CONFIG.PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY {160} \ +CONFIG.PCW_UIPARAM_DDR_DQS_1_LENGTH_MM {18.8} \ +CONFIG.PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH {66.904} \ +CONFIG.PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY {160} \ +CONFIG.PCW_UIPARAM_DDR_DQS_2_LENGTH_MM {0} \ +CONFIG.PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH {89.1715} \ +CONFIG.PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY {160} \ +CONFIG.PCW_UIPARAM_DDR_DQS_3_LENGTH_MM {0} \ +CONFIG.PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH {113.63} \ +CONFIG.PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY {160} \ +CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {0.040} \ +CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {0.058} \ +CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {-0.009} \ +CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {-0.033} \ +CONFIG.PCW_UIPARAM_DDR_DQ_0_LENGTH_MM {16.5} \ +CONFIG.PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH {98.503} \ +CONFIG.PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY {160} \ +CONFIG.PCW_UIPARAM_DDR_DQ_1_LENGTH_MM {18} \ +CONFIG.PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH {68.5855} \ +CONFIG.PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY {160} \ +CONFIG.PCW_UIPARAM_DDR_DQ_2_LENGTH_MM {0} \ +CONFIG.PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH {90.295} \ +CONFIG.PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY {160} \ +CONFIG.PCW_UIPARAM_DDR_DQ_3_LENGTH_MM {0} \ +CONFIG.PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH {103.977} \ +CONFIG.PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY {160} \ +CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH {16 Bits} \ +CONFIG.PCW_UIPARAM_DDR_ECC {Disabled} \ +CONFIG.PCW_UIPARAM_DDR_ENABLE {1} \ +CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ {525} \ +CONFIG.PCW_UIPARAM_DDR_HIGH_TEMP {Normal (0-85)} \ +CONFIG.PCW_UIPARAM_DDR_MEMORY_TYPE {DDR 3} \ +CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41J256M16 RE-125} \ +CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT {15} \ +CONFIG.PCW_UIPARAM_DDR_SPEED_BIN {DDR3_1066F} \ +CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE {1} \ +CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE {1} \ +CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL {1} \ +CONFIG.PCW_UIPARAM_DDR_T_FAW {40.0} \ +CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN {35.0} \ +CONFIG.PCW_UIPARAM_DDR_T_RC {48.91} \ +CONFIG.PCW_UIPARAM_DDR_T_RCD {7} \ +CONFIG.PCW_UIPARAM_DDR_T_RP {7} \ +CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF {0} \ +CONFIG.PCW_UIPARAM_GENERATE_SUMMARY {NA} \ +CONFIG.PCW_USB0_BASEADDR {0xE0102000} \ +CONFIG.PCW_USB0_HIGHADDR {0xE0102fff} \ +CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1} \ +CONFIG.PCW_USB0_PERIPHERAL_FREQMHZ {60} \ +CONFIG.PCW_USB0_RESET_ENABLE {1} \ +CONFIG.PCW_USB0_RESET_IO {MIO 46} \ +CONFIG.PCW_USB0_USB0_IO {MIO 28 .. 39} \ +CONFIG.PCW_USB1_BASEADDR {0xE0103000} \ +CONFIG.PCW_USB1_HIGHADDR {0xE0103fff} \ +CONFIG.PCW_USB1_PERIPHERAL_ENABLE {0} \ +CONFIG.PCW_USB1_PERIPHERAL_FREQMHZ {60} \ +CONFIG.PCW_USB_RESET_ENABLE {1} \ +CONFIG.PCW_USB_RESET_POLARITY {Active Low} \ +CONFIG.PCW_USB_RESET_SELECT {Share reset pin} \ +CONFIG.PCW_USE_AXI_FABRIC_IDLE {0} \ +CONFIG.PCW_USE_AXI_NONSECURE {0} \ +CONFIG.PCW_USE_CORESIGHT {0} \ +CONFIG.PCW_USE_CROSS_TRIGGER {0} \ +CONFIG.PCW_USE_CR_FABRIC {1} \ +CONFIG.PCW_USE_DDR_BYPASS {0} \ +CONFIG.PCW_USE_DEBUG {0} \ +CONFIG.PCW_USE_DEFAULT_ACP_USER_VAL {0} \ +CONFIG.PCW_USE_DMA0 {0} \ +CONFIG.PCW_USE_DMA1 {0} \ +CONFIG.PCW_USE_DMA2 {0} \ +CONFIG.PCW_USE_DMA3 {0} \ +CONFIG.PCW_USE_EXPANDED_IOP {0} \ +CONFIG.PCW_USE_EXPANDED_PS_SLCR_REGISTERS {0} \ +CONFIG.PCW_USE_FABRIC_INTERRUPT {0} \ +CONFIG.PCW_USE_HIGH_OCM {0} \ +CONFIG.PCW_USE_M_AXI_GP0 {1} \ +CONFIG.PCW_USE_M_AXI_GP1 {0} \ +CONFIG.PCW_USE_PROC_EVENT_BUS {0} \ +CONFIG.PCW_USE_PS_SLCR_REGISTERS {0} \ +CONFIG.PCW_USE_S_AXI_ACP {0} \ +CONFIG.PCW_USE_S_AXI_GP0 {0} \ +CONFIG.PCW_USE_S_AXI_GP1 {0} \ +CONFIG.PCW_USE_S_AXI_HP0 {1} \ +CONFIG.PCW_USE_S_AXI_HP1 {1} \ +CONFIG.PCW_USE_S_AXI_HP2 {1} \ +CONFIG.PCW_USE_S_AXI_HP3 {1} \ +CONFIG.PCW_USE_TRACE {0} \ +CONFIG.PCW_USE_TRACE_DATA_EDGE_DETECTOR {0} \ +CONFIG.PCW_VALUE_SILVERSION {3} \ +CONFIG.PCW_WDT_PERIPHERAL_CLKSRC {CPU_1X} \ +CONFIG.PCW_WDT_PERIPHERAL_DIVISOR0 {1} \ +CONFIG.PCW_WDT_PERIPHERAL_FREQMHZ {133.333333} \ + ] $processing_system7_0 + + # Create instance: ps7_0_axi_periph, and set properties + set ps7_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps7_0_axi_periph ] + set_property -dict [ list \ +CONFIG.NUM_MI {8} \ + ] $ps7_0_axi_periph + + # Create instance: rst_ps7_0_100M, and set properties + set rst_ps7_0_100M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ps7_0_100M ] + + # Create instance: triangle_counting_0, and set properties + set triangle_counting_0 [ create_bd_cell -type ip -vlnv xilinx.com:hls:triangle_counting:0.001 triangle_counting_0 ] + + # Create instance: triangle_counting_1, and set properties + set triangle_counting_1 [ create_bd_cell -type ip -vlnv xilinx.com:hls:triangle_counting:0.001 triangle_counting_1 ] + + # Create instance: triangle_counting_2, and set properties + set triangle_counting_2 [ create_bd_cell -type ip -vlnv xilinx.com:hls:triangle_counting:0.001 triangle_counting_2 ] + + # Create instance: triangle_counting_3, and set properties + set triangle_counting_3 [ create_bd_cell -type ip -vlnv xilinx.com:hls:triangle_counting:0.001 triangle_counting_3 ] + + # Create instance: triangle_counting_4, and set properties + set triangle_counting_4 [ create_bd_cell -type ip -vlnv xilinx.com:hls:triangle_counting:0.001 triangle_counting_4 ] + + # Create instance: triangle_counting_5, and set properties + set triangle_counting_5 [ create_bd_cell -type ip -vlnv xilinx.com:hls:triangle_counting:0.001 triangle_counting_5 ] + + # Create instance: triangle_counting_6, and set properties + set triangle_counting_6 [ create_bd_cell -type ip -vlnv xilinx.com:hls:triangle_counting:0.001 triangle_counting_6 ] + + # Create interface connections + connect_bd_intf_net -intf_net axi_smc_1_M00_AXI [get_bd_intf_pins axi_smc_1/M00_AXI] [get_bd_intf_pins processing_system7_0/S_AXI_HP1] + connect_bd_intf_net -intf_net axi_smc_2_M00_AXI [get_bd_intf_pins axi_smc_2/M00_AXI] [get_bd_intf_pins processing_system7_0/S_AXI_HP2] + connect_bd_intf_net -intf_net axi_smc_3_M00_AXI [get_bd_intf_pins axi_smc_3/M00_AXI] [get_bd_intf_pins processing_system7_0/S_AXI_HP3] + connect_bd_intf_net -intf_net axi_smc_M00_AXI [get_bd_intf_pins axi_smc/M00_AXI] [get_bd_intf_pins processing_system7_0/S_AXI_HP0] + connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR] + connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_0/FIXED_IO] + connect_bd_intf_net -intf_net processing_system7_0_M_AXI_GP0 [get_bd_intf_pins processing_system7_0/M_AXI_GP0] [get_bd_intf_pins ps7_0_axi_periph/S00_AXI] + connect_bd_intf_net -intf_net ps7_0_axi_periph_M00_AXI [get_bd_intf_pins ps7_0_axi_periph/M00_AXI] [get_bd_intf_pins triangle_counting_0/s_axi_AXILiteS] + connect_bd_intf_net -intf_net ps7_0_axi_periph_M01_AXI [get_bd_intf_pins ps7_0_axi_periph/M01_AXI] [get_bd_intf_pins triangle_counting_1/s_axi_AXILiteS] + connect_bd_intf_net -intf_net ps7_0_axi_periph_M02_AXI [get_bd_intf_pins ps7_0_axi_periph/M02_AXI] [get_bd_intf_pins triangle_counting_2/s_axi_AXILiteS] + connect_bd_intf_net -intf_net ps7_0_axi_periph_M03_AXI [get_bd_intf_pins ps7_0_axi_periph/M03_AXI] [get_bd_intf_pins triangle_counting_3/s_axi_AXILiteS] + connect_bd_intf_net -intf_net ps7_0_axi_periph_M04_AXI [get_bd_intf_pins ps7_0_axi_periph/M04_AXI] [get_bd_intf_pins triangle_counting_4/s_axi_AXILiteS] + connect_bd_intf_net -intf_net ps7_0_axi_periph_M05_AXI [get_bd_intf_pins ps7_0_axi_periph/M05_AXI] [get_bd_intf_pins triangle_counting_5/s_axi_AXILiteS] + connect_bd_intf_net -intf_net ps7_0_axi_periph_M06_AXI [get_bd_intf_pins ps7_0_axi_periph/M06_AXI] [get_bd_intf_pins triangle_counting_6/s_axi_AXILiteS] + connect_bd_intf_net -intf_net triangle_counting_0_m_axi_EDGE_r [get_bd_intf_pins axi_smc_2/S00_AXI] [get_bd_intf_pins triangle_counting_0/m_axi_EDGE_r] + connect_bd_intf_net -intf_net triangle_counting_0_m_axi_NEIGHBOR [get_bd_intf_pins axi_smc/S00_AXI] [get_bd_intf_pins triangle_counting_0/m_axi_NEIGHBOR] + connect_bd_intf_net -intf_net triangle_counting_0_m_axi_OFFSET [get_bd_intf_pins axi_smc_1/S00_AXI] [get_bd_intf_pins triangle_counting_0/m_axi_OFFSET] + connect_bd_intf_net -intf_net triangle_counting_0_m_axi_PROGRESS [get_bd_intf_pins axi_smc_3/S00_AXI] [get_bd_intf_pins triangle_counting_0/m_axi_PROGRESS] + connect_bd_intf_net -intf_net triangle_counting_1_m_axi_EDGE_r [get_bd_intf_pins axi_smc_2/S01_AXI] [get_bd_intf_pins triangle_counting_1/m_axi_EDGE_r] + connect_bd_intf_net -intf_net triangle_counting_1_m_axi_NEIGHBOR [get_bd_intf_pins axi_smc/S01_AXI] [get_bd_intf_pins triangle_counting_1/m_axi_NEIGHBOR] + connect_bd_intf_net -intf_net triangle_counting_1_m_axi_OFFSET [get_bd_intf_pins axi_smc_1/S01_AXI] [get_bd_intf_pins triangle_counting_1/m_axi_OFFSET] + connect_bd_intf_net -intf_net triangle_counting_1_m_axi_PROGRESS [get_bd_intf_pins axi_smc_3/S01_AXI] [get_bd_intf_pins triangle_counting_1/m_axi_PROGRESS] + connect_bd_intf_net -intf_net triangle_counting_2_m_axi_EDGE_r [get_bd_intf_pins axi_smc_2/S02_AXI] [get_bd_intf_pins triangle_counting_2/m_axi_EDGE_r] + connect_bd_intf_net -intf_net triangle_counting_2_m_axi_NEIGHBOR [get_bd_intf_pins axi_smc/S02_AXI] [get_bd_intf_pins triangle_counting_2/m_axi_NEIGHBOR] + connect_bd_intf_net -intf_net triangle_counting_2_m_axi_OFFSET [get_bd_intf_pins axi_smc_1/S02_AXI] [get_bd_intf_pins triangle_counting_2/m_axi_OFFSET] + connect_bd_intf_net -intf_net triangle_counting_2_m_axi_PROGRESS [get_bd_intf_pins axi_smc_3/S02_AXI] [get_bd_intf_pins triangle_counting_2/m_axi_PROGRESS] + connect_bd_intf_net -intf_net triangle_counting_3_m_axi_EDGE_r [get_bd_intf_pins axi_smc_2/S03_AXI] [get_bd_intf_pins triangle_counting_3/m_axi_EDGE_r] + connect_bd_intf_net -intf_net triangle_counting_3_m_axi_NEIGHBOR [get_bd_intf_pins axi_smc/S03_AXI] [get_bd_intf_pins triangle_counting_3/m_axi_NEIGHBOR] + connect_bd_intf_net -intf_net triangle_counting_3_m_axi_OFFSET [get_bd_intf_pins axi_smc_1/S03_AXI] [get_bd_intf_pins triangle_counting_3/m_axi_OFFSET] + connect_bd_intf_net -intf_net triangle_counting_3_m_axi_PROGRESS [get_bd_intf_pins axi_smc_3/S03_AXI] [get_bd_intf_pins triangle_counting_3/m_axi_PROGRESS] + connect_bd_intf_net -intf_net triangle_counting_4_m_axi_EDGE_r [get_bd_intf_pins axi_smc_2/S04_AXI] [get_bd_intf_pins triangle_counting_4/m_axi_EDGE_r] + connect_bd_intf_net -intf_net triangle_counting_4_m_axi_NEIGHBOR [get_bd_intf_pins axi_smc/S04_AXI] [get_bd_intf_pins triangle_counting_4/m_axi_NEIGHBOR] + connect_bd_intf_net -intf_net triangle_counting_4_m_axi_OFFSET [get_bd_intf_pins axi_smc_1/S04_AXI] [get_bd_intf_pins triangle_counting_4/m_axi_OFFSET] + connect_bd_intf_net -intf_net triangle_counting_4_m_axi_PROGRESS [get_bd_intf_pins axi_smc_3/S04_AXI] [get_bd_intf_pins triangle_counting_4/m_axi_PROGRESS] + connect_bd_intf_net -intf_net triangle_counting_5_m_axi_EDGE_r [get_bd_intf_pins axi_smc_2/S05_AXI] [get_bd_intf_pins triangle_counting_5/m_axi_EDGE_r] + connect_bd_intf_net -intf_net triangle_counting_5_m_axi_NEIGHBOR [get_bd_intf_pins axi_smc/S05_AXI] [get_bd_intf_pins triangle_counting_5/m_axi_NEIGHBOR] + connect_bd_intf_net -intf_net triangle_counting_5_m_axi_OFFSET [get_bd_intf_pins axi_smc_1/S05_AXI] [get_bd_intf_pins triangle_counting_5/m_axi_OFFSET] + connect_bd_intf_net -intf_net triangle_counting_5_m_axi_PROGRESS [get_bd_intf_pins axi_smc_3/S05_AXI] [get_bd_intf_pins triangle_counting_5/m_axi_PROGRESS] + connect_bd_intf_net -intf_net triangle_counting_6_m_axi_EDGE_r [get_bd_intf_pins axi_smc_2/S06_AXI] [get_bd_intf_pins triangle_counting_6/m_axi_EDGE_r] + connect_bd_intf_net -intf_net triangle_counting_6_m_axi_NEIGHBOR [get_bd_intf_pins axi_smc/S06_AXI] [get_bd_intf_pins triangle_counting_6/m_axi_NEIGHBOR] + connect_bd_intf_net -intf_net triangle_counting_6_m_axi_OFFSET [get_bd_intf_pins axi_smc_1/S06_AXI] [get_bd_intf_pins triangle_counting_6/m_axi_OFFSET] + connect_bd_intf_net -intf_net triangle_counting_6_m_axi_PROGRESS [get_bd_intf_pins axi_smc_3/S06_AXI] [get_bd_intf_pins triangle_counting_6/m_axi_PROGRESS] + + # Create port connections + connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_pins axi_smc/aclk] [get_bd_pins axi_smc_1/aclk] [get_bd_pins axi_smc_2/aclk] [get_bd_pins axi_smc_3/aclk] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP0_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP1_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP2_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP3_ACLK] [get_bd_pins ps7_0_axi_periph/ACLK] [get_bd_pins ps7_0_axi_periph/M00_ACLK] [get_bd_pins ps7_0_axi_periph/M01_ACLK] [get_bd_pins ps7_0_axi_periph/M02_ACLK] [get_bd_pins ps7_0_axi_periph/M03_ACLK] [get_bd_pins ps7_0_axi_periph/M04_ACLK] [get_bd_pins ps7_0_axi_periph/M05_ACLK] [get_bd_pins ps7_0_axi_periph/M06_ACLK] [get_bd_pins ps7_0_axi_periph/M07_ACLK] [get_bd_pins ps7_0_axi_periph/S00_ACLK] [get_bd_pins rst_ps7_0_100M/slowest_sync_clk] [get_bd_pins triangle_counting_0/ap_clk] [get_bd_pins triangle_counting_1/ap_clk] [get_bd_pins triangle_counting_2/ap_clk] [get_bd_pins triangle_counting_3/ap_clk] [get_bd_pins triangle_counting_4/ap_clk] [get_bd_pins triangle_counting_5/ap_clk] [get_bd_pins triangle_counting_6/ap_clk] + connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins processing_system7_0/FCLK_RESET0_N] [get_bd_pins rst_ps7_0_100M/ext_reset_in] + connect_bd_net -net rst_ps7_0_100M_interconnect_aresetn [get_bd_pins ps7_0_axi_periph/ARESETN] [get_bd_pins rst_ps7_0_100M/interconnect_aresetn] + connect_bd_net -net rst_ps7_0_100M_peripheral_aresetn [get_bd_pins axi_smc/aresetn] [get_bd_pins axi_smc_1/aresetn] [get_bd_pins axi_smc_2/aresetn] [get_bd_pins axi_smc_3/aresetn] [get_bd_pins ps7_0_axi_periph/M00_ARESETN] [get_bd_pins ps7_0_axi_periph/M01_ARESETN] [get_bd_pins ps7_0_axi_periph/M02_ARESETN] [get_bd_pins ps7_0_axi_periph/M03_ARESETN] [get_bd_pins ps7_0_axi_periph/M04_ARESETN] [get_bd_pins ps7_0_axi_periph/M05_ARESETN] [get_bd_pins ps7_0_axi_periph/M06_ARESETN] [get_bd_pins ps7_0_axi_periph/M07_ARESETN] [get_bd_pins ps7_0_axi_periph/S00_ARESETN] [get_bd_pins rst_ps7_0_100M/peripheral_aresetn] [get_bd_pins triangle_counting_0/ap_rst_n] [get_bd_pins triangle_counting_1/ap_rst_n] [get_bd_pins triangle_counting_2/ap_rst_n] [get_bd_pins triangle_counting_3/ap_rst_n] [get_bd_pins triangle_counting_4/ap_rst_n] [get_bd_pins triangle_counting_5/ap_rst_n] [get_bd_pins triangle_counting_6/ap_rst_n] + + # Create address segments + create_bd_addr_seg -range 0x00010000 -offset 0x43C00000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs triangle_counting_0/s_axi_AXILiteS/Reg] SEG_triangle_counting_0_Reg + create_bd_addr_seg -range 0x00010000 -offset 0x43C10000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs triangle_counting_1/s_axi_AXILiteS/Reg] SEG_triangle_counting_1_Reg + create_bd_addr_seg -range 0x00010000 -offset 0x43C20000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs triangle_counting_2/s_axi_AXILiteS/Reg] SEG_triangle_counting_2_Reg + create_bd_addr_seg -range 0x00010000 -offset 0x43C30000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs triangle_counting_3/s_axi_AXILiteS/Reg] SEG_triangle_counting_3_Reg + create_bd_addr_seg -range 0x00010000 -offset 0x43C40000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs triangle_counting_4/s_axi_AXILiteS/Reg] SEG_triangle_counting_4_Reg + create_bd_addr_seg -range 0x00010000 -offset 0x43C50000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs triangle_counting_5/s_axi_AXILiteS/Reg] SEG_triangle_counting_5_Reg + create_bd_addr_seg -range 0x00010000 -offset 0x43C60000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs triangle_counting_6/s_axi_AXILiteS/Reg] SEG_triangle_counting_6_Reg + create_bd_addr_seg -range 0x20000000 -offset 0x00000000 [get_bd_addr_spaces triangle_counting_0/Data_m_axi_NEIGHBOR] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM] SEG_processing_system7_0_HP0_DDR_LOWOCM + create_bd_addr_seg -range 0x20000000 -offset 0x00000000 [get_bd_addr_spaces triangle_counting_0/Data_m_axi_OFFSET] [get_bd_addr_segs processing_system7_0/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_processing_system7_0_HP1_DDR_LOWOCM + create_bd_addr_seg -range 0x20000000 -offset 0x00000000 [get_bd_addr_spaces triangle_counting_0/Data_m_axi_EDGE_r] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM + create_bd_addr_seg -range 0x20000000 -offset 0x00000000 [get_bd_addr_spaces triangle_counting_0/Data_m_axi_PROGRESS] [get_bd_addr_segs processing_system7_0/S_AXI_HP3/HP3_DDR_LOWOCM] SEG_processing_system7_0_HP3_DDR_LOWOCM + create_bd_addr_seg -range 0x20000000 -offset 0x00000000 [get_bd_addr_spaces triangle_counting_1/Data_m_axi_NEIGHBOR] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM] SEG_processing_system7_0_HP0_DDR_LOWOCM + create_bd_addr_seg -range 0x20000000 -offset 0x00000000 [get_bd_addr_spaces triangle_counting_1/Data_m_axi_OFFSET] [get_bd_addr_segs processing_system7_0/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_processing_system7_0_HP1_DDR_LOWOCM + create_bd_addr_seg -range 0x20000000 -offset 0x00000000 [get_bd_addr_spaces triangle_counting_1/Data_m_axi_EDGE_r] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM + create_bd_addr_seg -range 0x20000000 -offset 0x00000000 [get_bd_addr_spaces triangle_counting_1/Data_m_axi_PROGRESS] [get_bd_addr_segs processing_system7_0/S_AXI_HP3/HP3_DDR_LOWOCM] SEG_processing_system7_0_HP3_DDR_LOWOCM + create_bd_addr_seg -range 0x20000000 -offset 0x00000000 [get_bd_addr_spaces triangle_counting_2/Data_m_axi_NEIGHBOR] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM] SEG_processing_system7_0_HP0_DDR_LOWOCM + create_bd_addr_seg -range 0x20000000 -offset 0x00000000 [get_bd_addr_spaces triangle_counting_2/Data_m_axi_OFFSET] [get_bd_addr_segs processing_system7_0/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_processing_system7_0_HP1_DDR_LOWOCM + create_bd_addr_seg -range 0x20000000 -offset 0x00000000 [get_bd_addr_spaces triangle_counting_2/Data_m_axi_EDGE_r] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM + create_bd_addr_seg -range 0x20000000 -offset 0x00000000 [get_bd_addr_spaces triangle_counting_2/Data_m_axi_PROGRESS] [get_bd_addr_segs processing_system7_0/S_AXI_HP3/HP3_DDR_LOWOCM] SEG_processing_system7_0_HP3_DDR_LOWOCM + create_bd_addr_seg -range 0x20000000 -offset 0x00000000 [get_bd_addr_spaces triangle_counting_3/Data_m_axi_NEIGHBOR] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM] SEG_processing_system7_0_HP0_DDR_LOWOCM + create_bd_addr_seg -range 0x20000000 -offset 0x00000000 [get_bd_addr_spaces triangle_counting_3/Data_m_axi_OFFSET] [get_bd_addr_segs processing_system7_0/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_processing_system7_0_HP1_DDR_LOWOCM + create_bd_addr_seg -range 0x20000000 -offset 0x00000000 [get_bd_addr_spaces triangle_counting_3/Data_m_axi_EDGE_r] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM + create_bd_addr_seg -range 0x20000000 -offset 0x00000000 [get_bd_addr_spaces triangle_counting_3/Data_m_axi_PROGRESS] [get_bd_addr_segs processing_system7_0/S_AXI_HP3/HP3_DDR_LOWOCM] SEG_processing_system7_0_HP3_DDR_LOWOCM + create_bd_addr_seg -range 0x20000000 -offset 0x00000000 [get_bd_addr_spaces triangle_counting_4/Data_m_axi_NEIGHBOR] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM] SEG_processing_system7_0_HP0_DDR_LOWOCM + create_bd_addr_seg -range 0x20000000 -offset 0x00000000 [get_bd_addr_spaces triangle_counting_4/Data_m_axi_OFFSET] [get_bd_addr_segs processing_system7_0/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_processing_system7_0_HP1_DDR_LOWOCM + create_bd_addr_seg -range 0x20000000 -offset 0x00000000 [get_bd_addr_spaces triangle_counting_4/Data_m_axi_EDGE_r] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM + create_bd_addr_seg -range 0x20000000 -offset 0x00000000 [get_bd_addr_spaces triangle_counting_4/Data_m_axi_PROGRESS] [get_bd_addr_segs processing_system7_0/S_AXI_HP3/HP3_DDR_LOWOCM] SEG_processing_system7_0_HP3_DDR_LOWOCM + create_bd_addr_seg -range 0x20000000 -offset 0x00000000 [get_bd_addr_spaces triangle_counting_5/Data_m_axi_NEIGHBOR] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM] SEG_processing_system7_0_HP0_DDR_LOWOCM + create_bd_addr_seg -range 0x20000000 -offset 0x00000000 [get_bd_addr_spaces triangle_counting_5/Data_m_axi_OFFSET] [get_bd_addr_segs processing_system7_0/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_processing_system7_0_HP1_DDR_LOWOCM + create_bd_addr_seg -range 0x20000000 -offset 0x00000000 [get_bd_addr_spaces triangle_counting_5/Data_m_axi_EDGE_r] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM + create_bd_addr_seg -range 0x20000000 -offset 0x00000000 [get_bd_addr_spaces triangle_counting_5/Data_m_axi_PROGRESS] [get_bd_addr_segs processing_system7_0/S_AXI_HP3/HP3_DDR_LOWOCM] SEG_processing_system7_0_HP3_DDR_LOWOCM + create_bd_addr_seg -range 0x20000000 -offset 0x00000000 [get_bd_addr_spaces triangle_counting_6/Data_m_axi_NEIGHBOR] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM] SEG_processing_system7_0_HP0_DDR_LOWOCM + create_bd_addr_seg -range 0x20000000 -offset 0x00000000 [get_bd_addr_spaces triangle_counting_6/Data_m_axi_OFFSET] [get_bd_addr_segs processing_system7_0/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_processing_system7_0_HP1_DDR_LOWOCM + create_bd_addr_seg -range 0x20000000 -offset 0x00000000 [get_bd_addr_spaces triangle_counting_6/Data_m_axi_EDGE_r] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM + create_bd_addr_seg -range 0x20000000 -offset 0x00000000 [get_bd_addr_spaces triangle_counting_6/Data_m_axi_PROGRESS] [get_bd_addr_segs processing_system7_0/S_AXI_HP3/HP3_DDR_LOWOCM] SEG_processing_system7_0_HP3_DDR_LOWOCM + + + # Restore current instance + current_bd_instance $oldCurInst + + save_bd_design +} +# End of create_root_design() + + +################################################################## +# MAIN FLOW +################################################################## + +create_root_design "" + + diff --git a/bitstreams/triangle_counting.bit b/bitstreams/triangle_counting.bit new file mode 100644 index 0000000..d7b5217 Binary files /dev/null and b/bitstreams/triangle_counting.bit differ diff --git a/bitstreams/triangle_counting.tcl b/bitstreams/triangle_counting.tcl new file mode 100644 index 0000000..4ce4e44 --- /dev/null +++ b/bitstreams/triangle_counting.tcl @@ -0,0 +1,1012 @@ + +################################################################ +# This is a generated script based on design: hw_platform +# +# Though there are limitations about the generated script, +# the main purpose of this utility is to make learning +# IP Integrator Tcl commands easier. +################################################################ + +namespace eval _tcl { +proc get_script_folder {} { + set script_path [file normalize [info script]] + set script_folder [file dirname $script_path] + return $script_folder +} +} +variable script_folder +set script_folder [_tcl::get_script_folder] + +################################################################ +# Check if script is running in correct Vivado version. +################################################################ +set scripts_vivado_version 2017.2 +set current_vivado_version [version -short] + +if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { + puts "" + catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} + + return 1 +} + +################################################################ +# START +################################################################ + +# To test this script, run the following commands from Vivado Tcl console: +# source hw_platform_script.tcl + +# If there is no project opened, this script will create a +# project, but make sure you do not have an existing project +# <./myproj/project_1.xpr> in the current working folder. + +set list_projs [get_projects -quiet] +if { $list_projs eq "" } { + create_project project_1 myproj -part xc7z020clg400-1 + set_property BOARD_PART www.digilentinc.com:pynq-z1:part0:1.0 [current_project] +} + + +# CHANGE DESIGN NAME HERE +set design_name hw_platform + +# If you do not already have an existing IP Integrator design open, +# you can create a design using the following command: +# create_bd_design $design_name + +# Creating design if needed +set errMsg "" +set nRet 0 + +set cur_design [current_bd_design -quiet] +set list_cells [get_bd_cells -quiet] + +if { ${design_name} eq "" } { + # USE CASES: + # 1) Design_name not set + + set errMsg "Please set the variable to a non-empty value." + set nRet 1 + +} elseif { ${cur_design} ne "" && ${list_cells} eq "" } { + # USE CASES: + # 2): Current design opened AND is empty AND names same. + # 3): Current design opened AND is empty AND names diff; design_name NOT in project. + # 4): Current design opened AND is empty AND names diff; design_name exists in project. + + if { $cur_design ne $design_name } { + common::send_msg_id "BD_TCL-001" "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." + set design_name [get_property NAME $cur_design] + } + common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..." + +} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { + # USE CASES: + # 5) Current design opened AND has components AND same names. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 1 +} elseif { [get_files -quiet ${design_name}.bd] ne "" } { + # USE CASES: + # 6) Current opened design, has components, but diff names, design_name exists in project. + # 7) No opened design, design_name exists in project. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 2 + +} else { + # USE CASES: + # 8) No opened design, design_name not in project. + # 9) Current opened design, has components, but diff names, design_name not in project. + + common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..." + + create_bd_design $design_name + + common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design." + current_bd_design $design_name + +} + +common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable is equal to \"$design_name\"." + +if { $nRet != 0 } { + catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg} + return $nRet +} + +################################################################## +# DESIGN PROCs +################################################################## + + + +# Procedure to create entire design; Provide argument to make +# procedure reusable. If parentCell is "", will use root. +proc create_root_design { parentCell } { + + variable script_folder + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + + # Create interface ports + set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ] + set FIXED_IO [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO ] + + # Create ports + + # Create instance: axi_smc, and set properties + set axi_smc [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_smc ] + set_property -dict [ list \ +CONFIG.NUM_SI {1} \ + ] $axi_smc + + # Create instance: axi_smc_1, and set properties + set axi_smc_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_smc_1 ] + set_property -dict [ list \ +CONFIG.NUM_SI {1} \ + ] $axi_smc_1 + + # Create instance: axi_smc_2, and set properties + set axi_smc_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_smc_2 ] + set_property -dict [ list \ +CONFIG.NUM_SI {1} \ + ] $axi_smc_2 + + # Create instance: axi_smc_3, and set properties + set axi_smc_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_smc_3 ] + set_property -dict [ list \ +CONFIG.NUM_SI {1} \ + ] $axi_smc_3 + + # Create instance: processing_system7_0, and set properties + set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ] + set_property -dict [ list \ +CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {650.000000} \ +CONFIG.PCW_ACT_CAN0_PERIPHERAL_FREQMHZ {23.8095} \ +CONFIG.PCW_ACT_CAN1_PERIPHERAL_FREQMHZ {23.8095} \ +CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ {10.000000} \ +CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.096154} \ +CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {125.000000} \ +CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ {10.000000} \ +CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {100.000000} \ +CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {10.000000} \ +CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ {10.000000} \ +CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ {10.000000} \ +CONFIG.PCW_ACT_I2C_PERIPHERAL_FREQMHZ {50} \ +CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ {200.000000} \ +CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {200.000000} \ +CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {50.000000} \ +CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ {10.000000} \ +CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ {10.000000} \ +CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ {200.000000} \ +CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ {108.333336} \ +CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ {108.333336} \ +CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ {108.333336} \ +CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ {108.333336} \ +CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ {108.333336} \ +CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ {108.333336} \ +CONFIG.PCW_ACT_TTC_PERIPHERAL_FREQMHZ {50} \ +CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {100.000000} \ +CONFIG.PCW_ACT_USB0_PERIPHERAL_FREQMHZ {60} \ +CONFIG.PCW_ACT_USB1_PERIPHERAL_FREQMHZ {60} \ +CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ {108.333336} \ +CONFIG.PCW_APU_CLK_RATIO_ENABLE {6:2:1} \ +CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {650} \ +CONFIG.PCW_ARMPLL_CTRL_FBDIV {26} \ +CONFIG.PCW_CAN0_BASEADDR {0xE0008000} \ +CONFIG.PCW_CAN0_HIGHADDR {0xE0008FFF} \ +CONFIG.PCW_CAN0_PERIPHERAL_CLKSRC {External} \ +CONFIG.PCW_CAN0_PERIPHERAL_FREQMHZ {-1} \ +CONFIG.PCW_CAN1_BASEADDR {0xE0009000} \ +CONFIG.PCW_CAN1_HIGHADDR {0xE0009FFF} \ +CONFIG.PCW_CAN1_PERIPHERAL_CLKSRC {External} \ +CONFIG.PCW_CAN1_PERIPHERAL_FREQMHZ {-1} \ +CONFIG.PCW_CAN_PERIPHERAL_CLKSRC {IO PLL} \ +CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0 {1} \ +CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1 {1} \ +CONFIG.PCW_CAN_PERIPHERAL_FREQMHZ {100} \ +CONFIG.PCW_CAN_PERIPHERAL_VALID {0} \ +CONFIG.PCW_CLK0_FREQ {100000000} \ +CONFIG.PCW_CLK1_FREQ {10000000} \ +CONFIG.PCW_CLK2_FREQ {10000000} \ +CONFIG.PCW_CLK3_FREQ {10000000} \ +CONFIG.PCW_CORE0_FIQ_INTR {0} \ +CONFIG.PCW_CORE0_IRQ_INTR {0} \ +CONFIG.PCW_CORE1_FIQ_INTR {0} \ +CONFIG.PCW_CORE1_IRQ_INTR {0} \ +CONFIG.PCW_CPU_CPU_6X4X_MAX_RANGE {667} \ +CONFIG.PCW_CPU_CPU_PLL_FREQMHZ {1300.000} \ +CONFIG.PCW_CPU_PERIPHERAL_CLKSRC {ARM PLL} \ +CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0 {2} \ +CONFIG.PCW_CRYSTAL_PERIPHERAL_FREQMHZ {50} \ +CONFIG.PCW_DCI_PERIPHERAL_CLKSRC {DDR PLL} \ +CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0 {52} \ +CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1 {2} \ +CONFIG.PCW_DCI_PERIPHERAL_FREQMHZ {10.159} \ +CONFIG.PCW_DDRPLL_CTRL_FBDIV {21} \ +CONFIG.PCW_DDR_DDR_PLL_FREQMHZ {1050.000} \ +CONFIG.PCW_DDR_HPRLPR_QUEUE_PARTITION {HPR(0)/LPR(32)} \ +CONFIG.PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL {15} \ +CONFIG.PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL {2} \ +CONFIG.PCW_DDR_PERIPHERAL_CLKSRC {DDR PLL} \ +CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0 {2} \ +CONFIG.PCW_DDR_PORT0_HPR_ENABLE {0} \ +CONFIG.PCW_DDR_PORT1_HPR_ENABLE {0} \ +CONFIG.PCW_DDR_PORT2_HPR_ENABLE {0} \ +CONFIG.PCW_DDR_PORT3_HPR_ENABLE {0} \ +CONFIG.PCW_DDR_RAM_BASEADDR {0x00100000} \ +CONFIG.PCW_DDR_RAM_HIGHADDR {0x1FFFFFFF} \ +CONFIG.PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL {2} \ +CONFIG.PCW_DM_WIDTH {4} \ +CONFIG.PCW_DQS_WIDTH {4} \ +CONFIG.PCW_DQ_WIDTH {32} \ +CONFIG.PCW_ENET0_BASEADDR {0xE000B000} \ +CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27} \ +CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1} \ +CONFIG.PCW_ENET0_GRP_MDIO_IO {MIO 52 .. 53} \ +CONFIG.PCW_ENET0_HIGHADDR {0xE000BFFF} \ +CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC {IO PLL} \ +CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0 {8} \ +CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1 {1} \ +CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1} \ +CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ {1000 Mbps} \ +CONFIG.PCW_ENET0_RESET_ENABLE {1} \ +CONFIG.PCW_ENET0_RESET_IO {MIO 9} \ +CONFIG.PCW_ENET1_BASEADDR {0xE000C000} \ +CONFIG.PCW_ENET1_GRP_MDIO_ENABLE {0} \ +CONFIG.PCW_ENET1_HIGHADDR {0xE000CFFF} \ +CONFIG.PCW_ENET1_PERIPHERAL_CLKSRC {IO PLL} \ +CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0 {1} \ +CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1 {1} \ +CONFIG.PCW_ENET1_PERIPHERAL_ENABLE {0} \ +CONFIG.PCW_ENET1_PERIPHERAL_FREQMHZ {1000 Mbps} \ +CONFIG.PCW_ENET1_RESET_ENABLE {0} \ +CONFIG.PCW_ENET_RESET_ENABLE {1} \ +CONFIG.PCW_ENET_RESET_POLARITY {Active Low} \ +CONFIG.PCW_ENET_RESET_SELECT {Share reset pin} \ +CONFIG.PCW_EN_4K_TIMER {0} \ +CONFIG.PCW_EN_CAN0 {0} \ +CONFIG.PCW_EN_CAN1 {0} \ +CONFIG.PCW_EN_CLK0_PORT {1} \ +CONFIG.PCW_EN_CLK1_PORT {0} \ +CONFIG.PCW_EN_CLK2_PORT {0} \ +CONFIG.PCW_EN_CLK3_PORT {0} \ +CONFIG.PCW_EN_CLKTRIG0_PORT {0} \ +CONFIG.PCW_EN_CLKTRIG1_PORT {0} \ +CONFIG.PCW_EN_CLKTRIG2_PORT {0} \ +CONFIG.PCW_EN_CLKTRIG3_PORT {0} \ +CONFIG.PCW_EN_DDR {1} \ +CONFIG.PCW_EN_EMIO_CAN0 {0} \ +CONFIG.PCW_EN_EMIO_CAN1 {0} \ +CONFIG.PCW_EN_EMIO_CD_SDIO0 {0} \ +CONFIG.PCW_EN_EMIO_CD_SDIO1 {0} \ +CONFIG.PCW_EN_EMIO_ENET0 {0} \ +CONFIG.PCW_EN_EMIO_ENET1 {0} \ +CONFIG.PCW_EN_EMIO_GPIO {0} \ +CONFIG.PCW_EN_EMIO_I2C0 {0} \ +CONFIG.PCW_EN_EMIO_I2C1 {0} \ +CONFIG.PCW_EN_EMIO_MODEM_UART0 {0} \ +CONFIG.PCW_EN_EMIO_MODEM_UART1 {0} \ +CONFIG.PCW_EN_EMIO_PJTAG {0} \ +CONFIG.PCW_EN_EMIO_SDIO0 {0} \ +CONFIG.PCW_EN_EMIO_SDIO1 {0} \ +CONFIG.PCW_EN_EMIO_SPI0 {0} \ +CONFIG.PCW_EN_EMIO_SPI1 {0} \ +CONFIG.PCW_EN_EMIO_SRAM_INT {0} \ +CONFIG.PCW_EN_EMIO_TRACE {0} \ +CONFIG.PCW_EN_EMIO_TTC0 {0} \ +CONFIG.PCW_EN_EMIO_TTC1 {0} \ +CONFIG.PCW_EN_EMIO_UART0 {0} \ +CONFIG.PCW_EN_EMIO_UART1 {0} \ +CONFIG.PCW_EN_EMIO_WDT {0} \ +CONFIG.PCW_EN_EMIO_WP_SDIO0 {0} \ +CONFIG.PCW_EN_EMIO_WP_SDIO1 {0} \ +CONFIG.PCW_EN_ENET0 {1} \ +CONFIG.PCW_EN_ENET1 {0} \ +CONFIG.PCW_EN_GPIO {1} \ +CONFIG.PCW_EN_I2C0 {0} \ +CONFIG.PCW_EN_I2C1 {0} \ +CONFIG.PCW_EN_MODEM_UART0 {0} \ +CONFIG.PCW_EN_MODEM_UART1 {0} \ +CONFIG.PCW_EN_PJTAG {0} \ +CONFIG.PCW_EN_PTP_ENET0 {0} \ +CONFIG.PCW_EN_PTP_ENET1 {0} \ +CONFIG.PCW_EN_QSPI {1} \ +CONFIG.PCW_EN_RST0_PORT {1} \ +CONFIG.PCW_EN_RST1_PORT {0} \ +CONFIG.PCW_EN_RST2_PORT {0} \ +CONFIG.PCW_EN_RST3_PORT {0} \ +CONFIG.PCW_EN_SDIO0 {1} \ +CONFIG.PCW_EN_SDIO1 {0} \ +CONFIG.PCW_EN_SMC {0} \ +CONFIG.PCW_EN_SPI0 {0} \ +CONFIG.PCW_EN_SPI1 {0} \ +CONFIG.PCW_EN_TRACE {0} \ +CONFIG.PCW_EN_TTC0 {0} \ +CONFIG.PCW_EN_TTC1 {0} \ +CONFIG.PCW_EN_UART0 {1} \ +CONFIG.PCW_EN_UART1 {0} \ +CONFIG.PCW_EN_USB0 {1} \ +CONFIG.PCW_EN_USB1 {0} \ +CONFIG.PCW_EN_WDT {0} \ +CONFIG.PCW_FCLK0_PERIPHERAL_CLKSRC {IO PLL} \ +CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0 {5} \ +CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1 {2} \ +CONFIG.PCW_FCLK1_PERIPHERAL_CLKSRC {IO PLL} \ +CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0 {1} \ +CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1 {1} \ +CONFIG.PCW_FCLK2_PERIPHERAL_CLKSRC {IO PLL} \ +CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0 {1} \ +CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1 {1} \ +CONFIG.PCW_FCLK3_PERIPHERAL_CLKSRC {IO PLL} \ +CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0 {1} \ +CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1 {1} \ +CONFIG.PCW_FCLK_CLK0_BUF {TRUE} \ +CONFIG.PCW_FCLK_CLK1_BUF {FALSE} \ +CONFIG.PCW_FCLK_CLK2_BUF {FALSE} \ +CONFIG.PCW_FCLK_CLK3_BUF {FALSE} \ +CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100} \ +CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {50} \ +CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {50} \ +CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ {50} \ +CONFIG.PCW_FPGA_FCLK0_ENABLE {1} \ +CONFIG.PCW_FPGA_FCLK1_ENABLE {0} \ +CONFIG.PCW_FPGA_FCLK2_ENABLE {0} \ +CONFIG.PCW_FPGA_FCLK3_ENABLE {0} \ +CONFIG.PCW_GPIO_BASEADDR {0xE000A000} \ +CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {0} \ +CONFIG.PCW_GPIO_EMIO_GPIO_WIDTH {64} \ +CONFIG.PCW_GPIO_HIGHADDR {0xE000AFFF} \ +CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} \ +CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO} \ +CONFIG.PCW_GPIO_PERIPHERAL_ENABLE {0} \ +CONFIG.PCW_I2C0_BASEADDR {0xE0004000} \ +CONFIG.PCW_I2C0_HIGHADDR {0xE0004FFF} \ +CONFIG.PCW_I2C1_BASEADDR {0xE0005000} \ +CONFIG.PCW_I2C1_HIGHADDR {0xE0005FFF} \ +CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ {25} \ +CONFIG.PCW_I2C_RESET_POLARITY {Active Low} \ +CONFIG.PCW_IMPORT_BOARD_PRESET {None} \ +CONFIG.PCW_INCLUDE_ACP_TRANS_CHECK {0} \ +CONFIG.PCW_INCLUDE_TRACE_BUFFER {0} \ +CONFIG.PCW_IOPLL_CTRL_FBDIV {20} \ +CONFIG.PCW_IO_IO_PLL_FREQMHZ {1000.000} \ +CONFIG.PCW_IRQ_F2P_INTR {0} \ +CONFIG.PCW_IRQ_F2P_MODE {DIRECT} \ +CONFIG.PCW_MIO_0_DIRECTION {inout} \ +CONFIG.PCW_MIO_0_IOTYPE {LVCMOS 3.3V} \ +CONFIG.PCW_MIO_0_PULLUP {enabled} \ +CONFIG.PCW_MIO_0_SLEW {slow} \ +CONFIG.PCW_MIO_10_DIRECTION {inout} \ +CONFIG.PCW_MIO_10_IOTYPE {LVCMOS 3.3V} \ +CONFIG.PCW_MIO_10_PULLUP {enabled} \ +CONFIG.PCW_MIO_10_SLEW {slow} \ +CONFIG.PCW_MIO_11_DIRECTION {inout} \ +CONFIG.PCW_MIO_11_IOTYPE {LVCMOS 3.3V} \ +CONFIG.PCW_MIO_11_PULLUP {enabled} \ +CONFIG.PCW_MIO_11_SLEW {slow} \ +CONFIG.PCW_MIO_12_DIRECTION {inout} \ +CONFIG.PCW_MIO_12_IOTYPE {LVCMOS 3.3V} \ +CONFIG.PCW_MIO_12_PULLUP {enabled} \ +CONFIG.PCW_MIO_12_SLEW {slow} \ +CONFIG.PCW_MIO_13_DIRECTION {inout} \ +CONFIG.PCW_MIO_13_IOTYPE {LVCMOS 3.3V} \ +CONFIG.PCW_MIO_13_PULLUP {enabled} \ +CONFIG.PCW_MIO_13_SLEW {slow} \ +CONFIG.PCW_MIO_14_DIRECTION {in} \ +CONFIG.PCW_MIO_14_IOTYPE {LVCMOS 3.3V} \ +CONFIG.PCW_MIO_14_PULLUP {enabled} \ +CONFIG.PCW_MIO_14_SLEW {slow} \ +CONFIG.PCW_MIO_15_DIRECTION {out} \ +CONFIG.PCW_MIO_15_IOTYPE {LVCMOS 3.3V} \ +CONFIG.PCW_MIO_15_PULLUP {enabled} \ +CONFIG.PCW_MIO_15_SLEW {slow} \ +CONFIG.PCW_MIO_16_DIRECTION {out} \ +CONFIG.PCW_MIO_16_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_16_PULLUP {enabled} \ +CONFIG.PCW_MIO_16_SLEW {slow} \ +CONFIG.PCW_MIO_17_DIRECTION {out} \ +CONFIG.PCW_MIO_17_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_17_PULLUP {enabled} \ +CONFIG.PCW_MIO_17_SLEW {slow} \ +CONFIG.PCW_MIO_18_DIRECTION {out} \ +CONFIG.PCW_MIO_18_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_18_PULLUP {enabled} \ +CONFIG.PCW_MIO_18_SLEW {slow} \ +CONFIG.PCW_MIO_19_DIRECTION {out} \ +CONFIG.PCW_MIO_19_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_19_PULLUP {enabled} \ +CONFIG.PCW_MIO_19_SLEW {slow} \ +CONFIG.PCW_MIO_1_DIRECTION {out} \ +CONFIG.PCW_MIO_1_IOTYPE {LVCMOS 3.3V} \ +CONFIG.PCW_MIO_1_PULLUP {enabled} \ +CONFIG.PCW_MIO_1_SLEW {slow} \ +CONFIG.PCW_MIO_20_DIRECTION {out} \ +CONFIG.PCW_MIO_20_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_20_PULLUP {enabled} \ +CONFIG.PCW_MIO_20_SLEW {slow} \ +CONFIG.PCW_MIO_21_DIRECTION {out} \ +CONFIG.PCW_MIO_21_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_21_PULLUP {enabled} \ +CONFIG.PCW_MIO_21_SLEW {slow} \ +CONFIG.PCW_MIO_22_DIRECTION {in} \ +CONFIG.PCW_MIO_22_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_22_PULLUP {enabled} \ +CONFIG.PCW_MIO_22_SLEW {slow} \ +CONFIG.PCW_MIO_23_DIRECTION {in} \ +CONFIG.PCW_MIO_23_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_23_PULLUP {enabled} \ +CONFIG.PCW_MIO_23_SLEW {slow} \ +CONFIG.PCW_MIO_24_DIRECTION {in} \ +CONFIG.PCW_MIO_24_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_24_PULLUP {enabled} \ +CONFIG.PCW_MIO_24_SLEW {slow} \ +CONFIG.PCW_MIO_25_DIRECTION {in} \ +CONFIG.PCW_MIO_25_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_25_PULLUP {enabled} \ +CONFIG.PCW_MIO_25_SLEW {slow} \ +CONFIG.PCW_MIO_26_DIRECTION {in} \ +CONFIG.PCW_MIO_26_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_26_PULLUP {enabled} \ +CONFIG.PCW_MIO_26_SLEW {slow} \ +CONFIG.PCW_MIO_27_DIRECTION {in} \ +CONFIG.PCW_MIO_27_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_27_PULLUP {enabled} \ +CONFIG.PCW_MIO_27_SLEW {slow} \ +CONFIG.PCW_MIO_28_DIRECTION {inout} \ +CONFIG.PCW_MIO_28_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_28_PULLUP {enabled} \ +CONFIG.PCW_MIO_28_SLEW {slow} \ +CONFIG.PCW_MIO_29_DIRECTION {in} \ +CONFIG.PCW_MIO_29_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_29_PULLUP {enabled} \ +CONFIG.PCW_MIO_29_SLEW {slow} \ +CONFIG.PCW_MIO_2_DIRECTION {inout} \ +CONFIG.PCW_MIO_2_IOTYPE {LVCMOS 3.3V} \ +CONFIG.PCW_MIO_2_PULLUP {disabled} \ +CONFIG.PCW_MIO_2_SLEW {slow} \ +CONFIG.PCW_MIO_30_DIRECTION {out} \ +CONFIG.PCW_MIO_30_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_30_PULLUP {enabled} \ +CONFIG.PCW_MIO_30_SLEW {slow} \ +CONFIG.PCW_MIO_31_DIRECTION {in} \ +CONFIG.PCW_MIO_31_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_31_PULLUP {enabled} \ +CONFIG.PCW_MIO_31_SLEW {slow} \ +CONFIG.PCW_MIO_32_DIRECTION {inout} \ +CONFIG.PCW_MIO_32_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_32_PULLUP {enabled} \ +CONFIG.PCW_MIO_32_SLEW {slow} \ +CONFIG.PCW_MIO_33_DIRECTION {inout} \ +CONFIG.PCW_MIO_33_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_33_PULLUP {enabled} \ +CONFIG.PCW_MIO_33_SLEW {slow} \ +CONFIG.PCW_MIO_34_DIRECTION {inout} \ +CONFIG.PCW_MIO_34_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_34_PULLUP {enabled} \ +CONFIG.PCW_MIO_34_SLEW {slow} \ +CONFIG.PCW_MIO_35_DIRECTION {inout} \ +CONFIG.PCW_MIO_35_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_35_PULLUP {enabled} \ +CONFIG.PCW_MIO_35_SLEW {slow} \ +CONFIG.PCW_MIO_36_DIRECTION {in} \ +CONFIG.PCW_MIO_36_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_36_PULLUP {enabled} \ +CONFIG.PCW_MIO_36_SLEW {slow} \ +CONFIG.PCW_MIO_37_DIRECTION {inout} \ +CONFIG.PCW_MIO_37_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_37_PULLUP {enabled} \ +CONFIG.PCW_MIO_37_SLEW {slow} \ +CONFIG.PCW_MIO_38_DIRECTION {inout} \ +CONFIG.PCW_MIO_38_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_38_PULLUP {enabled} \ +CONFIG.PCW_MIO_38_SLEW {slow} \ +CONFIG.PCW_MIO_39_DIRECTION {inout} \ +CONFIG.PCW_MIO_39_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_39_PULLUP {enabled} \ +CONFIG.PCW_MIO_39_SLEW {slow} \ +CONFIG.PCW_MIO_3_DIRECTION {inout} \ +CONFIG.PCW_MIO_3_IOTYPE {LVCMOS 3.3V} \ +CONFIG.PCW_MIO_3_PULLUP {disabled} \ +CONFIG.PCW_MIO_3_SLEW {slow} \ +CONFIG.PCW_MIO_40_DIRECTION {inout} \ +CONFIG.PCW_MIO_40_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_40_PULLUP {enabled} \ +CONFIG.PCW_MIO_40_SLEW {slow} \ +CONFIG.PCW_MIO_41_DIRECTION {inout} \ +CONFIG.PCW_MIO_41_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_41_PULLUP {enabled} \ +CONFIG.PCW_MIO_41_SLEW {slow} \ +CONFIG.PCW_MIO_42_DIRECTION {inout} \ +CONFIG.PCW_MIO_42_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_42_PULLUP {enabled} \ +CONFIG.PCW_MIO_42_SLEW {slow} \ +CONFIG.PCW_MIO_43_DIRECTION {inout} \ +CONFIG.PCW_MIO_43_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_43_PULLUP {enabled} \ +CONFIG.PCW_MIO_43_SLEW {slow} \ +CONFIG.PCW_MIO_44_DIRECTION {inout} \ +CONFIG.PCW_MIO_44_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_44_PULLUP {enabled} \ +CONFIG.PCW_MIO_44_SLEW {slow} \ +CONFIG.PCW_MIO_45_DIRECTION {inout} \ +CONFIG.PCW_MIO_45_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_45_PULLUP {enabled} \ +CONFIG.PCW_MIO_45_SLEW {slow} \ +CONFIG.PCW_MIO_46_DIRECTION {out} \ +CONFIG.PCW_MIO_46_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_46_PULLUP {enabled} \ +CONFIG.PCW_MIO_46_SLEW {slow} \ +CONFIG.PCW_MIO_47_DIRECTION {in} \ +CONFIG.PCW_MIO_47_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_47_PULLUP {enabled} \ +CONFIG.PCW_MIO_47_SLEW {slow} \ +CONFIG.PCW_MIO_48_DIRECTION {inout} \ +CONFIG.PCW_MIO_48_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_48_PULLUP {enabled} \ +CONFIG.PCW_MIO_48_SLEW {slow} \ +CONFIG.PCW_MIO_49_DIRECTION {inout} \ +CONFIG.PCW_MIO_49_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_49_PULLUP {enabled} \ +CONFIG.PCW_MIO_49_SLEW {slow} \ +CONFIG.PCW_MIO_4_DIRECTION {inout} \ +CONFIG.PCW_MIO_4_IOTYPE {LVCMOS 3.3V} \ +CONFIG.PCW_MIO_4_PULLUP {disabled} \ +CONFIG.PCW_MIO_4_SLEW {slow} \ +CONFIG.PCW_MIO_50_DIRECTION {inout} \ +CONFIG.PCW_MIO_50_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_50_PULLUP {enabled} \ +CONFIG.PCW_MIO_50_SLEW {slow} \ +CONFIG.PCW_MIO_51_DIRECTION {inout} \ +CONFIG.PCW_MIO_51_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_51_PULLUP {enabled} \ +CONFIG.PCW_MIO_51_SLEW {slow} \ +CONFIG.PCW_MIO_52_DIRECTION {out} \ +CONFIG.PCW_MIO_52_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_52_PULLUP {enabled} \ +CONFIG.PCW_MIO_52_SLEW {slow} \ +CONFIG.PCW_MIO_53_DIRECTION {inout} \ +CONFIG.PCW_MIO_53_IOTYPE {LVCMOS 1.8V} \ +CONFIG.PCW_MIO_53_PULLUP {enabled} \ +CONFIG.PCW_MIO_53_SLEW {slow} \ +CONFIG.PCW_MIO_5_DIRECTION {inout} \ +CONFIG.PCW_MIO_5_IOTYPE {LVCMOS 3.3V} \ +CONFIG.PCW_MIO_5_PULLUP {disabled} \ +CONFIG.PCW_MIO_5_SLEW {slow} \ +CONFIG.PCW_MIO_6_DIRECTION {out} \ +CONFIG.PCW_MIO_6_IOTYPE {LVCMOS 3.3V} \ +CONFIG.PCW_MIO_6_PULLUP {disabled} \ +CONFIG.PCW_MIO_6_SLEW {slow} \ +CONFIG.PCW_MIO_7_DIRECTION {out} \ +CONFIG.PCW_MIO_7_IOTYPE {LVCMOS 3.3V} \ +CONFIG.PCW_MIO_7_PULLUP {disabled} \ +CONFIG.PCW_MIO_7_SLEW {slow} \ +CONFIG.PCW_MIO_8_DIRECTION {out} \ +CONFIG.PCW_MIO_8_IOTYPE {LVCMOS 3.3V} \ +CONFIG.PCW_MIO_8_PULLUP {disabled} \ +CONFIG.PCW_MIO_8_SLEW {slow} \ +CONFIG.PCW_MIO_9_DIRECTION {out} \ +CONFIG.PCW_MIO_9_IOTYPE {LVCMOS 3.3V} \ +CONFIG.PCW_MIO_9_PULLUP {enabled} \ +CONFIG.PCW_MIO_9_SLEW {slow} \ +CONFIG.PCW_MIO_PRIMITIVE {54} \ +CONFIG.PCW_MIO_TREE_PERIPHERALS {GPIO#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO#Quad SPI Flash#ENET Reset#GPIO#GPIO#GPIO#GPIO#UART 0#UART 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#USB Reset#SD 0#GPIO#GPIO#GPIO#GPIO#Enet 0#Enet 0} \ +CONFIG.PCW_MIO_TREE_SIGNALS {gpio[0]#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]#qspi0_sclk#gpio[7]#qspi_fbclk#reset#gpio[10]#gpio[11]#gpio[12]#gpio[13]#rx#tx#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#clk#cmd#data[0]#data[1]#data[2]#data[3]#reset#cd#gpio[48]#gpio[49]#gpio[50]#gpio[51]#mdc#mdio} \ +CONFIG.PCW_M_AXI_GP0_ENABLE_STATIC_REMAP {0} \ +CONFIG.PCW_M_AXI_GP0_ID_WIDTH {12} \ +CONFIG.PCW_M_AXI_GP0_SUPPORT_NARROW_BURST {0} \ +CONFIG.PCW_M_AXI_GP0_THREAD_ID_WIDTH {12} \ +CONFIG.PCW_M_AXI_GP1_ENABLE_STATIC_REMAP {0} \ +CONFIG.PCW_M_AXI_GP1_ID_WIDTH {12} \ +CONFIG.PCW_M_AXI_GP1_SUPPORT_NARROW_BURST {0} \ +CONFIG.PCW_M_AXI_GP1_THREAD_ID_WIDTH {12} \ +CONFIG.PCW_NAND_CYCLES_T_AR {1} \ +CONFIG.PCW_NAND_CYCLES_T_CLR {1} \ +CONFIG.PCW_NAND_CYCLES_T_RC {11} \ +CONFIG.PCW_NAND_CYCLES_T_REA {1} \ +CONFIG.PCW_NAND_CYCLES_T_RR {1} \ +CONFIG.PCW_NAND_CYCLES_T_WC {11} \ +CONFIG.PCW_NAND_CYCLES_T_WP {1} \ +CONFIG.PCW_NAND_GRP_D8_ENABLE {0} \ +CONFIG.PCW_NAND_PERIPHERAL_ENABLE {0} \ +CONFIG.PCW_NOR_CS0_T_CEOE {1} \ +CONFIG.PCW_NOR_CS0_T_PC {1} \ +CONFIG.PCW_NOR_CS0_T_RC {11} \ +CONFIG.PCW_NOR_CS0_T_TR {1} \ +CONFIG.PCW_NOR_CS0_T_WC {11} \ +CONFIG.PCW_NOR_CS0_T_WP {1} \ +CONFIG.PCW_NOR_CS0_WE_TIME {0} \ +CONFIG.PCW_NOR_CS1_T_CEOE {1} \ +CONFIG.PCW_NOR_CS1_T_PC {1} \ +CONFIG.PCW_NOR_CS1_T_RC {11} \ +CONFIG.PCW_NOR_CS1_T_TR {1} \ +CONFIG.PCW_NOR_CS1_T_WC {11} \ +CONFIG.PCW_NOR_CS1_T_WP {1} \ +CONFIG.PCW_NOR_CS1_WE_TIME {0} \ +CONFIG.PCW_NOR_GRP_A25_ENABLE {0} \ +CONFIG.PCW_NOR_GRP_CS0_ENABLE {0} \ +CONFIG.PCW_NOR_GRP_CS1_ENABLE {0} \ +CONFIG.PCW_NOR_GRP_SRAM_CS0_ENABLE {0} \ +CONFIG.PCW_NOR_GRP_SRAM_CS1_ENABLE {0} \ +CONFIG.PCW_NOR_GRP_SRAM_INT_ENABLE {0} \ +CONFIG.PCW_NOR_PERIPHERAL_ENABLE {0} \ +CONFIG.PCW_NOR_SRAM_CS0_T_CEOE {1} \ +CONFIG.PCW_NOR_SRAM_CS0_T_PC {1} \ +CONFIG.PCW_NOR_SRAM_CS0_T_RC {11} \ +CONFIG.PCW_NOR_SRAM_CS0_T_TR {1} \ +CONFIG.PCW_NOR_SRAM_CS0_T_WC {11} \ +CONFIG.PCW_NOR_SRAM_CS0_T_WP {1} \ +CONFIG.PCW_NOR_SRAM_CS0_WE_TIME {0} \ +CONFIG.PCW_NOR_SRAM_CS1_T_CEOE {1} \ +CONFIG.PCW_NOR_SRAM_CS1_T_PC {1} \ +CONFIG.PCW_NOR_SRAM_CS1_T_RC {11} \ +CONFIG.PCW_NOR_SRAM_CS1_T_TR {1} \ +CONFIG.PCW_NOR_SRAM_CS1_T_WC {11} \ +CONFIG.PCW_NOR_SRAM_CS1_T_WP {1} \ +CONFIG.PCW_NOR_SRAM_CS1_WE_TIME {0} \ +CONFIG.PCW_OVERRIDE_BASIC_CLOCK {0} \ +CONFIG.PCW_P2F_CAN0_INTR {0} \ +CONFIG.PCW_P2F_CAN1_INTR {0} \ +CONFIG.PCW_P2F_CTI_INTR {0} \ +CONFIG.PCW_P2F_DMAC0_INTR {0} \ +CONFIG.PCW_P2F_DMAC1_INTR {0} \ +CONFIG.PCW_P2F_DMAC2_INTR {0} \ +CONFIG.PCW_P2F_DMAC3_INTR {0} \ +CONFIG.PCW_P2F_DMAC4_INTR {0} \ +CONFIG.PCW_P2F_DMAC5_INTR {0} \ +CONFIG.PCW_P2F_DMAC6_INTR {0} \ +CONFIG.PCW_P2F_DMAC7_INTR {0} \ +CONFIG.PCW_P2F_DMAC_ABORT_INTR {0} \ +CONFIG.PCW_P2F_ENET0_INTR {0} \ +CONFIG.PCW_P2F_ENET1_INTR {0} \ +CONFIG.PCW_P2F_GPIO_INTR {0} \ +CONFIG.PCW_P2F_I2C0_INTR {0} \ +CONFIG.PCW_P2F_I2C1_INTR {0} \ +CONFIG.PCW_P2F_QSPI_INTR {0} \ +CONFIG.PCW_P2F_SDIO0_INTR {0} \ +CONFIG.PCW_P2F_SDIO1_INTR {0} \ +CONFIG.PCW_P2F_SMC_INTR {0} \ +CONFIG.PCW_P2F_SPI0_INTR {0} \ +CONFIG.PCW_P2F_SPI1_INTR {0} \ +CONFIG.PCW_P2F_UART0_INTR {0} \ +CONFIG.PCW_P2F_UART1_INTR {0} \ +CONFIG.PCW_P2F_USB0_INTR {0} \ +CONFIG.PCW_P2F_USB1_INTR {0} \ +CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY0 {0.223} \ +CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY1 {0.212} \ +CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY2 {0.085} \ +CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY3 {0.092} \ +CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_0 {0.040} \ +CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_1 {0.058} \ +CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_2 {-0.009} \ +CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_3 {-0.033} \ +CONFIG.PCW_PACKAGE_NAME {clg400} \ +CONFIG.PCW_PCAP_PERIPHERAL_CLKSRC {IO PLL} \ +CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0 {5} \ +CONFIG.PCW_PCAP_PERIPHERAL_FREQMHZ {200} \ +CONFIG.PCW_PERIPHERAL_BOARD_PRESET {None} \ +CONFIG.PCW_PLL_BYPASSMODE_ENABLE {0} \ +CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 3.3V} \ +CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} \ +CONFIG.PCW_PS7_SI_REV {PRODUCTION} \ +CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE {1} \ +CONFIG.PCW_QSPI_GRP_FBCLK_IO {MIO 8} \ +CONFIG.PCW_QSPI_GRP_IO1_ENABLE {0} \ +CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {1} \ +CONFIG.PCW_QSPI_GRP_SINGLE_SS_IO {MIO 1 .. 6} \ +CONFIG.PCW_QSPI_GRP_SS1_ENABLE {0} \ +CONFIG.PCW_QSPI_INTERNAL_HIGHADDRESS {0xFCFFFFFF} \ +CONFIG.PCW_QSPI_PERIPHERAL_CLKSRC {IO PLL} \ +CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0 {5} \ +CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1} \ +CONFIG.PCW_QSPI_PERIPHERAL_FREQMHZ {200} \ +CONFIG.PCW_QSPI_QSPI_IO {MIO 1 .. 6} \ +CONFIG.PCW_SD0_GRP_CD_ENABLE {1} \ +CONFIG.PCW_SD0_GRP_CD_IO {MIO 47} \ +CONFIG.PCW_SD0_GRP_POW_ENABLE {0} \ +CONFIG.PCW_SD0_GRP_WP_ENABLE {0} \ +CONFIG.PCW_SD0_PERIPHERAL_ENABLE {1} \ +CONFIG.PCW_SD0_SD0_IO {MIO 40 .. 45} \ +CONFIG.PCW_SD1_GRP_CD_ENABLE {0} \ +CONFIG.PCW_SD1_GRP_POW_ENABLE {0} \ +CONFIG.PCW_SD1_GRP_WP_ENABLE {0} \ +CONFIG.PCW_SD1_PERIPHERAL_ENABLE {0} \ +CONFIG.PCW_SDIO0_BASEADDR {0xE0100000} \ +CONFIG.PCW_SDIO0_HIGHADDR {0xE0100FFF} \ +CONFIG.PCW_SDIO1_BASEADDR {0xE0101000} \ +CONFIG.PCW_SDIO1_HIGHADDR {0xE0101FFF} \ +CONFIG.PCW_SDIO_PERIPHERAL_CLKSRC {IO PLL} \ +CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0 {20} \ +CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {50} \ +CONFIG.PCW_SDIO_PERIPHERAL_VALID {1} \ +CONFIG.PCW_SMC_CYCLE_T0 {NA} \ +CONFIG.PCW_SMC_CYCLE_T1 {NA} \ +CONFIG.PCW_SMC_CYCLE_T2 {NA} \ +CONFIG.PCW_SMC_CYCLE_T3 {NA} \ +CONFIG.PCW_SMC_CYCLE_T4 {NA} \ +CONFIG.PCW_SMC_CYCLE_T5 {NA} \ +CONFIG.PCW_SMC_CYCLE_T6 {NA} \ +CONFIG.PCW_SMC_PERIPHERAL_CLKSRC {IO PLL} \ +CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0 {1} \ +CONFIG.PCW_SMC_PERIPHERAL_FREQMHZ {100} \ +CONFIG.PCW_SMC_PERIPHERAL_VALID {0} \ +CONFIG.PCW_SPI0_BASEADDR {0xE0006000} \ +CONFIG.PCW_SPI0_GRP_SS0_ENABLE {0} \ +CONFIG.PCW_SPI0_GRP_SS1_ENABLE {0} \ +CONFIG.PCW_SPI0_GRP_SS2_ENABLE {0} \ +CONFIG.PCW_SPI0_HIGHADDR {0xE0006FFF} \ +CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {0} \ +CONFIG.PCW_SPI1_BASEADDR {0xE0007000} \ +CONFIG.PCW_SPI1_GRP_SS0_ENABLE {0} \ +CONFIG.PCW_SPI1_GRP_SS1_ENABLE {0} \ +CONFIG.PCW_SPI1_HIGHADDR {0xE0007FFF} \ +CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {0} \ +CONFIG.PCW_SPI_PERIPHERAL_CLKSRC {IO PLL} \ +CONFIG.PCW_SPI_PERIPHERAL_DIVISOR0 {1} \ +CONFIG.PCW_SPI_PERIPHERAL_FREQMHZ {166.666666} \ +CONFIG.PCW_SPI_PERIPHERAL_VALID {0} \ +CONFIG.PCW_S_AXI_ACP_ARUSER_VAL {31} \ +CONFIG.PCW_S_AXI_ACP_AWUSER_VAL {31} \ +CONFIG.PCW_S_AXI_ACP_ID_WIDTH {3} \ +CONFIG.PCW_S_AXI_GP0_ID_WIDTH {6} \ +CONFIG.PCW_S_AXI_GP1_ID_WIDTH {6} \ +CONFIG.PCW_S_AXI_HP0_DATA_WIDTH {64} \ +CONFIG.PCW_S_AXI_HP0_ID_WIDTH {6} \ +CONFIG.PCW_S_AXI_HP1_DATA_WIDTH {64} \ +CONFIG.PCW_S_AXI_HP1_ID_WIDTH {6} \ +CONFIG.PCW_S_AXI_HP2_DATA_WIDTH {64} \ +CONFIG.PCW_S_AXI_HP2_ID_WIDTH {6} \ +CONFIG.PCW_S_AXI_HP3_DATA_WIDTH {64} \ +CONFIG.PCW_S_AXI_HP3_ID_WIDTH {6} \ +CONFIG.PCW_TPIU_PERIPHERAL_CLKSRC {External} \ +CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0 {1} \ +CONFIG.PCW_TPIU_PERIPHERAL_FREQMHZ {200} \ +CONFIG.PCW_TRACE_BUFFER_CLOCK_DELAY {12} \ +CONFIG.PCW_TRACE_BUFFER_FIFO_SIZE {128} \ +CONFIG.PCW_TRACE_PIPELINE_WIDTH {8} \ +CONFIG.PCW_TTC0_BASEADDR {0xE0104000} \ +CONFIG.PCW_TTC0_CLK0_PERIPHERAL_CLKSRC {CPU_1X} \ +CONFIG.PCW_TTC0_CLK0_PERIPHERAL_DIVISOR0 {1} \ +CONFIG.PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ {133.333333} \ +CONFIG.PCW_TTC0_CLK1_PERIPHERAL_CLKSRC {CPU_1X} \ +CONFIG.PCW_TTC0_CLK1_PERIPHERAL_DIVISOR0 {1} \ +CONFIG.PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ {133.333333} \ +CONFIG.PCW_TTC0_CLK2_PERIPHERAL_CLKSRC {CPU_1X} \ +CONFIG.PCW_TTC0_CLK2_PERIPHERAL_DIVISOR0 {1} \ +CONFIG.PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ {133.333333} \ +CONFIG.PCW_TTC0_HIGHADDR {0xE0104fff} \ +CONFIG.PCW_TTC1_BASEADDR {0xE0105000} \ +CONFIG.PCW_TTC1_CLK0_PERIPHERAL_CLKSRC {CPU_1X} \ +CONFIG.PCW_TTC1_CLK0_PERIPHERAL_DIVISOR0 {1} \ +CONFIG.PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ {133.333333} \ +CONFIG.PCW_TTC1_CLK1_PERIPHERAL_CLKSRC {CPU_1X} \ +CONFIG.PCW_TTC1_CLK1_PERIPHERAL_DIVISOR0 {1} \ +CONFIG.PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ {133.333333} \ +CONFIG.PCW_TTC1_CLK2_PERIPHERAL_CLKSRC {CPU_1X} \ +CONFIG.PCW_TTC1_CLK2_PERIPHERAL_DIVISOR0 {1} \ +CONFIG.PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ {133.333333} \ +CONFIG.PCW_TTC1_HIGHADDR {0xE0105fff} \ +CONFIG.PCW_TTC_PERIPHERAL_FREQMHZ {50} \ +CONFIG.PCW_UART0_BASEADDR {0xE0000000} \ +CONFIG.PCW_UART0_BAUD_RATE {115200} \ +CONFIG.PCW_UART0_GRP_FULL_ENABLE {0} \ +CONFIG.PCW_UART0_HIGHADDR {0xE0000FFF} \ +CONFIG.PCW_UART0_PERIPHERAL_ENABLE {1} \ +CONFIG.PCW_UART0_UART0_IO {MIO 14 .. 15} \ +CONFIG.PCW_UART1_BASEADDR {0xE0001000} \ +CONFIG.PCW_UART1_BAUD_RATE {115200} \ +CONFIG.PCW_UART1_GRP_FULL_ENABLE {0} \ +CONFIG.PCW_UART1_HIGHADDR {0xE0001FFF} \ +CONFIG.PCW_UART1_PERIPHERAL_ENABLE {0} \ +CONFIG.PCW_UART_PERIPHERAL_CLKSRC {IO PLL} \ +CONFIG.PCW_UART_PERIPHERAL_DIVISOR0 {10} \ +CONFIG.PCW_UART_PERIPHERAL_FREQMHZ {100} \ +CONFIG.PCW_UART_PERIPHERAL_VALID {1} \ +CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ {525.000000} \ +CONFIG.PCW_UIPARAM_DDR_ADV_ENABLE {0} \ +CONFIG.PCW_UIPARAM_DDR_AL {0} \ +CONFIG.PCW_UIPARAM_DDR_BANK_ADDR_COUNT {3} \ +CONFIG.PCW_UIPARAM_DDR_BL {8} \ +CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.223} \ +CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.212} \ +CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.085} \ +CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.092} \ +CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {16 Bit} \ +CONFIG.PCW_UIPARAM_DDR_CL {7} \ +CONFIG.PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM {25.8} \ +CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH {80.4535} \ +CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY {160} \ +CONFIG.PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM {25.8} \ +CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH {80.4535} \ +CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY {160} \ +CONFIG.PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM {0} \ +CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH {80.4535} \ +CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY {160} \ +CONFIG.PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM {0} \ +CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH {80.4535} \ +CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY {160} \ +CONFIG.PCW_UIPARAM_DDR_CLOCK_STOP_EN {0} \ +CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT {10} \ +CONFIG.PCW_UIPARAM_DDR_CWL {6} \ +CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY {4096 MBits} \ +CONFIG.PCW_UIPARAM_DDR_DQS_0_LENGTH_MM {15.6} \ +CONFIG.PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH {105.056} \ +CONFIG.PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY {160} \ +CONFIG.PCW_UIPARAM_DDR_DQS_1_LENGTH_MM {18.8} \ +CONFIG.PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH {66.904} \ +CONFIG.PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY {160} \ +CONFIG.PCW_UIPARAM_DDR_DQS_2_LENGTH_MM {0} \ +CONFIG.PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH {89.1715} \ +CONFIG.PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY {160} \ +CONFIG.PCW_UIPARAM_DDR_DQS_3_LENGTH_MM {0} \ +CONFIG.PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH {113.63} \ +CONFIG.PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY {160} \ +CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {0.040} \ +CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {0.058} \ +CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {-0.009} \ +CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {-0.033} \ +CONFIG.PCW_UIPARAM_DDR_DQ_0_LENGTH_MM {16.5} \ +CONFIG.PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH {98.503} \ +CONFIG.PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY {160} \ +CONFIG.PCW_UIPARAM_DDR_DQ_1_LENGTH_MM {18} \ +CONFIG.PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH {68.5855} \ +CONFIG.PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY {160} \ +CONFIG.PCW_UIPARAM_DDR_DQ_2_LENGTH_MM {0} \ +CONFIG.PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH {90.295} \ +CONFIG.PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY {160} \ +CONFIG.PCW_UIPARAM_DDR_DQ_3_LENGTH_MM {0} \ +CONFIG.PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH {103.977} \ +CONFIG.PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY {160} \ +CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH {16 Bits} \ +CONFIG.PCW_UIPARAM_DDR_ECC {Disabled} \ +CONFIG.PCW_UIPARAM_DDR_ENABLE {1} \ +CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ {525} \ +CONFIG.PCW_UIPARAM_DDR_HIGH_TEMP {Normal (0-85)} \ +CONFIG.PCW_UIPARAM_DDR_MEMORY_TYPE {DDR 3} \ +CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41J256M16 RE-125} \ +CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT {15} \ +CONFIG.PCW_UIPARAM_DDR_SPEED_BIN {DDR3_1066F} \ +CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE {1} \ +CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE {1} \ +CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL {1} \ +CONFIG.PCW_UIPARAM_DDR_T_FAW {40.0} \ +CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN {35.0} \ +CONFIG.PCW_UIPARAM_DDR_T_RC {48.91} \ +CONFIG.PCW_UIPARAM_DDR_T_RCD {7} \ +CONFIG.PCW_UIPARAM_DDR_T_RP {7} \ +CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF {0} \ +CONFIG.PCW_UIPARAM_GENERATE_SUMMARY {NA} \ +CONFIG.PCW_USB0_BASEADDR {0xE0102000} \ +CONFIG.PCW_USB0_HIGHADDR {0xE0102fff} \ +CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1} \ +CONFIG.PCW_USB0_PERIPHERAL_FREQMHZ {60} \ +CONFIG.PCW_USB0_RESET_ENABLE {1} \ +CONFIG.PCW_USB0_RESET_IO {MIO 46} \ +CONFIG.PCW_USB0_USB0_IO {MIO 28 .. 39} \ +CONFIG.PCW_USB1_BASEADDR {0xE0103000} \ +CONFIG.PCW_USB1_HIGHADDR {0xE0103fff} \ +CONFIG.PCW_USB1_PERIPHERAL_ENABLE {0} \ +CONFIG.PCW_USB1_PERIPHERAL_FREQMHZ {60} \ +CONFIG.PCW_USB_RESET_ENABLE {1} \ +CONFIG.PCW_USB_RESET_POLARITY {Active Low} \ +CONFIG.PCW_USB_RESET_SELECT {Share reset pin} \ +CONFIG.PCW_USE_AXI_FABRIC_IDLE {0} \ +CONFIG.PCW_USE_AXI_NONSECURE {0} \ +CONFIG.PCW_USE_CORESIGHT {0} \ +CONFIG.PCW_USE_CROSS_TRIGGER {0} \ +CONFIG.PCW_USE_CR_FABRIC {1} \ +CONFIG.PCW_USE_DDR_BYPASS {0} \ +CONFIG.PCW_USE_DEBUG {0} \ +CONFIG.PCW_USE_DEFAULT_ACP_USER_VAL {0} \ +CONFIG.PCW_USE_DMA0 {0} \ +CONFIG.PCW_USE_DMA1 {0} \ +CONFIG.PCW_USE_DMA2 {0} \ +CONFIG.PCW_USE_DMA3 {0} \ +CONFIG.PCW_USE_EXPANDED_IOP {0} \ +CONFIG.PCW_USE_EXPANDED_PS_SLCR_REGISTERS {0} \ +CONFIG.PCW_USE_FABRIC_INTERRUPT {0} \ +CONFIG.PCW_USE_HIGH_OCM {0} \ +CONFIG.PCW_USE_M_AXI_GP0 {1} \ +CONFIG.PCW_USE_M_AXI_GP1 {0} \ +CONFIG.PCW_USE_PROC_EVENT_BUS {0} \ +CONFIG.PCW_USE_PS_SLCR_REGISTERS {0} \ +CONFIG.PCW_USE_S_AXI_ACP {0} \ +CONFIG.PCW_USE_S_AXI_GP0 {0} \ +CONFIG.PCW_USE_S_AXI_GP1 {0} \ +CONFIG.PCW_USE_S_AXI_HP0 {1} \ +CONFIG.PCW_USE_S_AXI_HP1 {1} \ +CONFIG.PCW_USE_S_AXI_HP2 {1} \ +CONFIG.PCW_USE_S_AXI_HP3 {1} \ +CONFIG.PCW_USE_TRACE {0} \ +CONFIG.PCW_USE_TRACE_DATA_EDGE_DETECTOR {0} \ +CONFIG.PCW_VALUE_SILVERSION {3} \ +CONFIG.PCW_WDT_PERIPHERAL_CLKSRC {CPU_1X} \ +CONFIG.PCW_WDT_PERIPHERAL_DIVISOR0 {1} \ +CONFIG.PCW_WDT_PERIPHERAL_FREQMHZ {133.333333} \ + ] $processing_system7_0 + + # Create instance: ps7_0_axi_periph, and set properties + set ps7_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps7_0_axi_periph ] + set_property -dict [ list \ +CONFIG.NUM_MI {1} \ + ] $ps7_0_axi_periph + + # Create instance: rst_ps7_0_100M, and set properties + set rst_ps7_0_100M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ps7_0_100M ] + + # Create instance: triangle_counting_0, and set properties + set triangle_counting_0 [ create_bd_cell -type ip -vlnv xilinx.com:hls:triangle_counting:0.001 triangle_counting_0 ] + + set_property -dict [ list \ +CONFIG.NUM_READ_OUTSTANDING {1} \ +CONFIG.NUM_WRITE_OUTSTANDING {1} \ + ] [get_bd_intf_pins /triangle_counting_0/s_axi_AXILiteS] + + # Create interface connections + connect_bd_intf_net -intf_net axi_smc_1_M00_AXI [get_bd_intf_pins axi_smc_1/M00_AXI] [get_bd_intf_pins processing_system7_0/S_AXI_HP1] + connect_bd_intf_net -intf_net axi_smc_2_M00_AXI [get_bd_intf_pins axi_smc_2/M00_AXI] [get_bd_intf_pins processing_system7_0/S_AXI_HP2] + connect_bd_intf_net -intf_net axi_smc_3_M00_AXI [get_bd_intf_pins axi_smc_3/M00_AXI] [get_bd_intf_pins processing_system7_0/S_AXI_HP3] + connect_bd_intf_net -intf_net axi_smc_M00_AXI [get_bd_intf_pins axi_smc/M00_AXI] [get_bd_intf_pins processing_system7_0/S_AXI_HP0] + connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR] + connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_0/FIXED_IO] + connect_bd_intf_net -intf_net processing_system7_0_M_AXI_GP0 [get_bd_intf_pins processing_system7_0/M_AXI_GP0] [get_bd_intf_pins ps7_0_axi_periph/S00_AXI] + connect_bd_intf_net -intf_net ps7_0_axi_periph_M00_AXI [get_bd_intf_pins ps7_0_axi_periph/M00_AXI] [get_bd_intf_pins triangle_counting_0/s_axi_AXILiteS] + connect_bd_intf_net -intf_net triangle_counting_0_m_axi_EDGE_r [get_bd_intf_pins axi_smc_2/S00_AXI] [get_bd_intf_pins triangle_counting_0/m_axi_EDGE_r] + connect_bd_intf_net -intf_net triangle_counting_0_m_axi_NEIGHBOR [get_bd_intf_pins axi_smc/S00_AXI] [get_bd_intf_pins triangle_counting_0/m_axi_NEIGHBOR] + connect_bd_intf_net -intf_net triangle_counting_0_m_axi_OFFSET [get_bd_intf_pins axi_smc_1/S00_AXI] [get_bd_intf_pins triangle_counting_0/m_axi_OFFSET] + connect_bd_intf_net -intf_net triangle_counting_0_m_axi_PROGRESS [get_bd_intf_pins axi_smc_3/S00_AXI] [get_bd_intf_pins triangle_counting_0/m_axi_PROGRESS] + + # Create port connections + connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_pins axi_smc/aclk] [get_bd_pins axi_smc_1/aclk] [get_bd_pins axi_smc_2/aclk] [get_bd_pins axi_smc_3/aclk] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP0_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP1_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP2_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP3_ACLK] [get_bd_pins ps7_0_axi_periph/ACLK] [get_bd_pins ps7_0_axi_periph/M00_ACLK] [get_bd_pins ps7_0_axi_periph/S00_ACLK] [get_bd_pins rst_ps7_0_100M/slowest_sync_clk] [get_bd_pins triangle_counting_0/ap_clk] + connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins processing_system7_0/FCLK_RESET0_N] [get_bd_pins rst_ps7_0_100M/ext_reset_in] + connect_bd_net -net rst_ps7_0_100M_interconnect_aresetn [get_bd_pins ps7_0_axi_periph/ARESETN] [get_bd_pins rst_ps7_0_100M/interconnect_aresetn] + connect_bd_net -net rst_ps7_0_100M_peripheral_aresetn [get_bd_pins axi_smc/aresetn] [get_bd_pins axi_smc_1/aresetn] [get_bd_pins axi_smc_2/aresetn] [get_bd_pins axi_smc_3/aresetn] [get_bd_pins ps7_0_axi_periph/M00_ARESETN] [get_bd_pins ps7_0_axi_periph/S00_ARESETN] [get_bd_pins rst_ps7_0_100M/peripheral_aresetn] [get_bd_pins triangle_counting_0/ap_rst_n] + + # Create address segments + create_bd_addr_seg -range 0x00010000 -offset 0x43C00000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs triangle_counting_0/s_axi_AXILiteS/Reg] SEG_triangle_counting_0_Reg + create_bd_addr_seg -range 0x20000000 -offset 0x00000000 [get_bd_addr_spaces triangle_counting_0/Data_m_axi_NEIGHBOR] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM] SEG_processing_system7_0_HP0_DDR_LOWOCM + create_bd_addr_seg -range 0x20000000 -offset 0x00000000 [get_bd_addr_spaces triangle_counting_0/Data_m_axi_OFFSET] [get_bd_addr_segs processing_system7_0/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_processing_system7_0_HP1_DDR_LOWOCM + create_bd_addr_seg -range 0x20000000 -offset 0x00000000 [get_bd_addr_spaces triangle_counting_0/Data_m_axi_EDGE_r] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM + create_bd_addr_seg -range 0x20000000 -offset 0x00000000 [get_bd_addr_spaces triangle_counting_0/Data_m_axi_PROGRESS] [get_bd_addr_segs processing_system7_0/S_AXI_HP3/HP3_DDR_LOWOCM] SEG_processing_system7_0_HP3_DDR_LOWOCM + + + # Restore current instance + current_bd_instance $oldCurInst + + save_bd_design +} +# End of create_root_design() + + +################################################################## +# MAIN FLOW +################################################################## + +create_root_design "" + +