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| 1 | +// Copyright (C) 2015 |
| 2 | +// Author [email protected] (Muzaffer Kal) |
| 3 | +// This module implements an AXI3 slave BFM |
| 4 | + |
| 5 | +module axi3_slave_bfm |
| 6 | + #(slave_name = "slave", |
| 7 | + data_bus_width = 32, |
| 8 | + address_bus_width = 32, |
| 9 | + id_bus_width = 3, |
| 10 | + slave_base_address = 0, |
| 11 | + slave_memory_size = 0, |
| 12 | + max_outstanding_transactions = 4, |
| 13 | + memory_model_mode = 0, |
| 14 | + exclusive_access_supported = 0, |
| 15 | + axi_rsp_width = 2, |
| 16 | + axi_len_width = 4, |
| 17 | + axi_qos_width = 4, |
| 18 | + axi_lock_width = 2, |
| 19 | + axi_size_width = 3, |
| 20 | + axi_prot_width = 3, |
| 21 | + axi_brst_width = 3, |
| 22 | + axi_burst_len = 16, |
| 23 | + max_burst_bytes_width = 8, |
| 24 | + max_wr_outstanding_transactions = 8, |
| 25 | + axi_brst_type_width = 3, |
| 26 | + axi_cache_width = 4 |
| 27 | + ) |
| 28 | + ( |
| 29 | + input ACLK, |
| 30 | + input ARESETn, |
| 31 | + output logic ARREADY, |
| 32 | + output logic AWREADY, |
| 33 | + output logic BVALID, |
| 34 | + output logic RLAST, |
| 35 | + output logic RVALID, |
| 36 | + output logic WREADY, |
| 37 | + output logic [axi_rsp_width-1:0] BRESP, |
| 38 | + output logic [axi_rsp_width-1:0] RRESP, |
| 39 | + output logic [data_bus_width-1:0] RDATA, |
| 40 | + output logic [id_bus_width-1:0] BID, |
| 41 | + output logic [id_bus_width-1:0] RID, |
| 42 | + input ARVALID, |
| 43 | + input AWVALID, |
| 44 | + input BREADY, |
| 45 | + input RREADY, |
| 46 | + input WLAST, |
| 47 | + input WVALID, |
| 48 | + input [axi_brst_type_width-1:0] ARBURST, |
| 49 | + input [axi_lock_width-1:0] ARLOCK, |
| 50 | + input [axi_size_width-1:0] ARSIZE, |
| 51 | + input [axi_brst_type_width-1:0] AWBURST, |
| 52 | + input [axi_lock_width-1:0] AWLOCK, |
| 53 | + input [axi_size_width-1:0] AWSIZE, |
| 54 | + input [axi_prot_width-1:0] ARPROT, |
| 55 | + input [axi_prot_width-1:0] AWPROT, |
| 56 | + input [address_bus_width-1:0] ARADDR, |
| 57 | + input [address_bus_width-1:0] AWADDR, |
| 58 | + input [data_bus_width-1:0] WDATA, |
| 59 | + input [axi_cache_width-1:0] ARCACHE, |
| 60 | + input [axi_cache_width-1:0] ARLEN, |
| 61 | + input [axi_qos_width-1:0] ARQOS, |
| 62 | + input [axi_cache_width-1:0] AWCACHE, |
| 63 | + input [axi_len_width-1:0] AWLEN, |
| 64 | + input [axi_qos_width-1:0] AWQOS, |
| 65 | + input [(data_bus_width/8)-1:0] WSTRB, |
| 66 | + input [id_bus_width-1:0] ARID, |
| 67 | + input [id_bus_width-1:0] AWID, |
| 68 | + input [id_bus_width-1:0] WID |
| 69 | + ); |
| 70 | + integer STOP_ON_ERROR; |
| 71 | + integer RESPONSE_TIMEOUT; |
| 72 | + |
| 73 | + assign ARREADY = 0; |
| 74 | + assign AWREADY = 0; |
| 75 | + assign BVALID = 0; |
| 76 | + assign RLAST = 0; |
| 77 | + assign RVALID = 0; |
| 78 | + assign WREADY = 0; |
| 79 | + assign BRESP = 0; |
| 80 | + assign RRESP = 0; |
| 81 | + assign RDATA = 0; |
| 82 | + assign BID = 0; |
| 83 | + assign RID = 0; |
| 84 | + |
| 85 | + task set_stop_on_error; |
| 86 | + input LEVEL; |
| 87 | + begin |
| 88 | + STOP_ON_ERROR = LEVEL; |
| 89 | + end |
| 90 | + endtask |
| 91 | + task automatic set_channel_level_info; |
| 92 | + input LEVEL; |
| 93 | + $display("SLV: set_channel_level_info: %d", LEVEL); |
| 94 | + endtask |
| 95 | + task automatic set_function_level_info; |
| 96 | + input LEVEL; |
| 97 | + $display("SLV: set_function_level_info: %d", LEVEL); |
| 98 | + endtask |
| 99 | + task automatic set_disable_reset_value_checks; |
| 100 | + input LEVEL; |
| 101 | + $display("SLV: set_disable_reset_value_checks: %d", LEVEL); |
| 102 | + endtask |
| 103 | + task automatic RECEIVE_WRITE_ADDRESS; |
| 104 | + input LEVEL; |
| 105 | + input id_invalid; |
| 106 | + input [address_bus_width-1:0] awaddr; |
| 107 | + input [axi_len_width-1:0] awlen; |
| 108 | + input [axi_size_width-1:0] awsize; |
| 109 | + input [axi_brst_width-1:0] awbrst; |
| 110 | + input [axi_lock_width-1:0] awlock; |
| 111 | + input [axi_cache_width-1:0] awcache; |
| 112 | + input [axi_prot_width-1:0] awprot; |
| 113 | + input [id_bus_width-1:0] awid; |
| 114 | + $display("SLV: RECEIVE_WRITE_ADDRESS: %d", LEVEL); |
| 115 | + endtask |
| 116 | + task automatic RECEIVE_READ_ADDRESS; |
| 117 | + input LEVEL; |
| 118 | + input id_invalid; |
| 119 | + input [address_bus_width-1:0] araddr; |
| 120 | + input [axi_len_width-1:0] arlen; |
| 121 | + input [axi_size_width-1:0] arsize; |
| 122 | + input [axi_brst_width-1:0] arbrst; |
| 123 | + input [axi_lock_width-1:0] arlock; |
| 124 | + input [axi_cache_width-1:0] arcache; |
| 125 | + input [axi_prot_width-1:0] arprot; |
| 126 | + input [id_bus_width-1:0] arid; |
| 127 | + $display("SLV: RECEIVE_READ_ADDRESS %d", LEVEL); |
| 128 | + endtask |
| 129 | + task automatic RECEIVE_WRITE_BURST_NO_CHECKS; |
| 130 | + input [id_bus_width-1:0] wid; |
| 131 | + //output [(data_bus_width*axi_burst_len)-1:0] burst_data [0:max_wr_outstanding_transactions-1]; |
| 132 | + output [(max_wr_outstanding_transactions*data_bus_width*axi_burst_len)-1:0] burst_data; |
| 133 | + //output [max_burst_bytes_width:0] burst_valid_bytes [0:max_wr_outstanding_transactions-1]; |
| 134 | + output [max_wr_outstanding_transactions*max_burst_bytes_width:0] burst_valid_bytes; |
| 135 | + $display("SLV: RECEIVE_WRITE_BURST_NO_CHECKS: %d", wid); |
| 136 | + endtask |
| 137 | + task automatic SEND_WRITE_RESPONSE; |
| 138 | + input [id_bus_width-1:0] wid; |
| 139 | + output [axi_rsp_width-1:0] bresp; |
| 140 | + $display("SLV: SEND_WRITE_RESPONSE: %d", wid); |
| 141 | + endtask |
| 142 | + task automatic SEND_READ_BURST_RESP_CTRL; |
| 143 | + input [id_bus_width-1:0] arid; |
| 144 | + input [address_bus_width-1:0] araddr; |
| 145 | + input [axi_len_width-1:0] arlen; |
| 146 | + input [axi_size_width-1:0] arsize; |
| 147 | + input [axi_brst_width-1:0] arbrst; |
| 148 | + input [axi_brst_width-1:0] data; |
| 149 | + input [axi_brst_width-1:0] resp; |
| 150 | + $display("SLV: SEND_READ_BURST_RESP_CTRL: %d", arid); |
| 151 | + endtask |
| 152 | +endmodule |
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