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soufianekhiatsoufianekhiat
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Fix comment and mismatch naming
1 parent bc85661 commit 8f17c7d

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7 files changed

+46
-46
lines changed

7 files changed

+46
-46
lines changed

‎src/CodeGen_D3D12Compute_Dev.cpp‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -193,7 +193,7 @@ string CodeGen_D3D12Compute_Dev::CodeGen_D3D12Compute_C::print_type_maybe_storag
193193
oss << "double";
194194
} else {
195195
user_error << "HLSL SM 5.1 does not support 64-bit float. "
196-
<< "Use target feature d3d12compute_sm60 or higher.\n";
196+
<< "Use target feature hlsl_sm60 or higher.\n";
197197
oss << "double";
198198
}
199199
break;
@@ -267,7 +267,7 @@ string CodeGen_D3D12Compute_Dev::CodeGen_D3D12Compute_C::print_type_maybe_storag
267267
}
268268
} else {
269269
user_error << "HLSL SM 5.1 does not support 64-bit integers. "
270-
<< "Use target feature d3d12compute_sm60 or higher.\n";
270+
<< "Use target feature hlsl_sm60 or higher.\n";
271271
}
272272
break;
273273
default:
@@ -297,7 +297,7 @@ string CodeGen_D3D12Compute_Dev::CodeGen_D3D12Compute_C::print_type_maybe_storag
297297
oss << "vector<" << scalar << ", " << type.lanes() << ">";
298298
} else {
299299
user_error << "Unsupported vector width in HLSL: " << type << ". "
300-
<< "Vectors wider than 4 elements require d3d12compute_sm69.\n";
300+
<< "Vectors wider than 4 elements require hlsl_sm69.\n";
301301
}
302302
break;
303303
}
@@ -948,7 +948,7 @@ void CodeGen_D3D12Compute_Dev::CodeGen_D3D12Compute_C::visit(const Store *op) {
948948
} else if (is_atomic_add) {
949949
user_assert(false)
950950
<< "D3D12Compute: float atomic add requires SM 6.6+ "
951-
<< "(add d3d12compute_sm66 to your target features). "
951+
<< "(add hlsl_sm66 to your target features). "
952952
<< "Type was: " << t << "\n";
953953
} else {
954954
user_assert(false)

‎src/Target.cpp‎

Lines changed: 15 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -776,16 +776,16 @@ const std::map<std::string, Target::Feature> feature_name_map = {
776776
{"trace_realizations", Target::TraceRealizations},
777777
{"trace_pipeline", Target::TracePipeline},
778778
{"d3d12compute", Target::D3D12Compute},
779-
{"d3d12compute_sm60", Target::D3D12ComputeSM60},
780-
{"d3d12compute_sm61", Target::D3D12ComputeSM61},
781-
{"d3d12compute_sm62", Target::D3D12ComputeSM62},
782-
{"d3d12compute_sm63", Target::D3D12ComputeSM63},
783-
{"d3d12compute_sm64", Target::D3D12ComputeSM64},
784-
{"d3d12compute_sm65", Target::D3D12ComputeSM65},
785-
{"d3d12compute_sm66", Target::D3D12ComputeSM66},
786-
{"d3d12compute_sm67", Target::D3D12ComputeSM67},
787-
{"d3d12compute_sm68", Target::D3D12ComputeSM68},
788-
{"d3d12compute_sm69", Target::D3D12ComputeSM69},
779+
{"hlsl_sm60", Target::D3D12ComputeSM60},
780+
{"hlsl_sm61", Target::D3D12ComputeSM61},
781+
{"hlsl_sm62", Target::D3D12ComputeSM62},
782+
{"hlsl_sm63", Target::D3D12ComputeSM63},
783+
{"hlsl_sm64", Target::D3D12ComputeSM64},
784+
{"hlsl_sm65", Target::D3D12ComputeSM65},
785+
{"hlsl_sm66", Target::D3D12ComputeSM66},
786+
{"hlsl_sm67", Target::D3D12ComputeSM67},
787+
{"hlsl_sm68", Target::D3D12ComputeSM68},
788+
{"hlsl_sm69", Target::D3D12ComputeSM69},
789789
{"strict_float", Target::StrictFloat},
790790
{"tsan", Target::TSAN},
791791
{"asan", Target::ASAN},
@@ -1994,11 +1994,11 @@ void target_test() {
19941994
{{"hexagon-32-qurt-hvx_v62", "hexagon-32-qurt", "hexagon-32-qurt"}},
19951995
{{"hexagon-32-qurt-hvx_v62-hvx", "hexagon-32-qurt", ""}},
19961996
{{"hexagon-32-qurt-hvx_v62-hvx", "hexagon-32-qurt-hvx", "hexagon-32-qurt-hvx"}},
1997-
{{"x86-64-windows-d3d12compute-d3d12compute_sm66", "x86-64-windows-d3d12compute", "x86-64-windows-d3d12compute"}},
1998-
{{"x86-64-windows-d3d12compute-d3d12compute_sm66", "x86-64-windows-d3d12compute-d3d12compute_sm60", "x86-64-windows-d3d12compute-d3d12compute_sm60"}},
1999-
{{"x86-64-windows-d3d12compute-d3d12compute_sm62", "x86-64-windows-d3d12compute-d3d12compute_sm62", "x86-64-windows-d3d12compute-d3d12compute_sm62"}},
2000-
{{"x86-64-windows-d3d12compute-d3d12compute_sm69", "x86-64-windows-d3d12compute", "x86-64-windows-d3d12compute"}},
2001-
{{"x86-64-windows-d3d12compute-d3d12compute_sm69", "x86-64-windows-d3d12compute-d3d12compute_sm60", "x86-64-windows-d3d12compute-d3d12compute_sm60"}},
1997+
{{"x86-64-windows-d3d12compute-hlsl_sm66", "x86-64-windows-d3d12compute", "x86-64-windows-d3d12compute"}},
1998+
{{"x86-64-windows-d3d12compute-hlsl_sm66", "x86-64-windows-d3d12compute-hlsl_sm60", "x86-64-windows-d3d12compute-hlsl_sm60"}},
1999+
{{"x86-64-windows-d3d12compute-hlsl_sm62", "x86-64-windows-d3d12compute-hlsl_sm62", "x86-64-windows-d3d12compute-hlsl_sm62"}},
2000+
{{"x86-64-windows-d3d12compute-hlsl_sm69", "x86-64-windows-d3d12compute", "x86-64-windows-d3d12compute"}},
2001+
{{"x86-64-windows-d3d12compute-hlsl_sm69", "x86-64-windows-d3d12compute-hlsl_sm60", "x86-64-windows-d3d12compute-hlsl_sm60"}},
20022002
};
20032003

20042004
for (const auto &test : gcd_tests) {

‎src/Target.h‎

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -184,16 +184,16 @@ struct Target {
184184
AVX10_1 = halide_target_feature_avx10_1,
185185
X86APX = halide_target_feature_x86_apx,
186186
Simulator = halide_target_feature_simulator,
187-
D3D12ComputeSM60 = halide_target_feature_d3d12compute_sm60,
188-
D3D12ComputeSM61 = halide_target_feature_d3d12compute_sm61,
189-
D3D12ComputeSM62 = halide_target_feature_d3d12compute_sm62,
190-
D3D12ComputeSM63 = halide_target_feature_d3d12compute_sm63,
191-
D3D12ComputeSM64 = halide_target_feature_d3d12compute_sm64,
192-
D3D12ComputeSM65 = halide_target_feature_d3d12compute_sm65,
193-
D3D12ComputeSM66 = halide_target_feature_d3d12compute_sm66,
194-
D3D12ComputeSM67 = halide_target_feature_d3d12compute_sm67,
195-
D3D12ComputeSM68 = halide_target_feature_d3d12compute_sm68,
196-
D3D12ComputeSM69 = halide_target_feature_d3d12compute_sm69,
187+
D3D12ComputeSM60 = halide_target_feature_hlsl_sm60,
188+
D3D12ComputeSM61 = halide_target_feature_hlsl_sm61,
189+
D3D12ComputeSM62 = halide_target_feature_hlsl_sm62,
190+
D3D12ComputeSM63 = halide_target_feature_hlsl_sm63,
191+
D3D12ComputeSM64 = halide_target_feature_hlsl_sm64,
192+
D3D12ComputeSM65 = halide_target_feature_hlsl_sm65,
193+
D3D12ComputeSM66 = halide_target_feature_hlsl_sm66,
194+
D3D12ComputeSM67 = halide_target_feature_hlsl_sm67,
195+
D3D12ComputeSM68 = halide_target_feature_hlsl_sm68,
196+
D3D12ComputeSM69 = halide_target_feature_hlsl_sm69,
197197
FeatureEnd = halide_target_feature_end
198198
};
199199
Target() = default;

‎src/runtime/HalideRuntime.h‎

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -1478,16 +1478,16 @@ typedef enum halide_target_feature_t {
14781478
halide_target_feature_avx10_1, ///< Intel AVX10 version 1 support. vector_bits is used to indicate width.
14791479
halide_target_feature_x86_apx, ///< Intel x86 APX support. Covers initial set of features released as APX: egpr,push2pop2,ppx,ndd .
14801480
halide_target_feature_simulator, ///< Target is for a simulator environment. Currently only applies to iOS.
1481-
halide_target_feature_d3d12compute_sm60, ///< Enable D3D12 Shader Model 6.0 (DXIL, 64-bit types, wave intrinsics). Requires d3d12compute. Uses DXC compiler.
1482-
halide_target_feature_d3d12compute_sm61, ///< Enable D3D12 Shader Model 6.1
1483-
halide_target_feature_d3d12compute_sm62, ///< Enable D3D12 Shader Model 6.2 (native 16-bit scalar types with -enable-16bit-types)
1484-
halide_target_feature_d3d12compute_sm63, ///< Enable D3D12 Shader Model 6.3
1485-
halide_target_feature_d3d12compute_sm64, ///< Enable D3D12 Shader Model 6.4
1486-
halide_target_feature_d3d12compute_sm65, ///< Enable D3D12 Shader Model 6.5
1487-
halide_target_feature_d3d12compute_sm66, ///< Enable D3D12 Shader Model 6.6 (64-bit atomics, packed 8-bit types)
1488-
halide_target_feature_d3d12compute_sm67, ///< Enable D3D12 Shader Model 6.7
1489-
halide_target_feature_d3d12compute_sm68, ///< Enable D3D12 Shader Model 6.8
1490-
halide_target_feature_d3d12compute_sm69, ///< Enable D3D12 Shader Model 6.9 (long vectors 5-1024 lanes, native 16-bit/wave/int64 required)
1481+
halide_target_feature_hlsl_sm60, ///< Enable D3D12 Shader Model 6.0 (DXIL, 64-bit types, wave intrinsics). Requires d3d12compute. Uses DXC compiler.
1482+
halide_target_feature_hlsl_sm61, ///< Enable D3D12 Shader Model 6.1
1483+
halide_target_feature_hlsl_sm62, ///< Enable D3D12 Shader Model 6.2 (native 16-bit scalar types with -enable-16bit-types)
1484+
halide_target_feature_hlsl_sm63, ///< Enable D3D12 Shader Model 6.3
1485+
halide_target_feature_hlsl_sm64, ///< Enable D3D12 Shader Model 6.4
1486+
halide_target_feature_hlsl_sm65, ///< Enable D3D12 Shader Model 6.5
1487+
halide_target_feature_hlsl_sm66, ///< Enable D3D12 Shader Model 6.6 (64-bit atomics, packed 8-bit types)
1488+
halide_target_feature_hlsl_sm67, ///< Enable D3D12 Shader Model 6.7
1489+
halide_target_feature_hlsl_sm68, ///< Enable D3D12 Shader Model 6.8
1490+
halide_target_feature_hlsl_sm69, ///< Enable D3D12 Shader Model 6.9 (long vectors 5-1024 lanes, native 16-bit/wave/int64 required)
14911491
halide_target_feature_end ///< A sentinel. Every target is considered to have this feature, and setting this feature does nothing.
14921492
} halide_target_feature_t;
14931493

‎src/runtime/d3d12compute.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2067,7 +2067,7 @@ WEAK d3d12_function *d3d12_compile_shader_dxc(d3d12_device *device, d3d12_librar
20672067

20682068
if (!D3D12LoadDXC(user_context)) {
20692069
TRACEFATAL("D3D12Compute: Unable to load dxcompiler.dll. "
2070-
"DXC is required for HLSL Shader Model 6.x (d3d12compute_sm60+).");
2070+
"DXC is required for HLSL Shader Model 6.x (hlsl_sm60+).");
20712071
return nullptr;
20722072
}
20732073

‎test/correctness/d3d12compute_sm6x.cpp‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -2,9 +2,9 @@
22
//
33
// Each sub-test is guarded by the minimum SM version it requires.
44
// Run with, e.g.:
5-
// HL_JIT_TARGET=x86-64-windows-d3d12compute_sm60 (64-bit types)
6-
// HL_JIT_TARGET=x86-64-windows-d3d12compute_sm62 (+ 16-bit types)
7-
// HL_JIT_TARGET=x86-64-windows-d3d12compute_sm66 (+ float atomics)
5+
// HL_JIT_TARGET=x86-64-windows-hlsl_sm60 (64-bit types)
6+
// HL_JIT_TARGET=x86-64-windows-hlsl_sm62 (+ 16-bit types)
7+
// HL_JIT_TARGET=x86-64-windows-hlsl_sm66 (+ float atomics)
88

99
#include "Halide.h"
1010
#include <cstdio>
@@ -161,14 +161,14 @@ int main(int argc, char **argv) {
161161

162162
if (!t.has_feature(Target::D3D12Compute)) {
163163
printf("[SKIP] D3D12Compute not in target.\n");
164-
printf(" Set HL_JIT_TARGET=x86-64-windows-d3d12compute_sm60 (or _sm62/_sm66)\n");
164+
printf(" Set HL_JIT_TARGET=x86-64-windows-hlsl_sm60 (or _sm62/_sm66)\n");
165165
return 0;
166166
}
167167

168168
int sm = t.get_d3d12compute_capability_lower_bound();
169169
if (sm < 60) {
170170
printf("[SKIP] SM %d: no SM 6.x features to test.\n", sm);
171-
printf(" Set HL_JIT_TARGET=x86-64-windows-d3d12compute_sm60 (or _sm62/_sm66)\n");
171+
printf(" Set HL_JIT_TARGET=x86-64-windows-hlsl_sm60 (or _sm62/_sm66)\n");
172172
return 0;
173173
}
174174

‎test/correctness/d3d12compute_strict_float.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -163,7 +163,7 @@ static int test_strict_float64(const Target &t) {
163163
// Compute in float64 with strict ops, store as float32.
164164
// Use integer literals (3, 1) so Halide folds them to FloatImm(Float(64))
165165
// rather than Cast(Float(64), IntImm) nodes, matching the pattern of the
166-
// working test_float64 in d3d12compute_sm6x.cpp.
166+
// working test_float64 in hlsl_sm6x.cpp.
167167
f(x) = cast<float>(strict_float(cast<double>(x) * 3 + 1));
168168
f.gpu_tile(x, xo, xi, 32);
169169

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