#59 Add support for AMD Leaf 8000_001B

Author: Zeppelin1979

src/display.rs

@@ -1311,6 +1311,49 @@ pub fn markdown<R: crate::CpuIdReader>(cpuid: crate::CpuId<R>) {
         );
     }
 
+    if let Some(info) = cpuid.get_instruction_based_sampling_capabilities() {
+        print_title(
+            &skin,
+            "Instruction-Based Sampling Capabilities (0x8000_001b):",
+        );
+        table2(
+            &skin,
+            &[
+                RowGen::tuple("IBS feature flags valid", info.has_feature_flags()),
+                RowGen::tuple("IBS fetch sampling supporte", info.has_fetch_sampling()),
+                RowGen::tuple(
+                    "IBS execution sampling supported",
+                    info.has_execution_sampling(),
+                ),
+                RowGen::tuple(
+                    "Read write of op counter supported",
+                    info.has_read_write_operation_counter(),
+                ),
+                RowGen::tuple("Op counting mode supported", info.has_operation_counter()),
+                RowGen::tuple(
+                    "Branch target address reporting supported",
+                    info.has_branch_target_address_reporting(),
+                ),
+                RowGen::tuple(
+                    "IbsOpCurCnt and IbsOpMaxCnt extend by 7 bits",
+                    info.has_operation_counter_extended(),
+                ),
+                RowGen::tuple(
+                    "Invalid RIP indication supported",
+                    info.has_invalid_rip_indication(),
+                ),
+                RowGen::tuple(
+                    "Fused branch micro-op indication supported",
+                    info.has_fused_branch_micro_op_indication(),
+                ),
+                RowGen::tuple(
+                    "L3 Miss Filtering for IBS supported",
+                    info.has_l3_miss_filtering(),
+                ),
+            ],
+        );
+    }
+
     if let Some(info) = cpuid.get_processor_topology_info() {
         print_title(&skin, "Processor Topology Info (0x8000_001e):");
         table2(

src/extended.rs

@@ -1576,6 +1576,109 @@ bitflags! {
     }
 }
 
+/// Performance Optimization Identifier (LEAF=0x8000_001A).
+///
+/// # Platforms
+/// ✅ AMD ❌ Intel
+#[derive(PartialEq, Eq, Debug)]
+pub struct InstructionBasedSamplingCapabilities {
+    eax: InstructionBasedSamplingCapabilitiesEax,
+    /// Reserved
+    _ebx: u32,
+    /// Reserved
+    _ecx: u32,
+    /// Reserved
+    _edx: u32,
+}
+
+impl InstructionBasedSamplingCapabilities {
+    pub(crate) fn new(data: CpuIdResult) -> Self {
+        Self {
+            eax: InstructionBasedSamplingCapabilitiesEax::from_bits_truncate(data.eax),
+            _ebx: data.ebx,
+            _ecx: data.ecx,
+            _edx: data.edx,
+        }
+    }
+
+    /// IBS feature flags valid if set.
+    pub fn has_feature_flags(&self) -> bool {
+        self.eax
+            .contains(InstructionBasedSamplingCapabilitiesEax::IBSFFV)
+    }
+
+    /// IBS fetch sampling supported if set.
+    pub fn has_fetch_sampling(&self) -> bool {
+        self.eax
+            .contains(InstructionBasedSamplingCapabilitiesEax::FETCH_SAM)
+    }
+
+    /// IBS execution sampling supported if set.
+    pub fn has_execution_sampling(&self) -> bool {
+        self.eax
+            .contains(InstructionBasedSamplingCapabilitiesEax::OP_SAM)
+    }
+
+    /// Read write of op counter supported if set.
+    pub fn has_read_write_operation_counter(&self) -> bool {
+        self.eax
+            .contains(InstructionBasedSamplingCapabilitiesEax::RD_WR_OP_CNT)
+    }
+
+    /// Op counting mode supported if set.
+    pub fn has_operation_counter(&self) -> bool {
+        self.eax
+            .contains(InstructionBasedSamplingCapabilitiesEax::OP_CNT)
+    }
+
+    /// Branch target address reporting supported if set.
+    pub fn has_branch_target_address_reporting(&self) -> bool {
+        self.eax
+            .contains(InstructionBasedSamplingCapabilitiesEax::BRN_TRGT)
+    }
+
+    /// IbsOpCurCnt and IbsOpMaxCnt extend by 7 bits if set.
+    pub fn has_operation_counter_extended(&self) -> bool {
+        self.eax
+            .contains(InstructionBasedSamplingCapabilitiesEax::OP_CNT_EXT)
+    }
+
+    /// Invalid RIP indication supported if set.
+    pub fn has_invalid_rip_indication(&self) -> bool {
+        self.eax
+            .contains(InstructionBasedSamplingCapabilitiesEax::RIP_INVALID_CHK)
+    }
+
+    /// Fused branch micro-op indication supported if set.
+    pub fn has_fused_branch_micro_op_indication(&self) -> bool {
+        self.eax
+            .contains(InstructionBasedSamplingCapabilitiesEax::OP_BRN_FUSE)
+    }
+
+    /// L3 Miss Filtering for IBS supported if set.
+    pub fn has_l3_miss_filtering(&self) -> bool {
+        self.eax
+            .contains(InstructionBasedSamplingCapabilitiesEax::IBS_L3_MISS_FILTERING)
+    }
+}
+
+bitflags! {
+    #[repr(transparent)]
+    #[derive(Debug, Clone, Copy, PartialEq, Eq)]
+    struct InstructionBasedSamplingCapabilitiesEax: u32 {
+        const IBSFFV = 1 << 0;
+        const FETCH_SAM = 1 << 1;
+        const OP_SAM = 1 << 2;
+        const RD_WR_OP_CNT = 1 << 3;
+        const OP_CNT = 1 << 4;
+        const BRN_TRGT = 1 << 5;
+        const OP_CNT_EXT = 1 << 6;
+        const RIP_INVALID_CHK = 1 << 7;
+        const OP_BRN_FUSE = 1 << 8;
+        const IBS_L3_MISS_FILTERING = 1 << 11;
+    }
+}
+
 /// Processor Topology Information (LEAF=0x8000_001E).
 ///
 /// # Platforms

src/lib.rs

@@ -319,6 +319,7 @@ const EAX_ADVANCED_POWER_MGMT_INFO: u32 = 0x8000_0007;
 const EAX_PROCESSOR_CAPACITY_INFO: u32 = 0x8000_0008;
 const EAX_TLB_1GB_PAGE_INFO: u32 = 0x8000_0019;
 const EAX_PERFORMANCE_OPTIMIZATION_INFO: u32 = 0x8000_001A;
+const EAX_INSTRUCTION_BASED_SAMPLING_CAPABILITIES: u32 = 0x8000_001B;
 const EAX_CACHE_PARAMETERS_AMD: u32 = 0x8000_001D;
 const EAX_PROCESSOR_TOPOLOGY_INFO: u32 = 0x8000_001E;
 const EAX_MEMORY_ENCRYPTION_INFO: u32 = 0x8000_001F;
@@ -934,6 +935,23 @@ impl<R: CpuIdReader> CpuId<R> {
         }
     }
 
+    /// Instruction-Based Sampling Capabilities (LEAF=0x8000_001B)
+    ///
+    /// # Platforms
+    /// ✅ AMD ❌ Intel (reserved)
+    pub fn get_instruction_based_sampling_capabilities(
+        &self,
+    ) -> Option<InstructionBasedSamplingCapabilities> {
+        if self.leaf_is_supported(EAX_INSTRUCTION_BASED_SAMPLING_CAPABILITIES) {
+            Some(InstructionBasedSamplingCapabilities::new(
+                self.read
+                    .cpuid1(EAX_INSTRUCTION_BASED_SAMPLING_CAPABILITIES),
+            ))
+        } else {
+            None
+        }
+    }
+
     /// Informations about processor topology (LEAF=0x8000_001E)
     ///
     /// # Platforms

src/tests/ryzen_matisse.rs

@@ -1243,6 +1243,25 @@ fn performance_optimization_info() {
     assert!(e.has_fp256());
 }
 
+#[test]
+fn instruction_based_sampling_capabilities() {
+    let cpuid = CpuId::with_cpuid_fn(cpuid_reader);
+    let e = cpuid
+        .get_instruction_based_sampling_capabilities()
+        .expect("Leaf is supported");
+
+    assert!(e.has_feature_flags());
+    assert!(e.has_fetch_sampling());
+    assert!(e.has_execution_sampling());
+    assert!(e.has_read_write_operation_counter());
+    assert!(e.has_operation_counter());
+    assert!(e.has_branch_target_address_reporting());
+    assert!(e.has_operation_counter_extended());
+    assert!(e.has_invalid_rip_indication());
+    assert!(e.has_fused_branch_micro_op_indication());
+    assert!(!e.has_l3_miss_filtering());
+}
+
 #[test]
 fn processor_topology_info() {
     let cpuid = CpuId::with_cpuid_fn(cpuid_reader);