diff --git a/.devcontainer/Dockerfile b/.devcontainer/Dockerfile deleted file mode 100644 index 3f37cff8..00000000 --- a/.devcontainer/Dockerfile +++ /dev/null @@ -1,10 +0,0 @@ -FROM gcr.io/gem5-test/gem5-tutorial-env:latest - -RUN apt update -y && apt -y install apt-transport-https ca-certificates curl gnupg2 software-properties-common -RUN curl -fsSL https://download.docker.com/linux/ubuntu/gpg | apt-key add - -RUN add-apt-repository "deb [arch=amd64] https://download.docker.com/linux/ubuntu $(lsb_release -cs) stable" - -RUN apt-get update && apt-get -y install docker-ce docker-ce-cli containerd.io docker-compose-plugin - -# "deb [arch=$(dpkg --print-architecture) signed-by=/etc/apt/keyrings/docker.gpg] https://download.docker.com/linux/ubuntu \ -# $(lsb_release -cs) stable" | sudo tee /etc/apt/sources.list.d/docker.list > /dev/null \ No newline at end of file diff --git a/.devcontainer/devcontainer.json b/.devcontainer/devcontainer.json index dd37a47e..6adb8220 100644 --- a/.devcontainer/devcontainer.json +++ b/.devcontainer/devcontainer.json @@ -1,17 +1,38 @@ { + "name": "gem5 Development Container", + "image": "ghcr.io/gem5/devcontainer:v24-0", "hostRequirements": { - "cpus": 16, + "cpus": 1, "memory": "8gb", - "storage": "32gb" + "storage": "64gb" + }, + "customizations": { + "vscode": { + "extensions": [ + "GitHub.copilot", + "GitHub.copilot-chat", + "GitHub.vscode-pull-request-github", + "ms-python.debugpy", + "ms-python.isort", + "ms-python.python", + "ms-python.vscode-pylance", + "ms-vscode.cpptools", + "ms-vscode.cpptools-extension-pack", + "ms-vscode.cpptools-themes", + "ms-vscode.makefile-tools", + "Tsinghua-Hexin-Joint-Institute.gem5-slicc", + "ms-python.black-formatter", + "marp-team.marp-vscode", + "hediet.vscode-drawio" + ] + } }, - "build": { "dockerfile": "Dockerfile" }, - "onCreateCommand" : "bash ./.devcontainer/on_create.sh", - "runArgs": ["--privileged", "-v", "/var/run/docker.sock:/var/run/docker.sock", "--security-opt", "seccomp=unconfined"], - "extensions": [ - "ms-vscode.cpptools", - "streetsidesoftware.code-spell-checker", - "eamodio.gitlens", - "ms-python.vscode-pylance", - "ms-python.python" - ] + "features": { + "ghcr.io/devcontainers/features/docker-in-docker:2": {}, + "ghcr.io/devcontainers/features/github-cli:1": {}, + "ghcr.io/devcontainers-contrib/features/actionlint:1": {}, + "ghcr.io/devcontainers-contrib/features/vscode-cli:1": {} + }, + "onCreateCommand": "./.devcontainer/on_create.sh", + "postStartCommand": "./.devcontainer/post_start.sh" } diff --git a/.devcontainer/on_create.sh b/.devcontainer/on_create.sh index a8dcb7fa..7cf76091 100755 --- a/.devcontainer/on_create.sh +++ b/.devcontainer/on_create.sh @@ -3,15 +3,8 @@ # Update the submodules git submodule update --init --recursive -# Create the stubs -gem5-arm gem5_stubgen.py -gem5-x86 gem5_stubgen.py -gem5-riscv gem5_stubgen.py - -mv out typings - # Setups the gem5 source directory -cd gem5 +pushd gem5 ## We cleanup git's 'blame' feature by ignoring certain commits (typically ## commits that have reformatted files) @@ -19,3 +12,21 @@ git config --global blame.ignoreRevsFile .git-blame-ignore-revs ## `git pull` should rebase by default git config --global pull.rebase true + +./util/pre-commit-install.sh + +popd # gem5 + +# Pre-download the resources we use + +gem5 pre-download-resources.py + +docker pull ghcr.io/gem5/gcn-gpu:v24-0 + +wget http://dist.gem5.org/dist/v24-0/test-progs/square/square + +wget https://storage.googleapis.com/dist.gem5.org/dist/v24-0/gpu-fs/kernel/vmlinux-gpu-ml-isca + +# Note: this unzips to 55 GB so must in on /tmp. +# See post_start.sh where it is unzipped each time the devcontainer starts +wget https://storage.googleapis.com/dist.gem5.org/dist/v24-0/gpu-fs/diskimage/x86-ubuntu-gpu-ml-isca.gz diff --git a/.devcontainer/post_start.sh b/.devcontainer/post_start.sh new file mode 100755 index 00000000..ec608607 --- /dev/null +++ b/.devcontainer/post_start.sh @@ -0,0 +1,8 @@ +#!/bin/bash + +if [ ! -f /tmp/x86-ubuntu-gpu-ml-isca ]; then + cp x86-ubuntu-gpu-ml-isca.gz /tmp + gunzip /tmp/x86-ubuntu-gpu-ml-isca.gz +fi + +ln -s /tmp/x86-ubuntu-gpu-ml-isca . diff --git a/.gitignore b/.gitignore index 77a3b25a..26457716 100644 --- a/.gitignore +++ b/.gitignore @@ -1,5 +1,6 @@ # Ignore all m5out directories and build directories **/m5out/ +**/checkpoint/ # Jekyll stuff _site/ @@ -12,3 +13,13 @@ typings/ .vscode/*.log __pycache__ + +# Ignore downloaded files +square +vmlinux-gpu-ml-isca +x86-ubuntu-gpu-ml-isca +x86-ubuntu-gpu-ml-isca.gz + +# Ignore slides +*.pdf +*.html diff --git a/.gitmodules b/.gitmodules index 4d79aeaa..ee09c2b5 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,6 +1,6 @@ [submodule "gem5"] path = gem5 - url = https://gem5.googlesource.com/public/gem5 + url = https://github.com/gem5/gem5 [submodule "gem5-resources"] path = gem5-resources - url = https://gem5.googlesource.com/public/gem5-resources + url = https://github.com/gem5/gem5-resources diff --git a/.vscode/settings.json b/.vscode/settings.json index b8371e21..6d0f7369 100644 --- a/.vscode/settings.json +++ b/.vscode/settings.json @@ -1,12 +1,17 @@ { - "python.formatting.provider": "black", - "python.analysis.stubPath": "typings", "python.analysis.extraPaths": ["gem5/src/python"], - "python.formatting.blackArgs": [ - "--line-length", - "79" - ], "editor.rulers": [ 79 - ] + ], + "files.trimTrailingWhitespace": true, + "files.insertFinalNewline": true, + "markdown.marp.themes": [ + "slides/themes/gem5.css" + ], + "markdown.marp.enableHtml": true, + "hediet.vscode-drawio.globalVars": { + "pageScale": "1", + "pageWidth": "1160", + "pageHeight": "440" + } } diff --git a/README.md b/README.md index f58ab055..7cf7a46a 100644 --- a/README.md +++ b/README.md @@ -1,38 +1,43 @@ +# gem5 bootcamp environment + This repository has been designed for use in gem5 tutorials. + It has been built with the assumption users will utilize [Codespaces](https://github.com/features/codespaces) to learn gem5. The repository contains the following directories: * [docker](docker) : -The source code for the Docker image used by [.devcontainer/Dockerfile](.devcontainer/Dockerfile) to create the Codespace Docker container. +The source code for the Docker image used by the [Dockerfile](gem5/util/dockerfiles/devcontainer/Dockerfile) to create the Codespace Docker container. * gem5 : -v22.0.0.1 of gem5. +v24.0.0.0 of gem5. * gem5-resources : -gem5-resources which may be used with v22.0 of gem5. +gem5-resources which may be used with v24.0 of gem5. * materials: Example materials used as part of the tutorial. -* modules: Source for the accompying website: https://gem5bootcamp.github.io/gem5-bootcamp-env +* modules: Source for the accompanying website: (This link is not up to date.) The website contains links to slides, presentation videos, and notes for the tutorials. -**Note:** 'gem5' and 'gem5-resources' are submodules though the [.devcontainer/devcontainer.json](.devcontainer/devcontainer.json) file specifies that a `git module update --init --recursive` command is executed when the Codespace Docker container is created. +**Note:** 'gem5' and 'gem5-resources' are submodules though the [.devcontainer/devcontainer.json](.devcontainer/devcontainer.json) file specifies that a `git submodule update --init --recursive` command is executed when the Codespace Docker container is created. -The container used by Codespaces is built from [.devcontainer/Dockerfile](.devcontainer/Dockerfile). +The container used by Codespaces is built from [Dockerfile](gem5/util/dockerfiles/devcontainer/Dockerfile). It contains: * All gem5 dependencies (inc. optional dependencies). * Prebuilt gem5 binaries: - - `/usr/local/bin/gem5-x86` - - `/usr/local/bin/gem5-arm` - - `/usr/local/bin/gem5-riscv` + * `/usr/local/bin/gem5` (gem5 ALL ISAs with CHI protocol) + * `/usr/local/bin/gem5-default` (default gem5 ALL build with MESI_Two_Level) + * `/usr/local/bin/gem5-vega` (x86-only with GPU protocol) + * `/usr/local/bin/gem5-vega-se` (same as above, but compiled with 20.04) * A RISCV64 and an AARCH64 GNU cross-compiler: - * RISCV64 GNU cross-compiler found in `/opt/cross-compiler/riscv64-linux/`. - * AARCH64 GNU cross-compiler found in `/opt/cross-compiler/aarch64-linux/`. + * RISCV64 GNU cross-compiler found in `/opt/cross-compiler/riscv64-linux/`. + * AARCH64 GNU cross-compiler found in `/opt/cross-compiler/aarch64-linux/`. +* ROCm development environment 6.1.2 (note, this is why the container is based on 22.04 instead of 24.04) ## Beginners' example The following can be used within the Codespace container to run a basic gem5 simulation straight away: ``` -gem5-arm gem5/configs/example/gem5_library/arm-hello.py +gem5 gem5/configs/example/gem5_library/arm-hello.py ``` This will execute a "Hello world!" program inside a simulated ARM system. @@ -41,12 +46,13 @@ This will execute a "Hello world!" program inside a simulated ARM system. In this project we have two submodules: 'gem5' and 'gem5-resources'. These are automatically obtained when the codespaces is initialized. -At the time of writing the 'gem5' directory is checked out to the stable branch at v22.0.0.1. -The 'gem5-resources' repository is checkoued out to revision '871e715', which should contain resources with known compatibility with gem5 v22.0. +At the time of writing the 'gem5' directory is checked out to the stable branch at v24.0.0.0. +The 'gem5-resources' repository is checked out to revision '97532302', which should contain resources with known compatibility with gem5 v24.0. -To update the git submodules to be in-sync with their remote origins (that hosted on our [googlesource](https://gem5.googlesource.com)), execute the following command: +To update the git submodules to be in-sync with their remote origins (that hosted on our [GitHub](https://github.com/gem5/gem5)), execute the following command: ```sh +git submodule sync # Only needed if submodule remotes changed git submodule update --remote ``` @@ -58,7 +64,7 @@ git commit -m "git submodules updated" git push ``` -## Best practises +## Best practices ### Using branches @@ -83,7 +89,7 @@ git branch example-1 # Creating a new branch named 'example-1'. 3. Checkout this branch: ```sh -git checkout example-` +git checkout example-1 ``` 4. Make changes on this branch and commit the changes. @@ -113,3 +119,12 @@ To see a list of all available branches you can execute: ```sh git branch ``` + +## Note on running GPU SE + +You can use docker. +Below is an example command + +```sh +docker run -v $PWD:$PWD -v /usr/local/bin:/usr/local/bin -w $PWD ghcr.io/gem5/gcn-gpu:v24-0 gem5-vega-se gem5/configs/example/apu_se.py -n 3 -c square +``` diff --git a/_data/course.yml b/_data/course.yml index 55f10b49..ec6631c3 100644 --- a/_data/course.yml +++ b/_data/course.yml @@ -1,3 +1,3 @@ -title: "gem5 Bootcamp 2022" -description: "gem5 Bootcamp Summer 2022 at UC Davis offered by the Davis Computer Architecture Research Group" +title: "gem5 Bootcamp" +description: "gem5 Bootcamp Summer 2024 at UC Davis offered by the Davis Computer Architecture Research Group" modules: ["Introduction", "Using gem5", "Developing gem5 models", "Extra topics"] diff --git a/gem5 b/gem5 index a1007311..43769aba 160000 --- a/gem5 +++ b/gem5 @@ -1 +1 @@ -Subproject commit a10073119ecdb95961d92f734cc0f5fd7c49adba +Subproject commit 43769abaf05120fed1e4e0cfbb34619edbc10f3f diff --git a/gem5-resources b/gem5-resources index c30d1d60..6734bb49 160000 --- a/gem5-resources +++ b/gem5-resources @@ -1 +1 @@ -Subproject commit c30d1d60457cf19504272d4ce02e79b3c1c5ace1 +Subproject commit 6734bb4940dd90f3b7c0349eedeefcf3ee405938 diff --git a/index.md b/index.md index 1a05ac15..d7af2d80 100644 --- a/index.md +++ b/index.md @@ -1,36 +1,116 @@ --- layout: index -title: Learning gem5 Bootcamp 2022 +title: Learning gem5 Bootcamp 2024 --- -## Livestream and discussion - -You can find links to all of the livestreamed videos on [YouTube](https://www.youtube.com/playlist?list=PL_hVbFs_loVSaSDPr1RJXP5RRFWjBMqq3). - -Instead of using YouTube comments, we will be using [Slack](https://app.slack.com/client/T03JNC47S2E/C03PJRJ4RQ8) for our discussions. -You can use the following [invite link](https://join.slack.com/t/gem5-workspace/shared_invite/zt-1aal963w6-_cqn0u8QgBh3GeeSi2Ja7g) to enter the slack. -Once you have joined, type `/join-channel bootcamp-2022` in any text box (e.g., in a DM to yourself) to join the bootcamp channel. - -## Tentative schedule - -|Session| Topic | Objectives| -| :--- | :--- | :--- | -| Monday Morning | Welcome and Introduction | | -| | Building gem5 |- Learn about the gem5 dependencies
- Be introduced to SCons
- Understand the different gem5 binary types (opt, debug, fast)| -| | Python basics | - A recap of basic Python skills needed to use gem5
- Object-oriented programming reminder
- Run a simple python script in gem5 | -| | Using gem5 basics | - Understand gem5 configuration scripts and its python interpreter
- Understand what the `m5` and `gem5` libraries are
- Get a general architecture outline of gem5
- Obtain and understand the stats output
- Understand the `config.ini` file | -| | About simulation | - Learn about common gem5 terminology: "host", "guest", etc.
- Learn about the difference between Full-System and Syscall emulation mode | -| Monday Afternoon | The gem5 standard library | - Use the stdlib components to build a simulated system
- Use the stdlib `resource` class to automatically obtain gem5-resources to use in their experiment
- Create a gem5 resource custom resource
- Set workloads for a simulated system via the `set_workload` functions
- Create functions to run on specific exit events
- Create an stdlib component| -| | **Welcome dinner** | | -|Tuesday Morning | Using gem5 models | - Use different gem5 CPU models (Timing Simple, Atomic, O3, Minor, Trace, etc.)
- Use classic caches in a simulation
- Use Ruby caches in a simulation (understand the different coherence protocols, how to compile them and how to create a cache hierarchy via a simple network) | -| | Using gem5 to run things | - Use traffic generators to test memory systems
- Incorporate the m5 utility into workloads
- Learn to use cross-compilers for non-host ISA workloads
- Learn how to output and parse stats| -| Tuesday Afternoon| Full system simulation | - Create a disk image for FS simulations
- Create and add and modify gem5 resources
- Learn how to use the `m5 readfile` interface| -| | Accelerating Simulation | - Create checkpoints
- Load from checkpoints
- Fastforward a simulation
- Employ sampling techniques
- Learn about KVM | -| Wednesday Morning| Creating your own SimObjects| - Understand how a request travels through the system
- Implement a SimObject
- Learn how to model real-world hardware timing
- Learn how to add SimStats and how it maps to real-world hardware
- Debug a gem5 SimObject | -| Wednesday Afternoon| Adding your own instructions| - Understand the details of the ISA sub-system
- Extend gem5 to simulate an unsupported instruction
- Understand the differences between modeling a user-mode and supervisor mode instruction
- Understand gem5 debug traces for a particular execution | -| Thursday Morning | Advanced topics in memory systems | - Learn how to extend a packet with a new MemCmd
- Learn how to use Garnet (How to create different network topologies with specific characteristics; using the Garnet synthetic traffic; and understanding the output statistics)
- Create and extend cache coherence protocols (create a classic coherence protocol; design a Ruby coherence protocol)| -| Thursday Afternoon | The gem5 GPU Model | [TBD] | -| | **Group Social Event** | | -| Friday Morning | Writing tests and contributing to gem5 | - Write a GTest to test a piece of CPP code
- Write a PyUnit test to test a python function
- Use testlib to test a gem5 simulation condition
- Run Testlib/PyUnit/GUnit tests for gem5
- Understand gem5's quick/Kokoro, long/Nightly, very-long/Weekly test structure
- Understand gem5's code-formatting guidelines
- Use git to add code to the repo
- Review patches on Gerrit
- Respond to feedback on Gerrit | -| Friday Afternoon | gem5 extensions and other simulators | - Incorporate SST into a simulation
- Incorporate DRAMSim into a simulation
- Use SystemC in gem5 and gem5 in SystemC | -| | Wrapping things up | | +Welcome to the gem5 Bootcamp! + +[Register for the 2024 gem5 Bootcamp](https://na.eventscloud.com/ereg/index.php?eventid=799532&){: .btn .btn-lg .btn-primary} + +As the premier destination for computer architecture enthusiasts and researchers, our bootcamp offers an immersive experience into the world of architectural simulation and modeling. +Whether you're a student eager to learn, a professional looking to sharpen your skills, or a researcher seeking to push the boundaries of technology, the gem5 Bootcamp is your gateway to mastering the gem5 simulator. + +Join us to explore the intricate workings of modern computer systems, engage with experts in the field, and collaborate with peers from around the globe. +With hands-on sessions, in-depth tutorials, and challenging projects, you'll gain practical knowledge and experience that will propel your understanding and innovation in computer architecture. + +Dive into the dynamic world of simulation with the gem5 Bootcamp, and emerge equipped to tackle the computational challenges of tomorrow. + +We also held a [gem5 Bootcamp in 2022](https://gem5bootcamp.github.io/gem5-bootcamp-env/) which you can check out for more information. +Videos from that bootcamp are available [on YouTube](https://www.youtube.com/watch?v=orASbQ02pDw&list=PL_hVbFs_loVSaSDPr1RJXP5RRFWjBMqq3). + +## Tentative schedule for 2024 + +The bootcamp will be held from July 29th to August 2nd, 2024. +The bootcamp will run from 9am-4pm each day in the [UC Davis Conference Center](https://conferencecenter.ucdavis.edu/). + +The full five day registration runs Monday-Friday. +The three day registration runs Tuesday-Thursday. + +**Note: The links on this website are under construction and will be updated as the bootcamp approaches.** + +- **Day 1: Computer architecture and computer architectures simulation 101** + - **Morning:** + - Introduction to computer architecture simulation + - Introduction to gem5 + - Running gem5 + - gem5's input and output + - Python language reminder + - **Afternoon:** + - Exercises with gem5 + - Discussions on research plans and preview the rest of the bootcamp +- **Day 2: gem5 basics** + - **Morning: Configuring and running gem5 with pre-built resources** + - gem5 Standard Library + - Using stdlib components + - Extending stdlib components + - Using the `Simulator` object + - Customizing exit operations + - gem5 Resources + - Using pre-built resources from + - Kinds of resources: disk images, kernels, binaries, workloads, suites + - Creating your own resources + - Using local resources + - Extending disk images (more on FS mode later) + - gem5 basics + - Building gem5, dependencies, SCons + - Understanding gem5's build options + - Available gem5 models + - CPU models + - Memory models + - Cache models + - Device and other models + - **Afternoon: Using gem5 for computer system evaluation** + - Deep dive on inputs to gem5 + - Traffic generators + - Building binaries for gem5 and cross compiling + - Marking regions of interest and the `gem5-bridge` (`m5`) library + - Full system simulation + - Required pieces + - Creating disk images + - `gem5-bridge` application + - Bundling FS resources together into `Workload`s + - Accelerating simulation + - Fast-fowarding + - KVM-based CPU + - Checkpointing + - Sampling +- **Day 3: Advanced gem5 uses and beginning gem5 development** + - **Morning: Advanced gem5 uses** + - gem5's GPU model + - Introduction to the GPU model + - Requirements for running the GPU model + - GPU resources + - Limitations of the GPU model + - **Afternoon: Getting started with gem5 development** + - Getting started with gem5 development and setting up a development environment + - Creating your own `SimObject`s + - Understand how a request travels through the system + - Implement a SimObject + - Learn how to model real-world hardware timing + - Learn how to add SimStats and how it maps to real-world hardware + - Debug a gem5 SimObject +- **Day 4: Advanced gem5 development** + - **Morning: gem5's memory system** + - Learn how to extend a packet with a new MemCmd + - Learn how to use Garnet (How to create different network topologies with specific characteristics; using the Garnet synthetic traffic; and understanding the output statistics) + - Create and extend cache coherence protocols (create a classic coherence protocol; design a Ruby coherence protocol) +- **Afternoon: gem5's execution model and adding new instructions** + - Understand the details of the ISA sub-system + - Extend gem5 to simulate an unsupported instruction + - Understand the differences between modeling a user-mode and supervisor mode instruction + - Understand gem5 debug traces for a particular execution +- **Day 5: Integrations with other simulators and contributing to gem5** + - **Morning: Integrations with other simulators** + - gem5's integration with other simulators + - SystemC in gem5 & gem5 in SystemC + - DRAMSys + - DRAMSim + - gem5 + [SST](https://sst-simulator.org/) + - **Afternoon: Contributing to gem5** + - Overview of gem5 governance model + - Contributing to gem5 + - Understand the gem5 contribution process + - Learn how to write a gem5 patch + - Learn how to review a gem5 patch + - Using git with gem5 + - gem5 testing diff --git a/materials/README.md b/materials/README.md new file mode 100644 index 00000000..427c6b1e --- /dev/null +++ b/materials/README.md @@ -0,0 +1,6 @@ +# Using the bootcamp materials + +- Explain directory structure + - Same as slides +- All files must have docstring with example usage +- Examples should probably appear in slides somewhere diff --git a/materials/isca24/01-basic.py b/materials/isca24/01-basic.py new file mode 100644 index 00000000..b3da7503 --- /dev/null +++ b/materials/isca24/01-basic.py @@ -0,0 +1,10 @@ +""" +This will start Linux boot on X86DemoBoard and run for 20 billion cycles. +Used as a very simple example. + +run with `gem5-mesi 01-basic.py` +""" + +from gem5.prebuilt.demo.x86_demo_board import X86DemoBoard +from gem5.resources.resource import obtain_resource +from gem5.simulate.simulator import Simulator diff --git a/materials/isca24/02-components.py b/materials/isca24/02-components.py new file mode 100644 index 00000000..0d566470 --- /dev/null +++ b/materials/isca24/02-components.py @@ -0,0 +1,21 @@ +""" +This will build a classic caches based system to run a simple x86 SE workload. +IS takes about 40 seconds. + +Run with `gem5 02-components.py` +""" + +from gem5.components.boards.simple_board import SimpleBoard +from gem5.components.cachehierarchies.classic.private_l1_shared_l2_cache_hierarchy import ( + PrivateL1SharedL2CacheHierarchy, +) +from gem5.components.memory.single_channel import SingleChannelDDR4_2400 + +from gem5.components.processors.cpu_types import CPUTypes +from gem5.components.processors.simple_processor import SimpleProcessor +from gem5.isas import ISA + +from gem5.resources.resource import obtain_resource + +from gem5.simulate.simulator import Simulator + diff --git a/materials/isca24/03-processor.py b/materials/isca24/03-processor.py new file mode 100644 index 00000000..2d881f32 --- /dev/null +++ b/materials/isca24/03-processor.py @@ -0,0 +1,65 @@ +""" +Script with a specialized O3 CPU +IS takes about 2-3 minutes with this script + +Run with `gem5 03-processor.py` +""" + +from gem5.components.boards.simple_board import SimpleBoard +from gem5.components.cachehierarchies.classic.private_l1_shared_l2_cache_hierarchy import ( + PrivateL1SharedL2CacheHierarchy, +) +from gem5.components.memory.single_channel import SingleChannelDDR4_2400 +from gem5.resources.resource import obtain_resource +from gem5.simulate.simulator import Simulator +from gem5.isas import ISA + +from gem5.components.processors.base_cpu_core import BaseCPUCore +from gem5.components.processors.base_cpu_processor import BaseCPUProcessor + +from m5.objects import X86O3CPU +from m5.objects import TournamentBP + +class MyOutOfOrderCore(BaseCPUCore): + def __init__(self, width, rob_size, num_int_regs, num_fp_regs): + pass + +class MyOutOfOrderProcessor(BaseCPUProcessor): + def __init__(self, width, rob_size, num_int_regs, num_fp_regs): + """ + :param width: sets the width of fetch, decode, raname, issue, wb, and + commit stages. + :param rob_size: determine the number of entries in the reorder buffer. + :param num_int_regs: determines the size of the integer register file. + :param num_int_regs: determines the size of the vector/floating point + register file. + """ + pass + + +main_memory = SingleChannelDDR4_2400(size="2GB") + +caches = PrivateL1SharedL2CacheHierarchy( + l1d_size="32KiB", + l1d_assoc=8, + l1i_size="32KiB", + l1i_assoc=8, + l2_size="256KiB", + l2_assoc=16, +) + +my_ooo_processor = MyOutOfOrderProcessor( + width=8, rob_size=192, num_int_regs=256, num_fp_regs=256 +) + +board = SimpleBoard( + processor=my_ooo_processor, + memory=main_memory, + cache_hierarchy=caches, + clk_freq="3GHz", +) + +board.set_workload(obtain_resource("x86-npb-is-size-s-run")) + +simulator = Simulator(board) +simulator.run() diff --git a/materials/isca24/04-kvm.py b/materials/isca24/04-kvm.py new file mode 100644 index 00000000..2b32e8ec --- /dev/null +++ b/materials/isca24/04-kvm.py @@ -0,0 +1,88 @@ +""" +Simple example to play around with KVM +Takes about 30 seconds to boot to the interactive prompt. + +Run with gem5-mesi 04-kvm.py +""" + +from gem5.coherence_protocol import CoherenceProtocol +from gem5.components.boards.x86_board import X86Board +from gem5.components.cachehierarchies.ruby.mesi_two_level_cache_hierarchy import ( + MESITwoLevelCacheHierarchy, +) +from gem5.components.memory.single_channel import SingleChannelDDR4_2400 +from gem5.components.processors.cpu_types import CPUTypes +from gem5.components.processors.simple_switchable_processor import ( + SimpleSwitchableProcessor, +) +from gem5.isas import ISA +from gem5.resources.resource import obtain_resource +from gem5.simulate.exit_event import ExitEvent +from gem5.simulate.simulator import Simulator +from gem5.utils.requires import requires + +# This simulation requires using KVM with gem5 compiled for X86 simulation +# and with MESI_Two_Level cache coherence protocol. +requires( + isa_required=ISA.X86, + coherence_protocol_required=CoherenceProtocol.MESI_TWO_LEVEL, + kvm_required=True, +) + +from gem5.components.cachehierarchies.ruby.mesi_two_level_cache_hierarchy import ( + MESITwoLevelCacheHierarchy, +) + +cache_hierarchy = MESITwoLevelCacheHierarchy( + l1d_size="32KiB", + l1d_assoc=8, + l1i_size="32KiB", + l1i_assoc=8, + l2_size="512KiB", + l2_assoc=16, + num_l2_banks=1, +) + +# Main memory +memory = SingleChannelDDR4_2400(size="3GiB") + +# This is a switchable CPU. We first boot Ubuntu using KVM, then the guest +# will exit the simulation by calling "m5 exit" (see the `command` variable +# below, which contains the command to be run in the guest after booting). +# Upon exiting from the simulation, the Exit Event handler will switch the +# CPU type (see the ExitEvent.EXIT line below, which contains a map to +# a function to be called when an exit event happens). +processor = SimpleSwitchableProcessor( + starting_core_type=CPUTypes.KVM, + switch_core_type=CPUTypes.TIMING, + isa=ISA.X86, + num_cores=1, +) + +# Here we tell the KVM CPU (the starting CPU) not to use perf. +for proc in processor.start: + proc.core.usePerf = False + +# Here we setup the board. The X86Board allows for Full-System X86 simulations. +board = X86Board( + clk_freq="3GHz", + processor=processor, + memory=memory, + cache_hierarchy=cache_hierarchy, +) + +workload = obtain_resource("x86-ubuntu-24.04-boot-with-systemd") +board.set_workload(workload) +board.append_kernel_arg("interactive=true") # don't execute default script + +def on_exit(): + pass + +simulator = Simulator( + board=board, + on_exit_event={ + ExitEvent.EXIT: on_exit(), + }, +) + +simulator.run() diff --git a/materials/isca24/05-fs-npb.py b/materials/isca24/05-fs-npb.py new file mode 100644 index 00000000..66224797 --- /dev/null +++ b/materials/isca24/05-fs-npb.py @@ -0,0 +1,94 @@ +""" +Simple example to play around with KVM fast-forwarding and switching +between KVM and Timing CPU models. This script boots a Linux kernel +using KVM, runs a simple workload, and then switches to a Timing CPU at +work begin and ends at the work end designation + +To run `gem5-mesi 05-fs-npb.py` +Takes about 30 seconds to boot and 30 seconds to run IS +It's about 1 minute total +""" + +from gem5.coherence_protocol import CoherenceProtocol +from gem5.components.boards.x86_board import X86Board +from gem5.components.cachehierarchies.ruby.mesi_two_level_cache_hierarchy import ( + MESITwoLevelCacheHierarchy, +) +from gem5.components.memory.single_channel import SingleChannelDDR4_2400 +from gem5.components.processors.cpu_types import CPUTypes +from gem5.components.processors.simple_switchable_processor import ( + SimpleSwitchableProcessor, +) +from gem5.isas import ISA +from gem5.resources.resource import obtain_resource +from gem5.simulate.exit_event import ExitEvent +from gem5.simulate.simulator import Simulator +from gem5.utils.requires import requires +import m5 + +# This simulation requires using KVM with gem5 compiled for X86 simulation +# and with MESI_Two_Level cache coherence protocol. +requires( + isa_required=ISA.X86, + coherence_protocol_required=CoherenceProtocol.MESI_TWO_LEVEL, + kvm_required=True, +) + +from gem5.components.cachehierarchies.ruby.mesi_two_level_cache_hierarchy import ( + MESITwoLevelCacheHierarchy, +) + +cache_hierarchy = MESITwoLevelCacheHierarchy( + l1d_size="32KiB", + l1d_assoc=8, + l1i_size="32KiB", + l1i_assoc=8, + l2_size="512KiB", + l2_assoc=16, + num_l2_banks=1, +) + +# Main memory +memory = SingleChannelDDR4_2400(size="3GiB") + +# This is a switchable CPU. We first boot Ubuntu using KVM, then the guest +# will exit the simulation by calling "m5 exit" (see the `command` variable +# below, which contains the command to be run in the guest after booting). +# Upon exiting from the simulation, the Exit Event handler will switch the +# CPU type (see the ExitEvent.EXIT line below, which contains a map to +# a function to be called when an exit event happens). +processor = SimpleSwitchableProcessor( + starting_core_type=CPUTypes.KVM, + switch_core_type=CPUTypes.TIMING, + isa=ISA.X86, + num_cores=1, +) + +# Here we tell the KVM CPU (the starting CPU) not to use perf. +for proc in processor.start: + proc.core.usePerf = False + +# Here we setup the board. The X86Board allows for Full-System X86 simulations. +board = X86Board( + clk_freq="3GHz", + processor=processor, + memory=memory, + cache_hierarchy=cache_hierarchy, +) + +board.set_workload() + +def on_exit(): + print("Exiting the simulation for kernel boot") + yield False + print("Exiting the simulation for systemd complete") + yield False + +simulator = Simulator( + board=board, + on_exit_event={ + ExitEvent.EXIT: on_exit(), + }, +) + +simulator.run() diff --git a/materials/isca24/06-npb-checkpoint.py b/materials/isca24/06-npb-checkpoint.py new file mode 100644 index 00000000..b2c0e430 --- /dev/null +++ b/materials/isca24/06-npb-checkpoint.py @@ -0,0 +1,91 @@ +""" +Example of how to take checkpoint after booting linux. +Most useful for when you have to use a timing CPU to boot, not with KVM. +Let's use KVM so it's fast, though. +Note: Checkpointing with switchable processor is not well supported + +Run with `gem5-mesi 06-npb-checkpoint.py` +""" + +from gem5.coherence_protocol import CoherenceProtocol +from gem5.components.boards.x86_board import X86Board +from gem5.components.cachehierarchies.ruby.mesi_two_level_cache_hierarchy import ( + MESITwoLevelCacheHierarchy, +) +from gem5.components.memory.single_channel import SingleChannelDDR4_2400 +from gem5.components.processors.cpu_types import CPUTypes +from gem5.components.processors.simple_switchable_processor import ( + SimpleSwitchableProcessor, +) +from gem5.isas import ISA +from gem5.resources.resource import obtain_resource +from gem5.simulate.exit_event import ExitEvent +from gem5.simulate.simulator import Simulator +from gem5.utils.requires import requires +import m5 + +# This simulation requires using KVM with gem5 compiled for X86 simulation +# and with MESI_Two_Level cache coherence protocol. +requires( + isa_required=ISA.X86, + coherence_protocol_required=CoherenceProtocol.MESI_TWO_LEVEL, + kvm_required=True, +) + +from gem5.components.cachehierarchies.classic.private_l1_shared_l2_cache_hierarchy import ( + PrivateL1SharedL2CacheHierarchy, +) + +caches = PrivateL1SharedL2CacheHierarchy( + l1d_size="32KiB", + l1d_assoc=8, + l1i_size="32KiB", + l1i_assoc=8, + l2_size="256KiB", + l2_assoc=16, +) + +# Main memory +memory = SingleChannelDDR4_2400(size="3GiB") + +# This is a switchable CPU. We first boot Ubuntu using KVM, then the guest +# will exit the simulation by calling "m5 exit" (see the `command` variable +# below, which contains the command to be run in the guest after booting). +# Upon exiting from the simulation, the Exit Event handler will switch the +# CPU type (see the ExitEvent.EXIT line below, which contains a map to +# a function to be called when an exit event happens). +processor = SimpleSwitchableProcessor( + starting_core_type=CPUTypes.KVM, + switch_core_type=CPUTypes.TIMING, + isa=ISA.X86, + num_cores=1, +) + +# Here we tell the KVM CPU (the starting CPU) not to use perf. +for proc in processor.start: + proc.core.usePerf = False + +# Here we setup the board. The X86Board allows for Full-System X86 simulations. +board = X86Board( + clk_freq="3GHz", + processor=processor, + memory=memory, + cache_hierarchy=caches, +) + +board.set_workload(obtain_resource("x86-ubuntu-24.04-npb-is-s-run")) + +def on_exit(): + print("Exiting the simulation for kernel boot") + yield False + print("Exiting the simulation for systemd complete") + print("Checkpointing") + +simulator = Simulator( + board=board, + on_exit_event={ + ExitEvent.EXIT: on_exit(), + }, +) + +simulator.run() diff --git a/materials/isca24/06-npb-restore.py b/materials/isca24/06-npb-restore.py new file mode 100644 index 00000000..c0888362 --- /dev/null +++ b/materials/isca24/06-npb-restore.py @@ -0,0 +1,112 @@ +""" +Example of how to take restore from a checkpoint taken after booting linux. +Most useful for when you have to use a timing CPU to boot, not with KVM. +Let's use KVM so it's fast, though. +Note: Checkpointing with switchable processor is not well supported + +This script changes the CPU type to O3 as an example of what can change +(Note: It's not a great example... but it's an example) + +Run with `gem5-mesi 06-npb-restore.py` + +When running SP instead of IS, it takes about 5 minutes with timing CPU and +15 minutes with O3 +""" + +from gem5.coherence_protocol import CoherenceProtocol +from gem5.components.boards.x86_board import X86Board +from gem5.components.cachehierarchies.ruby.mesi_two_level_cache_hierarchy import ( + MESITwoLevelCacheHierarchy, +) +from gem5.components.memory.single_channel import SingleChannelDDR4_2400 +from gem5.components.processors.cpu_types import CPUTypes +from gem5.components.processors.simple_switchable_processor import ( + SimpleSwitchableProcessor, +) +from gem5.isas import ISA +from gem5.resources.resource import obtain_resource, CheckpointResource +from gem5.simulate.exit_event import ExitEvent +from gem5.simulate.simulator import Simulator +from gem5.utils.requires import requires +import m5 + +# This simulation requires using KVM with gem5 compiled for X86 simulation +# and with MESI_Two_Level cache coherence protocol. +requires( + isa_required=ISA.X86, + coherence_protocol_required=CoherenceProtocol.MESI_TWO_LEVEL, + kvm_required=True, +) + +from gem5.components.cachehierarchies.classic.private_l1_shared_l2_cache_hierarchy import ( + PrivateL1SharedL2CacheHierarchy, +) + +caches = PrivateL1SharedL2CacheHierarchy( + l1d_size="32KiB", + l1d_assoc=8, + l1i_size="32KiB", + l1i_assoc=8, + l2_size="256KiB", + l2_assoc=16, +) + +# Main memory +memory = SingleChannelDDR4_2400(size="3GiB") + +# This is a switchable CPU. We first boot Ubuntu using KVM, then the guest +# will exit the simulation by calling "m5 exit" (see the `command` variable +# below, which contains the command to be run in the guest after booting). +# Upon exiting from the simulation, the Exit Event handler will switch the +# CPU type (see the ExitEvent.EXIT line below, which contains a map to +# a function to be called when an exit event happens). +processor = SimpleSwitchableProcessor( + starting_core_type=CPUTypes.KVM, + switch_core_type=, + isa=ISA.X86, + num_cores=1, +) + +# Here we tell the KVM CPU (the starting CPU) not to use perf. +for proc in processor.start: + proc.core.usePerf = False + +# Here we setup the board. The X86Board allows for Full-System X86 simulations. +board = X86Board( + clk_freq="3GHz", + processor=processor, + memory=memory, + cache_hierarchy=caches, +) + +board.set_kernel_disk_workload( + kernel=obtain_resource("x86-linux-kernel-5.4.0-105-generic"), + disk_image=obtain_resource("x86-ubuntu-24.04-npb-img"), + kernel_args=[ + "earlyprintk=ttyS0", + "console=ttyS0", + "lpj=7999923", + "root=/dev/sda2" + ], + readfile_contents=f"echo 12345 | sudo -S /home/gem5/NPB3.4-OMP/bin/is.S.x; sleep 5; m5 exit;", +) + +def on_work_begin(): + print("Work begin. Switching to detailed CPU") + m5.stats.reset() + processor.switch() + yield False + +def on_work_end(): + print("Work end") + yield True + +simulator = Simulator( + board=board, + on_exit_event={ + ExitEvent.WORKBEGIN: on_work_begin(), + ExitEvent.WORKEND: on_work_end(), + }, +) + +simulator.run() diff --git a/materials/isca24/07-multisim.py b/materials/isca24/07-multisim.py new file mode 100644 index 00000000..8568e504 --- /dev/null +++ b/materials/isca24/07-multisim.py @@ -0,0 +1,22 @@ +""" +A small multisim example + +Run with `gem5 -m gem5.utils.multisim 07-multisim.py` +or with `gem5 07-multisim.py -l` to list the ids of the simulators. +or with `gem5 07-multisim.py riscv-npb-is-size-s-run` to run one simulation + +Running all situations on 8 cores takes about 4 minutes since there are 9 +workloads +Running just IS takes about 1 minute +Most workloads finish within 2 minutes. +""" + +from gem5.prebuilt.riscvmatched.riscvmatched_board import RISCVMatchedBoard +from gem5.resources.resource import obtain_resource +from gem5.simulate.simulator import Simulator + +from gem5.utils.multisim import add_simulator + +board = RISCVMatchedBoard() + + diff --git a/materials/isca24/08-simobj/HelloSimObject.py b/materials/isca24/08-simobj/HelloSimObject.py new file mode 100644 index 00000000..2d581442 --- /dev/null +++ b/materials/isca24/08-simobj/HelloSimObject.py @@ -0,0 +1,33 @@ +# Copyright (c) 2021 The Regents of the University of California. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# + +from m5.SimObject import SimObject + +class HelloSimObject(SimObject): + type = "HelloSimObject" + cxx_header = "bootcamp/hello-sim-object/hello_sim_object.hh" + cxx_class = "gem5::HelloSimObject" diff --git a/materials/isca24/08-simobj/completed/HelloSimObject.py b/materials/isca24/08-simobj/completed/HelloSimObject.py new file mode 100644 index 00000000..8167baf1 --- /dev/null +++ b/materials/isca24/08-simobj/completed/HelloSimObject.py @@ -0,0 +1,37 @@ +# Copyright (c) 2021 The Regents of the University of California. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# + +from m5.params import * +from m5.SimObject import SimObject + +class HelloSimObject(SimObject): + type = "HelloSimObject" + cxx_header = "bootcamp/hello-sim-object/hello_sim_object.hh" + cxx_class = "gem5::HelloSimObject" + + time_to_wait = Param.Latency("Time to wait before/between greets.") + number_of_greets = Param.Int(1, "Number of times to greet.") diff --git a/materials/isca24/08-simobj/completed/hello_sim_object.cc b/materials/isca24/08-simobj/completed/hello_sim_object.cc new file mode 100644 index 00000000..2236c577 --- /dev/null +++ b/materials/isca24/08-simobj/completed/hello_sim_object.cc @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2021 The Regents of the University of California. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "bootcamp/hello-sim-object/hello_sim_object.hh" + +#include "base/trace.hh" +#include "debug/HelloExampleFlag.hh" +#include "sim/sim_exit.hh" + +namespace gem5 +{ + +HelloSimObject::HelloSimObject(const Params ¶ms): + SimObject(params), + event([this]{ processEvent(); }, name() + ".event"), + latency(params.time_to_wait), + timesLeft(params.number_of_greets) +{ + DPRINTF(HelloExampleFlag, "%s: Hello World! From a " + "SimObject (constructor).\n", __func__); +} + +void +HelloSimObject::startup() +{ + DPRINTF(HelloExampleFlag, "%s: HelloWorld! From a " + "SimObject (startup).\n", __func__); + + assert(!event.scheduled()); + + schedule(event, curTick() + latency); +} + +void +HelloSimObject::processEvent() +{ + if (timesLeft > 0) { + timesLeft--; + DPRINTF(HelloExampleFlag, "%s: Hello World! Processing an event. " + "%d greets left.\n", __func__, timesLeft); + } + + if (timesLeft == 0) { + DPRINTF(HelloExampleFlag, "%s: Done greeting.\n", __func__); + exitSimLoopNow("No greets left.", 0); + } + + if ((timesLeft > 0) && (!event.scheduled())) { + schedule(event, curTick() + latency); + } +} + +} // namespace gem5 diff --git a/materials/isca24/08-simobj/completed/hello_sim_object.hh b/materials/isca24/08-simobj/completed/hello_sim_object.hh new file mode 100644 index 00000000..f27f8a9a --- /dev/null +++ b/materials/isca24/08-simobj/completed/hello_sim_object.hh @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2021 The Regents of the University of California. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __BOOTCAMP_HELLO_SIM_OBJECT_HELLO_SIM_OBJECT_HH__ +#define __BOOTCAMP_HELLO_SIM_OBJECT_HELLO_SIM_OBJECT_HH__ + +#include "params/HelloSimObject.hh" +#include "sim/sim_object.hh" + +namespace gem5 +{ + +class HelloSimObject : public SimObject +{ + private: + EventFunctionWrapper event; + + void processEvent(); + + const Tick latency; + + int timesLeft; + + public: + PARAMS(HelloSimObject); + HelloSimObject(const Params& params); + + virtual void startup() override; +}; + +} // namespace gem5 + +#endif // __BOOTCAMP_HELLO_SIM_OBJECT_HELLO_SIM_OBJECT_HH__ diff --git a/materials/isca24/08-simobj/hello_sim_object.cc b/materials/isca24/08-simobj/hello_sim_object.cc new file mode 100644 index 00000000..f1ef3c66 --- /dev/null +++ b/materials/isca24/08-simobj/hello_sim_object.cc @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2021 The Regents of the University of California. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "bootcamp/hello-sim-object/hello_sim_object.hh" + +#include + +namespace gem5 +{ + +HelloSimObject::HelloSimObject(const Params ¶ms): + SimObject(params) +{ + std::cout << "Hello World! From a SimObject (constructor)." << std::endl; +} + +} // namespace gem5 diff --git a/materials/isca24/08-simobj/hello_sim_object.hh b/materials/isca24/08-simobj/hello_sim_object.hh new file mode 100644 index 00000000..a486879b --- /dev/null +++ b/materials/isca24/08-simobj/hello_sim_object.hh @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2021 The Regents of the University of California. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __BOOTCAMP_HELLO_SIM_OBJECT_HELLO_SIM_OBJECT_HH__ +#define __BOOTCAMP_HELLO_SIM_OBJECT_HELLO_SIM_OBJECT_HH__ + +#include "params/HelloSimObject.hh" +#include "sim/sim_object.hh" + +namespace gem5 +{ + +class HelloSimObject : public SimObject +{ + public: + PARAMS(HelloSimObject); + HelloSimObject(const Params& params); +}; + +} // namespace gem5 + +#endif // __BOOTCAMP_HELLO_SIM_OBJECT_HELLO_SIM_OBJECT_HH__ diff --git a/materials/isca24/0n-se-binary-resource.py b/materials/isca24/0n-se-binary-resource.py new file mode 100644 index 00000000..7f63ab51 --- /dev/null +++ b/materials/isca24/0n-se-binary-resource.py @@ -0,0 +1,5 @@ + + +board.set_se_binary_resource( + +("x86-hello64-static")) diff --git a/materials/isca24/10-gpufs/Makefile b/materials/isca24/10-gpufs/Makefile new file mode 100644 index 00000000..db6479ad --- /dev/null +++ b/materials/isca24/10-gpufs/Makefile @@ -0,0 +1,24 @@ +HIP_PATH?= /opt/rocm +HIPCC=$(HIP_PATH)/bin/hipcc + +BIN_DIR?= ./bin + +GEM5_PATH?=/workspaces/gem5-bootcamp-env/gem5 + +CXXFLAGS=-I$(GEM5_PATH)/include +CXXFLAGS+=-I$(GEM5_PATH)/util/m5/src +LDFLAGS=-L$(GEM5_PATH)/util/m5/build/x86/out +LDFLAGS+=-lm5 + +square: $(BIN_DIR)/square + +$(BIN_DIR)/square: square.cpp $(BIN_DIR) + $(HIPCC) --amdgpu-target=gfx801,gfx803,gfx900,gfx902,gfx90a $(CXXFLAGS) square.cpp -o $(BIN_DIR)/square $(CXXFLAGS) $(LDFLAGS) + +$(BIN_DIR): + mkdir -p $(BIN_DIR) + +clean: + rm -rf $(BIN_DIR) + +.PHONY: square clean diff --git a/materials/isca24/10-gpufs/README.md b/materials/isca24/10-gpufs/README.md new file mode 100644 index 00000000..1b6a16b0 --- /dev/null +++ b/materials/isca24/10-gpufs/README.md @@ -0,0 +1,62 @@ +## Note on running GPU FS + +You need not use docker to run simulations in GPU FS mode. We will be simulating AMD's latest GPU, MI300, in FS mode + +#If you haven't built m5ops yet, then + +```sh +cd /workspaces/gem5-bootcamp-env/gem5/util/m5 +``` +```sh +scons build/x86/out/m5 +``` + +#To compile square for MI300 + +```sh +cd /workspaces/gem5-bootcamp-env/gem5-resources/src/gpu/square +``` +```sh +cp /workspaces/gem5-bootcamp-env/materials/isca24/10-gpufs/Makefile ./ +``` +```sh +make +``` + +#To run square in FS mode + +```sh +cd /workspaces/gem5-bootcamp-env +``` +```sh +/usr/local/bin/gem5-vega gem5/configs/example/gpufs/mi200.py --kernel ./vmlinux-gpu-ml-isca --disk-image ./x86-ubuntu-gpu-ml-isca --app ./gem5-resources/src/gpu/square/bin/square --no-kvm-perf +``` + +#To create a checkpoint (assuming m5_checkpoint_addr() is already included in the application), we need to recompile square so that it creates a checkpoint + +```sh +cp materials/isca24/10-gpufs/square-cpt/square.cpp gem5-resources/src/gpu/square/ +``` +```sh +cp materials/isca24/10-gpufs/mi300.py gem5/configs/example/gpufs/ +``` +```sh +cd gem5-resources/src/gpu/square +``` +```sh +make clean && make +``` + +# To create checkpoint + +```sh +cd /workspaces/gem5-bootcamp-env +``` +```sh +/usr/local/bin/gem5-vega gem5/configs/example/gpufs/mi200.py --kernel ./vmlinux-gpu-ml-isca --disk-image ./x86-ubuntu-gpu-ml-isca --app ./gem5-resources/src/gpu/square/bin/square --no-kvm-perf --checkpoint-dir ./m5out +``` + +# To restore +```sh +/usr/local/bin/gem5-vega gem5/configs/example/gpufs/mi200.py --kernel ./vmlinux-gpu-ml-isca --disk-image ./x86-ubuntu-gpu-ml-isca --app ./gem5-resources/src/gpu/square/bin/square --no-kvm-perf --restore-dir ./m5out +``` diff --git a/materials/isca24/10-gpufs/mi300.py b/materials/isca24/10-gpufs/mi300.py new file mode 100644 index 00000000..69882332 --- /dev/null +++ b/materials/isca24/10-gpufs/mi300.py @@ -0,0 +1,172 @@ +# Copyright (c) 2024 Advanced Micro Devices, Inc. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# 3. Neither the name of the copyright holder nor the names of its +# contributors may be used to endorse or promote products derived from this +# software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. + +""" This file creates an X86 system with a KVM CPU and GPU device capable of +running the MI300 ISA (gfx942). Most of this file sets up a runscript which +will load in a binary, shell script, or python file from the host and run that +within gem5. Jump to line 146 for list of system parameters to configure. +""" + +import argparse +import base64 +import os +import sys +import tempfile +from typing import Optional + +import runfs +from amd import AmdGPUOptions +from common import ( + GPUTLBOptions, + Options, +) +from ruby import Ruby + +import m5 + +from gem5.resources.resource import AbstractResource + +demo_runscript_without_checkpoint = """\ +export LD_LIBRARY_PATH=/opt/rocm/lib:$LD_LIBRARY_PATH +export HSA_ENABLE_INTERRUPT=0 +export HCC_AMDGPU_TARGET=gfx942 +export HSA_OVERRIDE_GFX_VERSION="9.4.2" +dmesg -n8 +cat /proc/cpuinfo +dd if=/root/roms/mi200.rom of=/dev/mem bs=1k seek=768 count=128 +if [ ! -f /lib/modules/`uname -r`/updates/dkms/amdgpu.ko ]; then + echo "ERROR: Missing DKMS package for kernel `uname -r`. Exiting gem5." + /sbin/m5 exit +fi +modprobe -v amdgpu ip_block_mask=0x6f ppfeaturemask=0 dpm=0 audio=0 ras_enable=0 +echo "Running {} {}" +echo "{}" | base64 -d > myapp +chmod +x myapp +./myapp {} +/sbin/m5 exit +""" + +demo_runscript_with_checkpoint = """\ +export LD_LIBRARY_PATH=/opt/rocm/lib:$LD_LIBRARY_PATH +export HSA_ENABLE_INTERRUPT=0 +export HCC_AMDGPU_TARGET=gfx942 +export HSA_OVERRIDE_GFX_VERSION="9.4.2" +dmesg -n8 +dd if=/root/roms/mi200.rom of=/dev/mem bs=1k seek=768 count=128 +if [ ! -f /lib/modules/`uname -r`/updates/dkms/amdgpu.ko ]; then + echo "ERROR: Missing DKMS package for kernel `uname -r`. Exiting gem5." + /sbin/m5 exit +fi +modprobe -v amdgpu ip_block_mask=0x6f ppfeaturemask=0 dpm=0 audio=0 ras_enable=0 +echo "Running {} {}" +echo "{}" | base64 -d > myapp +chmod +x myapp +./myapp {} +/sbin/m5 exit +""" + + +def addDemoOptions(parser): + parser.add_argument( + "-a", "--app", default=None, help="GPU application to run" + ) + parser.add_argument( + "-o", "--opts", default="", help="GPU application arguments" + ) + + +def runMI300GPUFS( + cpu_type, + disk: Optional[AbstractResource] = None, + kernel: Optional[AbstractResource] = None, + app: Optional[AbstractResource] = None, +): + parser = argparse.ArgumentParser() + runfs.addRunFSOptions(parser) + Options.addCommonOptions(parser) + AmdGPUOptions.addAmdGPUOptions(parser) + Ruby.define_options(parser) + GPUTLBOptions.tlb_options(parser) + addDemoOptions(parser) + + # Parse now so we can override options + args = parser.parse_args() + demo_runscript = "" + + if disk != None: + args.disk_image = disk.get_local_path() + if kernel != None: + args.kernel = kernel.get_local_path() + if app != None: + args.app = app.get_local_path() + + # Create temp script to run application + if not os.path.isfile(args.app): + print("Could not find applcation", args.app) + sys.exit(1) + + # Choose runscript Based on whether any checkpointing args are set + if args.checkpoint_dir is not None: + demo_runscript = demo_runscript_with_checkpoint + else: + demo_runscript = demo_runscript_without_checkpoint + + with open(os.path.abspath(args.app), "rb") as binfile: + encodedBin = base64.b64encode(binfile.read()).decode() + + _, tempRunscript = tempfile.mkstemp() + with open(tempRunscript, "w") as b64file: + runscriptStr = demo_runscript.format( + args.app, args.opts, encodedBin, args.opts + ) + b64file.write(runscriptStr) + + args.script = tempRunscript + + # Defaults for CPU + args.cpu_type = "X86KvmCPU" + args.mem_size = "8GB" + + # Defaults for MI300X + args.gpu_device = "MI300X" + args.dgpu_mem_size = "16GB" # GPU memory size, must be 16GB currently. + + # See: https://rocm.docs.amd.com/en/latest/conceptual/gpu-arch/mi300.html + # Topology for one XCD. Number of CUs is approximately 304 / 8, rounded + # up to 40 due to gem5 restriction of 4 CUs per SQC / scalar cache. + args.num_compute_units = 40 + args.gpu_topology = "Crossbar" + + # Run gem5 + runfs.runGpuFSSystem(args) + + +if __name__ == "__m5_main__": + runMI300GPUFS("X86KvmCPU") + diff --git a/materials/isca24/10-gpufs/square-cpt/square.cpp b/materials/isca24/10-gpufs/square-cpt/square.cpp new file mode 100644 index 00000000..044057b3 --- /dev/null +++ b/materials/isca24/10-gpufs/square-cpt/square.cpp @@ -0,0 +1,94 @@ +/* +Copyright (c) 2015-2016 Advanced Micro Devices, Inc. All rights reserved. + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. +*/ + +#include +#include "hip/hip_runtime.h" +#include "gem5/m5ops.h" +#include + +#define CHECK(cmd) \ +{\ + hipError_t error = cmd;\ + if (error != hipSuccess) { \ + fprintf(stderr, "error: '%s'(%d) at %s:%d\n", hipGetErrorString(error), error,__FILE__, __LINE__); \ + exit(EXIT_FAILURE);\ + }\ +} + +/* + * Square each element in the array A and write to array C. + */ +template +__global__ void +vector_square(T *C_d, const T *A_d, size_t N) +{ + size_t offset = (hipBlockIdx_x * hipBlockDim_x + hipThreadIdx_x); + size_t stride = hipBlockDim_x * hipGridDim_x ; + + for (size_t i=offset; i + +## Welcome to the gem5 bootcamp! + +--- + +## About the overall structure of the bootcamp + +- People presenting +- People attending + +--- + +## Plan for the week + +- Introduction + - [Background on simulation](01-simulation-background.md): 1 hour (Jason) + - What is is simulation and why does it matter + - gem5 history + - [Getting started with gem5](02-getting-started.md): 30 minutes (Jason) + - Getting into the codespace environment + - Running your first simulation + - [Background on Python and gem5](03-python-background.md): 1.5 hours (Bobby) + - Python basics + - Python in gem5 + - Object-oriented programming in Python +- Using gem5 + - [gem5's standard library](../02-Using-gem5/01-stdlib.md): 2 hours (Bobby) + - [gem5 resources](../02-Using-gem5/02-gem5-resources.md): 1 hour (Harshil) + - What are resources? (Disks, kernels, binaries, etc.) + - How to get resources + - How to use resources + - Workloads and suites + - Local resources + - [Running things in gem5](../02-Using-gem5/03-running-in-gem5.md): 2 hours (Erin / Zhantong) + - Intro to syscall emulation mode + - The gem5-bridge utility and library + - Cross compiling + - Traffic generator (Test board) + - Process.map and drivers in SE mode (maybe cut) + - [Modeling cores in gem5](../02-Using-gem5/04-cores.md): 1 hour (Mysore / Jason) + - CPU models in gem5 + - Using the CPU models + - Branch predictors + - Look at the gem5 generated statistics + - Overview of ISAs and tradeoffs + - [Modeling caches in gem5](../02-Using-gem5/05-cache-hierarchies.md): 1.5 hour (Leo / Mahyar) + - Cache models in gem5 (Ruby and classic) + - Using the cache models + - Replacement policies + - Tag policies + - Tradeoffs between classic and Ruby + - Look at the gem5 generated statistics + - Garnet/network-on-chip + - CHI protocol + - [Modeling memory in gem5](../02-Using-gem5/06-memory.md) 1 hours (Noah / William (Maryam)) + - Memory models in gem5 () + - Using the memory models + - Testing memory with traffic generators + - Comm Monitor + - [Full system simulation](../02-Using-gem5/07-full-system.md) (Harshil) 1 hour + - What is full system simulation? + - Basics of booting up a real system in gem5 + - Creating disk images using packer and qemu + - Extending/modifying a gem5 disk image + - m5term to interact with a running system + - [Accelerating simulation](../02-Using-gem5/08-accelerating-simulation.md) (Zhantong) 0.5 hours + - KVM fast forwarding + - Checkpointing + - [Sampled simulation with gem5](../02-Using-gem5/09-sampling.md) (Zhantong) 1.5 hours + - Simpoint & Looppoint ideas + - Simpoint & Loopoint analysis + - Simpoint & Loopoint checkpoints + - How to analyze sampled simulation data + - Statistical simulation ideas + - Statistical simulation running and analysis + - [Multisim](../02-Using-gem5/10-multisim.md) (Bobby) (10 minutes) + - Example using multisim + - [Power modeling](../02-Using-gem5/10-modeling-power.md) (Jason?) +- Developing + - [SimObject intro](../03-Developing-gem5-models/01-sim-objects-intro.md) (Mahyar) 0.5 hours + - Development environment, code style, git branches + - The most simple `SimObject` + - Simple run script + - How to add parameters to a `SimObject` + - [Debugging and debug flags](../03-Developing-gem5-models/02-debugging-gem5.md) (Mahyar) 0.5 hours + - How to enable debug flags (examples of DRAM and Exec) + - `--debug-help` + - Adding a new debug flag + - Functions other than DPRINTF + - Panic/fatal/assert + - gdb? + - [Event-driven simulation](../03-Developing-gem5-models/03-event-driven-sim.md) (Mahyar) 1 hours + - Creating a simple callback event + - Scheduling events + - Modeling bandwidth and latency with events + - Other SimObjects as parameters + - Hello/Goodbye example with buffer + - Clock domains? + - [Ports and memory-based SimObjects](../03-Developing-gem5-models/04-ports.md) (Mahyar) 1 hours + - Idea of ports (request/response), packets, interface + - A simple memory object that forwards things + - Connecting ports and writing config files + - Adding stats to a SimObject + - [Modeling Cores](../03-Developing-gem5-models/05-modeling-cores.md) (Bobby) 1.5 hours + - New instructions + - How the execution model works + - Debugging + - [Modeling cache coherence with Ruby and SLICC](../03-Developing-gem5-models/06-modeling-cache-coherence.md) (Jason) 1.5 hours + - Ruby intro + - Structure of SLICC + - Building/running/configuring protocols + - Debugging + - Ruby network + - (Note to Jason: could do a whole day here if split like before.) + - [Extending gem5](../03-Developing-gem5-models/07-extending-gem5-models.md) (Zhantong) 0.5 hours + - Probe points + - Base utilites (e.g., bitset) + - Random numbers + - Signal ports? +- [GPU modeling](../04-GPU-model/01-intro.md) (Matt S.) +- Other simulators (Jason?) + - [SST](../05-Other-simulators/01-sst.md) + - [DRAMSim/DRAMSys](../05-Other-simulators/02-dram.md) + - [SystemC](../05-Other-simulators/03-systemc.md) + +--- + +## Our goals for the gem5 bootcamp + +- Make gem5 less painful and flatten the learning curve +- Give you a vocabulary for asking questions​ +- Provide a reference for the future​ +- Give you material to take back and teach your colleagues + +--- + +## How this is going to work + +- We'll be going mostly top-down + - First: How to use gem5 + - Second: How to each model can be used + - Third: How to develop your own models and modify existing models +- Highly iterative: + - You'll see the same thing over and over + - Each time it will be one level deeper +- Lots of coding examples + - Both live coding and practice problems + +--- + +## Other admin things + +--- + +## Important resources + +- [Bootcamp website]() +- [Source for bootcamp materials]() (You'll work here) +- [GitHub Classroom]() (Needed to use codespaces) +- [gem5 Slack]() (for asking offline questions) +- [gem5 code](https://github.com/gem5/gem5) +- [gem5 website](https://www.gem5.org/) +- [gem5 YouTube](https://youtube.com/@gem5) + +--- + +## Slides about gem5 + +(Get from PPT) diff --git a/slides/01-Introduction/01-simulation-background.md b/slides/01-Introduction/01-simulation-background.md new file mode 100644 index 00000000..4677aa43 --- /dev/null +++ b/slides/01-Introduction/01-simulation-background.md @@ -0,0 +1,12 @@ +--- +marp: true +paginate: true +theme: gem5 +title: Computer Architecture Simulation +--- + + + +## Computer Architecture Simulation + +--- diff --git a/slides/01-Introduction/02-getting-started-imgs/codespaces-screenshot-1.drawio.png b/slides/01-Introduction/02-getting-started-imgs/codespaces-screenshot-1.drawio.png new file mode 100644 index 00000000..6e9ed54e Binary files /dev/null and b/slides/01-Introduction/02-getting-started-imgs/codespaces-screenshot-1.drawio.png differ diff --git a/slides/01-Introduction/02-getting-started-imgs/resources-screenshot.drawio.png b/slides/01-Introduction/02-getting-started-imgs/resources-screenshot.drawio.png new file mode 100644 index 00000000..1536a6fd Binary files /dev/null and b/slides/01-Introduction/02-getting-started-imgs/resources-screenshot.drawio.png differ diff --git a/slides/01-Introduction/02-getting-started.md b/slides/01-Introduction/02-getting-started.md new file mode 100644 index 00000000..1224a0d6 --- /dev/null +++ b/slides/01-Introduction/02-getting-started.md @@ -0,0 +1,186 @@ +--- +marp: true +paginate: true +theme: gem5 +title: Getting Started with gem5 +--- + + + +## Getting started with gem5 + +In this section, we will get familiar the tutorial's codespace environment and run our first gem5 simulation. + +--- + +## Let’s hit the ground running + +### This example will show + +1. How someone obtains gem5. +2. How you build it. +3. Running a very basic "Hello World" simulation. + +- Getting and compiling gem5 is often the hardest part. +- There's a lot of complicated things happening behind the scenes. We will explain them later. + +--- + +## Typical Downloading + +```sh +> git clone https://github.com/gem5/gem5 +> cd gem5 +``` + +> There are two main branches in the gem5 repository: +> **stable**: The default branch for gem5. Updated at stable releases. Currently v24.0. +> **develop**: The branch in which new features, improvements, etc. are added regularly for the next release. + +In this tutorial we’re going to use codespaces with a repo which includes some example materials. Though all the gem5 code is v24.0 + +--- + +## Using codespaces + +- We will be using the "bootcamp environment" + - Note: That's also where the source for these slides are + +> **Step 1:** Go to the classroom + +You need to be in the github organization (via the classroom) to get free codespaces. + +--- + +## Using codespaces 2 + +**AFTER** joining the classroom, you can go to the repository and click on the green "Code" button. +Again, note that this is the repo where the slides are. + + + +![Screenshot of starting a codespace](02-getting-started-imgs/codespaces-screenshot-1.drawio.png) + +--- + +## Using codespaces 3 + +> **Step 3:** Wait for the environment to load. + +![Screenshot](test.drawio.png) + +--- + +## Building gem5 + +```sh +> scons build/ALL/gem5.opt +``` + +- This takes a while (10-15 minutes with 16 cores, ~1hr on 1 core). +- If you're using codespaces, we have prebuilt binaries for you. +- We'll talk more about the build system and options later. + +[![asciicast](https://asciinema.org/a/6rAd24brgGqb3Sj8Kmvy1msaG.svg)](https://asciinema.org/a/6rAd24brgGqb3Sj8Kmvy1msaG) + + +--- + +## Let’s start by writing a simulation configuration + +```python +from gem5.prebuilt.demo.x86_demo_board import X86DemoBoard +from gem5.resources.resource import obtain_resource +from gem5.simulate.simulator import Simulator +``` + +This template code is available in the [materials/](/materials/...) directory. +Open the `materials/01-basic.py` file and start editing. + +--- + +## Let’s be lazy and use a prebuild board + +```python +board = X86DemoBoard() +``` + +The X86DemoBoard has the following properties: + +- Single Channel DDR3, 2GB Memory. +- A 4 core 3GHz processor (using gem5’s ‘timing’ model). +- A MESI Two Level Cache Hierarchy, with 32kB data and instruction case and a 1MB L2 Cache. +- Will be run as a Full-System simulation. + +Source is available: [src/python/gem5/prebuilt/demo/x86_demo_board.py](/src/python/gem5/prebuilt/demo/x86_demo_board.py). + +--- + +## Let't load some software + +```python +board.set_workload( + obtain_resource("x86-ubuntu-24.04-boot-no-systemd") +) +``` + +- `obtain_resource` downloads the files needed to run workload + - Boots Ubuntu without systemd then exits the simulation + - Downloads disk image, kernel, and sets default parameters + +See the [gem5 resource page](https://resources.gem5.org/resources/x86-ubuntu-24.04-boot-no-systemd?version=1.0.0) + +--- + +## gem5 resources web portal + +[Link](https://resources.gem5.org/resources/x86-ubuntu-24.04-boot-no-systemd?version=1.0.0) + +![Screenshot of gem5 resources webpage](02-getting-started-imgs/resources-screenshot.drawio.png) + +--- + +## Now, let's create a simulator to actually run + +```python +sim = Simulator(board) +sim.run(20_000_000_000) # 20 billion ticks or 20 ms +``` + +--- + +## That's it! + +```python +from gem5.prebuilt.demo.x86_demo_board import X86DemoBoard +from gem5.resources.resource import obtain_resource +from gem5.simulate.simulator import Simulator +board = X86DemoBoard() +board.set_workload( + obtain_resource("x86-ubuntu-24.04-boot-no-systemd") +) +sim = Simulator(board) +sim.run(20_000_000_000) # 20 billion ticks or 20 ms +``` + +To run it: + +```sh +> gem5 materials/01-basic.py +``` + +--- + +## Take aways + +- `gem5` is a Python interpreter. +- The *interface* to `gem5` is Python scripts. +- `gem5` contains many Python libraries. + - All of the models in gem5 (e.g., caches, CPUs, etc.). + - The standard library (stdlib) +- The output of gem5 is in `m5out/` by default. + - Details of configuration + - Other output + - **Statistics** (the most important part) +- The codespaces environment is configured to make things easy. + - You'll need to do some work to set up your own environment. diff --git a/slides/01-Introduction/03-python-background.md b/slides/01-Introduction/03-python-background.md new file mode 100644 index 00000000..47834a68 --- /dev/null +++ b/slides/01-Introduction/03-python-background.md @@ -0,0 +1,18 @@ +--- +marp: true +paginate: true +theme: gem5 +title: gem5 and Python Programming +--- + + + +## gem5 and Python Programming + +--- + +## We will cover + +- Python basics +- Python in gem5 +- Object-oriented programming in Python diff --git a/slides/02-Using-gem5/01-stdlib.md b/slides/02-Using-gem5/01-stdlib.md new file mode 100644 index 00000000..733be9e6 --- /dev/null +++ b/slides/02-Using-gem5/01-stdlib.md @@ -0,0 +1,25 @@ +--- +marp: true +paginate: true +theme: gem5 +title: gem5's Standard Library +--- + + + +## gem5's Standard Library + +--- + +## What is the standard library for? + +- When done without the library you must define *every part* of your simulation +- This allows for maximum flexibility, but it can mean creating 100s of lines of python to create the most basic simulation + +--- + +## Where to find stuff: Importing in a script + +```python +from gem5.components import * +``` diff --git a/slides/02-Using-gem5/02-gem5-resources.md b/slides/02-Using-gem5/02-gem5-resources.md new file mode 100644 index 00000000..c4dd2113 --- /dev/null +++ b/slides/02-Using-gem5/02-gem5-resources.md @@ -0,0 +1,18 @@ +--- +marp: true +paginate: true +theme: gem5 +title: gem5 Resources +--- + + + +## gem5 Resources + +--- + +- What are resources? (Disks, kernels, binaries, etc.) +- How to get resources +- How to use resources +- Workloads and suites +- Local resources diff --git a/slides/02-Using-gem5/03-running-in-gem5.md b/slides/02-Using-gem5/03-running-in-gem5.md new file mode 100644 index 00000000..e4218a61 --- /dev/null +++ b/slides/02-Using-gem5/03-running-in-gem5.md @@ -0,0 +1,21 @@ +--- +marp: true +paginate: true +theme: gem5 +title: Running Things on gem5 +author: "Maryam Babaie" +editor: "Jason Lowe-Power" +--- + + + +## Running Things on gem5 + +--- + +## What we will cover + +- Intro to syscall emulation mode +- The gem5-bridge utility and library +- Cross compiling +- Traffic generator diff --git a/slides/02-Using-gem5/04-cores.md b/slides/02-Using-gem5/04-cores.md new file mode 100644 index 00000000..7ad57638 --- /dev/null +++ b/slides/02-Using-gem5/04-cores.md @@ -0,0 +1,21 @@ +--- +marp: true +paginate: true +theme: gem5 +title: Modeling CPU cores in gem5 +--- + + + +## Modeling CPU cores in gem5 + +--- + +## Outline + +- CPU models in gem5​ + - AtomicSimpleCPU, TimingSimpleCPU, O3CPU, MinorCPU, KvmCPU​ +- Using the CPU models​ + - Set-up a simple system with two cache sizes and three CPU models​ +- Look at the gem5 generated statistics​ + - To understand differences among CPU models diff --git a/slides/02-Using-gem5/05-cache-hierarchies.md b/slides/02-Using-gem5/05-cache-hierarchies.md new file mode 100644 index 00000000..16899770 --- /dev/null +++ b/slides/02-Using-gem5/05-cache-hierarchies.md @@ -0,0 +1,12 @@ +--- +marp: true +paginate: true +theme: gem5 +title: Modeling caches in gem5 +--- + + + +## Modeling caches in gem5 + +--- diff --git a/slides/02-Using-gem5/06-memory.md b/slides/02-Using-gem5/06-memory.md new file mode 100644 index 00000000..43a185ac --- /dev/null +++ b/slides/02-Using-gem5/06-memory.md @@ -0,0 +1,18 @@ +--- +marp: true +paginate: true +theme: gem5 +title: Modeling DRAM in gem5 +--- + + + +## Modeling DRAM in gem5 + +--- + +I don't think this exists, yet. + +Doing some stuff about the traffic generators and testing memory controllers would be a good idea. + +Show examples of interleaved memory, HBM, hybrid memory would be good. diff --git a/slides/02-Using-gem5/07-full-system.md b/slides/02-Using-gem5/07-full-system.md new file mode 100644 index 00000000..e860b825 --- /dev/null +++ b/slides/02-Using-gem5/07-full-system.md @@ -0,0 +1,20 @@ +--- +marp: true +paginate: true +theme: gem5 +title: Full system simulation in gem5 +--- + + + +## Full system simulation in gem5 + +--- + +## What we will cover + +- What is full system simulation? +- Basics of booting up a real system in gem5 +- Creating disk images using packer and qemu +- Extending/modifying a gem5 disk image +- m5term to interact with a running system diff --git a/slides/02-Using-gem5/08-accelerating-simulation.md b/slides/02-Using-gem5/08-accelerating-simulation.md new file mode 100644 index 00000000..c0fb4a29 --- /dev/null +++ b/slides/02-Using-gem5/08-accelerating-simulation.md @@ -0,0 +1,14 @@ +--- +marp: true +paginate: true +theme: gem5 +title: Accelerating gem5 simulations +--- + + + +## Accelerating gem5 simulations + +In this section, we will cover how to accelerate gem5 simulations using fast-forwarding and checkpointing. + +--- diff --git a/slides/02-Using-gem5/09-sampling.md b/slides/02-Using-gem5/09-sampling.md new file mode 100644 index 00000000..a1bf0410 --- /dev/null +++ b/slides/02-Using-gem5/09-sampling.md @@ -0,0 +1,14 @@ +--- +marp: true +paginate: true +theme: gem5 +title: Sampled simulation with gem5 +--- + + + +## Sampled simulation with gem5 + +--- + +This is all new! diff --git a/slides/02-Using-gem5/10-modeling-power.md b/slides/02-Using-gem5/10-modeling-power.md new file mode 100644 index 00000000..d866a248 --- /dev/null +++ b/slides/02-Using-gem5/10-modeling-power.md @@ -0,0 +1,18 @@ +--- +marp: true +paginate: true +theme: gem5 +title: Modeling Power in gem5 +--- + + + +## Modeling Power in gem5 + +--- + +## What we will cover + +- Idea behind power modeling +- The `MathExprPowerModel` +- An example diff --git a/slides/03-Developing-gem5-models/01-sim-objects-intro.md b/slides/03-Developing-gem5-models/01-sim-objects-intro.md new file mode 100644 index 00000000..baca37d1 --- /dev/null +++ b/slides/03-Developing-gem5-models/01-sim-objects-intro.md @@ -0,0 +1,21 @@ +--- +marp: true +paginate: true +theme: gem5 +title: Developing SimObjects in gem5 +--- + + + +## Developing `SimObjects` in gem5 + +In this section, you will go from a blank page to a cache! + +--- + +## We will cover + +- Development environment, code style, git branches +- The most simple `SimObject` +- Simple run script +- How to add parameters to a `SimObject` diff --git a/slides/03-Developing-gem5-models/02-debugging-gem5.md b/slides/03-Developing-gem5-models/02-debugging-gem5.md new file mode 100644 index 00000000..96ba39b7 --- /dev/null +++ b/slides/03-Developing-gem5-models/02-debugging-gem5.md @@ -0,0 +1,21 @@ +--- +marp: true +paginate: true +theme: gem5 +title: Debugging and Debug Flags +--- + + + +## Debugging and debug flags + +--- + +## We will cover + +- How to enable debug flags (examples of DRAM and Exec) +- `--debug-help` +- Adding a new debug flag +- Functions other than DPRINTF +- Panic/fatal/assert +- gdb? diff --git a/slides/03-Developing-gem5-models/03-event-driven-sim.md b/slides/03-Developing-gem5-models/03-event-driven-sim.md new file mode 100644 index 00000000..6a894ada --- /dev/null +++ b/slides/03-Developing-gem5-models/03-event-driven-sim.md @@ -0,0 +1,20 @@ +--- +marp: true +paginate: true +theme: gem5 +title: Programming Event-Driven Simulation +--- + + + +## Programming Event-Driven Simulation + +Here you'll learn how to actually model architecture! + +--- + +- Creating a simple callback event +- Scheduling events +- Modeling bandwidth and latency with events +- Other SimObjects as parameters +- Hello/Goodbye example with buffer diff --git a/slides/03-Developing-gem5-models/04-ports.md b/slides/03-Developing-gem5-models/04-ports.md new file mode 100644 index 00000000..75f06453 --- /dev/null +++ b/slides/03-Developing-gem5-models/04-ports.md @@ -0,0 +1,17 @@ +--- +marp: true +paginate: true +theme: gem5 +title: "Modeling memory objects in gem5: Ports" +--- + + + +## Modeling memory objects in gem5: Ports + +--- + +- Idea of ports (request/response), packets, interface +- A simple memory object that forwards things +- Connecting ports and writing config files +- Adding stats to a SimObject diff --git a/slides/03-Developing-gem5-models/05-modeling-cores.md b/slides/03-Developing-gem5-models/05-modeling-cores.md new file mode 100644 index 00000000..ae0ed94b --- /dev/null +++ b/slides/03-Developing-gem5-models/05-modeling-cores.md @@ -0,0 +1,21 @@ +--- +marp: true +paginate: true +theme: gem5 +title: Modeling Cores in gem5 +--- + + + +## Modeling Cores in gem5 + +--- + +## Outline + +- How the execution model works in gem5 +- The idea of how gem5 separates microarchitecture from ISA +- How translation works in gem5 +- How instructions are executed in gem5 +- How to add a new instruction +- How the ISA language works in gem5 diff --git a/slides/03-Developing-gem5-models/06-modeling-cache-coherence.md b/slides/03-Developing-gem5-models/06-modeling-cache-coherence.md new file mode 100644 index 00000000..2ea4d38b --- /dev/null +++ b/slides/03-Developing-gem5-models/06-modeling-cache-coherence.md @@ -0,0 +1,18 @@ +--- +marp: true +paginate: true +theme: gem5 +title: Modeling Cache Coherence in gem5 +--- + + + +## Modeling Cache Coherence in gem5 + +--- + +## Outline + +This is all about Ruby/slicc + +- Network/garnet diff --git a/slides/03-Developing-gem5-models/07-extending-gem5-models.md b/slides/03-Developing-gem5-models/07-extending-gem5-models.md new file mode 100644 index 00000000..bf7fa18b --- /dev/null +++ b/slides/03-Developing-gem5-models/07-extending-gem5-models.md @@ -0,0 +1,19 @@ +--- +marp: true +paginate: true +theme: gem5 +title: Developing SimObjects in gem5 +--- + + + +## Tools to extend gem5 models + +--- + +## We will cover + +- Probe points +- Base utilities like bitsets +- Random number generation +- Signal ports? diff --git a/slides/04-GPU-model/01-intro.md b/slides/04-GPU-model/01-intro.md new file mode 100644 index 00000000..6afb2e38 --- /dev/null +++ b/slides/04-GPU-model/01-intro.md @@ -0,0 +1,12 @@ +--- +marp: true +paginate: true +theme: gem5 +title: gem5's GPU model +--- + + + +## gem5's GPU model + +--- diff --git a/slides/05-Other-simulators/01-sst.md b/slides/05-Other-simulators/01-sst.md new file mode 100644 index 00000000..e69de29b diff --git a/slides/05-Other-simulators/02-dram.md b/slides/05-Other-simulators/02-dram.md new file mode 100644 index 00000000..48aac9ed --- /dev/null +++ b/slides/05-Other-simulators/02-dram.md @@ -0,0 +1,15 @@ +--- +marp: true +paginate: true +theme: gem5 +title: Extending gem5 with DRAMSim and DRAMSys +--- + + + +## Extending gem5 with DRAMSim and DRAMSys + +--- + +- DRAMSim +- DRAMSys diff --git a/slides/05-Other-simulators/03-systemc.md b/slides/05-Other-simulators/03-systemc.md new file mode 100644 index 00000000..e228e0eb --- /dev/null +++ b/slides/05-Other-simulators/03-systemc.md @@ -0,0 +1,16 @@ +--- +marp: true +paginate: true +theme: gem5 +title: Extending gem5 with SystemC +--- + + + +## Extending gem5 with SystemC + +--- + +- What is SystemC +- SystemC in gem5 +- gem5 in SystemC diff --git a/slides/06-Contributing/01-contributing.md b/slides/06-Contributing/01-contributing.md new file mode 100644 index 00000000..6719c3f4 --- /dev/null +++ b/slides/06-Contributing/01-contributing.md @@ -0,0 +1,15 @@ +--- +marp: true +paginate: true +theme: gem5 +title: Contributing to gem5 +author: Jason Lowe-Power +--- + + + +## Contributing to gem5 + +Learn to create PRs, issues, and review code in gem5. + +--- diff --git a/slides/06-Contributing/02-testing.md b/slides/06-Contributing/02-testing.md new file mode 100644 index 00000000..333253b3 --- /dev/null +++ b/slides/06-Contributing/02-testing.md @@ -0,0 +1,15 @@ +--- +marp: true +paginate: true +theme: gem5 +title: Running gem5 Tests +author: Jason Lowe-Power +--- + + + +## Running gem5 Tests + +Learn to run, interpret the output, and add new tests to gem5. + +--- diff --git a/slides/README.md b/slides/README.md new file mode 100644 index 00000000..25e9c070 --- /dev/null +++ b/slides/README.md @@ -0,0 +1,44 @@ +# Slides for the gem5 bootcamp + +In this directory, you will find the slides that we use during the gem5 bootcamp and gem5 tutorials. +They are written using [Marp](https://marp.app/), a Markdown-based slide design tool. + +We chose to use Markdown for slides to make it easier for us to update the code in the slides as gem5 changes and for the participants to copy-paste code. + +To use Marp, we encourage you to install the [VS Code extension](https://marketplace.visualstudio.com/items?itemName=marp-team.marp-vscode), which should be automatically installed if you're using the codespaces devcontainer. +With the VS Code extension installed, when you open one of the slide decks (e.g., [Getting started](02-Using gem5/00-getting-started.md)), you can click on the preview button in the upper right to view the slides. +Also, you can use the Marp extension to save the slides as HTML or PDF. + +For using the Marp command line, you can use the following command (pass in the file to convert). +Note: The local paths for the css file and the markdown don't work great. YMMV. + +```sh +docker run --rm -v $PWD:/home/marp/app/ -e MARP_USER=$UID:$GID -e LANG=$LANG marpteam/marp-cli +``` + +## Style rules + +- INSTALL THE [MARKDOWN LINT EXTENSION IN VS CODE](https://marketplace.visualstudio.com/items?itemName=DavidAnson.vscode-markdownlint) TO HELP WITH FORMATTING. +- Use `---` to separate slides. +- The first slide should be a "title" slide ``. +- The titles of all slides should be heading 2 `##` +- Code should be at most 65 characters wide. +- One line per sentence in Markdown. + +## Adding diagrams + +To add diagrams, you can use the [draw.io VS Code extension](https://marketplace.visualstudio.com/items?itemName=hediet.vscode-drawio). + +After installing the extension, create a file with the name "\.drawio.png" and open it in VS Code. +Make sure you create a directory for each slide deck with its images. +You can then embed the image in the slide with the following markdown. + +```md +![](/.drawio.png) +``` + +## Improvement to make + +- [ ] Fix `[bg left]` `[bg right]` in the slides so that the gem5 logo at the bottom doesn't move +- [ ] Extend marp to support [asciinema](https://github.com/asciinema/asciinema-player/releases/tag/v3.8.0) + - We could [embed an SVG](https://docs.asciinema.org/manual/server/embedding/#preview-image-link). diff --git a/slides/themes/gem5.css b/slides/themes/gem5.css new file mode 100644 index 00000000..65a0662b --- /dev/null +++ b/slides/themes/gem5.css @@ -0,0 +1,303 @@ +@charset "UTF-8"; +/*! + * Marp gem5 theme + * @theme gem5 + * @author Jason Lowe-Power + * + * @auto-scaling true + * @size 16:9 1280px 720px + * @size 4:3 960px 720px + */ + +@import url('https://fonts.googleapis.com/css2?family=Roboto+Mono:ital,wght@0,100..700;1,100..700&display=swap'); + +:root { + --gem5-gem5: #008EB0; + --gem5-background: #F6F8FA; + --gem5-light: #c8eaf3; + --gem5-dark: #00627a; +} + +section { + font-size: 1.6rem; + font-family: sans-serif; + line-height: 2rem; + padding: 70px; + background-color: var(--gem5-background); + background-image: url("../themes/gem5Long.png"); + background-repeat: no-repeat; + background-position-x: center; + background-size: 220px; + background-position-y: 97%; +} + +/* Move the title of the slide up a bit */ +section>*:first-child, +section>header:first-child+* { + margin-top: 0; +} + +/* Draw a triangle on the left of the title */ +h2::before { + content: ""; + position: absolute; + top: 65px; + left: -10px; + width: 0; + height: 0; + border-left: 30px solid transparent; + border-right: 30px solid transparent; + border-bottom: 40px solid var(--gem5-gem5); + rotate: 90deg; +} + +/* Draw a triangle in the lower right */ +section::before { + content: ""; + position: absolute; + bottom: 0; + right: 0; + width: 0; + height: 0; + border-left: 100px solid transparent; + border-top: 100px solid var(--gem5-gem5); + rotate: 90deg; +} + +/* Add an image to the bottom center of the page */ +footer { + position: fixed; + left: 0; + right: 0; + bottom: 60px; + height: 100px; + margin-bottom: -80px; +} + +footer img { + height: 60px; + display: block; + margin: 0 auto; +} + +/* For the page number */ +section::after { + right: -50px; + bottom: -50px; + font-size: 80%; +} + +a { + color: var(--gem5-gem5); +} + +blockquote { + position: relative; + margin: 0.6rem 0; + padding: 0 1.2rem; + border-left: 4px solid var(--gem5-gem5); + background-color: var(--gem5-light); +} + +blockquote a { + color: var(--gem5-dark); +} + +/****************************************************/ +/* For title page */ +/* Remove the triangle */ +section.title h2::before { + border: none; +} + +/* Remove the triangle in the lower right */ +section.title::before { + border: none; +} + +/* Remove the page number */ +section.title::after { + display: none; +} + +/* Remove the bottom image */ +section.title footer img { + display: none; +} + +section.title h2 { + font-size: 5rem; + line-height: 5rem; + margin-top: 50px; + display: block; + text-align: center; + width: 60%; +} + +/* gem5 logo on the right */ +section.title { + background-image: url("../../slides/themes/gem5ColorVert.png"); + background-repeat: no-repeat; + background-position: right; + background-size: contain; +} + +/* title on the left */ +section.title p { + width: 60%; + font-size: 2.5rem; + line-height: 2.5rem; +} + +/****************************************************/ +/* For code block */ + +pre { + padding: 10px; + border-radius: 5px; + background-color: #ffffff; +} + +code { + font-family: "Roboto Mono", monospace; + font-size: 1.4rem; + background-color: #ffffff; +} + +/*! + Theme: Default + Description: Original highlight.js style + Author: (c) Ivan Sagalaev + Maintainer: @highlightjs/core-team + Website: https://highlightjs.org/ + License: see project LICENSE + Touched: 2021 +*/ + +/* +This is left on purpose making default.css the single file that can be lifted +as-is from the repository directly without the need for a build step + +Typically this "required" baseline CSS is added by `makestuff.js` during build. +*/ + +pre code.hljs { + display: block; + overflow-x: auto; + padding: 1rem; + background-color: #ffffff; +} + +code.hljs { + padding: 3px 5px; +} + +/* end baseline CSS */ + +.hljs { + background: #ffffff; + color: #444; +} + +/* Base color: saturation 0; */ + +.hljs-subst { + /* default */ +} + +/* purposely ignored */ +.hljs-formula, +.hljs-attr, +.hljs-property, +.hljs-params {} + +.hljs-comment { + color: #697070; +} + +.hljs-tag, +.hljs-punctuation { + color: #444a; +} + +.hljs-tag .hljs-name, +.hljs-tag .hljs-attr { + color: #444; +} + + +.hljs-keyword, +.hljs-attribute, +.hljs-selector-tag, +.hljs-meta .hljs-keyword, + +.hljs-doctag, +.hljs-name { + font-weight: bold; +} + + +/* User color: hue: 0 */ + +.hljs-type, +.hljs-string, +.hljs-number, +.hljs-selector-id, +.hljs-selector-class, +.hljs-quote, +.hljs-template-tag, +.hljs-deletion { + color: #880000; +} + +.hljs-title, +.hljs-section { + color: #880000; + font-weight: bold; +} + +.hljs-regexp, +.hljs-symbol, +.hljs-variable, +.hljs-template-variable, +.hljs-link, +.hljs-selector-attr, +.hljs-operator, +.hljs-selector-pseudo { + color: #ab5656; +} + +/* Language color: hue: 90; */ + +.hljs-literal { + color: #695; +} + +.hljs-built_in, +.hljs-bullet, +.hljs-code, +.hljs-addition { + color: #397300; +} + + +/* Meta color: hue: 200 */ + +.hljs-meta { + color: #1f7199; +} + +.hljs-meta .hljs-string { + color: #38a; +} + + +/* Misc effects */ + +.hljs-emphasis { + font-style: italic; +} + +.hljs-strong { + font-weight: bold; +} diff --git a/slides/themes/gem5ColorVert.png b/slides/themes/gem5ColorVert.png new file mode 100644 index 00000000..6ced4671 Binary files /dev/null and b/slides/themes/gem5ColorVert.png differ diff --git a/slides/themes/gem5Long.png b/slides/themes/gem5Long.png new file mode 100644 index 00000000..868aa14f Binary files /dev/null and b/slides/themes/gem5Long.png differ