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ROM0.PLD
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71 lines (67 loc) · 1.95 KB
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Name ROM0;
Partno 1;
Revision 01;
Date 5/20/25;
Designer Sylvain Fortin;
Company Home;
Location Montreal;
Assembly Example;
Device g16v8;
/****************************************************************/
/* ROM LUT */
/* Inputs: C3, C2, C1, C0, PHI2 */
/* Outputs: I_N, RW, DIR, G_N, AL, AH, UL, UH */
/****************************************************************/
/** Inputs **/
PIN 3 = A; // PHI2
PIN 4 = B; // C0
PIN 5 = C; // C1
PIN 6 = D; // C2
PIN 7 = E; // C3
/** Outputs **/
PIN 12 = I_N;
PIN 13 = RW;
PIN 14 = DIR;
PIN 15 = G_N;
PIN 16 = AL;
PIN 17 = AH;
PIN 18 = UL;
PIN 19 = UH;
/** Field Declarations **/
FIELD Address = [E, D, C, B, A];
FIELD OutputBits = [UH, UL, AH, AL, G_N, DIR, RW, I_N]; // 8-bit output
/** Table Mapping **/
TABLE Address => OutputBits {
'b'00000 => 'b'00001011; // REG -> UH
'b'00001 => 'b'10001011;
'b'00010 => 'b'00001011; // REG -> UL
'b'00011 => 'b'01001011;
'b'00100 => 'b'00001011; // REG -> AH
'b'00101 => 'b'00101011;
'b'00110 => 'b'00001011; // REG -> AL
'b'00111 => 'b'00011011;
'b'01000 => 'b'00000011; // DATA -> REG
'b'01001 => 'b'00000011;
'b'01010 => 'b'00001010; // u<7:0> -> REG
'b'01011 => 'b'00001010;
'b'01100 => 'b'00001010; // u<7:0> -> uH
'b'01101 => 'b'10001010;
'b'01110 => 'b'00001010; // u<7:0> -> uL
'b'01111 => 'b'01001010;
'b'10000 => 'b'00001011; // R -> ALU B -> Q
'b'10001 => 'b'00001011;
'b'10010 => 'b'00001011; // A -> Q
'b'10011 => 'b'00001011;
'b'10100 => 'b'00001011; // REG -> A
'b'10101 => 'b'00001011;
'b'10110 => 'b'00000101; // REG -> DATA
'b'10111 => 'b'00000101;
'b'11000 => 'b'00001011; // Q -> REG
'b'11001 => 'b'00001011;
'b'11010 => 'b'00001010; // u<7:0> -> AL
'b'11011 => 'b'00011010;
'b'11100 => 'b'00001011; // Qn -> A
'b'11101 => 'b'00001011;
'b'11110 => 'b'00001010; // u<7:0> -> AH
'b'11111 => 'b'00101010;
}