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Merge branch 'master' into patch-1
2 parents 1260396 + c7520cc commit d556463

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‎.github/ISSUE_TEMPLATE/Issue-report.yml

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Original file line numberDiff line numberDiff line change
@@ -43,6 +43,7 @@ body:
4343
- latest stable Release (if not listed below)
4444
- latest development Release Candidate (RC-X)
4545
- latest master (checkout manually)
46+
- v3.3.0
4647
- v3.2.1
4748
- v3.2.0
4849
- v3.1.3

‎.github/scripts/on-push.sh

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Original file line numberDiff line numberDiff line change
@@ -90,6 +90,7 @@ if [ "$BUILD_LOG" -eq 1 ]; then
9090
fi
9191

9292
#build sketches for different targets
93+
build "esp32c5" "$CHUNK_INDEX" "$CHUNKS_CNT" "$BUILD_LOG" "$LOG_LEVEL" "$SKETCHES_FILE" "${SKETCHES_ESP32[@]}"
9394
build "esp32p4" "$CHUNK_INDEX" "$CHUNKS_CNT" "$BUILD_LOG" "$LOG_LEVEL" "$SKETCHES_FILE" "${SKETCHES_ESP32[@]}"
9495
build "esp32s3" "$CHUNK_INDEX" "$CHUNKS_CNT" "$BUILD_LOG" "$LOG_LEVEL" "$SKETCHES_FILE" "${SKETCHES_ESP32[@]}"
9596
build "esp32s2" "$CHUNK_INDEX" "$CHUNKS_CNT" "$BUILD_LOG" "$LOG_LEVEL" "$SKETCHES_FILE" "${SKETCHES_ESP32[@]}"

‎.github/scripts/sketch_utils.sh

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -156,6 +156,7 @@ function build_sketch { # build_sketch <ide_path> <user_path> <path-to-ino> [ext
156156
esp32c6_opts=$(echo "$debug_level,$fqbn_append" | sed 's/^,*//;s/,*$//;s/,\{2,\}/,/g')
157157
esp32h2_opts=$(echo "$debug_level,$fqbn_append" | sed 's/^,*//;s/,*$//;s/,\{2,\}/,/g')
158158
esp32p4_opts=$(echo "PSRAM=enabled,USBMode=default,$debug_level,$fqbn_append" | sed 's/^,*//;s/,*$//;s/,\{2,\}/,/g')
159+
esp32c5_opts=$(echo "$debug_level,$fqbn_append" | sed 's/^,*//;s/,*$//;s/,\{2,\}/,/g')
159160

160161
# Select the common part of the FQBN based on the target. The rest will be
161162
# appended depending on the passed options.
@@ -191,6 +192,10 @@ function build_sketch { # build_sketch <ide_path> <user_path> <path-to-ino> [ext
191192
[ -n "${options:-$esp32p4_opts}" ] && opt=":${options:-$esp32p4_opts}"
192193
fqbn="espressif:esp32:esp32p4$opt"
193194
;;
195+
"esp32c5")
196+
[ -n "${options:-$esp32c5_opts}" ] && opt=":${options:-$esp32c5_opts}"
197+
fqbn="espressif:esp32:esp32c5$opt"
198+
;;
194199
*)
195200
echo "ERROR: Invalid chip: $target"
196201
exit 1

‎.github/workflows/push.yml

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -47,6 +47,7 @@ on:
4747
- "!.github/scripts/upload_*"
4848
- "variants/esp32/**/*"
4949
- "variants/esp32c3/**/*"
50+
- "variants/esp32c5/**/*"
5051
- "variants/esp32c6/**/*"
5152
- "variants/esp32h2/**/*"
5253
- "variants/esp32p4/**/*"
@@ -247,7 +248,7 @@ jobs:
247248
# See https://hub.docker.com/r/espressif/idf/tags and
248249
# https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-guides/tools/idf-docker-image.html
249250
# for details.
250-
idf_ver: ["release-v5.4"]
251+
idf_ver: ["release-v5.3","release-v5.4","release-v5.5"]
251252
idf_target:
252253
[
253254
"esp32",
@@ -282,7 +283,7 @@ jobs:
282283
uses: actions/upload-artifact@ea165f8d65b6e75b540449e92b4886f43607fa02 # v4.6.2
283284
if: always()
284285
with:
285-
name: sdkconfig-${{ matrix.idf_target }}
286+
name: sdkconfig-${{ matrix.idf_ver }}-${{ matrix.idf_target }}
286287
path: ./components/arduino-esp32/idf_component_examples/**/sdkconfig
287288

288289
# Save artifacts to gh-pages

‎.gitlab/workflows/common.yml

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -9,8 +9,8 @@ stages:
99
- result
1010

1111
variables:
12-
ESP_IDF_VERSION: "5.4"
13-
ESP_ARDUINO_VERSION: "3.2.1"
12+
ESP_IDF_VERSION: "5.5"
13+
ESP_ARDUINO_VERSION: "3.3.0"
1414

1515
#############
1616
# `default` #

‎CMakeLists.txt

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -6,7 +6,7 @@
66
# idf.py build
77

88
set(min_supported_idf_version "5.3.0")
9-
set(max_supported_idf_version "5.4.99")
9+
set(max_supported_idf_version "5.5.99")
1010
set(idf_version "${IDF_VERSION_MAJOR}.${IDF_VERSION_MINOR}.${IDF_VERSION_PATCH}")
1111

1212
if ("${idf_version}" AND NOT "$ENV{ARDUINO_SKIP_IDF_VERSION_CHECK}")
@@ -184,7 +184,8 @@ set(ARDUINO_LIBRARY_Matter_SRCS
184184
libraries/Matter/src/MatterEndpoints/MatterOccupancySensor.cpp
185185
libraries/Matter/src/MatterEndpoints/MatterOnOffPlugin.cpp
186186
libraries/Matter/src/MatterEndpoints/MatterThermostat.cpp
187-
libraries/Matter/src/Matter.cpp)
187+
libraries/Matter/src/Matter.cpp
188+
libraries/Matter/src/MatterEndPoint.cpp)
188189

189190
set(ARDUINO_LIBRARY_PPP_SRCS
190191
libraries/PPP/src/PPP.cpp
@@ -361,13 +362,13 @@ endforeach()
361362
set(includedirs variants/${CONFIG_ARDUINO_VARIANT}/ cores/esp32/ ${ARDUINO_LIBRARIES_INCLUDEDIRS})
362363
set(srcs ${CORE_SRCS} ${ARDUINO_LIBRARIES_SRCS})
363364
set(priv_includes cores/esp32/libb64)
364-
set(requires spi_flash esp_partition mbedtls wpa_supplicant esp_adc esp_eth http_parser esp_ringbuf esp_driver_gptimer esp_driver_usb_serial_jtag driver)
365+
set(requires spi_flash esp_partition mbedtls wpa_supplicant esp_adc esp_eth http_parser esp_ringbuf esp_driver_gptimer esp_driver_usb_serial_jtag driver esp_http_client esp_https_ota)
365366
set(priv_requires fatfs nvs_flash app_update spiffs bootloader_support bt esp_hid usb esp_psram ${ARDUINO_LIBRARIES_REQUIRES})
366367

367368
if(NOT CONFIG_ARDUINO_SELECTIVE_COMPILATION OR CONFIG_ARDUINO_SELECTIVE_OpenThread)
368369
#if(CONFIG_SOC_IEEE802154_SUPPORTED) # Does not work!
369370
#if(CONFIG_OPENTHREAD_ENABLED) # Does not work!
370-
if(IDF_TARGET STREQUAL "esp32c6" OR IDF_TARGET STREQUAL "esp32h2") # Sadly only this works
371+
if(IDF_TARGET STREQUAL "esp32c6" OR IDF_TARGET STREQUAL "esp32h2" OR IDF_TARGET STREQUAL "esp32c5") # Sadly only this works
371372
list(APPEND requires openthread)
372373
endif()
373374
endif()

‎boards.txt

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Original file line numberDiff line numberDiff line change
@@ -161,6 +161,217 @@ esp32c2.menu.EraseFlash.all.upload.erase_cmd=-e
161161

162162
##############################################################
163163

164+
esp32c5.name=ESP32C5 Dev Module
165+
166+
esp32c5.bootloader.tool=esptool_py
167+
esp32c5.bootloader.tool.default=esptool_py
168+
169+
esp32c5.upload.tool=esptool_py
170+
esp32c5.upload.tool.default=esptool_py
171+
esp32c5.upload.tool.network=esp_ota
172+
173+
esp32c5.upload.maximum_size=1310720
174+
esp32c5.upload.maximum_data_size=327680
175+
esp32c5.upload.flags=
176+
esp32c5.upload.extra_flags=
177+
esp32c5.upload.use_1200bps_touch=false
178+
esp32c5.upload.wait_for_upload_port=false
179+
180+
esp32c5.serial.disableDTR=false
181+
esp32c5.serial.disableRTS=false
182+
183+
esp32c5.build.tarch=riscv32
184+
esp32c5.build.target=esp
185+
esp32c5.build.mcu=esp32c5
186+
esp32c5.build.core=esp32
187+
esp32c5.build.variant=esp32c5
188+
esp32c5.build.board=ESP32C5_DEV
189+
esp32c5.build.bootloader_addr=0x2000
190+
191+
esp32c5.build.cdc_on_boot=0
192+
esp32c5.build.f_cpu=240000000L
193+
esp32c5.build.flash_size=4MB
194+
esp32c5.build.flash_freq=80m
195+
esp32c5.build.flash_mode=qio
196+
esp32c5.build.boot=qio
197+
esp32c5.build.partitions=default
198+
esp32c5.build.defines=
199+
200+
## IDE 2.0 Seems to not update the value
201+
esp32c5.menu.JTAGAdapter.default=Disabled
202+
esp32c5.menu.JTAGAdapter.default.build.copy_jtag_files=0
203+
esp32c5.menu.JTAGAdapter.builtin=Integrated USB JTAG
204+
esp32c5.menu.JTAGAdapter.builtin.build.openocdscript=esp32c5-builtin.cfg
205+
esp32c5.menu.JTAGAdapter.builtin.build.copy_jtag_files=1
206+
esp32c5.menu.JTAGAdapter.external=FTDI Adapter
207+
esp32c5.menu.JTAGAdapter.external.build.openocdscript=esp32c5-ftdi.cfg
208+
esp32c5.menu.JTAGAdapter.external.build.copy_jtag_files=1
209+
esp32c5.menu.JTAGAdapter.bridge=ESP USB Bridge
210+
esp32c5.menu.JTAGAdapter.bridge.build.openocdscript=esp32c5-bridge.cfg
211+
esp32c5.menu.JTAGAdapter.bridge.build.copy_jtag_files=1
212+
213+
esp32c5.menu.PSRAM.disabled=Disabled
214+
esp32c5.menu.PSRAM.disabled.build.defines=
215+
esp32c5.menu.PSRAM.enabled=Enabled
216+
esp32c5.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
217+
218+
esp32c5.menu.CDCOnBoot.default=Disabled
219+
esp32c5.menu.CDCOnBoot.default.build.cdc_on_boot=0
220+
esp32c5.menu.CDCOnBoot.cdc=Enabled
221+
esp32c5.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
222+
223+
esp32c5.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
224+
esp32c5.menu.PartitionScheme.default.build.partitions=default
225+
esp32c5.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
226+
esp32c5.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
227+
esp32c5.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
228+
esp32c5.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
229+
esp32c5.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
230+
esp32c5.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
231+
esp32c5.menu.PartitionScheme.minimal.build.partitions=minimal
232+
esp32c5.menu.PartitionScheme.no_fs=No FS 4MB (2MB APP x2)
233+
esp32c5.menu.PartitionScheme.no_fs.build.partitions=no_fs
234+
esp32c5.menu.PartitionScheme.no_fs.upload.maximum_size=2031616
235+
esp32c5.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
236+
esp32c5.menu.PartitionScheme.no_ota.build.partitions=no_ota
237+
esp32c5.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
238+
esp32c5.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
239+
esp32c5.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
240+
esp32c5.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
241+
esp32c5.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
242+
esp32c5.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
243+
esp32c5.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
244+
esp32c5.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
245+
esp32c5.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
246+
esp32c5.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
247+
esp32c5.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
248+
esp32c5.menu.PartitionScheme.huge_app.build.partitions=huge_app
249+
esp32c5.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
250+
esp32c5.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
251+
esp32c5.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
252+
esp32c5.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
253+
esp32c5.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
254+
esp32c5.menu.PartitionScheme.fatflash.build.partitions=ffat
255+
esp32c5.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
256+
esp32c5.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
257+
esp32c5.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
258+
esp32c5.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
259+
esp32c5.menu.PartitionScheme.rainmaker=RainMaker 4MB
260+
esp32c5.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
261+
esp32c5.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
262+
esp32c5.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
263+
esp32c5.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
264+
esp32c5.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
265+
esp32c5.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
266+
esp32c5.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
267+
esp32c5.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
268+
esp32c5.menu.PartitionScheme.zigbee_2MB=Zigbee 2MB with spiffs
269+
esp32c5.menu.PartitionScheme.zigbee_2MB.build.partitions=zigbee_2MB
270+
esp32c5.menu.PartitionScheme.zigbee_2MB.upload.maximum_size=1310720
271+
esp32c5.menu.PartitionScheme.zigbee=Zigbee 4MB with spiffs
272+
esp32c5.menu.PartitionScheme.zigbee.build.partitions=zigbee
273+
esp32c5.menu.PartitionScheme.zigbee.upload.maximum_size=1310720
274+
esp32c5.menu.PartitionScheme.zigbee_8MB=Zigbee 8MB with spiffs
275+
esp32c5.menu.PartitionScheme.zigbee_8MB.build.partitions=zigbee_8MB
276+
esp32c5.menu.PartitionScheme.zigbee_8MB.upload.maximum_size=3407872
277+
esp32c5.menu.PartitionScheme.zigbee_zczr_2MB=Zigbee ZCZR 2MB with spiffs
278+
esp32c5.menu.PartitionScheme.zigbee_zczr_2MB.build.partitions=zigbee_zczr_2MB
279+
esp32c5.menu.PartitionScheme.zigbee_zczr_2MB.upload.maximum_size=1310720
280+
esp32c5.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs
281+
esp32c5.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr
282+
esp32c5.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720
283+
esp32c5.menu.PartitionScheme.zigbee_zczr_8MB=Zigbee ZCZR 8MB with spiffs
284+
esp32c5.menu.PartitionScheme.zigbee_zczr_8MB.build.partitions=zigbee_zczr_8MB
285+
esp32c5.menu.PartitionScheme.zigbee_zczr_8MB.upload.maximum_size=3407872
286+
esp32c5.menu.PartitionScheme.custom=Custom
287+
esp32c5.menu.PartitionScheme.custom.build.partitions=
288+
esp32c5.menu.PartitionScheme.custom.upload.maximum_size=16777216
289+
290+
esp32c5.menu.CPUFreq.240=240MHz (WiFi)
291+
esp32c5.menu.CPUFreq.240.build.f_cpu=240000000L
292+
esp32c5.menu.CPUFreq.120=120MHz (WiFi)
293+
esp32c5.menu.CPUFreq.120.build.f_cpu=120000000L
294+
esp32c5.menu.CPUFreq.80=80MHz (WiFi)
295+
esp32c5.menu.CPUFreq.80.build.f_cpu=80000000L
296+
esp32c5.menu.CPUFreq.40=40MHz
297+
esp32c5.menu.CPUFreq.40.build.f_cpu=40000000L
298+
esp32c5.menu.CPUFreq.20=20MHz
299+
esp32c5.menu.CPUFreq.20.build.f_cpu=20000000L
300+
esp32c5.menu.CPUFreq.10=10MHz
301+
esp32c5.menu.CPUFreq.10.build.f_cpu=10000000L
302+
303+
esp32c5.menu.FlashMode.qio=QIO
304+
esp32c5.menu.FlashMode.qio.build.flash_mode=dio
305+
esp32c5.menu.FlashMode.qio.build.boot=qio
306+
esp32c5.menu.FlashMode.dio=DIO
307+
esp32c5.menu.FlashMode.dio.build.flash_mode=dio
308+
esp32c5.menu.FlashMode.dio.build.boot=dio
309+
310+
esp32c5.menu.FlashFreq.80=80MHz
311+
esp32c5.menu.FlashFreq.80.build.flash_freq=80m
312+
esp32c5.menu.FlashFreq.40=40MHz
313+
esp32c5.menu.FlashFreq.40.build.flash_freq=40m
314+
315+
esp32c5.menu.FlashSize.4M=4MB (32Mb)
316+
esp32c5.menu.FlashSize.4M.build.flash_size=4MB
317+
esp32c5.menu.FlashSize.8M=8MB (64Mb)
318+
esp32c5.menu.FlashSize.8M.build.flash_size=8MB
319+
esp32c5.menu.FlashSize.2M=2MB (16Mb)
320+
esp32c5.menu.FlashSize.2M.build.flash_size=2MB
321+
esp32c5.menu.FlashSize.16M=16MB (128Mb)
322+
esp32c5.menu.FlashSize.16M.build.flash_size=16MB
323+
324+
esp32c5.menu.UploadSpeed.921600=921600
325+
esp32c5.menu.UploadSpeed.921600.upload.speed=921600
326+
esp32c5.menu.UploadSpeed.115200=115200
327+
esp32c5.menu.UploadSpeed.115200.upload.speed=115200
328+
esp32c5.menu.UploadSpeed.256000.windows=256000
329+
esp32c5.menu.UploadSpeed.256000.upload.speed=256000
330+
esp32c5.menu.UploadSpeed.230400.windows.upload.speed=256000
331+
esp32c5.menu.UploadSpeed.230400=230400
332+
esp32c5.menu.UploadSpeed.230400.upload.speed=230400
333+
esp32c5.menu.UploadSpeed.460800.linux=460800
334+
esp32c5.menu.UploadSpeed.460800.macosx=460800
335+
esp32c5.menu.UploadSpeed.460800.upload.speed=460800
336+
esp32c5.menu.UploadSpeed.512000.windows=512000
337+
esp32c5.menu.UploadSpeed.512000.upload.speed=512000
338+
339+
esp32c5.menu.DebugLevel.none=None
340+
esp32c5.menu.DebugLevel.none.build.code_debug=0
341+
esp32c5.menu.DebugLevel.error=Error
342+
esp32c5.menu.DebugLevel.error.build.code_debug=1
343+
esp32c5.menu.DebugLevel.warn=Warn
344+
esp32c5.menu.DebugLevel.warn.build.code_debug=2
345+
esp32c5.menu.DebugLevel.info=Info
346+
esp32c5.menu.DebugLevel.info.build.code_debug=3
347+
esp32c5.menu.DebugLevel.debug=Debug
348+
esp32c5.menu.DebugLevel.debug.build.code_debug=4
349+
esp32c5.menu.DebugLevel.verbose=Verbose
350+
esp32c5.menu.DebugLevel.verbose.build.code_debug=5
351+
352+
esp32c5.menu.EraseFlash.none=Disabled
353+
esp32c5.menu.EraseFlash.none.upload.erase_cmd=
354+
esp32c5.menu.EraseFlash.all=Enabled
355+
esp32c5.menu.EraseFlash.all.upload.erase_cmd=-e
356+
357+
esp32c5.menu.ZigbeeMode.default=Disabled
358+
esp32c5.menu.ZigbeeMode.default.build.zigbee_mode=
359+
esp32c5.menu.ZigbeeMode.default.build.zigbee_libs=
360+
esp32c5.menu.ZigbeeMode.ed=Zigbee ED (end device)
361+
esp32c5.menu.ZigbeeMode.ed.build.zigbee_mode=-DZIGBEE_MODE_ED
362+
esp32c5.menu.ZigbeeMode.ed.build.zigbee_libs=-lesp_zb_api.ed -lzboss_stack.ed -lzboss_port.native
363+
esp32c5.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router)
364+
esp32c5.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR
365+
esp32c5.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.native
366+
esp32c5.menu.ZigbeeMode.ed_debug=Zigbee ED (end device) - Debug
367+
esp32c5.menu.ZigbeeMode.ed_debug.build.zigbee_mode=-DZIGBEE_MODE_ED
368+
esp32c5.menu.ZigbeeMode.ed_debug.build.zigbee_libs=-lesp_zb_api.ed.debug -lzboss_stack.ed.debug -lzboss_port.native.debug
369+
esp32c5.menu.ZigbeeMode.zczr_debug=Zigbee ZCZR (coordinator/router) - Debug
370+
esp32c5.menu.ZigbeeMode.zczr_debug.build.zigbee_mode=-DZIGBEE_MODE_ZCZR
371+
esp32c5.menu.ZigbeeMode.zczr_debug.build.zigbee_libs=-lesp_zb_api.zczr.debug -lzboss_stack.zczr.debug -lzboss_port.native.debug
372+
373+
##############################################################
374+
164375
esp32p4.name=ESP32P4 Dev Module
165376

166377
esp32p4.bootloader.tool=esptool_py

‎cores/esp32/Esp.cpp

Lines changed: 10 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -21,6 +21,7 @@
2121
#include "Esp.h"
2222
#include "esp_sleep.h"
2323
#include "spi_flash_mmap.h"
24+
#include "esp_idf_version.h"
2425
#include <memory>
2526
#include <soc/soc.h>
2627
#include <esp_partition.h>
@@ -63,6 +64,9 @@ extern "C" {
6364
#elif CONFIG_IDF_TARGET_ESP32P4
6465
#include "esp32p4/rom/spi_flash.h"
6566
#define ESP_FLASH_IMAGE_BASE 0x2000 // Esp32p4 is located at 0x2000
67+
#elif CONFIG_IDF_TARGET_ESP32C5
68+
#include "esp32c5/rom/spi_flash.h"
69+
#define ESP_FLASH_IMAGE_BASE 0x2000 // Esp32c5 is located at 0x2000
6670
#else
6771
#error Target CONFIG_IDF_TARGET is not supported
6872
#endif
@@ -301,7 +305,12 @@ const char *EspClass::getChipModel(void) {
301305
case CHIP_ESP32C6: return "ESP32-C6";
302306
case CHIP_ESP32H2: return "ESP32-H2";
303307
case CHIP_ESP32P4: return "ESP32-P4";
304-
default: return "UNKNOWN";
308+
#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 5, 0)
309+
case CHIP_ESP32C5: return "ESP32-C5";
310+
case CHIP_ESP32C61: return "ESP32-C61";
311+
case CHIP_ESP32H21: return "ESP32-H21";
312+
#endif
313+
default: return "UNKNOWN";
305314
}
306315
#endif
307316
}

‎cores/esp32/HardwareSerial.h

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -162,6 +162,8 @@ typedef enum {
162162
#define SOC_RX0 (gpio_num_t)23
163163
#elif CONFIG_IDF_TARGET_ESP32P4
164164
#define SOC_RX0 (gpio_num_t)38
165+
#elif CONFIG_IDF_TARGET_ESP32C5
166+
#define SOC_RX0 (gpio_num_t)12
165167
#endif
166168
#endif
167169

@@ -180,6 +182,8 @@ typedef enum {
180182
#define SOC_TX0 (gpio_num_t)24
181183
#elif CONFIG_IDF_TARGET_ESP32P4
182184
#define SOC_TX0 (gpio_num_t)37
185+
#elif CONFIG_IDF_TARGET_ESP32C5
186+
#define SOC_TX0 (gpio_num_t)11
183187
#endif
184188
#endif
185189

@@ -203,6 +207,8 @@ typedef enum {
203207
#define RX1 (gpio_num_t)0
204208
#elif CONFIG_IDF_TARGET_ESP32P4
205209
#define RX1 (gpio_num_t)11
210+
#elif CONFIG_IDF_TARGET_ESP32C5
211+
#define RX1 (gpio_num_t)4
206212
#endif
207213
#endif
208214

@@ -223,6 +229,8 @@ typedef enum {
223229
#define TX1 (gpio_num_t)1
224230
#elif CONFIG_IDF_TARGET_ESP32P4
225231
#define TX1 (gpio_num_t)10
232+
#elif CONFIG_IDF_TARGET_ESP32C5
233+
#define TX1 (gpio_num_t)5
226234
#endif
227235
#endif
228236
#endif /* SOC_UART_HP_NUM > 1 */

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