fixup: sdio: pac-specific init functions

Uses conditional compilation to perform PAC-specific initialization
routines. Mainly handles different register naming conventions.

Author: rmsyn

esp-hal/src/sdio.rs

@@ -18,7 +18,10 @@ use embedded_hal_sdmmc::{
     tuning::{TuningMode, TuningWidth},
 };
 
-use crate::gpio::{InputConfig, OutputConfig, Pull};
+use crate::{
+    gpio::{InputConfig, OutputConfig, Pull},
+    pac,
+};
 
 mod config;
 mod hinf;
@@ -145,16 +148,31 @@ impl<'d> Sdio<'d> {
         self.slc.info()
     }
 
+    /// Convenience function to get a reference to the SLC register block.
+    fn slc_block(&self) -> &'_ pac::slc::RegisterBlock {
+        unsafe { &*self.slc().register_block }
+    }
+
     /// Gets a static reference to the SLCHOST information.
     pub fn slchost(&self) -> &'static SlchostInfo {
         self.slchost.info()
     }
 
+    /// Convenience function to get a reference to the SLCHOST register block.
+    fn slchost_block(&self) -> &'_ pac::slchost::RegisterBlock {
+        unsafe { &*self.slchost().register_block }
+    }
+
     /// Gets a static reference to the HINF information.
     pub fn hinf(&self) -> &'static HinfInfo {
         self.hinf.info()
     }
 
+    /// Convenience function to get a reference to the SLCHOST register block.
+    fn hinf_block(&self) -> &'_ pac::hinf::RegisterBlock {
+        unsafe { &*self.hinf().register_block }
+    }
+
     /// Gets a reference to the [Pins] information.
     pub const fn pins(&self) -> &Pins<'_> {
         &self.pins
@@ -192,16 +210,42 @@ impl<'d> Sdio<'d> {
 
     /// Performs final low-level HAL hardware initialization.
     pub(crate) fn hardware_init(&mut self) -> Result<(), Error> {
-        self.low_level_init()?;
-        self.low_level_enable_hs()?;
-        self.low_level_set_timing()?;
-        self.low_level_set_timing()?;
-        self.low_level_dev_interrupt_enable(0xffu8.into())
+        self.pac_init()?;
+        self.pac_enable_hs()?;
+        self.pac_set_timing()?;
+        self.pac_dev_interrupt_enable(0xffu8.into())
+    }
+
+    /// Performs low-level initialization of the SDIO peripheral.
+    #[cfg(feature = "esp32")]
+    fn pac_init(&mut self) -> Result<(), Error> {
+        let slc = self.slc_block();
+
+        slc.slcconf0().modify(|_, w| {
+            w.slc0_rx_auto_wrback().set_bit();
+            w.slc0_token_auto_clr().clear_bit();
+
+            w.slc0_rx_loop_test().clear_bit();
+            w.slc0_tx_loop_test().clear_bit()
+        });
+
+        slc.slcconf1().modify(|_, w| {
+            w.slc0_rx_stitch_en().clear_bit();
+            w.slc0_tx_stitch_en().clear_bit();
+
+            w.slc0_len_auto_clr().clear_bit()
+        });
+
+        slc.slc_rx_dscr_conf()
+            .modify(|_, w| w.slc0_token_no_replace().set_bit());
+
+        Ok(())
     }
 
     /// Performs low-level initialization of the SDIO peripheral.
-    pub(crate) fn low_level_init(&mut self) -> Result<(), Error> {
-        let slc = unsafe { &*self.slc.info().register_block };
+    #[cfg(feature = "esp32c6")]
+    fn pac_init(&mut self) -> Result<(), Error> {
+        let slc = self.slc_block();
 
         slc.slcconf0().modify(|_, w| {
             w.sdio_slc0_rx_auto_wrback().set_bit();
@@ -225,18 +269,62 @@ impl<'d> Sdio<'d> {
     }
 
     /// Sets the high-speed supported bit to be read by the host.
-    pub(crate) fn low_level_enable_hs(&mut self) -> Result<(), Error> {
-        let hinf = unsafe { &*self.hinf.info().register_block };
-
-        hinf.cfg_data1()
+    #[cfg(any(feature = "esp32", feature = "esp32c6"))]
+    fn pac_enable_hs(&mut self) -> Result<(), Error> {
+        self.hinf_block()
+            .cfg_data1()
             .modify(|_, w| w.highspeed_enable().variant(self.config.hs()));
 
         Ok(())
     }
 
     /// Sets the communication timing.
-    pub(crate) fn low_level_set_timing(&mut self) -> Result<(), Error> {
-        let host = unsafe { &*self.slchost.info().register_block };
+    #[cfg(feature = "esp32")]
+    fn pac_set_timing(&mut self) -> Result<(), Error> {
+        let host = self.slchost_block();
+
+        match self.config.timing() {
+            Timing::PsendPsample => {
+                host.host_slchost_conf().modify(|_, w| unsafe {
+                    w.host_frc_sdio20().bits(0x1f);
+                    w.host_frc_sdio11().bits(0x0);
+                    w.host_frc_pos_samp().bits(0x1f);
+                    w.host_frc_neg_samp().bits(0x0)
+                });
+            }
+            Timing::PsendNsample => {
+                host.host_slchost_conf().modify(|_, w| unsafe {
+                    w.host_frc_sdio20().bits(0x1f);
+                    w.host_frc_sdio11().bits(0x0);
+                    w.host_frc_pos_samp().bits(0x0);
+                    w.host_frc_neg_samp().bits(0x1f)
+                });
+            }
+            Timing::NsendPsample => {
+                host.host_slchost_conf().modify(|_, w| unsafe {
+                    w.host_frc_sdio20().bits(0x0);
+                    w.host_frc_sdio11().bits(0x1f);
+                    w.host_frc_pos_samp().bits(0x1f);
+                    w.host_frc_neg_samp().bits(0x0)
+                });
+            }
+            Timing::NsendNsample => {
+                host.host_slchost_conf().modify(|_, w| unsafe {
+                    w.host_frc_sdio20().bits(0x0);
+                    w.host_frc_sdio11().bits(0x1f);
+                    w.host_frc_pos_samp().bits(0x0);
+                    w.host_frc_neg_samp().bits(0x1f)
+                });
+            }
+        }
+
+        Ok(())
+    }
+
+    /// Sets the communication timing.
+    #[cfg(feature = "esp32c6")]
+    fn pac_set_timing(&mut self) -> Result<(), Error> {
+        let host = self.slchost_block();
 
         match self.config.timing() {
             Timing::PsendPsample => {
@@ -277,13 +365,26 @@ impl<'d> Sdio<'d> {
     }
 
     /// Sets which device interrupts to enable based on the provided mask.
-    pub(crate) fn low_level_dev_interrupt_enable(
-        &self,
-        mask: DeviceInterrupt,
-    ) -> Result<(), Error> {
-        let slc = unsafe { &*self.slc.info().register_block };
+    #[cfg(feature = "esp32")]
+    fn pac_dev_interrupt_enable(&self, mask: DeviceInterrupt) -> Result<(), Error> {
+        self.slc_block()._0int_ena().modify(|_, w| {
+            w.frhost_bit0_int_ena().variant(mask.general0());
+            w.frhost_bit1_int_ena().variant(mask.general1());
+            w.frhost_bit2_int_ena().variant(mask.general2());
+            w.frhost_bit3_int_ena().variant(mask.general3());
+            w.frhost_bit4_int_ena().variant(mask.general4());
+            w.frhost_bit5_int_ena().variant(mask.general5());
+            w.frhost_bit6_int_ena().variant(mask.general6());
+            w.frhost_bit7_int_ena().variant(mask.general7())
+        });
+
+        Ok(())
+    }
 
-        slc.slc0int_ena().modify(|_, w| {
+    /// Sets which device interrupts to enable based on the provided mask.
+    #[cfg(feature = "esp32c6")]
+    fn pac_dev_interrupt_enable(&self, mask: DeviceInterrupt) -> Result<(), Error> {
+        self.slc_block().slc0int_ena().modify(|_, w| {
             w.sdio_slc_frhost_bit0_int_ena().variant(mask.general0());
             w.sdio_slc_frhost_bit1_int_ena().variant(mask.general1());
             w.sdio_slc_frhost_bit2_int_ena().variant(mask.general2());