sdio: qa-test integration tests

Adds a split `qa-test` SPI-mode SDIO integration test.

The tests are split with the intention to flash each half of the test to
separate devices, allowing for concurrent execution.

Author: rmsyn

esp-hal/src/sdio.rs

@@ -36,7 +36,7 @@ mod slchost;
 mod state;
 mod timing;
 
-pub use config::Config;
+pub use config::{Config, SpiMode};
 pub use direction::Direction;
 pub use hinf::{AnyHinf, HinfInfo, HinfInstance};
 pub use interrupt::{DeviceInterrupt, HostInterrupt};
@@ -408,7 +408,7 @@ impl<'d> Sdio<'d> {
     }
 
     /// Waits for a clock edge transition to indicate when to read/write data.
-    // TODO: configure SPI modes
+    // TODO: add timeout parameter
     pub(crate) fn wait_for_clock_edge(&self, direction: SpiDirection) -> Result<(), Error> {
         match self.pins.mode() {
             Mode::Spi => {

esp-hal/src/sdio/config.rs

@@ -1,11 +1,13 @@
 use super::Timing;
+pub use crate::spi::Mode as SpiMode;
 
 /// Represents SDIO configuration parameters.
 #[repr(C)]
 #[derive(Clone, Copy, Debug, Eq, PartialEq)]
 pub struct Config {
     hs: bool,
     timing: Timing,
+    spi_mode: SpiMode,
 }
 
 impl Config {
@@ -14,6 +16,7 @@ impl Config {
         Self {
             hs: false,
             timing: Timing::new(),
+            spi_mode: SpiMode::_0,
         }
     }
 
@@ -46,6 +49,21 @@ impl Config {
     pub fn with_timing(self, timing: Timing) -> Self {
         Self { timing, ..self }
     }
+
+    /// Gets the SPI mode setting.
+    pub const fn spi_mode(&self) -> SpiMode {
+        self.spi_mode
+    }
+
+    /// Sets the SPI mode seting.
+    pub fn set_spi_mode(&mut self, spi_mode: SpiMode) {
+        self.spi_mode = spi_mode;
+    }
+
+    /// Builder funciton that sets the SPI mode setting.
+    pub fn with_spi_mode(self, spi_mode: SpiMode) -> Self {
+        Self { spi_mode, ..self }
+    }
 }
 
 impl Default for Config {

qa-test/src/bin/sdio-spi-device.rs

@@ -0,0 +1,139 @@
+#![no_std]
+#![no_main]
+
+use esp_backtrace as _;
+use esp_hal::{
+    dma::{DescriptorFlagFields, Owner},
+    sdio::{
+        Config,
+        Mode,
+        Pins,
+        Sdio,
+        SpiMode,
+        dma::{
+            AtomicBuffer,
+            AtomicDmaDescriptor,
+            AtomicDmaDescriptors,
+            DmaDescriptor,
+            DmaDescriptorFlags,
+        },
+    },
+};
+
+esp_bootloader_esp_idf::esp_app_desc!();
+
+// Use 10KB of data to fit inside SRAM
+// One RX + one TX buffer
+const DATA_SIZE: usize = 1024 * 5;
+// Use 6KB of descriptors to fit inside SRAM
+const DESC_SIZE: usize = 1024 * 6;
+// Represents the default byte length of a SDIO block.
+const BLOCK_LEN: usize = 512;
+// Total number of DMA descriptors.
+const DESC_NUM: usize = DESC_SIZE / core::mem::size_of::<AtomicDmaDescriptor>() / 2;
+// Represents the set of Receive DMA descriptors.
+static RX_DESCRIPTORS: AtomicDmaDescriptors<DESC_NUM> = AtomicDmaDescriptors::new();
+// Represents the set of Transmit DMA descriptors.
+static TX_DESCRIPTORS: AtomicDmaDescriptors<DESC_NUM> = AtomicDmaDescriptors::new();
+// Represents the Receive DMA buffer.
+static RX_BUFFER: AtomicBuffer<DATA_SIZE> = AtomicBuffer::new();
+// Represents the Transmit DMA buffer.
+static TX_BUFFER: AtomicBuffer<DATA_SIZE> = AtomicBuffer::new();
+
+struct Context {
+    sdio: Sdio<'static>,
+}
+
+impl Context {
+    /// Creates a new context for the SDIO SPI slave controller.
+    pub fn new() -> Self {
+        let peripherals = esp_hal::init(esp_hal::Config::default());
+
+        cfg_if::cfg_if! {
+            if #[cfg(feature = "esp32")] {
+                // GPIO Slot 1 config
+                let pins = Pins::new(
+                    Mode::Spi,
+                    peripherals.GPIO6,  // CLK/SCK
+                    peripherals.GPIO11, // CMD/MOSI
+                    peripherals.GPIO7,  // DAT0/MISO
+                    peripherals.GPIO8,  // DAT1/IRQ
+                    peripherals.GPIO9,  // DAT2
+                    peripherals.GPIO10, // DAT3/#CS
+                );
+
+                // GPIO Slot 2 config
+                //let pins = Pins::new(
+                //    Mode::Spi,
+                //    peripherals.GPIO14, // CLK/SCK
+                //    peripherals.GPIO15, // CMD/MOSI
+                //    peripherals.GPIO2,  // DAT0/MISO
+                //    peripherals.GPIO4,  // DAT1/IRQ
+                //    peripherals.GPIO12, // DAT2
+                //    peripherals.GPIO13, // DAT3/#CS
+                //);
+            } else if #[cfg(feature = "esp32c6")] {
+                let pins = Pins::new(
+                    Mode::Spi,
+                    peripherals.GPIO19, // CLK/SCLK
+                    peripherals.GPIO18, // CMD/MOSI
+                    peripherals.GPIO20, // DAT0/MISO
+                    peripherals.GPIO21, // DAT1/IRQ
+                    peripherals.GPIO22, // DAT2
+                    peripherals.GPIO23, // DAT3/#CS
+                );
+            } else {
+                panic!("unsupported platform");
+            }
+        }
+
+        let config = Config::new().with_spi_mode(SpiMode::_2);
+
+        let sdio = Sdio::new(
+            peripherals.SLC,
+            peripherals.SLCHOST,
+            peripherals.HINF,
+            pins,
+            config,
+        );
+
+        Self { sdio }
+    }
+}
+
+#[esp_hal::main]
+fn main() -> ! {
+    let ctx = Context::new();
+
+    // TODO: perform data transfer
+    // indicate a transfer of a single SDIO block
+    let mut flags = DmaDescriptorFlags::new();
+    flags.set_owner(Owner::Dma);
+    flags.set_suc_eof(true);
+    flags.set_size(BLOCK_LEN);
+    flags.set_len(BLOCK_LEN);
+
+    let tx_descriptor = &TX_DESCRIPTORS[0];
+
+    let packet = b"test RX packet";
+    RX_BUFFER.write(packet.as_slice());
+
+    let buffer = unsafe { RX_BUFFER.as_ptr_mut() };
+    tx_descriptor.update(DmaDescriptor {
+        flags,
+        buffer,
+        next: core::ptr::null_mut(),
+    });
+
+    let slc = unsafe { &*ctx.sdio.slc().register_block };
+
+    // configure SLC RX descriptors
+    slc.slc1rx_link_addr()
+        .write(|w| unsafe { w.bits(RX_DESCRIPTORS.address()) });
+    slc.slc1rx_link()
+        .modify(|_, w| w.sdio_slc1_rxlink_start().set_bit());
+
+    loop {
+        core::hint::spin_loop()
+    }
+}

qa-test/src/bin/sdio-spi-host.rs

@@ -0,0 +1,173 @@
+//! SDIO SPI mode master driver example.
+
+#![no_std]
+#![no_main]
+
+use esp_backtrace as _;
+use esp_hal::{
+    Blocking,
+    sdio::{
+        command::{Cmd0, Cmd5, Cmd52, Cmd53, FunctionNumber, RwFlag},
+        response::{
+            R1,
+            spi::{R4, R5},
+        },
+    },
+    spi::{Mode, master as spi},
+    time::Rate,
+};
+use esp_println::println;
+
+esp_bootloader_esp_idf::esp_app_desc!();
+
+// Represents the byte length of a SDIO block.
+const BLOCK_LEN: usize = 512;
+
+struct Context {
+    spi: spi::Spi<'static, Blocking>,
+}
+
+impl Context {
+    /// Creates a new context for the SDIO SPI master controller.
+    pub fn new() -> Self {
+        let peripherals = esp_hal::init(esp_hal::Config::default());
+
+        let config = spi::Config::default()
+            .with_mode(Mode::_2)
+            .with_frequency(Rate::from_mhz(40));
+
+        cfg_if::cfg_if! {
+            if #[cfg(feature = "esp32")] {
+                // Create SPI master for mock SDIO host
+                // HSPI config
+                let spi = spi::Spi::new(
+                    peripherals.SPI2,
+                    config,
+                )
+                .unwrap()
+                .with_sck(peripherals.GPIO14)
+                .with_mosi(peripherals.GPIO13)
+                .with_miso(peripherals.GPIO12)
+                .with_cs(peripherals.GPIO15);
+
+                // Create SPI master for mock SDIO host
+                // VSPI config
+                //let spi = spi::Spi::new(
+                //    peripherals.SPI3,
+                //    spi::Config::default().with_frequency(Rate::from_mhz(40)),
+                //)
+                //.unwrap()
+                //.with_sck(peripherals.GPIO18)
+                //.with_mosi(peripherals.GPIO23)
+                //.with_miso(peripherals.GPIO19)
+                //.with_cs(peripherals.GPIO5);
+            } else if #[cfg(feature = "esp32c6")] {
+                // Create SPI master for mock SDIO host
+                let spi = spi::Spi::new(
+                    peripherals.SPI2,
+                    config,
+                )
+                .unwrap()
+                .with_sck(peripherals.GPIO6)
+                .with_mosi(peripherals.GPIO7)
+                .with_miso(peripherals.GPIO2)
+                .with_cs(peripherals.GPIO16);
+            } else {
+                panic!("unsupported platform");
+            }
+        }
+
+        Self { spi }
+    }
+}
+
+#[esp_hal::main]
+fn main() -> ! {
+    let mut ctx = Context::new();
+
+    ctx.spi
+        .write(&[0u8; 10])
+        .expect("error sending SPI init cycles");
+
+    let mut poll = true;
+
+    // continually send CMD0 until an IDLE R1 response
+    while poll {
+        let mut packet = Cmd0::new().into_bytes();
+        ctx.spi
+            .transfer(&mut packet)
+            .expect("error writing SDIO from host");
+
+        // expect R1 response from SDIO device
+        match R1::try_from(packet.as_ref()) {
+            Ok(r1) if r1.idle() && !r1.is_err() => {
+                println!("response: {r1}");
+                poll = false;
+            }
+            _ => (),
+        }
+    }
+
+    println!("received R1 IDLE response ...");
+    poll = true;
+
+    while poll {
+        let mut packet = Cmd5::new().into_bytes();
+
+        // expect R4 response from SDIO device
+        ctx.spi
+            .transfer(&mut packet)
+            .expect("error transfer CMD5 from SPI host");
+
+        match R4::try_from(packet.as_ref()) {
+            Ok(r4) if r4.ready() && !r4.is_err() => {
+                poll = false;
+                println!("response: {r4:x?}");
+            }
+            Ok(r4) if r4.is_err() => {
+                println!("error response: {}", r4.modified_r1());
+            }
+            _ => (),
+        }
+    }
+
+    println!("received R4 READY response ...");
+    poll = true;
+
+    let mut packet = [0u8; Cmd53::LEN + BLOCK_LEN];
+
+    while poll {
+        let mut cmd = Cmd53::new();
+
+        cmd.set_function_number(FunctionNumber::Io2);
+        cmd.set_read_write_flag(RwFlag::ReadOnly);
+        // Fixed-address transfer
+        cmd.set_register_address(0x0);
+        cmd.set_crc();
+
+        packet[..Cmd53::LEN].copy_from_slice(cmd.into_bytes().as_slice());
+
+        ctx.spi
+            .transfer(&mut packet)
+            .expect("error transfer CMD53 from SPI host");
+
+        match R5::try_from(packet.as_ref()) {
+            Ok(r5) if r5.idle() && !r5.is_err() => {
+                poll = false;
+
+                println!("response: {r5}");
+
+                let data = &packet[R5::LEN..];
+                println!("data: {data:x?}");
+            }
+            Ok(r5) if r5.is_err() => {
+                println!("error response: {r5}");
+            }
+            _ => (),
+        }
+    }
+
+    loop {
+        core::hint::spin_loop()
+    }
+}