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• All Logic

  It is necessary to get transistor and logic circuits of all PSXCPU component base (terminals, custom blocks, standard cells). This study also includes making some kind of standard cell database and assigning their ports, for the upcoming connection to the netlist.

  No due date

  •0/3 issues closed
  0% complete3 open0 closed

• All Topology

  All datasets of the PSXCPU topology must be collected and saved for later generations. In addition to the "raw" datasets, additional work on their preprocessing is also expected: - M1/M2 slide stitching - Obtaining the topology of standard cells and custom blocks

  No due date

  •0/3 issues closed
  0% complete3 open0 closed