2025-10-07
- Binutils CMDBUF support
- GCC builtins support
- WP2: Add binutils support for the ISA extension
- New specification provided by Tenstorrent to Embecosm on 2025-09-30
- Twenty new cmdbuf instruction implemented
- Six misc instructions implemented
- IN PROGRESS
- WP4: Builtin function support for the ISA extension
- Specification available here
- Structure for builtins ready
__builtin_rvtt_rocc_noc_fence&__builtin_rvtt_rocc_dbg_postcodeimplemented and tested__builtin_rvtt_rocc_cmdbuf_wr_reg&__builtin_rvtt_rocc_cmdbuf_rd_regimplemented- Note: Upstreaming will require the builtins to follow RISC-V standard naming for GCC and LLVM, which is
__builtin_riscv_tt_<name>
- IN PROGRESS
- RISCV configuration questions
- WP2: Continue work on binutils (Pietra & Pierre-Emmanuel)
- WP4: Add builtin function support (Arthur)
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WP1 - Extend the tool chain drivers
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WP2 - Add assembler/disassembler support for the ISA extension
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WP3 - Test the assembler and disassembler
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WP4 - Add builtin function support for the ISA extension
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Instructions added to binutils: 30/70
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Binutils instructions tested: 0/70
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Builtins completed: 4/70
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Builtins tested: 2/70
| MS | Description | Time estimation |
|---|---|---|
| MS0 | Project SoW signed-off, Tenstorrent PO received, and down-payment invoiced by Ashling. | T0=Sep-2, 2025 |
| MS1 | Initial release of GCC and GNU binutils with ISA extension support. At this stage all the functionalities will be present, but testing will not have been completed | T0+5w "subject to delay" on MS1/2 |
| MS2 | Final release of GCC and GNU binutils with ISA extension support. All testing will be complete, and there will be no new regressions in either GCC or GNU binutils | T0+10w |
- MS1 deadline under review
Risk register available at the following link
- Arthur and Pierre-Emmanuel will attend Eurorust on October 9 and 10.
- Pietra will be on vacation from October 16 to 27.