diff --git a/regs_analog_ctrl_APB/base.sdc b/regs_analog_ctrl_APB/base.sdc new file mode 100644 index 0000000..7d2ede4 --- /dev/null +++ b/regs_analog_ctrl_APB/base.sdc @@ -0,0 +1,58 @@ +## CLOCK CONSTRAINTS +create_clock [get_ports $::env(CLOCK_PORT)] -name $::env(CLOCK_PORT) -period 15 +set_propagated_clock [get_clocks $::env(CLOCK_PORT)] +# set_clock_transition 1.5 [get_clocks $::env(CLOCK_PORT)] +set_driving_cell -lib_cell sky130_fd_sc_hd__clkbuf_4 -pin {X} [get_ports $::env(CLOCK_PORT)] +set_clock_uncertainty 0.1 [get_clocks $::env(CLOCK_PORT)] + +## INPUT DELAY +set_input_transition 0.5 [all_inputs] +set_input_delay 4.8 -clock [get_clocks $::env(CLOCK_PORT)] [all_inputs] +set_input_delay -min 3.2 -clock [get_clocks $::env(CLOCK_PORT)] [get_ports PADDR*] + +set_input_delay 0 -clock [get_clocks $::env(CLOCK_PORT)] [get_ports PCLK] + + + +## OUTPUT DELAY +set_output_delay 4.8 -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs] + +#Menna to avoid infeasable path from and to the following two points + set_input_delay 4.8 -clock [get_clocks $::env(CLOCK_PORT)] [get_ports PADDR*] + set_input_delay -min 3.2 -clock [get_clocks $::env(CLOCK_PORT)] [get_ports PADDR*] + set_input_delay 4.8 -clock [get_clocks $::env(CLOCK_PORT)] [get_ports brownout_timeout*] + set_input_delay 4.8 -clock [get_clocks $::env(CLOCK_PORT)] [get_ports vdda1_pwr_good*] + set_input_delay 4.8 -clock [get_clocks $::env(CLOCK_PORT)] [get_ports comp_out*] + set_input_delay 4.8 -clock [get_clocks $::env(CLOCK_PORT)] [get_ports vccd2_pwr_good*] + + set_input_delay 4.8 -clock [get_clocks $::env(CLOCK_PORT)] [get_ports vccd1_pwr_good*] + set_input_delay 4.8 -clock [get_clocks $::env(CLOCK_PORT)] [get_ports brownout_vunder*] + set_input_delay 4.8 -clock [get_clocks $::env(CLOCK_PORT)] [get_ports vdda2_pwr_good*] + set_input_delay 4.8 -clock [get_clocks $::env(CLOCK_PORT)] [get_ports ulpcomp_out*] + set_input_delay 4.8 -clock [get_clocks $::env(CLOCK_PORT)] [get_ports overvoltage_out*] + set_input_delay 4.8 -clock [get_clocks $::env(CLOCK_PORT)] [get_ports brownout_filt*] + set_input_delay 4.8 -clock [get_clocks $::env(CLOCK_PORT)] [get_ports brownout_unfilt*] + set_input_delay 4.8 -clock [get_clocks $::env(CLOCK_PORT)] [get_ports vccd2_pwr_good*] + + + set_output_delay 4.5 -clock [get_clocks $::env(CLOCK_PORT)] [get_ports PRDATA*] + + + +## CAP LOAD +set cap_load 0.075 +puts "\[INFO\]: Setting load to: $cap_load" +set_load $cap_load [all_outputs] + +## MAX TRANS +set_max_transition 1 [current_design] + +## DERATES +puts "\[INFO\]: Setting timing derate to: [expr {5 * 100}] %" +set_timing_derate -early 0.95 +set_timing_derate -late 1.05 + +#Menna Oct30 +# Maximum fanout +set_max_fanout $::env(MAX_FANOUT_CONSTRAINT) [current_design] +puts "\[INFO\]: Setting maximum fanout to: $::env(MAX_FANOUT_CONSTRAINT)" diff --git a/regs_analog_ctrl_APB/config.yaml b/regs_analog_ctrl_APB/config.yaml new file mode 100644 index 0000000..8e7b4ca --- /dev/null +++ b/regs_analog_ctrl_APB/config.yaml @@ -0,0 +1,51 @@ +{ + "DESIGN_NAME": "regs_analog_ctrl_APB", + "FP_PDN_SKIPTRIM": true, + "DESIGN_IS_CORE": false, + "VERILOG_FILES": [ + "dir::regs_analog_ctrl_APB.v", + "dir::regs_analog_ctrl.v" + ], + "PNR_SDC_FILE":"dir::base.sdc", + "CLOCK_PORT":"PCLK", + "SIGNOFF_SDC_FILE":"dir::signoff.sdc", + "ERROR_ON_SYNTH_CHECKS": false, + "DRT_THREADS": 16, + "FP_SIZING": "absolute", + "DIE_AREA": [0, 0, 1605, 105], + "CORE_AREA": [5, 5, 1600, 100], + "FP_PIN_ORDER_CFG": "dir::pin_order.cfg", + "PL_TARGET_DENSITY_PCT": 25, + + "GPL_CELL_PADDING": 3, + "MAX_FANOUT_CONSTRAINT": 16, + + + "PL_WIRE_LENGTH_COEF": 0.1, + "PL_ROUTABILITY_DRIVEN": true, + "MAGIC_DEF_LABELS": false, + "GRT_ADJUSTMENT": 0.05, + "RT_MAX_LAYER": "met3", + "VDD_NETS": [ + "vccd0" + ], + "GND_NETS": [ + "vssd0" + ], + "GRT_ALLOW_CONGESTION": true, + "DIODE_ON_PORTS": "both", + "RUN_HEURISTIC_DIODE_INSERTION": true, + "GRT_REPAIR_ANTENNAS": true, + "HEURISTIC_ANTENNA_THRESHOLD": 200, + "TOP_MARGIN_MULT": 2, + "BOTTOM_MARGIN_MULT": 2, + "PDN_OBSTRUCTIONS": [ + [met4,1090,0,1180,105] + ], + "ROUTING_OBSTRUCTIONS": [ + [met4,1090,0,1180,105] + ], + "DEFAULT_CORNER": "max_ss_100C_1v60", + "DESIGN_REPAIR_MAX_WIRE_LENGTH": 1200, + "PL_KEEP_RESIZE_BELOW_OVERFLOW": 0 +} diff --git a/regs_analog_ctrl_APB/pin_order.cfg b/regs_analog_ctrl_APB/pin_order.cfg new file mode 100644 index 0000000..93f4c94 --- /dev/null +++ b/regs_analog_ctrl_APB/pin_order.cfg @@ -0,0 +1,301 @@ +#NR +dac_refl_to_gpio1_0.* +vbg_test_to_gpio1_1.* +dac_refh_to_gpio1_1.* +adc1_to_gpio1_2.* +idac_to_gpio1_2.* +ibias_test_to_gpio1_2.* +idac_to_gpio1_3.* +adc0_to_gpio1_3.* +comp_n_to_gpio1_4.* +comp_p_to_gpio1_5.* +ulpcomp_n_to_gpio1_6.* +ulpcomp_p_to_gpio1_7.* +left_hgbw_opamp_n_to_gpio2_0.* +left_hgbw_opamp_p_to_gpio2_1.* +right_hgbw_opamp_n_to_gpio2_2.* +right_hgbw_opamp_p_to_gpio2_3.* +right_lp_opamp_n_to_gpio2_4.* +right_lp_opamp_p_to_gpio2_5.* +right_instramp_n_to_gpio2_6.* +right_instramp_p_to_gpio2_7.* +right_instramp_p_to_sio0 +right_instramp_to_gpio3_0.* +left_hgbw_opamp_to_gpio3_1.* +right_hgbw_opamp_to_gpio3_2.* +right_lp_opamp_to_gpio3_3.* +left_lp_opamp_to_gpio3_4.* +left_hgbw_opamp_to_gpio3_5.* +right_hgbw_opamp_to_gpio3_6.* +right_lp_opamp_to_gpio3_7.* +right_instramp_p_to_voutref +right_instramp_p_to_left_vref +right_instramp_p_to_tempsense +right_instramp_p_to_amuxbusA +right_instramp_p_to_analog0 +right_instramp_n_to_vinref +right_instramp_n_to_right_vref +right_instramp_n_to_sio1 +right_instramp_n_to_amuxbusB +right_instramp_n_to_analog1 +right_instramp_to_amuxbusA.* +right_instramp_to_analog0.* +right_hgbw_opamp_n_to_vinref +right_hgbw_opamp_n_to_right_vref +right_hgbw_opamp_n_to_vbgsc +right_hgbw_opamp_n_to_sio1 +right_hgbw_opamp_n_to_rheostat_tap +right_hgbw_opamp_n_to_rheostat_out +right_hgbw_opamp_n_to_amuxbusB +right_hgbw_opamp_n_to_analog1 +right_hgbw_opamp_n_to_dac1 +right_hgbw_opamp_p_to_voutref +right_hgbw_opamp_p_to_left_vref +right_hgbw_opamp_p_to_sio0 +right_hgbw_opamp_p_to_rheostat_out +right_hgbw_opamp_p_to_amuxbusA +right_hgbw_opamp_p_to_analog0 +right_hgbw_opamp_p_to_dac0 +right_hgbw_opamp_to_amuxbusA.* +right_hgbw_opamp_to_analog0.* +right_lp_opamp_n_to_vinref +right_lp_opamp_n_to_right_vref +right_lp_opamp_n_to_vbgtc +right_lp_opamp_n_to_sio1 +right_lp_opamp_n_to_rheostat_tap +right_lp_opamp_n_to_rheostat_out +right_lp_opamp_n_to_amuxbusB +right_lp_opamp_n_to_analog1 +right_lp_opamp_n_to_dac1 +right_lp_opamp_p_to_voutref +right_lp_opamp_p_to_left_vref +right_lp_opamp_p_to_tempsense +right_lp_opamp_p_to_sio0 +right_lp_opamp_p_to_rheostat_out +right_lp_opamp_p_to_amuxbusA +right_lp_opamp_p_to_analog0 +right_lp_opamp_p_to_dac0 +right_lp_opamp_to_amuxbusB.* +right_lp_opamp_to_analog1.* +adc1_to_vinref +adc1_to_right_vref +adc1_to_vbgsc +adc0_to_voutref +adc0_to_left_vref +adc0_to_tempsense +adc0_to_vbgtc +left_lp_opamp_n_to_vinref +left_lp_opamp_n_to_right_vref +left_lp_opamp_n_to_vbgsc +left_lp_opamp_n_to_sio1 +left_hgbw_opamp_n_to_vinref +left_hgbw_opamp_n_to_right_vref +left_hgbw_opamp_n_to_vbgtc +left_hgbw_opamp_n_to_sio1 +left_lp_opamp_p_to_voutref +left_lp_opamp_p_to_left_vref +left_lp_opamp_p_to_sio0 +left_hgbw_opamp_p_to_voutref +left_hgbw_opamp_p_to_left_vref +left_hgbw_opamp_p_to_tempsense +left_hgbw_opamp_p_to_sio0 +left_instramp_p_to_voutref +left_instramp_p_to_left_vref +left_instramp_p_to_tempsense +left_instramp_p_to_sio0 +left_instramp_n_to_vinref +left_instramp_n_to_right_vref +left_instramp_n_to_sio1 +ulpcomp_n_to_vinref +ulpcomp_n_to_right_vref +ulpcomp_n_to_vbgsc +ulpcomp_n_to_sio1 +ulpcomp_n_to_analog0 +ulpcomp_n_to_dac1 +ulpcomp_p_to_voutref +ulpcomp_p_to_left_vref +ulpcomp_p_to_tempsense +ulpcomp_p_to_vbgtc +ulpcomp_p_to_sio0 +ulpcomp_p_to_analog1 +ulpcomp_p_to_dac0 +comp_n_to_vinref +comp_n_to_right_vref +comp_n_to_vbgsc +comp_n_to_sio1 +comp_n_to_analog0 +comp_n_to_dac1 +comp_p_to_voutref +comp_p_to_left_vref +comp_p_to_tempsense +comp_p_to_vbgtc +comp_p_to_sio0 +comp_p_to_analog1 +comp_p_to_dac0 +sio1_connect.* +sio0_connect.* +vbgsc_to_user +vbgtc_to_user +voutref_to_user +vinref_to_user +left_vref_to_user +right_vref_to_user +tempsense_to_user +dac1_to_user +dac0_to_user +user_to_adc1.* +user_to_adc0.* +user_to_ulpcomp_p.* +user_to_ulpcomp_n.* +user_to_comp_p.* +user_to_comp_n.* +right_rheostat2_b.* +right_rheostat1_b.* +right_lp_opamp_ena +right_hgbw_opamp_ena +right_instramp_G2.* +right_instramp_G1.* +right_instramp_ena +idac_ena +idac_value.* +overvoltage_trim.* +overvoltage_ena +ibias_ref_select +ibias_snk_ena.* +ibias_src_ena.* +ibias_ena +ldo_ena +bandgap_trim.* +bandgap_ena +ulpcomp_clk +ulpcomp_ena +comp_hyst.* +comp_trim.* +comp_ena +overvoltage_out +ulpcomp_out +comp_out +bandgap_sel +ldo_ref_sel +tempsense_sel + +brownout_unfilt +brownout_filt +brownout_timeout +brownout_vunder +brownout_rc_dis +brownout_rc_ena +brownout_oneshot +brownout_isrc_sel +brownout_otrip.* +brownout_vtrip.* +brownout_ena +analog1_connect.* +analog0_connect.* +left_rheostat2_b.* +left_rheostat1_b.* +left_lp_opamp_ena +left_hgbw_opamp_ena +left_instramp_G2.* +left_instramp_G1.* +left_instramp_ena +rdac1_value.* +rdac1_ena +rdac0_value.* +rdac0_ena +tempsense_ena +vccd2_pwr_good +vdda2_pwr_good +vccd1_pwr_good +vdda1_pwr_good +dac1_to_analog0 +dac0_to_analog1 +adc1_to_analog0 +adc1_to_dac1 +adc0_to_analog1 +adc0_to_dac0 +audiodac_out_to_analog1.* +audiodac_outb_to_analog0.* +left_lp_opamp_n_to_rheostat_tap +left_lp_opamp_n_to_rheostat_out +left_lp_opamp_n_to_amuxbusB +left_lp_opamp_n_to_analog1 +left_lp_opamp_n_to_dac1 +left_lp_opamp_p_to_rheostat_out +left_lp_opamp_p_to_amuxbusA +left_lp_opamp_p_to_analog0 +left_lp_opamp_p_to_dac0 +left_lp_opamp_to_amuxbusA.* +left_lp_opamp_to_analog0.* +left_lp_opamp_to_adc1.* +left_lp_opamp_to_comp_n.* +left_lp_opamp_to_ulpcomp_n.* +left_hgbw_opamp_n_to_rheostat_tap +left_hgbw_opamp_n_to_rheostat_out +left_hgbw_opamp_n_to_amuxbusB +left_hgbw_opamp_n_to_analog1 +left_hgbw_opamp_n_to_dac1 +left_hgbw_opamp_p_to_rheostat_out +left_hgbw_opamp_p_to_amuxbusA +left_hgbw_opamp_p_to_analog0 +left_hgbw_opamp_p_to_dac0 +left_hgbw_opamp_to_amuxbusB.* +left_hgbw_opamp_to_analog1.* +left_hgbw_opamp_to_adc0.* +left_hgbw_opamp_to_comp_p.* +left_hgbw_opamp_to_ulpcomp_p.* +left_instramp_p_to_amuxbusA +left_instramp_p_to_analog0 +right_instramp_to_adc1.* +right_instramp_to_comp_n.* +right_instramp_to_ulpcomp_n.* +right_hgbw_opamp_to_adc1.* +right_hgbw_opamp_to_comp_n.* +right_hgbw_opamp_to_ulpcomp_n.* +right_lp_opamp_to_adc0.* +right_lp_opamp_to_comp_p.* +right_lp_opamp_to_ulpcomp_p.* +left_instramp_n_to_amuxbusB +left_instramp_n_to_analog1 +left_instramp_to_amuxbusB.* +left_instramp_to_analog1.* +left_instramp_to_adc0.* +left_instramp_to_comp_p.* +left_instramp_to_ulpcomp_p.* +left_lp_opamp_to_gpio4_0.* +left_hgbw_opamp_to_gpio4_1.* +right_hgbw_opamp_to_gpio4_2.* +right_lp_opamp_to_gpio4_3.* +left_instramp_to_gpio4_4.* +left_hgbw_opamp_to_gpio4_5.* +right_hgbw_opamp_to_gpio4_6.* +right_lp_opamp_to_gpio4_7.* +right_hgbw_opamp_p_to_gpio5_0.* +right_hgbw_opamp_n_to_gpio5_1.* +left_hgbw_opamp_p_to_gpio5_2.* +left_hgbw_opamp_n_to_gpio5_3.* +left_lp_opamp_p_to_gpio5_4.* +left_lp_opamp_n_to_gpio5_5.* +left_instramp_p_to_gpio5_6.* +left_instramp_n_to_gpio5_7.* +ulpcomp_p_to_gpio6_0.* +ulpcomp_n_to_gpio6_1.* +comp_n_to_gpio6_3.* +comp_p_to_gpio6_2.* +adc0_to_gpio6_4.* +adc1_to_gpio6_5.* +adc_refh_to_gpio6_6.* +adc_refl_to_gpio6_7.* + +#S +PCLK +PRESETn +PWRITE +PWDATA.* +PADDR.* +PENABLE +PSEL +PREADY +PRDATA.* +IRQ +$300 \ No newline at end of file diff --git a/regs_analog_ctrl_APB/regs_analog_ctrl.v b/regs_analog_ctrl_APB/regs_analog_ctrl.v new file mode 100644 index 0000000..04350c7 --- /dev/null +++ b/regs_analog_ctrl_APB/regs_analog_ctrl.v @@ -0,0 +1,1063 @@ +// SPDX-FileCopyrightText: 2020 Efabless Corporation +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 + +`timescale 1ns/1ps +`default_nettype none + +module regs_analog_ctrl ( + + input clk, + input rst_n, + + // Test points enable/disable connections + input wire [1:0] bus_ibias_test_to_gpio1_2, + input wire [1:0] bus_vbg_test_to_gpio1_1, + + // iDAC enable/disable connections + input wire [1:0] bus_idac_to_gpio1_3, + input wire [1:0] bus_idac_to_gpio1_2, + + // ADC and DAC reference voltage selection enable/disable connections + input wire [1:0] bus_adc_refh_to_gpio6_6, + input wire [1:0] bus_dac_refh_to_gpio1_1, + input wire [1:0] bus_adc_refl_to_gpio6_7, + input wire [1:0] bus_dac_refl_to_gpio1_0, + + // Right lp op-amp output wire wire enable/disable connections + input wire [1:0] bus_right_lp_opamp_to_ulpcomp_p, + input wire [1:0] bus_right_lp_opamp_to_comp_p, + input wire [1:0] bus_right_lp_opamp_to_adc0, + input wire [1:0] bus_right_lp_opamp_to_gpio4_7, + input wire [1:0] bus_right_lp_opamp_to_gpio4_3, + input wire [1:0] bus_right_lp_opamp_to_analog1, + input wire [1:0] bus_right_lp_opamp_to_amuxbusB, + input wire [1:0] bus_right_lp_opamp_to_gpio3_7, + input wire [1:0] bus_right_lp_opamp_to_gpio3_3, + + // Right hgbw op-amp output wire wire enable/disable connections + input wire [1:0] bus_right_hgbw_opamp_to_ulpcomp_n, + input wire [1:0] bus_right_hgbw_opamp_to_comp_n, + input wire [1:0] bus_right_hgbw_opamp_to_adc1, + input wire [1:0] bus_right_hgbw_opamp_to_gpio4_6, + input wire [1:0] bus_right_hgbw_opamp_to_gpio4_2, + input wire [1:0] bus_right_hgbw_opamp_to_analog0, + input wire [1:0] bus_right_hgbw_opamp_to_amuxbusA, + input wire [1:0] bus_right_hgbw_opamp_to_gpio3_6, + input wire [1:0] bus_right_hgbw_opamp_to_gpio3_2, + + // Left hgbw op-amp output wire wire enable/disable connections + input wire [1:0] bus_left_hgbw_opamp_to_ulpcomp_p, + input wire [1:0] bus_left_hgbw_opamp_to_comp_p, + input wire [1:0] bus_left_hgbw_opamp_to_adc0, + input wire [1:0] bus_left_hgbw_opamp_to_gpio4_5, + input wire [1:0] bus_left_hgbw_opamp_to_gpio4_1, + input wire [1:0] bus_left_hgbw_opamp_to_analog1, + input wire [1:0] bus_left_hgbw_opamp_to_amuxbusB, + input wire [1:0] bus_left_hgbw_opamp_to_gpio3_5, + input wire [1:0] bus_left_hgbw_opamp_to_gpio3_1, + + // Left lp op-amp output wire wire enable/disable connections + input wire [1:0] bus_left_lp_opamp_to_ulpcomp_n, + input wire [1:0] bus_left_lp_opamp_to_comp_n, + input wire [1:0] bus_left_lp_opamp_to_adc1, + input wire [1:0] bus_left_lp_opamp_to_gpio4_0, + input wire [1:0] bus_left_lp_opamp_to_analog0, + input wire [1:0] bus_left_lp_opamp_to_amuxbusA, + input wire [1:0] bus_left_lp_opamp_to_gpio3_4, + + // Right lp op-amp positive input wire enable/disable connections + input wire bus_right_lp_opamp_p_to_dac0, + input wire bus_right_lp_opamp_p_to_analog0, + input wire bus_right_lp_opamp_p_to_amuxbusA, + input wire bus_right_lp_opamp_p_to_rheostat_out, + input wire bus_right_lp_opamp_p_to_sio0, + input wire bus_right_lp_opamp_p_to_tempsense, + input wire bus_right_lp_opamp_p_to_left_vref, + input wire bus_right_lp_opamp_p_to_voutref, + input wire [1:0] bus_right_lp_opamp_p_to_gpio2_5, + + // Right lp op-amp negative input wire enable/disable connections + input wire bus_right_lp_opamp_n_to_dac1, + input wire bus_right_lp_opamp_n_to_analog1, + input wire bus_right_lp_opamp_n_to_amuxbusB, + input wire bus_right_lp_opamp_n_to_rheostat_out, + input wire bus_right_lp_opamp_n_to_rheostat_tap, + input wire bus_right_lp_opamp_n_to_sio1, + input wire bus_right_lp_opamp_n_to_vbgtc, + input wire bus_right_lp_opamp_n_to_right_vref, + input wire bus_right_lp_opamp_n_to_vinref, + input wire [1:0] bus_right_lp_opamp_n_to_gpio2_4, + + // Right hgbw op-amp positive input wire enable/disable connections + input wire [1:0] bus_right_hgbw_opamp_p_to_gpio5_0, + input wire bus_right_hgbw_opamp_p_to_dac0, + input wire bus_right_hgbw_opamp_p_to_analog0, + input wire bus_right_hgbw_opamp_p_to_amuxbusA, + input wire bus_right_hgbw_opamp_p_to_rheostat_out, + input wire bus_right_hgbw_opamp_p_to_sio0, + input wire bus_right_hgbw_opamp_p_to_left_vref, + input wire bus_right_hgbw_opamp_p_to_voutref, + input wire [1:0] bus_right_hgbw_opamp_p_to_gpio2_3, + + // Right hgbw op-amp negative input wire enable/disable connections + input wire [1:0] bus_right_hgbw_opamp_n_to_gpio5_1, + input wire bus_right_hgbw_opamp_n_to_dac1, + input wire bus_right_hgbw_opamp_n_to_analog1, + input wire bus_right_hgbw_opamp_n_to_amuxbusB, + input wire bus_right_hgbw_opamp_n_to_rheostat_out, + input wire bus_right_hgbw_opamp_n_to_rheostat_tap, + input wire bus_right_hgbw_opamp_n_to_sio1, + input wire bus_right_hgbw_opamp_n_to_vbgsc, + input wire bus_right_hgbw_opamp_n_to_right_vref, + input wire bus_right_hgbw_opamp_n_to_vinref, + input wire [1:0] bus_right_hgbw_opamp_n_to_gpio2_2, + + // Left hgbw op-amp positive input wire enable/disable connections + input wire [1:0] bus_left_hgbw_opamp_p_to_gpio5_2, + input wire bus_left_hgbw_opamp_p_to_dac0, + input wire bus_left_hgbw_opamp_p_to_analog0, + input wire bus_left_hgbw_opamp_p_to_amuxbusA, + input wire bus_left_hgbw_opamp_p_to_rheostat_out, + input wire bus_left_hgbw_opamp_p_to_sio0, + input wire bus_left_hgbw_opamp_p_to_tempsense, + input wire bus_left_hgbw_opamp_p_to_left_vref, + input wire bus_left_hgbw_opamp_p_to_voutref, + input wire [1:0] bus_left_hgbw_opamp_p_to_gpio2_1, + + // Left hgbw op-amp negative input wire enable/disable connections + input wire [1:0] bus_left_hgbw_opamp_n_to_gpio5_3, + input wire bus_left_hgbw_opamp_n_to_dac1, + input wire bus_left_hgbw_opamp_n_to_analog1, + input wire bus_left_hgbw_opamp_n_to_amuxbusB, + input wire bus_left_hgbw_opamp_n_to_rheostat_out, + input wire bus_left_hgbw_opamp_n_to_rheostat_tap, + input wire bus_left_hgbw_opamp_n_to_sio1, + input wire bus_left_hgbw_opamp_n_to_vbgtc, + input wire bus_left_hgbw_opamp_n_to_right_vref, + input wire bus_left_hgbw_opamp_n_to_vinref, + input wire [1:0] bus_left_hgbw_opamp_n_to_gpio2_0, + + // Left lp op-amp positive input wire enable/disable connections + input wire [1:0] bus_left_lp_opamp_p_to_gpio5_4, + input wire bus_left_lp_opamp_p_to_dac0, + input wire bus_left_lp_opamp_p_to_analog0, + input wire bus_left_lp_opamp_p_to_amuxbusA, + input wire bus_left_lp_opamp_p_to_rheostat_out, + input wire bus_left_lp_opamp_p_to_sio0, + input wire bus_left_lp_opamp_p_to_left_vref, + input wire bus_left_lp_opamp_p_to_voutref, + + // Left lp op-amp negative input wire enable/disable connections + input wire [1:0] bus_left_lp_opamp_n_to_gpio5_5, + input wire bus_left_lp_opamp_n_to_dac1, + input wire bus_left_lp_opamp_n_to_analog1, + input wire bus_left_lp_opamp_n_to_amuxbusB, + input wire bus_left_lp_opamp_n_to_rheostat_out, + input wire bus_left_lp_opamp_n_to_rheostat_tap, + input wire bus_left_lp_opamp_n_to_sio1, + input wire bus_left_lp_opamp_n_to_vbgsc, + input wire bus_left_lp_opamp_n_to_right_vref, + input wire bus_left_lp_opamp_n_to_vinref, + + // Left instrumentation amplifier output wire wire enable/disable connections + input wire [1:0] bus_left_instramp_to_ulpcomp_p, + input wire [1:0] bus_left_instramp_to_comp_p, + input wire [1:0] bus_left_instramp_to_adc0, + input wire [1:0] bus_left_instramp_to_gpio4_4, + input wire [1:0] bus_left_instramp_to_analog1, + input wire [1:0] bus_left_instramp_to_amuxbusB, + + // Right instrumentation amplifier output wire wire enable/disable connections + input wire [1:0] bus_right_instramp_to_ulpcomp_n, + input wire [1:0] bus_right_instramp_to_comp_n, + input wire [1:0] bus_right_instramp_to_adc1, + input wire [1:0] bus_right_instramp_to_analog0, + input wire [1:0] bus_right_instramp_to_amuxbusA, + input wire [1:0] bus_right_instramp_to_gpio3_0, + + // Left instrumentation amplifier negative input wire enable/disable connections + input wire [1:0] bus_left_instramp_n_to_gpio5_7, + input wire bus_left_instramp_n_to_analog1, + input wire bus_left_instramp_n_to_amuxbusB, + input wire bus_left_instramp_n_to_sio1, + input wire bus_left_instramp_n_to_right_vref, + input wire bus_left_instramp_n_to_vinref, + + // Left instrumentation amplifier positive input wire enable/disable connections + input wire [1:0] bus_left_instramp_p_to_gpio5_6, + input wire bus_left_instramp_p_to_analog0, + input wire bus_left_instramp_p_to_amuxbusA, + input wire bus_left_instramp_p_to_sio0, + input wire bus_left_instramp_p_to_tempsense, + input wire bus_left_instramp_p_to_left_vref, + input wire bus_left_instramp_p_to_voutref, + + // Right instrumentation amplifier negative input wire enable/disable connections + input wire bus_right_instramp_n_to_analog1, + input wire bus_right_instramp_n_to_amuxbusB, + input wire bus_right_instramp_n_to_sio1, + input wire bus_right_instramp_n_to_right_vref, + input wire bus_right_instramp_n_to_vinref, + input wire [1:0] bus_right_instramp_n_to_gpio2_6, + + // Right instrumentation amplifier positive input wire enable/disable connections + input wire bus_right_instramp_p_to_analog0, + input wire bus_right_instramp_p_to_amuxbusA, + input wire bus_right_instramp_p_to_sio0, + input wire bus_right_instramp_p_to_tempsense, + input wire bus_right_instramp_p_to_left_vref, + input wire bus_right_instramp_p_to_voutref, + input wire [1:0] bus_right_instramp_p_to_gpio2_7, + + // ULP comparator positive input wire enable/disable connections + input wire bus_ulpcomp_p_to_dac0, + input wire bus_ulpcomp_p_to_analog1, + input wire bus_ulpcomp_p_to_sio0, + input wire bus_ulpcomp_p_to_vbgtc, + input wire bus_ulpcomp_p_to_tempsense, + input wire bus_ulpcomp_p_to_left_vref, + input wire bus_ulpcomp_p_to_voutref, + input wire [1:0] bus_ulpcomp_p_to_gpio6_0, + input wire [1:0] bus_ulpcomp_p_to_gpio1_7, + + // ULP comparator negative input wire enable/disable connections + input wire bus_ulpcomp_n_to_dac1, + input wire bus_ulpcomp_n_to_analog0, + input wire bus_ulpcomp_n_to_sio1, + input wire bus_ulpcomp_n_to_vbgsc, + input wire bus_ulpcomp_n_to_right_vref, + input wire bus_ulpcomp_n_to_vinref, + input wire [1:0] bus_ulpcomp_n_to_gpio6_1, + input wire [1:0] bus_ulpcomp_n_to_gpio1_6, + + // Comparator positive input wire enable/disable connections + input wire bus_comp_p_to_dac0, + input wire bus_comp_p_to_analog1, + input wire bus_comp_p_to_sio0, + input wire bus_comp_p_to_vbgtc, + input wire bus_comp_p_to_tempsense, + input wire bus_comp_p_to_left_vref, + input wire bus_comp_p_to_voutref, + input wire [1:0] bus_comp_p_to_gpio6_2, + input wire [1:0] bus_comp_p_to_gpio1_5, + + // Comparator negative input wire enable/disable connections + input wire bus_comp_n_to_dac1, + input wire bus_comp_n_to_analog0, + input wire bus_comp_n_to_sio1, + input wire bus_comp_n_to_vbgsc, + input wire bus_comp_n_to_right_vref, + input wire bus_comp_n_to_vinref, + input wire [1:0] bus_comp_n_to_gpio6_3, + input wire [1:0] bus_comp_n_to_gpio1_4, + + // ADC0 input wire enable/disable connections + input wire bus_adc0_to_dac0, + input wire bus_adc0_to_analog1, + input wire bus_adc0_to_vbgtc, + input wire bus_adc0_to_tempsense, + input wire bus_adc0_to_left_vref, + input wire bus_adc0_to_voutref, + input wire [1:0] bus_adc0_to_gpio6_4, + input wire [1:0] bus_adc0_to_gpio1_3, + + // ADC1 input wire enable/disable connections + input wire bus_adc1_to_dac1, + input wire bus_adc1_to_analog0, + input wire bus_adc1_to_vbgsc, + input wire bus_adc1_to_right_vref, + input wire bus_adc1_to_vinref, + input wire [1:0] bus_adc1_to_gpio6_5, + input wire [1:0] bus_adc1_to_gpio1_2, + + // SIO pin enable/disable connections + input wire [1:0] bus_sio0_connect, + input wire [1:0] bus_sio1_connect, + + // Analog pin enable/disable connections + input wire [1:0] bus_analog0_connect, + input wire [1:0] bus_analog1_connect, + + // User project enable/disable connections + input wire bus_vbgtc_to_user, + input wire bus_vbgsc_to_user, + input wire [1:0] bus_user_to_comp_n, + input wire [1:0] bus_user_to_comp_p, + input wire [1:0] bus_user_to_ulpcomp_n, + input wire [1:0] bus_user_to_ulpcomp_p, + input wire [1:0] bus_user_to_adc0, + input wire [1:0] bus_user_to_adc1, + input wire bus_dac0_to_user, + input wire bus_dac1_to_user, + input wire bus_tempsense_to_user, + input wire bus_right_vref_to_user, + input wire bus_left_vref_to_user, + input wire bus_vinref_to_user, + input wire bus_voutref_to_user, + + input wire bus_dac0_to_analog1, + input wire bus_dac1_to_analog0, + input wire [2-1:0] bus_audiodac_out_to_analog1, + input wire [2-1:0] bus_audiodac_outb_to_analog0, + + input wire [1-1:0] bus_left_instramp_ena, + input wire [5-1:0] bus_left_instramp_G1, + input wire [5-1:0] bus_left_instramp_G2, + input wire [1-1:0] bus_left_hgbw_opamp_ena, + input wire [1-1:0] bus_left_lp_opamp_ena, + input wire [8-1:0] bus_left_rheostat1_b, + input wire [8-1:0] bus_left_rheostat2_b, + input wire [1-1:0] bus_right_instramp_ena, + input wire [5-1:0] bus_right_instramp_G1, + input wire [5-1:0] bus_right_instramp_G2, + input wire [1-1:0] bus_right_hgbw_opamp_ena, + input wire [1-1:0] bus_right_lp_opamp_ena, + input wire [8-1:0] bus_right_rheostat1_b, + input wire [8-1:0] bus_right_rheostat2_b, + input wire [1-1:0] bus_comp_ena, + input wire [6-1:0] bus_comp_trim, + input wire [2-1:0] bus_comp_hyst, + input wire [1-1:0] bus_ulpcomp_ena, + input wire [1-1:0] bus_ulpcomp_clk, + input wire [1-1:0] bus_bandgap_ena, + input wire [16-1:0] bus_bandgap_trim, + input wire [1-1:0] bus_bandgap_sel, + input wire [1-1:0] bus_ldo_ena, + input wire [1-1:0] bus_overvoltage_ena, + input wire [4-1:0] bus_overvoltage_trim, + input wire [1-1:0] bus_ldo_ref_sel, + input wire [1-1:0] bus_ibias_ena, + input wire [24-1:0] bus_ibias_src_ena, + input wire [4-1:0] bus_ibias_snk_ena, + input wire [1-1:0] bus_ibias_ref_select, + input wire [12-1:0] bus_idac_value, + input wire [1-1:0] bus_idac_ena, + input wire [1-1:0] bus_tempsense_ena, + input wire [1-1:0] bus_tempsense_sel, + input wire [1-1:0] bus_rdac0_ena, + input wire [12-1:0] bus_rdac0_value, + input wire [1-1:0] bus_rdac1_ena, + input wire [12-1:0] bus_rdac1_value, + + input wire [1-1:0] bus_brownout_ena, + input wire [3-1:0] bus_brownout_vtrip, + input wire [3-1:0] bus_brownout_otrip, + input wire [1-1:0] bus_brownout_isrc_sel, + input wire [1-1:0] bus_brownout_oneshot, + input wire [1-1:0] bus_brownout_rc_ena, + input wire [1-1:0] bus_brownout_rc_dis, + + output wire [1-1:0] bus_brownout_vunder, + output wire [1-1:0] bus_brownout_timeout, + output wire [1-1:0] bus_brownout_filt, + output wire [1-1:0] bus_brownout_unfilt, + + output wire [1-1:0] bus_comp_out, + output wire [1-1:0] bus_ulpcomp_out, + output wire [1-1:0] bus_overvoltage_out, + output wire [1-1:0] bus_vdda1_pwr_good, + output wire [1-1:0] bus_vccd1_pwr_good, + output wire [1-1:0] bus_vdda2_pwr_good, + output wire [1-1:0] bus_vccd2_pwr_good, + + // Test points enable/disable connections + output wire [1:0] ibias_test_to_gpio1_2, + output wire [1:0] vbg_test_to_gpio1_1, + + // iDAC enable/disable connections + output wire [1:0] idac_to_gpio1_3, + output wire [1:0] idac_to_gpio1_2, + + // ADC and DAC reference voltage selection enable/disable connections + output wire [1:0] adc_refh_to_gpio6_6, + output wire [1:0] dac_refh_to_gpio1_1, + output wire [1:0] adc_refl_to_gpio6_7, + output wire [1:0] dac_refl_to_gpio1_0, + + // Right lp op-amp output wire enable/disable connections + output wire [1:0] right_lp_opamp_to_ulpcomp_p, + output wire [1:0] right_lp_opamp_to_comp_p, + output wire [1:0] right_lp_opamp_to_adc0, + output wire [1:0] right_lp_opamp_to_gpio4_7, + output wire [1:0] right_lp_opamp_to_gpio4_3, + output wire [1:0] right_lp_opamp_to_analog1, + output wire [1:0] right_lp_opamp_to_amuxbusB, + output wire [1:0] right_lp_opamp_to_gpio3_7, + output wire [1:0] right_lp_opamp_to_gpio3_3, + + // Right hgbw op-amp output wire enable/disable connections + output wire [1:0] right_hgbw_opamp_to_ulpcomp_n, + output wire [1:0] right_hgbw_opamp_to_comp_n, + output wire [1:0] right_hgbw_opamp_to_adc1, + output wire [1:0] right_hgbw_opamp_to_gpio4_6, + output wire [1:0] right_hgbw_opamp_to_gpio4_2, + output wire [1:0] right_hgbw_opamp_to_analog0, + output wire [1:0] right_hgbw_opamp_to_amuxbusA, + output wire [1:0] right_hgbw_opamp_to_gpio3_6, + output wire [1:0] right_hgbw_opamp_to_gpio3_2, + + // Left hgbw op-amp output wire enable/disable connections + output wire [1:0] left_hgbw_opamp_to_ulpcomp_p, + output wire [1:0] left_hgbw_opamp_to_comp_p, + output wire [1:0] left_hgbw_opamp_to_adc0, + output wire [1:0] left_hgbw_opamp_to_gpio4_5, + output wire [1:0] left_hgbw_opamp_to_gpio4_1, + output wire [1:0] left_hgbw_opamp_to_analog1, + output wire [1:0] left_hgbw_opamp_to_amuxbusB, + output wire [1:0] left_hgbw_opamp_to_gpio3_5, + output wire [1:0] left_hgbw_opamp_to_gpio3_1, + + // Left lp op-amp output wire enable/disable connections + output wire [1:0] left_lp_opamp_to_ulpcomp_n, + output wire [1:0] left_lp_opamp_to_comp_n, + output wire [1:0] left_lp_opamp_to_adc1, + output wire [1:0] left_lp_opamp_to_gpio4_0, + output wire [1:0] left_lp_opamp_to_analog0, + output wire [1:0] left_lp_opamp_to_amuxbusA, + output wire [1:0] left_lp_opamp_to_gpio3_4, + + // Right lp op-amp positive output wire enable/disable connections + output wire right_lp_opamp_p_to_dac0, + output wire right_lp_opamp_p_to_analog0, + output wire right_lp_opamp_p_to_amuxbusA, + output wire right_lp_opamp_p_to_rheostat_out, + output wire right_lp_opamp_p_to_sio0, + output wire right_lp_opamp_p_to_tempsense, + output wire right_lp_opamp_p_to_left_vref, + output wire right_lp_opamp_p_to_voutref, + output wire [1:0] right_lp_opamp_p_to_gpio2_5, + + // Right lp op-amp negative output wire enable/disable connections + output wire right_lp_opamp_n_to_dac1, + output wire right_lp_opamp_n_to_analog1, + output wire right_lp_opamp_n_to_amuxbusB, + output wire right_lp_opamp_n_to_rheostat_out, + output wire right_lp_opamp_n_to_rheostat_tap, + output wire right_lp_opamp_n_to_sio1, + output wire right_lp_opamp_n_to_vbgtc, + output wire right_lp_opamp_n_to_right_vref, + output wire right_lp_opamp_n_to_vinref, + output wire [1:0] right_lp_opamp_n_to_gpio2_4, + + // Right hgbw op-amp positive output wire enable/disable connections + output wire [1:0] right_hgbw_opamp_p_to_gpio5_0, + output wire right_hgbw_opamp_p_to_dac0, + output wire right_hgbw_opamp_p_to_analog0, + output wire right_hgbw_opamp_p_to_amuxbusA, + output wire right_hgbw_opamp_p_to_rheostat_out, + output wire right_hgbw_opamp_p_to_sio0, + output wire right_hgbw_opamp_p_to_left_vref, + output wire right_hgbw_opamp_p_to_voutref, + output wire [1:0] right_hgbw_opamp_p_to_gpio2_3, + + // Right hgbw op-amp negative output wire enable/disable connections + output wire [1:0] right_hgbw_opamp_n_to_gpio5_1, + output wire right_hgbw_opamp_n_to_dac1, + output wire right_hgbw_opamp_n_to_analog1, + output wire right_hgbw_opamp_n_to_amuxbusB, + output wire right_hgbw_opamp_n_to_rheostat_out, + output wire right_hgbw_opamp_n_to_rheostat_tap, + output wire right_hgbw_opamp_n_to_sio1, + output wire right_hgbw_opamp_n_to_vbgsc, + output wire right_hgbw_opamp_n_to_right_vref, + output wire right_hgbw_opamp_n_to_vinref, + output wire [1:0] right_hgbw_opamp_n_to_gpio2_2, + + // Left hgbw op-amp positive output wire enable/disable connections + output wire [1:0] left_hgbw_opamp_p_to_gpio5_2, + output wire left_hgbw_opamp_p_to_dac0, + output wire left_hgbw_opamp_p_to_analog0, + output wire left_hgbw_opamp_p_to_amuxbusA, + output wire left_hgbw_opamp_p_to_rheostat_out, + output wire left_hgbw_opamp_p_to_sio0, + output wire left_hgbw_opamp_p_to_tempsense, + output wire left_hgbw_opamp_p_to_left_vref, + output wire left_hgbw_opamp_p_to_voutref, + output wire [1:0] left_hgbw_opamp_p_to_gpio2_1, + + // Left hgbw op-amp negative output wire enable/disable connections + output wire [1:0] left_hgbw_opamp_n_to_gpio5_3, + output wire left_hgbw_opamp_n_to_dac1, + output wire left_hgbw_opamp_n_to_analog1, + output wire left_hgbw_opamp_n_to_amuxbusB, + output wire left_hgbw_opamp_n_to_rheostat_out, + output wire left_hgbw_opamp_n_to_rheostat_tap, + output wire left_hgbw_opamp_n_to_sio1, + output wire left_hgbw_opamp_n_to_vbgtc, + output wire left_hgbw_opamp_n_to_right_vref, + output wire left_hgbw_opamp_n_to_vinref, + output wire [1:0] left_hgbw_opamp_n_to_gpio2_0, + + // Left lp op-amp positive output wire enable/disable connections + output wire [1:0] left_lp_opamp_p_to_gpio5_4, + output wire left_lp_opamp_p_to_dac0, + output wire left_lp_opamp_p_to_analog0, + output wire left_lp_opamp_p_to_amuxbusA, + output wire left_lp_opamp_p_to_rheostat_out, + output wire left_lp_opamp_p_to_sio0, + output wire left_lp_opamp_p_to_left_vref, + output wire left_lp_opamp_p_to_voutref, + + // Left lp op-amp negative output wire enable/disable connections + output wire [1:0] left_lp_opamp_n_to_gpio5_5, + output wire left_lp_opamp_n_to_dac1, + output wire left_lp_opamp_n_to_analog1, + output wire left_lp_opamp_n_to_amuxbusB, + output wire left_lp_opamp_n_to_rheostat_out, + output wire left_lp_opamp_n_to_rheostat_tap, + output wire left_lp_opamp_n_to_sio1, + output wire left_lp_opamp_n_to_vbgsc, + output wire left_lp_opamp_n_to_right_vref, + output wire left_lp_opamp_n_to_vinref, + + // Left instrumentation amplifier output wire enable/disable connections + output wire [1:0] left_instramp_to_ulpcomp_p, + output wire [1:0] left_instramp_to_comp_p, + output wire [1:0] left_instramp_to_adc0, + output wire [1:0] left_instramp_to_gpio4_4, + output wire [1:0] left_instramp_to_analog1, + output wire [1:0] left_instramp_to_amuxbusB, + + // Right instrumentation amplifier output wire enable/disable connections + output wire [1:0] right_instramp_to_ulpcomp_n, + output wire [1:0] right_instramp_to_comp_n, + output wire [1:0] right_instramp_to_adc1, + output wire [1:0] right_instramp_to_analog0, + output wire [1:0] right_instramp_to_amuxbusA, + output wire [1:0] right_instramp_to_gpio3_0, + + // Left instrumentation amplifier negative output wire enable/disable connections + output wire [1:0] left_instramp_n_to_gpio5_7, + output wire left_instramp_n_to_analog1, + output wire left_instramp_n_to_amuxbusB, + output wire left_instramp_n_to_sio1, + output wire left_instramp_n_to_right_vref, + output wire left_instramp_n_to_vinref, + + // Left instrumentation amplifier positive output wire enable/disable connections + output wire [1:0] left_instramp_p_to_gpio5_6, + output wire left_instramp_p_to_analog0, + output wire left_instramp_p_to_amuxbusA, + output wire left_instramp_p_to_sio0, + output wire left_instramp_p_to_tempsense, + output wire left_instramp_p_to_left_vref, + output wire left_instramp_p_to_voutref, + + // Right instrumentation amplifier negative output wire enable/disable connections + output wire right_instramp_n_to_analog1, + output wire right_instramp_n_to_amuxbusB, + output wire right_instramp_n_to_sio1, + output wire right_instramp_n_to_right_vref, + output wire right_instramp_n_to_vinref, + output wire [1:0] right_instramp_n_to_gpio2_6, + + // Right instrumentation amplifier positive output wire enable/disable connections + output wire right_instramp_p_to_analog0, + output wire right_instramp_p_to_amuxbusA, + output wire right_instramp_p_to_sio0, + output wire right_instramp_p_to_tempsense, + output wire right_instramp_p_to_left_vref, + output wire right_instramp_p_to_voutref, + output wire [1:0] right_instramp_p_to_gpio2_7, + + // ULP comparator positive output wire enable/disable connections + output wire ulpcomp_p_to_dac0, + output wire ulpcomp_p_to_analog1, + output wire ulpcomp_p_to_sio0, + output wire ulpcomp_p_to_vbgtc, + output wire ulpcomp_p_to_tempsense, + output wire ulpcomp_p_to_left_vref, + output wire ulpcomp_p_to_voutref, + output wire [1:0] ulpcomp_p_to_gpio6_0, + output wire [1:0] ulpcomp_p_to_gpio1_7, + + // ULP comparator negative output wire enable/disable connections + output wire ulpcomp_n_to_dac1, + output wire ulpcomp_n_to_analog0, + output wire ulpcomp_n_to_sio1, + output wire ulpcomp_n_to_vbgsc, + output wire ulpcomp_n_to_right_vref, + output wire ulpcomp_n_to_vinref, + output wire [1:0] ulpcomp_n_to_gpio6_1, + output wire [1:0] ulpcomp_n_to_gpio1_6, + + // Comparator positive output wire enable/disable connections + output wire comp_p_to_dac0, + output wire comp_p_to_analog1, + output wire comp_p_to_sio0, + output wire comp_p_to_vbgtc, + output wire comp_p_to_tempsense, + output wire comp_p_to_left_vref, + output wire comp_p_to_voutref, + output wire [1:0] comp_p_to_gpio6_2, + output wire [1:0] comp_p_to_gpio1_5, + + // Comparator negative output wire enable/disable connections + output wire comp_n_to_dac1, + output wire comp_n_to_analog0, + output wire comp_n_to_sio1, + output wire comp_n_to_vbgsc, + output wire comp_n_to_right_vref, + output wire comp_n_to_vinref, + output wire [1:0] comp_n_to_gpio6_3, + output wire [1:0] comp_n_to_gpio1_4, + + // ADC0 output wire enable/disable connections + output wire adc0_to_dac0, + output wire adc0_to_analog1, + output wire adc0_to_vbgtc, + output wire adc0_to_tempsense, + output wire adc0_to_left_vref, + output wire adc0_to_voutref, + output wire [1:0] adc0_to_gpio6_4, + output wire [1:0] adc0_to_gpio1_3, + + // ADC1 output wire enable/disable connections + output wire adc1_to_dac1, + output wire adc1_to_analog0, + output wire adc1_to_vbgsc, + output wire adc1_to_right_vref, + output wire adc1_to_vinref, + output wire [1:0] adc1_to_gpio6_5, + output wire [1:0] adc1_to_gpio1_2, + + // SIO pin enable/disable connections + output wire [1:0] sio0_connect, + output wire [1:0] sio1_connect, + + // Analog pin enable/disable connections + output wire [1:0] analog0_connect, + output wire [1:0] analog1_connect, + + // User project enable/disable connections + output wire vbgtc_to_user, + output wire vbgsc_to_user, + output wire [1:0] user_to_comp_n, + output wire [1:0] user_to_comp_p, + output wire [1:0] user_to_ulpcomp_n, + output wire [1:0] user_to_ulpcomp_p, + output wire [1:0] user_to_adc0, + output wire [1:0] user_to_adc1, + output wire dac0_to_user, + output wire dac1_to_user, + output wire tempsense_to_user, + output wire right_vref_to_user, + output wire left_vref_to_user, + output wire vinref_to_user, + output wire voutref_to_user, + + // Audiodac output connections + output wire dac0_to_analog1, + output wire dac1_to_analog0, + output wire [1:0] audiodac_out_to_analog1, + output wire [1:0] audiodac_outb_to_analog0, + + // Instrumentation amplifier (TBD) + output wire left_instramp_ena, + output wire [4:0] left_instramp_G1, // programmable gain + output wire [4:0] left_instramp_G2, // programmable gain + + // High gain-bandwidth operational amplifier + output wire left_hgbw_opamp_ena, + + // Low power operational amplifier (TBD) + output wire left_lp_opamp_ena, + + // Rheostat 1 + output wire [7:0] left_rheostat1_b, // programmable tap + + // Rheostat 2 + output wire [7:0] left_rheostat2_b, // programmable tap + + // Amplifiers right + // Instrumentation amplifier (TBD) + output wire right_instramp_ena, + output wire [4:0] right_instramp_G1, // programmable gain + output wire [4:0] right_instramp_G2, // programmable gain + + // High gain-bandwidth operational amplifier + output wire right_hgbw_opamp_ena, + + // Low power operational amplifier (TBD) + output wire right_lp_opamp_ena, + + // Rheostat 1 + output wire [7:0] right_rheostat1_b, // programmable tap + + // Rheostat 2 + output wire [7:0] right_rheostat2_b, // programmable tap + + // Comparator + output wire comp_ena, + output wire [5:0] comp_trim, // offset trim + output wire [1:0] comp_hyst, // hysteresis trim + input wire comp_out, // comparator output wire + + // Ultra-low-power comparator + output wire ulpcomp_ena, + output wire ulpcomp_clk, + input wire ulpcomp_out, // comparator output wire + + // Bandgap + output wire bandgap_ena, + output wire [15:0] bandgap_trim, // bandgap trim + output wire bandgap_sel, + + // LDO + output wire ldo_ena, + + // Bias current generator + output wire ibias_ena, // bias generator master enable + output wire [23:0] ibias_src_ena, // bias generator individual source enables + output wire [3:0] ibias_snk_ena, // bias generator individual sink enables + output wire ibias_ref_select, // bias reference voltage selection + + // Overvoltage detector + output wire overvoltage_ena, + output wire [3:0] overvoltage_trim, // overvoltage trip point set + output wire ldo_ref_sel, + input wire overvoltage_out, // overvoltage alarm + + // 12-bit Current DAC (TBD) + output wire [11:0] idac_value, + output wire idac_ena, + + // Temperature sensor + output wire tempsense_ena, + output wire tempsense_sel, + + // Voltage detector 0 + input wire vdda1_pwr_good, // power good signal + input wire vccd1_pwr_good, // power good signal + + // Voltage detector 1 + input wire vdda2_pwr_good, // power good signal + input wire vccd2_pwr_good, // power good signal + + // 12-bit RDAC 0 + output wire rdac0_ena, + output wire [11:0] rdac0_value, + + // 12-bit RDAC 1 + output wire rdac1_ena, + output wire [11:0] rdac1_value, + + // Brownout detector + output brownout_ena, // brownout detector enable + output [2:0] brownout_vtrip, // brownout detector trip point + output [2:0] brownout_otrip, // brownout detector trip point + output brownout_isrc_sel, // brownout detector select current bias + output brownout_oneshot, // brownout detector force short one-shot + output brownout_rc_ena, // brownout detector force oscillator enabled + output brownout_rc_dis, // brownout detector force oscillator disabled + + input brownout_vunder, // brownout detector undervoltage alarm + input brownout_timeout, // brownout detector timeout + input brownout_filt, // brownout detector undervoltage (filtered) + input brownout_unfilt // brownout detector undervoltage (unfiltered) + +); + +assign ibias_test_to_gpio1_2 = bus_ibias_test_to_gpio1_2; +assign vbg_test_to_gpio1_1 = bus_vbg_test_to_gpio1_1; +assign idac_to_gpio1_3 = bus_idac_to_gpio1_3; +assign idac_to_gpio1_2 = bus_idac_to_gpio1_2; +assign adc_refh_to_gpio6_6 = bus_adc_refh_to_gpio6_6; +assign dac_refh_to_gpio1_1 = bus_dac_refh_to_gpio1_1; +assign adc_refl_to_gpio6_7 = bus_adc_refl_to_gpio6_7; +assign dac_refl_to_gpio1_0 = bus_dac_refl_to_gpio1_0; +assign right_lp_opamp_to_ulpcomp_p = bus_right_lp_opamp_to_ulpcomp_p; +assign right_lp_opamp_to_comp_p = bus_right_lp_opamp_to_comp_p; +assign right_lp_opamp_to_adc0 = bus_right_lp_opamp_to_adc0; +assign right_lp_opamp_to_gpio4_7 = bus_right_lp_opamp_to_gpio4_7; +assign right_lp_opamp_to_gpio4_3 = bus_right_lp_opamp_to_gpio4_3; +assign right_lp_opamp_to_analog1 = bus_right_lp_opamp_to_analog1; +assign right_lp_opamp_to_amuxbusB = bus_right_lp_opamp_to_amuxbusB; +assign right_lp_opamp_to_gpio3_7 = bus_right_lp_opamp_to_gpio3_7; +assign right_lp_opamp_to_gpio3_3 = bus_right_lp_opamp_to_gpio3_3; +assign right_hgbw_opamp_to_ulpcomp_n = bus_right_hgbw_opamp_to_ulpcomp_n; +assign right_hgbw_opamp_to_comp_n = bus_right_hgbw_opamp_to_comp_n; +assign right_hgbw_opamp_to_adc1 = bus_right_hgbw_opamp_to_adc1; +assign right_hgbw_opamp_to_gpio4_6 = bus_right_hgbw_opamp_to_gpio4_6; +assign right_hgbw_opamp_to_gpio4_2 = bus_right_hgbw_opamp_to_gpio4_2; +assign right_hgbw_opamp_to_analog0 = bus_right_hgbw_opamp_to_analog0; +assign right_hgbw_opamp_to_amuxbusA = bus_right_hgbw_opamp_to_amuxbusA; +assign right_hgbw_opamp_to_gpio3_6 = bus_right_hgbw_opamp_to_gpio3_6; +assign right_hgbw_opamp_to_gpio3_2 = bus_right_hgbw_opamp_to_gpio3_2; +assign left_hgbw_opamp_to_ulpcomp_p = bus_left_hgbw_opamp_to_ulpcomp_p; +assign left_hgbw_opamp_to_comp_p = bus_left_hgbw_opamp_to_comp_p; +assign left_hgbw_opamp_to_adc0 = bus_left_hgbw_opamp_to_adc0; +assign left_hgbw_opamp_to_gpio4_5 = bus_left_hgbw_opamp_to_gpio4_5; +assign left_hgbw_opamp_to_gpio4_1 = bus_left_hgbw_opamp_to_gpio4_1; +assign left_hgbw_opamp_to_analog1 = bus_left_hgbw_opamp_to_analog1; +assign left_hgbw_opamp_to_amuxbusB = bus_left_hgbw_opamp_to_amuxbusB; +assign left_hgbw_opamp_to_gpio3_5 = bus_left_hgbw_opamp_to_gpio3_5; +assign left_hgbw_opamp_to_gpio3_1 = bus_left_hgbw_opamp_to_gpio3_1; +assign left_lp_opamp_to_ulpcomp_n = bus_left_lp_opamp_to_ulpcomp_n; +assign left_lp_opamp_to_comp_n = bus_left_lp_opamp_to_comp_n; +assign left_lp_opamp_to_adc1 = bus_left_lp_opamp_to_adc1; +assign left_lp_opamp_to_gpio4_0 = bus_left_lp_opamp_to_gpio4_0; +assign left_lp_opamp_to_analog0 = bus_left_lp_opamp_to_analog0; +assign left_lp_opamp_to_amuxbusA = bus_left_lp_opamp_to_amuxbusA; +assign left_lp_opamp_to_gpio3_4 = bus_left_lp_opamp_to_gpio3_4; +assign right_lp_opamp_p_to_dac0 = bus_right_lp_opamp_p_to_dac0; +assign right_lp_opamp_p_to_analog0 = bus_right_lp_opamp_p_to_analog0; +assign right_lp_opamp_p_to_amuxbusA = bus_right_lp_opamp_p_to_amuxbusA; +assign right_lp_opamp_p_to_rheostat_out = bus_right_lp_opamp_p_to_rheostat_out; +assign right_lp_opamp_p_to_sio0 = bus_right_lp_opamp_p_to_sio0; +assign right_lp_opamp_p_to_tempsense = bus_right_lp_opamp_p_to_tempsense; +assign right_lp_opamp_p_to_left_vref = bus_right_lp_opamp_p_to_left_vref; +assign right_lp_opamp_p_to_voutref = bus_right_lp_opamp_p_to_voutref; +assign right_lp_opamp_p_to_gpio2_5 = bus_right_lp_opamp_p_to_gpio2_5; +assign right_lp_opamp_n_to_dac1 = bus_right_lp_opamp_n_to_dac1; +assign right_lp_opamp_n_to_analog1 = bus_right_lp_opamp_n_to_analog1; +assign right_lp_opamp_n_to_amuxbusB = bus_right_lp_opamp_n_to_amuxbusB; +assign right_lp_opamp_n_to_rheostat_out = bus_right_lp_opamp_n_to_rheostat_out; +assign right_lp_opamp_n_to_rheostat_tap = bus_right_lp_opamp_n_to_rheostat_tap; +assign right_lp_opamp_n_to_sio1 = bus_right_lp_opamp_n_to_sio1; +assign right_lp_opamp_n_to_vbgtc = bus_right_lp_opamp_n_to_vbgtc; +assign right_lp_opamp_n_to_right_vref = bus_right_lp_opamp_n_to_right_vref; +assign right_lp_opamp_n_to_vinref = bus_right_lp_opamp_n_to_vinref; +assign right_lp_opamp_n_to_gpio2_4 = bus_right_lp_opamp_n_to_gpio2_4; +assign right_hgbw_opamp_p_to_gpio5_0 = bus_right_hgbw_opamp_p_to_gpio5_0; +assign right_hgbw_opamp_p_to_dac0 = bus_right_hgbw_opamp_p_to_dac0; +assign right_hgbw_opamp_p_to_analog0 = bus_right_hgbw_opamp_p_to_analog0; +assign right_hgbw_opamp_p_to_amuxbusA = bus_right_hgbw_opamp_p_to_amuxbusA; +assign right_hgbw_opamp_p_to_rheostat_out = bus_right_hgbw_opamp_p_to_rheostat_out; +assign right_hgbw_opamp_p_to_sio0 = bus_right_hgbw_opamp_p_to_sio0; +assign right_hgbw_opamp_p_to_left_vref = bus_right_hgbw_opamp_p_to_left_vref; +assign right_hgbw_opamp_p_to_voutref = bus_right_hgbw_opamp_p_to_voutref; +assign right_hgbw_opamp_p_to_gpio2_3 = bus_right_hgbw_opamp_p_to_gpio2_3; +assign right_hgbw_opamp_n_to_gpio5_1 = bus_right_hgbw_opamp_n_to_gpio5_1; +assign right_hgbw_opamp_n_to_dac1 = bus_right_hgbw_opamp_n_to_dac1; +assign right_hgbw_opamp_n_to_analog1 = bus_right_hgbw_opamp_n_to_analog1; +assign right_hgbw_opamp_n_to_amuxbusB = bus_right_hgbw_opamp_n_to_amuxbusB; +assign right_hgbw_opamp_n_to_rheostat_out = bus_right_hgbw_opamp_n_to_rheostat_out; +assign right_hgbw_opamp_n_to_rheostat_tap = bus_right_hgbw_opamp_n_to_rheostat_tap; +assign right_hgbw_opamp_n_to_sio1 = bus_right_hgbw_opamp_n_to_sio1; +assign right_hgbw_opamp_n_to_vbgsc = bus_right_hgbw_opamp_n_to_vbgsc; +assign right_hgbw_opamp_n_to_right_vref = bus_right_hgbw_opamp_n_to_right_vref; +assign right_hgbw_opamp_n_to_vinref = bus_right_hgbw_opamp_n_to_vinref; +assign right_hgbw_opamp_n_to_gpio2_2 = bus_right_hgbw_opamp_n_to_gpio2_2; +assign left_hgbw_opamp_p_to_gpio5_2 = bus_left_hgbw_opamp_p_to_gpio5_2; +assign left_hgbw_opamp_p_to_dac0 = bus_left_hgbw_opamp_p_to_dac0; +assign left_hgbw_opamp_p_to_analog0 = bus_left_hgbw_opamp_p_to_analog0; +assign left_hgbw_opamp_p_to_amuxbusA = bus_left_hgbw_opamp_p_to_amuxbusA; +assign left_hgbw_opamp_p_to_rheostat_out = bus_left_hgbw_opamp_p_to_rheostat_out; +assign left_hgbw_opamp_p_to_sio0 = bus_left_hgbw_opamp_p_to_sio0; +assign left_hgbw_opamp_p_to_tempsense = bus_left_hgbw_opamp_p_to_tempsense; +assign left_hgbw_opamp_p_to_left_vref = bus_left_hgbw_opamp_p_to_left_vref; +assign left_hgbw_opamp_p_to_voutref = bus_left_hgbw_opamp_p_to_voutref; +assign left_hgbw_opamp_p_to_gpio2_1 = bus_left_hgbw_opamp_p_to_gpio2_1; +assign left_hgbw_opamp_n_to_gpio5_3 = bus_left_hgbw_opamp_n_to_gpio5_3; +assign left_hgbw_opamp_n_to_dac1 = bus_left_hgbw_opamp_n_to_dac1; +assign left_hgbw_opamp_n_to_analog1 = bus_left_hgbw_opamp_n_to_analog1; +assign left_hgbw_opamp_n_to_amuxbusB = bus_left_hgbw_opamp_n_to_amuxbusB; +assign left_hgbw_opamp_n_to_rheostat_out = bus_left_hgbw_opamp_n_to_rheostat_out; +assign left_hgbw_opamp_n_to_rheostat_tap = bus_left_hgbw_opamp_n_to_rheostat_tap; +assign left_hgbw_opamp_n_to_sio1 = bus_left_hgbw_opamp_n_to_sio1; +assign left_hgbw_opamp_n_to_vbgtc = bus_left_hgbw_opamp_n_to_vbgtc; +assign left_hgbw_opamp_n_to_right_vref = bus_left_hgbw_opamp_n_to_right_vref; +assign left_hgbw_opamp_n_to_vinref = bus_left_hgbw_opamp_n_to_vinref; +assign left_hgbw_opamp_n_to_gpio2_0 = bus_left_hgbw_opamp_n_to_gpio2_0; +assign left_lp_opamp_p_to_gpio5_4 = bus_left_lp_opamp_p_to_gpio5_4; +assign left_lp_opamp_p_to_dac0 = bus_left_lp_opamp_p_to_dac0; +assign left_lp_opamp_p_to_analog0 = bus_left_lp_opamp_p_to_analog0; +assign left_lp_opamp_p_to_amuxbusA = bus_left_lp_opamp_p_to_amuxbusA; +assign left_lp_opamp_p_to_rheostat_out = bus_left_lp_opamp_p_to_rheostat_out; +assign left_lp_opamp_p_to_sio0 = bus_left_lp_opamp_p_to_sio0; +assign left_lp_opamp_p_to_left_vref = bus_left_lp_opamp_p_to_left_vref; +assign left_lp_opamp_p_to_voutref = bus_left_lp_opamp_p_to_voutref; +assign left_lp_opamp_n_to_gpio5_5 = bus_left_lp_opamp_n_to_gpio5_5; +assign left_lp_opamp_n_to_dac1 = bus_left_lp_opamp_n_to_dac1; +assign left_lp_opamp_n_to_analog1 = bus_left_lp_opamp_n_to_analog1; +assign left_lp_opamp_n_to_amuxbusB = bus_left_lp_opamp_n_to_amuxbusB; +assign left_lp_opamp_n_to_rheostat_out = bus_left_lp_opamp_n_to_rheostat_out; +assign left_lp_opamp_n_to_rheostat_tap = bus_left_lp_opamp_n_to_rheostat_tap; +assign left_lp_opamp_n_to_sio1 = bus_left_lp_opamp_n_to_sio1; +assign left_lp_opamp_n_to_vbgsc = bus_left_lp_opamp_n_to_vbgsc; +assign left_lp_opamp_n_to_right_vref = bus_left_lp_opamp_n_to_right_vref; +assign left_lp_opamp_n_to_vinref = bus_left_lp_opamp_n_to_vinref; +assign left_instramp_to_ulpcomp_p = bus_left_instramp_to_ulpcomp_p; +assign left_instramp_to_comp_p = bus_left_instramp_to_comp_p; +assign left_instramp_to_adc0 = bus_left_instramp_to_adc0; +assign left_instramp_to_gpio4_4 = bus_left_instramp_to_gpio4_4; +assign left_instramp_to_analog1 = bus_left_instramp_to_analog1; +assign left_instramp_to_amuxbusB = bus_left_instramp_to_amuxbusB; +assign right_instramp_to_ulpcomp_n = bus_right_instramp_to_ulpcomp_n; +assign right_instramp_to_comp_n = bus_right_instramp_to_comp_n; +assign right_instramp_to_adc1 = bus_right_instramp_to_adc1; +assign right_instramp_to_analog0 = bus_right_instramp_to_analog0; +assign right_instramp_to_amuxbusA = bus_right_instramp_to_amuxbusA; +assign right_instramp_to_gpio3_0 = bus_right_instramp_to_gpio3_0; +assign left_instramp_n_to_gpio5_7 = bus_left_instramp_n_to_gpio5_7; +assign left_instramp_n_to_analog1 = bus_left_instramp_n_to_analog1; +assign left_instramp_n_to_amuxbusB = bus_left_instramp_n_to_amuxbusB; +assign left_instramp_n_to_sio1 = bus_left_instramp_n_to_sio1; +assign left_instramp_n_to_right_vref = bus_left_instramp_n_to_right_vref; +assign left_instramp_n_to_vinref = bus_left_instramp_n_to_vinref; +assign left_instramp_p_to_gpio5_6 = bus_left_instramp_p_to_gpio5_6; +assign left_instramp_p_to_analog0 = bus_left_instramp_p_to_analog0; +assign left_instramp_p_to_amuxbusA = bus_left_instramp_p_to_amuxbusA; +assign left_instramp_p_to_sio0 = bus_left_instramp_p_to_sio0; +assign left_instramp_p_to_tempsense = bus_left_instramp_p_to_tempsense; +assign left_instramp_p_to_left_vref = bus_left_instramp_p_to_left_vref; +assign left_instramp_p_to_voutref = bus_left_instramp_p_to_voutref; +assign right_instramp_n_to_analog1 = bus_right_instramp_n_to_analog1; +assign right_instramp_n_to_amuxbusB = bus_right_instramp_n_to_amuxbusB; +assign right_instramp_n_to_sio1 = bus_right_instramp_n_to_sio1; +assign right_instramp_n_to_right_vref = bus_right_instramp_n_to_right_vref; +assign right_instramp_n_to_vinref = bus_right_instramp_n_to_vinref; +assign right_instramp_n_to_gpio2_6 = bus_right_instramp_n_to_gpio2_6; +assign right_instramp_p_to_analog0 = bus_right_instramp_p_to_analog0; +assign right_instramp_p_to_amuxbusA = bus_right_instramp_p_to_amuxbusA; +assign right_instramp_p_to_sio0 = bus_right_instramp_p_to_sio0; +assign right_instramp_p_to_tempsense = bus_right_instramp_p_to_tempsense; +assign right_instramp_p_to_left_vref = bus_right_instramp_p_to_left_vref; +assign right_instramp_p_to_voutref = bus_right_instramp_p_to_voutref; +assign right_instramp_p_to_gpio2_7 = bus_right_instramp_p_to_gpio2_7; +assign ulpcomp_p_to_dac0 = bus_ulpcomp_p_to_dac0; +assign ulpcomp_p_to_analog1 = bus_ulpcomp_p_to_analog1; +assign ulpcomp_p_to_sio0 = bus_ulpcomp_p_to_sio0; +assign ulpcomp_p_to_vbgtc = bus_ulpcomp_p_to_vbgtc; +assign ulpcomp_p_to_tempsense = bus_ulpcomp_p_to_tempsense; +assign ulpcomp_p_to_left_vref = bus_ulpcomp_p_to_left_vref; +assign ulpcomp_p_to_voutref = bus_ulpcomp_p_to_voutref; +assign ulpcomp_p_to_gpio6_0 = bus_ulpcomp_p_to_gpio6_0; +assign ulpcomp_p_to_gpio1_7 = bus_ulpcomp_p_to_gpio1_7; +assign ulpcomp_n_to_dac1 = bus_ulpcomp_n_to_dac1; +assign ulpcomp_n_to_analog0 = bus_ulpcomp_n_to_analog0; +assign ulpcomp_n_to_sio1 = bus_ulpcomp_n_to_sio1; +assign ulpcomp_n_to_vbgsc = bus_ulpcomp_n_to_vbgsc; +assign ulpcomp_n_to_right_vref = bus_ulpcomp_n_to_right_vref; +assign ulpcomp_n_to_vinref = bus_ulpcomp_n_to_vinref; +assign ulpcomp_n_to_gpio6_1 = bus_ulpcomp_n_to_gpio6_1; +assign ulpcomp_n_to_gpio1_6 = bus_ulpcomp_n_to_gpio1_6; +assign comp_p_to_dac0 = bus_comp_p_to_dac0; +assign comp_p_to_analog1 = bus_comp_p_to_analog1; +assign comp_p_to_sio0 = bus_comp_p_to_sio0; +assign comp_p_to_vbgtc = bus_comp_p_to_vbgtc; +assign comp_p_to_tempsense = bus_comp_p_to_tempsense; +assign comp_p_to_left_vref = bus_comp_p_to_left_vref; +assign comp_p_to_voutref = bus_comp_p_to_voutref; +assign comp_p_to_gpio6_2 = bus_comp_p_to_gpio6_2; +assign comp_p_to_gpio1_5 = bus_comp_p_to_gpio1_5; +assign comp_n_to_dac1 = bus_comp_n_to_dac1; +assign comp_n_to_analog0 = bus_comp_n_to_analog0; +assign comp_n_to_sio1 = bus_comp_n_to_sio1; +assign comp_n_to_vbgsc = bus_comp_n_to_vbgsc; +assign comp_n_to_right_vref = bus_comp_n_to_right_vref; +assign comp_n_to_vinref = bus_comp_n_to_vinref; +assign comp_n_to_gpio6_3 = bus_comp_n_to_gpio6_3; +assign comp_n_to_gpio1_4 = bus_comp_n_to_gpio1_4; +assign adc0_to_dac0 = bus_adc0_to_dac0; +assign adc0_to_analog1 = bus_adc0_to_analog1; +assign adc0_to_vbgtc = bus_adc0_to_vbgtc; +assign adc0_to_tempsense = bus_adc0_to_tempsense; +assign adc0_to_left_vref = bus_adc0_to_left_vref; +assign adc0_to_voutref = bus_adc0_to_voutref; +assign adc0_to_gpio6_4 = bus_adc0_to_gpio6_4; +assign adc0_to_gpio1_3 = bus_adc0_to_gpio1_3; +assign adc1_to_dac1 = bus_adc1_to_dac1; +assign adc1_to_analog0 = bus_adc1_to_analog0; +assign adc1_to_vbgsc = bus_adc1_to_vbgsc; +assign adc1_to_right_vref = bus_adc1_to_right_vref; +assign adc1_to_vinref = bus_adc1_to_vinref; +assign adc1_to_gpio6_5 = bus_adc1_to_gpio6_5; +assign adc1_to_gpio1_2 = bus_adc1_to_gpio1_2; +assign sio0_connect = bus_sio0_connect; +assign sio1_connect = bus_sio1_connect; +assign analog0_connect = bus_analog0_connect; +assign analog1_connect = bus_analog1_connect; +assign vbgtc_to_user = bus_vbgtc_to_user; +assign vbgsc_to_user = bus_vbgsc_to_user; +assign user_to_comp_n = bus_user_to_comp_n; +assign user_to_comp_p = bus_user_to_comp_p; +assign user_to_ulpcomp_n = bus_user_to_ulpcomp_n; +assign user_to_ulpcomp_p = bus_user_to_ulpcomp_p; +assign user_to_adc0 = bus_user_to_adc0; +assign user_to_adc1 = bus_user_to_adc1; +assign dac0_to_user = bus_dac0_to_user; +assign dac1_to_user = bus_dac1_to_user; +assign tempsense_to_user = bus_tempsense_to_user; +assign right_vref_to_user = bus_right_vref_to_user; +assign left_vref_to_user = bus_left_vref_to_user; +assign vinref_to_user = bus_vinref_to_user; +assign voutref_to_user = bus_voutref_to_user; +assign dac0_to_analog1 = bus_dac0_to_analog1; +assign dac1_to_analog0 = bus_dac1_to_analog0; +assign audiodac_out_to_analog1 = bus_audiodac_out_to_analog1; +assign audiodac_outb_to_analog0 = bus_audiodac_outb_to_analog0; + +assign left_instramp_ena = bus_left_instramp_ena; +assign left_instramp_G1 = bus_left_instramp_G1; +assign left_instramp_G2 = bus_left_instramp_G2; +assign left_hgbw_opamp_ena = bus_left_hgbw_opamp_ena; +assign left_lp_opamp_ena = bus_left_lp_opamp_ena; +assign left_rheostat1_b = bus_left_rheostat1_b; +assign left_rheostat2_b = bus_left_rheostat2_b; +assign right_instramp_ena = bus_right_instramp_ena; +assign right_instramp_G1 = bus_right_instramp_G1; +assign right_instramp_G2 = bus_right_instramp_G2; +assign right_hgbw_opamp_ena = bus_right_hgbw_opamp_ena; +assign right_lp_opamp_ena = bus_right_lp_opamp_ena; +assign right_rheostat1_b = bus_right_rheostat1_b; +assign right_rheostat2_b = bus_right_rheostat2_b; +assign comp_ena = bus_comp_ena; +assign comp_trim = bus_comp_trim; +assign comp_hyst = bus_comp_hyst; +assign ulpcomp_ena = bus_ulpcomp_ena; +assign ulpcomp_clk = bus_ulpcomp_clk; +assign bandgap_ena = bus_bandgap_ena; +assign bandgap_trim = bus_bandgap_trim; +assign bandgap_sel = bus_bandgap_sel; +assign ldo_ena = bus_ldo_ena; +assign overvoltage_ena = bus_overvoltage_ena; +assign overvoltage_trim = bus_overvoltage_trim; +assign ldo_ref_sel = bus_ldo_ref_sel; +assign ibias_ena = bus_ibias_ena; +assign ibias_src_ena = bus_ibias_src_ena; +assign ibias_snk_ena = bus_ibias_snk_ena; +assign ibias_ref_select = bus_ibias_ref_select; +assign idac_value = bus_idac_value; +assign idac_ena = bus_idac_ena; +assign tempsense_ena = bus_tempsense_ena; +assign tempsense_sel = bus_tempsense_sel; +assign rdac0_ena = bus_rdac0_ena; +assign rdac0_value = bus_rdac0_value; +assign rdac1_ena = bus_rdac1_ena; +assign rdac1_value = bus_rdac1_value; +assign brownout_ena = bus_brownout_ena; +assign brownout_vtrip = bus_brownout_vtrip; +assign brownout_otrip = bus_brownout_otrip; +assign brownout_isrc_sel = bus_brownout_isrc_sel; +assign brownout_oneshot = bus_brownout_oneshot; +assign brownout_rc_ena = bus_brownout_rc_ena; +assign brownout_rc_dis = bus_brownout_rc_dis; + +assign bus_brownout_vunder = brownout_vunder; +assign bus_brownout_timeout = brownout_timeout; +assign bus_brownout_filt = brownout_filt; +assign bus_brownout_unfilt = brownout_unfilt; + +assign bus_comp_out = comp_out; +assign bus_ulpcomp_out = ulpcomp_out; +assign bus_overvoltage_out = overvoltage_out; +assign bus_vdda1_pwr_good = vdda1_pwr_good; +assign bus_vccd1_pwr_good = vccd1_pwr_good; +assign bus_vdda2_pwr_good = vdda2_pwr_good; +assign bus_vccd2_pwr_good = vccd2_pwr_good; + +endmodule \ No newline at end of file diff --git a/regs_analog_ctrl_APB/regs_analog_ctrl_APB.v b/regs_analog_ctrl_APB/regs_analog_ctrl_APB.v new file mode 100644 index 0000000..6f83926 --- /dev/null +++ b/regs_analog_ctrl_APB/regs_analog_ctrl_APB.v @@ -0,0 +1,1816 @@ +/* + Copyright 2023 Efabless Corp. + + Author: Mohamed Shalan (mshalan@efabless.com) + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +*/ + +/* THIS FILE IS GENERATED, DO NOT EDIT */ + +`timescale 1ns/1ps +`default_nettype none + + +module regs_analog_ctrl_APB ( + input wire PCLK, + input wire PRESETn, + input wire PWRITE, + input wire [31:0] PWDATA, + input wire [31:0] PADDR, + input wire PENABLE, + input wire PSEL, + output wire PREADY, + output wire [31:0] PRDATA, + output wire IRQ +, + output wire [2-1:0] ibias_test_to_gpio1_2, + output wire [2-1:0] vbg_test_to_gpio1_1, + output wire [2-1:0] idac_to_gpio1_3, + output wire [2-1:0] idac_to_gpio1_2, + output wire [2-1:0] adc_refh_to_gpio6_6, + output wire [2-1:0] dac_refh_to_gpio1_1, + output wire [2-1:0] adc_refl_to_gpio6_7, + output wire [2-1:0] dac_refl_to_gpio1_0, + output wire [2-1:0] right_lp_opamp_to_ulpcomp_p, + output wire [2-1:0] right_lp_opamp_to_comp_p, + output wire [2-1:0] right_lp_opamp_to_adc0, + output wire [2-1:0] right_lp_opamp_to_gpio4_7, + output wire [2-1:0] right_lp_opamp_to_gpio4_3, + output wire [2-1:0] right_lp_opamp_to_analog1, + output wire [2-1:0] right_lp_opamp_to_amuxbusB, + output wire [2-1:0] right_lp_opamp_to_gpio3_7, + output wire [2-1:0] right_lp_opamp_to_gpio3_3, + output wire [2-1:0] right_hgbw_opamp_to_ulpcomp_n, + output wire [2-1:0] right_hgbw_opamp_to_comp_n, + output wire [2-1:0] right_hgbw_opamp_to_adc1, + output wire [2-1:0] right_hgbw_opamp_to_gpio4_6, + output wire [2-1:0] right_hgbw_opamp_to_gpio4_2, + output wire [2-1:0] right_hgbw_opamp_to_analog0, + output wire [2-1:0] right_hgbw_opamp_to_amuxbusA, + output wire [2-1:0] right_hgbw_opamp_to_gpio3_6, + output wire [2-1:0] right_hgbw_opamp_to_gpio3_2, + output wire [2-1:0] left_hgbw_opamp_to_ulpcomp_p, + output wire [2-1:0] left_hgbw_opamp_to_comp_p, + output wire [2-1:0] left_hgbw_opamp_to_adc0, + output wire [2-1:0] left_hgbw_opamp_to_gpio4_5, + output wire [2-1:0] left_hgbw_opamp_to_gpio4_1, + output wire [2-1:0] left_hgbw_opamp_to_analog1, + output wire [2-1:0] left_hgbw_opamp_to_amuxbusB, + output wire [2-1:0] left_hgbw_opamp_to_gpio3_5, + output wire [2-1:0] left_hgbw_opamp_to_gpio3_1, + output wire [2-1:0] left_lp_opamp_to_ulpcomp_n, + output wire [2-1:0] left_lp_opamp_to_comp_n, + output wire [2-1:0] left_lp_opamp_to_adc1, + output wire [2-1:0] left_lp_opamp_to_gpio4_0, + output wire [2-1:0] left_lp_opamp_to_analog0, + output wire [2-1:0] left_lp_opamp_to_amuxbusA, + output wire [2-1:0] left_lp_opamp_to_gpio3_4, + output wire [1-1:0] right_lp_opamp_p_to_dac0, + output wire [1-1:0] right_lp_opamp_p_to_analog0, + output wire [1-1:0] right_lp_opamp_p_to_amuxbusA, + output wire [1-1:0] right_lp_opamp_p_to_rheostat_out, + output wire [1-1:0] right_lp_opamp_p_to_sio0, + output wire [1-1:0] right_lp_opamp_p_to_tempsense, + output wire [1-1:0] right_lp_opamp_p_to_left_vref, + output wire [1-1:0] right_lp_opamp_p_to_voutref, + output wire [2-1:0] right_lp_opamp_p_to_gpio2_5, + output wire [1-1:0] right_lp_opamp_n_to_dac1, + output wire [1-1:0] right_lp_opamp_n_to_analog1, + output wire [1-1:0] right_lp_opamp_n_to_amuxbusB, + output wire [1-1:0] right_lp_opamp_n_to_rheostat_out, + output wire [1-1:0] right_lp_opamp_n_to_rheostat_tap, + output wire [1-1:0] right_lp_opamp_n_to_sio1, + output wire [1-1:0] right_lp_opamp_n_to_vbgtc, + output wire [1-1:0] right_lp_opamp_n_to_right_vref, + output wire [1-1:0] right_lp_opamp_n_to_vinref, + output wire [2-1:0] right_lp_opamp_n_to_gpio2_4, + output wire [2-1:0] right_hgbw_opamp_p_to_gpio5_0, + output wire [1-1:0] right_hgbw_opamp_p_to_dac0, + output wire [1-1:0] right_hgbw_opamp_p_to_analog0, + output wire [1-1:0] right_hgbw_opamp_p_to_amuxbusA, + output wire [1-1:0] right_hgbw_opamp_p_to_rheostat_out, + output wire [1-1:0] right_hgbw_opamp_p_to_sio0, + output wire [1-1:0] right_hgbw_opamp_p_to_left_vref, + output wire [1-1:0] right_hgbw_opamp_p_to_voutref, + output wire [2-1:0] right_hgbw_opamp_p_to_gpio2_3, + output wire [2-1:0] right_hgbw_opamp_n_to_gpio5_1, + output wire [1-1:0] right_hgbw_opamp_n_to_dac1, + output wire [1-1:0] right_hgbw_opamp_n_to_analog1, + output wire [1-1:0] right_hgbw_opamp_n_to_amuxbusB, + output wire [1-1:0] right_hgbw_opamp_n_to_rheostat_out, + output wire [1-1:0] right_hgbw_opamp_n_to_rheostat_tap, + output wire [1-1:0] right_hgbw_opamp_n_to_sio1, + output wire [1-1:0] right_hgbw_opamp_n_to_vbgsc, + output wire [1-1:0] right_hgbw_opamp_n_to_right_vref, + output wire [1-1:0] right_hgbw_opamp_n_to_vinref, + output wire [2-1:0] right_hgbw_opamp_n_to_gpio2_2, + output wire [2-1:0] left_hgbw_opamp_p_to_gpio5_2, + output wire [1-1:0] left_hgbw_opamp_p_to_dac0, + output wire [1-1:0] left_hgbw_opamp_p_to_analog0, + output wire [1-1:0] left_hgbw_opamp_p_to_amuxbusA, + output wire [1-1:0] left_hgbw_opamp_p_to_rheostat_out, + output wire [1-1:0] left_hgbw_opamp_p_to_sio0, + output wire [1-1:0] left_hgbw_opamp_p_to_tempsense, + output wire [1-1:0] left_hgbw_opamp_p_to_left_vref, + output wire [1-1:0] left_hgbw_opamp_p_to_voutref, + output wire [2-1:0] left_hgbw_opamp_p_to_gpio2_1, + output wire [2-1:0] left_hgbw_opamp_n_to_gpio5_3, + output wire [1-1:0] left_hgbw_opamp_n_to_dac1, + output wire [1-1:0] left_hgbw_opamp_n_to_analog1, + output wire [1-1:0] left_hgbw_opamp_n_to_amuxbusB, + output wire [1-1:0] left_hgbw_opamp_n_to_rheostat_out, + output wire [1-1:0] left_hgbw_opamp_n_to_rheostat_tap, + output wire [1-1:0] left_hgbw_opamp_n_to_sio1, + output wire [1-1:0] left_hgbw_opamp_n_to_vbgtc, + output wire [1-1:0] left_hgbw_opamp_n_to_right_vref, + output wire [1-1:0] left_hgbw_opamp_n_to_vinref, + output wire [2-1:0] left_hgbw_opamp_n_to_gpio2_0, + output wire [2-1:0] left_lp_opamp_p_to_gpio5_4, + output wire [1-1:0] left_lp_opamp_p_to_dac0, + output wire [1-1:0] left_lp_opamp_p_to_analog0, + output wire [1-1:0] left_lp_opamp_p_to_amuxbusA, + output wire [1-1:0] left_lp_opamp_p_to_rheostat_out, + output wire [1-1:0] left_lp_opamp_p_to_sio0, + output wire [1-1:0] left_lp_opamp_p_to_left_vref, + output wire [1-1:0] left_lp_opamp_p_to_voutref, + output wire [2-1:0] left_lp_opamp_n_to_gpio5_5, + output wire [1-1:0] left_lp_opamp_n_to_dac1, + output wire [1-1:0] left_lp_opamp_n_to_analog1, + output wire [1-1:0] left_lp_opamp_n_to_amuxbusB, + output wire [1-1:0] left_lp_opamp_n_to_rheostat_out, + output wire [1-1:0] left_lp_opamp_n_to_rheostat_tap, + output wire [1-1:0] left_lp_opamp_n_to_sio1, + output wire [1-1:0] left_lp_opamp_n_to_vbgsc, + output wire [1-1:0] left_lp_opamp_n_to_right_vref, + output wire [1-1:0] left_lp_opamp_n_to_vinref, + output wire [2-1:0] left_instramp_to_ulpcomp_p, + output wire [2-1:0] left_instramp_to_comp_p, + output wire [2-1:0] left_instramp_to_adc0, + output wire [2-1:0] left_instramp_to_gpio4_4, + output wire [2-1:0] left_instramp_to_analog1, + output wire [2-1:0] left_instramp_to_amuxbusB, + output wire [2-1:0] right_instramp_to_ulpcomp_n, + output wire [2-1:0] right_instramp_to_comp_n, + output wire [2-1:0] right_instramp_to_adc1, + output wire [2-1:0] right_instramp_to_analog0, + output wire [2-1:0] right_instramp_to_amuxbusA, + output wire [2-1:0] right_instramp_to_gpio3_0, + output wire [2-1:0] left_instramp_n_to_gpio5_7, + output wire [1-1:0] left_instramp_n_to_analog1, + output wire [1-1:0] left_instramp_n_to_amuxbusB, + output wire [1-1:0] left_instramp_n_to_sio1, + output wire [1-1:0] left_instramp_n_to_right_vref, + output wire [1-1:0] left_instramp_n_to_vinref, + output wire [2-1:0] left_instramp_p_to_gpio5_6, + output wire [1-1:0] left_instramp_p_to_analog0, + output wire [1-1:0] left_instramp_p_to_amuxbusA, + output wire [1-1:0] left_instramp_p_to_sio0, + output wire [1-1:0] left_instramp_p_to_tempsense, + output wire [1-1:0] left_instramp_p_to_left_vref, + output wire [1-1:0] left_instramp_p_to_voutref, + output wire [1-1:0] right_instramp_n_to_analog1, + output wire [1-1:0] right_instramp_n_to_amuxbusB, + output wire [1-1:0] right_instramp_n_to_sio1, + output wire [1-1:0] right_instramp_n_to_right_vref, + output wire [1-1:0] right_instramp_n_to_vinref, + output wire [2-1:0] right_instramp_n_to_gpio2_6, + output wire [1-1:0] right_instramp_p_to_analog0, + output wire [1-1:0] right_instramp_p_to_amuxbusA, + output wire [1-1:0] right_instramp_p_to_sio0, + output wire [1-1:0] right_instramp_p_to_tempsense, + output wire [1-1:0] right_instramp_p_to_left_vref, + output wire [1-1:0] right_instramp_p_to_voutref, + output wire [2-1:0] right_instramp_p_to_gpio2_7, + output wire [1-1:0] ulpcomp_p_to_dac0, + output wire [1-1:0] ulpcomp_p_to_analog1, + output wire [1-1:0] ulpcomp_p_to_sio0, + output wire [1-1:0] ulpcomp_p_to_vbgtc, + output wire [1-1:0] ulpcomp_p_to_tempsense, + output wire [1-1:0] ulpcomp_p_to_left_vref, + output wire [1-1:0] ulpcomp_p_to_voutref, + output wire [2-1:0] ulpcomp_p_to_gpio6_0, + output wire [2-1:0] ulpcomp_p_to_gpio1_7, + output wire [1-1:0] ulpcomp_n_to_dac1, + output wire [1-1:0] ulpcomp_n_to_analog0, + output wire [1-1:0] ulpcomp_n_to_sio1, + output wire [1-1:0] ulpcomp_n_to_vbgsc, + output wire [1-1:0] ulpcomp_n_to_right_vref, + output wire [1-1:0] ulpcomp_n_to_vinref, + output wire [2-1:0] ulpcomp_n_to_gpio6_1, + output wire [2-1:0] ulpcomp_n_to_gpio1_6, + output wire [1-1:0] comp_p_to_dac0, + output wire [1-1:0] comp_p_to_analog1, + output wire [1-1:0] comp_p_to_sio0, + output wire [1-1:0] comp_p_to_vbgtc, + output wire [1-1:0] comp_p_to_tempsense, + output wire [1-1:0] comp_p_to_left_vref, + output wire [1-1:0] comp_p_to_voutref, + output wire [2-1:0] comp_p_to_gpio6_2, + output wire [2-1:0] comp_p_to_gpio1_5, + output wire [1-1:0] comp_n_to_dac1, + output wire [1-1:0] comp_n_to_analog0, + output wire [1-1:0] comp_n_to_sio1, + output wire [1-1:0] comp_n_to_vbgsc, + output wire [1-1:0] comp_n_to_right_vref, + output wire [1-1:0] comp_n_to_vinref, + output wire [2-1:0] comp_n_to_gpio6_3, + output wire [2-1:0] comp_n_to_gpio1_4, + output wire [1-1:0] adc0_to_dac0, + output wire [1-1:0] adc0_to_analog1, + output wire [1-1:0] adc0_to_vbgtc, + output wire [1-1:0] adc0_to_tempsense, + output wire [1-1:0] adc0_to_left_vref, + output wire [1-1:0] adc0_to_voutref, + output wire [2-1:0] adc0_to_gpio6_4, + output wire [2-1:0] adc0_to_gpio1_3, + output wire [1-1:0] adc1_to_dac1, + output wire [1-1:0] adc1_to_analog0, + output wire [1-1:0] adc1_to_vbgsc, + output wire [1-1:0] adc1_to_right_vref, + output wire [1-1:0] adc1_to_vinref, + output wire [2-1:0] adc1_to_gpio6_5, + output wire [2-1:0] adc1_to_gpio1_2, + output wire [2-1:0] sio0_connect, + output wire [2-1:0] sio1_connect, + output wire [2-1:0] analog0_connect, + output wire [2-1:0] analog1_connect, + output wire [1-1:0] vbgtc_to_user, + output wire [1-1:0] vbgsc_to_user, + output wire [2-1:0] user_to_comp_n, + output wire [2-1:0] user_to_comp_p, + output wire [2-1:0] user_to_ulpcomp_n, + output wire [2-1:0] user_to_ulpcomp_p, + output wire [2-1:0] user_to_adc0, + output wire [2-1:0] user_to_adc1, + output wire [1-1:0] dac0_to_user, + output wire [1-1:0] dac1_to_user, + output wire [1-1:0] tempsense_to_user, + output wire [1-1:0] right_vref_to_user, + output wire [1-1:0] left_vref_to_user, + output wire [1-1:0] vinref_to_user, + output wire [1-1:0] voutref_to_user, + output wire [1-1:0] dac0_to_analog1, + output wire [1-1:0] dac1_to_analog0, + output wire [2-1:0] audiodac_out_to_analog1, + output wire [2-1:0] audiodac_outb_to_analog0, + output wire [1-1:0] left_instramp_ena, + output wire [5-1:0] left_instramp_G1, + output wire [5-1:0] left_instramp_G2, + output wire [1-1:0] left_hgbw_opamp_ena, + output wire [1-1:0] left_lp_opamp_ena, + output wire [8-1:0] left_rheostat1_b, + output wire [8-1:0] left_rheostat2_b, + output wire [1-1:0] right_instramp_ena, + output wire [5-1:0] right_instramp_G1, + output wire [5-1:0] right_instramp_G2, + output wire [1-1:0] right_hgbw_opamp_ena, + output wire [1-1:0] right_lp_opamp_ena, + output wire [8-1:0] right_rheostat1_b, + output wire [8-1:0] right_rheostat2_b, + output wire [1-1:0] comp_ena, + output wire [6-1:0] comp_trim, + output wire [2-1:0] comp_hyst, + output wire [1-1:0] ulpcomp_ena, + output wire [1-1:0] ulpcomp_clk, + output wire [1-1:0] bandgap_ena, + output wire [16-1:0] bandgap_trim, + output wire [1-1:0] bandgap_sel, + output wire [1-1:0] ldo_ena, + output wire [1-1:0] overvoltage_ena, + output wire [4-1:0] overvoltage_trim, + output wire [1-1:0] ldo_ref_sel, + output wire [1-1:0] ibias_ena, + output wire [24-1:0] ibias_src_ena, + output wire [4-1:0] ibias_snk_ena, + output wire [1-1:0] ibias_ref_select, + output wire [12-1:0] idac_value, + output wire [1-1:0] idac_ena, + output wire [1-1:0] tempsense_ena, + output wire [1-1:0] tempsense_sel, + output wire [1-1:0] rdac0_ena, + output wire [12-1:0] rdac0_value, + output wire [1-1:0] rdac1_ena, + output wire [12-1:0] rdac1_value, + output wire [1-1:0] brownout_ena, + output wire [3-1:0] brownout_vtrip, + output wire [3-1:0] brownout_otrip, + output wire [1-1:0] brownout_isrc_sel, + output wire [1-1:0] brownout_oneshot, + output wire [1-1:0] brownout_rc_ena, + output wire [1-1:0] brownout_rc_dis, + input wire [1-1:0] brownout_vunder, + input wire [1-1:0] brownout_timeout, + input wire [1-1:0] brownout_filt, + input wire [1-1:0] brownout_unfilt, + input wire [1-1:0] comp_out, + input wire [1-1:0] ulpcomp_out, + input wire [1-1:0] overvoltage_out, + input wire [1-1:0] vdda1_pwr_good, + input wire [1-1:0] vccd1_pwr_good, + input wire [1-1:0] vdda2_pwr_good, + input wire [1-1:0] vccd2_pwr_good +); + + localparam reg_ana_test_REG_OFFSET = 16'h0000; + localparam reg_ana_idac_REG_OFFSET = 16'h0004; + localparam reg_ana_ref_REG_OFFSET = 16'h0008; + localparam reg_ana_amp3_out_REG_OFFSET = 16'h000C; + localparam reg_ana_amp2_out_REG_OFFSET = 16'h0010; + localparam reg_ana_amp1_out_REG_OFFSET = 16'h0014; + localparam reg_ana_amp0_out_REG_OFFSET = 16'h0018; + localparam reg_ana_amp3_inp_REG_OFFSET = 16'h001C; + localparam reg_ana_amp3_inn_REG_OFFSET = 16'h0020; + localparam reg_ana_amp2_inp_REG_OFFSET = 16'h0024; + localparam reg_ana_amp2_inn_REG_OFFSET = 16'h0028; + localparam reg_ana_amp1_inp_REG_OFFSET = 16'h002C; + localparam reg_ana_amp1_inn_REG_OFFSET = 16'h0030; + localparam reg_ana_amp0_inp_REG_OFFSET = 16'h0034; + localparam reg_ana_amp0_inn_REG_OFFSET = 16'h0038; + localparam reg_ana_preamp0_out_REG_OFFSET = 16'h003C; + localparam reg_ana_preamp1_out_REG_OFFSET = 16'h0040; + localparam reg_ana_preamp0_inn_REG_OFFSET = 16'h0044; + localparam reg_ana_preamp0_inp_REG_OFFSET = 16'h0048; + localparam reg_ana_preamp1_inn_REG_OFFSET = 16'h004C; + localparam reg_ana_preamp1_inp_REG_OFFSET = 16'h0050; + localparam reg_ana_comp1_inp_REG_OFFSET = 16'h0054; + localparam reg_ana_comp1_inn_REG_OFFSET = 16'h0058; + localparam reg_ana_comp0_inp_REG_OFFSET = 16'h005C; + localparam reg_ana_comp0_inn_REG_OFFSET = 16'h0060; + localparam reg_ana_adc0_in_REG_OFFSET = 16'h0064; + localparam reg_ana_adc1_in_REG_OFFSET = 16'h0068; + localparam reg_ana_sio_iso_REG_OFFSET = 16'h006C; + localparam reg_ana_sio_ana_REG_OFFSET = 16'h0070; + localparam reg_ana_uproj_REG_OFFSET = 16'h0074; + localparam reg_ana_dac_out_REG_OFFSET = 16'h0078; + localparam reg_left_instramp_ctrl_REG_OFFSET = 16'h007C; + localparam reg_left_opamp_ctrl_REG_OFFSET = 16'h0080; + localparam reg_right_instramp_ctrl_REG_OFFSET = 16'h0084; + localparam reg_right_opamp_ctrl_REG_OFFSET = 16'h0088; + localparam reg_comparator_ctrl_REG_OFFSET = 16'h008C; + localparam reg_bandgap_ctrl_REG_OFFSET = 16'h0090; + localparam reg_ibias_ctrl_REG_OFFSET = 16'h0094; + localparam reg_idac_ctrl_REG_OFFSET = 16'h0098; + localparam reg_tempsense_ctrl_REG_OFFSET = 16'h009C; + localparam reg_rdac_ctrl_REG_OFFSET = 16'h00A0; + localparam reg_brownout_ctrl_REG_OFFSET = 16'h00A4; + localparam reg_brownout_output_REG_OFFSET = 16'h00A8; + localparam reg_comparator0_out_REG_OFFSET = 16'h00AC; + localparam reg_comparator1_out_REG_OFFSET = 16'h00B0; + localparam reg_overvoltage_out_REG_OFFSET = 16'h00B4; + localparam reg_vdda1_pwr_good_REG_OFFSET = 16'h00B8; + localparam reg_vccd1_pwr_good_REG_OFFSET = 16'h00BC; + localparam reg_vdda2_pwr_good_REG_OFFSET = 16'h00C0; + localparam reg_vccd2_pwr_good_REG_OFFSET = 16'h00C4; + wire clk = PCLK; + wire rst_n = PRESETn; + + + wire apb_valid = PSEL & PENABLE; + wire apb_we = PWRITE & apb_valid; + wire apb_re = ~PWRITE & apb_valid; + + wire [2-1:0] bus_ibias_test_to_gpio1_2; + wire [2-1:0] bus_vbg_test_to_gpio1_1; + wire [2-1:0] bus_idac_to_gpio1_3; + wire [2-1:0] bus_idac_to_gpio1_2; + wire [2-1:0] bus_adc_refh_to_gpio6_6; + wire [2-1:0] bus_dac_refh_to_gpio1_1; + wire [2-1:0] bus_adc_refl_to_gpio6_7; + wire [2-1:0] bus_dac_refl_to_gpio1_0; + wire [2-1:0] bus_right_lp_opamp_to_ulpcomp_p; + wire [2-1:0] bus_right_lp_opamp_to_comp_p; + wire [2-1:0] bus_right_lp_opamp_to_adc0; + wire [2-1:0] bus_right_lp_opamp_to_gpio4_7; + wire [2-1:0] bus_right_lp_opamp_to_gpio4_3; + wire [2-1:0] bus_right_lp_opamp_to_analog1; + wire [2-1:0] bus_right_lp_opamp_to_amuxbusB; + wire [2-1:0] bus_right_lp_opamp_to_gpio3_7; + wire [2-1:0] bus_right_lp_opamp_to_gpio3_3; + wire [2-1:0] bus_right_hgbw_opamp_to_ulpcomp_n; + wire [2-1:0] bus_right_hgbw_opamp_to_comp_n; + wire [2-1:0] bus_right_hgbw_opamp_to_adc1; + wire [2-1:0] bus_right_hgbw_opamp_to_gpio4_6; + wire [2-1:0] bus_right_hgbw_opamp_to_gpio4_2; + wire [2-1:0] bus_right_hgbw_opamp_to_analog0; + wire [2-1:0] bus_right_hgbw_opamp_to_amuxbusA; + wire [2-1:0] bus_right_hgbw_opamp_to_gpio3_6; + wire [2-1:0] bus_right_hgbw_opamp_to_gpio3_2; + wire [2-1:0] bus_left_hgbw_opamp_to_ulpcomp_p; + wire [2-1:0] bus_left_hgbw_opamp_to_comp_p; + wire [2-1:0] bus_left_hgbw_opamp_to_adc0; + wire [2-1:0] bus_left_hgbw_opamp_to_gpio4_5; + wire [2-1:0] bus_left_hgbw_opamp_to_gpio4_1; + wire [2-1:0] bus_left_hgbw_opamp_to_analog1; + wire [2-1:0] bus_left_hgbw_opamp_to_amuxbusB; + wire [2-1:0] bus_left_hgbw_opamp_to_gpio3_5; + wire [2-1:0] bus_left_hgbw_opamp_to_gpio3_1; + wire [2-1:0] bus_left_lp_opamp_to_ulpcomp_n; + wire [2-1:0] bus_left_lp_opamp_to_comp_n; + wire [2-1:0] bus_left_lp_opamp_to_adc1; + wire [2-1:0] bus_left_lp_opamp_to_gpio4_0; + wire [2-1:0] bus_left_lp_opamp_to_analog0; + wire [2-1:0] bus_left_lp_opamp_to_amuxbusA; + wire [2-1:0] bus_left_lp_opamp_to_gpio3_4; + wire [1-1:0] bus_right_lp_opamp_p_to_dac0; + wire [1-1:0] bus_right_lp_opamp_p_to_analog0; + wire [1-1:0] bus_right_lp_opamp_p_to_amuxbusA; + wire [1-1:0] bus_right_lp_opamp_p_to_rheostat_out; + wire [1-1:0] bus_right_lp_opamp_p_to_sio0; + wire [1-1:0] bus_right_lp_opamp_p_to_tempsense; + wire [1-1:0] bus_right_lp_opamp_p_to_left_vref; + wire [1-1:0] bus_right_lp_opamp_p_to_voutref; + wire [2-1:0] bus_right_lp_opamp_p_to_gpio2_5; + wire [1-1:0] bus_right_lp_opamp_n_to_dac1; + wire [1-1:0] bus_right_lp_opamp_n_to_analog1; + wire [1-1:0] bus_right_lp_opamp_n_to_amuxbusB; + wire [1-1:0] bus_right_lp_opamp_n_to_rheostat_out; + wire [1-1:0] bus_right_lp_opamp_n_to_rheostat_tap; + wire [1-1:0] bus_right_lp_opamp_n_to_sio1; + wire [1-1:0] bus_right_lp_opamp_n_to_vbgtc; + wire [1-1:0] bus_right_lp_opamp_n_to_right_vref; + wire [1-1:0] bus_right_lp_opamp_n_to_vinref; + wire [2-1:0] bus_right_lp_opamp_n_to_gpio2_4; + wire [2-1:0] bus_right_hgbw_opamp_p_to_gpio5_0; + wire [1-1:0] bus_right_hgbw_opamp_p_to_dac0; + wire [1-1:0] bus_right_hgbw_opamp_p_to_analog0; + wire [1-1:0] bus_right_hgbw_opamp_p_to_amuxbusA; + wire [1-1:0] bus_right_hgbw_opamp_p_to_rheostat_out; + wire [1-1:0] bus_right_hgbw_opamp_p_to_sio0; + wire [1-1:0] bus_right_hgbw_opamp_p_to_left_vref; + wire [1-1:0] bus_right_hgbw_opamp_p_to_voutref; + wire [2-1:0] bus_right_hgbw_opamp_p_to_gpio2_3; + wire [2-1:0] bus_right_hgbw_opamp_n_to_gpio5_1; + wire [1-1:0] bus_right_hgbw_opamp_n_to_dac1; + wire [1-1:0] bus_right_hgbw_opamp_n_to_analog1; + wire [1-1:0] bus_right_hgbw_opamp_n_to_amuxbusB; + wire [1-1:0] bus_right_hgbw_opamp_n_to_rheostat_out; + wire [1-1:0] bus_right_hgbw_opamp_n_to_rheostat_tap; + wire [1-1:0] bus_right_hgbw_opamp_n_to_sio1; + wire [1-1:0] bus_right_hgbw_opamp_n_to_vbgsc; + wire [1-1:0] bus_right_hgbw_opamp_n_to_right_vref; + wire [1-1:0] bus_right_hgbw_opamp_n_to_vinref; + wire [2-1:0] bus_right_hgbw_opamp_n_to_gpio2_2; + wire [2-1:0] bus_left_hgbw_opamp_p_to_gpio5_2; + wire [1-1:0] bus_left_hgbw_opamp_p_to_dac0; + wire [1-1:0] bus_left_hgbw_opamp_p_to_analog0; + wire [1-1:0] bus_left_hgbw_opamp_p_to_amuxbusA; + wire [1-1:0] bus_left_hgbw_opamp_p_to_rheostat_out; + wire [1-1:0] bus_left_hgbw_opamp_p_to_sio0; + wire [1-1:0] bus_left_hgbw_opamp_p_to_tempsense; + wire [1-1:0] bus_left_hgbw_opamp_p_to_left_vref; + wire [1-1:0] bus_left_hgbw_opamp_p_to_voutref; + wire [2-1:0] bus_left_hgbw_opamp_p_to_gpio2_1; + wire [2-1:0] bus_left_hgbw_opamp_n_to_gpio5_3; + wire [1-1:0] bus_left_hgbw_opamp_n_to_dac1; + wire [1-1:0] bus_left_hgbw_opamp_n_to_analog1; + wire [1-1:0] bus_left_hgbw_opamp_n_to_amuxbusB; + wire [1-1:0] bus_left_hgbw_opamp_n_to_rheostat_out; + wire [1-1:0] bus_left_hgbw_opamp_n_to_rheostat_tap; + wire [1-1:0] bus_left_hgbw_opamp_n_to_sio1; + wire [1-1:0] bus_left_hgbw_opamp_n_to_vbgtc; + wire [1-1:0] bus_left_hgbw_opamp_n_to_right_vref; + wire [1-1:0] bus_left_hgbw_opamp_n_to_vinref; + wire [2-1:0] bus_left_hgbw_opamp_n_to_gpio2_0; + wire [2-1:0] bus_left_lp_opamp_p_to_gpio5_4; + wire [1-1:0] bus_left_lp_opamp_p_to_dac0; + wire [1-1:0] bus_left_lp_opamp_p_to_analog0; + wire [1-1:0] bus_left_lp_opamp_p_to_amuxbusA; + wire [1-1:0] bus_left_lp_opamp_p_to_rheostat_out; + wire [1-1:0] bus_left_lp_opamp_p_to_sio0; + wire [1-1:0] bus_left_lp_opamp_p_to_left_vref; + wire [1-1:0] bus_left_lp_opamp_p_to_voutref; + wire [2-1:0] bus_left_lp_opamp_n_to_gpio5_5; + wire [1-1:0] bus_left_lp_opamp_n_to_dac1; + wire [1-1:0] bus_left_lp_opamp_n_to_analog1; + wire [1-1:0] bus_left_lp_opamp_n_to_amuxbusB; + wire [1-1:0] bus_left_lp_opamp_n_to_rheostat_out; + wire [1-1:0] bus_left_lp_opamp_n_to_rheostat_tap; + wire [1-1:0] bus_left_lp_opamp_n_to_sio1; + wire [1-1:0] bus_left_lp_opamp_n_to_vbgsc; + wire [1-1:0] bus_left_lp_opamp_n_to_right_vref; + wire [1-1:0] bus_left_lp_opamp_n_to_vinref; + wire [2-1:0] bus_left_instramp_to_ulpcomp_p; + wire [2-1:0] bus_left_instramp_to_comp_p; + wire [2-1:0] bus_left_instramp_to_adc0; + wire [2-1:0] bus_left_instramp_to_gpio4_4; + wire [2-1:0] bus_left_instramp_to_analog1; + wire [2-1:0] bus_left_instramp_to_amuxbusB; + wire [2-1:0] bus_right_instramp_to_ulpcomp_n; + wire [2-1:0] bus_right_instramp_to_comp_n; + wire [2-1:0] bus_right_instramp_to_adc1; + wire [2-1:0] bus_right_instramp_to_analog0; + wire [2-1:0] bus_right_instramp_to_amuxbusA; + wire [2-1:0] bus_right_instramp_to_gpio3_0; + wire [2-1:0] bus_left_instramp_n_to_gpio5_7; + wire [1-1:0] bus_left_instramp_n_to_analog1; + wire [1-1:0] bus_left_instramp_n_to_amuxbusB; + wire [1-1:0] bus_left_instramp_n_to_sio1; + wire [1-1:0] bus_left_instramp_n_to_right_vref; + wire [1-1:0] bus_left_instramp_n_to_vinref; + wire [2-1:0] bus_left_instramp_p_to_gpio5_6; + wire [1-1:0] bus_left_instramp_p_to_analog0; + wire [1-1:0] bus_left_instramp_p_to_amuxbusA; + wire [1-1:0] bus_left_instramp_p_to_sio0; + wire [1-1:0] bus_left_instramp_p_to_tempsense; + wire [1-1:0] bus_left_instramp_p_to_left_vref; + wire [1-1:0] bus_left_instramp_p_to_voutref; + wire [1-1:0] bus_right_instramp_n_to_analog1; + wire [1-1:0] bus_right_instramp_n_to_amuxbusB; + wire [1-1:0] bus_right_instramp_n_to_sio1; + wire [1-1:0] bus_right_instramp_n_to_right_vref; + wire [1-1:0] bus_right_instramp_n_to_vinref; + wire [2-1:0] bus_right_instramp_n_to_gpio2_6; + wire [1-1:0] bus_right_instramp_p_to_analog0; + wire [1-1:0] bus_right_instramp_p_to_amuxbusA; + wire [1-1:0] bus_right_instramp_p_to_sio0; + wire [1-1:0] bus_right_instramp_p_to_tempsense; + wire [1-1:0] bus_right_instramp_p_to_left_vref; + wire [1-1:0] bus_right_instramp_p_to_voutref; + wire [2-1:0] bus_right_instramp_p_to_gpio2_7; + wire [1-1:0] bus_ulpcomp_p_to_dac0; + wire [1-1:0] bus_ulpcomp_p_to_analog1; + wire [1-1:0] bus_ulpcomp_p_to_sio0; + wire [1-1:0] bus_ulpcomp_p_to_vbgtc; + wire [1-1:0] bus_ulpcomp_p_to_tempsense; + wire [1-1:0] bus_ulpcomp_p_to_left_vref; + wire [1-1:0] bus_ulpcomp_p_to_voutref; + wire [2-1:0] bus_ulpcomp_p_to_gpio6_0; + wire [2-1:0] bus_ulpcomp_p_to_gpio1_7; + wire [1-1:0] bus_ulpcomp_n_to_dac1; + wire [1-1:0] bus_ulpcomp_n_to_analog0; + wire [1-1:0] bus_ulpcomp_n_to_sio1; + wire [1-1:0] bus_ulpcomp_n_to_vbgsc; + wire [1-1:0] bus_ulpcomp_n_to_right_vref; + wire [1-1:0] bus_ulpcomp_n_to_vinref; + wire [2-1:0] bus_ulpcomp_n_to_gpio6_1; + wire [2-1:0] bus_ulpcomp_n_to_gpio1_6; + wire [1-1:0] bus_comp_p_to_dac0; + wire [1-1:0] bus_comp_p_to_analog1; + wire [1-1:0] bus_comp_p_to_sio0; + wire [1-1:0] bus_comp_p_to_vbgtc; + wire [1-1:0] bus_comp_p_to_tempsense; + wire [1-1:0] bus_comp_p_to_left_vref; + wire [1-1:0] bus_comp_p_to_voutref; + wire [2-1:0] bus_comp_p_to_gpio6_2; + wire [2-1:0] bus_comp_p_to_gpio1_5; + wire [1-1:0] bus_comp_n_to_dac1; + wire [1-1:0] bus_comp_n_to_analog0; + wire [1-1:0] bus_comp_n_to_sio1; + wire [1-1:0] bus_comp_n_to_vbgsc; + wire [1-1:0] bus_comp_n_to_right_vref; + wire [1-1:0] bus_comp_n_to_vinref; + wire [2-1:0] bus_comp_n_to_gpio6_3; + wire [2-1:0] bus_comp_n_to_gpio1_4; + wire [1-1:0] bus_adc0_to_dac0; + wire [1-1:0] bus_adc0_to_analog1; + wire [1-1:0] bus_adc0_to_vbgtc; + wire [1-1:0] bus_adc0_to_tempsense; + wire [1-1:0] bus_adc0_to_left_vref; + wire [1-1:0] bus_adc0_to_voutref; + wire [2-1:0] bus_adc0_to_gpio6_4; + wire [2-1:0] bus_adc0_to_gpio1_3; + wire [1-1:0] bus_adc1_to_dac1; + wire [1-1:0] bus_adc1_to_analog0; + wire [1-1:0] bus_adc1_to_vbgsc; + wire [1-1:0] bus_adc1_to_right_vref; + wire [1-1:0] bus_adc1_to_vinref; + wire [2-1:0] bus_adc1_to_gpio6_5; + wire [2-1:0] bus_adc1_to_gpio1_2; + wire [2-1:0] bus_sio0_connect; + wire [2-1:0] bus_sio1_connect; + wire [2-1:0] bus_analog0_connect; + wire [2-1:0] bus_analog1_connect; + wire [1-1:0] bus_vbgtc_to_user; + wire [1-1:0] bus_vbgsc_to_user; + wire [2-1:0] bus_user_to_comp_n; + wire [2-1:0] bus_user_to_comp_p; + wire [2-1:0] bus_user_to_ulpcomp_n; + wire [2-1:0] bus_user_to_ulpcomp_p; + wire [2-1:0] bus_user_to_adc0; + wire [2-1:0] bus_user_to_adc1; + wire [1-1:0] bus_dac0_to_user; + wire [1-1:0] bus_dac1_to_user; + wire [1-1:0] bus_tempsense_to_user; + wire [1-1:0] bus_right_vref_to_user; + wire [1-1:0] bus_left_vref_to_user; + wire [1-1:0] bus_vinref_to_user; + wire [1-1:0] bus_voutref_to_user; + wire [1-1:0] bus_dac0_to_analog1; + wire [1-1:0] bus_dac1_to_analog0; + wire [2-1:0] bus_audiodac_out_to_analog1; + wire [2-1:0] bus_audiodac_outb_to_analog0; + wire [1-1:0] bus_left_instramp_ena; + wire [5-1:0] bus_left_instramp_G1; + wire [5-1:0] bus_left_instramp_G2; + wire [1-1:0] bus_left_hgbw_opamp_ena; + wire [1-1:0] bus_left_lp_opamp_ena; + wire [8-1:0] bus_left_rheostat1_b; + wire [8-1:0] bus_left_rheostat2_b; + wire [1-1:0] bus_right_instramp_ena; + wire [5-1:0] bus_right_instramp_G1; + wire [5-1:0] bus_right_instramp_G2; + wire [1-1:0] bus_right_hgbw_opamp_ena; + wire [1-1:0] bus_right_lp_opamp_ena; + wire [8-1:0] bus_right_rheostat1_b; + wire [8-1:0] bus_right_rheostat2_b; + wire [1-1:0] bus_comp_ena; + wire [6-1:0] bus_comp_trim; + wire [2-1:0] bus_comp_hyst; + wire [1-1:0] bus_ulpcomp_ena; + wire [1-1:0] bus_ulpcomp_clk; + wire [1-1:0] bus_bandgap_ena; + wire [16-1:0] bus_bandgap_trim; + wire [1-1:0] bus_bandgap_sel; + wire [1-1:0] bus_ldo_ena; + wire [1-1:0] bus_overvoltage_ena; + wire [4-1:0] bus_overvoltage_trim; + wire [1-1:0] bus_ldo_ref_sel; + wire [1-1:0] bus_ibias_ena; + wire [24-1:0] bus_ibias_src_ena; + wire [4-1:0] bus_ibias_snk_ena; + wire [1-1:0] bus_ibias_ref_select; + wire [12-1:0] bus_idac_value; + wire [1-1:0] bus_idac_ena; + wire [1-1:0] bus_tempsense_ena; + wire [1-1:0] bus_tempsense_sel; + wire [1-1:0] bus_rdac0_ena; + wire [12-1:0] bus_rdac0_value; + wire [1-1:0] bus_rdac1_ena; + wire [12-1:0] bus_rdac1_value; + wire [1-1:0] bus_brownout_ena; + wire [3-1:0] bus_brownout_vtrip; + wire [3-1:0] bus_brownout_otrip; + wire [1-1:0] bus_brownout_isrc_sel; + wire [1-1:0] bus_brownout_oneshot; + wire [1-1:0] bus_brownout_rc_ena; + wire [1-1:0] bus_brownout_rc_dis; + wire [1-1:0] bus_brownout_vunder; + wire [1-1:0] bus_brownout_timeout; + wire [1-1:0] bus_brownout_filt; + wire [1-1:0] bus_brownout_unfilt; + wire [1-1:0] bus_comp_out; + wire [1-1:0] bus_ulpcomp_out; + wire [1-1:0] bus_overvoltage_out; + wire [1-1:0] bus_vdda1_pwr_good; + wire [1-1:0] bus_vccd1_pwr_good; + wire [1-1:0] bus_vdda2_pwr_good; + wire [1-1:0] bus_vccd2_pwr_good; + + // Register Definitions + reg [3:0] reg_ana_test_REG; + assign bus_ibias_test_to_gpio1_2 = reg_ana_test_REG[1 : 0]; + assign bus_vbg_test_to_gpio1_1 = reg_ana_test_REG[3 : 2]; + always @(posedge PCLK or negedge PRESETn) if(~PRESETn) reg_ana_test_REG <= 0; + else if(apb_we & (PADDR[16-1:0]==reg_ana_test_REG_OFFSET)) + reg_ana_test_REG <= PWDATA[4-1:0]; + + reg [3:0] reg_ana_idac_REG; + assign bus_idac_to_gpio1_3 = reg_ana_idac_REG[1 : 0]; + assign bus_idac_to_gpio1_2 = reg_ana_idac_REG[3 : 2]; + always @(posedge PCLK or negedge PRESETn) if(~PRESETn) reg_ana_idac_REG <= 0; + else if(apb_we & (PADDR[16-1:0]==reg_ana_idac_REG_OFFSET)) + reg_ana_idac_REG <= PWDATA[4-1:0]; + + reg [7:0] reg_ana_ref_REG; + assign bus_adc_refh_to_gpio6_6 = reg_ana_ref_REG[1 : 0]; + assign bus_dac_refh_to_gpio1_1 = reg_ana_ref_REG[3 : 2]; + assign bus_adc_refl_to_gpio6_7 = reg_ana_ref_REG[5 : 4]; + assign bus_dac_refl_to_gpio1_0 = reg_ana_ref_REG[7 : 6]; + always @(posedge PCLK or negedge PRESETn) if(~PRESETn) reg_ana_ref_REG <= 0; + else if(apb_we & (PADDR[16-1:0]==reg_ana_ref_REG_OFFSET)) + reg_ana_ref_REG <= PWDATA[8-1:0]; + + reg [17:0] reg_ana_amp3_out_REG; + assign bus_right_lp_opamp_to_ulpcomp_p = reg_ana_amp3_out_REG[1 : 0]; + assign bus_right_lp_opamp_to_comp_p = reg_ana_amp3_out_REG[3 : 2]; + assign bus_right_lp_opamp_to_adc0 = reg_ana_amp3_out_REG[5 : 4]; + assign bus_right_lp_opamp_to_gpio4_7 = reg_ana_amp3_out_REG[7 : 6]; + assign bus_right_lp_opamp_to_gpio4_3 = reg_ana_amp3_out_REG[9 : 8]; + assign bus_right_lp_opamp_to_analog1 = reg_ana_amp3_out_REG[11 : 10]; + assign bus_right_lp_opamp_to_amuxbusB = reg_ana_amp3_out_REG[13 : 12]; + assign bus_right_lp_opamp_to_gpio3_7 = reg_ana_amp3_out_REG[15 : 14]; + assign bus_right_lp_opamp_to_gpio3_3 = reg_ana_amp3_out_REG[17 : 16]; + always @(posedge PCLK or negedge PRESETn) if(~PRESETn) reg_ana_amp3_out_REG <= 0; + else if(apb_we & (PADDR[16-1:0]==reg_ana_amp3_out_REG_OFFSET)) + reg_ana_amp3_out_REG <= PWDATA[18-1:0]; + + reg [17:0] reg_ana_amp2_out_REG; + assign bus_right_hgbw_opamp_to_ulpcomp_n = reg_ana_amp2_out_REG[1 : 0]; + assign bus_right_hgbw_opamp_to_comp_n = reg_ana_amp2_out_REG[3 : 2]; + assign bus_right_hgbw_opamp_to_adc1 = reg_ana_amp2_out_REG[5 : 4]; + assign bus_right_hgbw_opamp_to_gpio4_6 = reg_ana_amp2_out_REG[7 : 6]; + assign bus_right_hgbw_opamp_to_gpio4_2 = reg_ana_amp2_out_REG[9 : 8]; + assign bus_right_hgbw_opamp_to_analog0 = reg_ana_amp2_out_REG[11 : 10]; + assign bus_right_hgbw_opamp_to_amuxbusA = reg_ana_amp2_out_REG[13 : 12]; + assign bus_right_hgbw_opamp_to_gpio3_6 = reg_ana_amp2_out_REG[15 : 14]; + assign bus_right_hgbw_opamp_to_gpio3_2 = reg_ana_amp2_out_REG[17 : 16]; + always @(posedge PCLK or negedge PRESETn) if(~PRESETn) reg_ana_amp2_out_REG <= 0; + else if(apb_we & (PADDR[16-1:0]==reg_ana_amp2_out_REG_OFFSET)) + reg_ana_amp2_out_REG <= PWDATA[18-1:0]; + + reg [17:0] reg_ana_amp1_out_REG; + assign bus_left_hgbw_opamp_to_ulpcomp_p = reg_ana_amp1_out_REG[1 : 0]; + assign bus_left_hgbw_opamp_to_comp_p = reg_ana_amp1_out_REG[3 : 2]; + assign bus_left_hgbw_opamp_to_adc0 = reg_ana_amp1_out_REG[5 : 4]; + assign bus_left_hgbw_opamp_to_gpio4_5 = reg_ana_amp1_out_REG[7 : 6]; + assign bus_left_hgbw_opamp_to_gpio4_1 = reg_ana_amp1_out_REG[9 : 8]; + assign bus_left_hgbw_opamp_to_analog1 = reg_ana_amp1_out_REG[11 : 10]; + assign bus_left_hgbw_opamp_to_amuxbusB = reg_ana_amp1_out_REG[13 : 12]; + assign bus_left_hgbw_opamp_to_gpio3_5 = reg_ana_amp1_out_REG[15 : 14]; + assign bus_left_hgbw_opamp_to_gpio3_1 = reg_ana_amp1_out_REG[17 : 16]; + always @(posedge PCLK or negedge PRESETn) if(~PRESETn) reg_ana_amp1_out_REG <= 0; + else if(apb_we & (PADDR[16-1:0]==reg_ana_amp1_out_REG_OFFSET)) + reg_ana_amp1_out_REG <= PWDATA[18-1:0]; + + reg [13:0] reg_ana_amp0_out_REG; + assign bus_left_lp_opamp_to_ulpcomp_n = reg_ana_amp0_out_REG[1 : 0]; + assign bus_left_lp_opamp_to_comp_n = reg_ana_amp0_out_REG[3 : 2]; + assign bus_left_lp_opamp_to_adc1 = reg_ana_amp0_out_REG[5 : 4]; + assign bus_left_lp_opamp_to_gpio4_0 = reg_ana_amp0_out_REG[7 : 6]; + assign bus_left_lp_opamp_to_analog0 = reg_ana_amp0_out_REG[9 : 8]; + assign bus_left_lp_opamp_to_amuxbusA = reg_ana_amp0_out_REG[11 : 10]; + assign bus_left_lp_opamp_to_gpio3_4 = reg_ana_amp0_out_REG[13 : 12]; + always @(posedge PCLK or negedge PRESETn) if(~PRESETn) reg_ana_amp0_out_REG <= 0; + else if(apb_we & (PADDR[16-1:0]==reg_ana_amp0_out_REG_OFFSET)) + reg_ana_amp0_out_REG <= PWDATA[14-1:0]; + + reg [9:0] reg_ana_amp3_inp_REG; + assign bus_right_lp_opamp_p_to_dac0 = reg_ana_amp3_inp_REG[0 : 0]; + assign bus_right_lp_opamp_p_to_analog0 = reg_ana_amp3_inp_REG[1 : 1]; + assign bus_right_lp_opamp_p_to_amuxbusA = reg_ana_amp3_inp_REG[2 : 2]; + assign bus_right_lp_opamp_p_to_rheostat_out = reg_ana_amp3_inp_REG[3 : 3]; + assign bus_right_lp_opamp_p_to_sio0 = reg_ana_amp3_inp_REG[4 : 4]; + assign bus_right_lp_opamp_p_to_tempsense = reg_ana_amp3_inp_REG[5 : 5]; + assign bus_right_lp_opamp_p_to_left_vref = reg_ana_amp3_inp_REG[6 : 6]; + assign bus_right_lp_opamp_p_to_voutref = reg_ana_amp3_inp_REG[7 : 7]; + assign bus_right_lp_opamp_p_to_gpio2_5 = reg_ana_amp3_inp_REG[9 : 8]; + always @(posedge PCLK or negedge PRESETn) if(~PRESETn) reg_ana_amp3_inp_REG <= 0; + else if(apb_we & (PADDR[16-1:0]==reg_ana_amp3_inp_REG_OFFSET)) + reg_ana_amp3_inp_REG <= PWDATA[10-1:0]; + + reg [10:0] reg_ana_amp3_inn_REG; + assign bus_right_lp_opamp_n_to_dac1 = reg_ana_amp3_inn_REG[0 : 0]; + assign bus_right_lp_opamp_n_to_analog1 = reg_ana_amp3_inn_REG[1 : 1]; + assign bus_right_lp_opamp_n_to_amuxbusB = reg_ana_amp3_inn_REG[2 : 2]; + assign bus_right_lp_opamp_n_to_rheostat_out = reg_ana_amp3_inn_REG[3 : 3]; + assign bus_right_lp_opamp_n_to_rheostat_tap = reg_ana_amp3_inn_REG[4 : 4]; + assign bus_right_lp_opamp_n_to_sio1 = reg_ana_amp3_inn_REG[5 : 5]; + assign bus_right_lp_opamp_n_to_vbgtc = reg_ana_amp3_inn_REG[6 : 6]; + assign bus_right_lp_opamp_n_to_right_vref = reg_ana_amp3_inn_REG[7 : 7]; + assign bus_right_lp_opamp_n_to_vinref = reg_ana_amp3_inn_REG[8 : 8]; + assign bus_right_lp_opamp_n_to_gpio2_4 = reg_ana_amp3_inn_REG[10 : 9]; + always @(posedge PCLK or negedge PRESETn) if(~PRESETn) reg_ana_amp3_inn_REG <= 0; + else if(apb_we & (PADDR[16-1:0]==reg_ana_amp3_inn_REG_OFFSET)) + reg_ana_amp3_inn_REG <= PWDATA[11-1:0]; + + reg [10:0] reg_ana_amp2_inp_REG; + assign bus_right_hgbw_opamp_p_to_gpio5_0 = reg_ana_amp2_inp_REG[1 : 0]; + assign bus_right_hgbw_opamp_p_to_dac0 = reg_ana_amp2_inp_REG[2 : 2]; + assign bus_right_hgbw_opamp_p_to_analog0 = reg_ana_amp2_inp_REG[3 : 3]; + assign bus_right_hgbw_opamp_p_to_amuxbusA = reg_ana_amp2_inp_REG[4 : 4]; + assign bus_right_hgbw_opamp_p_to_rheostat_out = reg_ana_amp2_inp_REG[5 : 5]; + assign bus_right_hgbw_opamp_p_to_sio0 = reg_ana_amp2_inp_REG[6 : 6]; + assign bus_right_hgbw_opamp_p_to_left_vref = reg_ana_amp2_inp_REG[7 : 7]; + assign bus_right_hgbw_opamp_p_to_voutref = reg_ana_amp2_inp_REG[8 : 8]; + assign bus_right_hgbw_opamp_p_to_gpio2_3 = reg_ana_amp2_inp_REG[10 : 9]; + always @(posedge PCLK or negedge PRESETn) if(~PRESETn) reg_ana_amp2_inp_REG <= 0; + else if(apb_we & (PADDR[16-1:0]==reg_ana_amp2_inp_REG_OFFSET)) + reg_ana_amp2_inp_REG <= PWDATA[11-1:0]; + + reg [12:0] reg_ana_amp2_inn_REG; + assign bus_right_hgbw_opamp_n_to_gpio5_1 = reg_ana_amp2_inn_REG[1 : 0]; + assign bus_right_hgbw_opamp_n_to_dac1 = reg_ana_amp2_inn_REG[2 : 2]; + assign bus_right_hgbw_opamp_n_to_analog1 = reg_ana_amp2_inn_REG[3 : 3]; + assign bus_right_hgbw_opamp_n_to_amuxbusB = reg_ana_amp2_inn_REG[4 : 4]; + assign bus_right_hgbw_opamp_n_to_rheostat_out = reg_ana_amp2_inn_REG[5 : 5]; + assign bus_right_hgbw_opamp_n_to_rheostat_tap = reg_ana_amp2_inn_REG[6 : 6]; + assign bus_right_hgbw_opamp_n_to_sio1 = reg_ana_amp2_inn_REG[7 : 7]; + assign bus_right_hgbw_opamp_n_to_vbgsc = reg_ana_amp2_inn_REG[8 : 8]; + assign bus_right_hgbw_opamp_n_to_right_vref = reg_ana_amp2_inn_REG[9 : 9]; + assign bus_right_hgbw_opamp_n_to_vinref = reg_ana_amp2_inn_REG[10 : 10]; + assign bus_right_hgbw_opamp_n_to_gpio2_2 = reg_ana_amp2_inn_REG[12 : 11]; + always @(posedge PCLK or negedge PRESETn) if(~PRESETn) reg_ana_amp2_inn_REG <= 0; + else if(apb_we & (PADDR[16-1:0]==reg_ana_amp2_inn_REG_OFFSET)) + reg_ana_amp2_inn_REG <= PWDATA[13-1:0]; + + reg [11:0] reg_ana_amp1_inp_REG; + assign bus_left_hgbw_opamp_p_to_gpio5_2 = reg_ana_amp1_inp_REG[1 : 0]; + assign bus_left_hgbw_opamp_p_to_dac0 = reg_ana_amp1_inp_REG[2 : 2]; + assign bus_left_hgbw_opamp_p_to_analog0 = reg_ana_amp1_inp_REG[3 : 3]; + assign bus_left_hgbw_opamp_p_to_amuxbusA = reg_ana_amp1_inp_REG[4 : 4]; + assign bus_left_hgbw_opamp_p_to_rheostat_out = reg_ana_amp1_inp_REG[5 : 5]; + assign bus_left_hgbw_opamp_p_to_sio0 = reg_ana_amp1_inp_REG[6 : 6]; + assign bus_left_hgbw_opamp_p_to_tempsense = reg_ana_amp1_inp_REG[7 : 7]; + assign bus_left_hgbw_opamp_p_to_left_vref = reg_ana_amp1_inp_REG[8 : 8]; + assign bus_left_hgbw_opamp_p_to_voutref = reg_ana_amp1_inp_REG[9 : 9]; + assign bus_left_hgbw_opamp_p_to_gpio2_1 = reg_ana_amp1_inp_REG[11 : 10]; + always @(posedge PCLK or negedge PRESETn) if(~PRESETn) reg_ana_amp1_inp_REG <= 0; + else if(apb_we & (PADDR[16-1:0]==reg_ana_amp1_inp_REG_OFFSET)) + reg_ana_amp1_inp_REG <= PWDATA[12-1:0]; + + reg [12:0] reg_ana_amp1_inn_REG; + assign bus_left_hgbw_opamp_n_to_gpio5_3 = reg_ana_amp1_inn_REG[1 : 0]; + assign bus_left_hgbw_opamp_n_to_dac1 = reg_ana_amp1_inn_REG[2 : 2]; + assign bus_left_hgbw_opamp_n_to_analog1 = reg_ana_amp1_inn_REG[3 : 3]; + assign bus_left_hgbw_opamp_n_to_amuxbusB = reg_ana_amp1_inn_REG[4 : 4]; + assign bus_left_hgbw_opamp_n_to_rheostat_out = reg_ana_amp1_inn_REG[5 : 5]; + assign bus_left_hgbw_opamp_n_to_rheostat_tap = reg_ana_amp1_inn_REG[6 : 6]; + assign bus_left_hgbw_opamp_n_to_sio1 = reg_ana_amp1_inn_REG[7 : 7]; + assign bus_left_hgbw_opamp_n_to_vbgtc = reg_ana_amp1_inn_REG[8 : 8]; + assign bus_left_hgbw_opamp_n_to_right_vref = reg_ana_amp1_inn_REG[9 : 9]; + assign bus_left_hgbw_opamp_n_to_vinref = reg_ana_amp1_inn_REG[10 : 10]; + assign bus_left_hgbw_opamp_n_to_gpio2_0 = reg_ana_amp1_inn_REG[12 : 11]; + always @(posedge PCLK or negedge PRESETn) if(~PRESETn) reg_ana_amp1_inn_REG <= 0; + else if(apb_we & (PADDR[16-1:0]==reg_ana_amp1_inn_REG_OFFSET)) + reg_ana_amp1_inn_REG <= PWDATA[13-1:0]; + + reg [8:0] reg_ana_amp0_inp_REG; + assign bus_left_lp_opamp_p_to_gpio5_4 = reg_ana_amp0_inp_REG[1 : 0]; + assign bus_left_lp_opamp_p_to_dac0 = reg_ana_amp0_inp_REG[2 : 2]; + assign bus_left_lp_opamp_p_to_analog0 = reg_ana_amp0_inp_REG[3 : 3]; + assign bus_left_lp_opamp_p_to_amuxbusA = reg_ana_amp0_inp_REG[4 : 4]; + assign bus_left_lp_opamp_p_to_rheostat_out = reg_ana_amp0_inp_REG[5 : 5]; + assign bus_left_lp_opamp_p_to_sio0 = reg_ana_amp0_inp_REG[6 : 6]; + assign bus_left_lp_opamp_p_to_left_vref = reg_ana_amp0_inp_REG[7 : 7]; + assign bus_left_lp_opamp_p_to_voutref = reg_ana_amp0_inp_REG[8 : 8]; + always @(posedge PCLK or negedge PRESETn) if(~PRESETn) reg_ana_amp0_inp_REG <= 0; + else if(apb_we & (PADDR[16-1:0]==reg_ana_amp0_inp_REG_OFFSET)) + reg_ana_amp0_inp_REG <= PWDATA[9-1:0]; + + reg [10:0] reg_ana_amp0_inn_REG; + assign bus_left_lp_opamp_n_to_gpio5_5 = reg_ana_amp0_inn_REG[1 : 0]; + assign bus_left_lp_opamp_n_to_dac1 = reg_ana_amp0_inn_REG[2 : 2]; + assign bus_left_lp_opamp_n_to_analog1 = reg_ana_amp0_inn_REG[3 : 3]; + assign bus_left_lp_opamp_n_to_amuxbusB = reg_ana_amp0_inn_REG[4 : 4]; + assign bus_left_lp_opamp_n_to_rheostat_out = reg_ana_amp0_inn_REG[5 : 5]; + assign bus_left_lp_opamp_n_to_rheostat_tap = reg_ana_amp0_inn_REG[6 : 6]; + assign bus_left_lp_opamp_n_to_sio1 = reg_ana_amp0_inn_REG[7 : 7]; + assign bus_left_lp_opamp_n_to_vbgsc = reg_ana_amp0_inn_REG[8 : 8]; + assign bus_left_lp_opamp_n_to_right_vref = reg_ana_amp0_inn_REG[9 : 9]; + assign bus_left_lp_opamp_n_to_vinref = reg_ana_amp0_inn_REG[10 : 10]; + always @(posedge PCLK or negedge PRESETn) if(~PRESETn) reg_ana_amp0_inn_REG <= 0; + else if(apb_we & (PADDR[16-1:0]==reg_ana_amp0_inn_REG_OFFSET)) + reg_ana_amp0_inn_REG <= PWDATA[11-1:0]; + + reg [11:0] reg_ana_preamp0_out_REG; + assign bus_left_instramp_to_ulpcomp_p = reg_ana_preamp0_out_REG[1 : 0]; + assign bus_left_instramp_to_comp_p = reg_ana_preamp0_out_REG[3 : 2]; + assign bus_left_instramp_to_adc0 = reg_ana_preamp0_out_REG[5 : 4]; + assign bus_left_instramp_to_gpio4_4 = reg_ana_preamp0_out_REG[7 : 6]; + assign bus_left_instramp_to_analog1 = reg_ana_preamp0_out_REG[9 : 8]; + assign bus_left_instramp_to_amuxbusB = reg_ana_preamp0_out_REG[11 : 10]; + always @(posedge PCLK or negedge PRESETn) if(~PRESETn) reg_ana_preamp0_out_REG <= 0; + else if(apb_we & (PADDR[16-1:0]==reg_ana_preamp0_out_REG_OFFSET)) + reg_ana_preamp0_out_REG <= PWDATA[12-1:0]; + + reg [11:0] reg_ana_preamp1_out_REG; + assign bus_right_instramp_to_ulpcomp_n = reg_ana_preamp1_out_REG[1 : 0]; + assign bus_right_instramp_to_comp_n = reg_ana_preamp1_out_REG[3 : 2]; + assign bus_right_instramp_to_adc1 = reg_ana_preamp1_out_REG[5 : 4]; + assign bus_right_instramp_to_analog0 = reg_ana_preamp1_out_REG[7 : 6]; + assign bus_right_instramp_to_amuxbusA = reg_ana_preamp1_out_REG[9 : 8]; + assign bus_right_instramp_to_gpio3_0 = reg_ana_preamp1_out_REG[11 : 10]; + always @(posedge PCLK or negedge PRESETn) if(~PRESETn) reg_ana_preamp1_out_REG <= 0; + else if(apb_we & (PADDR[16-1:0]==reg_ana_preamp1_out_REG_OFFSET)) + reg_ana_preamp1_out_REG <= PWDATA[12-1:0]; + + reg [6:0] reg_ana_preamp0_inn_REG; + assign bus_left_instramp_n_to_gpio5_7 = reg_ana_preamp0_inn_REG[1 : 0]; + assign bus_left_instramp_n_to_analog1 = reg_ana_preamp0_inn_REG[2 : 2]; + assign bus_left_instramp_n_to_amuxbusB = reg_ana_preamp0_inn_REG[3 : 3]; + assign bus_left_instramp_n_to_sio1 = reg_ana_preamp0_inn_REG[4 : 4]; + assign bus_left_instramp_n_to_right_vref = reg_ana_preamp0_inn_REG[5 : 5]; + assign bus_left_instramp_n_to_vinref = reg_ana_preamp0_inn_REG[6 : 6]; + always @(posedge PCLK or negedge PRESETn) if(~PRESETn) reg_ana_preamp0_inn_REG <= 0; + else if(apb_we & (PADDR[16-1:0]==reg_ana_preamp0_inn_REG_OFFSET)) + reg_ana_preamp0_inn_REG <= PWDATA[7-1:0]; + + reg [7:0] reg_ana_preamp0_inp_REG; + assign bus_left_instramp_p_to_gpio5_6 = reg_ana_preamp0_inp_REG[1 : 0]; + assign bus_left_instramp_p_to_analog0 = reg_ana_preamp0_inp_REG[2 : 2]; + assign bus_left_instramp_p_to_amuxbusA = reg_ana_preamp0_inp_REG[3 : 3]; + assign bus_left_instramp_p_to_sio0 = reg_ana_preamp0_inp_REG[4 : 4]; + assign bus_left_instramp_p_to_tempsense = reg_ana_preamp0_inp_REG[5 : 5]; + assign bus_left_instramp_p_to_left_vref = reg_ana_preamp0_inp_REG[6 : 6]; + assign bus_left_instramp_p_to_voutref = reg_ana_preamp0_inp_REG[7 : 7]; + always @(posedge PCLK or negedge PRESETn) if(~PRESETn) reg_ana_preamp0_inp_REG <= 0; + else if(apb_we & (PADDR[16-1:0]==reg_ana_preamp0_inp_REG_OFFSET)) + reg_ana_preamp0_inp_REG <= PWDATA[8-1:0]; + + reg [6:0] reg_ana_preamp1_inn_REG; + assign bus_right_instramp_n_to_analog1 = reg_ana_preamp1_inn_REG[0 : 0]; + assign bus_right_instramp_n_to_amuxbusB = reg_ana_preamp1_inn_REG[1 : 1]; + assign bus_right_instramp_n_to_sio1 = reg_ana_preamp1_inn_REG[2 : 2]; + assign bus_right_instramp_n_to_right_vref = reg_ana_preamp1_inn_REG[3 : 3]; + assign bus_right_instramp_n_to_vinref = reg_ana_preamp1_inn_REG[4 : 4]; + assign bus_right_instramp_n_to_gpio2_6 = reg_ana_preamp1_inn_REG[6 : 5]; + always @(posedge PCLK or negedge PRESETn) if(~PRESETn) reg_ana_preamp1_inn_REG <= 0; + else if(apb_we & (PADDR[16-1:0]==reg_ana_preamp1_inn_REG_OFFSET)) + reg_ana_preamp1_inn_REG <= PWDATA[7-1:0]; + + reg [7:0] reg_ana_preamp1_inp_REG; + assign bus_right_instramp_p_to_analog0 = reg_ana_preamp1_inp_REG[0 : 0]; + assign bus_right_instramp_p_to_amuxbusA = reg_ana_preamp1_inp_REG[1 : 1]; + assign bus_right_instramp_p_to_sio0 = reg_ana_preamp1_inp_REG[2 : 2]; + assign bus_right_instramp_p_to_tempsense = reg_ana_preamp1_inp_REG[3 : 3]; + assign bus_right_instramp_p_to_left_vref = reg_ana_preamp1_inp_REG[4 : 4]; + assign bus_right_instramp_p_to_voutref = reg_ana_preamp1_inp_REG[5 : 5]; + assign bus_right_instramp_p_to_gpio2_7 = reg_ana_preamp1_inp_REG[7 : 6]; + always @(posedge PCLK or negedge PRESETn) if(~PRESETn) reg_ana_preamp1_inp_REG <= 0; + else if(apb_we & (PADDR[16-1:0]==reg_ana_preamp1_inp_REG_OFFSET)) + reg_ana_preamp1_inp_REG <= PWDATA[8-1:0]; + + reg [10:0] reg_ana_comp1_inp_REG; + assign bus_ulpcomp_p_to_dac0 = reg_ana_comp1_inp_REG[0 : 0]; + assign bus_ulpcomp_p_to_analog1 = reg_ana_comp1_inp_REG[1 : 1]; + assign bus_ulpcomp_p_to_sio0 = reg_ana_comp1_inp_REG[2 : 2]; + assign bus_ulpcomp_p_to_vbgtc = reg_ana_comp1_inp_REG[3 : 3]; + assign bus_ulpcomp_p_to_tempsense = reg_ana_comp1_inp_REG[4 : 4]; + assign bus_ulpcomp_p_to_left_vref = reg_ana_comp1_inp_REG[5 : 5]; + assign bus_ulpcomp_p_to_voutref = reg_ana_comp1_inp_REG[6 : 6]; + assign bus_ulpcomp_p_to_gpio6_0 = reg_ana_comp1_inp_REG[8 : 7]; + assign bus_ulpcomp_p_to_gpio1_7 = reg_ana_comp1_inp_REG[10 : 9]; + always @(posedge PCLK or negedge PRESETn) if(~PRESETn) reg_ana_comp1_inp_REG <= 0; + else if(apb_we & (PADDR[16-1:0]==reg_ana_comp1_inp_REG_OFFSET)) + reg_ana_comp1_inp_REG <= PWDATA[11-1:0]; + + reg [9:0] reg_ana_comp1_inn_REG; + assign bus_ulpcomp_n_to_dac1 = reg_ana_comp1_inn_REG[0 : 0]; + assign bus_ulpcomp_n_to_analog0 = reg_ana_comp1_inn_REG[1 : 1]; + assign bus_ulpcomp_n_to_sio1 = reg_ana_comp1_inn_REG[2 : 2]; + assign bus_ulpcomp_n_to_vbgsc = reg_ana_comp1_inn_REG[3 : 3]; + assign bus_ulpcomp_n_to_right_vref = reg_ana_comp1_inn_REG[4 : 4]; + assign bus_ulpcomp_n_to_vinref = reg_ana_comp1_inn_REG[5 : 5]; + assign bus_ulpcomp_n_to_gpio6_1 = reg_ana_comp1_inn_REG[7 : 6]; + assign bus_ulpcomp_n_to_gpio1_6 = reg_ana_comp1_inn_REG[9 : 8]; + always @(posedge PCLK or negedge PRESETn) if(~PRESETn) reg_ana_comp1_inn_REG <= 0; + else if(apb_we & (PADDR[16-1:0]==reg_ana_comp1_inn_REG_OFFSET)) + reg_ana_comp1_inn_REG <= PWDATA[10-1:0]; + + reg [10:0] reg_ana_comp0_inp_REG; + assign bus_comp_p_to_dac0 = reg_ana_comp0_inp_REG[0 : 0]; + assign bus_comp_p_to_analog1 = reg_ana_comp0_inp_REG[1 : 1]; + assign bus_comp_p_to_sio0 = reg_ana_comp0_inp_REG[2 : 2]; + assign bus_comp_p_to_vbgtc = reg_ana_comp0_inp_REG[3 : 3]; + assign bus_comp_p_to_tempsense = reg_ana_comp0_inp_REG[4 : 4]; + assign bus_comp_p_to_left_vref = reg_ana_comp0_inp_REG[5 : 5]; + assign bus_comp_p_to_voutref = reg_ana_comp0_inp_REG[6 : 6]; + assign bus_comp_p_to_gpio6_2 = reg_ana_comp0_inp_REG[8 : 7]; + assign bus_comp_p_to_gpio1_5 = reg_ana_comp0_inp_REG[10 : 9]; + always @(posedge PCLK or negedge PRESETn) if(~PRESETn) reg_ana_comp0_inp_REG <= 0; + else if(apb_we & (PADDR[16-1:0]==reg_ana_comp0_inp_REG_OFFSET)) + reg_ana_comp0_inp_REG <= PWDATA[11-1:0]; + + reg [9:0] reg_ana_comp0_inn_REG; + assign bus_comp_n_to_dac1 = reg_ana_comp0_inn_REG[0 : 0]; + assign bus_comp_n_to_analog0 = reg_ana_comp0_inn_REG[1 : 1]; + assign bus_comp_n_to_sio1 = reg_ana_comp0_inn_REG[2 : 2]; + assign bus_comp_n_to_vbgsc = reg_ana_comp0_inn_REG[3 : 3]; + assign bus_comp_n_to_right_vref = reg_ana_comp0_inn_REG[4 : 4]; + assign bus_comp_n_to_vinref = reg_ana_comp0_inn_REG[5 : 5]; + assign bus_comp_n_to_gpio6_3 = reg_ana_comp0_inn_REG[7 : 6]; + assign bus_comp_n_to_gpio1_4 = reg_ana_comp0_inn_REG[9 : 8]; + always @(posedge PCLK or negedge PRESETn) if(~PRESETn) reg_ana_comp0_inn_REG <= 0; + else if(apb_we & (PADDR[16-1:0]==reg_ana_comp0_inn_REG_OFFSET)) + reg_ana_comp0_inn_REG <= PWDATA[10-1:0]; + + reg [9:0] reg_ana_adc0_in_REG; + assign bus_adc0_to_dac0 = reg_ana_adc0_in_REG[0 : 0]; + assign bus_adc0_to_analog1 = reg_ana_adc0_in_REG[1 : 1]; + assign bus_adc0_to_vbgtc = reg_ana_adc0_in_REG[2 : 2]; + assign bus_adc0_to_tempsense = reg_ana_adc0_in_REG[3 : 3]; + assign bus_adc0_to_left_vref = reg_ana_adc0_in_REG[4 : 4]; + assign bus_adc0_to_voutref = reg_ana_adc0_in_REG[5 : 5]; + assign bus_adc0_to_gpio6_4 = reg_ana_adc0_in_REG[7 : 6]; + assign bus_adc0_to_gpio1_3 = reg_ana_adc0_in_REG[9 : 8]; + always @(posedge PCLK or negedge PRESETn) if(~PRESETn) reg_ana_adc0_in_REG <= 0; + else if(apb_we & (PADDR[16-1:0]==reg_ana_adc0_in_REG_OFFSET)) + reg_ana_adc0_in_REG <= PWDATA[10-1:0]; + + reg [8:0] reg_ana_adc1_in_REG; + assign bus_adc1_to_dac1 = reg_ana_adc1_in_REG[0 : 0]; + assign bus_adc1_to_analog0 = reg_ana_adc1_in_REG[1 : 1]; + assign bus_adc1_to_vbgsc = reg_ana_adc1_in_REG[2 : 2]; + assign bus_adc1_to_right_vref = reg_ana_adc1_in_REG[3 : 3]; + assign bus_adc1_to_vinref = reg_ana_adc1_in_REG[4 : 4]; + assign bus_adc1_to_gpio6_5 = reg_ana_adc1_in_REG[6 : 5]; + assign bus_adc1_to_gpio1_2 = reg_ana_adc1_in_REG[8 : 7]; + always @(posedge PCLK or negedge PRESETn) if(~PRESETn) reg_ana_adc1_in_REG <= 0; + else if(apb_we & (PADDR[16-1:0]==reg_ana_adc1_in_REG_OFFSET)) + reg_ana_adc1_in_REG <= PWDATA[9-1:0]; + + reg [3:0] reg_ana_sio_iso_REG; + assign bus_sio0_connect = reg_ana_sio_iso_REG[1 : 0]; + assign bus_sio1_connect = reg_ana_sio_iso_REG[3 : 2]; + always @(posedge PCLK or negedge PRESETn) if(~PRESETn) reg_ana_sio_iso_REG <= 0; + else if(apb_we & (PADDR[16-1:0]==reg_ana_sio_iso_REG_OFFSET)) + reg_ana_sio_iso_REG <= PWDATA[4-1:0]; + + reg [3:0] reg_ana_sio_ana_REG; + assign bus_analog0_connect = reg_ana_sio_ana_REG[1 : 0]; + assign bus_analog1_connect = reg_ana_sio_ana_REG[3 : 2]; + always @(posedge PCLK or negedge PRESETn) if(~PRESETn) reg_ana_sio_ana_REG <= 0; + else if(apb_we & (PADDR[16-1:0]==reg_ana_sio_ana_REG_OFFSET)) + reg_ana_sio_ana_REG <= PWDATA[4-1:0]; + + reg [20:0] reg_ana_uproj_REG; + assign bus_vbgtc_to_user = reg_ana_uproj_REG[0 : 0]; + assign bus_vbgsc_to_user = reg_ana_uproj_REG[1 : 1]; + assign bus_user_to_comp_n = reg_ana_uproj_REG[3 : 2]; + assign bus_user_to_comp_p = reg_ana_uproj_REG[5 : 4]; + assign bus_user_to_ulpcomp_n = reg_ana_uproj_REG[7 : 6]; + assign bus_user_to_ulpcomp_p = reg_ana_uproj_REG[9 : 8]; + assign bus_user_to_adc0 = reg_ana_uproj_REG[11 : 10]; + assign bus_user_to_adc1 = reg_ana_uproj_REG[13 : 12]; + assign bus_dac0_to_user = reg_ana_uproj_REG[14 : 14]; + assign bus_dac1_to_user = reg_ana_uproj_REG[15 : 15]; + assign bus_tempsense_to_user = reg_ana_uproj_REG[16 : 16]; + assign bus_right_vref_to_user = reg_ana_uproj_REG[17 : 17]; + assign bus_left_vref_to_user = reg_ana_uproj_REG[18 : 18]; + assign bus_vinref_to_user = reg_ana_uproj_REG[19 : 19]; + assign bus_voutref_to_user = reg_ana_uproj_REG[20 : 20]; + always @(posedge PCLK or negedge PRESETn) if(~PRESETn) reg_ana_uproj_REG <= 0; + else if(apb_we & (PADDR[16-1:0]==reg_ana_uproj_REG_OFFSET)) + reg_ana_uproj_REG <= PWDATA[21-1:0]; + + reg [5:0] reg_ana_dac_out_REG; + assign bus_dac0_to_analog1 = reg_ana_dac_out_REG[0 : 0]; + assign bus_dac1_to_analog0 = reg_ana_dac_out_REG[1 : 1]; + assign bus_audiodac_out_to_analog1 = reg_ana_dac_out_REG[3 : 2]; + assign bus_audiodac_outb_to_analog0 = reg_ana_dac_out_REG[5 : 4]; + always @(posedge PCLK or negedge PRESETn) if(~PRESETn) reg_ana_dac_out_REG <= 0; + else if(apb_we & (PADDR[16-1:0]==reg_ana_dac_out_REG_OFFSET)) + reg_ana_dac_out_REG <= PWDATA[6-1:0]; + + reg [10:0] reg_left_instramp_ctrl_REG; + assign bus_left_instramp_ena = reg_left_instramp_ctrl_REG[0 : 0]; + assign bus_left_instramp_G1 = reg_left_instramp_ctrl_REG[5 : 1]; + assign bus_left_instramp_G2 = reg_left_instramp_ctrl_REG[10 : 6]; + always @(posedge PCLK or negedge PRESETn) if(~PRESETn) reg_left_instramp_ctrl_REG <= 0; + else if(apb_we & (PADDR[16-1:0]==reg_left_instramp_ctrl_REG_OFFSET)) + reg_left_instramp_ctrl_REG <= PWDATA[11-1:0]; + + reg [17:0] reg_left_opamp_ctrl_REG; + assign bus_left_hgbw_opamp_ena = reg_left_opamp_ctrl_REG[0 : 0]; + assign bus_left_lp_opamp_ena = reg_left_opamp_ctrl_REG[1 : 1]; + assign bus_left_rheostat1_b = reg_left_opamp_ctrl_REG[9 : 2]; + assign bus_left_rheostat2_b = reg_left_opamp_ctrl_REG[17 : 10]; + always @(posedge PCLK or negedge PRESETn) if(~PRESETn) reg_left_opamp_ctrl_REG <= 0; + else if(apb_we & (PADDR[16-1:0]==reg_left_opamp_ctrl_REG_OFFSET)) + reg_left_opamp_ctrl_REG <= PWDATA[18-1:0]; + + reg [10:0] reg_right_instramp_ctrl_REG; + assign bus_right_instramp_ena = reg_right_instramp_ctrl_REG[0 : 0]; + assign bus_right_instramp_G1 = reg_right_instramp_ctrl_REG[5 : 1]; + assign bus_right_instramp_G2 = reg_right_instramp_ctrl_REG[10 : 6]; + always @(posedge PCLK or negedge PRESETn) if(~PRESETn) reg_right_instramp_ctrl_REG <= 0; + else if(apb_we & (PADDR[16-1:0]==reg_right_instramp_ctrl_REG_OFFSET)) + reg_right_instramp_ctrl_REG <= PWDATA[11-1:0]; + + reg [17:0] reg_right_opamp_ctrl_REG; + assign bus_right_hgbw_opamp_ena = reg_right_opamp_ctrl_REG[0 : 0]; + assign bus_right_lp_opamp_ena = reg_right_opamp_ctrl_REG[1 : 1]; + assign bus_right_rheostat1_b = reg_right_opamp_ctrl_REG[9 : 2]; + assign bus_right_rheostat2_b = reg_right_opamp_ctrl_REG[17 : 10]; + always @(posedge PCLK or negedge PRESETn) if(~PRESETn) reg_right_opamp_ctrl_REG <= 0; + else if(apb_we & (PADDR[16-1:0]==reg_right_opamp_ctrl_REG_OFFSET)) + reg_right_opamp_ctrl_REG <= PWDATA[18-1:0]; + + reg [10:0] reg_comparator_ctrl_REG; + assign bus_comp_ena = reg_comparator_ctrl_REG[0 : 0]; + assign bus_comp_trim = reg_comparator_ctrl_REG[6 : 1]; + assign bus_comp_hyst = reg_comparator_ctrl_REG[8 : 7]; + assign bus_ulpcomp_ena = reg_comparator_ctrl_REG[9 : 9]; + assign bus_ulpcomp_clk = reg_comparator_ctrl_REG[10 : 10]; + always @(posedge PCLK or negedge PRESETn) if(~PRESETn) reg_comparator_ctrl_REG <= 0; + else if(apb_we & (PADDR[16-1:0]==reg_comparator_ctrl_REG_OFFSET)) + reg_comparator_ctrl_REG <= PWDATA[11-1:0]; + + reg [24:0] reg_bandgap_ctrl_REG; + assign bus_bandgap_ena = reg_bandgap_ctrl_REG[0 : 0]; + assign bus_bandgap_trim = reg_bandgap_ctrl_REG[16 : 1]; + assign bus_bandgap_sel = reg_bandgap_ctrl_REG[17 : 17]; + assign bus_ldo_ena = reg_bandgap_ctrl_REG[18 : 18]; + assign bus_overvoltage_ena = reg_bandgap_ctrl_REG[19 : 19]; + assign bus_overvoltage_trim = reg_bandgap_ctrl_REG[23 : 20]; + assign bus_ldo_ref_sel = reg_bandgap_ctrl_REG[24 : 24]; + always @(posedge PCLK or negedge PRESETn) if(~PRESETn) reg_bandgap_ctrl_REG <= 25'h40001; // bandgap_ena and ldo_ena must be = 1 at power up + else if(apb_we & (PADDR[16-1:0]==reg_bandgap_ctrl_REG_OFFSET)) + reg_bandgap_ctrl_REG <= PWDATA[25-1:0]; + + reg [29:0] reg_ibias_ctrl_REG; + assign bus_ibias_ena = reg_ibias_ctrl_REG[0 : 0]; + assign bus_ibias_src_ena = reg_ibias_ctrl_REG[24 : 1]; + assign bus_ibias_snk_ena = reg_ibias_ctrl_REG[28 : 25]; + assign bus_ibias_ref_select = reg_ibias_ctrl_REG[29 : 29]; + always @(posedge PCLK or negedge PRESETn) if(~PRESETn) reg_ibias_ctrl_REG <= 0; + else if(apb_we & (PADDR[16-1:0]==reg_ibias_ctrl_REG_OFFSET)) + reg_ibias_ctrl_REG <= PWDATA[30-1:0]; + + reg [12:0] reg_idac_ctrl_REG; + assign bus_idac_value = reg_idac_ctrl_REG[11 : 0]; + assign bus_idac_ena = reg_idac_ctrl_REG[12 : 12]; + always @(posedge PCLK or negedge PRESETn) if(~PRESETn) reg_idac_ctrl_REG <= 0; + else if(apb_we & (PADDR[16-1:0]==reg_idac_ctrl_REG_OFFSET)) + reg_idac_ctrl_REG <= PWDATA[13-1:0]; + + reg [1:0] reg_tempsense_ctrl_REG; + assign bus_tempsense_ena = reg_tempsense_ctrl_REG[0 : 0]; + assign bus_tempsense_sel = reg_tempsense_ctrl_REG[1 : 1]; + always @(posedge PCLK or negedge PRESETn) if(~PRESETn) reg_tempsense_ctrl_REG <= 0; + else if(apb_we & (PADDR[16-1:0]==reg_tempsense_ctrl_REG_OFFSET)) + reg_tempsense_ctrl_REG <= PWDATA[2-1:0]; + + reg [25:0] reg_rdac_ctrl_REG; + assign bus_rdac0_ena = reg_rdac_ctrl_REG[0 : 0]; + assign bus_rdac0_value = reg_rdac_ctrl_REG[12 : 1]; + assign bus_rdac1_ena = reg_rdac_ctrl_REG[13 : 13]; + assign bus_rdac1_value = reg_rdac_ctrl_REG[25 : 14]; + always @(posedge PCLK or negedge PRESETn) if(~PRESETn) reg_rdac_ctrl_REG <= 0; + else if(apb_we & (PADDR[16-1:0]==reg_rdac_ctrl_REG_OFFSET)) + reg_rdac_ctrl_REG <= PWDATA[26-1:0]; + + reg [10:0] reg_brownout_ctrl_REG; + assign bus_brownout_ena = reg_brownout_ctrl_REG[0 : 0]; + assign bus_brownout_vtrip = reg_brownout_ctrl_REG[3 : 1]; + assign bus_brownout_otrip = reg_brownout_ctrl_REG[6 : 4]; + assign bus_brownout_isrc_sel = reg_brownout_ctrl_REG[7 : 7]; + assign bus_brownout_oneshot = reg_brownout_ctrl_REG[8 : 8]; + assign bus_brownout_rc_ena = reg_brownout_ctrl_REG[9 : 9]; + assign bus_brownout_rc_dis = reg_brownout_ctrl_REG[10 : 10]; + always @(posedge PCLK or negedge PRESETn) if(~PRESETn) reg_brownout_ctrl_REG <= 0; + else if(apb_we & (PADDR[16-1:0]==reg_brownout_ctrl_REG_OFFSET)) + reg_brownout_ctrl_REG <= PWDATA[11-1:0]; + + wire [4-1:0] reg_brownout_output_WIRE; + assign reg_brownout_output_WIRE[0 : 0] = bus_brownout_vunder; + assign reg_brownout_output_WIRE[1 : 1] = bus_brownout_timeout; + assign reg_brownout_output_WIRE[2 : 2] = bus_brownout_filt; + assign reg_brownout_output_WIRE[3 : 3] = bus_brownout_unfilt; + + wire [1-1:0] reg_comparator0_out_WIRE; + assign reg_comparator0_out_WIRE = bus_comp_out; + + wire [1-1:0] reg_comparator1_out_WIRE; + assign reg_comparator1_out_WIRE = bus_ulpcomp_out; + + wire [1-1:0] reg_overvoltage_out_WIRE; + assign reg_overvoltage_out_WIRE = bus_overvoltage_out; + + wire [1-1:0] reg_vdda1_pwr_good_WIRE; + assign reg_vdda1_pwr_good_WIRE = bus_vdda1_pwr_good; + + wire [1-1:0] reg_vccd1_pwr_good_WIRE; + assign reg_vccd1_pwr_good_WIRE = bus_vccd1_pwr_good; + + wire [1-1:0] reg_vdda2_pwr_good_WIRE; + assign reg_vdda2_pwr_good_WIRE = bus_vdda2_pwr_good; + + wire [1-1:0] reg_vccd2_pwr_good_WIRE; + assign reg_vccd2_pwr_good_WIRE = bus_vccd2_pwr_good; + + regs_analog_ctrl instance_to_wrap ( + .clk(clk), + .rst_n(rst_n), + .bus_ibias_test_to_gpio1_2(bus_ibias_test_to_gpio1_2), + .bus_vbg_test_to_gpio1_1(bus_vbg_test_to_gpio1_1), + .bus_idac_to_gpio1_3(bus_idac_to_gpio1_3), + .bus_idac_to_gpio1_2(bus_idac_to_gpio1_2), + .bus_adc_refh_to_gpio6_6(bus_adc_refh_to_gpio6_6), + .bus_dac_refh_to_gpio1_1(bus_dac_refh_to_gpio1_1), + .bus_adc_refl_to_gpio6_7(bus_adc_refl_to_gpio6_7), + .bus_dac_refl_to_gpio1_0(bus_dac_refl_to_gpio1_0), + .bus_right_lp_opamp_to_ulpcomp_p(bus_right_lp_opamp_to_ulpcomp_p), + .bus_right_lp_opamp_to_comp_p(bus_right_lp_opamp_to_comp_p), + .bus_right_lp_opamp_to_adc0(bus_right_lp_opamp_to_adc0), + .bus_right_lp_opamp_to_gpio4_7(bus_right_lp_opamp_to_gpio4_7), + .bus_right_lp_opamp_to_gpio4_3(bus_right_lp_opamp_to_gpio4_3), + .bus_right_lp_opamp_to_analog1(bus_right_lp_opamp_to_analog1), + .bus_right_lp_opamp_to_amuxbusB(bus_right_lp_opamp_to_amuxbusB), + .bus_right_lp_opamp_to_gpio3_7(bus_right_lp_opamp_to_gpio3_7), + .bus_right_lp_opamp_to_gpio3_3(bus_right_lp_opamp_to_gpio3_3), + .bus_right_hgbw_opamp_to_ulpcomp_n(bus_right_hgbw_opamp_to_ulpcomp_n), + .bus_right_hgbw_opamp_to_comp_n(bus_right_hgbw_opamp_to_comp_n), + .bus_right_hgbw_opamp_to_adc1(bus_right_hgbw_opamp_to_adc1), + .bus_right_hgbw_opamp_to_gpio4_6(bus_right_hgbw_opamp_to_gpio4_6), + .bus_right_hgbw_opamp_to_gpio4_2(bus_right_hgbw_opamp_to_gpio4_2), + .bus_right_hgbw_opamp_to_analog0(bus_right_hgbw_opamp_to_analog0), + .bus_right_hgbw_opamp_to_amuxbusA(bus_right_hgbw_opamp_to_amuxbusA), + .bus_right_hgbw_opamp_to_gpio3_6(bus_right_hgbw_opamp_to_gpio3_6), + .bus_right_hgbw_opamp_to_gpio3_2(bus_right_hgbw_opamp_to_gpio3_2), + .bus_left_hgbw_opamp_to_ulpcomp_p(bus_left_hgbw_opamp_to_ulpcomp_p), + .bus_left_hgbw_opamp_to_comp_p(bus_left_hgbw_opamp_to_comp_p), + .bus_left_hgbw_opamp_to_adc0(bus_left_hgbw_opamp_to_adc0), + .bus_left_hgbw_opamp_to_gpio4_5(bus_left_hgbw_opamp_to_gpio4_5), + .bus_left_hgbw_opamp_to_gpio4_1(bus_left_hgbw_opamp_to_gpio4_1), + .bus_left_hgbw_opamp_to_analog1(bus_left_hgbw_opamp_to_analog1), + .bus_left_hgbw_opamp_to_amuxbusB(bus_left_hgbw_opamp_to_amuxbusB), + .bus_left_hgbw_opamp_to_gpio3_5(bus_left_hgbw_opamp_to_gpio3_5), + .bus_left_hgbw_opamp_to_gpio3_1(bus_left_hgbw_opamp_to_gpio3_1), + .bus_left_lp_opamp_to_ulpcomp_n(bus_left_lp_opamp_to_ulpcomp_n), + .bus_left_lp_opamp_to_comp_n(bus_left_lp_opamp_to_comp_n), + .bus_left_lp_opamp_to_adc1(bus_left_lp_opamp_to_adc1), + .bus_left_lp_opamp_to_gpio4_0(bus_left_lp_opamp_to_gpio4_0), + .bus_left_lp_opamp_to_analog0(bus_left_lp_opamp_to_analog0), + .bus_left_lp_opamp_to_amuxbusA(bus_left_lp_opamp_to_amuxbusA), + .bus_left_lp_opamp_to_gpio3_4(bus_left_lp_opamp_to_gpio3_4), + .bus_right_lp_opamp_p_to_dac0(bus_right_lp_opamp_p_to_dac0), + .bus_right_lp_opamp_p_to_analog0(bus_right_lp_opamp_p_to_analog0), + .bus_right_lp_opamp_p_to_amuxbusA(bus_right_lp_opamp_p_to_amuxbusA), + .bus_right_lp_opamp_p_to_rheostat_out(bus_right_lp_opamp_p_to_rheostat_out), + .bus_right_lp_opamp_p_to_sio0(bus_right_lp_opamp_p_to_sio0), + .bus_right_lp_opamp_p_to_tempsense(bus_right_lp_opamp_p_to_tempsense), + .bus_right_lp_opamp_p_to_left_vref(bus_right_lp_opamp_p_to_left_vref), + .bus_right_lp_opamp_p_to_voutref(bus_right_lp_opamp_p_to_voutref), + .bus_right_lp_opamp_p_to_gpio2_5(bus_right_lp_opamp_p_to_gpio2_5), + .bus_right_lp_opamp_n_to_dac1(bus_right_lp_opamp_n_to_dac1), + .bus_right_lp_opamp_n_to_analog1(bus_right_lp_opamp_n_to_analog1), + .bus_right_lp_opamp_n_to_amuxbusB(bus_right_lp_opamp_n_to_amuxbusB), + .bus_right_lp_opamp_n_to_rheostat_out(bus_right_lp_opamp_n_to_rheostat_out), + .bus_right_lp_opamp_n_to_rheostat_tap(bus_right_lp_opamp_n_to_rheostat_tap), + .bus_right_lp_opamp_n_to_sio1(bus_right_lp_opamp_n_to_sio1), + .bus_right_lp_opamp_n_to_vbgtc(bus_right_lp_opamp_n_to_vbgtc), + .bus_right_lp_opamp_n_to_right_vref(bus_right_lp_opamp_n_to_right_vref), + .bus_right_lp_opamp_n_to_vinref(bus_right_lp_opamp_n_to_vinref), + .bus_right_lp_opamp_n_to_gpio2_4(bus_right_lp_opamp_n_to_gpio2_4), + .bus_right_hgbw_opamp_p_to_gpio5_0(bus_right_hgbw_opamp_p_to_gpio5_0), + .bus_right_hgbw_opamp_p_to_dac0(bus_right_hgbw_opamp_p_to_dac0), + .bus_right_hgbw_opamp_p_to_analog0(bus_right_hgbw_opamp_p_to_analog0), + .bus_right_hgbw_opamp_p_to_amuxbusA(bus_right_hgbw_opamp_p_to_amuxbusA), + .bus_right_hgbw_opamp_p_to_rheostat_out(bus_right_hgbw_opamp_p_to_rheostat_out), + .bus_right_hgbw_opamp_p_to_sio0(bus_right_hgbw_opamp_p_to_sio0), + .bus_right_hgbw_opamp_p_to_left_vref(bus_right_hgbw_opamp_p_to_left_vref), + .bus_right_hgbw_opamp_p_to_voutref(bus_right_hgbw_opamp_p_to_voutref), + .bus_right_hgbw_opamp_p_to_gpio2_3(bus_right_hgbw_opamp_p_to_gpio2_3), + .bus_right_hgbw_opamp_n_to_gpio5_1(bus_right_hgbw_opamp_n_to_gpio5_1), + .bus_right_hgbw_opamp_n_to_dac1(bus_right_hgbw_opamp_n_to_dac1), + .bus_right_hgbw_opamp_n_to_analog1(bus_right_hgbw_opamp_n_to_analog1), + .bus_right_hgbw_opamp_n_to_amuxbusB(bus_right_hgbw_opamp_n_to_amuxbusB), + .bus_right_hgbw_opamp_n_to_rheostat_out(bus_right_hgbw_opamp_n_to_rheostat_out), + .bus_right_hgbw_opamp_n_to_rheostat_tap(bus_right_hgbw_opamp_n_to_rheostat_tap), + .bus_right_hgbw_opamp_n_to_sio1(bus_right_hgbw_opamp_n_to_sio1), + .bus_right_hgbw_opamp_n_to_vbgsc(bus_right_hgbw_opamp_n_to_vbgsc), + .bus_right_hgbw_opamp_n_to_right_vref(bus_right_hgbw_opamp_n_to_right_vref), + .bus_right_hgbw_opamp_n_to_vinref(bus_right_hgbw_opamp_n_to_vinref), + .bus_right_hgbw_opamp_n_to_gpio2_2(bus_right_hgbw_opamp_n_to_gpio2_2), + .bus_left_hgbw_opamp_p_to_gpio5_2(bus_left_hgbw_opamp_p_to_gpio5_2), + .bus_left_hgbw_opamp_p_to_dac0(bus_left_hgbw_opamp_p_to_dac0), + .bus_left_hgbw_opamp_p_to_analog0(bus_left_hgbw_opamp_p_to_analog0), + .bus_left_hgbw_opamp_p_to_amuxbusA(bus_left_hgbw_opamp_p_to_amuxbusA), + .bus_left_hgbw_opamp_p_to_rheostat_out(bus_left_hgbw_opamp_p_to_rheostat_out), + .bus_left_hgbw_opamp_p_to_sio0(bus_left_hgbw_opamp_p_to_sio0), + .bus_left_hgbw_opamp_p_to_tempsense(bus_left_hgbw_opamp_p_to_tempsense), + .bus_left_hgbw_opamp_p_to_left_vref(bus_left_hgbw_opamp_p_to_left_vref), + .bus_left_hgbw_opamp_p_to_voutref(bus_left_hgbw_opamp_p_to_voutref), + .bus_left_hgbw_opamp_p_to_gpio2_1(bus_left_hgbw_opamp_p_to_gpio2_1), + .bus_left_hgbw_opamp_n_to_gpio5_3(bus_left_hgbw_opamp_n_to_gpio5_3), + .bus_left_hgbw_opamp_n_to_dac1(bus_left_hgbw_opamp_n_to_dac1), + .bus_left_hgbw_opamp_n_to_analog1(bus_left_hgbw_opamp_n_to_analog1), + .bus_left_hgbw_opamp_n_to_amuxbusB(bus_left_hgbw_opamp_n_to_amuxbusB), + .bus_left_hgbw_opamp_n_to_rheostat_out(bus_left_hgbw_opamp_n_to_rheostat_out), + .bus_left_hgbw_opamp_n_to_rheostat_tap(bus_left_hgbw_opamp_n_to_rheostat_tap), + .bus_left_hgbw_opamp_n_to_sio1(bus_left_hgbw_opamp_n_to_sio1), + .bus_left_hgbw_opamp_n_to_vbgtc(bus_left_hgbw_opamp_n_to_vbgtc), + .bus_left_hgbw_opamp_n_to_right_vref(bus_left_hgbw_opamp_n_to_right_vref), + .bus_left_hgbw_opamp_n_to_vinref(bus_left_hgbw_opamp_n_to_vinref), + .bus_left_hgbw_opamp_n_to_gpio2_0(bus_left_hgbw_opamp_n_to_gpio2_0), + .bus_left_lp_opamp_p_to_gpio5_4(bus_left_lp_opamp_p_to_gpio5_4), + .bus_left_lp_opamp_p_to_dac0(bus_left_lp_opamp_p_to_dac0), + .bus_left_lp_opamp_p_to_analog0(bus_left_lp_opamp_p_to_analog0), + .bus_left_lp_opamp_p_to_amuxbusA(bus_left_lp_opamp_p_to_amuxbusA), + .bus_left_lp_opamp_p_to_rheostat_out(bus_left_lp_opamp_p_to_rheostat_out), + .bus_left_lp_opamp_p_to_sio0(bus_left_lp_opamp_p_to_sio0), + .bus_left_lp_opamp_p_to_left_vref(bus_left_lp_opamp_p_to_left_vref), + .bus_left_lp_opamp_p_to_voutref(bus_left_lp_opamp_p_to_voutref), + .bus_left_lp_opamp_n_to_gpio5_5(bus_left_lp_opamp_n_to_gpio5_5), + .bus_left_lp_opamp_n_to_dac1(bus_left_lp_opamp_n_to_dac1), + .bus_left_lp_opamp_n_to_analog1(bus_left_lp_opamp_n_to_analog1), + .bus_left_lp_opamp_n_to_amuxbusB(bus_left_lp_opamp_n_to_amuxbusB), + .bus_left_lp_opamp_n_to_rheostat_out(bus_left_lp_opamp_n_to_rheostat_out), + .bus_left_lp_opamp_n_to_rheostat_tap(bus_left_lp_opamp_n_to_rheostat_tap), + .bus_left_lp_opamp_n_to_sio1(bus_left_lp_opamp_n_to_sio1), + .bus_left_lp_opamp_n_to_vbgsc(bus_left_lp_opamp_n_to_vbgsc), + .bus_left_lp_opamp_n_to_right_vref(bus_left_lp_opamp_n_to_right_vref), + .bus_left_lp_opamp_n_to_vinref(bus_left_lp_opamp_n_to_vinref), + .bus_left_instramp_to_ulpcomp_p(bus_left_instramp_to_ulpcomp_p), + .bus_left_instramp_to_comp_p(bus_left_instramp_to_comp_p), + .bus_left_instramp_to_adc0(bus_left_instramp_to_adc0), + .bus_left_instramp_to_gpio4_4(bus_left_instramp_to_gpio4_4), + .bus_left_instramp_to_analog1(bus_left_instramp_to_analog1), + .bus_left_instramp_to_amuxbusB(bus_left_instramp_to_amuxbusB), + .bus_right_instramp_to_ulpcomp_n(bus_right_instramp_to_ulpcomp_n), + .bus_right_instramp_to_comp_n(bus_right_instramp_to_comp_n), + .bus_right_instramp_to_adc1(bus_right_instramp_to_adc1), + .bus_right_instramp_to_analog0(bus_right_instramp_to_analog0), + .bus_right_instramp_to_amuxbusA(bus_right_instramp_to_amuxbusA), + .bus_right_instramp_to_gpio3_0(bus_right_instramp_to_gpio3_0), + .bus_left_instramp_n_to_gpio5_7(bus_left_instramp_n_to_gpio5_7), + .bus_left_instramp_n_to_analog1(bus_left_instramp_n_to_analog1), + .bus_left_instramp_n_to_amuxbusB(bus_left_instramp_n_to_amuxbusB), + .bus_left_instramp_n_to_sio1(bus_left_instramp_n_to_sio1), + .bus_left_instramp_n_to_right_vref(bus_left_instramp_n_to_right_vref), + .bus_left_instramp_n_to_vinref(bus_left_instramp_n_to_vinref), + .bus_left_instramp_p_to_gpio5_6(bus_left_instramp_p_to_gpio5_6), + .bus_left_instramp_p_to_analog0(bus_left_instramp_p_to_analog0), + .bus_left_instramp_p_to_amuxbusA(bus_left_instramp_p_to_amuxbusA), + .bus_left_instramp_p_to_sio0(bus_left_instramp_p_to_sio0), + .bus_left_instramp_p_to_tempsense(bus_left_instramp_p_to_tempsense), + .bus_left_instramp_p_to_left_vref(bus_left_instramp_p_to_left_vref), + .bus_left_instramp_p_to_voutref(bus_left_instramp_p_to_voutref), + .bus_right_instramp_n_to_analog1(bus_right_instramp_n_to_analog1), + .bus_right_instramp_n_to_amuxbusB(bus_right_instramp_n_to_amuxbusB), + .bus_right_instramp_n_to_sio1(bus_right_instramp_n_to_sio1), + .bus_right_instramp_n_to_right_vref(bus_right_instramp_n_to_right_vref), + .bus_right_instramp_n_to_vinref(bus_right_instramp_n_to_vinref), + .bus_right_instramp_n_to_gpio2_6(bus_right_instramp_n_to_gpio2_6), + .bus_right_instramp_p_to_analog0(bus_right_instramp_p_to_analog0), + .bus_right_instramp_p_to_amuxbusA(bus_right_instramp_p_to_amuxbusA), + .bus_right_instramp_p_to_sio0(bus_right_instramp_p_to_sio0), + .bus_right_instramp_p_to_tempsense(bus_right_instramp_p_to_tempsense), + .bus_right_instramp_p_to_left_vref(bus_right_instramp_p_to_left_vref), + .bus_right_instramp_p_to_voutref(bus_right_instramp_p_to_voutref), + .bus_right_instramp_p_to_gpio2_7(bus_right_instramp_p_to_gpio2_7), + .bus_ulpcomp_p_to_dac0(bus_ulpcomp_p_to_dac0), + .bus_ulpcomp_p_to_analog1(bus_ulpcomp_p_to_analog1), + .bus_ulpcomp_p_to_sio0(bus_ulpcomp_p_to_sio0), + .bus_ulpcomp_p_to_vbgtc(bus_ulpcomp_p_to_vbgtc), + .bus_ulpcomp_p_to_tempsense(bus_ulpcomp_p_to_tempsense), + .bus_ulpcomp_p_to_left_vref(bus_ulpcomp_p_to_left_vref), + .bus_ulpcomp_p_to_voutref(bus_ulpcomp_p_to_voutref), + .bus_ulpcomp_p_to_gpio6_0(bus_ulpcomp_p_to_gpio6_0), + .bus_ulpcomp_p_to_gpio1_7(bus_ulpcomp_p_to_gpio1_7), + .bus_ulpcomp_n_to_dac1(bus_ulpcomp_n_to_dac1), + .bus_ulpcomp_n_to_analog0(bus_ulpcomp_n_to_analog0), + .bus_ulpcomp_n_to_sio1(bus_ulpcomp_n_to_sio1), + .bus_ulpcomp_n_to_vbgsc(bus_ulpcomp_n_to_vbgsc), + .bus_ulpcomp_n_to_right_vref(bus_ulpcomp_n_to_right_vref), + .bus_ulpcomp_n_to_vinref(bus_ulpcomp_n_to_vinref), + .bus_ulpcomp_n_to_gpio6_1(bus_ulpcomp_n_to_gpio6_1), + .bus_ulpcomp_n_to_gpio1_6(bus_ulpcomp_n_to_gpio1_6), + .bus_comp_p_to_dac0(bus_comp_p_to_dac0), + .bus_comp_p_to_analog1(bus_comp_p_to_analog1), + .bus_comp_p_to_sio0(bus_comp_p_to_sio0), + .bus_comp_p_to_vbgtc(bus_comp_p_to_vbgtc), + .bus_comp_p_to_tempsense(bus_comp_p_to_tempsense), + .bus_comp_p_to_left_vref(bus_comp_p_to_left_vref), + .bus_comp_p_to_voutref(bus_comp_p_to_voutref), + .bus_comp_p_to_gpio6_2(bus_comp_p_to_gpio6_2), + .bus_comp_p_to_gpio1_5(bus_comp_p_to_gpio1_5), + .bus_comp_n_to_dac1(bus_comp_n_to_dac1), + .bus_comp_n_to_analog0(bus_comp_n_to_analog0), + .bus_comp_n_to_sio1(bus_comp_n_to_sio1), + .bus_comp_n_to_vbgsc(bus_comp_n_to_vbgsc), + .bus_comp_n_to_right_vref(bus_comp_n_to_right_vref), + .bus_comp_n_to_vinref(bus_comp_n_to_vinref), + .bus_comp_n_to_gpio6_3(bus_comp_n_to_gpio6_3), + .bus_comp_n_to_gpio1_4(bus_comp_n_to_gpio1_4), + .bus_adc0_to_dac0(bus_adc0_to_dac0), + .bus_adc0_to_analog1(bus_adc0_to_analog1), + .bus_adc0_to_vbgtc(bus_adc0_to_vbgtc), + .bus_adc0_to_tempsense(bus_adc0_to_tempsense), + .bus_adc0_to_left_vref(bus_adc0_to_left_vref), + .bus_adc0_to_voutref(bus_adc0_to_voutref), + .bus_adc0_to_gpio6_4(bus_adc0_to_gpio6_4), + .bus_adc0_to_gpio1_3(bus_adc0_to_gpio1_3), + .bus_adc1_to_dac1(bus_adc1_to_dac1), + .bus_adc1_to_analog0(bus_adc1_to_analog0), + .bus_adc1_to_vbgsc(bus_adc1_to_vbgsc), + .bus_adc1_to_right_vref(bus_adc1_to_right_vref), + .bus_adc1_to_vinref(bus_adc1_to_vinref), + .bus_adc1_to_gpio6_5(bus_adc1_to_gpio6_5), + .bus_adc1_to_gpio1_2(bus_adc1_to_gpio1_2), + .bus_sio0_connect(bus_sio0_connect), + .bus_sio1_connect(bus_sio1_connect), + .bus_analog0_connect(bus_analog0_connect), + .bus_analog1_connect(bus_analog1_connect), + .bus_vbgtc_to_user(bus_vbgtc_to_user), + .bus_vbgsc_to_user(bus_vbgsc_to_user), + .bus_user_to_comp_n(bus_user_to_comp_n), + .bus_user_to_comp_p(bus_user_to_comp_p), + .bus_user_to_ulpcomp_n(bus_user_to_ulpcomp_n), + .bus_user_to_ulpcomp_p(bus_user_to_ulpcomp_p), + .bus_user_to_adc0(bus_user_to_adc0), + .bus_user_to_adc1(bus_user_to_adc1), + .bus_dac0_to_user(bus_dac0_to_user), + .bus_dac1_to_user(bus_dac1_to_user), + .bus_tempsense_to_user(bus_tempsense_to_user), + .bus_right_vref_to_user(bus_right_vref_to_user), + .bus_left_vref_to_user(bus_left_vref_to_user), + .bus_vinref_to_user(bus_vinref_to_user), + .bus_voutref_to_user(bus_voutref_to_user), + .bus_dac0_to_analog1(bus_dac0_to_analog1), + .bus_dac1_to_analog0(bus_dac1_to_analog0), + .bus_audiodac_out_to_analog1(bus_audiodac_out_to_analog1), + .bus_audiodac_outb_to_analog0(bus_audiodac_outb_to_analog0), + .bus_left_instramp_ena(bus_left_instramp_ena), + .bus_left_instramp_G1(bus_left_instramp_G1), + .bus_left_instramp_G2(bus_left_instramp_G2), + .bus_left_hgbw_opamp_ena(bus_left_hgbw_opamp_ena), + .bus_left_lp_opamp_ena(bus_left_lp_opamp_ena), + .bus_left_rheostat1_b(bus_left_rheostat1_b), + .bus_left_rheostat2_b(bus_left_rheostat2_b), + .bus_right_instramp_ena(bus_right_instramp_ena), + .bus_right_instramp_G1(bus_right_instramp_G1), + .bus_right_instramp_G2(bus_right_instramp_G2), + .bus_right_hgbw_opamp_ena(bus_right_hgbw_opamp_ena), + .bus_right_lp_opamp_ena(bus_right_lp_opamp_ena), + .bus_right_rheostat1_b(bus_right_rheostat1_b), + .bus_right_rheostat2_b(bus_right_rheostat2_b), + .bus_comp_ena(bus_comp_ena), + .bus_comp_trim(bus_comp_trim), + .bus_comp_hyst(bus_comp_hyst), + .bus_ulpcomp_ena(bus_ulpcomp_ena), + .bus_ulpcomp_clk(bus_ulpcomp_clk), + .bus_bandgap_ena(bus_bandgap_ena), + .bus_bandgap_trim(bus_bandgap_trim), + .bus_bandgap_sel(bus_bandgap_sel), + .bus_ldo_ena(bus_ldo_ena), + .bus_overvoltage_ena(bus_overvoltage_ena), + .bus_overvoltage_trim(bus_overvoltage_trim), + .bus_ldo_ref_sel(bus_ldo_ref_sel), + .bus_ibias_ena(bus_ibias_ena), + .bus_ibias_src_ena(bus_ibias_src_ena), + .bus_ibias_snk_ena(bus_ibias_snk_ena), + .bus_ibias_ref_select(bus_ibias_ref_select), + .bus_idac_value(bus_idac_value), + .bus_idac_ena(bus_idac_ena), + .bus_tempsense_ena(bus_tempsense_ena), + .bus_tempsense_sel(bus_tempsense_sel), + .bus_rdac0_ena(bus_rdac0_ena), + .bus_rdac0_value(bus_rdac0_value), + .bus_rdac1_ena(bus_rdac1_ena), + .bus_rdac1_value(bus_rdac1_value), + .bus_brownout_ena(bus_brownout_ena), + .bus_brownout_vtrip(bus_brownout_vtrip), + .bus_brownout_otrip(bus_brownout_otrip), + .bus_brownout_isrc_sel(bus_brownout_isrc_sel), + .bus_brownout_oneshot(bus_brownout_oneshot), + .bus_brownout_rc_ena(bus_brownout_rc_ena), + .bus_brownout_rc_dis(bus_brownout_rc_dis), + .bus_brownout_vunder(bus_brownout_vunder), + .bus_brownout_timeout(bus_brownout_timeout), + .bus_brownout_filt(bus_brownout_filt), + .bus_brownout_unfilt(bus_brownout_unfilt), + .bus_comp_out(bus_comp_out), + .bus_ulpcomp_out(bus_ulpcomp_out), + .bus_overvoltage_out(bus_overvoltage_out), + .bus_vdda1_pwr_good(bus_vdda1_pwr_good), + .bus_vccd1_pwr_good(bus_vccd1_pwr_good), + .bus_vdda2_pwr_good(bus_vdda2_pwr_good), + .bus_vccd2_pwr_good(bus_vccd2_pwr_good), + .ibias_test_to_gpio1_2(ibias_test_to_gpio1_2), + .vbg_test_to_gpio1_1(vbg_test_to_gpio1_1), + .idac_to_gpio1_3(idac_to_gpio1_3), + .idac_to_gpio1_2(idac_to_gpio1_2), + .adc_refh_to_gpio6_6(adc_refh_to_gpio6_6), + .dac_refh_to_gpio1_1(dac_refh_to_gpio1_1), + .adc_refl_to_gpio6_7(adc_refl_to_gpio6_7), + .dac_refl_to_gpio1_0(dac_refl_to_gpio1_0), + .right_lp_opamp_to_ulpcomp_p(right_lp_opamp_to_ulpcomp_p), + .right_lp_opamp_to_comp_p(right_lp_opamp_to_comp_p), + .right_lp_opamp_to_adc0(right_lp_opamp_to_adc0), + .right_lp_opamp_to_gpio4_7(right_lp_opamp_to_gpio4_7), + .right_lp_opamp_to_gpio4_3(right_lp_opamp_to_gpio4_3), + .right_lp_opamp_to_analog1(right_lp_opamp_to_analog1), + .right_lp_opamp_to_amuxbusB(right_lp_opamp_to_amuxbusB), + .right_lp_opamp_to_gpio3_7(right_lp_opamp_to_gpio3_7), + .right_lp_opamp_to_gpio3_3(right_lp_opamp_to_gpio3_3), + .right_hgbw_opamp_to_ulpcomp_n(right_hgbw_opamp_to_ulpcomp_n), + .right_hgbw_opamp_to_comp_n(right_hgbw_opamp_to_comp_n), + .right_hgbw_opamp_to_adc1(right_hgbw_opamp_to_adc1), + .right_hgbw_opamp_to_gpio4_6(right_hgbw_opamp_to_gpio4_6), + .right_hgbw_opamp_to_gpio4_2(right_hgbw_opamp_to_gpio4_2), + .right_hgbw_opamp_to_analog0(right_hgbw_opamp_to_analog0), + .right_hgbw_opamp_to_amuxbusA(right_hgbw_opamp_to_amuxbusA), + .right_hgbw_opamp_to_gpio3_6(right_hgbw_opamp_to_gpio3_6), + .right_hgbw_opamp_to_gpio3_2(right_hgbw_opamp_to_gpio3_2), + .left_hgbw_opamp_to_ulpcomp_p(left_hgbw_opamp_to_ulpcomp_p), + .left_hgbw_opamp_to_comp_p(left_hgbw_opamp_to_comp_p), + .left_hgbw_opamp_to_adc0(left_hgbw_opamp_to_adc0), + .left_hgbw_opamp_to_gpio4_5(left_hgbw_opamp_to_gpio4_5), + .left_hgbw_opamp_to_gpio4_1(left_hgbw_opamp_to_gpio4_1), + .left_hgbw_opamp_to_analog1(left_hgbw_opamp_to_analog1), + .left_hgbw_opamp_to_amuxbusB(left_hgbw_opamp_to_amuxbusB), + .left_hgbw_opamp_to_gpio3_5(left_hgbw_opamp_to_gpio3_5), + .left_hgbw_opamp_to_gpio3_1(left_hgbw_opamp_to_gpio3_1), + .left_lp_opamp_to_ulpcomp_n(left_lp_opamp_to_ulpcomp_n), + .left_lp_opamp_to_comp_n(left_lp_opamp_to_comp_n), + .left_lp_opamp_to_adc1(left_lp_opamp_to_adc1), + .left_lp_opamp_to_gpio4_0(left_lp_opamp_to_gpio4_0), + .left_lp_opamp_to_analog0(left_lp_opamp_to_analog0), + .left_lp_opamp_to_amuxbusA(left_lp_opamp_to_amuxbusA), + .left_lp_opamp_to_gpio3_4(left_lp_opamp_to_gpio3_4), + .right_lp_opamp_p_to_dac0(right_lp_opamp_p_to_dac0), + .right_lp_opamp_p_to_analog0(right_lp_opamp_p_to_analog0), + .right_lp_opamp_p_to_amuxbusA(right_lp_opamp_p_to_amuxbusA), + .right_lp_opamp_p_to_rheostat_out(right_lp_opamp_p_to_rheostat_out), + .right_lp_opamp_p_to_sio0(right_lp_opamp_p_to_sio0), + .right_lp_opamp_p_to_tempsense(right_lp_opamp_p_to_tempsense), + .right_lp_opamp_p_to_left_vref(right_lp_opamp_p_to_left_vref), + .right_lp_opamp_p_to_voutref(right_lp_opamp_p_to_voutref), + .right_lp_opamp_p_to_gpio2_5(right_lp_opamp_p_to_gpio2_5), + .right_lp_opamp_n_to_dac1(right_lp_opamp_n_to_dac1), + .right_lp_opamp_n_to_analog1(right_lp_opamp_n_to_analog1), + .right_lp_opamp_n_to_amuxbusB(right_lp_opamp_n_to_amuxbusB), + .right_lp_opamp_n_to_rheostat_out(right_lp_opamp_n_to_rheostat_out), + .right_lp_opamp_n_to_rheostat_tap(right_lp_opamp_n_to_rheostat_tap), + .right_lp_opamp_n_to_sio1(right_lp_opamp_n_to_sio1), + .right_lp_opamp_n_to_vbgtc(right_lp_opamp_n_to_vbgtc), + .right_lp_opamp_n_to_right_vref(right_lp_opamp_n_to_right_vref), + .right_lp_opamp_n_to_vinref(right_lp_opamp_n_to_vinref), + .right_lp_opamp_n_to_gpio2_4(right_lp_opamp_n_to_gpio2_4), + .right_hgbw_opamp_p_to_gpio5_0(right_hgbw_opamp_p_to_gpio5_0), + .right_hgbw_opamp_p_to_dac0(right_hgbw_opamp_p_to_dac0), + .right_hgbw_opamp_p_to_analog0(right_hgbw_opamp_p_to_analog0), + .right_hgbw_opamp_p_to_amuxbusA(right_hgbw_opamp_p_to_amuxbusA), + .right_hgbw_opamp_p_to_rheostat_out(right_hgbw_opamp_p_to_rheostat_out), + .right_hgbw_opamp_p_to_sio0(right_hgbw_opamp_p_to_sio0), + .right_hgbw_opamp_p_to_left_vref(right_hgbw_opamp_p_to_left_vref), + .right_hgbw_opamp_p_to_voutref(right_hgbw_opamp_p_to_voutref), + .right_hgbw_opamp_p_to_gpio2_3(right_hgbw_opamp_p_to_gpio2_3), + .right_hgbw_opamp_n_to_gpio5_1(right_hgbw_opamp_n_to_gpio5_1), + .right_hgbw_opamp_n_to_dac1(right_hgbw_opamp_n_to_dac1), + .right_hgbw_opamp_n_to_analog1(right_hgbw_opamp_n_to_analog1), + .right_hgbw_opamp_n_to_amuxbusB(right_hgbw_opamp_n_to_amuxbusB), + .right_hgbw_opamp_n_to_rheostat_out(right_hgbw_opamp_n_to_rheostat_out), + .right_hgbw_opamp_n_to_rheostat_tap(right_hgbw_opamp_n_to_rheostat_tap), + .right_hgbw_opamp_n_to_sio1(right_hgbw_opamp_n_to_sio1), + .right_hgbw_opamp_n_to_vbgsc(right_hgbw_opamp_n_to_vbgsc), + .right_hgbw_opamp_n_to_right_vref(right_hgbw_opamp_n_to_right_vref), + .right_hgbw_opamp_n_to_vinref(right_hgbw_opamp_n_to_vinref), + .right_hgbw_opamp_n_to_gpio2_2(right_hgbw_opamp_n_to_gpio2_2), + .left_hgbw_opamp_p_to_gpio5_2(left_hgbw_opamp_p_to_gpio5_2), + .left_hgbw_opamp_p_to_dac0(left_hgbw_opamp_p_to_dac0), + .left_hgbw_opamp_p_to_analog0(left_hgbw_opamp_p_to_analog0), + .left_hgbw_opamp_p_to_amuxbusA(left_hgbw_opamp_p_to_amuxbusA), + .left_hgbw_opamp_p_to_rheostat_out(left_hgbw_opamp_p_to_rheostat_out), + .left_hgbw_opamp_p_to_sio0(left_hgbw_opamp_p_to_sio0), + .left_hgbw_opamp_p_to_tempsense(left_hgbw_opamp_p_to_tempsense), + .left_hgbw_opamp_p_to_left_vref(left_hgbw_opamp_p_to_left_vref), + .left_hgbw_opamp_p_to_voutref(left_hgbw_opamp_p_to_voutref), + .left_hgbw_opamp_p_to_gpio2_1(left_hgbw_opamp_p_to_gpio2_1), + .left_hgbw_opamp_n_to_gpio5_3(left_hgbw_opamp_n_to_gpio5_3), + .left_hgbw_opamp_n_to_dac1(left_hgbw_opamp_n_to_dac1), + .left_hgbw_opamp_n_to_analog1(left_hgbw_opamp_n_to_analog1), + .left_hgbw_opamp_n_to_amuxbusB(left_hgbw_opamp_n_to_amuxbusB), + .left_hgbw_opamp_n_to_rheostat_out(left_hgbw_opamp_n_to_rheostat_out), + .left_hgbw_opamp_n_to_rheostat_tap(left_hgbw_opamp_n_to_rheostat_tap), + .left_hgbw_opamp_n_to_sio1(left_hgbw_opamp_n_to_sio1), + .left_hgbw_opamp_n_to_vbgtc(left_hgbw_opamp_n_to_vbgtc), + .left_hgbw_opamp_n_to_right_vref(left_hgbw_opamp_n_to_right_vref), + .left_hgbw_opamp_n_to_vinref(left_hgbw_opamp_n_to_vinref), + .left_hgbw_opamp_n_to_gpio2_0(left_hgbw_opamp_n_to_gpio2_0), + .left_lp_opamp_p_to_gpio5_4(left_lp_opamp_p_to_gpio5_4), + .left_lp_opamp_p_to_dac0(left_lp_opamp_p_to_dac0), + .left_lp_opamp_p_to_analog0(left_lp_opamp_p_to_analog0), + .left_lp_opamp_p_to_amuxbusA(left_lp_opamp_p_to_amuxbusA), + .left_lp_opamp_p_to_rheostat_out(left_lp_opamp_p_to_rheostat_out), + .left_lp_opamp_p_to_sio0(left_lp_opamp_p_to_sio0), + .left_lp_opamp_p_to_left_vref(left_lp_opamp_p_to_left_vref), + .left_lp_opamp_p_to_voutref(left_lp_opamp_p_to_voutref), + .left_lp_opamp_n_to_gpio5_5(left_lp_opamp_n_to_gpio5_5), + .left_lp_opamp_n_to_dac1(left_lp_opamp_n_to_dac1), + .left_lp_opamp_n_to_analog1(left_lp_opamp_n_to_analog1), + .left_lp_opamp_n_to_amuxbusB(left_lp_opamp_n_to_amuxbusB), + .left_lp_opamp_n_to_rheostat_out(left_lp_opamp_n_to_rheostat_out), + .left_lp_opamp_n_to_rheostat_tap(left_lp_opamp_n_to_rheostat_tap), + .left_lp_opamp_n_to_sio1(left_lp_opamp_n_to_sio1), + .left_lp_opamp_n_to_vbgsc(left_lp_opamp_n_to_vbgsc), + .left_lp_opamp_n_to_right_vref(left_lp_opamp_n_to_right_vref), + .left_lp_opamp_n_to_vinref(left_lp_opamp_n_to_vinref), + .left_instramp_to_ulpcomp_p(left_instramp_to_ulpcomp_p), + .left_instramp_to_comp_p(left_instramp_to_comp_p), + .left_instramp_to_adc0(left_instramp_to_adc0), + .left_instramp_to_gpio4_4(left_instramp_to_gpio4_4), + .left_instramp_to_analog1(left_instramp_to_analog1), + .left_instramp_to_amuxbusB(left_instramp_to_amuxbusB), + .right_instramp_to_ulpcomp_n(right_instramp_to_ulpcomp_n), + .right_instramp_to_comp_n(right_instramp_to_comp_n), + .right_instramp_to_adc1(right_instramp_to_adc1), + .right_instramp_to_analog0(right_instramp_to_analog0), + .right_instramp_to_amuxbusA(right_instramp_to_amuxbusA), + .right_instramp_to_gpio3_0(right_instramp_to_gpio3_0), + .left_instramp_n_to_gpio5_7(left_instramp_n_to_gpio5_7), + .left_instramp_n_to_analog1(left_instramp_n_to_analog1), + .left_instramp_n_to_amuxbusB(left_instramp_n_to_amuxbusB), + .left_instramp_n_to_sio1(left_instramp_n_to_sio1), + .left_instramp_n_to_right_vref(left_instramp_n_to_right_vref), + .left_instramp_n_to_vinref(left_instramp_n_to_vinref), + .left_instramp_p_to_gpio5_6(left_instramp_p_to_gpio5_6), + .left_instramp_p_to_analog0(left_instramp_p_to_analog0), + .left_instramp_p_to_amuxbusA(left_instramp_p_to_amuxbusA), + .left_instramp_p_to_sio0(left_instramp_p_to_sio0), + .left_instramp_p_to_tempsense(left_instramp_p_to_tempsense), + .left_instramp_p_to_left_vref(left_instramp_p_to_left_vref), + .left_instramp_p_to_voutref(left_instramp_p_to_voutref), + .right_instramp_n_to_analog1(right_instramp_n_to_analog1), + .right_instramp_n_to_amuxbusB(right_instramp_n_to_amuxbusB), + .right_instramp_n_to_sio1(right_instramp_n_to_sio1), + .right_instramp_n_to_right_vref(right_instramp_n_to_right_vref), + .right_instramp_n_to_vinref(right_instramp_n_to_vinref), + .right_instramp_n_to_gpio2_6(right_instramp_n_to_gpio2_6), + .right_instramp_p_to_analog0(right_instramp_p_to_analog0), + .right_instramp_p_to_amuxbusA(right_instramp_p_to_amuxbusA), + .right_instramp_p_to_sio0(right_instramp_p_to_sio0), + .right_instramp_p_to_tempsense(right_instramp_p_to_tempsense), + .right_instramp_p_to_left_vref(right_instramp_p_to_left_vref), + .right_instramp_p_to_voutref(right_instramp_p_to_voutref), + .right_instramp_p_to_gpio2_7(right_instramp_p_to_gpio2_7), + .ulpcomp_p_to_dac0(ulpcomp_p_to_dac0), + .ulpcomp_p_to_analog1(ulpcomp_p_to_analog1), + .ulpcomp_p_to_sio0(ulpcomp_p_to_sio0), + .ulpcomp_p_to_vbgtc(ulpcomp_p_to_vbgtc), + .ulpcomp_p_to_tempsense(ulpcomp_p_to_tempsense), + .ulpcomp_p_to_left_vref(ulpcomp_p_to_left_vref), + .ulpcomp_p_to_voutref(ulpcomp_p_to_voutref), + .ulpcomp_p_to_gpio6_0(ulpcomp_p_to_gpio6_0), + .ulpcomp_p_to_gpio1_7(ulpcomp_p_to_gpio1_7), + .ulpcomp_n_to_dac1(ulpcomp_n_to_dac1), + .ulpcomp_n_to_analog0(ulpcomp_n_to_analog0), + .ulpcomp_n_to_sio1(ulpcomp_n_to_sio1), + .ulpcomp_n_to_vbgsc(ulpcomp_n_to_vbgsc), + .ulpcomp_n_to_right_vref(ulpcomp_n_to_right_vref), + .ulpcomp_n_to_vinref(ulpcomp_n_to_vinref), + .ulpcomp_n_to_gpio6_1(ulpcomp_n_to_gpio6_1), + .ulpcomp_n_to_gpio1_6(ulpcomp_n_to_gpio1_6), + .comp_p_to_dac0(comp_p_to_dac0), + .comp_p_to_analog1(comp_p_to_analog1), + .comp_p_to_sio0(comp_p_to_sio0), + .comp_p_to_vbgtc(comp_p_to_vbgtc), + .comp_p_to_tempsense(comp_p_to_tempsense), + .comp_p_to_left_vref(comp_p_to_left_vref), + .comp_p_to_voutref(comp_p_to_voutref), + .comp_p_to_gpio6_2(comp_p_to_gpio6_2), + .comp_p_to_gpio1_5(comp_p_to_gpio1_5), + .comp_n_to_dac1(comp_n_to_dac1), + .comp_n_to_analog0(comp_n_to_analog0), + .comp_n_to_sio1(comp_n_to_sio1), + .comp_n_to_vbgsc(comp_n_to_vbgsc), + .comp_n_to_right_vref(comp_n_to_right_vref), + .comp_n_to_vinref(comp_n_to_vinref), + .comp_n_to_gpio6_3(comp_n_to_gpio6_3), + .comp_n_to_gpio1_4(comp_n_to_gpio1_4), + .adc0_to_dac0(adc0_to_dac0), + .adc0_to_analog1(adc0_to_analog1), + .adc0_to_vbgtc(adc0_to_vbgtc), + .adc0_to_tempsense(adc0_to_tempsense), + .adc0_to_left_vref(adc0_to_left_vref), + .adc0_to_voutref(adc0_to_voutref), + .adc0_to_gpio6_4(adc0_to_gpio6_4), + .adc0_to_gpio1_3(adc0_to_gpio1_3), + .adc1_to_dac1(adc1_to_dac1), + .adc1_to_analog0(adc1_to_analog0), + .adc1_to_vbgsc(adc1_to_vbgsc), + .adc1_to_right_vref(adc1_to_right_vref), + .adc1_to_vinref(adc1_to_vinref), + .adc1_to_gpio6_5(adc1_to_gpio6_5), + .adc1_to_gpio1_2(adc1_to_gpio1_2), + .sio0_connect(sio0_connect), + .sio1_connect(sio1_connect), + .analog0_connect(analog0_connect), + .analog1_connect(analog1_connect), + .vbgtc_to_user(vbgtc_to_user), + .vbgsc_to_user(vbgsc_to_user), + .user_to_comp_n(user_to_comp_n), + .user_to_comp_p(user_to_comp_p), + .user_to_ulpcomp_n(user_to_ulpcomp_n), + .user_to_ulpcomp_p(user_to_ulpcomp_p), + .user_to_adc0(user_to_adc0), + .user_to_adc1(user_to_adc1), + .dac0_to_user(dac0_to_user), + .dac1_to_user(dac1_to_user), + .tempsense_to_user(tempsense_to_user), + .right_vref_to_user(right_vref_to_user), + .left_vref_to_user(left_vref_to_user), + .vinref_to_user(vinref_to_user), + .voutref_to_user(voutref_to_user), + .dac0_to_analog1(dac0_to_analog1), + .dac1_to_analog0(dac1_to_analog0), + .audiodac_out_to_analog1(audiodac_out_to_analog1), + .audiodac_outb_to_analog0(audiodac_outb_to_analog0), + .left_instramp_ena(left_instramp_ena), + .left_instramp_G1(left_instramp_G1), + .left_instramp_G2(left_instramp_G2), + .left_hgbw_opamp_ena(left_hgbw_opamp_ena), + .left_lp_opamp_ena(left_lp_opamp_ena), + .left_rheostat1_b(left_rheostat1_b), + .left_rheostat2_b(left_rheostat2_b), + .right_instramp_ena(right_instramp_ena), + .right_instramp_G1(right_instramp_G1), + .right_instramp_G2(right_instramp_G2), + .right_hgbw_opamp_ena(right_hgbw_opamp_ena), + .right_lp_opamp_ena(right_lp_opamp_ena), + .right_rheostat1_b(right_rheostat1_b), + .right_rheostat2_b(right_rheostat2_b), + .comp_ena(comp_ena), + .comp_trim(comp_trim), + .comp_hyst(comp_hyst), + .ulpcomp_ena(ulpcomp_ena), + .ulpcomp_clk(ulpcomp_clk), + .bandgap_ena(bandgap_ena), + .bandgap_trim(bandgap_trim), + .bandgap_sel(bandgap_sel), + .ldo_ena(ldo_ena), + .overvoltage_ena(overvoltage_ena), + .overvoltage_trim(overvoltage_trim), + .ldo_ref_sel(ldo_ref_sel), + .ibias_ena(ibias_ena), + .ibias_src_ena(ibias_src_ena), + .ibias_snk_ena(ibias_snk_ena), + .ibias_ref_select(ibias_ref_select), + .idac_value(idac_value), + .idac_ena(idac_ena), + .tempsense_ena(tempsense_ena), + .tempsense_sel(tempsense_sel), + .rdac0_ena(rdac0_ena), + .rdac0_value(rdac0_value), + .rdac1_ena(rdac1_ena), + .rdac1_value(rdac1_value), + .brownout_ena(brownout_ena), + .brownout_vtrip(brownout_vtrip), + .brownout_otrip(brownout_otrip), + .brownout_isrc_sel(brownout_isrc_sel), + .brownout_oneshot(brownout_oneshot), + .brownout_rc_ena(brownout_rc_ena), + .brownout_rc_dis(brownout_rc_dis), + .brownout_vunder(brownout_vunder), + .brownout_timeout(brownout_timeout), + .brownout_filt(brownout_filt), + .brownout_unfilt(brownout_unfilt), + .comp_out(comp_out), + .ulpcomp_out(ulpcomp_out), + .overvoltage_out(overvoltage_out), + .vdda1_pwr_good(vdda1_pwr_good), + .vccd1_pwr_good(vccd1_pwr_good), + .vdda2_pwr_good(vdda2_pwr_good), + .vccd2_pwr_good(vccd2_pwr_good) + ); + + assign PRDATA = + (PADDR[16-1:0] == reg_ana_test_REG_OFFSET) ? reg_ana_test_REG : + (PADDR[16-1:0] == reg_ana_idac_REG_OFFSET) ? reg_ana_idac_REG : + (PADDR[16-1:0] == reg_ana_ref_REG_OFFSET) ? reg_ana_ref_REG : + (PADDR[16-1:0] == reg_ana_amp3_out_REG_OFFSET) ? reg_ana_amp3_out_REG : + (PADDR[16-1:0] == reg_ana_amp2_out_REG_OFFSET) ? reg_ana_amp2_out_REG : + (PADDR[16-1:0] == reg_ana_amp1_out_REG_OFFSET) ? reg_ana_amp1_out_REG : + (PADDR[16-1:0] == reg_ana_amp0_out_REG_OFFSET) ? reg_ana_amp0_out_REG : + (PADDR[16-1:0] == reg_ana_amp3_inp_REG_OFFSET) ? reg_ana_amp3_inp_REG : + (PADDR[16-1:0] == reg_ana_amp3_inn_REG_OFFSET) ? reg_ana_amp3_inn_REG : + (PADDR[16-1:0] == reg_ana_amp2_inp_REG_OFFSET) ? reg_ana_amp2_inp_REG : + (PADDR[16-1:0] == reg_ana_amp2_inn_REG_OFFSET) ? reg_ana_amp2_inn_REG : + (PADDR[16-1:0] == reg_ana_amp1_inp_REG_OFFSET) ? reg_ana_amp1_inp_REG : + (PADDR[16-1:0] == reg_ana_amp1_inn_REG_OFFSET) ? reg_ana_amp1_inn_REG : + (PADDR[16-1:0] == reg_ana_amp0_inp_REG_OFFSET) ? reg_ana_amp0_inp_REG : + (PADDR[16-1:0] == reg_ana_amp0_inn_REG_OFFSET) ? reg_ana_amp0_inn_REG : + (PADDR[16-1:0] == reg_ana_preamp0_out_REG_OFFSET) ? reg_ana_preamp0_out_REG : + (PADDR[16-1:0] == reg_ana_preamp1_out_REG_OFFSET) ? reg_ana_preamp1_out_REG : + (PADDR[16-1:0] == reg_ana_preamp0_inn_REG_OFFSET) ? reg_ana_preamp0_inn_REG : + (PADDR[16-1:0] == reg_ana_preamp0_inp_REG_OFFSET) ? reg_ana_preamp0_inp_REG : + (PADDR[16-1:0] == reg_ana_preamp1_inn_REG_OFFSET) ? reg_ana_preamp1_inn_REG : + (PADDR[16-1:0] == reg_ana_preamp1_inp_REG_OFFSET) ? reg_ana_preamp1_inp_REG : + (PADDR[16-1:0] == reg_ana_comp1_inp_REG_OFFSET) ? reg_ana_comp1_inp_REG : + (PADDR[16-1:0] == reg_ana_comp1_inn_REG_OFFSET) ? reg_ana_comp1_inn_REG : + (PADDR[16-1:0] == reg_ana_comp0_inp_REG_OFFSET) ? reg_ana_comp0_inp_REG : + (PADDR[16-1:0] == reg_ana_comp0_inn_REG_OFFSET) ? reg_ana_comp0_inn_REG : + (PADDR[16-1:0] == reg_ana_adc0_in_REG_OFFSET) ? reg_ana_adc0_in_REG : + (PADDR[16-1:0] == reg_ana_adc1_in_REG_OFFSET) ? reg_ana_adc1_in_REG : + (PADDR[16-1:0] == reg_ana_sio_iso_REG_OFFSET) ? reg_ana_sio_iso_REG : + (PADDR[16-1:0] == reg_ana_sio_ana_REG_OFFSET) ? reg_ana_sio_ana_REG : + (PADDR[16-1:0] == reg_ana_uproj_REG_OFFSET) ? reg_ana_uproj_REG : + (PADDR[16-1:0] == reg_ana_dac_out_REG_OFFSET) ? reg_ana_dac_out_REG : + (PADDR[16-1:0] == reg_left_instramp_ctrl_REG_OFFSET) ? reg_left_instramp_ctrl_REG : + (PADDR[16-1:0] == reg_left_opamp_ctrl_REG_OFFSET) ? reg_left_opamp_ctrl_REG : + (PADDR[16-1:0] == reg_right_instramp_ctrl_REG_OFFSET) ? reg_right_instramp_ctrl_REG : + (PADDR[16-1:0] == reg_right_opamp_ctrl_REG_OFFSET) ? reg_right_opamp_ctrl_REG : + (PADDR[16-1:0] == reg_comparator_ctrl_REG_OFFSET) ? reg_comparator_ctrl_REG : + (PADDR[16-1:0] == reg_bandgap_ctrl_REG_OFFSET) ? reg_bandgap_ctrl_REG : + (PADDR[16-1:0] == reg_ibias_ctrl_REG_OFFSET) ? reg_ibias_ctrl_REG : + (PADDR[16-1:0] == reg_idac_ctrl_REG_OFFSET) ? reg_idac_ctrl_REG : + (PADDR[16-1:0] == reg_tempsense_ctrl_REG_OFFSET) ? reg_tempsense_ctrl_REG : + (PADDR[16-1:0] == reg_rdac_ctrl_REG_OFFSET) ? reg_rdac_ctrl_REG : + (PADDR[16-1:0] == reg_brownout_ctrl_REG_OFFSET) ? reg_brownout_ctrl_REG : + (PADDR[16-1:0] == reg_brownout_output_REG_OFFSET) ? reg_brownout_output_WIRE : + (PADDR[16-1:0] == reg_comparator0_out_REG_OFFSET) ? reg_comparator0_out_WIRE : + (PADDR[16-1:0] == reg_comparator1_out_REG_OFFSET) ? reg_comparator1_out_WIRE : + (PADDR[16-1:0] == reg_overvoltage_out_REG_OFFSET) ? reg_overvoltage_out_WIRE : + (PADDR[16-1:0] == reg_vdda1_pwr_good_REG_OFFSET) ? reg_vdda1_pwr_good_WIRE : + (PADDR[16-1:0] == reg_vccd1_pwr_good_REG_OFFSET) ? reg_vccd1_pwr_good_WIRE : + (PADDR[16-1:0] == reg_vdda2_pwr_good_REG_OFFSET) ? reg_vdda2_pwr_good_WIRE : + (PADDR[16-1:0] == reg_vccd2_pwr_good_REG_OFFSET) ? reg_vccd2_pwr_good_WIRE : + 32'hDEADBEEF; + + assign PREADY = 1'b1; + +endmodule diff --git a/regs_analog_ctrl_APB/signoff.sdc b/regs_analog_ctrl_APB/signoff.sdc new file mode 100644 index 0000000..e96b4b1 --- /dev/null +++ b/regs_analog_ctrl_APB/signoff.sdc @@ -0,0 +1,27 @@ +## CLOCK CONSTRAINTS +create_clock [get_ports $::env(CLOCK_PORT)] -name $::env(CLOCK_PORT) -period 20 +set_propagated_clock [get_clocks $::env(CLOCK_PORT)] +# set_clock_transition 1.5 [get_clocks $::env(CLOCK_PORT)] +set_driving_cell -lib_cell sky130_fd_sc_hd__clkbuf_4 -pin {X} [get_ports $::env(CLOCK_PORT)] +set_clock_uncertainty 0.1 [get_clocks $::env(CLOCK_PORT)] + +## INPUT DELAY +set_input_transition 0.5 [all_inputs] +set_input_delay -max 4 -clock [get_clocks $::env(CLOCK_PORT)] [all_inputs] +set_input_delay -min 3.3 -clock [get_clocks $::env(CLOCK_PORT)] [all_inputs] + +## OUTPUT DELAY +set_output_delay 4 -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs] + +## CAP LOAD +set cap_load 0.075 +puts "\[INFO\]: Setting load to: $cap_load" +set_load $cap_load [all_outputs] + +## MAX TRANS +set_max_trans 1.5 [current_design] + +## DERATES +puts "\[INFO\]: Setting timing derate to: [expr {5 * 100}] %" +set_timing_derate -early 0.95 +set_timing_derate -late 1.05