diff --git a/hdl/rtl/EF_UART.v b/hdl/rtl/EF_UART.v
index 8b4b01f..f33f817 100644
--- a/hdl/rtl/EF_UART.v
+++ b/hdl/rtl/EF_UART.v
@@ -103,13 +103,13 @@ module EF_UART #(parameter  MDW = 9,        // Max data size/width
     wire        rx_filtered;
     wire        rx_in;
 
-    aucohl_sync rx_sync (
+    ef_util_sync rx_sync (
         .clk(clk),
         .in(rx),
         .out(rx_synched)
     );
 
-    aucohl_glitch_filter #(.N(GFLEN)) rx_glitch_filter (
+    ef_util_glitch_filter #(.N(GFLEN)) rx_glitch_filter (
         .clk(clk),
         .rst_n(rst_n),
         .en(glitch_filter_en),
@@ -129,7 +129,7 @@ module EF_UART #(parameter  MDW = 9,        // Max data size/width
         .baudtick(b_tick)
     );
   
-    aucohl_fifo #(.DW(FIFO_DW), .AW(FAW)) fifo_tx (
+    ef_util_fifo #(.DW(FIFO_DW), .AW(FAW)) fifo_tx (
         .clk(clk),
         .rst_n(rst_n),
         .rd(tx_done),
@@ -155,7 +155,7 @@ module EF_UART #(parameter  MDW = 9,        // Max data size/width
         .tx(tx)
     );
 
-    aucohl_fifo #(.DW(FIFO_DW), .AW(FAW)) fifo_rx (
+    ef_util_fifo #(.DW(FIFO_DW), .AW(FAW)) fifo_rx (
         .clk(clk),
         .rst_n(rst_n),
         .rd(rd),
diff --git a/hdl/rtl/bus_wrappers/EF_UART_AHBL.dev.v b/hdl/rtl/bus_wrappers/EF_UART_AHBL.dev.v
new file mode 100644
index 0000000..4d8dc07
--- /dev/null
+++ b/hdl/rtl/bus_wrappers/EF_UART_AHBL.dev.v
@@ -0,0 +1,294 @@
+/*
+	Copyright 2024 Efabless Corp.
+
+	Author: Mohamed Shalan (mshalan@efabless.com)
+
+	Licensed under the Apache License, Version 2.0 (the "License");
+	you may not use this file except in compliance with the License.
+	You may obtain a copy of the License at
+
+	    http://www.apache.org/licenses/LICENSE-2.0
+
+	Unless required by applicable law or agreed to in writing, software
+	distributed under the License is distributed on an "AS IS" BASIS,
+	WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+	See the License for the specific language governing permissions and
+	limitations under the License.
+
+*/
+
+/* THIS FILE IS GENERATED, DO NOT EDIT */
+
+`timescale			1ns/1ps
+`default_nettype	none
+
+`define				AHBL_AW		16
+
+`include			"ahbl_wrapper.vh"
+
+module EF_UART_AHBL #( 
+	parameter	
+		SC = 8,
+		MDW = 9,
+		GFLEN = 8,
+		FAW = 4
+) (
+`ifdef USE_POWER_PINS
+	inout VPWR,
+	inout VGND,
+`endif
+	`AHBL_SLAVE_PORTS,
+	input	wire	[1-1:0]	rx,
+	output	wire	[1-1:0]	tx
+);
+
+	localparam	RXDATA_REG_OFFSET = `AHBL_AW'h0000;
+	localparam	TXDATA_REG_OFFSET = `AHBL_AW'h0004;
+	localparam	PR_REG_OFFSET = `AHBL_AW'h0008;
+	localparam	CTRL_REG_OFFSET = `AHBL_AW'h000C;
+	localparam	CFG_REG_OFFSET = `AHBL_AW'h0010;
+	localparam	MATCH_REG_OFFSET = `AHBL_AW'h001C;
+	localparam	RX_FIFO_LEVEL_REG_OFFSET = `AHBL_AW'hFE00;
+	localparam	RX_FIFO_THRESHOLD_REG_OFFSET = `AHBL_AW'hFE04;
+	localparam	RX_FIFO_FLUSH_REG_OFFSET = `AHBL_AW'hFE08;
+	localparam	TX_FIFO_LEVEL_REG_OFFSET = `AHBL_AW'hFE10;
+	localparam	TX_FIFO_THRESHOLD_REG_OFFSET = `AHBL_AW'hFE14;
+	localparam	TX_FIFO_FLUSH_REG_OFFSET = `AHBL_AW'hFE18;
+	localparam	IM_REG_OFFSET = `AHBL_AW'hFF00;
+	localparam	MIS_REG_OFFSET = `AHBL_AW'hFF04;
+	localparam	RIS_REG_OFFSET = `AHBL_AW'hFF08;
+	localparam	IC_REG_OFFSET = `AHBL_AW'hFF0C;
+
+    reg [0:0] GCLK_REG;
+    wire clk_g;
+    wire clk_gated_en = GCLK_REG[0];
+    ef_util_gating_cell clk_gate_cell(
+        `ifdef USE_POWER_PINS 
+        .vpwr(VPWR),
+        .vgnd(VGND),
+        `endif // USE_POWER_PINS
+        .clk(HCLK),
+        .clk_en(clk_gated_en),
+        .clk_o(clk_g)
+    );
+    
+	wire		clk = clk_g;
+	wire		rst_n = HRESETn;
+
+
+	`AHBL_CTRL_SIGNALS
+
+	wire [16-1:0]	prescaler;
+	wire [1-1:0]	en;
+	wire [1-1:0]	tx_en;
+	wire [1-1:0]	rx_en;
+	wire [MDW-1:0]	wdata;
+	wire [6-1:0]	timeout_bits;
+	wire [1-1:0]	loopback_en;
+	wire [1-1:0]	glitch_filter_en;
+	wire [FAW-1:0]	tx_level;
+	wire [FAW-1:0]	rx_level;
+	wire [1-1:0]	rd;
+	wire [1-1:0]	wr;
+	wire [1-1:0]	tx_fifo_flush;
+	wire [1-1:0]	rx_fifo_flush;
+	wire [4-1:0]	data_size;
+	wire [1-1:0]	stop_bits_count;
+	wire [3-1:0]	parity_type;
+	wire [FAW-1:0]	txfifotr;
+	wire [FAW-1:0]	rxfifotr;
+	wire [MDW-1:0]	match_data;
+	wire [1-1:0]	tx_empty;
+	wire [1-1:0]	tx_full;
+	wire [1-1:0]	tx_level_below;
+	wire [MDW-1:0]	rdata;
+	wire [1-1:0]	rx_empty;
+	wire [1-1:0]	rx_full;
+	wire [1-1:0]	rx_level_above;
+	wire [1-1:0]	break_flag;
+	wire [1-1:0]	match_flag;
+	wire [1-1:0]	frame_error_flag;
+	wire [1-1:0]	parity_error_flag;
+	wire [1-1:0]	overrun_flag;
+	wire [1-1:0]	timeout_flag;
+
+	// Register Definitions
+	wire	[MDW-1:0]	RXDATA_WIRE;
+
+	wire	[MDW-1:0]	TXDATA_WIRE;
+
+	reg [15:0]	PR_REG;
+	assign	prescaler = PR_REG;
+	`AHBL_REG(PR_REG, 0, 16)
+
+	reg [4:0]	CTRL_REG;
+	assign	en	=	CTRL_REG[0 : 0];
+	assign	tx_en	=	CTRL_REG[1 : 1];
+	assign	rx_en	=	CTRL_REG[2 : 2];
+	assign	loopback_en	=	CTRL_REG[3 : 3];
+	assign	glitch_filter_en	=	CTRL_REG[4 : 4];
+	`AHBL_REG(CTRL_REG, 0, 5)
+
+	reg [13:0]	CFG_REG;
+	assign	data_size	=	CFG_REG[3 : 0];
+	assign	stop_bits_count	=	CFG_REG[4 : 4];
+	assign	parity_type	=	CFG_REG[7 : 5];
+	assign	timeout_bits	=	CFG_REG[13 : 8];
+	`AHBL_REG(CFG_REG, 'h3F08, 14)
+
+	reg [MDW-1:0]	MATCH_REG;
+	assign	match_data = MATCH_REG;
+	`AHBL_REG(MATCH_REG, 0, MDW)
+
+	wire [FAW-1:0]	RX_FIFO_LEVEL_WIRE;
+	assign	RX_FIFO_LEVEL_WIRE[(FAW - 1) : 0] = rx_level;
+
+	reg [FAW-1:0]	RX_FIFO_THRESHOLD_REG;
+	assign	rxfifotr	=	RX_FIFO_THRESHOLD_REG[(FAW - 1) : 0];
+	`AHBL_REG(RX_FIFO_THRESHOLD_REG, 0, FAW)
+
+	reg [0:0]	RX_FIFO_FLUSH_REG;
+	assign	rx_fifo_flush	=	RX_FIFO_FLUSH_REG[0 : 0];
+	`AHBL_REG_AC(RX_FIFO_FLUSH_REG, 0, 1, 1'h0)
+
+	wire [FAW-1:0]	TX_FIFO_LEVEL_WIRE;
+	assign	TX_FIFO_LEVEL_WIRE[(FAW - 1) : 0] = tx_level;
+
+	reg [FAW-1:0]	TX_FIFO_THRESHOLD_REG;
+	assign	txfifotr	=	TX_FIFO_THRESHOLD_REG[(FAW - 1) : 0];
+	`AHBL_REG(TX_FIFO_THRESHOLD_REG, 0, FAW)
+
+	reg [0:0]	TX_FIFO_FLUSH_REG;
+	assign	tx_fifo_flush	=	TX_FIFO_FLUSH_REG[0 : 0];
+	`AHBL_REG_AC(TX_FIFO_FLUSH_REG, 0, 1, 1'h0)
+
+	localparam	GCLK_REG_OFFSET = `AHBL_AW'hFF10;
+	`AHBL_REG(GCLK_REG, 0, 1)
+
+	reg [9:0] IM_REG;
+	reg [9:0] IC_REG;
+	reg [9:0] RIS_REG;
+
+	`AHBL_MIS_REG(10)
+	`AHBL_REG(IM_REG, 0, 10)
+	`AHBL_IC_REG(10)
+
+	wire [0:0] TXE = tx_empty;
+	wire [0:0] RXF = rx_full;
+	wire [0:0] TXB = tx_level_below;
+	wire [0:0] RXA = rx_level_above;
+	wire [0:0] BRK = break_flag;
+	wire [0:0] MATCH = match_flag;
+	wire [0:0] FE = frame_error_flag;
+	wire [0:0] PRE = parity_error_flag;
+	wire [0:0] OR = overrun_flag;
+	wire [0:0] RTO = timeout_flag;
+
+
+	integer _i_;
+	`AHBL_BLOCK(RIS_REG, 0) else begin
+		for(_i_ = 0; _i_ < 1; _i_ = _i_ + 1) begin
+			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(TXE[_i_ - 0] == 1'b1) RIS_REG[_i_] <= 1'b1;
+		end
+		for(_i_ = 1; _i_ < 2; _i_ = _i_ + 1) begin
+			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(RXF[_i_ - 1] == 1'b1) RIS_REG[_i_] <= 1'b1;
+		end
+		for(_i_ = 2; _i_ < 3; _i_ = _i_ + 1) begin
+			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(TXB[_i_ - 2] == 1'b1) RIS_REG[_i_] <= 1'b1;
+		end
+		for(_i_ = 3; _i_ < 4; _i_ = _i_ + 1) begin
+			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(RXA[_i_ - 3] == 1'b1) RIS_REG[_i_] <= 1'b1;
+		end
+		for(_i_ = 4; _i_ < 5; _i_ = _i_ + 1) begin
+			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(BRK[_i_ - 4] == 1'b1) RIS_REG[_i_] <= 1'b1;
+		end
+		for(_i_ = 5; _i_ < 6; _i_ = _i_ + 1) begin
+			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(MATCH[_i_ - 5] == 1'b1) RIS_REG[_i_] <= 1'b1;
+		end
+		for(_i_ = 6; _i_ < 7; _i_ = _i_ + 1) begin
+			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(FE[_i_ - 6] == 1'b1) RIS_REG[_i_] <= 1'b1;
+		end
+		for(_i_ = 7; _i_ < 8; _i_ = _i_ + 1) begin
+			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(PRE[_i_ - 7] == 1'b1) RIS_REG[_i_] <= 1'b1;
+		end
+		for(_i_ = 8; _i_ < 9; _i_ = _i_ + 1) begin
+			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(OR[_i_ - 8] == 1'b1) RIS_REG[_i_] <= 1'b1;
+		end
+		for(_i_ = 9; _i_ < 10; _i_ = _i_ + 1) begin
+			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(RTO[_i_ - 9] == 1'b1) RIS_REG[_i_] <= 1'b1;
+		end
+	end
+
+	assign IRQ = |MIS_REG;
+
+	EF_UART #(
+		.SC(SC),
+		.MDW(MDW),
+		.GFLEN(GFLEN),
+		.FAW(FAW)
+	) instance_to_wrap (
+		.clk(clk),
+		.rst_n(rst_n),
+		.prescaler(prescaler),
+		.en(en),
+		.tx_en(tx_en),
+		.rx_en(rx_en),
+		.wdata(wdata),
+		.timeout_bits(timeout_bits),
+		.loopback_en(loopback_en),
+		.glitch_filter_en(glitch_filter_en),
+		.tx_level(tx_level),
+		.rx_level(rx_level),
+		.rd(rd),
+		.wr(wr),
+		.tx_fifo_flush(tx_fifo_flush),
+		.rx_fifo_flush(rx_fifo_flush),
+		.data_size(data_size),
+		.stop_bits_count(stop_bits_count),
+		.parity_type(parity_type),
+		.txfifotr(txfifotr),
+		.rxfifotr(rxfifotr),
+		.match_data(match_data),
+		.tx_empty(tx_empty),
+		.tx_full(tx_full),
+		.tx_level_below(tx_level_below),
+		.rdata(rdata),
+		.rx_empty(rx_empty),
+		.rx_full(rx_full),
+		.rx_level_above(rx_level_above),
+		.break_flag(break_flag),
+		.match_flag(match_flag),
+		.frame_error_flag(frame_error_flag),
+		.parity_error_flag(parity_error_flag),
+		.overrun_flag(overrun_flag),
+		.timeout_flag(timeout_flag),
+		.rx(rx),
+		.tx(tx)
+	);
+
+	assign	HRDATA = 
+			(last_HADDR[`AHBL_AW-1:0] == RXDATA_REG_OFFSET)	? RXDATA_WIRE :
+			(last_HADDR[`AHBL_AW-1:0] == TXDATA_REG_OFFSET)	? TXDATA_WIRE :
+			(last_HADDR[`AHBL_AW-1:0] == PR_REG_OFFSET)	? PR_REG :
+			(last_HADDR[`AHBL_AW-1:0] == CTRL_REG_OFFSET)	? CTRL_REG :
+			(last_HADDR[`AHBL_AW-1:0] == CFG_REG_OFFSET)	? CFG_REG :
+			(last_HADDR[`AHBL_AW-1:0] == MATCH_REG_OFFSET)	? MATCH_REG :
+			(last_HADDR[`AHBL_AW-1:0] == RX_FIFO_LEVEL_REG_OFFSET)	? RX_FIFO_LEVEL_WIRE :
+			(last_HADDR[`AHBL_AW-1:0] == RX_FIFO_THRESHOLD_REG_OFFSET)	? RX_FIFO_THRESHOLD_REG :
+			(last_HADDR[`AHBL_AW-1:0] == RX_FIFO_FLUSH_REG_OFFSET)	? RX_FIFO_FLUSH_REG :
+			(last_HADDR[`AHBL_AW-1:0] == TX_FIFO_LEVEL_REG_OFFSET)	? TX_FIFO_LEVEL_WIRE :
+			(last_HADDR[`AHBL_AW-1:0] == TX_FIFO_THRESHOLD_REG_OFFSET)	? TX_FIFO_THRESHOLD_REG :
+			(last_HADDR[`AHBL_AW-1:0] == TX_FIFO_FLUSH_REG_OFFSET)	? TX_FIFO_FLUSH_REG :
+			(last_HADDR[`AHBL_AW-1:0] == IM_REG_OFFSET)	? IM_REG :
+			(last_HADDR[`AHBL_AW-1:0] == MIS_REG_OFFSET)	? MIS_REG :
+			(last_HADDR[`AHBL_AW-1:0] == RIS_REG_OFFSET)	? RIS_REG :
+			(last_HADDR[`AHBL_AW-1:0] == GCLK_REG_OFFSET)	? GCLK_REG :
+			32'hDEADBEEF;
+
+	assign	HREADYOUT = 1'b1;
+
+	assign	RXDATA_WIRE = rdata;
+	assign	rd = (ahbl_re & (last_HADDR[`AHBL_AW-1:0] == RXDATA_REG_OFFSET));
+	assign	wdata = HWDATA;
+	assign	wr = (ahbl_we & (last_HADDR[`AHBL_AW-1:0] == TXDATA_REG_OFFSET));
+endmodule
diff --git a/hdl/rtl/bus_wrappers/EF_UART_AHBL.pp.v b/hdl/rtl/bus_wrappers/EF_UART_AHBL.pp.v
deleted file mode 100644
index 475cfe1..0000000
--- a/hdl/rtl/bus_wrappers/EF_UART_AHBL.pp.v
+++ /dev/null
@@ -1,422 +0,0 @@
-/*
-	Copyright 2024 Efabless Corp.
-
-	Author: Mohamed Shalan (mshalan@efabless.com)
-
-	Licensed under the Apache License, Version 2.0 (the "License");
-	you may not use this file except in compliance with the License.
-	You may obtain a copy of the License at
-
-	    http://www.apache.org/licenses/LICENSE-2.0
-
-	Unless required by applicable law or agreed to in writing, software
-	distributed under the License is distributed on an "AS IS" BASIS,
-	WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-	See the License for the specific language governing permissions and
-	limitations under the License.
-
-*/
-
-/* THIS FILE IS GENERATED, DO NOT EDIT */
-
-`timescale			1ns/1ps
-`default_nettype	none
-
-
-
-/*
-	Copyright 2020 AUCOHL
-
-    Author: Mohamed Shalan (mshalan@aucegypt.edu)
-	
-	Licensed under the Apache License, Version 2.0 (the "License"); 
-	you may not use this file except in compliance with the License. 
-	You may obtain a copy of the License at:
-
-	http://www.apache.org/licenses/LICENSE-2.0
-
-	Unless required by applicable law or agreed to in writing, software 
-	distributed under the License is distributed on an "AS IS" BASIS, 
-	WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 
-	See the License for the specific language governing permissions and 
-	limitations under the License.
-*/
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-    
-
-
-
-
-
-
-                                                
-    
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-module EF_UART_AHBL #( 
-	parameter	
-		SC = 8,
-		MDW = 9,
-		GFLEN = 8,
-		FAW = 4
-) (
-
-
-
-
-	input wire          HCLK,
-                                        input wire          HRESETn,
-                                        input wire          HWRITE,
-                                        input wire [31:0]   HWDATA,
-                                        input wire [31:0]   HADDR,
-                                        input wire [1:0]    HTRANS,
-                                        input wire          HSEL,
-                                        input wire          HREADY,
-                                        output wire         HREADYOUT,
-                                        output wire [31:0]  HRDATA,
-                                        output wire         IRQ
-,
-	input	wire	[1-1:0]	rx,
-	output	wire	[1-1:0]	tx
-);
-
-	localparam	RXDATA_REG_OFFSET = 16'h0000;
-	localparam	TXDATA_REG_OFFSET = 16'h0004;
-	localparam	PR_REG_OFFSET = 16'h0008;
-	localparam	CTRL_REG_OFFSET = 16'h000C;
-	localparam	CFG_REG_OFFSET = 16'h0010;
-	localparam	MATCH_REG_OFFSET = 16'h001C;
-	localparam	RX_FIFO_LEVEL_REG_OFFSET = 16'hFE00;
-	localparam	RX_FIFO_THRESHOLD_REG_OFFSET = 16'hFE04;
-	localparam	RX_FIFO_FLUSH_REG_OFFSET = 16'hFE08;
-	localparam	TX_FIFO_LEVEL_REG_OFFSET = 16'hFE10;
-	localparam	TX_FIFO_THRESHOLD_REG_OFFSET = 16'hFE14;
-	localparam	TX_FIFO_FLUSH_REG_OFFSET = 16'hFE18;
-	localparam	IM_REG_OFFSET = 16'hFF00;
-	localparam	MIS_REG_OFFSET = 16'hFF04;
-	localparam	RIS_REG_OFFSET = 16'hFF08;
-	localparam	IC_REG_OFFSET = 16'hFF0C;
-
-    reg [0:0] GCLK_REG;
-    wire clk_g;
-    wire clk_gated_en = GCLK_REG[0];
-    ef_gating_cell clk_gate_cell(
-        
-
-
- // USE_POWER_PINS
-        .clk(HCLK),
-        .clk_en(clk_gated_en),
-        .clk_o(clk_g)
-    );
-    
-	wire		clk = clk_g;
-	wire		rst_n = HRESETn;
-
-
-	reg  last_HSEL, last_HWRITE; reg [31:0] last_HADDR; reg [1:0] last_HTRANS;
-                                        always@ (posedge HCLK or negedge HRESETn) begin
-					   if(~HRESETn) begin
-					       last_HSEL       <= 1'b0;
-					       last_HADDR      <= 1'b0;
-					       last_HWRITE     <= 1'b0;
-					       last_HTRANS     <= 1'b0;
-				            end else if(HREADY) begin
-                                                last_HSEL       <= HSEL;
-                                                last_HADDR      <= HADDR;
-                                                last_HWRITE     <= HWRITE;
-                                                last_HTRANS     <= HTRANS;
-                                            end
-                                        end
-                                        wire    ahbl_valid	= last_HSEL & last_HTRANS[1];
-	                                    wire	ahbl_we	= last_HWRITE & ahbl_valid;
-	                                    wire	ahbl_re	= ~last_HWRITE & ahbl_valid;
-
-	wire [16-1:0]	prescaler;
-	wire [1-1:0]	en;
-	wire [1-1:0]	tx_en;
-	wire [1-1:0]	rx_en;
-	wire [MDW-1:0]	wdata;
-	wire [6-1:0]	timeout_bits;
-	wire [1-1:0]	loopback_en;
-	wire [1-1:0]	glitch_filter_en;
-	wire [FAW-1:0]	tx_level;
-	wire [FAW-1:0]	rx_level;
-	wire [1-1:0]	rd;
-	wire [1-1:0]	wr;
-	wire [1-1:0]	tx_fifo_flush;
-	wire [1-1:0]	rx_fifo_flush;
-	wire [4-1:0]	data_size;
-	wire [1-1:0]	stop_bits_count;
-	wire [3-1:0]	parity_type;
-	wire [FAW-1:0]	txfifotr;
-	wire [FAW-1:0]	rxfifotr;
-	wire [MDW-1:0]	match_data;
-	wire [1-1:0]	tx_empty;
-	wire [1-1:0]	tx_full;
-	wire [1-1:0]	tx_level_below;
-	wire [MDW-1:0]	rdata;
-	wire [1-1:0]	rx_empty;
-	wire [1-1:0]	rx_full;
-	wire [1-1:0]	rx_level_above;
-	wire [1-1:0]	break_flag;
-	wire [1-1:0]	match_flag;
-	wire [1-1:0]	frame_error_flag;
-	wire [1-1:0]	parity_error_flag;
-	wire [1-1:0]	overrun_flag;
-	wire [1-1:0]	timeout_flag;
-
-	// Register Definitions
-	wire	[MDW-1:0]	RXDATA_WIRE;
-
-	wire	[MDW-1:0]	TXDATA_WIRE;
-
-	reg [15:0]	PR_REG;
-	assign	prescaler = PR_REG;
-	always @(posedge HCLK or negedge HRESETn) if(~HRESETn) PR_REG <= 0;
-                                        else if(ahbl_we & (last_HADDR[16-1:0]==PR_REG_OFFSET))
-                                            PR_REG <= HWDATA[16-1:0];
-
-	reg [4:0]	CTRL_REG;
-	assign	en	=	CTRL_REG[0 : 0];
-	assign	tx_en	=	CTRL_REG[1 : 1];
-	assign	rx_en	=	CTRL_REG[2 : 2];
-	assign	loopback_en	=	CTRL_REG[3 : 3];
-	assign	glitch_filter_en	=	CTRL_REG[4 : 4];
-	always @(posedge HCLK or negedge HRESETn) if(~HRESETn) CTRL_REG <= 0;
-                                        else if(ahbl_we & (last_HADDR[16-1:0]==CTRL_REG_OFFSET))
-                                            CTRL_REG <= HWDATA[5-1:0];
-
-	reg [13:0]	CFG_REG;
-	assign	data_size	=	CFG_REG[3 : 0];
-	assign	stop_bits_count	=	CFG_REG[4 : 4];
-	assign	parity_type	=	CFG_REG[7 : 5];
-	assign	timeout_bits	=	CFG_REG[13 : 8];
-	always @(posedge HCLK or negedge HRESETn) if(~HRESETn) CFG_REG <= 'h3F08;
-                                        else if(ahbl_we & (last_HADDR[16-1:0]==CFG_REG_OFFSET))
-                                            CFG_REG <= HWDATA[14-1:0];
-
-	reg [MDW-1:0]	MATCH_REG;
-	assign	match_data = MATCH_REG;
-	always @(posedge HCLK or negedge HRESETn) if(~HRESETn) MATCH_REG <= 0;
-                                        else if(ahbl_we & (last_HADDR[16-1:0]==MATCH_REG_OFFSET))
-                                            MATCH_REG <= HWDATA[MDW-1:0];
-
-	wire [FAW-1:0]	RX_FIFO_LEVEL_WIRE;
-	assign	RX_FIFO_LEVEL_WIRE[(FAW - 1) : 0] = rx_level;
-
-	reg [FAW-1:0]	RX_FIFO_THRESHOLD_REG;
-	assign	rxfifotr	=	RX_FIFO_THRESHOLD_REG[(FAW - 1) : 0];
-	always @(posedge HCLK or negedge HRESETn) if(~HRESETn) RX_FIFO_THRESHOLD_REG <= 0;
-                                        else if(ahbl_we & (last_HADDR[16-1:0]==RX_FIFO_THRESHOLD_REG_OFFSET))
-                                            RX_FIFO_THRESHOLD_REG <= HWDATA[FAW-1:0];
-
-	reg [0:0]	RX_FIFO_FLUSH_REG;
-	assign	rx_fifo_flush	=	RX_FIFO_FLUSH_REG[0 : 0];
-	always @(posedge HCLK or negedge HRESETn) if(~HRESETn) RX_FIFO_FLUSH_REG <= 0;
-                                                else if(ahbl_we & (last_HADDR[16-1:0]==RX_FIFO_FLUSH_REG_OFFSET))
-                                                    RX_FIFO_FLUSH_REG <= HWDATA[1-1:0];
-                                                else
-                                                    RX_FIFO_FLUSH_REG <= 1'h0 & RX_FIFO_FLUSH_REG;
-
-	wire [FAW-1:0]	TX_FIFO_LEVEL_WIRE;
-	assign	TX_FIFO_LEVEL_WIRE[(FAW - 1) : 0] = tx_level;
-
-	reg [FAW-1:0]	TX_FIFO_THRESHOLD_REG;
-	assign	txfifotr	=	TX_FIFO_THRESHOLD_REG[(FAW - 1) : 0];
-	always @(posedge HCLK or negedge HRESETn) if(~HRESETn) TX_FIFO_THRESHOLD_REG <= 0;
-                                        else if(ahbl_we & (last_HADDR[16-1:0]==TX_FIFO_THRESHOLD_REG_OFFSET))
-                                            TX_FIFO_THRESHOLD_REG <= HWDATA[FAW-1:0];
-
-	reg [0:0]	TX_FIFO_FLUSH_REG;
-	assign	tx_fifo_flush	=	TX_FIFO_FLUSH_REG[0 : 0];
-	always @(posedge HCLK or negedge HRESETn) if(~HRESETn) TX_FIFO_FLUSH_REG <= 0;
-                                                else if(ahbl_we & (last_HADDR[16-1:0]==TX_FIFO_FLUSH_REG_OFFSET))
-                                                    TX_FIFO_FLUSH_REG <= HWDATA[1-1:0];
-                                                else
-                                                    TX_FIFO_FLUSH_REG <= 1'h0 & TX_FIFO_FLUSH_REG;
-
-	localparam	GCLK_REG_OFFSET = 16'hFF10;
-	always @(posedge HCLK or negedge HRESETn) if(~HRESETn) GCLK_REG <= 0;
-                                        else if(ahbl_we & (last_HADDR[16-1:0]==GCLK_REG_OFFSET))
-                                            GCLK_REG <= HWDATA[1-1:0];
-
-	reg [9:0] IM_REG;
-	reg [9:0] IC_REG;
-	reg [9:0] RIS_REG;
-
-	wire[10-1:0]      MIS_REG	= RIS_REG & IM_REG;
-	always @(posedge HCLK or negedge HRESETn) if(~HRESETn) IM_REG <= 0;
-                                        else if(ahbl_we & (last_HADDR[16-1:0]==IM_REG_OFFSET))
-                                            IM_REG <= HWDATA[10-1:0];
-	always @(posedge HCLK or negedge HRESETn) if(~HRESETn) IC_REG <= 10'b0;
-                                        else if(ahbl_we & (last_HADDR[16-1:0]==IC_REG_OFFSET))
-                                            IC_REG <= HWDATA[10-1:0];
-                                        else IC_REG <= 10'd0;
-
-	wire [0:0] TXE = tx_empty;
-	wire [0:0] RXF = rx_full;
-	wire [0:0] TXB = tx_level_below;
-	wire [0:0] RXA = rx_level_above;
-	wire [0:0] BRK = break_flag;
-	wire [0:0] MATCH = match_flag;
-	wire [0:0] FE = frame_error_flag;
-	wire [0:0] PRE = parity_error_flag;
-	wire [0:0] OR = overrun_flag;
-	wire [0:0] RTO = timeout_flag;
-
-
-	integer _i_;
-	always @(posedge HCLK or negedge HRESETn) if(~HRESETn) RIS_REG <= 0; else begin
-		for(_i_ = 0; _i_ < 1; _i_ = _i_ + 1) begin
-			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(TXE[_i_ - 0] == 1'b1) RIS_REG[_i_] <= 1'b1;
-		end
-		for(_i_ = 1; _i_ < 2; _i_ = _i_ + 1) begin
-			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(RXF[_i_ - 1] == 1'b1) RIS_REG[_i_] <= 1'b1;
-		end
-		for(_i_ = 2; _i_ < 3; _i_ = _i_ + 1) begin
-			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(TXB[_i_ - 2] == 1'b1) RIS_REG[_i_] <= 1'b1;
-		end
-		for(_i_ = 3; _i_ < 4; _i_ = _i_ + 1) begin
-			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(RXA[_i_ - 3] == 1'b1) RIS_REG[_i_] <= 1'b1;
-		end
-		for(_i_ = 4; _i_ < 5; _i_ = _i_ + 1) begin
-			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(BRK[_i_ - 4] == 1'b1) RIS_REG[_i_] <= 1'b1;
-		end
-		for(_i_ = 5; _i_ < 6; _i_ = _i_ + 1) begin
-			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(MATCH[_i_ - 5] == 1'b1) RIS_REG[_i_] <= 1'b1;
-		end
-		for(_i_ = 6; _i_ < 7; _i_ = _i_ + 1) begin
-			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(FE[_i_ - 6] == 1'b1) RIS_REG[_i_] <= 1'b1;
-		end
-		for(_i_ = 7; _i_ < 8; _i_ = _i_ + 1) begin
-			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(PRE[_i_ - 7] == 1'b1) RIS_REG[_i_] <= 1'b1;
-		end
-		for(_i_ = 8; _i_ < 9; _i_ = _i_ + 1) begin
-			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(OR[_i_ - 8] == 1'b1) RIS_REG[_i_] <= 1'b1;
-		end
-		for(_i_ = 9; _i_ < 10; _i_ = _i_ + 1) begin
-			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(RTO[_i_ - 9] == 1'b1) RIS_REG[_i_] <= 1'b1;
-		end
-	end
-
-	assign IRQ = |MIS_REG;
-
-	EF_UART #(
-		.SC(SC),
-		.MDW(MDW),
-		.GFLEN(GFLEN),
-		.FAW(FAW)
-	) instance_to_wrap (
-		.clk(clk),
-		.rst_n(rst_n),
-		.prescaler(prescaler),
-		.en(en),
-		.tx_en(tx_en),
-		.rx_en(rx_en),
-		.wdata(wdata),
-		.timeout_bits(timeout_bits),
-		.loopback_en(loopback_en),
-		.glitch_filter_en(glitch_filter_en),
-		.tx_level(tx_level),
-		.rx_level(rx_level),
-		.rd(rd),
-		.wr(wr),
-		.tx_fifo_flush(tx_fifo_flush),
-		.rx_fifo_flush(rx_fifo_flush),
-		.data_size(data_size),
-		.stop_bits_count(stop_bits_count),
-		.parity_type(parity_type),
-		.txfifotr(txfifotr),
-		.rxfifotr(rxfifotr),
-		.match_data(match_data),
-		.tx_empty(tx_empty),
-		.tx_full(tx_full),
-		.tx_level_below(tx_level_below),
-		.rdata(rdata),
-		.rx_empty(rx_empty),
-		.rx_full(rx_full),
-		.rx_level_above(rx_level_above),
-		.break_flag(break_flag),
-		.match_flag(match_flag),
-		.frame_error_flag(frame_error_flag),
-		.parity_error_flag(parity_error_flag),
-		.overrun_flag(overrun_flag),
-		.timeout_flag(timeout_flag),
-		.rx(rx),
-		.tx(tx)
-	);
-
-	assign	HRDATA = 
-			(last_HADDR[16-1:0] == RXDATA_REG_OFFSET)	? RXDATA_WIRE :
-			(last_HADDR[16-1:0] == TXDATA_REG_OFFSET)	? TXDATA_WIRE :
-			(last_HADDR[16-1:0] == PR_REG_OFFSET)	? PR_REG :
-			(last_HADDR[16-1:0] == CTRL_REG_OFFSET)	? CTRL_REG :
-			(last_HADDR[16-1:0] == CFG_REG_OFFSET)	? CFG_REG :
-			(last_HADDR[16-1:0] == MATCH_REG_OFFSET)	? MATCH_REG :
-			(last_HADDR[16-1:0] == RX_FIFO_LEVEL_REG_OFFSET)	? RX_FIFO_LEVEL_WIRE :
-			(last_HADDR[16-1:0] == RX_FIFO_THRESHOLD_REG_OFFSET)	? RX_FIFO_THRESHOLD_REG :
-			(last_HADDR[16-1:0] == RX_FIFO_FLUSH_REG_OFFSET)	? RX_FIFO_FLUSH_REG :
-			(last_HADDR[16-1:0] == TX_FIFO_LEVEL_REG_OFFSET)	? TX_FIFO_LEVEL_WIRE :
-			(last_HADDR[16-1:0] == TX_FIFO_THRESHOLD_REG_OFFSET)	? TX_FIFO_THRESHOLD_REG :
-			(last_HADDR[16-1:0] == TX_FIFO_FLUSH_REG_OFFSET)	? TX_FIFO_FLUSH_REG :
-			(last_HADDR[16-1:0] == IM_REG_OFFSET)	? IM_REG :
-			(last_HADDR[16-1:0] == MIS_REG_OFFSET)	? MIS_REG :
-			(last_HADDR[16-1:0] == RIS_REG_OFFSET)	? RIS_REG :
-			(last_HADDR[16-1:0] == IC_REG_OFFSET)	? IC_REG :
-			(last_HADDR[16-1:0] == GCLK_REG_OFFSET)	? GCLK_REG :
-			32'hDEADBEEF;
-
-	assign	HREADYOUT = 1'b1;
-
-	assign	RXDATA_WIRE = rdata;
-	assign	rd = (ahbl_re & (last_HADDR[16-1:0] == RXDATA_REG_OFFSET));
-	assign	wdata = HWDATA;
-	assign	wr = (ahbl_we & (last_HADDR[16-1:0] == TXDATA_REG_OFFSET));
-endmodule
diff --git a/hdl/rtl/bus_wrappers/EF_UART_AHBL.v b/hdl/rtl/bus_wrappers/EF_UART_AHBL.v
index 5964d81..7d0e3b9 100644
--- a/hdl/rtl/bus_wrappers/EF_UART_AHBL.v
+++ b/hdl/rtl/bus_wrappers/EF_UART_AHBL.v
@@ -19,277 +19,416 @@
 
 /* THIS FILE IS GENERATED, DO NOT EDIT */
 
-`timescale			1ns/1ps
-`default_nettype	none
+`timescale 1ns / 1ps `default_nettype none
 
-`define				AHBL_AW		16
 
-`include			"ahbl_wrapper.vh"
 
-module EF_UART_AHBL #( 
-	parameter	
-		SC = 8,
-		MDW = 9,
-		GFLEN = 8,
-		FAW = 4
+/*
+	Copyright 2020 AUCOHL
+
+    Author: Mohamed Shalan (mshalan@aucegypt.edu)
+	
+	Licensed under the Apache License, Version 2.0 (the "License"); 
+	you may not use this file except in compliance with the License. 
+	You may obtain a copy of the License at:
+
+	http://www.apache.org/licenses/LICENSE-2.0
+
+	Unless required by applicable law or agreed to in writing, software 
+	distributed under the License is distributed on an "AS IS" BASIS, 
+	WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 
+	See the License for the specific language governing permissions and 
+	limitations under the License.
+*/
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+module EF_UART_AHBL #(
+    parameter SC = 8,
+    MDW = 9,
+    GFLEN = 8,
+    FAW = 4
 ) (
-`ifdef USE_POWER_PINS
-	inout VPWR,
-	inout VGND,
-`endif
-	`AHBL_SLAVE_PORTS,
-	input	wire	[1-1:0]	rx,
-	output	wire	[1-1:0]	tx
+
+
+
+
+    input  wire         HCLK,
+    input  wire         HRESETn,
+    input  wire         HWRITE,
+    input  wire [ 31:0] HWDATA,
+    input  wire [ 31:0] HADDR,
+    input  wire [  1:0] HTRANS,
+    input  wire         HSEL,
+    input  wire         HREADY,
+    output wire         HREADYOUT,
+    output wire [ 31:0] HRDATA,
+    output wire         IRQ,
+    input  wire [1-1:0] rx,
+    output wire [1-1:0] tx
 );
 
-	localparam	RXDATA_REG_OFFSET = `AHBL_AW'h0000;
-	localparam	TXDATA_REG_OFFSET = `AHBL_AW'h0004;
-	localparam	PR_REG_OFFSET = `AHBL_AW'h0008;
-	localparam	CTRL_REG_OFFSET = `AHBL_AW'h000C;
-	localparam	CFG_REG_OFFSET = `AHBL_AW'h0010;
-	localparam	MATCH_REG_OFFSET = `AHBL_AW'h001C;
-	localparam	RX_FIFO_LEVEL_REG_OFFSET = `AHBL_AW'hFE00;
-	localparam	RX_FIFO_THRESHOLD_REG_OFFSET = `AHBL_AW'hFE04;
-	localparam	RX_FIFO_FLUSH_REG_OFFSET = `AHBL_AW'hFE08;
-	localparam	TX_FIFO_LEVEL_REG_OFFSET = `AHBL_AW'hFE10;
-	localparam	TX_FIFO_THRESHOLD_REG_OFFSET = `AHBL_AW'hFE14;
-	localparam	TX_FIFO_FLUSH_REG_OFFSET = `AHBL_AW'hFE18;
-	localparam	IM_REG_OFFSET = `AHBL_AW'hFF00;
-	localparam	MIS_REG_OFFSET = `AHBL_AW'hFF04;
-	localparam	RIS_REG_OFFSET = `AHBL_AW'hFF08;
-	localparam	IC_REG_OFFSET = `AHBL_AW'hFF0C;
-
-    reg [0:0] GCLK_REG;
-    wire clk_g;
-    wire clk_gated_en = GCLK_REG[0];
-    ef_gating_cell clk_gate_cell(
-        `ifdef USE_POWER_PINS 
-        .vpwr(VPWR),
-        .vgnd(VGND),
-        `endif // USE_POWER_PINS
-        .clk(HCLK),
-        .clk_en(clk_gated_en),
-        .clk_o(clk_g)
-    )
-    
-	wire		clk = clk_g;
-	wire		rst_n = HRESETn;
-
-
-	`AHBL_CTRL_SIGNALS
-
-	wire [16-1:0]	prescaler;
-	wire [1-1:0]	en;
-	wire [1-1:0]	tx_en;
-	wire [1-1:0]	rx_en;
-	wire [MDW-1:0]	wdata;
-	wire [6-1:0]	timeout_bits;
-	wire [1-1:0]	loopback_en;
-	wire [1-1:0]	glitch_filter_en;
-	wire [FAW-1:0]	tx_level;
-	wire [FAW-1:0]	rx_level;
-	wire [1-1:0]	rd;
-	wire [1-1:0]	wr;
-	wire [1-1:0]	tx_fifo_flush;
-	wire [1-1:0]	rx_fifo_flush;
-	wire [4-1:0]	data_size;
-	wire [1-1:0]	stop_bits_count;
-	wire [3-1:0]	parity_type;
-	wire [FAW-1:0]	txfifotr;
-	wire [FAW-1:0]	rxfifotr;
-	wire [MDW-1:0]	match_data;
-	wire [1-1:0]	tx_empty;
-	wire [1-1:0]	tx_full;
-	wire [1-1:0]	tx_level_below;
-	wire [MDW-1:0]	rdata;
-	wire [1-1:0]	rx_empty;
-	wire [1-1:0]	rx_full;
-	wire [1-1:0]	rx_level_above;
-	wire [1-1:0]	break_flag;
-	wire [1-1:0]	match_flag;
-	wire [1-1:0]	frame_error_flag;
-	wire [1-1:0]	parity_error_flag;
-	wire [1-1:0]	overrun_flag;
-	wire [1-1:0]	timeout_flag;
-
-	// Register Definitions
-	wire	[MDW-1:0]	RXDATA_WIRE;
-
-	wire	[MDW-1:0]	TXDATA_WIRE;
-
-	reg [15:0]	PR_REG;
-	assign	prescaler = PR_REG;
-	`AHBL_REG(PR_REG, 0, 16)
-
-	reg [4:0]	CTRL_REG;
-	assign	en	=	CTRL_REG[0 : 0];
-	assign	tx_en	=	CTRL_REG[1 : 1];
-	assign	rx_en	=	CTRL_REG[2 : 2];
-	assign	loopback_en	=	CTRL_REG[3 : 3];
-	assign	glitch_filter_en	=	CTRL_REG[4 : 4];
-	`AHBL_REG(CTRL_REG, 0, 5)
-
-	reg [13:0]	CFG_REG;
-	assign	data_size	=	CFG_REG[3 : 0];
-	assign	stop_bits_count	=	CFG_REG[4 : 4];
-	assign	parity_type	=	CFG_REG[7 : 5];
-	assign	timeout_bits	=	CFG_REG[13 : 8];
-	`AHBL_REG(CFG_REG, 'h3F08, 14)
-
-	reg [MDW-1:0]	MATCH_REG;
-	assign	match_data = MATCH_REG;
-	`AHBL_REG(MATCH_REG, 0, MDW)
-
-	wire [FAW-1:0]	RX_FIFO_LEVEL_WIRE;
-	assign	RX_FIFO_LEVEL_WIRE[(FAW - 1) : 0] = rx_level;
-
-	reg [FAW-1:0]	RX_FIFO_THRESHOLD_REG;
-	assign	rxfifotr	=	RX_FIFO_THRESHOLD_REG[(FAW - 1) : 0];
-	`AHBL_REG(RX_FIFO_THRESHOLD_REG, 0, FAW)
-
-	reg [0:0]	RX_FIFO_FLUSH_REG;
-	assign	rx_fifo_flush	=	RX_FIFO_FLUSH_REG[0 : 0];
-	`AHBL_REG_AC(RX_FIFO_FLUSH_REG, 0, 1, 1'h0)
-
-	wire [FAW-1:0]	TX_FIFO_LEVEL_WIRE;
-	assign	TX_FIFO_LEVEL_WIRE[(FAW - 1) : 0] = tx_level;
-
-	reg [FAW-1:0]	TX_FIFO_THRESHOLD_REG;
-	assign	txfifotr	=	TX_FIFO_THRESHOLD_REG[(FAW - 1) : 0];
-	`AHBL_REG(TX_FIFO_THRESHOLD_REG, 0, FAW)
-
-	reg [0:0]	TX_FIFO_FLUSH_REG;
-	assign	tx_fifo_flush	=	TX_FIFO_FLUSH_REG[0 : 0];
-	`AHBL_REG_AC(TX_FIFO_FLUSH_REG, 0, 1, 1'h0)
-
-	localparam	GCLK_REG_OFFSET = `AHBL_AW'hFF10;
-	`AHBL_REG(GCLK_REG, 0, 1)
-
-	reg [9:0] IM_REG;
-	reg [9:0] IC_REG;
-	reg [9:0] RIS_REG;
-
-	`AHBL_MIS_REG(10)
-	`AHBL_REG(IM_REG, 0, 10)
-	`AHBL_IC_REG(10)
-
-	wire [0:0] TXE = tx_empty;
-	wire [0:0] RXF = rx_full;
-	wire [0:0] TXB = tx_level_below;
-	wire [0:0] RXA = rx_level_above;
-	wire [0:0] BRK = break_flag;
-	wire [0:0] MATCH = match_flag;
-	wire [0:0] FE = frame_error_flag;
-	wire [0:0] PRE = parity_error_flag;
-	wire [0:0] OR = overrun_flag;
-	wire [0:0] RTO = timeout_flag;
-
-
-	integer _i_;
-	`AHBL_BLOCK(RIS_REG, 0) else begin
-		for(_i_ = 0; _i_ < 1; _i_ = _i_ + 1) begin
-			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(TXE[_i_ - 0] == 1'b1) RIS_REG[_i_] <= 1'b1;
-		end
-		for(_i_ = 1; _i_ < 2; _i_ = _i_ + 1) begin
-			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(RXF[_i_ - 1] == 1'b1) RIS_REG[_i_] <= 1'b1;
-		end
-		for(_i_ = 2; _i_ < 3; _i_ = _i_ + 1) begin
-			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(TXB[_i_ - 2] == 1'b1) RIS_REG[_i_] <= 1'b1;
-		end
-		for(_i_ = 3; _i_ < 4; _i_ = _i_ + 1) begin
-			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(RXA[_i_ - 3] == 1'b1) RIS_REG[_i_] <= 1'b1;
-		end
-		for(_i_ = 4; _i_ < 5; _i_ = _i_ + 1) begin
-			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(BRK[_i_ - 4] == 1'b1) RIS_REG[_i_] <= 1'b1;
-		end
-		for(_i_ = 5; _i_ < 6; _i_ = _i_ + 1) begin
-			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(MATCH[_i_ - 5] == 1'b1) RIS_REG[_i_] <= 1'b1;
-		end
-		for(_i_ = 6; _i_ < 7; _i_ = _i_ + 1) begin
-			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(FE[_i_ - 6] == 1'b1) RIS_REG[_i_] <= 1'b1;
-		end
-		for(_i_ = 7; _i_ < 8; _i_ = _i_ + 1) begin
-			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(PRE[_i_ - 7] == 1'b1) RIS_REG[_i_] <= 1'b1;
-		end
-		for(_i_ = 8; _i_ < 9; _i_ = _i_ + 1) begin
-			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(OR[_i_ - 8] == 1'b1) RIS_REG[_i_] <= 1'b1;
-		end
-		for(_i_ = 9; _i_ < 10; _i_ = _i_ + 1) begin
-			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(RTO[_i_ - 9] == 1'b1) RIS_REG[_i_] <= 1'b1;
-		end
-	end
-
-	assign IRQ = |MIS_REG;
-
-	EF_UART #(
-		.SC(SC),
-		.MDW(MDW),
-		.GFLEN(GFLEN),
-		.FAW(FAW)
-	) instance_to_wrap (
-		.clk(clk),
-		.rst_n(rst_n),
-		.prescaler(prescaler),
-		.en(en),
-		.tx_en(tx_en),
-		.rx_en(rx_en),
-		.wdata(wdata),
-		.timeout_bits(timeout_bits),
-		.loopback_en(loopback_en),
-		.glitch_filter_en(glitch_filter_en),
-		.tx_level(tx_level),
-		.rx_level(rx_level),
-		.rd(rd),
-		.wr(wr),
-		.tx_fifo_flush(tx_fifo_flush),
-		.rx_fifo_flush(rx_fifo_flush),
-		.data_size(data_size),
-		.stop_bits_count(stop_bits_count),
-		.parity_type(parity_type),
-		.txfifotr(txfifotr),
-		.rxfifotr(rxfifotr),
-		.match_data(match_data),
-		.tx_empty(tx_empty),
-		.tx_full(tx_full),
-		.tx_level_below(tx_level_below),
-		.rdata(rdata),
-		.rx_empty(rx_empty),
-		.rx_full(rx_full),
-		.rx_level_above(rx_level_above),
-		.break_flag(break_flag),
-		.match_flag(match_flag),
-		.frame_error_flag(frame_error_flag),
-		.parity_error_flag(parity_error_flag),
-		.overrun_flag(overrun_flag),
-		.timeout_flag(timeout_flag),
-		.rx(rx),
-		.tx(tx)
-	);
-
-	assign	HRDATA = 
-			(last_HADDR[`AHBL_AW-1:0] == RXDATA_REG_OFFSET)	? RXDATA_WIRE :
-			(last_HADDR[`AHBL_AW-1:0] == TXDATA_REG_OFFSET)	? TXDATA_WIRE :
-			(last_HADDR[`AHBL_AW-1:0] == PR_REG_OFFSET)	? PR_REG :
-			(last_HADDR[`AHBL_AW-1:0] == CTRL_REG_OFFSET)	? CTRL_REG :
-			(last_HADDR[`AHBL_AW-1:0] == CFG_REG_OFFSET)	? CFG_REG :
-			(last_HADDR[`AHBL_AW-1:0] == MATCH_REG_OFFSET)	? MATCH_REG :
-			(last_HADDR[`AHBL_AW-1:0] == RX_FIFO_LEVEL_REG_OFFSET)	? RX_FIFO_LEVEL_WIRE :
-			(last_HADDR[`AHBL_AW-1:0] == RX_FIFO_THRESHOLD_REG_OFFSET)	? RX_FIFO_THRESHOLD_REG :
-			(last_HADDR[`AHBL_AW-1:0] == RX_FIFO_FLUSH_REG_OFFSET)	? RX_FIFO_FLUSH_REG :
-			(last_HADDR[`AHBL_AW-1:0] == TX_FIFO_LEVEL_REG_OFFSET)	? TX_FIFO_LEVEL_WIRE :
-			(last_HADDR[`AHBL_AW-1:0] == TX_FIFO_THRESHOLD_REG_OFFSET)	? TX_FIFO_THRESHOLD_REG :
-			(last_HADDR[`AHBL_AW-1:0] == TX_FIFO_FLUSH_REG_OFFSET)	? TX_FIFO_FLUSH_REG :
-			(last_HADDR[`AHBL_AW-1:0] == IM_REG_OFFSET)	? IM_REG :
-			(last_HADDR[`AHBL_AW-1:0] == MIS_REG_OFFSET)	? MIS_REG :
-			(last_HADDR[`AHBL_AW-1:0] == RIS_REG_OFFSET)	? RIS_REG :
-			(last_HADDR[`AHBL_AW-1:0] == IC_REG_OFFSET)	? IC_REG :
-			(last_HADDR[`AHBL_AW-1:0] == GCLK_REG_OFFSET)	? GCLK_REG :
+  localparam RXDATA_REG_OFFSET = 16'h0000;
+  localparam TXDATA_REG_OFFSET = 16'h0004;
+  localparam PR_REG_OFFSET = 16'h0008;
+  localparam CTRL_REG_OFFSET = 16'h000C;
+  localparam CFG_REG_OFFSET = 16'h0010;
+  localparam MATCH_REG_OFFSET = 16'h001C;
+  localparam RX_FIFO_LEVEL_REG_OFFSET = 16'hFE00;
+  localparam RX_FIFO_THRESHOLD_REG_OFFSET = 16'hFE04;
+  localparam RX_FIFO_FLUSH_REG_OFFSET = 16'hFE08;
+  localparam TX_FIFO_LEVEL_REG_OFFSET = 16'hFE10;
+  localparam TX_FIFO_THRESHOLD_REG_OFFSET = 16'hFE14;
+  localparam TX_FIFO_FLUSH_REG_OFFSET = 16'hFE18;
+  localparam IM_REG_OFFSET = 16'hFF00;
+  localparam MIS_REG_OFFSET = 16'hFF04;
+  localparam RIS_REG_OFFSET = 16'hFF08;
+  localparam IC_REG_OFFSET = 16'hFF0C;
+
+  reg [0:0] GCLK_REG;
+  wire clk_g;
+  wire clk_gated_en = GCLK_REG[0];
+  ef_util_gating_cell clk_gate_cell (
+
+
+
+      // USE_POWER_PINS
+      .clk(HCLK),
+      .clk_en(clk_gated_en),
+      .clk_o(clk_g)
+  );
+
+  wire clk = clk_g;
+  wire rst_n = HRESETn;
+
+
+  reg last_HSEL, last_HWRITE;
+  reg [31:0] last_HADDR;
+  reg [ 1:0] last_HTRANS;
+  always @(posedge HCLK or negedge HRESETn) begin
+    if (~HRESETn) begin
+      last_HSEL   <= 1'b0;
+      last_HADDR  <= 1'b0;
+      last_HWRITE <= 1'b0;
+      last_HTRANS <= 1'b0;
+    end else if (HREADY) begin
+      last_HSEL   <= HSEL;
+      last_HADDR  <= HADDR;
+      last_HWRITE <= HWRITE;
+      last_HTRANS <= HTRANS;
+    end
+  end
+  wire    ahbl_valid = last_HSEL & last_HTRANS[1];
+  wire ahbl_we = last_HWRITE & ahbl_valid;
+  wire ahbl_re = ~last_HWRITE & ahbl_valid;
+
+  wire [16-1:0] prescaler;
+  wire [1-1:0] en;
+  wire [1-1:0] tx_en;
+  wire [1-1:0] rx_en;
+  wire [MDW-1:0] wdata;
+  wire [6-1:0] timeout_bits;
+  wire [1-1:0] loopback_en;
+  wire [1-1:0] glitch_filter_en;
+  wire [FAW-1:0] tx_level;
+  wire [FAW-1:0] rx_level;
+  wire [1-1:0] rd;
+  wire [1-1:0] wr;
+  wire [1-1:0] tx_fifo_flush;
+  wire [1-1:0] rx_fifo_flush;
+  wire [4-1:0] data_size;
+  wire [1-1:0] stop_bits_count;
+  wire [3-1:0] parity_type;
+  wire [FAW-1:0] txfifotr;
+  wire [FAW-1:0] rxfifotr;
+  wire [MDW-1:0] match_data;
+  wire [1-1:0] tx_empty;
+  wire [1-1:0] tx_full;
+  wire [1-1:0] tx_level_below;
+  wire [MDW-1:0] rdata;
+  wire [1-1:0] rx_empty;
+  wire [1-1:0] rx_full;
+  wire [1-1:0] rx_level_above;
+  wire [1-1:0] break_flag;
+  wire [1-1:0] match_flag;
+  wire [1-1:0] frame_error_flag;
+  wire [1-1:0] parity_error_flag;
+  wire [1-1:0] overrun_flag;
+  wire [1-1:0] timeout_flag;
+
+  // Register Definitions
+  wire [MDW-1:0] RXDATA_WIRE;
+
+  wire [MDW-1:0] TXDATA_WIRE;
+
+  reg [15:0] PR_REG;
+  assign prescaler = PR_REG;
+  always @(posedge HCLK or negedge HRESETn)
+    if (~HRESETn) PR_REG <= 0;
+    else if (ahbl_we & (last_HADDR[16-1:0] == PR_REG_OFFSET)) PR_REG <= HWDATA[16-1:0];
+
+  reg [4:0] CTRL_REG;
+  assign en = CTRL_REG[0 : 0];
+  assign tx_en = CTRL_REG[1 : 1];
+  assign rx_en = CTRL_REG[2 : 2];
+  assign loopback_en = CTRL_REG[3 : 3];
+  assign glitch_filter_en = CTRL_REG[4 : 4];
+  always @(posedge HCLK or negedge HRESETn)
+    if (~HRESETn) CTRL_REG <= 0;
+    else if (ahbl_we & (last_HADDR[16-1:0] == CTRL_REG_OFFSET)) CTRL_REG <= HWDATA[5-1:0];
+
+  reg [13:0] CFG_REG;
+  assign data_size = CFG_REG[3 : 0];
+  assign stop_bits_count = CFG_REG[4 : 4];
+  assign parity_type = CFG_REG[7 : 5];
+  assign timeout_bits = CFG_REG[13 : 8];
+  always @(posedge HCLK or negedge HRESETn)
+    if (~HRESETn) CFG_REG <= 'h3F08;
+    else if (ahbl_we & (last_HADDR[16-1:0] == CFG_REG_OFFSET)) CFG_REG <= HWDATA[14-1:0];
+
+  reg [MDW-1:0] MATCH_REG;
+  assign match_data = MATCH_REG;
+  always @(posedge HCLK or negedge HRESETn)
+    if (~HRESETn) MATCH_REG <= 0;
+    else if (ahbl_we & (last_HADDR[16-1:0] == MATCH_REG_OFFSET)) MATCH_REG <= HWDATA[MDW-1:0];
+
+  wire [FAW-1:0] RX_FIFO_LEVEL_WIRE;
+  assign RX_FIFO_LEVEL_WIRE[(FAW-1) : 0] = rx_level;
+
+  reg [FAW-1:0] RX_FIFO_THRESHOLD_REG;
+  assign rxfifotr = RX_FIFO_THRESHOLD_REG[(FAW-1) : 0];
+  always @(posedge HCLK or negedge HRESETn)
+    if (~HRESETn) RX_FIFO_THRESHOLD_REG <= 0;
+    else if (ahbl_we & (last_HADDR[16-1:0] == RX_FIFO_THRESHOLD_REG_OFFSET))
+      RX_FIFO_THRESHOLD_REG <= HWDATA[FAW-1:0];
+
+  reg [0:0] RX_FIFO_FLUSH_REG;
+  assign rx_fifo_flush = RX_FIFO_FLUSH_REG[0 : 0];
+  always @(posedge HCLK or negedge HRESETn)
+    if (~HRESETn) RX_FIFO_FLUSH_REG <= 0;
+    else if (ahbl_we & (last_HADDR[16-1:0] == RX_FIFO_FLUSH_REG_OFFSET))
+      RX_FIFO_FLUSH_REG <= HWDATA[1-1:0];
+    else RX_FIFO_FLUSH_REG <= 1'h0 & RX_FIFO_FLUSH_REG;
+
+  wire [FAW-1:0] TX_FIFO_LEVEL_WIRE;
+  assign TX_FIFO_LEVEL_WIRE[(FAW-1) : 0] = tx_level;
+
+  reg [FAW-1:0] TX_FIFO_THRESHOLD_REG;
+  assign txfifotr = TX_FIFO_THRESHOLD_REG[(FAW-1) : 0];
+  always @(posedge HCLK or negedge HRESETn)
+    if (~HRESETn) TX_FIFO_THRESHOLD_REG <= 0;
+    else if (ahbl_we & (last_HADDR[16-1:0] == TX_FIFO_THRESHOLD_REG_OFFSET))
+      TX_FIFO_THRESHOLD_REG <= HWDATA[FAW-1:0];
+
+  reg [0:0] TX_FIFO_FLUSH_REG;
+  assign tx_fifo_flush = TX_FIFO_FLUSH_REG[0 : 0];
+  always @(posedge HCLK or negedge HRESETn)
+    if (~HRESETn) TX_FIFO_FLUSH_REG <= 0;
+    else if (ahbl_we & (last_HADDR[16-1:0] == TX_FIFO_FLUSH_REG_OFFSET))
+      TX_FIFO_FLUSH_REG <= HWDATA[1-1:0];
+    else TX_FIFO_FLUSH_REG <= 1'h0 & TX_FIFO_FLUSH_REG;
+
+  localparam GCLK_REG_OFFSET = 16'hFF10;
+  always @(posedge HCLK or negedge HRESETn)
+    if (~HRESETn) GCLK_REG <= 0;
+    else if (ahbl_we & (last_HADDR[16-1:0] == GCLK_REG_OFFSET)) GCLK_REG <= HWDATA[1-1:0];
+
+  reg  [   9:0] IM_REG;
+  reg  [   9:0] IC_REG;
+  reg  [   9:0] RIS_REG;
+
+  wire [10-1:0] MIS_REG = RIS_REG & IM_REG;
+  always @(posedge HCLK or negedge HRESETn)
+    if (~HRESETn) IM_REG <= 0;
+    else if (ahbl_we & (last_HADDR[16-1:0] == IM_REG_OFFSET)) IM_REG <= HWDATA[10-1:0];
+  always @(posedge HCLK or negedge HRESETn)
+    if (~HRESETn) IC_REG <= 10'b0;
+    else if (ahbl_we & (last_HADDR[16-1:0] == IC_REG_OFFSET)) IC_REG <= HWDATA[10-1:0];
+    else IC_REG <= 10'd0;
+
+  wire [0:0] TXE = tx_empty;
+  wire [0:0] RXF = rx_full;
+  wire [0:0] TXB = tx_level_below;
+  wire [0:0] RXA = rx_level_above;
+  wire [0:0] BRK = break_flag;
+  wire [0:0] MATCH = match_flag;
+  wire [0:0] FE = frame_error_flag;
+  wire [0:0] PRE = parity_error_flag;
+  wire [0:0] OR = overrun_flag;
+  wire [0:0] RTO = timeout_flag;
+
+
+  integer _i_;
+  always @(posedge HCLK or negedge HRESETn)
+    if (~HRESETn) RIS_REG <= 0;
+    else begin
+      for (_i_ = 0; _i_ < 1; _i_ = _i_ + 1) begin
+        if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+        else if (TXE[_i_-0] == 1'b1) RIS_REG[_i_] <= 1'b1;
+      end
+      for (_i_ = 1; _i_ < 2; _i_ = _i_ + 1) begin
+        if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+        else if (RXF[_i_-1] == 1'b1) RIS_REG[_i_] <= 1'b1;
+      end
+      for (_i_ = 2; _i_ < 3; _i_ = _i_ + 1) begin
+        if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+        else if (TXB[_i_-2] == 1'b1) RIS_REG[_i_] <= 1'b1;
+      end
+      for (_i_ = 3; _i_ < 4; _i_ = _i_ + 1) begin
+        if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+        else if (RXA[_i_-3] == 1'b1) RIS_REG[_i_] <= 1'b1;
+      end
+      for (_i_ = 4; _i_ < 5; _i_ = _i_ + 1) begin
+        if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+        else if (BRK[_i_-4] == 1'b1) RIS_REG[_i_] <= 1'b1;
+      end
+      for (_i_ = 5; _i_ < 6; _i_ = _i_ + 1) begin
+        if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+        else if (MATCH[_i_-5] == 1'b1) RIS_REG[_i_] <= 1'b1;
+      end
+      for (_i_ = 6; _i_ < 7; _i_ = _i_ + 1) begin
+        if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+        else if (FE[_i_-6] == 1'b1) RIS_REG[_i_] <= 1'b1;
+      end
+      for (_i_ = 7; _i_ < 8; _i_ = _i_ + 1) begin
+        if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+        else if (PRE[_i_-7] == 1'b1) RIS_REG[_i_] <= 1'b1;
+      end
+      for (_i_ = 8; _i_ < 9; _i_ = _i_ + 1) begin
+        if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+        else if (OR[_i_-8] == 1'b1) RIS_REG[_i_] <= 1'b1;
+      end
+      for (_i_ = 9; _i_ < 10; _i_ = _i_ + 1) begin
+        if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+        else if (RTO[_i_-9] == 1'b1) RIS_REG[_i_] <= 1'b1;
+      end
+    end
+
+  assign IRQ = |MIS_REG;
+
+  EF_UART #(
+      .SC(SC),
+      .MDW(MDW),
+      .GFLEN(GFLEN),
+      .FAW(FAW)
+  ) instance_to_wrap (
+      .clk(clk),
+      .rst_n(rst_n),
+      .prescaler(prescaler),
+      .en(en),
+      .tx_en(tx_en),
+      .rx_en(rx_en),
+      .wdata(wdata),
+      .timeout_bits(timeout_bits),
+      .loopback_en(loopback_en),
+      .glitch_filter_en(glitch_filter_en),
+      .tx_level(tx_level),
+      .rx_level(rx_level),
+      .rd(rd),
+      .wr(wr),
+      .tx_fifo_flush(tx_fifo_flush),
+      .rx_fifo_flush(rx_fifo_flush),
+      .data_size(data_size),
+      .stop_bits_count(stop_bits_count),
+      .parity_type(parity_type),
+      .txfifotr(txfifotr),
+      .rxfifotr(rxfifotr),
+      .match_data(match_data),
+      .tx_empty(tx_empty),
+      .tx_full(tx_full),
+      .tx_level_below(tx_level_below),
+      .rdata(rdata),
+      .rx_empty(rx_empty),
+      .rx_full(rx_full),
+      .rx_level_above(rx_level_above),
+      .break_flag(break_flag),
+      .match_flag(match_flag),
+      .frame_error_flag(frame_error_flag),
+      .parity_error_flag(parity_error_flag),
+      .overrun_flag(overrun_flag),
+      .timeout_flag(timeout_flag),
+      .rx(rx),
+      .tx(tx)
+  );
+
+  assign	HRDATA = 
+			(last_HADDR[16-1:0] == RXDATA_REG_OFFSET)	? RXDATA_WIRE :
+			(last_HADDR[16-1:0] == TXDATA_REG_OFFSET)	? TXDATA_WIRE :
+			(last_HADDR[16-1:0] == PR_REG_OFFSET)	? PR_REG :
+			(last_HADDR[16-1:0] == CTRL_REG_OFFSET)	? CTRL_REG :
+			(last_HADDR[16-1:0] == CFG_REG_OFFSET)	? CFG_REG :
+			(last_HADDR[16-1:0] == MATCH_REG_OFFSET)	? MATCH_REG :
+			(last_HADDR[16-1:0] == RX_FIFO_LEVEL_REG_OFFSET)	? RX_FIFO_LEVEL_WIRE :
+			(last_HADDR[16-1:0] == RX_FIFO_THRESHOLD_REG_OFFSET)	? RX_FIFO_THRESHOLD_REG :
+			(last_HADDR[16-1:0] == RX_FIFO_FLUSH_REG_OFFSET)	? RX_FIFO_FLUSH_REG :
+			(last_HADDR[16-1:0] == TX_FIFO_LEVEL_REG_OFFSET)	? TX_FIFO_LEVEL_WIRE :
+			(last_HADDR[16-1:0] == TX_FIFO_THRESHOLD_REG_OFFSET)	? TX_FIFO_THRESHOLD_REG :
+			(last_HADDR[16-1:0] == TX_FIFO_FLUSH_REG_OFFSET)	? TX_FIFO_FLUSH_REG :
+			(last_HADDR[16-1:0] == IM_REG_OFFSET)	? IM_REG :
+			(last_HADDR[16-1:0] == MIS_REG_OFFSET)	? MIS_REG :
+			(last_HADDR[16-1:0] == RIS_REG_OFFSET)	? RIS_REG :
+			(last_HADDR[16-1:0] == GCLK_REG_OFFSET)	? GCLK_REG :
 			32'hDEADBEEF;
 
-	assign	HREADYOUT = 1'b1;
+  assign HREADYOUT = 1'b1;
 
-	assign	RXDATA_WIRE = rdata;
-	assign	rd = (ahbl_re & (last_HADDR[`AHBL_AW-1:0] == RXDATA_REG_OFFSET));
-	assign	wdata = HWDATA;
-	assign	wr = (ahbl_we & (last_HADDR[`AHBL_AW-1:0] == TXDATA_REG_OFFSET));
+  assign RXDATA_WIRE = rdata;
+  assign rd = (ahbl_re & (last_HADDR[16-1:0] == RXDATA_REG_OFFSET));
+  assign wdata = HWDATA;
+  assign wr = (ahbl_we & (last_HADDR[16-1:0] == TXDATA_REG_OFFSET));
 endmodule
diff --git a/hdl/rtl/bus_wrappers/EF_UART_APB.dev.v b/hdl/rtl/bus_wrappers/EF_UART_APB.dev.v
new file mode 100644
index 0000000..b1343e6
--- /dev/null
+++ b/hdl/rtl/bus_wrappers/EF_UART_APB.dev.v
@@ -0,0 +1,294 @@
+/*
+	Copyright 2024 Efabless Corp.
+
+	Author: Mohamed Shalan (mshalan@efabless.com)
+
+	Licensed under the Apache License, Version 2.0 (the "License");
+	you may not use this file except in compliance with the License.
+	You may obtain a copy of the License at
+
+	    http://www.apache.org/licenses/LICENSE-2.0
+
+	Unless required by applicable law or agreed to in writing, software
+	distributed under the License is distributed on an "AS IS" BASIS,
+	WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+	See the License for the specific language governing permissions and
+	limitations under the License.
+
+*/
+
+/* THIS FILE IS GENERATED, DO NOT EDIT */
+
+`timescale			1ns/1ps
+`default_nettype	none
+
+`define				APB_AW		16
+
+`include			"apb_wrapper.vh"
+
+module EF_UART_APB #( 
+	parameter	
+		SC = 8,
+		MDW = 9,
+		GFLEN = 8,
+		FAW = 4
+) (
+`ifdef USE_POWER_PINS
+	inout VPWR,
+	inout VGND,
+`endif
+	`APB_SLAVE_PORTS,
+	input	wire	[1-1:0]	rx,
+	output	wire	[1-1:0]	tx
+);
+
+	localparam	RXDATA_REG_OFFSET = `APB_AW'h0000;
+	localparam	TXDATA_REG_OFFSET = `APB_AW'h0004;
+	localparam	PR_REG_OFFSET = `APB_AW'h0008;
+	localparam	CTRL_REG_OFFSET = `APB_AW'h000C;
+	localparam	CFG_REG_OFFSET = `APB_AW'h0010;
+	localparam	MATCH_REG_OFFSET = `APB_AW'h001C;
+	localparam	RX_FIFO_LEVEL_REG_OFFSET = `APB_AW'hFE00;
+	localparam	RX_FIFO_THRESHOLD_REG_OFFSET = `APB_AW'hFE04;
+	localparam	RX_FIFO_FLUSH_REG_OFFSET = `APB_AW'hFE08;
+	localparam	TX_FIFO_LEVEL_REG_OFFSET = `APB_AW'hFE10;
+	localparam	TX_FIFO_THRESHOLD_REG_OFFSET = `APB_AW'hFE14;
+	localparam	TX_FIFO_FLUSH_REG_OFFSET = `APB_AW'hFE18;
+	localparam	IM_REG_OFFSET = `APB_AW'hFF00;
+	localparam	MIS_REG_OFFSET = `APB_AW'hFF04;
+	localparam	RIS_REG_OFFSET = `APB_AW'hFF08;
+	localparam	IC_REG_OFFSET = `APB_AW'hFF0C;
+
+    reg [0:0] GCLK_REG;
+    wire clk_g;
+    wire clk_gated_en = GCLK_REG[0];
+    ef_util_gating_cell clk_gate_cell(
+        `ifdef USE_POWER_PINS 
+        .vpwr(VPWR),
+        .vgnd(VGND),
+        `endif // USE_POWER_PINS
+        .clk(PCLK),
+        .clk_en(clk_gated_en),
+        .clk_o(clk_g)
+    );
+    
+	wire		clk = clk_g;
+	wire		rst_n = PRESETn;
+
+
+	`APB_CTRL_SIGNALS
+
+	wire [16-1:0]	prescaler;
+	wire [1-1:0]	en;
+	wire [1-1:0]	tx_en;
+	wire [1-1:0]	rx_en;
+	wire [MDW-1:0]	wdata;
+	wire [6-1:0]	timeout_bits;
+	wire [1-1:0]	loopback_en;
+	wire [1-1:0]	glitch_filter_en;
+	wire [FAW-1:0]	tx_level;
+	wire [FAW-1:0]	rx_level;
+	wire [1-1:0]	rd;
+	wire [1-1:0]	wr;
+	wire [1-1:0]	tx_fifo_flush;
+	wire [1-1:0]	rx_fifo_flush;
+	wire [4-1:0]	data_size;
+	wire [1-1:0]	stop_bits_count;
+	wire [3-1:0]	parity_type;
+	wire [FAW-1:0]	txfifotr;
+	wire [FAW-1:0]	rxfifotr;
+	wire [MDW-1:0]	match_data;
+	wire [1-1:0]	tx_empty;
+	wire [1-1:0]	tx_full;
+	wire [1-1:0]	tx_level_below;
+	wire [MDW-1:0]	rdata;
+	wire [1-1:0]	rx_empty;
+	wire [1-1:0]	rx_full;
+	wire [1-1:0]	rx_level_above;
+	wire [1-1:0]	break_flag;
+	wire [1-1:0]	match_flag;
+	wire [1-1:0]	frame_error_flag;
+	wire [1-1:0]	parity_error_flag;
+	wire [1-1:0]	overrun_flag;
+	wire [1-1:0]	timeout_flag;
+
+	// Register Definitions
+	wire	[MDW-1:0]	RXDATA_WIRE;
+
+	wire	[MDW-1:0]	TXDATA_WIRE;
+
+	reg [15:0]	PR_REG;
+	assign	prescaler = PR_REG;
+	`APB_REG(PR_REG, 0, 16)
+
+	reg [4:0]	CTRL_REG;
+	assign	en	=	CTRL_REG[0 : 0];
+	assign	tx_en	=	CTRL_REG[1 : 1];
+	assign	rx_en	=	CTRL_REG[2 : 2];
+	assign	loopback_en	=	CTRL_REG[3 : 3];
+	assign	glitch_filter_en	=	CTRL_REG[4 : 4];
+	`APB_REG(CTRL_REG, 0, 5)
+
+	reg [13:0]	CFG_REG;
+	assign	data_size	=	CFG_REG[3 : 0];
+	assign	stop_bits_count	=	CFG_REG[4 : 4];
+	assign	parity_type	=	CFG_REG[7 : 5];
+	assign	timeout_bits	=	CFG_REG[13 : 8];
+	`APB_REG(CFG_REG, 'h3F08, 14)
+
+	reg [MDW-1:0]	MATCH_REG;
+	assign	match_data = MATCH_REG;
+	`APB_REG(MATCH_REG, 0, MDW)
+
+	wire [FAW-1:0]	RX_FIFO_LEVEL_WIRE;
+	assign	RX_FIFO_LEVEL_WIRE[(FAW - 1) : 0] = rx_level;
+
+	reg [FAW-1:0]	RX_FIFO_THRESHOLD_REG;
+	assign	rxfifotr	=	RX_FIFO_THRESHOLD_REG[(FAW - 1) : 0];
+	`APB_REG(RX_FIFO_THRESHOLD_REG, 0, FAW)
+
+	reg [0:0]	RX_FIFO_FLUSH_REG;
+	assign	rx_fifo_flush	=	RX_FIFO_FLUSH_REG[0 : 0];
+	`APB_REG_AC(RX_FIFO_FLUSH_REG, 0, 1, 1'h0)
+
+	wire [FAW-1:0]	TX_FIFO_LEVEL_WIRE;
+	assign	TX_FIFO_LEVEL_WIRE[(FAW - 1) : 0] = tx_level;
+
+	reg [FAW-1:0]	TX_FIFO_THRESHOLD_REG;
+	assign	txfifotr	=	TX_FIFO_THRESHOLD_REG[(FAW - 1) : 0];
+	`APB_REG(TX_FIFO_THRESHOLD_REG, 0, FAW)
+
+	reg [0:0]	TX_FIFO_FLUSH_REG;
+	assign	tx_fifo_flush	=	TX_FIFO_FLUSH_REG[0 : 0];
+	`APB_REG_AC(TX_FIFO_FLUSH_REG, 0, 1, 1'h0)
+
+	localparam	GCLK_REG_OFFSET = `APB_AW'hFF10;
+	`APB_REG(GCLK_REG, 0, 1)
+
+	reg [9:0] IM_REG;
+	reg [9:0] IC_REG;
+	reg [9:0] RIS_REG;
+
+	`APB_MIS_REG(10)
+	`APB_REG(IM_REG, 0, 10)
+	`APB_IC_REG(10)
+
+	wire [0:0] TXE = tx_empty;
+	wire [0:0] RXF = rx_full;
+	wire [0:0] TXB = tx_level_below;
+	wire [0:0] RXA = rx_level_above;
+	wire [0:0] BRK = break_flag;
+	wire [0:0] MATCH = match_flag;
+	wire [0:0] FE = frame_error_flag;
+	wire [0:0] PRE = parity_error_flag;
+	wire [0:0] OR = overrun_flag;
+	wire [0:0] RTO = timeout_flag;
+
+
+	integer _i_;
+	`APB_BLOCK(RIS_REG, 0) else begin
+		for(_i_ = 0; _i_ < 1; _i_ = _i_ + 1) begin
+			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(TXE[_i_ - 0] == 1'b1) RIS_REG[_i_] <= 1'b1;
+		end
+		for(_i_ = 1; _i_ < 2; _i_ = _i_ + 1) begin
+			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(RXF[_i_ - 1] == 1'b1) RIS_REG[_i_] <= 1'b1;
+		end
+		for(_i_ = 2; _i_ < 3; _i_ = _i_ + 1) begin
+			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(TXB[_i_ - 2] == 1'b1) RIS_REG[_i_] <= 1'b1;
+		end
+		for(_i_ = 3; _i_ < 4; _i_ = _i_ + 1) begin
+			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(RXA[_i_ - 3] == 1'b1) RIS_REG[_i_] <= 1'b1;
+		end
+		for(_i_ = 4; _i_ < 5; _i_ = _i_ + 1) begin
+			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(BRK[_i_ - 4] == 1'b1) RIS_REG[_i_] <= 1'b1;
+		end
+		for(_i_ = 5; _i_ < 6; _i_ = _i_ + 1) begin
+			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(MATCH[_i_ - 5] == 1'b1) RIS_REG[_i_] <= 1'b1;
+		end
+		for(_i_ = 6; _i_ < 7; _i_ = _i_ + 1) begin
+			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(FE[_i_ - 6] == 1'b1) RIS_REG[_i_] <= 1'b1;
+		end
+		for(_i_ = 7; _i_ < 8; _i_ = _i_ + 1) begin
+			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(PRE[_i_ - 7] == 1'b1) RIS_REG[_i_] <= 1'b1;
+		end
+		for(_i_ = 8; _i_ < 9; _i_ = _i_ + 1) begin
+			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(OR[_i_ - 8] == 1'b1) RIS_REG[_i_] <= 1'b1;
+		end
+		for(_i_ = 9; _i_ < 10; _i_ = _i_ + 1) begin
+			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(RTO[_i_ - 9] == 1'b1) RIS_REG[_i_] <= 1'b1;
+		end
+	end
+
+	assign IRQ = |MIS_REG;
+
+	EF_UART #(
+		.SC(SC),
+		.MDW(MDW),
+		.GFLEN(GFLEN),
+		.FAW(FAW)
+	) instance_to_wrap (
+		.clk(clk),
+		.rst_n(rst_n),
+		.prescaler(prescaler),
+		.en(en),
+		.tx_en(tx_en),
+		.rx_en(rx_en),
+		.wdata(wdata),
+		.timeout_bits(timeout_bits),
+		.loopback_en(loopback_en),
+		.glitch_filter_en(glitch_filter_en),
+		.tx_level(tx_level),
+		.rx_level(rx_level),
+		.rd(rd),
+		.wr(wr),
+		.tx_fifo_flush(tx_fifo_flush),
+		.rx_fifo_flush(rx_fifo_flush),
+		.data_size(data_size),
+		.stop_bits_count(stop_bits_count),
+		.parity_type(parity_type),
+		.txfifotr(txfifotr),
+		.rxfifotr(rxfifotr),
+		.match_data(match_data),
+		.tx_empty(tx_empty),
+		.tx_full(tx_full),
+		.tx_level_below(tx_level_below),
+		.rdata(rdata),
+		.rx_empty(rx_empty),
+		.rx_full(rx_full),
+		.rx_level_above(rx_level_above),
+		.break_flag(break_flag),
+		.match_flag(match_flag),
+		.frame_error_flag(frame_error_flag),
+		.parity_error_flag(parity_error_flag),
+		.overrun_flag(overrun_flag),
+		.timeout_flag(timeout_flag),
+		.rx(rx),
+		.tx(tx)
+	);
+
+	assign	PRDATA = 
+			(PADDR[`APB_AW-1:0] == RXDATA_REG_OFFSET)	? RXDATA_WIRE :
+			(PADDR[`APB_AW-1:0] == TXDATA_REG_OFFSET)	? TXDATA_WIRE :
+			(PADDR[`APB_AW-1:0] == PR_REG_OFFSET)	? PR_REG :
+			(PADDR[`APB_AW-1:0] == CTRL_REG_OFFSET)	? CTRL_REG :
+			(PADDR[`APB_AW-1:0] == CFG_REG_OFFSET)	? CFG_REG :
+			(PADDR[`APB_AW-1:0] == MATCH_REG_OFFSET)	? MATCH_REG :
+			(PADDR[`APB_AW-1:0] == RX_FIFO_LEVEL_REG_OFFSET)	? RX_FIFO_LEVEL_WIRE :
+			(PADDR[`APB_AW-1:0] == RX_FIFO_THRESHOLD_REG_OFFSET)	? RX_FIFO_THRESHOLD_REG :
+			(PADDR[`APB_AW-1:0] == RX_FIFO_FLUSH_REG_OFFSET)	? RX_FIFO_FLUSH_REG :
+			(PADDR[`APB_AW-1:0] == TX_FIFO_LEVEL_REG_OFFSET)	? TX_FIFO_LEVEL_WIRE :
+			(PADDR[`APB_AW-1:0] == TX_FIFO_THRESHOLD_REG_OFFSET)	? TX_FIFO_THRESHOLD_REG :
+			(PADDR[`APB_AW-1:0] == TX_FIFO_FLUSH_REG_OFFSET)	? TX_FIFO_FLUSH_REG :
+			(PADDR[`APB_AW-1:0] == IM_REG_OFFSET)	? IM_REG :
+			(PADDR[`APB_AW-1:0] == MIS_REG_OFFSET)	? MIS_REG :
+			(PADDR[`APB_AW-1:0] == RIS_REG_OFFSET)	? RIS_REG :
+			(PADDR[`APB_AW-1:0] == GCLK_REG_OFFSET)	? GCLK_REG :
+			32'hDEADBEEF;
+
+	assign	PREADY = 1'b1;
+
+	assign	RXDATA_WIRE = rdata;
+	assign	rd = (apb_re & (PADDR[`APB_AW-1:0] == RXDATA_REG_OFFSET));
+	assign	wdata = PWDATA;
+	assign	wr = (apb_we & (PADDR[`APB_AW-1:0] == TXDATA_REG_OFFSET));
+endmodule
diff --git a/hdl/rtl/bus_wrappers/EF_UART_APB.pp.v b/hdl/rtl/bus_wrappers/EF_UART_APB.pp.v
deleted file mode 100644
index 172d966..0000000
--- a/hdl/rtl/bus_wrappers/EF_UART_APB.pp.v
+++ /dev/null
@@ -1,406 +0,0 @@
-/*
-	Copyright 2024 Efabless Corp.
-
-	Author: Mohamed Shalan (mshalan@efabless.com)
-
-	Licensed under the Apache License, Version 2.0 (the "License");
-	you may not use this file except in compliance with the License.
-	You may obtain a copy of the License at
-
-	    http://www.apache.org/licenses/LICENSE-2.0
-
-	Unless required by applicable law or agreed to in writing, software
-	distributed under the License is distributed on an "AS IS" BASIS,
-	WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-	See the License for the specific language governing permissions and
-	limitations under the License.
-
-*/
-
-/* THIS FILE IS GENERATED, DO NOT EDIT */
-
-`timescale			1ns/1ps
-`default_nettype	none
-
-
-
-/*
-	Copyright 2020 AUCOHL
-
-    Author: Mohamed Shalan (mshalan@aucegypt.edu)
-	
-	Licensed under the Apache License, Version 2.0 (the "License"); 
-	you may not use this file except in compliance with the License. 
-	You may obtain a copy of the License at:
-
-	http://www.apache.org/licenses/LICENSE-2.0
-
-	Unless required by applicable law or agreed to in writing, software 
-	distributed under the License is distributed on an "AS IS" BASIS, 
-	WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 
-	See the License for the specific language governing permissions and 
-	limitations under the License.
-*/
-
-
-
-
-
-
-                                        
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-    
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-module EF_UART_APB #( 
-	parameter	
-		SC = 8,
-		MDW = 9,
-		GFLEN = 8,
-		FAW = 4
-) (
-
-
-
-
-	input wire          PCLK,
-                                        input wire          PRESETn,
-                                        input wire          PWRITE,
-                                        input wire [31:0]   PWDATA,
-                                        input wire [31:0]   PADDR,
-                                        input wire          PENABLE,
-                                        input wire          PSEL,
-                                        output wire         PREADY,
-                                        output wire [31:0]  PRDATA,
-                                        output wire         IRQ
-,
-	input	wire	[1-1:0]	rx,
-	output	wire	[1-1:0]	tx
-);
-
-	localparam	RXDATA_REG_OFFSET = 16'h0000;
-	localparam	TXDATA_REG_OFFSET = 16'h0004;
-	localparam	PR_REG_OFFSET = 16'h0008;
-	localparam	CTRL_REG_OFFSET = 16'h000C;
-	localparam	CFG_REG_OFFSET = 16'h0010;
-	localparam	MATCH_REG_OFFSET = 16'h001C;
-	localparam	RX_FIFO_LEVEL_REG_OFFSET = 16'hFE00;
-	localparam	RX_FIFO_THRESHOLD_REG_OFFSET = 16'hFE04;
-	localparam	RX_FIFO_FLUSH_REG_OFFSET = 16'hFE08;
-	localparam	TX_FIFO_LEVEL_REG_OFFSET = 16'hFE10;
-	localparam	TX_FIFO_THRESHOLD_REG_OFFSET = 16'hFE14;
-	localparam	TX_FIFO_FLUSH_REG_OFFSET = 16'hFE18;
-	localparam	IM_REG_OFFSET = 16'hFF00;
-	localparam	MIS_REG_OFFSET = 16'hFF04;
-	localparam	RIS_REG_OFFSET = 16'hFF08;
-	localparam	IC_REG_OFFSET = 16'hFF0C;
-
-    reg [0:0] GCLK_REG;
-    wire clk_g;
-    wire clk_gated_en = GCLK_REG[0];
-    ef_gating_cell clk_gate_cell(
-        
-
-
- // USE_POWER_PINS
-        .clk(PCLK),
-        .clk_en(clk_gated_en),
-        .clk_o(clk_g)
-    );
-    
-	wire		clk = clk_g;
-	wire		rst_n = PRESETn;
-
-
-	wire		apb_valid   = PSEL & PENABLE;
-                                        wire		apb_we	    = PWRITE & apb_valid;
-                                        wire		apb_re	    = ~PWRITE & apb_valid;
-
-	wire [16-1:0]	prescaler;
-	wire [1-1:0]	en;
-	wire [1-1:0]	tx_en;
-	wire [1-1:0]	rx_en;
-	wire [MDW-1:0]	wdata;
-	wire [6-1:0]	timeout_bits;
-	wire [1-1:0]	loopback_en;
-	wire [1-1:0]	glitch_filter_en;
-	wire [FAW-1:0]	tx_level;
-	wire [FAW-1:0]	rx_level;
-	wire [1-1:0]	rd;
-	wire [1-1:0]	wr;
-	wire [1-1:0]	tx_fifo_flush;
-	wire [1-1:0]	rx_fifo_flush;
-	wire [4-1:0]	data_size;
-	wire [1-1:0]	stop_bits_count;
-	wire [3-1:0]	parity_type;
-	wire [FAW-1:0]	txfifotr;
-	wire [FAW-1:0]	rxfifotr;
-	wire [MDW-1:0]	match_data;
-	wire [1-1:0]	tx_empty;
-	wire [1-1:0]	tx_full;
-	wire [1-1:0]	tx_level_below;
-	wire [MDW-1:0]	rdata;
-	wire [1-1:0]	rx_empty;
-	wire [1-1:0]	rx_full;
-	wire [1-1:0]	rx_level_above;
-	wire [1-1:0]	break_flag;
-	wire [1-1:0]	match_flag;
-	wire [1-1:0]	frame_error_flag;
-	wire [1-1:0]	parity_error_flag;
-	wire [1-1:0]	overrun_flag;
-	wire [1-1:0]	timeout_flag;
-
-	// Register Definitions
-	wire	[MDW-1:0]	RXDATA_WIRE;
-
-	wire	[MDW-1:0]	TXDATA_WIRE;
-
-	reg [15:0]	PR_REG;
-	assign	prescaler = PR_REG;
-	always @(posedge PCLK or negedge PRESETn) if(~PRESETn) PR_REG <= 0;
-                                        else if(apb_we & (PADDR[16-1:0]==PR_REG_OFFSET))
-                                            PR_REG <= PWDATA[16-1:0];
-
-	reg [4:0]	CTRL_REG;
-	assign	en	=	CTRL_REG[0 : 0];
-	assign	tx_en	=	CTRL_REG[1 : 1];
-	assign	rx_en	=	CTRL_REG[2 : 2];
-	assign	loopback_en	=	CTRL_REG[3 : 3];
-	assign	glitch_filter_en	=	CTRL_REG[4 : 4];
-	always @(posedge PCLK or negedge PRESETn) if(~PRESETn) CTRL_REG <= 0;
-                                        else if(apb_we & (PADDR[16-1:0]==CTRL_REG_OFFSET))
-                                            CTRL_REG <= PWDATA[5-1:0];
-
-	reg [13:0]	CFG_REG;
-	assign	data_size	=	CFG_REG[3 : 0];
-	assign	stop_bits_count	=	CFG_REG[4 : 4];
-	assign	parity_type	=	CFG_REG[7 : 5];
-	assign	timeout_bits	=	CFG_REG[13 : 8];
-	always @(posedge PCLK or negedge PRESETn) if(~PRESETn) CFG_REG <= 'h3F08;
-                                        else if(apb_we & (PADDR[16-1:0]==CFG_REG_OFFSET))
-                                            CFG_REG <= PWDATA[14-1:0];
-
-	reg [MDW-1:0]	MATCH_REG;
-	assign	match_data = MATCH_REG;
-	always @(posedge PCLK or negedge PRESETn) if(~PRESETn) MATCH_REG <= 0;
-                                        else if(apb_we & (PADDR[16-1:0]==MATCH_REG_OFFSET))
-                                            MATCH_REG <= PWDATA[MDW-1:0];
-
-	wire [FAW-1:0]	RX_FIFO_LEVEL_WIRE;
-	assign	RX_FIFO_LEVEL_WIRE[(FAW - 1) : 0] = rx_level;
-
-	reg [FAW-1:0]	RX_FIFO_THRESHOLD_REG;
-	assign	rxfifotr	=	RX_FIFO_THRESHOLD_REG[(FAW - 1) : 0];
-	always @(posedge PCLK or negedge PRESETn) if(~PRESETn) RX_FIFO_THRESHOLD_REG <= 0;
-                                        else if(apb_we & (PADDR[16-1:0]==RX_FIFO_THRESHOLD_REG_OFFSET))
-                                            RX_FIFO_THRESHOLD_REG <= PWDATA[FAW-1:0];
-
-	reg [0:0]	RX_FIFO_FLUSH_REG;
-	assign	rx_fifo_flush	=	RX_FIFO_FLUSH_REG[0 : 0];
-	always @(posedge PCLK or negedge PRESETn) if(~PRESETn) RX_FIFO_FLUSH_REG <= 0;
-                                                else if(apb_we & (PADDR[16-1:0]==RX_FIFO_FLUSH_REG_OFFSET))
-                                                    RX_FIFO_FLUSH_REG <= PWDATA[1-1:0];
-                                                else
-                                                    RX_FIFO_FLUSH_REG <= 1'h0 & RX_FIFO_FLUSH_REG;
-
-	wire [FAW-1:0]	TX_FIFO_LEVEL_WIRE;
-	assign	TX_FIFO_LEVEL_WIRE[(FAW - 1) : 0] = tx_level;
-
-	reg [FAW-1:0]	TX_FIFO_THRESHOLD_REG;
-	assign	txfifotr	=	TX_FIFO_THRESHOLD_REG[(FAW - 1) : 0];
-	always @(posedge PCLK or negedge PRESETn) if(~PRESETn) TX_FIFO_THRESHOLD_REG <= 0;
-                                        else if(apb_we & (PADDR[16-1:0]==TX_FIFO_THRESHOLD_REG_OFFSET))
-                                            TX_FIFO_THRESHOLD_REG <= PWDATA[FAW-1:0];
-
-	reg [0:0]	TX_FIFO_FLUSH_REG;
-	assign	tx_fifo_flush	=	TX_FIFO_FLUSH_REG[0 : 0];
-	always @(posedge PCLK or negedge PRESETn) if(~PRESETn) TX_FIFO_FLUSH_REG <= 0;
-                                                else if(apb_we & (PADDR[16-1:0]==TX_FIFO_FLUSH_REG_OFFSET))
-                                                    TX_FIFO_FLUSH_REG <= PWDATA[1-1:0];
-                                                else
-                                                    TX_FIFO_FLUSH_REG <= 1'h0 & TX_FIFO_FLUSH_REG;
-
-	localparam	GCLK_REG_OFFSET = 16'hFF10;
-	always @(posedge PCLK or negedge PRESETn) if(~PRESETn) GCLK_REG <= 0;
-                                        else if(apb_we & (PADDR[16-1:0]==GCLK_REG_OFFSET))
-                                            GCLK_REG <= PWDATA[1-1:0];
-
-	reg [9:0] IM_REG;
-	reg [9:0] IC_REG;
-	reg [9:0] RIS_REG;
-
-	wire[10-1:0]      MIS_REG	= RIS_REG & IM_REG;
-	always @(posedge PCLK or negedge PRESETn) if(~PRESETn) IM_REG <= 0;
-                                        else if(apb_we & (PADDR[16-1:0]==IM_REG_OFFSET))
-                                            IM_REG <= PWDATA[10-1:0];
-	always @(posedge PCLK or negedge PRESETn) if(~PRESETn) IC_REG <= 10'b0;
-                                        else if(apb_we & (PADDR[16-1:0]==IC_REG_OFFSET))
-                                            IC_REG <= PWDATA[10-1:0];
-                                        else
-                                            IC_REG <= 10'd0;
-
-	wire [0:0] TXE = tx_empty;
-	wire [0:0] RXF = rx_full;
-	wire [0:0] TXB = tx_level_below;
-	wire [0:0] RXA = rx_level_above;
-	wire [0:0] BRK = break_flag;
-	wire [0:0] MATCH = match_flag;
-	wire [0:0] FE = frame_error_flag;
-	wire [0:0] PRE = parity_error_flag;
-	wire [0:0] OR = overrun_flag;
-	wire [0:0] RTO = timeout_flag;
-
-
-	integer _i_;
-	always @(posedge PCLK or negedge PRESETn) if(~PRESETn) RIS_REG <= 0; else begin
-		for(_i_ = 0; _i_ < 1; _i_ = _i_ + 1) begin
-			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(TXE[_i_ - 0] == 1'b1) RIS_REG[_i_] <= 1'b1;
-		end
-		for(_i_ = 1; _i_ < 2; _i_ = _i_ + 1) begin
-			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(RXF[_i_ - 1] == 1'b1) RIS_REG[_i_] <= 1'b1;
-		end
-		for(_i_ = 2; _i_ < 3; _i_ = _i_ + 1) begin
-			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(TXB[_i_ - 2] == 1'b1) RIS_REG[_i_] <= 1'b1;
-		end
-		for(_i_ = 3; _i_ < 4; _i_ = _i_ + 1) begin
-			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(RXA[_i_ - 3] == 1'b1) RIS_REG[_i_] <= 1'b1;
-		end
-		for(_i_ = 4; _i_ < 5; _i_ = _i_ + 1) begin
-			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(BRK[_i_ - 4] == 1'b1) RIS_REG[_i_] <= 1'b1;
-		end
-		for(_i_ = 5; _i_ < 6; _i_ = _i_ + 1) begin
-			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(MATCH[_i_ - 5] == 1'b1) RIS_REG[_i_] <= 1'b1;
-		end
-		for(_i_ = 6; _i_ < 7; _i_ = _i_ + 1) begin
-			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(FE[_i_ - 6] == 1'b1) RIS_REG[_i_] <= 1'b1;
-		end
-		for(_i_ = 7; _i_ < 8; _i_ = _i_ + 1) begin
-			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(PRE[_i_ - 7] == 1'b1) RIS_REG[_i_] <= 1'b1;
-		end
-		for(_i_ = 8; _i_ < 9; _i_ = _i_ + 1) begin
-			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(OR[_i_ - 8] == 1'b1) RIS_REG[_i_] <= 1'b1;
-		end
-		for(_i_ = 9; _i_ < 10; _i_ = _i_ + 1) begin
-			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(RTO[_i_ - 9] == 1'b1) RIS_REG[_i_] <= 1'b1;
-		end
-	end
-
-	assign IRQ = |MIS_REG;
-
-	EF_UART #(
-		.SC(SC),
-		.MDW(MDW),
-		.GFLEN(GFLEN),
-		.FAW(FAW)
-	) instance_to_wrap (
-		.clk(clk),
-		.rst_n(rst_n),
-		.prescaler(prescaler),
-		.en(en),
-		.tx_en(tx_en),
-		.rx_en(rx_en),
-		.wdata(wdata),
-		.timeout_bits(timeout_bits),
-		.loopback_en(loopback_en),
-		.glitch_filter_en(glitch_filter_en),
-		.tx_level(tx_level),
-		.rx_level(rx_level),
-		.rd(rd),
-		.wr(wr),
-		.tx_fifo_flush(tx_fifo_flush),
-		.rx_fifo_flush(rx_fifo_flush),
-		.data_size(data_size),
-		.stop_bits_count(stop_bits_count),
-		.parity_type(parity_type),
-		.txfifotr(txfifotr),
-		.rxfifotr(rxfifotr),
-		.match_data(match_data),
-		.tx_empty(tx_empty),
-		.tx_full(tx_full),
-		.tx_level_below(tx_level_below),
-		.rdata(rdata),
-		.rx_empty(rx_empty),
-		.rx_full(rx_full),
-		.rx_level_above(rx_level_above),
-		.break_flag(break_flag),
-		.match_flag(match_flag),
-		.frame_error_flag(frame_error_flag),
-		.parity_error_flag(parity_error_flag),
-		.overrun_flag(overrun_flag),
-		.timeout_flag(timeout_flag),
-		.rx(rx),
-		.tx(tx)
-	);
-
-	assign	PRDATA = 
-			(PADDR[16-1:0] == RXDATA_REG_OFFSET)	? RXDATA_WIRE :
-			(PADDR[16-1:0] == TXDATA_REG_OFFSET)	? TXDATA_WIRE :
-			(PADDR[16-1:0] == PR_REG_OFFSET)	? PR_REG :
-			(PADDR[16-1:0] == CTRL_REG_OFFSET)	? CTRL_REG :
-			(PADDR[16-1:0] == CFG_REG_OFFSET)	? CFG_REG :
-			(PADDR[16-1:0] == MATCH_REG_OFFSET)	? MATCH_REG :
-			(PADDR[16-1:0] == RX_FIFO_LEVEL_REG_OFFSET)	? RX_FIFO_LEVEL_WIRE :
-			(PADDR[16-1:0] == RX_FIFO_THRESHOLD_REG_OFFSET)	? RX_FIFO_THRESHOLD_REG :
-			(PADDR[16-1:0] == RX_FIFO_FLUSH_REG_OFFSET)	? RX_FIFO_FLUSH_REG :
-			(PADDR[16-1:0] == TX_FIFO_LEVEL_REG_OFFSET)	? TX_FIFO_LEVEL_WIRE :
-			(PADDR[16-1:0] == TX_FIFO_THRESHOLD_REG_OFFSET)	? TX_FIFO_THRESHOLD_REG :
-			(PADDR[16-1:0] == TX_FIFO_FLUSH_REG_OFFSET)	? TX_FIFO_FLUSH_REG :
-			(PADDR[16-1:0] == IM_REG_OFFSET)	? IM_REG :
-			(PADDR[16-1:0] == MIS_REG_OFFSET)	? MIS_REG :
-			(PADDR[16-1:0] == RIS_REG_OFFSET)	? RIS_REG :
-			(PADDR[16-1:0] == IC_REG_OFFSET)	? IC_REG :
-			(PADDR[16-1:0] == GCLK_REG_OFFSET)	? GCLK_REG :
-			32'hDEADBEEF;
-
-	assign	PREADY = 1'b1;
-
-	assign	RXDATA_WIRE = rdata;
-	assign	rd = (apb_re & (PADDR[16-1:0] == RXDATA_REG_OFFSET));
-	assign	wdata = PWDATA;
-	assign	wr = (apb_we & (PADDR[16-1:0] == TXDATA_REG_OFFSET));
-endmodule
diff --git a/hdl/rtl/bus_wrappers/EF_UART_APB.v b/hdl/rtl/bus_wrappers/EF_UART_APB.v
index 3e692b9..331f7cb 100644
--- a/hdl/rtl/bus_wrappers/EF_UART_APB.v
+++ b/hdl/rtl/bus_wrappers/EF_UART_APB.v
@@ -19,277 +19,397 @@
 
 /* THIS FILE IS GENERATED, DO NOT EDIT */
 
-`timescale			1ns/1ps
-`default_nettype	none
+`timescale 1ns / 1ps `default_nettype none
 
-`define				APB_AW		16
 
-`include			"apb_wrapper.vh"
 
-module EF_UART_APB #( 
-	parameter	
-		SC = 8,
-		MDW = 9,
-		GFLEN = 8,
-		FAW = 4
+/*
+	Copyright 2020 AUCOHL
+
+    Author: Mohamed Shalan (mshalan@aucegypt.edu)
+	
+	Licensed under the Apache License, Version 2.0 (the "License"); 
+	you may not use this file except in compliance with the License. 
+	You may obtain a copy of the License at:
+
+	http://www.apache.org/licenses/LICENSE-2.0
+
+	Unless required by applicable law or agreed to in writing, software 
+	distributed under the License is distributed on an "AS IS" BASIS, 
+	WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 
+	See the License for the specific language governing permissions and 
+	limitations under the License.
+*/
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+module EF_UART_APB #(
+    parameter SC = 8,
+    MDW = 9,
+    GFLEN = 8,
+    FAW = 4
 ) (
-`ifdef USE_POWER_PINS
-	inout VPWR,
-	inout VGND,
-`endif
-	`APB_SLAVE_PORTS,
-	input	wire	[1-1:0]	rx,
-	output	wire	[1-1:0]	tx
+
+
+
+
+    input  wire         PCLK,
+    input  wire         PRESETn,
+    input  wire         PWRITE,
+    input  wire [ 31:0] PWDATA,
+    input  wire [ 31:0] PADDR,
+    input  wire         PENABLE,
+    input  wire         PSEL,
+    output wire         PREADY,
+    output wire [ 31:0] PRDATA,
+    output wire         IRQ,
+    input  wire [1-1:0] rx,
+    output wire [1-1:0] tx
 );
 
-	localparam	RXDATA_REG_OFFSET = `APB_AW'h0000;
-	localparam	TXDATA_REG_OFFSET = `APB_AW'h0004;
-	localparam	PR_REG_OFFSET = `APB_AW'h0008;
-	localparam	CTRL_REG_OFFSET = `APB_AW'h000C;
-	localparam	CFG_REG_OFFSET = `APB_AW'h0010;
-	localparam	MATCH_REG_OFFSET = `APB_AW'h001C;
-	localparam	RX_FIFO_LEVEL_REG_OFFSET = `APB_AW'hFE00;
-	localparam	RX_FIFO_THRESHOLD_REG_OFFSET = `APB_AW'hFE04;
-	localparam	RX_FIFO_FLUSH_REG_OFFSET = `APB_AW'hFE08;
-	localparam	TX_FIFO_LEVEL_REG_OFFSET = `APB_AW'hFE10;
-	localparam	TX_FIFO_THRESHOLD_REG_OFFSET = `APB_AW'hFE14;
-	localparam	TX_FIFO_FLUSH_REG_OFFSET = `APB_AW'hFE18;
-	localparam	IM_REG_OFFSET = `APB_AW'hFF00;
-	localparam	MIS_REG_OFFSET = `APB_AW'hFF04;
-	localparam	RIS_REG_OFFSET = `APB_AW'hFF08;
-	localparam	IC_REG_OFFSET = `APB_AW'hFF0C;
-
-    reg [0:0] GCLK_REG;
-    wire clk_g;
-    wire clk_gated_en = GCLK_REG[0];
-    ef_gating_cell clk_gate_cell(
-        `ifdef USE_POWER_PINS 
-        .vpwr(VPWR),
-        .vgnd(VGND),
-        `endif // USE_POWER_PINS
-        .clk(PCLK),
-        .clk_en(clk_gated_en),
-        .clk_o(clk_g)
-    )
-    
-	wire		clk = clk_g;
-	wire		rst_n = PRESETn;
-
-
-	`APB_CTRL_SIGNALS
-
-	wire [16-1:0]	prescaler;
-	wire [1-1:0]	en;
-	wire [1-1:0]	tx_en;
-	wire [1-1:0]	rx_en;
-	wire [MDW-1:0]	wdata;
-	wire [6-1:0]	timeout_bits;
-	wire [1-1:0]	loopback_en;
-	wire [1-1:0]	glitch_filter_en;
-	wire [FAW-1:0]	tx_level;
-	wire [FAW-1:0]	rx_level;
-	wire [1-1:0]	rd;
-	wire [1-1:0]	wr;
-	wire [1-1:0]	tx_fifo_flush;
-	wire [1-1:0]	rx_fifo_flush;
-	wire [4-1:0]	data_size;
-	wire [1-1:0]	stop_bits_count;
-	wire [3-1:0]	parity_type;
-	wire [FAW-1:0]	txfifotr;
-	wire [FAW-1:0]	rxfifotr;
-	wire [MDW-1:0]	match_data;
-	wire [1-1:0]	tx_empty;
-	wire [1-1:0]	tx_full;
-	wire [1-1:0]	tx_level_below;
-	wire [MDW-1:0]	rdata;
-	wire [1-1:0]	rx_empty;
-	wire [1-1:0]	rx_full;
-	wire [1-1:0]	rx_level_above;
-	wire [1-1:0]	break_flag;
-	wire [1-1:0]	match_flag;
-	wire [1-1:0]	frame_error_flag;
-	wire [1-1:0]	parity_error_flag;
-	wire [1-1:0]	overrun_flag;
-	wire [1-1:0]	timeout_flag;
-
-	// Register Definitions
-	wire	[MDW-1:0]	RXDATA_WIRE;
-
-	wire	[MDW-1:0]	TXDATA_WIRE;
-
-	reg [15:0]	PR_REG;
-	assign	prescaler = PR_REG;
-	`APB_REG(PR_REG, 0, 16)
-
-	reg [4:0]	CTRL_REG;
-	assign	en	=	CTRL_REG[0 : 0];
-	assign	tx_en	=	CTRL_REG[1 : 1];
-	assign	rx_en	=	CTRL_REG[2 : 2];
-	assign	loopback_en	=	CTRL_REG[3 : 3];
-	assign	glitch_filter_en	=	CTRL_REG[4 : 4];
-	`APB_REG(CTRL_REG, 0, 5)
-
-	reg [13:0]	CFG_REG;
-	assign	data_size	=	CFG_REG[3 : 0];
-	assign	stop_bits_count	=	CFG_REG[4 : 4];
-	assign	parity_type	=	CFG_REG[7 : 5];
-	assign	timeout_bits	=	CFG_REG[13 : 8];
-	`APB_REG(CFG_REG, 'h3F08, 14)
-
-	reg [MDW-1:0]	MATCH_REG;
-	assign	match_data = MATCH_REG;
-	`APB_REG(MATCH_REG, 0, MDW)
-
-	wire [FAW-1:0]	RX_FIFO_LEVEL_WIRE;
-	assign	RX_FIFO_LEVEL_WIRE[(FAW - 1) : 0] = rx_level;
-
-	reg [FAW-1:0]	RX_FIFO_THRESHOLD_REG;
-	assign	rxfifotr	=	RX_FIFO_THRESHOLD_REG[(FAW - 1) : 0];
-	`APB_REG(RX_FIFO_THRESHOLD_REG, 0, FAW)
-
-	reg [0:0]	RX_FIFO_FLUSH_REG;
-	assign	rx_fifo_flush	=	RX_FIFO_FLUSH_REG[0 : 0];
-	`APB_REG_AC(RX_FIFO_FLUSH_REG, 0, 1, 1'h0)
-
-	wire [FAW-1:0]	TX_FIFO_LEVEL_WIRE;
-	assign	TX_FIFO_LEVEL_WIRE[(FAW - 1) : 0] = tx_level;
-
-	reg [FAW-1:0]	TX_FIFO_THRESHOLD_REG;
-	assign	txfifotr	=	TX_FIFO_THRESHOLD_REG[(FAW - 1) : 0];
-	`APB_REG(TX_FIFO_THRESHOLD_REG, 0, FAW)
-
-	reg [0:0]	TX_FIFO_FLUSH_REG;
-	assign	tx_fifo_flush	=	TX_FIFO_FLUSH_REG[0 : 0];
-	`APB_REG_AC(TX_FIFO_FLUSH_REG, 0, 1, 1'h0)
-
-	localparam	GCLK_REG_OFFSET = `APB_AW'hFF10;
-	`APB_REG(GCLK_REG, 0, 1)
-
-	reg [9:0] IM_REG;
-	reg [9:0] IC_REG;
-	reg [9:0] RIS_REG;
-
-	`APB_MIS_REG(10)
-	`APB_REG(IM_REG, 0, 10)
-	`APB_IC_REG(10)
-
-	wire [0:0] TXE = tx_empty;
-	wire [0:0] RXF = rx_full;
-	wire [0:0] TXB = tx_level_below;
-	wire [0:0] RXA = rx_level_above;
-	wire [0:0] BRK = break_flag;
-	wire [0:0] MATCH = match_flag;
-	wire [0:0] FE = frame_error_flag;
-	wire [0:0] PRE = parity_error_flag;
-	wire [0:0] OR = overrun_flag;
-	wire [0:0] RTO = timeout_flag;
-
-
-	integer _i_;
-	`APB_BLOCK(RIS_REG, 0) else begin
-		for(_i_ = 0; _i_ < 1; _i_ = _i_ + 1) begin
-			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(TXE[_i_ - 0] == 1'b1) RIS_REG[_i_] <= 1'b1;
-		end
-		for(_i_ = 1; _i_ < 2; _i_ = _i_ + 1) begin
-			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(RXF[_i_ - 1] == 1'b1) RIS_REG[_i_] <= 1'b1;
-		end
-		for(_i_ = 2; _i_ < 3; _i_ = _i_ + 1) begin
-			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(TXB[_i_ - 2] == 1'b1) RIS_REG[_i_] <= 1'b1;
-		end
-		for(_i_ = 3; _i_ < 4; _i_ = _i_ + 1) begin
-			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(RXA[_i_ - 3] == 1'b1) RIS_REG[_i_] <= 1'b1;
-		end
-		for(_i_ = 4; _i_ < 5; _i_ = _i_ + 1) begin
-			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(BRK[_i_ - 4] == 1'b1) RIS_REG[_i_] <= 1'b1;
-		end
-		for(_i_ = 5; _i_ < 6; _i_ = _i_ + 1) begin
-			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(MATCH[_i_ - 5] == 1'b1) RIS_REG[_i_] <= 1'b1;
-		end
-		for(_i_ = 6; _i_ < 7; _i_ = _i_ + 1) begin
-			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(FE[_i_ - 6] == 1'b1) RIS_REG[_i_] <= 1'b1;
-		end
-		for(_i_ = 7; _i_ < 8; _i_ = _i_ + 1) begin
-			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(PRE[_i_ - 7] == 1'b1) RIS_REG[_i_] <= 1'b1;
-		end
-		for(_i_ = 8; _i_ < 9; _i_ = _i_ + 1) begin
-			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(OR[_i_ - 8] == 1'b1) RIS_REG[_i_] <= 1'b1;
-		end
-		for(_i_ = 9; _i_ < 10; _i_ = _i_ + 1) begin
-			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(RTO[_i_ - 9] == 1'b1) RIS_REG[_i_] <= 1'b1;
-		end
-	end
-
-	assign IRQ = |MIS_REG;
-
-	EF_UART #(
-		.SC(SC),
-		.MDW(MDW),
-		.GFLEN(GFLEN),
-		.FAW(FAW)
-	) instance_to_wrap (
-		.clk(clk),
-		.rst_n(rst_n),
-		.prescaler(prescaler),
-		.en(en),
-		.tx_en(tx_en),
-		.rx_en(rx_en),
-		.wdata(wdata),
-		.timeout_bits(timeout_bits),
-		.loopback_en(loopback_en),
-		.glitch_filter_en(glitch_filter_en),
-		.tx_level(tx_level),
-		.rx_level(rx_level),
-		.rd(rd),
-		.wr(wr),
-		.tx_fifo_flush(tx_fifo_flush),
-		.rx_fifo_flush(rx_fifo_flush),
-		.data_size(data_size),
-		.stop_bits_count(stop_bits_count),
-		.parity_type(parity_type),
-		.txfifotr(txfifotr),
-		.rxfifotr(rxfifotr),
-		.match_data(match_data),
-		.tx_empty(tx_empty),
-		.tx_full(tx_full),
-		.tx_level_below(tx_level_below),
-		.rdata(rdata),
-		.rx_empty(rx_empty),
-		.rx_full(rx_full),
-		.rx_level_above(rx_level_above),
-		.break_flag(break_flag),
-		.match_flag(match_flag),
-		.frame_error_flag(frame_error_flag),
-		.parity_error_flag(parity_error_flag),
-		.overrun_flag(overrun_flag),
-		.timeout_flag(timeout_flag),
-		.rx(rx),
-		.tx(tx)
-	);
-
-	assign	PRDATA = 
-			(PADDR[`APB_AW-1:0] == RXDATA_REG_OFFSET)	? RXDATA_WIRE :
-			(PADDR[`APB_AW-1:0] == TXDATA_REG_OFFSET)	? TXDATA_WIRE :
-			(PADDR[`APB_AW-1:0] == PR_REG_OFFSET)	? PR_REG :
-			(PADDR[`APB_AW-1:0] == CTRL_REG_OFFSET)	? CTRL_REG :
-			(PADDR[`APB_AW-1:0] == CFG_REG_OFFSET)	? CFG_REG :
-			(PADDR[`APB_AW-1:0] == MATCH_REG_OFFSET)	? MATCH_REG :
-			(PADDR[`APB_AW-1:0] == RX_FIFO_LEVEL_REG_OFFSET)	? RX_FIFO_LEVEL_WIRE :
-			(PADDR[`APB_AW-1:0] == RX_FIFO_THRESHOLD_REG_OFFSET)	? RX_FIFO_THRESHOLD_REG :
-			(PADDR[`APB_AW-1:0] == RX_FIFO_FLUSH_REG_OFFSET)	? RX_FIFO_FLUSH_REG :
-			(PADDR[`APB_AW-1:0] == TX_FIFO_LEVEL_REG_OFFSET)	? TX_FIFO_LEVEL_WIRE :
-			(PADDR[`APB_AW-1:0] == TX_FIFO_THRESHOLD_REG_OFFSET)	? TX_FIFO_THRESHOLD_REG :
-			(PADDR[`APB_AW-1:0] == TX_FIFO_FLUSH_REG_OFFSET)	? TX_FIFO_FLUSH_REG :
-			(PADDR[`APB_AW-1:0] == IM_REG_OFFSET)	? IM_REG :
-			(PADDR[`APB_AW-1:0] == MIS_REG_OFFSET)	? MIS_REG :
-			(PADDR[`APB_AW-1:0] == RIS_REG_OFFSET)	? RIS_REG :
-			(PADDR[`APB_AW-1:0] == IC_REG_OFFSET)	? IC_REG :
-			(PADDR[`APB_AW-1:0] == GCLK_REG_OFFSET)	? GCLK_REG :
+  localparam RXDATA_REG_OFFSET = 16'h0000;
+  localparam TXDATA_REG_OFFSET = 16'h0004;
+  localparam PR_REG_OFFSET = 16'h0008;
+  localparam CTRL_REG_OFFSET = 16'h000C;
+  localparam CFG_REG_OFFSET = 16'h0010;
+  localparam MATCH_REG_OFFSET = 16'h001C;
+  localparam RX_FIFO_LEVEL_REG_OFFSET = 16'hFE00;
+  localparam RX_FIFO_THRESHOLD_REG_OFFSET = 16'hFE04;
+  localparam RX_FIFO_FLUSH_REG_OFFSET = 16'hFE08;
+  localparam TX_FIFO_LEVEL_REG_OFFSET = 16'hFE10;
+  localparam TX_FIFO_THRESHOLD_REG_OFFSET = 16'hFE14;
+  localparam TX_FIFO_FLUSH_REG_OFFSET = 16'hFE18;
+  localparam IM_REG_OFFSET = 16'hFF00;
+  localparam MIS_REG_OFFSET = 16'hFF04;
+  localparam RIS_REG_OFFSET = 16'hFF08;
+  localparam IC_REG_OFFSET = 16'hFF0C;
+
+  reg [0:0] GCLK_REG;
+  wire clk_g;
+  wire clk_gated_en = GCLK_REG[0];
+  ef_util_gating_cell clk_gate_cell (
+
+
+
+      // USE_POWER_PINS
+      .clk(PCLK),
+      .clk_en(clk_gated_en),
+      .clk_o(clk_g)
+  );
+
+  wire           clk = clk_g;
+  wire           rst_n = PRESETn;
+
+
+  wire           apb_valid = PSEL & PENABLE;
+  wire           apb_we = PWRITE & apb_valid;
+  wire           apb_re = ~PWRITE & apb_valid;
+
+  wire [ 16-1:0] prescaler;
+  wire [  1-1:0] en;
+  wire [  1-1:0] tx_en;
+  wire [  1-1:0] rx_en;
+  wire [MDW-1:0] wdata;
+  wire [  6-1:0] timeout_bits;
+  wire [  1-1:0] loopback_en;
+  wire [  1-1:0] glitch_filter_en;
+  wire [FAW-1:0] tx_level;
+  wire [FAW-1:0] rx_level;
+  wire [  1-1:0] rd;
+  wire [  1-1:0] wr;
+  wire [  1-1:0] tx_fifo_flush;
+  wire [  1-1:0] rx_fifo_flush;
+  wire [  4-1:0] data_size;
+  wire [  1-1:0] stop_bits_count;
+  wire [  3-1:0] parity_type;
+  wire [FAW-1:0] txfifotr;
+  wire [FAW-1:0] rxfifotr;
+  wire [MDW-1:0] match_data;
+  wire [  1-1:0] tx_empty;
+  wire [  1-1:0] tx_full;
+  wire [  1-1:0] tx_level_below;
+  wire [MDW-1:0] rdata;
+  wire [  1-1:0] rx_empty;
+  wire [  1-1:0] rx_full;
+  wire [  1-1:0] rx_level_above;
+  wire [  1-1:0] break_flag;
+  wire [  1-1:0] match_flag;
+  wire [  1-1:0] frame_error_flag;
+  wire [  1-1:0] parity_error_flag;
+  wire [  1-1:0] overrun_flag;
+  wire [  1-1:0] timeout_flag;
+
+  // Register Definitions
+  wire [MDW-1:0] RXDATA_WIRE;
+
+  wire [MDW-1:0] TXDATA_WIRE;
+
+  reg  [   15:0] PR_REG;
+  assign prescaler = PR_REG;
+  always @(posedge PCLK or negedge PRESETn)
+    if (~PRESETn) PR_REG <= 0;
+    else if (apb_we & (PADDR[16-1:0] == PR_REG_OFFSET)) PR_REG <= PWDATA[16-1:0];
+
+  reg [4:0] CTRL_REG;
+  assign en = CTRL_REG[0 : 0];
+  assign tx_en = CTRL_REG[1 : 1];
+  assign rx_en = CTRL_REG[2 : 2];
+  assign loopback_en = CTRL_REG[3 : 3];
+  assign glitch_filter_en = CTRL_REG[4 : 4];
+  always @(posedge PCLK or negedge PRESETn)
+    if (~PRESETn) CTRL_REG <= 0;
+    else if (apb_we & (PADDR[16-1:0] == CTRL_REG_OFFSET)) CTRL_REG <= PWDATA[5-1:0];
+
+  reg [13:0] CFG_REG;
+  assign data_size = CFG_REG[3 : 0];
+  assign stop_bits_count = CFG_REG[4 : 4];
+  assign parity_type = CFG_REG[7 : 5];
+  assign timeout_bits = CFG_REG[13 : 8];
+  always @(posedge PCLK or negedge PRESETn)
+    if (~PRESETn) CFG_REG <= 'h3F08;
+    else if (apb_we & (PADDR[16-1:0] == CFG_REG_OFFSET)) CFG_REG <= PWDATA[14-1:0];
+
+  reg [MDW-1:0] MATCH_REG;
+  assign match_data = MATCH_REG;
+  always @(posedge PCLK or negedge PRESETn)
+    if (~PRESETn) MATCH_REG <= 0;
+    else if (apb_we & (PADDR[16-1:0] == MATCH_REG_OFFSET)) MATCH_REG <= PWDATA[MDW-1:0];
+
+  wire [FAW-1:0] RX_FIFO_LEVEL_WIRE;
+  assign RX_FIFO_LEVEL_WIRE[(FAW-1) : 0] = rx_level;
+
+  reg [FAW-1:0] RX_FIFO_THRESHOLD_REG;
+  assign rxfifotr = RX_FIFO_THRESHOLD_REG[(FAW-1) : 0];
+  always @(posedge PCLK or negedge PRESETn)
+    if (~PRESETn) RX_FIFO_THRESHOLD_REG <= 0;
+    else if (apb_we & (PADDR[16-1:0] == RX_FIFO_THRESHOLD_REG_OFFSET))
+      RX_FIFO_THRESHOLD_REG <= PWDATA[FAW-1:0];
+
+  reg [0:0] RX_FIFO_FLUSH_REG;
+  assign rx_fifo_flush = RX_FIFO_FLUSH_REG[0 : 0];
+  always @(posedge PCLK or negedge PRESETn)
+    if (~PRESETn) RX_FIFO_FLUSH_REG <= 0;
+    else if (apb_we & (PADDR[16-1:0] == RX_FIFO_FLUSH_REG_OFFSET))
+      RX_FIFO_FLUSH_REG <= PWDATA[1-1:0];
+    else RX_FIFO_FLUSH_REG <= 1'h0 & RX_FIFO_FLUSH_REG;
+
+  wire [FAW-1:0] TX_FIFO_LEVEL_WIRE;
+  assign TX_FIFO_LEVEL_WIRE[(FAW-1) : 0] = tx_level;
+
+  reg [FAW-1:0] TX_FIFO_THRESHOLD_REG;
+  assign txfifotr = TX_FIFO_THRESHOLD_REG[(FAW-1) : 0];
+  always @(posedge PCLK or negedge PRESETn)
+    if (~PRESETn) TX_FIFO_THRESHOLD_REG <= 0;
+    else if (apb_we & (PADDR[16-1:0] == TX_FIFO_THRESHOLD_REG_OFFSET))
+      TX_FIFO_THRESHOLD_REG <= PWDATA[FAW-1:0];
+
+  reg [0:0] TX_FIFO_FLUSH_REG;
+  assign tx_fifo_flush = TX_FIFO_FLUSH_REG[0 : 0];
+  always @(posedge PCLK or negedge PRESETn)
+    if (~PRESETn) TX_FIFO_FLUSH_REG <= 0;
+    else if (apb_we & (PADDR[16-1:0] == TX_FIFO_FLUSH_REG_OFFSET))
+      TX_FIFO_FLUSH_REG <= PWDATA[1-1:0];
+    else TX_FIFO_FLUSH_REG <= 1'h0 & TX_FIFO_FLUSH_REG;
+
+  localparam GCLK_REG_OFFSET = 16'hFF10;
+  always @(posedge PCLK or negedge PRESETn)
+    if (~PRESETn) GCLK_REG <= 0;
+    else if (apb_we & (PADDR[16-1:0] == GCLK_REG_OFFSET)) GCLK_REG <= PWDATA[1-1:0];
+
+  reg  [   9:0] IM_REG;
+  reg  [   9:0] IC_REG;
+  reg  [   9:0] RIS_REG;
+
+  wire [10-1:0] MIS_REG = RIS_REG & IM_REG;
+  always @(posedge PCLK or negedge PRESETn)
+    if (~PRESETn) IM_REG <= 0;
+    else if (apb_we & (PADDR[16-1:0] == IM_REG_OFFSET)) IM_REG <= PWDATA[10-1:0];
+  always @(posedge PCLK or negedge PRESETn)
+    if (~PRESETn) IC_REG <= 10'b0;
+    else if (apb_we & (PADDR[16-1:0] == IC_REG_OFFSET)) IC_REG <= PWDATA[10-1:0];
+    else IC_REG <= 10'd0;
+
+  wire [0:0] TXE = tx_empty;
+  wire [0:0] RXF = rx_full;
+  wire [0:0] TXB = tx_level_below;
+  wire [0:0] RXA = rx_level_above;
+  wire [0:0] BRK = break_flag;
+  wire [0:0] MATCH = match_flag;
+  wire [0:0] FE = frame_error_flag;
+  wire [0:0] PRE = parity_error_flag;
+  wire [0:0] OR = overrun_flag;
+  wire [0:0] RTO = timeout_flag;
+
+
+  integer _i_;
+  always @(posedge PCLK or negedge PRESETn)
+    if (~PRESETn) RIS_REG <= 0;
+    else begin
+      for (_i_ = 0; _i_ < 1; _i_ = _i_ + 1) begin
+        if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+        else if (TXE[_i_-0] == 1'b1) RIS_REG[_i_] <= 1'b1;
+      end
+      for (_i_ = 1; _i_ < 2; _i_ = _i_ + 1) begin
+        if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+        else if (RXF[_i_-1] == 1'b1) RIS_REG[_i_] <= 1'b1;
+      end
+      for (_i_ = 2; _i_ < 3; _i_ = _i_ + 1) begin
+        if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+        else if (TXB[_i_-2] == 1'b1) RIS_REG[_i_] <= 1'b1;
+      end
+      for (_i_ = 3; _i_ < 4; _i_ = _i_ + 1) begin
+        if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+        else if (RXA[_i_-3] == 1'b1) RIS_REG[_i_] <= 1'b1;
+      end
+      for (_i_ = 4; _i_ < 5; _i_ = _i_ + 1) begin
+        if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+        else if (BRK[_i_-4] == 1'b1) RIS_REG[_i_] <= 1'b1;
+      end
+      for (_i_ = 5; _i_ < 6; _i_ = _i_ + 1) begin
+        if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+        else if (MATCH[_i_-5] == 1'b1) RIS_REG[_i_] <= 1'b1;
+      end
+      for (_i_ = 6; _i_ < 7; _i_ = _i_ + 1) begin
+        if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+        else if (FE[_i_-6] == 1'b1) RIS_REG[_i_] <= 1'b1;
+      end
+      for (_i_ = 7; _i_ < 8; _i_ = _i_ + 1) begin
+        if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+        else if (PRE[_i_-7] == 1'b1) RIS_REG[_i_] <= 1'b1;
+      end
+      for (_i_ = 8; _i_ < 9; _i_ = _i_ + 1) begin
+        if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+        else if (OR[_i_-8] == 1'b1) RIS_REG[_i_] <= 1'b1;
+      end
+      for (_i_ = 9; _i_ < 10; _i_ = _i_ + 1) begin
+        if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+        else if (RTO[_i_-9] == 1'b1) RIS_REG[_i_] <= 1'b1;
+      end
+    end
+
+  assign IRQ = |MIS_REG;
+
+  EF_UART #(
+      .SC(SC),
+      .MDW(MDW),
+      .GFLEN(GFLEN),
+      .FAW(FAW)
+  ) instance_to_wrap (
+      .clk(clk),
+      .rst_n(rst_n),
+      .prescaler(prescaler),
+      .en(en),
+      .tx_en(tx_en),
+      .rx_en(rx_en),
+      .wdata(wdata),
+      .timeout_bits(timeout_bits),
+      .loopback_en(loopback_en),
+      .glitch_filter_en(glitch_filter_en),
+      .tx_level(tx_level),
+      .rx_level(rx_level),
+      .rd(rd),
+      .wr(wr),
+      .tx_fifo_flush(tx_fifo_flush),
+      .rx_fifo_flush(rx_fifo_flush),
+      .data_size(data_size),
+      .stop_bits_count(stop_bits_count),
+      .parity_type(parity_type),
+      .txfifotr(txfifotr),
+      .rxfifotr(rxfifotr),
+      .match_data(match_data),
+      .tx_empty(tx_empty),
+      .tx_full(tx_full),
+      .tx_level_below(tx_level_below),
+      .rdata(rdata),
+      .rx_empty(rx_empty),
+      .rx_full(rx_full),
+      .rx_level_above(rx_level_above),
+      .break_flag(break_flag),
+      .match_flag(match_flag),
+      .frame_error_flag(frame_error_flag),
+      .parity_error_flag(parity_error_flag),
+      .overrun_flag(overrun_flag),
+      .timeout_flag(timeout_flag),
+      .rx(rx),
+      .tx(tx)
+  );
+
+  assign	PRDATA = 
+			(PADDR[16-1:0] == RXDATA_REG_OFFSET)	? RXDATA_WIRE :
+			(PADDR[16-1:0] == TXDATA_REG_OFFSET)	? TXDATA_WIRE :
+			(PADDR[16-1:0] == PR_REG_OFFSET)	? PR_REG :
+			(PADDR[16-1:0] == CTRL_REG_OFFSET)	? CTRL_REG :
+			(PADDR[16-1:0] == CFG_REG_OFFSET)	? CFG_REG :
+			(PADDR[16-1:0] == MATCH_REG_OFFSET)	? MATCH_REG :
+			(PADDR[16-1:0] == RX_FIFO_LEVEL_REG_OFFSET)	? RX_FIFO_LEVEL_WIRE :
+			(PADDR[16-1:0] == RX_FIFO_THRESHOLD_REG_OFFSET)	? RX_FIFO_THRESHOLD_REG :
+			(PADDR[16-1:0] == RX_FIFO_FLUSH_REG_OFFSET)	? RX_FIFO_FLUSH_REG :
+			(PADDR[16-1:0] == TX_FIFO_LEVEL_REG_OFFSET)	? TX_FIFO_LEVEL_WIRE :
+			(PADDR[16-1:0] == TX_FIFO_THRESHOLD_REG_OFFSET)	? TX_FIFO_THRESHOLD_REG :
+			(PADDR[16-1:0] == TX_FIFO_FLUSH_REG_OFFSET)	? TX_FIFO_FLUSH_REG :
+			(PADDR[16-1:0] == IM_REG_OFFSET)	? IM_REG :
+			(PADDR[16-1:0] == MIS_REG_OFFSET)	? MIS_REG :
+			(PADDR[16-1:0] == RIS_REG_OFFSET)	? RIS_REG :
+			(PADDR[16-1:0] == GCLK_REG_OFFSET)	? GCLK_REG :
 			32'hDEADBEEF;
 
-	assign	PREADY = 1'b1;
+  assign PREADY = 1'b1;
 
-	assign	RXDATA_WIRE = rdata;
-	assign	rd = (apb_re & (PADDR[`APB_AW-1:0] == RXDATA_REG_OFFSET));
-	assign	wdata = PWDATA;
-	assign	wr = (apb_we & (PADDR[`APB_AW-1:0] == TXDATA_REG_OFFSET));
+  assign RXDATA_WIRE = rdata;
+  assign rd = (apb_re & (PADDR[16-1:0] == RXDATA_REG_OFFSET));
+  assign wdata = PWDATA;
+  assign wr = (apb_we & (PADDR[16-1:0] == TXDATA_REG_OFFSET));
 endmodule
diff --git a/hdl/rtl/bus_wrappers/EF_UART_WB.pp.v b/hdl/rtl/bus_wrappers/EF_UART_WB.dev.v
similarity index 51%
rename from hdl/rtl/bus_wrappers/EF_UART_WB.pp.v
rename to hdl/rtl/bus_wrappers/EF_UART_WB.dev.v
index 2cba783..9334f88 100644
--- a/hdl/rtl/bus_wrappers/EF_UART_WB.pp.v
+++ b/hdl/rtl/bus_wrappers/EF_UART_WB.dev.v
@@ -22,59 +22,9 @@
 `timescale			1ns/1ps
 `default_nettype	none
 
+`define				WB_AW		16
 
-
-/*
-	Copyright 2020 AUCOHL
-
-    Author: Mohamed Shalan (mshalan@aucegypt.edu)
-	
-	Licensed under the Apache License, Version 2.0 (the "License"); 
-	you may not use this file except in compliance with the License. 
-	You may obtain a copy of the License at:
-
-	http://www.apache.org/licenses/LICENSE-2.0
-
-	Unless required by applicable law or agreed to in writing, software 
-	distributed under the License is distributed on an "AS IS" BASIS, 
-	WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 
-	See the License for the specific language governing permissions and 
-	limitations under the License.
-*/
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-                                        
-
+`include			"wb_wrapper.vh"
 
 module EF_UART_WB #( 
 	parameter	
@@ -83,51 +33,40 @@ module EF_UART_WB #(
 		GFLEN = 8,
 		FAW = 4
 ) (
-
-
-
-
-	input   wire            ext_clk,
-                                        input   wire            clk_i,
-                                        input   wire            rst_i,
-                                        input   wire [31:0]     adr_i,
-                                        input   wire [31:0]     dat_i,
-                                        output  wire [31:0]     dat_o,
-                                        input   wire [3:0]      sel_i,
-                                        input   wire            cyc_i,
-                                        input   wire            stb_i,
-                                        output  reg             ack_o,
-                                        input   wire            we_i,
-                                        output  wire            IRQ,
+`ifdef USE_POWER_PINS
+	inout VPWR,
+	inout VGND,
+`endif
+	`WB_SLAVE_PORTS,
 	input	wire	[1-1:0]	rx,
 	output	wire	[1-1:0]	tx
 );
 
-	localparam	RXDATA_REG_OFFSET = 16'h0000;
-	localparam	TXDATA_REG_OFFSET = 16'h0004;
-	localparam	PR_REG_OFFSET = 16'h0008;
-	localparam	CTRL_REG_OFFSET = 16'h000C;
-	localparam	CFG_REG_OFFSET = 16'h0010;
-	localparam	MATCH_REG_OFFSET = 16'h001C;
-	localparam	RX_FIFO_LEVEL_REG_OFFSET = 16'hFE00;
-	localparam	RX_FIFO_THRESHOLD_REG_OFFSET = 16'hFE04;
-	localparam	RX_FIFO_FLUSH_REG_OFFSET = 16'hFE08;
-	localparam	TX_FIFO_LEVEL_REG_OFFSET = 16'hFE10;
-	localparam	TX_FIFO_THRESHOLD_REG_OFFSET = 16'hFE14;
-	localparam	TX_FIFO_FLUSH_REG_OFFSET = 16'hFE18;
-	localparam	IM_REG_OFFSET = 16'hFF00;
-	localparam	MIS_REG_OFFSET = 16'hFF04;
-	localparam	RIS_REG_OFFSET = 16'hFF08;
-	localparam	IC_REG_OFFSET = 16'hFF0C;
+	localparam	RXDATA_REG_OFFSET = `WB_AW'h0000;
+	localparam	TXDATA_REG_OFFSET = `WB_AW'h0004;
+	localparam	PR_REG_OFFSET = `WB_AW'h0008;
+	localparam	CTRL_REG_OFFSET = `WB_AW'h000C;
+	localparam	CFG_REG_OFFSET = `WB_AW'h0010;
+	localparam	MATCH_REG_OFFSET = `WB_AW'h001C;
+	localparam	RX_FIFO_LEVEL_REG_OFFSET = `WB_AW'hFE00;
+	localparam	RX_FIFO_THRESHOLD_REG_OFFSET = `WB_AW'hFE04;
+	localparam	RX_FIFO_FLUSH_REG_OFFSET = `WB_AW'hFE08;
+	localparam	TX_FIFO_LEVEL_REG_OFFSET = `WB_AW'hFE10;
+	localparam	TX_FIFO_THRESHOLD_REG_OFFSET = `WB_AW'hFE14;
+	localparam	TX_FIFO_FLUSH_REG_OFFSET = `WB_AW'hFE18;
+	localparam	IM_REG_OFFSET = `WB_AW'hFF00;
+	localparam	MIS_REG_OFFSET = `WB_AW'hFF04;
+	localparam	RIS_REG_OFFSET = `WB_AW'hFF08;
+	localparam	IC_REG_OFFSET = `WB_AW'hFF0C;
 
     reg [0:0] GCLK_REG;
     wire clk_g;
     wire clk_gated_en = GCLK_REG[0];
-    ef_gating_cell clk_gate_cell(
-        
-
-
- // USE_POWER_PINS
+    ef_util_gating_cell clk_gate_cell(
+        `ifdef USE_POWER_PINS 
+        .vpwr(VPWR),
+        .vgnd(VGND),
+        `endif // USE_POWER_PINS
         .clk(clk_i),
         .clk_en(clk_gated_en),
         .clk_o(clk_g)
@@ -137,10 +76,7 @@ module EF_UART_WB #(
 	wire		rst_n = (~rst_i);
 
 
-	wire            wb_valid    = cyc_i & stb_i;
-                                        wire            wb_we       = we_i & wb_valid;
-                                        wire            wb_re       = ~we_i & wb_valid;
-                                        wire[3:0]       wb_byte_sel = sel_i & {4{wb_we}};
+	`WB_CTRL_SIGNALS
 
 	wire [16-1:0]	prescaler;
 	wire [1-1:0]	en;
@@ -183,7 +119,7 @@ module EF_UART_WB #(
 
 	reg [15:0]	PR_REG;
 	assign	prescaler = PR_REG;
-	always @(posedge clk_i or posedge rst_i) if(rst_i) PR_REG <= 0; else if(wb_we & (adr_i[16-1:0]==PR_REG_OFFSET)) PR_REG <= dat_i[16-1:0];
+	`WB_REG(PR_REG, 0, 16)
 
 	reg [4:0]	CTRL_REG;
 	assign	en	=	CTRL_REG[0 : 0];
@@ -191,55 +127,51 @@ module EF_UART_WB #(
 	assign	rx_en	=	CTRL_REG[2 : 2];
 	assign	loopback_en	=	CTRL_REG[3 : 3];
 	assign	glitch_filter_en	=	CTRL_REG[4 : 4];
-	always @(posedge clk_i or posedge rst_i) if(rst_i) CTRL_REG <= 0; else if(wb_we & (adr_i[16-1:0]==CTRL_REG_OFFSET)) CTRL_REG <= dat_i[5-1:0];
+	`WB_REG(CTRL_REG, 0, 5)
 
 	reg [13:0]	CFG_REG;
 	assign	data_size	=	CFG_REG[3 : 0];
 	assign	stop_bits_count	=	CFG_REG[4 : 4];
 	assign	parity_type	=	CFG_REG[7 : 5];
 	assign	timeout_bits	=	CFG_REG[13 : 8];
-	always @(posedge clk_i or posedge rst_i) if(rst_i) CFG_REG <= 'h3F08; else if(wb_we & (adr_i[16-1:0]==CFG_REG_OFFSET)) CFG_REG <= dat_i[14-1:0];
+	`WB_REG(CFG_REG, 'h3F08, 14)
 
 	reg [MDW-1:0]	MATCH_REG;
 	assign	match_data = MATCH_REG;
-	always @(posedge clk_i or posedge rst_i) if(rst_i) MATCH_REG <= 0; else if(wb_we & (adr_i[16-1:0]==MATCH_REG_OFFSET)) MATCH_REG <= dat_i[MDW-1:0];
+	`WB_REG(MATCH_REG, 0, MDW)
 
 	wire [FAW-1:0]	RX_FIFO_LEVEL_WIRE;
 	assign	RX_FIFO_LEVEL_WIRE[(FAW - 1) : 0] = rx_level;
 
 	reg [FAW-1:0]	RX_FIFO_THRESHOLD_REG;
 	assign	rxfifotr	=	RX_FIFO_THRESHOLD_REG[(FAW - 1) : 0];
-	always @(posedge clk_i or posedge rst_i) if(rst_i) RX_FIFO_THRESHOLD_REG <= 0; else if(wb_we & (adr_i[16-1:0]==RX_FIFO_THRESHOLD_REG_OFFSET)) RX_FIFO_THRESHOLD_REG <= dat_i[FAW-1:0];
+	`WB_REG(RX_FIFO_THRESHOLD_REG, 0, FAW)
 
 	reg [0:0]	RX_FIFO_FLUSH_REG;
 	assign	rx_fifo_flush	=	RX_FIFO_FLUSH_REG[0 : 0];
-	always @(posedge clk_i or posedge rst_i) if(rst_i) RX_FIFO_FLUSH_REG <= 0; else if(wb_we & (adr_i[16-1:0]==RX_FIFO_FLUSH_REG_OFFSET)) RX_FIFO_FLUSH_REG <= dat_i[1-1:0]; else RX_FIFO_FLUSH_REG <= 1'h0 & RX_FIFO_FLUSH_REG;
+	`WB_REG_AC(RX_FIFO_FLUSH_REG, 0, 1, 1'h0)
 
 	wire [FAW-1:0]	TX_FIFO_LEVEL_WIRE;
 	assign	TX_FIFO_LEVEL_WIRE[(FAW - 1) : 0] = tx_level;
 
 	reg [FAW-1:0]	TX_FIFO_THRESHOLD_REG;
 	assign	txfifotr	=	TX_FIFO_THRESHOLD_REG[(FAW - 1) : 0];
-	always @(posedge clk_i or posedge rst_i) if(rst_i) TX_FIFO_THRESHOLD_REG <= 0; else if(wb_we & (adr_i[16-1:0]==TX_FIFO_THRESHOLD_REG_OFFSET)) TX_FIFO_THRESHOLD_REG <= dat_i[FAW-1:0];
+	`WB_REG(TX_FIFO_THRESHOLD_REG, 0, FAW)
 
 	reg [0:0]	TX_FIFO_FLUSH_REG;
 	assign	tx_fifo_flush	=	TX_FIFO_FLUSH_REG[0 : 0];
-	always @(posedge clk_i or posedge rst_i) if(rst_i) TX_FIFO_FLUSH_REG <= 0; else if(wb_we & (adr_i[16-1:0]==TX_FIFO_FLUSH_REG_OFFSET)) TX_FIFO_FLUSH_REG <= dat_i[1-1:0]; else TX_FIFO_FLUSH_REG <= 1'h0 & TX_FIFO_FLUSH_REG;
+	`WB_REG_AC(TX_FIFO_FLUSH_REG, 0, 1, 1'h0)
 
-	localparam	GCLK_REG_OFFSET = 16'hFF10;
-	always @(posedge clk_i or posedge rst_i) if(rst_i) GCLK_REG <= 0; else if(wb_we & (adr_i[16-1:0]==GCLK_REG_OFFSET)) GCLK_REG <= dat_i[1-1:0];
+	localparam	GCLK_REG_OFFSET = `WB_AW'hFF10;
+	`WB_REG(GCLK_REG, 0, 1)
 
 	reg [9:0] IM_REG;
 	reg [9:0] IC_REG;
 	reg [9:0] RIS_REG;
 
-	wire[10-1:0]      MIS_REG	= RIS_REG & IM_REG;
-	always @(posedge clk_i or posedge rst_i) if(rst_i) IM_REG <= 0; else if(wb_we & (adr_i[16-1:0]==IM_REG_OFFSET)) IM_REG <= dat_i[10-1:0];
-	always @(posedge clk_i or posedge rst_i) if(rst_i) IC_REG <= 10'b0;
-                                        else if(wb_we & (adr_i[16-1:0]==IC_REG_OFFSET))
-                                            IC_REG <= dat_i[10-1:0];
-                                        else
-                                            IC_REG <= 10'd0;
+	`WB_MIS_REG(10)
+	`WB_REG(IM_REG, 0, 10)
+	`WB_IC_REG(10)
 
 	wire [0:0] TXE = tx_empty;
 	wire [0:0] RXF = rx_full;
@@ -254,7 +186,7 @@ module EF_UART_WB #(
 
 
 	integer _i_;
-	always @(posedge clk_i or posedge rst_i) if(rst_i) RIS_REG <= 0; else begin
+	`WB_BLOCK(RIS_REG, 0) else begin
 		for(_i_ = 0; _i_ < 1; _i_ = _i_ + 1) begin
 			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(TXE[_i_ - 0] == 1'b1) RIS_REG[_i_] <= 1'b1;
 		end
@@ -335,22 +267,22 @@ module EF_UART_WB #(
 	);
 
 	assign	dat_o = 
-			(adr_i[16-1:0] == RXDATA_REG_OFFSET)	? RXDATA_WIRE :
-			(adr_i[16-1:0] == TXDATA_REG_OFFSET)	? TXDATA_WIRE :
-			(adr_i[16-1:0] == PR_REG_OFFSET)	? PR_REG :
-			(adr_i[16-1:0] == CTRL_REG_OFFSET)	? CTRL_REG :
-			(adr_i[16-1:0] == CFG_REG_OFFSET)	? CFG_REG :
-			(adr_i[16-1:0] == MATCH_REG_OFFSET)	? MATCH_REG :
-			(adr_i[16-1:0] == RX_FIFO_LEVEL_REG_OFFSET)	? RX_FIFO_LEVEL_WIRE :
-			(adr_i[16-1:0] == RX_FIFO_THRESHOLD_REG_OFFSET)	? RX_FIFO_THRESHOLD_REG :
-			(adr_i[16-1:0] == RX_FIFO_FLUSH_REG_OFFSET)	? RX_FIFO_FLUSH_REG :
-			(adr_i[16-1:0] == TX_FIFO_LEVEL_REG_OFFSET)	? TX_FIFO_LEVEL_WIRE :
-			(adr_i[16-1:0] == TX_FIFO_THRESHOLD_REG_OFFSET)	? TX_FIFO_THRESHOLD_REG :
-			(adr_i[16-1:0] == TX_FIFO_FLUSH_REG_OFFSET)	? TX_FIFO_FLUSH_REG :
-			(adr_i[16-1:0] == IM_REG_OFFSET)	? IM_REG :
-			(adr_i[16-1:0] == MIS_REG_OFFSET)	? MIS_REG :
-			(adr_i[16-1:0] == RIS_REG_OFFSET)	? RIS_REG :
-			(adr_i[16-1:0] == IC_REG_OFFSET)	? IC_REG :
+			(adr_i[`WB_AW-1:0] == RXDATA_REG_OFFSET)	? RXDATA_WIRE :
+			(adr_i[`WB_AW-1:0] == TXDATA_REG_OFFSET)	? TXDATA_WIRE :
+			(adr_i[`WB_AW-1:0] == PR_REG_OFFSET)	? PR_REG :
+			(adr_i[`WB_AW-1:0] == CTRL_REG_OFFSET)	? CTRL_REG :
+			(adr_i[`WB_AW-1:0] == CFG_REG_OFFSET)	? CFG_REG :
+			(adr_i[`WB_AW-1:0] == MATCH_REG_OFFSET)	? MATCH_REG :
+			(adr_i[`WB_AW-1:0] == RX_FIFO_LEVEL_REG_OFFSET)	? RX_FIFO_LEVEL_WIRE :
+			(adr_i[`WB_AW-1:0] == RX_FIFO_THRESHOLD_REG_OFFSET)	? RX_FIFO_THRESHOLD_REG :
+			(adr_i[`WB_AW-1:0] == RX_FIFO_FLUSH_REG_OFFSET)	? RX_FIFO_FLUSH_REG :
+			(adr_i[`WB_AW-1:0] == TX_FIFO_LEVEL_REG_OFFSET)	? TX_FIFO_LEVEL_WIRE :
+			(adr_i[`WB_AW-1:0] == TX_FIFO_THRESHOLD_REG_OFFSET)	? TX_FIFO_THRESHOLD_REG :
+			(adr_i[`WB_AW-1:0] == TX_FIFO_FLUSH_REG_OFFSET)	? TX_FIFO_FLUSH_REG :
+			(adr_i[`WB_AW-1:0] == IM_REG_OFFSET)	? IM_REG :
+			(adr_i[`WB_AW-1:0] == MIS_REG_OFFSET)	? MIS_REG :
+			(adr_i[`WB_AW-1:0] == RIS_REG_OFFSET)	? RIS_REG :
+			(adr_i[`WB_AW-1:0] == IC_REG_OFFSET)	? IC_REG :
 			32'hDEADBEEF;
 
 	always @ (posedge clk_i or posedge rst_i)
@@ -361,7 +293,7 @@ module EF_UART_WB #(
 		else
 			ack_o <= 1'b0;
 	assign	RXDATA_WIRE = rdata;
-	assign	rd =  ack_o & (wb_re & (adr_i[16-1:0] == RXDATA_REG_OFFSET));
+	assign	rd =  ack_o & (wb_re & (adr_i[`WB_AW-1:0] == RXDATA_REG_OFFSET));
 	assign	wdata = dat_i;
-	assign	wr = ack_o & (wb_we & (adr_i[16-1:0] == TXDATA_REG_OFFSET));
+	assign	wr = ack_o & (wb_we & (adr_i[`WB_AW-1:0] == TXDATA_REG_OFFSET));
 endmodule
diff --git a/hdl/rtl/bus_wrappers/EF_UART_WB.v b/hdl/rtl/bus_wrappers/EF_UART_WB.v
index ae55db9..3c28f6a 100644
--- a/hdl/rtl/bus_wrappers/EF_UART_WB.v
+++ b/hdl/rtl/bus_wrappers/EF_UART_WB.v
@@ -19,281 +19,377 @@
 
 /* THIS FILE IS GENERATED, DO NOT EDIT */
 
-`timescale			1ns/1ps
-`default_nettype	none
+`timescale 1ns / 1ps `default_nettype none
 
-`define				WB_AW		16
 
-`include			"wb_wrapper.vh"
 
-module EF_UART_WB #( 
-	parameter	
-		SC = 8,
-		MDW = 9,
-		GFLEN = 8,
-		FAW = 4
+/*
+	Copyright 2020 AUCOHL
+
+    Author: Mohamed Shalan (mshalan@aucegypt.edu)
+	
+	Licensed under the Apache License, Version 2.0 (the "License"); 
+	you may not use this file except in compliance with the License. 
+	You may obtain a copy of the License at:
+
+	http://www.apache.org/licenses/LICENSE-2.0
+
+	Unless required by applicable law or agreed to in writing, software 
+	distributed under the License is distributed on an "AS IS" BASIS, 
+	WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 
+	See the License for the specific language governing permissions and 
+	limitations under the License.
+*/
+
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+
+module EF_UART_WB #(
+    parameter SC = 8,
+    MDW = 9,
+    GFLEN = 8,
+    FAW = 4
 ) (
-`ifdef USE_POWER_PINS
-	inout VPWR,
-	inout VGND,
-`endif
-	`WB_SLAVE_PORTS,
-	input	wire	[1-1:0]	rx,
-	output	wire	[1-1:0]	tx
+
+
+
+
+    input  wire         clk_i,
+    input  wire         rst_i,
+    input  wire [ 31:0] adr_i,
+    input  wire [ 31:0] dat_i,
+    output wire [ 31:0] dat_o,
+    input  wire [  3:0] sel_i,
+    input  wire         cyc_i,
+    input  wire         stb_i,
+    output reg          ack_o,
+    input  wire         we_i,
+    output wire         IRQ,
+    input  wire [1-1:0] rx,
+    output wire [1-1:0] tx
 );
 
-	localparam	RXDATA_REG_OFFSET = `WB_AW'h0000;
-	localparam	TXDATA_REG_OFFSET = `WB_AW'h0004;
-	localparam	PR_REG_OFFSET = `WB_AW'h0008;
-	localparam	CTRL_REG_OFFSET = `WB_AW'h000C;
-	localparam	CFG_REG_OFFSET = `WB_AW'h0010;
-	localparam	MATCH_REG_OFFSET = `WB_AW'h001C;
-	localparam	RX_FIFO_LEVEL_REG_OFFSET = `WB_AW'hFE00;
-	localparam	RX_FIFO_THRESHOLD_REG_OFFSET = `WB_AW'hFE04;
-	localparam	RX_FIFO_FLUSH_REG_OFFSET = `WB_AW'hFE08;
-	localparam	TX_FIFO_LEVEL_REG_OFFSET = `WB_AW'hFE10;
-	localparam	TX_FIFO_THRESHOLD_REG_OFFSET = `WB_AW'hFE14;
-	localparam	TX_FIFO_FLUSH_REG_OFFSET = `WB_AW'hFE18;
-	localparam	IM_REG_OFFSET = `WB_AW'hFF00;
-	localparam	MIS_REG_OFFSET = `WB_AW'hFF04;
-	localparam	RIS_REG_OFFSET = `WB_AW'hFF08;
-	localparam	IC_REG_OFFSET = `WB_AW'hFF0C;
-
-    reg [0:0] GCLK_REG;
-    wire clk_g;
-    wire clk_gated_en = GCLK_REG[0];
-    ef_gating_cell clk_gate_cell(
-        `ifdef USE_POWER_PINS 
-        .vpwr(VPWR),
-        .vgnd(VGND),
-        `endif // USE_POWER_PINS
-        .clk(clk_i),
-        .clk_en(clk_gated_en),
-        .clk_o(clk_g)
-    )
-    
-	wire		clk = clk_g;
-	wire		rst_n = (~rst_i);
-
-
-	`WB_CTRL_SIGNALS
-
-	wire [16-1:0]	prescaler;
-	wire [1-1:0]	en;
-	wire [1-1:0]	tx_en;
-	wire [1-1:0]	rx_en;
-	wire [MDW-1:0]	wdata;
-	wire [6-1:0]	timeout_bits;
-	wire [1-1:0]	loopback_en;
-	wire [1-1:0]	glitch_filter_en;
-	wire [FAW-1:0]	tx_level;
-	wire [FAW-1:0]	rx_level;
-	wire [1-1:0]	rd;
-	wire [1-1:0]	wr;
-	wire [1-1:0]	tx_fifo_flush;
-	wire [1-1:0]	rx_fifo_flush;
-	wire [4-1:0]	data_size;
-	wire [1-1:0]	stop_bits_count;
-	wire [3-1:0]	parity_type;
-	wire [FAW-1:0]	txfifotr;
-	wire [FAW-1:0]	rxfifotr;
-	wire [MDW-1:0]	match_data;
-	wire [1-1:0]	tx_empty;
-	wire [1-1:0]	tx_full;
-	wire [1-1:0]	tx_level_below;
-	wire [MDW-1:0]	rdata;
-	wire [1-1:0]	rx_empty;
-	wire [1-1:0]	rx_full;
-	wire [1-1:0]	rx_level_above;
-	wire [1-1:0]	break_flag;
-	wire [1-1:0]	match_flag;
-	wire [1-1:0]	frame_error_flag;
-	wire [1-1:0]	parity_error_flag;
-	wire [1-1:0]	overrun_flag;
-	wire [1-1:0]	timeout_flag;
-
-	// Register Definitions
-	wire	[MDW-1:0]	RXDATA_WIRE;
-
-	wire	[MDW-1:0]	TXDATA_WIRE;
-
-	reg [15:0]	PR_REG;
-	assign	prescaler = PR_REG;
-	`WB_REG(PR_REG, 0, 16)
-
-	reg [4:0]	CTRL_REG;
-	assign	en	=	CTRL_REG[0 : 0];
-	assign	tx_en	=	CTRL_REG[1 : 1];
-	assign	rx_en	=	CTRL_REG[2 : 2];
-	assign	loopback_en	=	CTRL_REG[3 : 3];
-	assign	glitch_filter_en	=	CTRL_REG[4 : 4];
-	`WB_REG(CTRL_REG, 0, 5)
-
-	reg [13:0]	CFG_REG;
-	assign	data_size	=	CFG_REG[3 : 0];
-	assign	stop_bits_count	=	CFG_REG[4 : 4];
-	assign	parity_type	=	CFG_REG[7 : 5];
-	assign	timeout_bits	=	CFG_REG[13 : 8];
-	`WB_REG(CFG_REG, 'h3F08, 14)
-
-	reg [MDW-1:0]	MATCH_REG;
-	assign	match_data = MATCH_REG;
-	`WB_REG(MATCH_REG, 0, MDW)
-
-	wire [FAW-1:0]	RX_FIFO_LEVEL_WIRE;
-	assign	RX_FIFO_LEVEL_WIRE[(FAW - 1) : 0] = rx_level;
-
-	reg [FAW-1:0]	RX_FIFO_THRESHOLD_REG;
-	assign	rxfifotr	=	RX_FIFO_THRESHOLD_REG[(FAW - 1) : 0];
-	`WB_REG(RX_FIFO_THRESHOLD_REG, 0, FAW)
-
-	reg [0:0]	RX_FIFO_FLUSH_REG;
-	assign	rx_fifo_flush	=	RX_FIFO_FLUSH_REG[0 : 0];
-	`WB_REG_AC(RX_FIFO_FLUSH_REG, 0, 1, 1'h0)
-
-	wire [FAW-1:0]	TX_FIFO_LEVEL_WIRE;
-	assign	TX_FIFO_LEVEL_WIRE[(FAW - 1) : 0] = tx_level;
-
-	reg [FAW-1:0]	TX_FIFO_THRESHOLD_REG;
-	assign	txfifotr	=	TX_FIFO_THRESHOLD_REG[(FAW - 1) : 0];
-	`WB_REG(TX_FIFO_THRESHOLD_REG, 0, FAW)
-
-	reg [0:0]	TX_FIFO_FLUSH_REG;
-	assign	tx_fifo_flush	=	TX_FIFO_FLUSH_REG[0 : 0];
-	`WB_REG_AC(TX_FIFO_FLUSH_REG, 0, 1, 1'h0)
-
-	localparam	GCLK_REG_OFFSET = `WB_AW'hFF10;
-	`WB_REG(GCLK_REG, 0, 1)
-
-	reg [9:0] IM_REG;
-	reg [9:0] IC_REG;
-	reg [9:0] RIS_REG;
-
-	`WB_MIS_REG(10)
-	`WB_REG(IM_REG, 0, 10)
-	`WB_IC_REG(10)
-
-	wire [0:0] TXE = tx_empty;
-	wire [0:0] RXF = rx_full;
-	wire [0:0] TXB = tx_level_below;
-	wire [0:0] RXA = rx_level_above;
-	wire [0:0] BRK = break_flag;
-	wire [0:0] MATCH = match_flag;
-	wire [0:0] FE = frame_error_flag;
-	wire [0:0] PRE = parity_error_flag;
-	wire [0:0] OR = overrun_flag;
-	wire [0:0] RTO = timeout_flag;
-
-
-	integer _i_;
-	`WB_BLOCK(RIS_REG, 0) else begin
-		for(_i_ = 0; _i_ < 1; _i_ = _i_ + 1) begin
-			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(TXE[_i_ - 0] == 1'b1) RIS_REG[_i_] <= 1'b1;
-		end
-		for(_i_ = 1; _i_ < 2; _i_ = _i_ + 1) begin
-			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(RXF[_i_ - 1] == 1'b1) RIS_REG[_i_] <= 1'b1;
-		end
-		for(_i_ = 2; _i_ < 3; _i_ = _i_ + 1) begin
-			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(TXB[_i_ - 2] == 1'b1) RIS_REG[_i_] <= 1'b1;
-		end
-		for(_i_ = 3; _i_ < 4; _i_ = _i_ + 1) begin
-			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(RXA[_i_ - 3] == 1'b1) RIS_REG[_i_] <= 1'b1;
-		end
-		for(_i_ = 4; _i_ < 5; _i_ = _i_ + 1) begin
-			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(BRK[_i_ - 4] == 1'b1) RIS_REG[_i_] <= 1'b1;
-		end
-		for(_i_ = 5; _i_ < 6; _i_ = _i_ + 1) begin
-			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(MATCH[_i_ - 5] == 1'b1) RIS_REG[_i_] <= 1'b1;
-		end
-		for(_i_ = 6; _i_ < 7; _i_ = _i_ + 1) begin
-			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(FE[_i_ - 6] == 1'b1) RIS_REG[_i_] <= 1'b1;
-		end
-		for(_i_ = 7; _i_ < 8; _i_ = _i_ + 1) begin
-			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(PRE[_i_ - 7] == 1'b1) RIS_REG[_i_] <= 1'b1;
-		end
-		for(_i_ = 8; _i_ < 9; _i_ = _i_ + 1) begin
-			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(OR[_i_ - 8] == 1'b1) RIS_REG[_i_] <= 1'b1;
-		end
-		for(_i_ = 9; _i_ < 10; _i_ = _i_ + 1) begin
-			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(RTO[_i_ - 9] == 1'b1) RIS_REG[_i_] <= 1'b1;
-		end
-	end
-
-	assign IRQ = |MIS_REG;
-
-	EF_UART #(
-		.SC(SC),
-		.MDW(MDW),
-		.GFLEN(GFLEN),
-		.FAW(FAW)
-	) instance_to_wrap (
-		.clk(clk),
-		.rst_n(rst_n),
-		.prescaler(prescaler),
-		.en(en),
-		.tx_en(tx_en),
-		.rx_en(rx_en),
-		.wdata(wdata),
-		.timeout_bits(timeout_bits),
-		.loopback_en(loopback_en),
-		.glitch_filter_en(glitch_filter_en),
-		.tx_level(tx_level),
-		.rx_level(rx_level),
-		.rd(rd),
-		.wr(wr),
-		.tx_fifo_flush(tx_fifo_flush),
-		.rx_fifo_flush(rx_fifo_flush),
-		.data_size(data_size),
-		.stop_bits_count(stop_bits_count),
-		.parity_type(parity_type),
-		.txfifotr(txfifotr),
-		.rxfifotr(rxfifotr),
-		.match_data(match_data),
-		.tx_empty(tx_empty),
-		.tx_full(tx_full),
-		.tx_level_below(tx_level_below),
-		.rdata(rdata),
-		.rx_empty(rx_empty),
-		.rx_full(rx_full),
-		.rx_level_above(rx_level_above),
-		.break_flag(break_flag),
-		.match_flag(match_flag),
-		.frame_error_flag(frame_error_flag),
-		.parity_error_flag(parity_error_flag),
-		.overrun_flag(overrun_flag),
-		.timeout_flag(timeout_flag),
-		.rx(rx),
-		.tx(tx)
-	);
-
-	assign	dat_o = 
-			(adr_i[`WB_AW-1:0] == RXDATA_REG_OFFSET)	? RXDATA_WIRE :
-			(adr_i[`WB_AW-1:0] == TXDATA_REG_OFFSET)	? TXDATA_WIRE :
-			(adr_i[`WB_AW-1:0] == PR_REG_OFFSET)	? PR_REG :
-			(adr_i[`WB_AW-1:0] == CTRL_REG_OFFSET)	? CTRL_REG :
-			(adr_i[`WB_AW-1:0] == CFG_REG_OFFSET)	? CFG_REG :
-			(adr_i[`WB_AW-1:0] == MATCH_REG_OFFSET)	? MATCH_REG :
-			(adr_i[`WB_AW-1:0] == RX_FIFO_LEVEL_REG_OFFSET)	? RX_FIFO_LEVEL_WIRE :
-			(adr_i[`WB_AW-1:0] == RX_FIFO_THRESHOLD_REG_OFFSET)	? RX_FIFO_THRESHOLD_REG :
-			(adr_i[`WB_AW-1:0] == RX_FIFO_FLUSH_REG_OFFSET)	? RX_FIFO_FLUSH_REG :
-			(adr_i[`WB_AW-1:0] == TX_FIFO_LEVEL_REG_OFFSET)	? TX_FIFO_LEVEL_WIRE :
-			(adr_i[`WB_AW-1:0] == TX_FIFO_THRESHOLD_REG_OFFSET)	? TX_FIFO_THRESHOLD_REG :
-			(adr_i[`WB_AW-1:0] == TX_FIFO_FLUSH_REG_OFFSET)	? TX_FIFO_FLUSH_REG :
-			(adr_i[`WB_AW-1:0] == IM_REG_OFFSET)	? IM_REG :
-			(adr_i[`WB_AW-1:0] == MIS_REG_OFFSET)	? MIS_REG :
-			(adr_i[`WB_AW-1:0] == RIS_REG_OFFSET)	? RIS_REG :
-			(adr_i[`WB_AW-1:0] == IC_REG_OFFSET)	? IC_REG :
+  localparam RXDATA_REG_OFFSET = 16'h0000;
+  localparam TXDATA_REG_OFFSET = 16'h0004;
+  localparam PR_REG_OFFSET = 16'h0008;
+  localparam CTRL_REG_OFFSET = 16'h000C;
+  localparam CFG_REG_OFFSET = 16'h0010;
+  localparam MATCH_REG_OFFSET = 16'h001C;
+  localparam RX_FIFO_LEVEL_REG_OFFSET = 16'hFE00;
+  localparam RX_FIFO_THRESHOLD_REG_OFFSET = 16'hFE04;
+  localparam RX_FIFO_FLUSH_REG_OFFSET = 16'hFE08;
+  localparam TX_FIFO_LEVEL_REG_OFFSET = 16'hFE10;
+  localparam TX_FIFO_THRESHOLD_REG_OFFSET = 16'hFE14;
+  localparam TX_FIFO_FLUSH_REG_OFFSET = 16'hFE18;
+  localparam IM_REG_OFFSET = 16'hFF00;
+  localparam MIS_REG_OFFSET = 16'hFF04;
+  localparam RIS_REG_OFFSET = 16'hFF08;
+  localparam IC_REG_OFFSET = 16'hFF0C;
+
+  reg [0:0] GCLK_REG;
+  wire clk_g;
+  wire clk_gated_en = GCLK_REG[0];
+  ef_util_gating_cell clk_gate_cell (
+
+
+
+      // USE_POWER_PINS
+      .clk(clk_i),
+      .clk_en(clk_gated_en),
+      .clk_o(clk_g)
+  );
+
+  wire           clk = clk_g;
+  wire           rst_n = (~rst_i);
+
+
+  wire           wb_valid = cyc_i & stb_i;
+  wire           wb_we = we_i & wb_valid;
+  wire           wb_re = ~we_i & wb_valid;
+  wire [    3:0] wb_byte_sel = sel_i & {4{wb_we}};
+
+  wire [ 16-1:0] prescaler;
+  wire [  1-1:0] en;
+  wire [  1-1:0] tx_en;
+  wire [  1-1:0] rx_en;
+  wire [MDW-1:0] wdata;
+  wire [  6-1:0] timeout_bits;
+  wire [  1-1:0] loopback_en;
+  wire [  1-1:0] glitch_filter_en;
+  wire [FAW-1:0] tx_level;
+  wire [FAW-1:0] rx_level;
+  wire [  1-1:0] rd;
+  wire [  1-1:0] wr;
+  wire [  1-1:0] tx_fifo_flush;
+  wire [  1-1:0] rx_fifo_flush;
+  wire [  4-1:0] data_size;
+  wire [  1-1:0] stop_bits_count;
+  wire [  3-1:0] parity_type;
+  wire [FAW-1:0] txfifotr;
+  wire [FAW-1:0] rxfifotr;
+  wire [MDW-1:0] match_data;
+  wire [  1-1:0] tx_empty;
+  wire [  1-1:0] tx_full;
+  wire [  1-1:0] tx_level_below;
+  wire [MDW-1:0] rdata;
+  wire [  1-1:0] rx_empty;
+  wire [  1-1:0] rx_full;
+  wire [  1-1:0] rx_level_above;
+  wire [  1-1:0] break_flag;
+  wire [  1-1:0] match_flag;
+  wire [  1-1:0] frame_error_flag;
+  wire [  1-1:0] parity_error_flag;
+  wire [  1-1:0] overrun_flag;
+  wire [  1-1:0] timeout_flag;
+
+  // Register Definitions
+  wire [MDW-1:0] RXDATA_WIRE;
+
+  wire [MDW-1:0] TXDATA_WIRE;
+
+  reg  [   15:0] PR_REG;
+  assign prescaler = PR_REG;
+  always @(posedge clk_i or posedge rst_i)
+    if (rst_i) PR_REG <= 0;
+    else if (wb_we & (adr_i[16-1:0] == PR_REG_OFFSET)) PR_REG <= dat_i[16-1:0];
+
+  reg [4:0] CTRL_REG;
+  assign en = CTRL_REG[0 : 0];
+  assign tx_en = CTRL_REG[1 : 1];
+  assign rx_en = CTRL_REG[2 : 2];
+  assign loopback_en = CTRL_REG[3 : 3];
+  assign glitch_filter_en = CTRL_REG[4 : 4];
+  always @(posedge clk_i or posedge rst_i)
+    if (rst_i) CTRL_REG <= 0;
+    else if (wb_we & (adr_i[16-1:0] == CTRL_REG_OFFSET)) CTRL_REG <= dat_i[5-1:0];
+
+  reg [13:0] CFG_REG;
+  assign data_size = CFG_REG[3 : 0];
+  assign stop_bits_count = CFG_REG[4 : 4];
+  assign parity_type = CFG_REG[7 : 5];
+  assign timeout_bits = CFG_REG[13 : 8];
+  always @(posedge clk_i or posedge rst_i)
+    if (rst_i) CFG_REG <= 'h3F08;
+    else if (wb_we & (adr_i[16-1:0] == CFG_REG_OFFSET)) CFG_REG <= dat_i[14-1:0];
+
+  reg [MDW-1:0] MATCH_REG;
+  assign match_data = MATCH_REG;
+  always @(posedge clk_i or posedge rst_i)
+    if (rst_i) MATCH_REG <= 0;
+    else if (wb_we & (adr_i[16-1:0] == MATCH_REG_OFFSET)) MATCH_REG <= dat_i[MDW-1:0];
+
+  wire [FAW-1:0] RX_FIFO_LEVEL_WIRE;
+  assign RX_FIFO_LEVEL_WIRE[(FAW-1) : 0] = rx_level;
+
+  reg [FAW-1:0] RX_FIFO_THRESHOLD_REG;
+  assign rxfifotr = RX_FIFO_THRESHOLD_REG[(FAW-1) : 0];
+  always @(posedge clk_i or posedge rst_i)
+    if (rst_i) RX_FIFO_THRESHOLD_REG <= 0;
+    else if (wb_we & (adr_i[16-1:0] == RX_FIFO_THRESHOLD_REG_OFFSET))
+      RX_FIFO_THRESHOLD_REG <= dat_i[FAW-1:0];
+
+  reg [0:0] RX_FIFO_FLUSH_REG;
+  assign rx_fifo_flush = RX_FIFO_FLUSH_REG[0 : 0];
+  always @(posedge clk_i or posedge rst_i)
+    if (rst_i) RX_FIFO_FLUSH_REG <= 0;
+    else if (wb_we & (adr_i[16-1:0] == RX_FIFO_FLUSH_REG_OFFSET)) RX_FIFO_FLUSH_REG <= dat_i[1-1:0];
+    else RX_FIFO_FLUSH_REG <= 1'h0 & RX_FIFO_FLUSH_REG;
+
+  wire [FAW-1:0] TX_FIFO_LEVEL_WIRE;
+  assign TX_FIFO_LEVEL_WIRE[(FAW-1) : 0] = tx_level;
+
+  reg [FAW-1:0] TX_FIFO_THRESHOLD_REG;
+  assign txfifotr = TX_FIFO_THRESHOLD_REG[(FAW-1) : 0];
+  always @(posedge clk_i or posedge rst_i)
+    if (rst_i) TX_FIFO_THRESHOLD_REG <= 0;
+    else if (wb_we & (adr_i[16-1:0] == TX_FIFO_THRESHOLD_REG_OFFSET))
+      TX_FIFO_THRESHOLD_REG <= dat_i[FAW-1:0];
+
+  reg [0:0] TX_FIFO_FLUSH_REG;
+  assign tx_fifo_flush = TX_FIFO_FLUSH_REG[0 : 0];
+  always @(posedge clk_i or posedge rst_i)
+    if (rst_i) TX_FIFO_FLUSH_REG <= 0;
+    else if (wb_we & (adr_i[16-1:0] == TX_FIFO_FLUSH_REG_OFFSET)) TX_FIFO_FLUSH_REG <= dat_i[1-1:0];
+    else TX_FIFO_FLUSH_REG <= 1'h0 & TX_FIFO_FLUSH_REG;
+
+  localparam GCLK_REG_OFFSET = 16'hFF10;
+  always @(posedge clk_i or posedge rst_i)
+    if (rst_i) GCLK_REG <= 0;
+    else if (wb_we & (adr_i[16-1:0] == GCLK_REG_OFFSET)) GCLK_REG <= dat_i[1-1:0];
+
+  reg  [   9:0] IM_REG;
+  reg  [   9:0] IC_REG;
+  reg  [   9:0] RIS_REG;
+
+  wire [10-1:0] MIS_REG = RIS_REG & IM_REG;
+  always @(posedge clk_i or posedge rst_i)
+    if (rst_i) IM_REG <= 0;
+    else if (wb_we & (adr_i[16-1:0] == IM_REG_OFFSET)) IM_REG <= dat_i[10-1:0];
+  always @(posedge clk_i or posedge rst_i)
+    if (rst_i) IC_REG <= 10'b0;
+    else if (wb_we & (adr_i[16-1:0] == IC_REG_OFFSET)) IC_REG <= dat_i[10-1:0];
+    else IC_REG <= 10'd0;
+
+  wire [0:0] TXE = tx_empty;
+  wire [0:0] RXF = rx_full;
+  wire [0:0] TXB = tx_level_below;
+  wire [0:0] RXA = rx_level_above;
+  wire [0:0] BRK = break_flag;
+  wire [0:0] MATCH = match_flag;
+  wire [0:0] FE = frame_error_flag;
+  wire [0:0] PRE = parity_error_flag;
+  wire [0:0] OR = overrun_flag;
+  wire [0:0] RTO = timeout_flag;
+
+
+  integer _i_;
+  always @(posedge clk_i or posedge rst_i)
+    if (rst_i) RIS_REG <= 0;
+    else begin
+      for (_i_ = 0; _i_ < 1; _i_ = _i_ + 1) begin
+        if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+        else if (TXE[_i_-0] == 1'b1) RIS_REG[_i_] <= 1'b1;
+      end
+      for (_i_ = 1; _i_ < 2; _i_ = _i_ + 1) begin
+        if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+        else if (RXF[_i_-1] == 1'b1) RIS_REG[_i_] <= 1'b1;
+      end
+      for (_i_ = 2; _i_ < 3; _i_ = _i_ + 1) begin
+        if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+        else if (TXB[_i_-2] == 1'b1) RIS_REG[_i_] <= 1'b1;
+      end
+      for (_i_ = 3; _i_ < 4; _i_ = _i_ + 1) begin
+        if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+        else if (RXA[_i_-3] == 1'b1) RIS_REG[_i_] <= 1'b1;
+      end
+      for (_i_ = 4; _i_ < 5; _i_ = _i_ + 1) begin
+        if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+        else if (BRK[_i_-4] == 1'b1) RIS_REG[_i_] <= 1'b1;
+      end
+      for (_i_ = 5; _i_ < 6; _i_ = _i_ + 1) begin
+        if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+        else if (MATCH[_i_-5] == 1'b1) RIS_REG[_i_] <= 1'b1;
+      end
+      for (_i_ = 6; _i_ < 7; _i_ = _i_ + 1) begin
+        if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+        else if (FE[_i_-6] == 1'b1) RIS_REG[_i_] <= 1'b1;
+      end
+      for (_i_ = 7; _i_ < 8; _i_ = _i_ + 1) begin
+        if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+        else if (PRE[_i_-7] == 1'b1) RIS_REG[_i_] <= 1'b1;
+      end
+      for (_i_ = 8; _i_ < 9; _i_ = _i_ + 1) begin
+        if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+        else if (OR[_i_-8] == 1'b1) RIS_REG[_i_] <= 1'b1;
+      end
+      for (_i_ = 9; _i_ < 10; _i_ = _i_ + 1) begin
+        if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+        else if (RTO[_i_-9] == 1'b1) RIS_REG[_i_] <= 1'b1;
+      end
+    end
+
+  assign IRQ = |MIS_REG;
+
+  EF_UART #(
+      .SC(SC),
+      .MDW(MDW),
+      .GFLEN(GFLEN),
+      .FAW(FAW)
+  ) instance_to_wrap (
+      .clk(clk),
+      .rst_n(rst_n),
+      .prescaler(prescaler),
+      .en(en),
+      .tx_en(tx_en),
+      .rx_en(rx_en),
+      .wdata(wdata),
+      .timeout_bits(timeout_bits),
+      .loopback_en(loopback_en),
+      .glitch_filter_en(glitch_filter_en),
+      .tx_level(tx_level),
+      .rx_level(rx_level),
+      .rd(rd),
+      .wr(wr),
+      .tx_fifo_flush(tx_fifo_flush),
+      .rx_fifo_flush(rx_fifo_flush),
+      .data_size(data_size),
+      .stop_bits_count(stop_bits_count),
+      .parity_type(parity_type),
+      .txfifotr(txfifotr),
+      .rxfifotr(rxfifotr),
+      .match_data(match_data),
+      .tx_empty(tx_empty),
+      .tx_full(tx_full),
+      .tx_level_below(tx_level_below),
+      .rdata(rdata),
+      .rx_empty(rx_empty),
+      .rx_full(rx_full),
+      .rx_level_above(rx_level_above),
+      .break_flag(break_flag),
+      .match_flag(match_flag),
+      .frame_error_flag(frame_error_flag),
+      .parity_error_flag(parity_error_flag),
+      .overrun_flag(overrun_flag),
+      .timeout_flag(timeout_flag),
+      .rx(rx),
+      .tx(tx)
+  );
+
+  assign	dat_o = 
+			(adr_i[16-1:0] == RXDATA_REG_OFFSET)	? RXDATA_WIRE :
+			(adr_i[16-1:0] == TXDATA_REG_OFFSET)	? TXDATA_WIRE :
+			(adr_i[16-1:0] == PR_REG_OFFSET)	? PR_REG :
+			(adr_i[16-1:0] == CTRL_REG_OFFSET)	? CTRL_REG :
+			(adr_i[16-1:0] == CFG_REG_OFFSET)	? CFG_REG :
+			(adr_i[16-1:0] == MATCH_REG_OFFSET)	? MATCH_REG :
+			(adr_i[16-1:0] == RX_FIFO_LEVEL_REG_OFFSET)	? RX_FIFO_LEVEL_WIRE :
+			(adr_i[16-1:0] == RX_FIFO_THRESHOLD_REG_OFFSET)	? RX_FIFO_THRESHOLD_REG :
+			(adr_i[16-1:0] == RX_FIFO_FLUSH_REG_OFFSET)	? RX_FIFO_FLUSH_REG :
+			(adr_i[16-1:0] == TX_FIFO_LEVEL_REG_OFFSET)	? TX_FIFO_LEVEL_WIRE :
+			(adr_i[16-1:0] == TX_FIFO_THRESHOLD_REG_OFFSET)	? TX_FIFO_THRESHOLD_REG :
+			(adr_i[16-1:0] == TX_FIFO_FLUSH_REG_OFFSET)	? TX_FIFO_FLUSH_REG :
+			(adr_i[16-1:0] == IM_REG_OFFSET)	? IM_REG :
+			(adr_i[16-1:0] == MIS_REG_OFFSET)	? MIS_REG :
+			(adr_i[16-1:0] == RIS_REG_OFFSET)	? RIS_REG :
+			(adr_i[16-1:0] == IC_REG_OFFSET)	? IC_REG :
 			32'hDEADBEEF;
 
-	always @ (posedge clk_i or posedge rst_i)
-		if(rst_i)
-			ack_o <= 1'b0;
-		else if(wb_valid & ~ack_o)
-			ack_o <= 1'b1;
-		else
-			ack_o <= 1'b0;
-	assign	RXDATA_WIRE = rdata;
-	assign	rd =  ack_o & (wb_re & (adr_i[`WB_AW-1:0] == RXDATA_REG_OFFSET));
-	assign	wdata = dat_i;
-	assign	wr = ack_o & (wb_we & (adr_i[`WB_AW-1:0] == TXDATA_REG_OFFSET));
+  always @(posedge clk_i or posedge rst_i)
+    if (rst_i) ack_o <= 1'b0;
+    else if (wb_valid & ~ack_o) ack_o <= 1'b1;
+    else ack_o <= 1'b0;
+  assign RXDATA_WIRE = rdata;
+  assign rd = ack_o & (wb_re & (adr_i[16-1:0] == RXDATA_REG_OFFSET));
+  assign wdata = dat_i;
+  assign wr = ack_o & (wb_we & (adr_i[16-1:0] == TXDATA_REG_OFFSET));
 endmodule
diff --git a/hdl/rtl/bus_wrappers/dft/EF_UART_AHBL_DFT.dev.v b/hdl/rtl/bus_wrappers/dft/EF_UART_AHBL_DFT.dev.v
new file mode 100644
index 0000000..ec322ca
--- /dev/null
+++ b/hdl/rtl/bus_wrappers/dft/EF_UART_AHBL_DFT.dev.v
@@ -0,0 +1,295 @@
+/*
+	Copyright 2024 Efabless Corp.
+
+	Author: Mohamed Shalan (mshalan@efabless.com)
+
+	Licensed under the Apache License, Version 2.0 (the "License");
+	you may not use this file except in compliance with the License.
+	You may obtain a copy of the License at
+
+	    http://www.apache.org/licenses/LICENSE-2.0
+
+	Unless required by applicable law or agreed to in writing, software
+	distributed under the License is distributed on an "AS IS" BASIS,
+	WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+	See the License for the specific language governing permissions and
+	limitations under the License.
+
+*/
+
+/* THIS FILE IS GENERATED, DO NOT EDIT */
+
+`timescale			1ns/1ps
+`default_nettype	none
+
+`define				AHBL_AW		16
+
+`include			"ahbl_wrapper.vh"
+
+module EF_UART_AHBL #( 
+	parameter	
+		SC = 8,
+		MDW = 9,
+		GFLEN = 8,
+		FAW = 4
+) (
+`ifdef USE_POWER_PINS
+	inout VPWR,
+	inout VGND,
+`endif
+	input	wire	sc_testmode,
+	`AHBL_SLAVE_PORTS,
+	input	wire	[1-1:0]	rx,
+	output	wire	[1-1:0]	tx
+);
+
+	localparam	RXDATA_REG_OFFSET = `AHBL_AW'h0000;
+	localparam	TXDATA_REG_OFFSET = `AHBL_AW'h0004;
+	localparam	PR_REG_OFFSET = `AHBL_AW'h0008;
+	localparam	CTRL_REG_OFFSET = `AHBL_AW'h000C;
+	localparam	CFG_REG_OFFSET = `AHBL_AW'h0010;
+	localparam	MATCH_REG_OFFSET = `AHBL_AW'h001C;
+	localparam	RX_FIFO_LEVEL_REG_OFFSET = `AHBL_AW'hFE00;
+	localparam	RX_FIFO_THRESHOLD_REG_OFFSET = `AHBL_AW'hFE04;
+	localparam	RX_FIFO_FLUSH_REG_OFFSET = `AHBL_AW'hFE08;
+	localparam	TX_FIFO_LEVEL_REG_OFFSET = `AHBL_AW'hFE10;
+	localparam	TX_FIFO_THRESHOLD_REG_OFFSET = `AHBL_AW'hFE14;
+	localparam	TX_FIFO_FLUSH_REG_OFFSET = `AHBL_AW'hFE18;
+	localparam	IM_REG_OFFSET = `AHBL_AW'hFF00;
+	localparam	MIS_REG_OFFSET = `AHBL_AW'hFF04;
+	localparam	RIS_REG_OFFSET = `AHBL_AW'hFF08;
+	localparam	IC_REG_OFFSET = `AHBL_AW'hFF0C;
+
+    reg [0:0] GCLK_REG;
+    wire clk_g;
+    wire clk_gated_en = sc_testmode ? 1'b1 : GCLK_REG[0];
+    ef_util_gating_cell clk_gate_cell(
+        `ifdef USE_POWER_PINS 
+        .vpwr(VPWR),
+        .vgnd(VGND),
+        `endif // USE_POWER_PINS
+        .clk(HCLK),
+        .clk_en(clk_gated_en),
+        .clk_o(clk_g)
+    );
+    
+	wire		clk = clk_g;
+	wire		rst_n = HRESETn;
+
+
+	`AHBL_CTRL_SIGNALS
+
+	wire [16-1:0]	prescaler;
+	wire [1-1:0]	en;
+	wire [1-1:0]	tx_en;
+	wire [1-1:0]	rx_en;
+	wire [MDW-1:0]	wdata;
+	wire [6-1:0]	timeout_bits;
+	wire [1-1:0]	loopback_en;
+	wire [1-1:0]	glitch_filter_en;
+	wire [FAW-1:0]	tx_level;
+	wire [FAW-1:0]	rx_level;
+	wire [1-1:0]	rd;
+	wire [1-1:0]	wr;
+	wire [1-1:0]	tx_fifo_flush;
+	wire [1-1:0]	rx_fifo_flush;
+	wire [4-1:0]	data_size;
+	wire [1-1:0]	stop_bits_count;
+	wire [3-1:0]	parity_type;
+	wire [FAW-1:0]	txfifotr;
+	wire [FAW-1:0]	rxfifotr;
+	wire [MDW-1:0]	match_data;
+	wire [1-1:0]	tx_empty;
+	wire [1-1:0]	tx_full;
+	wire [1-1:0]	tx_level_below;
+	wire [MDW-1:0]	rdata;
+	wire [1-1:0]	rx_empty;
+	wire [1-1:0]	rx_full;
+	wire [1-1:0]	rx_level_above;
+	wire [1-1:0]	break_flag;
+	wire [1-1:0]	match_flag;
+	wire [1-1:0]	frame_error_flag;
+	wire [1-1:0]	parity_error_flag;
+	wire [1-1:0]	overrun_flag;
+	wire [1-1:0]	timeout_flag;
+
+	// Register Definitions
+	wire	[MDW-1:0]	RXDATA_WIRE;
+
+	wire	[MDW-1:0]	TXDATA_WIRE;
+
+	reg [15:0]	PR_REG;
+	assign	prescaler = PR_REG;
+	`AHBL_REG(PR_REG, 0, 16)
+
+	reg [4:0]	CTRL_REG;
+	assign	en	=	CTRL_REG[0 : 0];
+	assign	tx_en	=	CTRL_REG[1 : 1];
+	assign	rx_en	=	CTRL_REG[2 : 2];
+	assign	loopback_en	=	CTRL_REG[3 : 3];
+	assign	glitch_filter_en	=	CTRL_REG[4 : 4];
+	`AHBL_REG(CTRL_REG, 0, 5)
+
+	reg [13:0]	CFG_REG;
+	assign	data_size	=	CFG_REG[3 : 0];
+	assign	stop_bits_count	=	CFG_REG[4 : 4];
+	assign	parity_type	=	CFG_REG[7 : 5];
+	assign	timeout_bits	=	CFG_REG[13 : 8];
+	`AHBL_REG(CFG_REG, 'h3F08, 14)
+
+	reg [MDW-1:0]	MATCH_REG;
+	assign	match_data = MATCH_REG;
+	`AHBL_REG(MATCH_REG, 0, MDW)
+
+	wire [FAW-1:0]	RX_FIFO_LEVEL_WIRE;
+	assign	RX_FIFO_LEVEL_WIRE[(FAW - 1) : 0] = rx_level;
+
+	reg [FAW-1:0]	RX_FIFO_THRESHOLD_REG;
+	assign	rxfifotr	=	RX_FIFO_THRESHOLD_REG[(FAW - 1) : 0];
+	`AHBL_REG(RX_FIFO_THRESHOLD_REG, 0, FAW)
+
+	reg [0:0]	RX_FIFO_FLUSH_REG;
+	assign	rx_fifo_flush	=	RX_FIFO_FLUSH_REG[0 : 0];
+	`AHBL_REG_AC(RX_FIFO_FLUSH_REG, 0, 1, 1'h0)
+
+	wire [FAW-1:0]	TX_FIFO_LEVEL_WIRE;
+	assign	TX_FIFO_LEVEL_WIRE[(FAW - 1) : 0] = tx_level;
+
+	reg [FAW-1:0]	TX_FIFO_THRESHOLD_REG;
+	assign	txfifotr	=	TX_FIFO_THRESHOLD_REG[(FAW - 1) : 0];
+	`AHBL_REG(TX_FIFO_THRESHOLD_REG, 0, FAW)
+
+	reg [0:0]	TX_FIFO_FLUSH_REG;
+	assign	tx_fifo_flush	=	TX_FIFO_FLUSH_REG[0 : 0];
+	`AHBL_REG_AC(TX_FIFO_FLUSH_REG, 0, 1, 1'h0)
+
+	localparam	GCLK_REG_OFFSET = `AHBL_AW'hFF10;
+	`AHBL_REG(GCLK_REG, 0, 1)
+
+	reg [9:0] IM_REG;
+	reg [9:0] IC_REG;
+	reg [9:0] RIS_REG;
+
+	`AHBL_MIS_REG(10)
+	`AHBL_REG(IM_REG, 0, 10)
+	`AHBL_IC_REG(10)
+
+	wire [0:0] TXE = tx_empty;
+	wire [0:0] RXF = rx_full;
+	wire [0:0] TXB = tx_level_below;
+	wire [0:0] RXA = rx_level_above;
+	wire [0:0] BRK = break_flag;
+	wire [0:0] MATCH = match_flag;
+	wire [0:0] FE = frame_error_flag;
+	wire [0:0] PRE = parity_error_flag;
+	wire [0:0] OR = overrun_flag;
+	wire [0:0] RTO = timeout_flag;
+
+
+	integer _i_;
+	`AHBL_BLOCK(RIS_REG, 0) else begin
+		for(_i_ = 0; _i_ < 1; _i_ = _i_ + 1) begin
+			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(TXE[_i_ - 0] == 1'b1) RIS_REG[_i_] <= 1'b1;
+		end
+		for(_i_ = 1; _i_ < 2; _i_ = _i_ + 1) begin
+			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(RXF[_i_ - 1] == 1'b1) RIS_REG[_i_] <= 1'b1;
+		end
+		for(_i_ = 2; _i_ < 3; _i_ = _i_ + 1) begin
+			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(TXB[_i_ - 2] == 1'b1) RIS_REG[_i_] <= 1'b1;
+		end
+		for(_i_ = 3; _i_ < 4; _i_ = _i_ + 1) begin
+			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(RXA[_i_ - 3] == 1'b1) RIS_REG[_i_] <= 1'b1;
+		end
+		for(_i_ = 4; _i_ < 5; _i_ = _i_ + 1) begin
+			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(BRK[_i_ - 4] == 1'b1) RIS_REG[_i_] <= 1'b1;
+		end
+		for(_i_ = 5; _i_ < 6; _i_ = _i_ + 1) begin
+			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(MATCH[_i_ - 5] == 1'b1) RIS_REG[_i_] <= 1'b1;
+		end
+		for(_i_ = 6; _i_ < 7; _i_ = _i_ + 1) begin
+			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(FE[_i_ - 6] == 1'b1) RIS_REG[_i_] <= 1'b1;
+		end
+		for(_i_ = 7; _i_ < 8; _i_ = _i_ + 1) begin
+			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(PRE[_i_ - 7] == 1'b1) RIS_REG[_i_] <= 1'b1;
+		end
+		for(_i_ = 8; _i_ < 9; _i_ = _i_ + 1) begin
+			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(OR[_i_ - 8] == 1'b1) RIS_REG[_i_] <= 1'b1;
+		end
+		for(_i_ = 9; _i_ < 10; _i_ = _i_ + 1) begin
+			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(RTO[_i_ - 9] == 1'b1) RIS_REG[_i_] <= 1'b1;
+		end
+	end
+
+	assign IRQ = |MIS_REG;
+
+	EF_UART #(
+		.SC(SC),
+		.MDW(MDW),
+		.GFLEN(GFLEN),
+		.FAW(FAW)
+	) instance_to_wrap (
+		.clk(clk),
+		.rst_n(rst_n),
+		.prescaler(prescaler),
+		.en(en),
+		.tx_en(tx_en),
+		.rx_en(rx_en),
+		.wdata(wdata),
+		.timeout_bits(timeout_bits),
+		.loopback_en(loopback_en),
+		.glitch_filter_en(glitch_filter_en),
+		.tx_level(tx_level),
+		.rx_level(rx_level),
+		.rd(rd),
+		.wr(wr),
+		.tx_fifo_flush(tx_fifo_flush),
+		.rx_fifo_flush(rx_fifo_flush),
+		.data_size(data_size),
+		.stop_bits_count(stop_bits_count),
+		.parity_type(parity_type),
+		.txfifotr(txfifotr),
+		.rxfifotr(rxfifotr),
+		.match_data(match_data),
+		.tx_empty(tx_empty),
+		.tx_full(tx_full),
+		.tx_level_below(tx_level_below),
+		.rdata(rdata),
+		.rx_empty(rx_empty),
+		.rx_full(rx_full),
+		.rx_level_above(rx_level_above),
+		.break_flag(break_flag),
+		.match_flag(match_flag),
+		.frame_error_flag(frame_error_flag),
+		.parity_error_flag(parity_error_flag),
+		.overrun_flag(overrun_flag),
+		.timeout_flag(timeout_flag),
+		.rx(rx),
+		.tx(tx)
+	);
+
+	assign	HRDATA = 
+			(last_HADDR[`AHBL_AW-1:0] == RXDATA_REG_OFFSET)	? RXDATA_WIRE :
+			(last_HADDR[`AHBL_AW-1:0] == TXDATA_REG_OFFSET)	? TXDATA_WIRE :
+			(last_HADDR[`AHBL_AW-1:0] == PR_REG_OFFSET)	? PR_REG :
+			(last_HADDR[`AHBL_AW-1:0] == CTRL_REG_OFFSET)	? CTRL_REG :
+			(last_HADDR[`AHBL_AW-1:0] == CFG_REG_OFFSET)	? CFG_REG :
+			(last_HADDR[`AHBL_AW-1:0] == MATCH_REG_OFFSET)	? MATCH_REG :
+			(last_HADDR[`AHBL_AW-1:0] == RX_FIFO_LEVEL_REG_OFFSET)	? RX_FIFO_LEVEL_WIRE :
+			(last_HADDR[`AHBL_AW-1:0] == RX_FIFO_THRESHOLD_REG_OFFSET)	? RX_FIFO_THRESHOLD_REG :
+			(last_HADDR[`AHBL_AW-1:0] == RX_FIFO_FLUSH_REG_OFFSET)	? RX_FIFO_FLUSH_REG :
+			(last_HADDR[`AHBL_AW-1:0] == TX_FIFO_LEVEL_REG_OFFSET)	? TX_FIFO_LEVEL_WIRE :
+			(last_HADDR[`AHBL_AW-1:0] == TX_FIFO_THRESHOLD_REG_OFFSET)	? TX_FIFO_THRESHOLD_REG :
+			(last_HADDR[`AHBL_AW-1:0] == TX_FIFO_FLUSH_REG_OFFSET)	? TX_FIFO_FLUSH_REG :
+			(last_HADDR[`AHBL_AW-1:0] == IM_REG_OFFSET)	? IM_REG :
+			(last_HADDR[`AHBL_AW-1:0] == MIS_REG_OFFSET)	? MIS_REG :
+			(last_HADDR[`AHBL_AW-1:0] == RIS_REG_OFFSET)	? RIS_REG :
+			(last_HADDR[`AHBL_AW-1:0] == GCLK_REG_OFFSET)	? GCLK_REG :
+			32'hDEADBEEF;
+
+	assign	HREADYOUT = 1'b1;
+
+	assign	RXDATA_WIRE = rdata;
+	assign	rd = (ahbl_re & (last_HADDR[`AHBL_AW-1:0] == RXDATA_REG_OFFSET));
+	assign	wdata = HWDATA;
+	assign	wr = (ahbl_we & (last_HADDR[`AHBL_AW-1:0] == TXDATA_REG_OFFSET));
+endmodule
diff --git a/hdl/rtl/bus_wrappers/dft/EF_UART_AHBL_DFT.v b/hdl/rtl/bus_wrappers/dft/EF_UART_AHBL_DFT.v
new file mode 100644
index 0000000..fa2e911
--- /dev/null
+++ b/hdl/rtl/bus_wrappers/dft/EF_UART_AHBL_DFT.v
@@ -0,0 +1,435 @@
+/*
+	Copyright 2024 Efabless Corp.
+
+	Author: Mohamed Shalan (mshalan@efabless.com)
+
+	Licensed under the Apache License, Version 2.0 (the "License");
+	you may not use this file except in compliance with the License.
+	You may obtain a copy of the License at
+
+	    http://www.apache.org/licenses/LICENSE-2.0
+
+	Unless required by applicable law or agreed to in writing, software
+	distributed under the License is distributed on an "AS IS" BASIS,
+	WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+	See the License for the specific language governing permissions and
+	limitations under the License.
+
+*/
+
+/* THIS FILE IS GENERATED, DO NOT EDIT */
+
+`timescale 1ns / 1ps `default_nettype none
+
+
+
+/*
+	Copyright 2020 AUCOHL
+
+    Author: Mohamed Shalan (mshalan@aucegypt.edu)
+	
+	Licensed under the Apache License, Version 2.0 (the "License"); 
+	you may not use this file except in compliance with the License. 
+	You may obtain a copy of the License at:
+
+	http://www.apache.org/licenses/LICENSE-2.0
+
+	Unless required by applicable law or agreed to in writing, software 
+	distributed under the License is distributed on an "AS IS" BASIS, 
+	WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 
+	See the License for the specific language governing permissions and 
+	limitations under the License.
+*/
+
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+
+
+module EF_UART_AHBL #(
+    parameter SC = 8,
+    MDW = 9,
+    GFLEN = 8,
+    FAW = 4
+) (
+
+
+
+
+    input  wire         sc_testmode,
+    input  wire         HCLK,
+    input  wire         HRESETn,
+    input  wire         HWRITE,
+    input  wire [ 31:0] HWDATA,
+    input  wire [ 31:0] HADDR,
+    input  wire [  1:0] HTRANS,
+    input  wire         HSEL,
+    input  wire         HREADY,
+    output wire         HREADYOUT,
+    output wire [ 31:0] HRDATA,
+    output wire         IRQ,
+    input  wire [1-1:0] rx,
+    output wire [1-1:0] tx
+);
+
+  localparam RXDATA_REG_OFFSET = 16'h0000;
+  localparam TXDATA_REG_OFFSET = 16'h0004;
+  localparam PR_REG_OFFSET = 16'h0008;
+  localparam CTRL_REG_OFFSET = 16'h000C;
+  localparam CFG_REG_OFFSET = 16'h0010;
+  localparam MATCH_REG_OFFSET = 16'h001C;
+  localparam RX_FIFO_LEVEL_REG_OFFSET = 16'hFE00;
+  localparam RX_FIFO_THRESHOLD_REG_OFFSET = 16'hFE04;
+  localparam RX_FIFO_FLUSH_REG_OFFSET = 16'hFE08;
+  localparam TX_FIFO_LEVEL_REG_OFFSET = 16'hFE10;
+  localparam TX_FIFO_THRESHOLD_REG_OFFSET = 16'hFE14;
+  localparam TX_FIFO_FLUSH_REG_OFFSET = 16'hFE18;
+  localparam IM_REG_OFFSET = 16'hFF00;
+  localparam MIS_REG_OFFSET = 16'hFF04;
+  localparam RIS_REG_OFFSET = 16'hFF08;
+  localparam IC_REG_OFFSET = 16'hFF0C;
+
+  reg [0:0] GCLK_REG;
+  wire clk_g;
+  wire clk_gated_en = sc_testmode ? 1'b1 : GCLK_REG[0];
+  ef_util_gating_cell clk_gate_cell (
+
+
+
+      // USE_POWER_PINS
+      .clk(HCLK),
+      .clk_en(clk_gated_en),
+      .clk_o(clk_g)
+  );
+
+  wire clk = clk_g;
+  wire rst_n = HRESETn;
+
+
+  reg last_HSEL, last_HWRITE;
+  reg [31:0] last_HADDR;
+  reg [ 1:0] last_HTRANS;
+  always @(posedge HCLK or negedge HRESETn) begin
+    if (~HRESETn) begin
+      last_HSEL   <= 1'b0;
+      last_HADDR  <= 1'b0;
+      last_HWRITE <= 1'b0;
+      last_HTRANS <= 1'b0;
+    end else if (HREADY) begin
+      last_HSEL   <= HSEL;
+      last_HADDR  <= HADDR;
+      last_HWRITE <= HWRITE;
+      last_HTRANS <= HTRANS;
+    end
+  end
+  wire    ahbl_valid = last_HSEL & last_HTRANS[1];
+  wire ahbl_we = last_HWRITE & ahbl_valid;
+  wire ahbl_re = ~last_HWRITE & ahbl_valid;
+
+  wire [16-1:0] prescaler;
+  wire [1-1:0] en;
+  wire [1-1:0] tx_en;
+  wire [1-1:0] rx_en;
+  wire [MDW-1:0] wdata;
+  wire [6-1:0] timeout_bits;
+  wire [1-1:0] loopback_en;
+  wire [1-1:0] glitch_filter_en;
+  wire [FAW-1:0] tx_level;
+  wire [FAW-1:0] rx_level;
+  wire [1-1:0] rd;
+  wire [1-1:0] wr;
+  wire [1-1:0] tx_fifo_flush;
+  wire [1-1:0] rx_fifo_flush;
+  wire [4-1:0] data_size;
+  wire [1-1:0] stop_bits_count;
+  wire [3-1:0] parity_type;
+  wire [FAW-1:0] txfifotr;
+  wire [FAW-1:0] rxfifotr;
+  wire [MDW-1:0] match_data;
+  wire [1-1:0] tx_empty;
+  wire [1-1:0] tx_full;
+  wire [1-1:0] tx_level_below;
+  wire [MDW-1:0] rdata;
+  wire [1-1:0] rx_empty;
+  wire [1-1:0] rx_full;
+  wire [1-1:0] rx_level_above;
+  wire [1-1:0] break_flag;
+  wire [1-1:0] match_flag;
+  wire [1-1:0] frame_error_flag;
+  wire [1-1:0] parity_error_flag;
+  wire [1-1:0] overrun_flag;
+  wire [1-1:0] timeout_flag;
+
+  // Register Definitions
+  wire [MDW-1:0] RXDATA_WIRE;
+
+  wire [MDW-1:0] TXDATA_WIRE;
+
+  reg [15:0] PR_REG;
+  assign prescaler = PR_REG;
+  always @(posedge HCLK or negedge HRESETn)
+    if (~HRESETn) PR_REG <= 0;
+    else if (ahbl_we & (last_HADDR[16-1:0] == PR_REG_OFFSET)) PR_REG <= HWDATA[16-1:0];
+
+  reg [4:0] CTRL_REG;
+  assign en = CTRL_REG[0 : 0];
+  assign tx_en = CTRL_REG[1 : 1];
+  assign rx_en = CTRL_REG[2 : 2];
+  assign loopback_en = CTRL_REG[3 : 3];
+  assign glitch_filter_en = CTRL_REG[4 : 4];
+  always @(posedge HCLK or negedge HRESETn)
+    if (~HRESETn) CTRL_REG <= 0;
+    else if (ahbl_we & (last_HADDR[16-1:0] == CTRL_REG_OFFSET)) CTRL_REG <= HWDATA[5-1:0];
+
+  reg [13:0] CFG_REG;
+  assign data_size = CFG_REG[3 : 0];
+  assign stop_bits_count = CFG_REG[4 : 4];
+  assign parity_type = CFG_REG[7 : 5];
+  assign timeout_bits = CFG_REG[13 : 8];
+  always @(posedge HCLK or negedge HRESETn)
+    if (~HRESETn) CFG_REG <= 'h3F08;
+    else if (ahbl_we & (last_HADDR[16-1:0] == CFG_REG_OFFSET)) CFG_REG <= HWDATA[14-1:0];
+
+  reg [MDW-1:0] MATCH_REG;
+  assign match_data = MATCH_REG;
+  always @(posedge HCLK or negedge HRESETn)
+    if (~HRESETn) MATCH_REG <= 0;
+    else if (ahbl_we & (last_HADDR[16-1:0] == MATCH_REG_OFFSET)) MATCH_REG <= HWDATA[MDW-1:0];
+
+  wire [FAW-1:0] RX_FIFO_LEVEL_WIRE;
+  assign RX_FIFO_LEVEL_WIRE[(FAW-1) : 0] = rx_level;
+
+  reg [FAW-1:0] RX_FIFO_THRESHOLD_REG;
+  assign rxfifotr = RX_FIFO_THRESHOLD_REG[(FAW-1) : 0];
+  always @(posedge HCLK or negedge HRESETn)
+    if (~HRESETn) RX_FIFO_THRESHOLD_REG <= 0;
+    else if (ahbl_we & (last_HADDR[16-1:0] == RX_FIFO_THRESHOLD_REG_OFFSET))
+      RX_FIFO_THRESHOLD_REG <= HWDATA[FAW-1:0];
+
+  reg [0:0] RX_FIFO_FLUSH_REG;
+  assign rx_fifo_flush = RX_FIFO_FLUSH_REG[0 : 0];
+  always @(posedge HCLK or negedge HRESETn)
+    if (~HRESETn) RX_FIFO_FLUSH_REG <= 0;
+    else if (ahbl_we & (last_HADDR[16-1:0] == RX_FIFO_FLUSH_REG_OFFSET))
+      RX_FIFO_FLUSH_REG <= HWDATA[1-1:0];
+    else RX_FIFO_FLUSH_REG <= 1'h0 & RX_FIFO_FLUSH_REG;
+
+  wire [FAW-1:0] TX_FIFO_LEVEL_WIRE;
+  assign TX_FIFO_LEVEL_WIRE[(FAW-1) : 0] = tx_level;
+
+  reg [FAW-1:0] TX_FIFO_THRESHOLD_REG;
+  assign txfifotr = TX_FIFO_THRESHOLD_REG[(FAW-1) : 0];
+  always @(posedge HCLK or negedge HRESETn)
+    if (~HRESETn) TX_FIFO_THRESHOLD_REG <= 0;
+    else if (ahbl_we & (last_HADDR[16-1:0] == TX_FIFO_THRESHOLD_REG_OFFSET))
+      TX_FIFO_THRESHOLD_REG <= HWDATA[FAW-1:0];
+
+  reg [0:0] TX_FIFO_FLUSH_REG;
+  assign tx_fifo_flush = TX_FIFO_FLUSH_REG[0 : 0];
+  always @(posedge HCLK or negedge HRESETn)
+    if (~HRESETn) TX_FIFO_FLUSH_REG <= 0;
+    else if (ahbl_we & (last_HADDR[16-1:0] == TX_FIFO_FLUSH_REG_OFFSET))
+      TX_FIFO_FLUSH_REG <= HWDATA[1-1:0];
+    else TX_FIFO_FLUSH_REG <= 1'h0 & TX_FIFO_FLUSH_REG;
+
+  localparam GCLK_REG_OFFSET = 16'hFF10;
+  always @(posedge HCLK or negedge HRESETn)
+    if (~HRESETn) GCLK_REG <= 0;
+    else if (ahbl_we & (last_HADDR[16-1:0] == GCLK_REG_OFFSET)) GCLK_REG <= HWDATA[1-1:0];
+
+  reg  [   9:0] IM_REG;
+  reg  [   9:0] IC_REG;
+  reg  [   9:0] RIS_REG;
+
+  wire [10-1:0] MIS_REG = RIS_REG & IM_REG;
+  always @(posedge HCLK or negedge HRESETn)
+    if (~HRESETn) IM_REG <= 0;
+    else if (ahbl_we & (last_HADDR[16-1:0] == IM_REG_OFFSET)) IM_REG <= HWDATA[10-1:0];
+  always @(posedge HCLK or negedge HRESETn)
+    if (~HRESETn) IC_REG <= 10'b0;
+    else if (ahbl_we & (last_HADDR[16-1:0] == IC_REG_OFFSET)) IC_REG <= HWDATA[10-1:0];
+    else IC_REG <= 10'd0;
+
+  wire [0:0] TXE = tx_empty;
+  wire [0:0] RXF = rx_full;
+  wire [0:0] TXB = tx_level_below;
+  wire [0:0] RXA = rx_level_above;
+  wire [0:0] BRK = break_flag;
+  wire [0:0] MATCH = match_flag;
+  wire [0:0] FE = frame_error_flag;
+  wire [0:0] PRE = parity_error_flag;
+  wire [0:0] OR = overrun_flag;
+  wire [0:0] RTO = timeout_flag;
+
+
+  integer _i_;
+  always @(posedge HCLK or negedge HRESETn)
+    if (~HRESETn) RIS_REG <= 0;
+    else begin
+      for (_i_ = 0; _i_ < 1; _i_ = _i_ + 1) begin
+        if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+        else if (TXE[_i_-0] == 1'b1) RIS_REG[_i_] <= 1'b1;
+      end
+      for (_i_ = 1; _i_ < 2; _i_ = _i_ + 1) begin
+        if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+        else if (RXF[_i_-1] == 1'b1) RIS_REG[_i_] <= 1'b1;
+      end
+      for (_i_ = 2; _i_ < 3; _i_ = _i_ + 1) begin
+        if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+        else if (TXB[_i_-2] == 1'b1) RIS_REG[_i_] <= 1'b1;
+      end
+      for (_i_ = 3; _i_ < 4; _i_ = _i_ + 1) begin
+        if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+        else if (RXA[_i_-3] == 1'b1) RIS_REG[_i_] <= 1'b1;
+      end
+      for (_i_ = 4; _i_ < 5; _i_ = _i_ + 1) begin
+        if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+        else if (BRK[_i_-4] == 1'b1) RIS_REG[_i_] <= 1'b1;
+      end
+      for (_i_ = 5; _i_ < 6; _i_ = _i_ + 1) begin
+        if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+        else if (MATCH[_i_-5] == 1'b1) RIS_REG[_i_] <= 1'b1;
+      end
+      for (_i_ = 6; _i_ < 7; _i_ = _i_ + 1) begin
+        if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+        else if (FE[_i_-6] == 1'b1) RIS_REG[_i_] <= 1'b1;
+      end
+      for (_i_ = 7; _i_ < 8; _i_ = _i_ + 1) begin
+        if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+        else if (PRE[_i_-7] == 1'b1) RIS_REG[_i_] <= 1'b1;
+      end
+      for (_i_ = 8; _i_ < 9; _i_ = _i_ + 1) begin
+        if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+        else if (OR[_i_-8] == 1'b1) RIS_REG[_i_] <= 1'b1;
+      end
+      for (_i_ = 9; _i_ < 10; _i_ = _i_ + 1) begin
+        if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+        else if (RTO[_i_-9] == 1'b1) RIS_REG[_i_] <= 1'b1;
+      end
+    end
+
+  assign IRQ = |MIS_REG;
+
+  EF_UART #(
+      .SC(SC),
+      .MDW(MDW),
+      .GFLEN(GFLEN),
+      .FAW(FAW)
+  ) instance_to_wrap (
+      .clk(clk),
+      .rst_n(rst_n),
+      .prescaler(prescaler),
+      .en(en),
+      .tx_en(tx_en),
+      .rx_en(rx_en),
+      .wdata(wdata),
+      .timeout_bits(timeout_bits),
+      .loopback_en(loopback_en),
+      .glitch_filter_en(glitch_filter_en),
+      .tx_level(tx_level),
+      .rx_level(rx_level),
+      .rd(rd),
+      .wr(wr),
+      .tx_fifo_flush(tx_fifo_flush),
+      .rx_fifo_flush(rx_fifo_flush),
+      .data_size(data_size),
+      .stop_bits_count(stop_bits_count),
+      .parity_type(parity_type),
+      .txfifotr(txfifotr),
+      .rxfifotr(rxfifotr),
+      .match_data(match_data),
+      .tx_empty(tx_empty),
+      .tx_full(tx_full),
+      .tx_level_below(tx_level_below),
+      .rdata(rdata),
+      .rx_empty(rx_empty),
+      .rx_full(rx_full),
+      .rx_level_above(rx_level_above),
+      .break_flag(break_flag),
+      .match_flag(match_flag),
+      .frame_error_flag(frame_error_flag),
+      .parity_error_flag(parity_error_flag),
+      .overrun_flag(overrun_flag),
+      .timeout_flag(timeout_flag),
+      .rx(rx),
+      .tx(tx)
+  );
+
+  assign	HRDATA = 
+			(last_HADDR[16-1:0] == RXDATA_REG_OFFSET)	? RXDATA_WIRE :
+			(last_HADDR[16-1:0] == TXDATA_REG_OFFSET)	? TXDATA_WIRE :
+			(last_HADDR[16-1:0] == PR_REG_OFFSET)	? PR_REG :
+			(last_HADDR[16-1:0] == CTRL_REG_OFFSET)	? CTRL_REG :
+			(last_HADDR[16-1:0] == CFG_REG_OFFSET)	? CFG_REG :
+			(last_HADDR[16-1:0] == MATCH_REG_OFFSET)	? MATCH_REG :
+			(last_HADDR[16-1:0] == RX_FIFO_LEVEL_REG_OFFSET)	? RX_FIFO_LEVEL_WIRE :
+			(last_HADDR[16-1:0] == RX_FIFO_THRESHOLD_REG_OFFSET)	? RX_FIFO_THRESHOLD_REG :
+			(last_HADDR[16-1:0] == RX_FIFO_FLUSH_REG_OFFSET)	? RX_FIFO_FLUSH_REG :
+			(last_HADDR[16-1:0] == TX_FIFO_LEVEL_REG_OFFSET)	? TX_FIFO_LEVEL_WIRE :
+			(last_HADDR[16-1:0] == TX_FIFO_THRESHOLD_REG_OFFSET)	? TX_FIFO_THRESHOLD_REG :
+			(last_HADDR[16-1:0] == TX_FIFO_FLUSH_REG_OFFSET)	? TX_FIFO_FLUSH_REG :
+			(last_HADDR[16-1:0] == IM_REG_OFFSET)	? IM_REG :
+			(last_HADDR[16-1:0] == MIS_REG_OFFSET)	? MIS_REG :
+			(last_HADDR[16-1:0] == RIS_REG_OFFSET)	? RIS_REG :
+			(last_HADDR[16-1:0] == GCLK_REG_OFFSET)	? GCLK_REG :
+			32'hDEADBEEF;
+
+  assign HREADYOUT = 1'b1;
+
+  assign RXDATA_WIRE = rdata;
+  assign rd = (ahbl_re & (last_HADDR[16-1:0] == RXDATA_REG_OFFSET));
+  assign wdata = HWDATA;
+  assign wr = (ahbl_we & (last_HADDR[16-1:0] == TXDATA_REG_OFFSET));
+endmodule
diff --git a/hdl/rtl/bus_wrappers/dft/EF_UART_APB_DFT.dev.v b/hdl/rtl/bus_wrappers/dft/EF_UART_APB_DFT.dev.v
new file mode 100644
index 0000000..3d4fe31
--- /dev/null
+++ b/hdl/rtl/bus_wrappers/dft/EF_UART_APB_DFT.dev.v
@@ -0,0 +1,295 @@
+/*
+	Copyright 2024 Efabless Corp.
+
+	Author: Mohamed Shalan (mshalan@efabless.com)
+
+	Licensed under the Apache License, Version 2.0 (the "License");
+	you may not use this file except in compliance with the License.
+	You may obtain a copy of the License at
+
+	    http://www.apache.org/licenses/LICENSE-2.0
+
+	Unless required by applicable law or agreed to in writing, software
+	distributed under the License is distributed on an "AS IS" BASIS,
+	WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+	See the License for the specific language governing permissions and
+	limitations under the License.
+
+*/
+
+/* THIS FILE IS GENERATED, DO NOT EDIT */
+
+`timescale			1ns/1ps
+`default_nettype	none
+
+`define				APB_AW		16
+
+`include			"apb_wrapper.vh"
+
+module EF_UART_APB #( 
+	parameter	
+		SC = 8,
+		MDW = 9,
+		GFLEN = 8,
+		FAW = 4
+) (
+`ifdef USE_POWER_PINS
+	inout VPWR,
+	inout VGND,
+`endif
+	input	wire	sc_testmode,
+	`APB_SLAVE_PORTS,
+	input	wire	[1-1:0]	rx,
+	output	wire	[1-1:0]	tx
+);
+
+	localparam	RXDATA_REG_OFFSET = `APB_AW'h0000;
+	localparam	TXDATA_REG_OFFSET = `APB_AW'h0004;
+	localparam	PR_REG_OFFSET = `APB_AW'h0008;
+	localparam	CTRL_REG_OFFSET = `APB_AW'h000C;
+	localparam	CFG_REG_OFFSET = `APB_AW'h0010;
+	localparam	MATCH_REG_OFFSET = `APB_AW'h001C;
+	localparam	RX_FIFO_LEVEL_REG_OFFSET = `APB_AW'hFE00;
+	localparam	RX_FIFO_THRESHOLD_REG_OFFSET = `APB_AW'hFE04;
+	localparam	RX_FIFO_FLUSH_REG_OFFSET = `APB_AW'hFE08;
+	localparam	TX_FIFO_LEVEL_REG_OFFSET = `APB_AW'hFE10;
+	localparam	TX_FIFO_THRESHOLD_REG_OFFSET = `APB_AW'hFE14;
+	localparam	TX_FIFO_FLUSH_REG_OFFSET = `APB_AW'hFE18;
+	localparam	IM_REG_OFFSET = `APB_AW'hFF00;
+	localparam	MIS_REG_OFFSET = `APB_AW'hFF04;
+	localparam	RIS_REG_OFFSET = `APB_AW'hFF08;
+	localparam	IC_REG_OFFSET = `APB_AW'hFF0C;
+
+    reg [0:0] GCLK_REG;
+    wire clk_g;
+    wire clk_gated_en = sc_testmode ? 1'b1 : GCLK_REG[0];
+    ef_util_gating_cell clk_gate_cell(
+        `ifdef USE_POWER_PINS 
+        .vpwr(VPWR),
+        .vgnd(VGND),
+        `endif // USE_POWER_PINS
+        .clk(PCLK),
+        .clk_en(clk_gated_en),
+        .clk_o(clk_g)
+    );
+    
+	wire		clk = clk_g;
+	wire		rst_n = PRESETn;
+
+
+	`APB_CTRL_SIGNALS
+
+	wire [16-1:0]	prescaler;
+	wire [1-1:0]	en;
+	wire [1-1:0]	tx_en;
+	wire [1-1:0]	rx_en;
+	wire [MDW-1:0]	wdata;
+	wire [6-1:0]	timeout_bits;
+	wire [1-1:0]	loopback_en;
+	wire [1-1:0]	glitch_filter_en;
+	wire [FAW-1:0]	tx_level;
+	wire [FAW-1:0]	rx_level;
+	wire [1-1:0]	rd;
+	wire [1-1:0]	wr;
+	wire [1-1:0]	tx_fifo_flush;
+	wire [1-1:0]	rx_fifo_flush;
+	wire [4-1:0]	data_size;
+	wire [1-1:0]	stop_bits_count;
+	wire [3-1:0]	parity_type;
+	wire [FAW-1:0]	txfifotr;
+	wire [FAW-1:0]	rxfifotr;
+	wire [MDW-1:0]	match_data;
+	wire [1-1:0]	tx_empty;
+	wire [1-1:0]	tx_full;
+	wire [1-1:0]	tx_level_below;
+	wire [MDW-1:0]	rdata;
+	wire [1-1:0]	rx_empty;
+	wire [1-1:0]	rx_full;
+	wire [1-1:0]	rx_level_above;
+	wire [1-1:0]	break_flag;
+	wire [1-1:0]	match_flag;
+	wire [1-1:0]	frame_error_flag;
+	wire [1-1:0]	parity_error_flag;
+	wire [1-1:0]	overrun_flag;
+	wire [1-1:0]	timeout_flag;
+
+	// Register Definitions
+	wire	[MDW-1:0]	RXDATA_WIRE;
+
+	wire	[MDW-1:0]	TXDATA_WIRE;
+
+	reg [15:0]	PR_REG;
+	assign	prescaler = PR_REG;
+	`APB_REG(PR_REG, 0, 16)
+
+	reg [4:0]	CTRL_REG;
+	assign	en	=	CTRL_REG[0 : 0];
+	assign	tx_en	=	CTRL_REG[1 : 1];
+	assign	rx_en	=	CTRL_REG[2 : 2];
+	assign	loopback_en	=	CTRL_REG[3 : 3];
+	assign	glitch_filter_en	=	CTRL_REG[4 : 4];
+	`APB_REG(CTRL_REG, 0, 5)
+
+	reg [13:0]	CFG_REG;
+	assign	data_size	=	CFG_REG[3 : 0];
+	assign	stop_bits_count	=	CFG_REG[4 : 4];
+	assign	parity_type	=	CFG_REG[7 : 5];
+	assign	timeout_bits	=	CFG_REG[13 : 8];
+	`APB_REG(CFG_REG, 'h3F08, 14)
+
+	reg [MDW-1:0]	MATCH_REG;
+	assign	match_data = MATCH_REG;
+	`APB_REG(MATCH_REG, 0, MDW)
+
+	wire [FAW-1:0]	RX_FIFO_LEVEL_WIRE;
+	assign	RX_FIFO_LEVEL_WIRE[(FAW - 1) : 0] = rx_level;
+
+	reg [FAW-1:0]	RX_FIFO_THRESHOLD_REG;
+	assign	rxfifotr	=	RX_FIFO_THRESHOLD_REG[(FAW - 1) : 0];
+	`APB_REG(RX_FIFO_THRESHOLD_REG, 0, FAW)
+
+	reg [0:0]	RX_FIFO_FLUSH_REG;
+	assign	rx_fifo_flush	=	RX_FIFO_FLUSH_REG[0 : 0];
+	`APB_REG_AC(RX_FIFO_FLUSH_REG, 0, 1, 1'h0)
+
+	wire [FAW-1:0]	TX_FIFO_LEVEL_WIRE;
+	assign	TX_FIFO_LEVEL_WIRE[(FAW - 1) : 0] = tx_level;
+
+	reg [FAW-1:0]	TX_FIFO_THRESHOLD_REG;
+	assign	txfifotr	=	TX_FIFO_THRESHOLD_REG[(FAW - 1) : 0];
+	`APB_REG(TX_FIFO_THRESHOLD_REG, 0, FAW)
+
+	reg [0:0]	TX_FIFO_FLUSH_REG;
+	assign	tx_fifo_flush	=	TX_FIFO_FLUSH_REG[0 : 0];
+	`APB_REG_AC(TX_FIFO_FLUSH_REG, 0, 1, 1'h0)
+
+	localparam	GCLK_REG_OFFSET = `APB_AW'hFF10;
+	`APB_REG(GCLK_REG, 0, 1)
+
+	reg [9:0] IM_REG;
+	reg [9:0] IC_REG;
+	reg [9:0] RIS_REG;
+
+	`APB_MIS_REG(10)
+	`APB_REG(IM_REG, 0, 10)
+	`APB_IC_REG(10)
+
+	wire [0:0] TXE = tx_empty;
+	wire [0:0] RXF = rx_full;
+	wire [0:0] TXB = tx_level_below;
+	wire [0:0] RXA = rx_level_above;
+	wire [0:0] BRK = break_flag;
+	wire [0:0] MATCH = match_flag;
+	wire [0:0] FE = frame_error_flag;
+	wire [0:0] PRE = parity_error_flag;
+	wire [0:0] OR = overrun_flag;
+	wire [0:0] RTO = timeout_flag;
+
+
+	integer _i_;
+	`APB_BLOCK(RIS_REG, 0) else begin
+		for(_i_ = 0; _i_ < 1; _i_ = _i_ + 1) begin
+			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(TXE[_i_ - 0] == 1'b1) RIS_REG[_i_] <= 1'b1;
+		end
+		for(_i_ = 1; _i_ < 2; _i_ = _i_ + 1) begin
+			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(RXF[_i_ - 1] == 1'b1) RIS_REG[_i_] <= 1'b1;
+		end
+		for(_i_ = 2; _i_ < 3; _i_ = _i_ + 1) begin
+			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(TXB[_i_ - 2] == 1'b1) RIS_REG[_i_] <= 1'b1;
+		end
+		for(_i_ = 3; _i_ < 4; _i_ = _i_ + 1) begin
+			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(RXA[_i_ - 3] == 1'b1) RIS_REG[_i_] <= 1'b1;
+		end
+		for(_i_ = 4; _i_ < 5; _i_ = _i_ + 1) begin
+			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(BRK[_i_ - 4] == 1'b1) RIS_REG[_i_] <= 1'b1;
+		end
+		for(_i_ = 5; _i_ < 6; _i_ = _i_ + 1) begin
+			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(MATCH[_i_ - 5] == 1'b1) RIS_REG[_i_] <= 1'b1;
+		end
+		for(_i_ = 6; _i_ < 7; _i_ = _i_ + 1) begin
+			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(FE[_i_ - 6] == 1'b1) RIS_REG[_i_] <= 1'b1;
+		end
+		for(_i_ = 7; _i_ < 8; _i_ = _i_ + 1) begin
+			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(PRE[_i_ - 7] == 1'b1) RIS_REG[_i_] <= 1'b1;
+		end
+		for(_i_ = 8; _i_ < 9; _i_ = _i_ + 1) begin
+			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(OR[_i_ - 8] == 1'b1) RIS_REG[_i_] <= 1'b1;
+		end
+		for(_i_ = 9; _i_ < 10; _i_ = _i_ + 1) begin
+			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(RTO[_i_ - 9] == 1'b1) RIS_REG[_i_] <= 1'b1;
+		end
+	end
+
+	assign IRQ = |MIS_REG;
+
+	EF_UART #(
+		.SC(SC),
+		.MDW(MDW),
+		.GFLEN(GFLEN),
+		.FAW(FAW)
+	) instance_to_wrap (
+		.clk(clk),
+		.rst_n(rst_n),
+		.prescaler(prescaler),
+		.en(en),
+		.tx_en(tx_en),
+		.rx_en(rx_en),
+		.wdata(wdata),
+		.timeout_bits(timeout_bits),
+		.loopback_en(loopback_en),
+		.glitch_filter_en(glitch_filter_en),
+		.tx_level(tx_level),
+		.rx_level(rx_level),
+		.rd(rd),
+		.wr(wr),
+		.tx_fifo_flush(tx_fifo_flush),
+		.rx_fifo_flush(rx_fifo_flush),
+		.data_size(data_size),
+		.stop_bits_count(stop_bits_count),
+		.parity_type(parity_type),
+		.txfifotr(txfifotr),
+		.rxfifotr(rxfifotr),
+		.match_data(match_data),
+		.tx_empty(tx_empty),
+		.tx_full(tx_full),
+		.tx_level_below(tx_level_below),
+		.rdata(rdata),
+		.rx_empty(rx_empty),
+		.rx_full(rx_full),
+		.rx_level_above(rx_level_above),
+		.break_flag(break_flag),
+		.match_flag(match_flag),
+		.frame_error_flag(frame_error_flag),
+		.parity_error_flag(parity_error_flag),
+		.overrun_flag(overrun_flag),
+		.timeout_flag(timeout_flag),
+		.rx(rx),
+		.tx(tx)
+	);
+
+	assign	PRDATA = 
+			(PADDR[`APB_AW-1:0] == RXDATA_REG_OFFSET)	? RXDATA_WIRE :
+			(PADDR[`APB_AW-1:0] == TXDATA_REG_OFFSET)	? TXDATA_WIRE :
+			(PADDR[`APB_AW-1:0] == PR_REG_OFFSET)	? PR_REG :
+			(PADDR[`APB_AW-1:0] == CTRL_REG_OFFSET)	? CTRL_REG :
+			(PADDR[`APB_AW-1:0] == CFG_REG_OFFSET)	? CFG_REG :
+			(PADDR[`APB_AW-1:0] == MATCH_REG_OFFSET)	? MATCH_REG :
+			(PADDR[`APB_AW-1:0] == RX_FIFO_LEVEL_REG_OFFSET)	? RX_FIFO_LEVEL_WIRE :
+			(PADDR[`APB_AW-1:0] == RX_FIFO_THRESHOLD_REG_OFFSET)	? RX_FIFO_THRESHOLD_REG :
+			(PADDR[`APB_AW-1:0] == RX_FIFO_FLUSH_REG_OFFSET)	? RX_FIFO_FLUSH_REG :
+			(PADDR[`APB_AW-1:0] == TX_FIFO_LEVEL_REG_OFFSET)	? TX_FIFO_LEVEL_WIRE :
+			(PADDR[`APB_AW-1:0] == TX_FIFO_THRESHOLD_REG_OFFSET)	? TX_FIFO_THRESHOLD_REG :
+			(PADDR[`APB_AW-1:0] == TX_FIFO_FLUSH_REG_OFFSET)	? TX_FIFO_FLUSH_REG :
+			(PADDR[`APB_AW-1:0] == IM_REG_OFFSET)	? IM_REG :
+			(PADDR[`APB_AW-1:0] == MIS_REG_OFFSET)	? MIS_REG :
+			(PADDR[`APB_AW-1:0] == RIS_REG_OFFSET)	? RIS_REG :
+			(PADDR[`APB_AW-1:0] == GCLK_REG_OFFSET)	? GCLK_REG :
+			32'hDEADBEEF;
+
+	assign	PREADY = 1'b1;
+
+	assign	RXDATA_WIRE = rdata;
+	assign	rd = (apb_re & (PADDR[`APB_AW-1:0] == RXDATA_REG_OFFSET));
+	assign	wdata = PWDATA;
+	assign	wr = (apb_we & (PADDR[`APB_AW-1:0] == TXDATA_REG_OFFSET));
+endmodule
diff --git a/hdl/rtl/bus_wrappers/dft/EF_UART_APB_DFT.v b/hdl/rtl/bus_wrappers/dft/EF_UART_APB_DFT.v
new file mode 100644
index 0000000..67ed893
--- /dev/null
+++ b/hdl/rtl/bus_wrappers/dft/EF_UART_APB_DFT.v
@@ -0,0 +1,416 @@
+/*
+	Copyright 2024 Efabless Corp.
+
+	Author: Mohamed Shalan (mshalan@efabless.com)
+
+	Licensed under the Apache License, Version 2.0 (the "License");
+	you may not use this file except in compliance with the License.
+	You may obtain a copy of the License at
+
+	    http://www.apache.org/licenses/LICENSE-2.0
+
+	Unless required by applicable law or agreed to in writing, software
+	distributed under the License is distributed on an "AS IS" BASIS,
+	WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+	See the License for the specific language governing permissions and
+	limitations under the License.
+
+*/
+
+/* THIS FILE IS GENERATED, DO NOT EDIT */
+
+`timescale 1ns / 1ps `default_nettype none
+
+
+
+/*
+	Copyright 2020 AUCOHL
+
+    Author: Mohamed Shalan (mshalan@aucegypt.edu)
+	
+	Licensed under the Apache License, Version 2.0 (the "License"); 
+	you may not use this file except in compliance with the License. 
+	You may obtain a copy of the License at:
+
+	http://www.apache.org/licenses/LICENSE-2.0
+
+	Unless required by applicable law or agreed to in writing, software 
+	distributed under the License is distributed on an "AS IS" BASIS, 
+	WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 
+	See the License for the specific language governing permissions and 
+	limitations under the License.
+*/
+
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+
+module EF_UART_APB #(
+    parameter SC = 8,
+    MDW = 9,
+    GFLEN = 8,
+    FAW = 4
+) (
+
+
+
+
+    input  wire         sc_testmode,
+    input  wire         PCLK,
+    input  wire         PRESETn,
+    input  wire         PWRITE,
+    input  wire [ 31:0] PWDATA,
+    input  wire [ 31:0] PADDR,
+    input  wire         PENABLE,
+    input  wire         PSEL,
+    output wire         PREADY,
+    output wire [ 31:0] PRDATA,
+    output wire         IRQ,
+    input  wire [1-1:0] rx,
+    output wire [1-1:0] tx
+);
+
+  localparam RXDATA_REG_OFFSET = 16'h0000;
+  localparam TXDATA_REG_OFFSET = 16'h0004;
+  localparam PR_REG_OFFSET = 16'h0008;
+  localparam CTRL_REG_OFFSET = 16'h000C;
+  localparam CFG_REG_OFFSET = 16'h0010;
+  localparam MATCH_REG_OFFSET = 16'h001C;
+  localparam RX_FIFO_LEVEL_REG_OFFSET = 16'hFE00;
+  localparam RX_FIFO_THRESHOLD_REG_OFFSET = 16'hFE04;
+  localparam RX_FIFO_FLUSH_REG_OFFSET = 16'hFE08;
+  localparam TX_FIFO_LEVEL_REG_OFFSET = 16'hFE10;
+  localparam TX_FIFO_THRESHOLD_REG_OFFSET = 16'hFE14;
+  localparam TX_FIFO_FLUSH_REG_OFFSET = 16'hFE18;
+  localparam IM_REG_OFFSET = 16'hFF00;
+  localparam MIS_REG_OFFSET = 16'hFF04;
+  localparam RIS_REG_OFFSET = 16'hFF08;
+  localparam IC_REG_OFFSET = 16'hFF0C;
+
+  reg [0:0] GCLK_REG;
+  wire clk_g;
+  wire clk_gated_en = sc_testmode ? 1'b1 : GCLK_REG[0];
+  ef_util_gating_cell clk_gate_cell (
+
+
+
+      // USE_POWER_PINS
+      .clk(PCLK),
+      .clk_en(clk_gated_en),
+      .clk_o(clk_g)
+  );
+
+  wire           clk = clk_g;
+  wire           rst_n = PRESETn;
+
+
+  wire           apb_valid = PSEL & PENABLE;
+  wire           apb_we = PWRITE & apb_valid;
+  wire           apb_re = ~PWRITE & apb_valid;
+
+  wire [ 16-1:0] prescaler;
+  wire [  1-1:0] en;
+  wire [  1-1:0] tx_en;
+  wire [  1-1:0] rx_en;
+  wire [MDW-1:0] wdata;
+  wire [  6-1:0] timeout_bits;
+  wire [  1-1:0] loopback_en;
+  wire [  1-1:0] glitch_filter_en;
+  wire [FAW-1:0] tx_level;
+  wire [FAW-1:0] rx_level;
+  wire [  1-1:0] rd;
+  wire [  1-1:0] wr;
+  wire [  1-1:0] tx_fifo_flush;
+  wire [  1-1:0] rx_fifo_flush;
+  wire [  4-1:0] data_size;
+  wire [  1-1:0] stop_bits_count;
+  wire [  3-1:0] parity_type;
+  wire [FAW-1:0] txfifotr;
+  wire [FAW-1:0] rxfifotr;
+  wire [MDW-1:0] match_data;
+  wire [  1-1:0] tx_empty;
+  wire [  1-1:0] tx_full;
+  wire [  1-1:0] tx_level_below;
+  wire [MDW-1:0] rdata;
+  wire [  1-1:0] rx_empty;
+  wire [  1-1:0] rx_full;
+  wire [  1-1:0] rx_level_above;
+  wire [  1-1:0] break_flag;
+  wire [  1-1:0] match_flag;
+  wire [  1-1:0] frame_error_flag;
+  wire [  1-1:0] parity_error_flag;
+  wire [  1-1:0] overrun_flag;
+  wire [  1-1:0] timeout_flag;
+
+  // Register Definitions
+  wire [MDW-1:0] RXDATA_WIRE;
+
+  wire [MDW-1:0] TXDATA_WIRE;
+
+  reg  [   15:0] PR_REG;
+  assign prescaler = PR_REG;
+  always @(posedge PCLK or negedge PRESETn)
+    if (~PRESETn) PR_REG <= 0;
+    else if (apb_we & (PADDR[16-1:0] == PR_REG_OFFSET)) PR_REG <= PWDATA[16-1:0];
+
+  reg [4:0] CTRL_REG;
+  assign en = CTRL_REG[0 : 0];
+  assign tx_en = CTRL_REG[1 : 1];
+  assign rx_en = CTRL_REG[2 : 2];
+  assign loopback_en = CTRL_REG[3 : 3];
+  assign glitch_filter_en = CTRL_REG[4 : 4];
+  always @(posedge PCLK or negedge PRESETn)
+    if (~PRESETn) CTRL_REG <= 0;
+    else if (apb_we & (PADDR[16-1:0] == CTRL_REG_OFFSET)) CTRL_REG <= PWDATA[5-1:0];
+
+  reg [13:0] CFG_REG;
+  assign data_size = CFG_REG[3 : 0];
+  assign stop_bits_count = CFG_REG[4 : 4];
+  assign parity_type = CFG_REG[7 : 5];
+  assign timeout_bits = CFG_REG[13 : 8];
+  always @(posedge PCLK or negedge PRESETn)
+    if (~PRESETn) CFG_REG <= 'h3F08;
+    else if (apb_we & (PADDR[16-1:0] == CFG_REG_OFFSET)) CFG_REG <= PWDATA[14-1:0];
+
+  reg [MDW-1:0] MATCH_REG;
+  assign match_data = MATCH_REG;
+  always @(posedge PCLK or negedge PRESETn)
+    if (~PRESETn) MATCH_REG <= 0;
+    else if (apb_we & (PADDR[16-1:0] == MATCH_REG_OFFSET)) MATCH_REG <= PWDATA[MDW-1:0];
+
+  wire [FAW-1:0] RX_FIFO_LEVEL_WIRE;
+  assign RX_FIFO_LEVEL_WIRE[(FAW-1) : 0] = rx_level;
+
+  reg [FAW-1:0] RX_FIFO_THRESHOLD_REG;
+  assign rxfifotr = RX_FIFO_THRESHOLD_REG[(FAW-1) : 0];
+  always @(posedge PCLK or negedge PRESETn)
+    if (~PRESETn) RX_FIFO_THRESHOLD_REG <= 0;
+    else if (apb_we & (PADDR[16-1:0] == RX_FIFO_THRESHOLD_REG_OFFSET))
+      RX_FIFO_THRESHOLD_REG <= PWDATA[FAW-1:0];
+
+  reg [0:0] RX_FIFO_FLUSH_REG;
+  assign rx_fifo_flush = RX_FIFO_FLUSH_REG[0 : 0];
+  always @(posedge PCLK or negedge PRESETn)
+    if (~PRESETn) RX_FIFO_FLUSH_REG <= 0;
+    else if (apb_we & (PADDR[16-1:0] == RX_FIFO_FLUSH_REG_OFFSET))
+      RX_FIFO_FLUSH_REG <= PWDATA[1-1:0];
+    else RX_FIFO_FLUSH_REG <= 1'h0 & RX_FIFO_FLUSH_REG;
+
+  wire [FAW-1:0] TX_FIFO_LEVEL_WIRE;
+  assign TX_FIFO_LEVEL_WIRE[(FAW-1) : 0] = tx_level;
+
+  reg [FAW-1:0] TX_FIFO_THRESHOLD_REG;
+  assign txfifotr = TX_FIFO_THRESHOLD_REG[(FAW-1) : 0];
+  always @(posedge PCLK or negedge PRESETn)
+    if (~PRESETn) TX_FIFO_THRESHOLD_REG <= 0;
+    else if (apb_we & (PADDR[16-1:0] == TX_FIFO_THRESHOLD_REG_OFFSET))
+      TX_FIFO_THRESHOLD_REG <= PWDATA[FAW-1:0];
+
+  reg [0:0] TX_FIFO_FLUSH_REG;
+  assign tx_fifo_flush = TX_FIFO_FLUSH_REG[0 : 0];
+  always @(posedge PCLK or negedge PRESETn)
+    if (~PRESETn) TX_FIFO_FLUSH_REG <= 0;
+    else if (apb_we & (PADDR[16-1:0] == TX_FIFO_FLUSH_REG_OFFSET))
+      TX_FIFO_FLUSH_REG <= PWDATA[1-1:0];
+    else TX_FIFO_FLUSH_REG <= 1'h0 & TX_FIFO_FLUSH_REG;
+
+  localparam GCLK_REG_OFFSET = 16'hFF10;
+  always @(posedge PCLK or negedge PRESETn)
+    if (~PRESETn) GCLK_REG <= 0;
+    else if (apb_we & (PADDR[16-1:0] == GCLK_REG_OFFSET)) GCLK_REG <= PWDATA[1-1:0];
+
+  reg  [   9:0] IM_REG;
+  reg  [   9:0] IC_REG;
+  reg  [   9:0] RIS_REG;
+
+  wire [10-1:0] MIS_REG = RIS_REG & IM_REG;
+  always @(posedge PCLK or negedge PRESETn)
+    if (~PRESETn) IM_REG <= 0;
+    else if (apb_we & (PADDR[16-1:0] == IM_REG_OFFSET)) IM_REG <= PWDATA[10-1:0];
+  always @(posedge PCLK or negedge PRESETn)
+    if (~PRESETn) IC_REG <= 10'b0;
+    else if (apb_we & (PADDR[16-1:0] == IC_REG_OFFSET)) IC_REG <= PWDATA[10-1:0];
+    else IC_REG <= 10'd0;
+
+  wire [0:0] TXE = tx_empty;
+  wire [0:0] RXF = rx_full;
+  wire [0:0] TXB = tx_level_below;
+  wire [0:0] RXA = rx_level_above;
+  wire [0:0] BRK = break_flag;
+  wire [0:0] MATCH = match_flag;
+  wire [0:0] FE = frame_error_flag;
+  wire [0:0] PRE = parity_error_flag;
+  wire [0:0] OR = overrun_flag;
+  wire [0:0] RTO = timeout_flag;
+
+
+  integer _i_;
+  always @(posedge PCLK or negedge PRESETn)
+    if (~PRESETn) RIS_REG <= 0;
+    else begin
+      for (_i_ = 0; _i_ < 1; _i_ = _i_ + 1) begin
+        if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+        else if (TXE[_i_-0] == 1'b1) RIS_REG[_i_] <= 1'b1;
+      end
+      for (_i_ = 1; _i_ < 2; _i_ = _i_ + 1) begin
+        if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+        else if (RXF[_i_-1] == 1'b1) RIS_REG[_i_] <= 1'b1;
+      end
+      for (_i_ = 2; _i_ < 3; _i_ = _i_ + 1) begin
+        if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+        else if (TXB[_i_-2] == 1'b1) RIS_REG[_i_] <= 1'b1;
+      end
+      for (_i_ = 3; _i_ < 4; _i_ = _i_ + 1) begin
+        if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+        else if (RXA[_i_-3] == 1'b1) RIS_REG[_i_] <= 1'b1;
+      end
+      for (_i_ = 4; _i_ < 5; _i_ = _i_ + 1) begin
+        if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+        else if (BRK[_i_-4] == 1'b1) RIS_REG[_i_] <= 1'b1;
+      end
+      for (_i_ = 5; _i_ < 6; _i_ = _i_ + 1) begin
+        if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+        else if (MATCH[_i_-5] == 1'b1) RIS_REG[_i_] <= 1'b1;
+      end
+      for (_i_ = 6; _i_ < 7; _i_ = _i_ + 1) begin
+        if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+        else if (FE[_i_-6] == 1'b1) RIS_REG[_i_] <= 1'b1;
+      end
+      for (_i_ = 7; _i_ < 8; _i_ = _i_ + 1) begin
+        if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+        else if (PRE[_i_-7] == 1'b1) RIS_REG[_i_] <= 1'b1;
+      end
+      for (_i_ = 8; _i_ < 9; _i_ = _i_ + 1) begin
+        if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+        else if (OR[_i_-8] == 1'b1) RIS_REG[_i_] <= 1'b1;
+      end
+      for (_i_ = 9; _i_ < 10; _i_ = _i_ + 1) begin
+        if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+        else if (RTO[_i_-9] == 1'b1) RIS_REG[_i_] <= 1'b1;
+      end
+    end
+
+  assign IRQ = |MIS_REG;
+
+  EF_UART #(
+      .SC(SC),
+      .MDW(MDW),
+      .GFLEN(GFLEN),
+      .FAW(FAW)
+  ) instance_to_wrap (
+      .clk(clk),
+      .rst_n(rst_n),
+      .prescaler(prescaler),
+      .en(en),
+      .tx_en(tx_en),
+      .rx_en(rx_en),
+      .wdata(wdata),
+      .timeout_bits(timeout_bits),
+      .loopback_en(loopback_en),
+      .glitch_filter_en(glitch_filter_en),
+      .tx_level(tx_level),
+      .rx_level(rx_level),
+      .rd(rd),
+      .wr(wr),
+      .tx_fifo_flush(tx_fifo_flush),
+      .rx_fifo_flush(rx_fifo_flush),
+      .data_size(data_size),
+      .stop_bits_count(stop_bits_count),
+      .parity_type(parity_type),
+      .txfifotr(txfifotr),
+      .rxfifotr(rxfifotr),
+      .match_data(match_data),
+      .tx_empty(tx_empty),
+      .tx_full(tx_full),
+      .tx_level_below(tx_level_below),
+      .rdata(rdata),
+      .rx_empty(rx_empty),
+      .rx_full(rx_full),
+      .rx_level_above(rx_level_above),
+      .break_flag(break_flag),
+      .match_flag(match_flag),
+      .frame_error_flag(frame_error_flag),
+      .parity_error_flag(parity_error_flag),
+      .overrun_flag(overrun_flag),
+      .timeout_flag(timeout_flag),
+      .rx(rx),
+      .tx(tx)
+  );
+
+  assign	PRDATA = 
+			(PADDR[16-1:0] == RXDATA_REG_OFFSET)	? RXDATA_WIRE :
+			(PADDR[16-1:0] == TXDATA_REG_OFFSET)	? TXDATA_WIRE :
+			(PADDR[16-1:0] == PR_REG_OFFSET)	? PR_REG :
+			(PADDR[16-1:0] == CTRL_REG_OFFSET)	? CTRL_REG :
+			(PADDR[16-1:0] == CFG_REG_OFFSET)	? CFG_REG :
+			(PADDR[16-1:0] == MATCH_REG_OFFSET)	? MATCH_REG :
+			(PADDR[16-1:0] == RX_FIFO_LEVEL_REG_OFFSET)	? RX_FIFO_LEVEL_WIRE :
+			(PADDR[16-1:0] == RX_FIFO_THRESHOLD_REG_OFFSET)	? RX_FIFO_THRESHOLD_REG :
+			(PADDR[16-1:0] == RX_FIFO_FLUSH_REG_OFFSET)	? RX_FIFO_FLUSH_REG :
+			(PADDR[16-1:0] == TX_FIFO_LEVEL_REG_OFFSET)	? TX_FIFO_LEVEL_WIRE :
+			(PADDR[16-1:0] == TX_FIFO_THRESHOLD_REG_OFFSET)	? TX_FIFO_THRESHOLD_REG :
+			(PADDR[16-1:0] == TX_FIFO_FLUSH_REG_OFFSET)	? TX_FIFO_FLUSH_REG :
+			(PADDR[16-1:0] == IM_REG_OFFSET)	? IM_REG :
+			(PADDR[16-1:0] == MIS_REG_OFFSET)	? MIS_REG :
+			(PADDR[16-1:0] == RIS_REG_OFFSET)	? RIS_REG :
+			(PADDR[16-1:0] == GCLK_REG_OFFSET)	? GCLK_REG :
+			32'hDEADBEEF;
+
+  assign PREADY = 1'b1;
+
+  assign RXDATA_WIRE = rdata;
+  assign rd = (apb_re & (PADDR[16-1:0] == RXDATA_REG_OFFSET));
+  assign wdata = PWDATA;
+  assign wr = (apb_we & (PADDR[16-1:0] == TXDATA_REG_OFFSET));
+endmodule
diff --git a/hdl/rtl/bus_wrappers/dft/EF_UART_WB_DFT.dev.v b/hdl/rtl/bus_wrappers/dft/EF_UART_WB_DFT.dev.v
new file mode 100644
index 0000000..62f9553
--- /dev/null
+++ b/hdl/rtl/bus_wrappers/dft/EF_UART_WB_DFT.dev.v
@@ -0,0 +1,300 @@
+/*
+	Copyright 2024 Efabless Corp.
+
+	Author: Mohamed Shalan (mshalan@efabless.com)
+
+	Licensed under the Apache License, Version 2.0 (the "License");
+	you may not use this file except in compliance with the License.
+	You may obtain a copy of the License at
+
+	    http://www.apache.org/licenses/LICENSE-2.0
+
+	Unless required by applicable law or agreed to in writing, software
+	distributed under the License is distributed on an "AS IS" BASIS,
+	WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+	See the License for the specific language governing permissions and
+	limitations under the License.
+
+*/
+
+/* THIS FILE IS GENERATED, DO NOT EDIT */
+
+`timescale			1ns/1ps
+`default_nettype	none
+
+`define				WB_AW		16
+
+`include			"wb_wrapper.vh"
+
+module EF_UART_WB #( 
+	parameter	
+		SC = 8,
+		MDW = 9,
+		GFLEN = 8,
+		FAW = 4
+) (
+`ifdef USE_POWER_PINS
+	inout VPWR,
+	inout VGND,
+`endif
+	input	wire	sc_testmode,
+	`WB_SLAVE_PORTS,
+	input	wire	[1-1:0]	rx,
+	output	wire	[1-1:0]	tx
+);
+
+	localparam	RXDATA_REG_OFFSET = `WB_AW'h0000;
+	localparam	TXDATA_REG_OFFSET = `WB_AW'h0004;
+	localparam	PR_REG_OFFSET = `WB_AW'h0008;
+	localparam	CTRL_REG_OFFSET = `WB_AW'h000C;
+	localparam	CFG_REG_OFFSET = `WB_AW'h0010;
+	localparam	MATCH_REG_OFFSET = `WB_AW'h001C;
+	localparam	RX_FIFO_LEVEL_REG_OFFSET = `WB_AW'hFE00;
+	localparam	RX_FIFO_THRESHOLD_REG_OFFSET = `WB_AW'hFE04;
+	localparam	RX_FIFO_FLUSH_REG_OFFSET = `WB_AW'hFE08;
+	localparam	TX_FIFO_LEVEL_REG_OFFSET = `WB_AW'hFE10;
+	localparam	TX_FIFO_THRESHOLD_REG_OFFSET = `WB_AW'hFE14;
+	localparam	TX_FIFO_FLUSH_REG_OFFSET = `WB_AW'hFE18;
+	localparam	IM_REG_OFFSET = `WB_AW'hFF00;
+	localparam	MIS_REG_OFFSET = `WB_AW'hFF04;
+	localparam	RIS_REG_OFFSET = `WB_AW'hFF08;
+	localparam	IC_REG_OFFSET = `WB_AW'hFF0C;
+
+    reg [0:0] GCLK_REG;
+    wire clk_g;
+    wire clk_gated_en = sc_testmode ? 1'b1 : GCLK_REG[0];
+    ef_util_gating_cell clk_gate_cell(
+        `ifdef USE_POWER_PINS 
+        .vpwr(VPWR),
+        .vgnd(VGND),
+        `endif // USE_POWER_PINS
+        .clk(clk_i),
+        .clk_en(clk_gated_en),
+        .clk_o(clk_g)
+    );
+    
+	wire		clk = clk_g;
+	wire		rst_n = (~rst_i);
+
+
+	`WB_CTRL_SIGNALS
+
+	wire [16-1:0]	prescaler;
+	wire [1-1:0]	en;
+	wire [1-1:0]	tx_en;
+	wire [1-1:0]	rx_en;
+	wire [MDW-1:0]	wdata;
+	wire [6-1:0]	timeout_bits;
+	wire [1-1:0]	loopback_en;
+	wire [1-1:0]	glitch_filter_en;
+	wire [FAW-1:0]	tx_level;
+	wire [FAW-1:0]	rx_level;
+	wire [1-1:0]	rd;
+	wire [1-1:0]	wr;
+	wire [1-1:0]	tx_fifo_flush;
+	wire [1-1:0]	rx_fifo_flush;
+	wire [4-1:0]	data_size;
+	wire [1-1:0]	stop_bits_count;
+	wire [3-1:0]	parity_type;
+	wire [FAW-1:0]	txfifotr;
+	wire [FAW-1:0]	rxfifotr;
+	wire [MDW-1:0]	match_data;
+	wire [1-1:0]	tx_empty;
+	wire [1-1:0]	tx_full;
+	wire [1-1:0]	tx_level_below;
+	wire [MDW-1:0]	rdata;
+	wire [1-1:0]	rx_empty;
+	wire [1-1:0]	rx_full;
+	wire [1-1:0]	rx_level_above;
+	wire [1-1:0]	break_flag;
+	wire [1-1:0]	match_flag;
+	wire [1-1:0]	frame_error_flag;
+	wire [1-1:0]	parity_error_flag;
+	wire [1-1:0]	overrun_flag;
+	wire [1-1:0]	timeout_flag;
+
+	// Register Definitions
+	wire	[MDW-1:0]	RXDATA_WIRE;
+
+	wire	[MDW-1:0]	TXDATA_WIRE;
+
+	reg [15:0]	PR_REG;
+	assign	prescaler = PR_REG;
+	`WB_REG(PR_REG, 0, 16)
+
+	reg [4:0]	CTRL_REG;
+	assign	en	=	CTRL_REG[0 : 0];
+	assign	tx_en	=	CTRL_REG[1 : 1];
+	assign	rx_en	=	CTRL_REG[2 : 2];
+	assign	loopback_en	=	CTRL_REG[3 : 3];
+	assign	glitch_filter_en	=	CTRL_REG[4 : 4];
+	`WB_REG(CTRL_REG, 0, 5)
+
+	reg [13:0]	CFG_REG;
+	assign	data_size	=	CFG_REG[3 : 0];
+	assign	stop_bits_count	=	CFG_REG[4 : 4];
+	assign	parity_type	=	CFG_REG[7 : 5];
+	assign	timeout_bits	=	CFG_REG[13 : 8];
+	`WB_REG(CFG_REG, 'h3F08, 14)
+
+	reg [MDW-1:0]	MATCH_REG;
+	assign	match_data = MATCH_REG;
+	`WB_REG(MATCH_REG, 0, MDW)
+
+	wire [FAW-1:0]	RX_FIFO_LEVEL_WIRE;
+	assign	RX_FIFO_LEVEL_WIRE[(FAW - 1) : 0] = rx_level;
+
+	reg [FAW-1:0]	RX_FIFO_THRESHOLD_REG;
+	assign	rxfifotr	=	RX_FIFO_THRESHOLD_REG[(FAW - 1) : 0];
+	`WB_REG(RX_FIFO_THRESHOLD_REG, 0, FAW)
+
+	reg [0:0]	RX_FIFO_FLUSH_REG;
+	assign	rx_fifo_flush	=	RX_FIFO_FLUSH_REG[0 : 0];
+	`WB_REG_AC(RX_FIFO_FLUSH_REG, 0, 1, 1'h0)
+
+	wire [FAW-1:0]	TX_FIFO_LEVEL_WIRE;
+	assign	TX_FIFO_LEVEL_WIRE[(FAW - 1) : 0] = tx_level;
+
+	reg [FAW-1:0]	TX_FIFO_THRESHOLD_REG;
+	assign	txfifotr	=	TX_FIFO_THRESHOLD_REG[(FAW - 1) : 0];
+	`WB_REG(TX_FIFO_THRESHOLD_REG, 0, FAW)
+
+	reg [0:0]	TX_FIFO_FLUSH_REG;
+	assign	tx_fifo_flush	=	TX_FIFO_FLUSH_REG[0 : 0];
+	`WB_REG_AC(TX_FIFO_FLUSH_REG, 0, 1, 1'h0)
+
+	localparam	GCLK_REG_OFFSET = `WB_AW'hFF10;
+	`WB_REG(GCLK_REG, 0, 1)
+
+	reg [9:0] IM_REG;
+	reg [9:0] IC_REG;
+	reg [9:0] RIS_REG;
+
+	`WB_MIS_REG(10)
+	`WB_REG(IM_REG, 0, 10)
+	`WB_IC_REG(10)
+
+	wire [0:0] TXE = tx_empty;
+	wire [0:0] RXF = rx_full;
+	wire [0:0] TXB = tx_level_below;
+	wire [0:0] RXA = rx_level_above;
+	wire [0:0] BRK = break_flag;
+	wire [0:0] MATCH = match_flag;
+	wire [0:0] FE = frame_error_flag;
+	wire [0:0] PRE = parity_error_flag;
+	wire [0:0] OR = overrun_flag;
+	wire [0:0] RTO = timeout_flag;
+
+
+	integer _i_;
+	`WB_BLOCK(RIS_REG, 0) else begin
+		for(_i_ = 0; _i_ < 1; _i_ = _i_ + 1) begin
+			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(TXE[_i_ - 0] == 1'b1) RIS_REG[_i_] <= 1'b1;
+		end
+		for(_i_ = 1; _i_ < 2; _i_ = _i_ + 1) begin
+			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(RXF[_i_ - 1] == 1'b1) RIS_REG[_i_] <= 1'b1;
+		end
+		for(_i_ = 2; _i_ < 3; _i_ = _i_ + 1) begin
+			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(TXB[_i_ - 2] == 1'b1) RIS_REG[_i_] <= 1'b1;
+		end
+		for(_i_ = 3; _i_ < 4; _i_ = _i_ + 1) begin
+			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(RXA[_i_ - 3] == 1'b1) RIS_REG[_i_] <= 1'b1;
+		end
+		for(_i_ = 4; _i_ < 5; _i_ = _i_ + 1) begin
+			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(BRK[_i_ - 4] == 1'b1) RIS_REG[_i_] <= 1'b1;
+		end
+		for(_i_ = 5; _i_ < 6; _i_ = _i_ + 1) begin
+			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(MATCH[_i_ - 5] == 1'b1) RIS_REG[_i_] <= 1'b1;
+		end
+		for(_i_ = 6; _i_ < 7; _i_ = _i_ + 1) begin
+			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(FE[_i_ - 6] == 1'b1) RIS_REG[_i_] <= 1'b1;
+		end
+		for(_i_ = 7; _i_ < 8; _i_ = _i_ + 1) begin
+			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(PRE[_i_ - 7] == 1'b1) RIS_REG[_i_] <= 1'b1;
+		end
+		for(_i_ = 8; _i_ < 9; _i_ = _i_ + 1) begin
+			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(OR[_i_ - 8] == 1'b1) RIS_REG[_i_] <= 1'b1;
+		end
+		for(_i_ = 9; _i_ < 10; _i_ = _i_ + 1) begin
+			if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(RTO[_i_ - 9] == 1'b1) RIS_REG[_i_] <= 1'b1;
+		end
+	end
+
+	assign IRQ = |MIS_REG;
+
+	EF_UART #(
+		.SC(SC),
+		.MDW(MDW),
+		.GFLEN(GFLEN),
+		.FAW(FAW)
+	) instance_to_wrap (
+		.clk(clk),
+		.rst_n(rst_n),
+		.prescaler(prescaler),
+		.en(en),
+		.tx_en(tx_en),
+		.rx_en(rx_en),
+		.wdata(wdata),
+		.timeout_bits(timeout_bits),
+		.loopback_en(loopback_en),
+		.glitch_filter_en(glitch_filter_en),
+		.tx_level(tx_level),
+		.rx_level(rx_level),
+		.rd(rd),
+		.wr(wr),
+		.tx_fifo_flush(tx_fifo_flush),
+		.rx_fifo_flush(rx_fifo_flush),
+		.data_size(data_size),
+		.stop_bits_count(stop_bits_count),
+		.parity_type(parity_type),
+		.txfifotr(txfifotr),
+		.rxfifotr(rxfifotr),
+		.match_data(match_data),
+		.tx_empty(tx_empty),
+		.tx_full(tx_full),
+		.tx_level_below(tx_level_below),
+		.rdata(rdata),
+		.rx_empty(rx_empty),
+		.rx_full(rx_full),
+		.rx_level_above(rx_level_above),
+		.break_flag(break_flag),
+		.match_flag(match_flag),
+		.frame_error_flag(frame_error_flag),
+		.parity_error_flag(parity_error_flag),
+		.overrun_flag(overrun_flag),
+		.timeout_flag(timeout_flag),
+		.rx(rx),
+		.tx(tx)
+	);
+
+	assign	dat_o = 
+			(adr_i[`WB_AW-1:0] == RXDATA_REG_OFFSET)	? RXDATA_WIRE :
+			(adr_i[`WB_AW-1:0] == TXDATA_REG_OFFSET)	? TXDATA_WIRE :
+			(adr_i[`WB_AW-1:0] == PR_REG_OFFSET)	? PR_REG :
+			(adr_i[`WB_AW-1:0] == CTRL_REG_OFFSET)	? CTRL_REG :
+			(adr_i[`WB_AW-1:0] == CFG_REG_OFFSET)	? CFG_REG :
+			(adr_i[`WB_AW-1:0] == MATCH_REG_OFFSET)	? MATCH_REG :
+			(adr_i[`WB_AW-1:0] == RX_FIFO_LEVEL_REG_OFFSET)	? RX_FIFO_LEVEL_WIRE :
+			(adr_i[`WB_AW-1:0] == RX_FIFO_THRESHOLD_REG_OFFSET)	? RX_FIFO_THRESHOLD_REG :
+			(adr_i[`WB_AW-1:0] == RX_FIFO_FLUSH_REG_OFFSET)	? RX_FIFO_FLUSH_REG :
+			(adr_i[`WB_AW-1:0] == TX_FIFO_LEVEL_REG_OFFSET)	? TX_FIFO_LEVEL_WIRE :
+			(adr_i[`WB_AW-1:0] == TX_FIFO_THRESHOLD_REG_OFFSET)	? TX_FIFO_THRESHOLD_REG :
+			(adr_i[`WB_AW-1:0] == TX_FIFO_FLUSH_REG_OFFSET)	? TX_FIFO_FLUSH_REG :
+			(adr_i[`WB_AW-1:0] == IM_REG_OFFSET)	? IM_REG :
+			(adr_i[`WB_AW-1:0] == MIS_REG_OFFSET)	? MIS_REG :
+			(adr_i[`WB_AW-1:0] == RIS_REG_OFFSET)	? RIS_REG :
+			(adr_i[`WB_AW-1:0] == IC_REG_OFFSET)	? IC_REG :
+			32'hDEADBEEF;
+
+	always @ (posedge clk_i or posedge rst_i)
+		if(rst_i)
+			ack_o <= 1'b0;
+		else if(wb_valid & ~ack_o)
+			ack_o <= 1'b1;
+		else
+			ack_o <= 1'b0;
+	assign	RXDATA_WIRE = rdata;
+	assign	rd =  ack_o & (wb_re & (adr_i[`WB_AW-1:0] == RXDATA_REG_OFFSET));
+	assign	wdata = dat_i;
+	assign	wr = ack_o & (wb_we & (adr_i[`WB_AW-1:0] == TXDATA_REG_OFFSET));
+endmodule
diff --git a/hdl/rtl/bus_wrappers/dft/EF_UART_WB_DFT.v b/hdl/rtl/bus_wrappers/dft/EF_UART_WB_DFT.v
new file mode 100644
index 0000000..803e0ba
--- /dev/null
+++ b/hdl/rtl/bus_wrappers/dft/EF_UART_WB_DFT.v
@@ -0,0 +1,396 @@
+/*
+	Copyright 2024 Efabless Corp.
+
+	Author: Mohamed Shalan (mshalan@efabless.com)
+
+	Licensed under the Apache License, Version 2.0 (the "License");
+	you may not use this file except in compliance with the License.
+	You may obtain a copy of the License at
+
+	    http://www.apache.org/licenses/LICENSE-2.0
+
+	Unless required by applicable law or agreed to in writing, software
+	distributed under the License is distributed on an "AS IS" BASIS,
+	WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+	See the License for the specific language governing permissions and
+	limitations under the License.
+
+*/
+
+/* THIS FILE IS GENERATED, DO NOT EDIT */
+
+`timescale 1ns / 1ps `default_nettype none
+
+
+
+/*
+	Copyright 2020 AUCOHL
+
+    Author: Mohamed Shalan (mshalan@aucegypt.edu)
+	
+	Licensed under the Apache License, Version 2.0 (the "License"); 
+	you may not use this file except in compliance with the License. 
+	You may obtain a copy of the License at:
+
+	http://www.apache.org/licenses/LICENSE-2.0
+
+	Unless required by applicable law or agreed to in writing, software 
+	distributed under the License is distributed on an "AS IS" BASIS, 
+	WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 
+	See the License for the specific language governing permissions and 
+	limitations under the License.
+*/
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+module EF_UART_WB #(
+    parameter SC = 8,
+    MDW = 9,
+    GFLEN = 8,
+    FAW = 4
+) (
+
+
+
+
+    input  wire         sc_testmode,
+    input  wire         clk_i,
+    input  wire         rst_i,
+    input  wire [ 31:0] adr_i,
+    input  wire [ 31:0] dat_i,
+    output wire [ 31:0] dat_o,
+    input  wire [  3:0] sel_i,
+    input  wire         cyc_i,
+    input  wire         stb_i,
+    output reg          ack_o,
+    input  wire         we_i,
+    output wire         IRQ,
+    input  wire [1-1:0] rx,
+    output wire [1-1:0] tx
+);
+
+  localparam RXDATA_REG_OFFSET = 16'h0000;
+  localparam TXDATA_REG_OFFSET = 16'h0004;
+  localparam PR_REG_OFFSET = 16'h0008;
+  localparam CTRL_REG_OFFSET = 16'h000C;
+  localparam CFG_REG_OFFSET = 16'h0010;
+  localparam MATCH_REG_OFFSET = 16'h001C;
+  localparam RX_FIFO_LEVEL_REG_OFFSET = 16'hFE00;
+  localparam RX_FIFO_THRESHOLD_REG_OFFSET = 16'hFE04;
+  localparam RX_FIFO_FLUSH_REG_OFFSET = 16'hFE08;
+  localparam TX_FIFO_LEVEL_REG_OFFSET = 16'hFE10;
+  localparam TX_FIFO_THRESHOLD_REG_OFFSET = 16'hFE14;
+  localparam TX_FIFO_FLUSH_REG_OFFSET = 16'hFE18;
+  localparam IM_REG_OFFSET = 16'hFF00;
+  localparam MIS_REG_OFFSET = 16'hFF04;
+  localparam RIS_REG_OFFSET = 16'hFF08;
+  localparam IC_REG_OFFSET = 16'hFF0C;
+
+  reg [0:0] GCLK_REG;
+  wire clk_g;
+  wire clk_gated_en = sc_testmode ? 1'b1 : GCLK_REG[0];
+  ef_util_gating_cell clk_gate_cell (
+
+
+
+      // USE_POWER_PINS
+      .clk(clk_i),
+      .clk_en(clk_gated_en),
+      .clk_o(clk_g)
+  );
+
+  wire           clk = clk_g;
+  wire           rst_n = (~rst_i);
+
+
+  wire           wb_valid = cyc_i & stb_i;
+  wire           wb_we = we_i & wb_valid;
+  wire           wb_re = ~we_i & wb_valid;
+  wire [    3:0] wb_byte_sel = sel_i & {4{wb_we}};
+
+  wire [ 16-1:0] prescaler;
+  wire [  1-1:0] en;
+  wire [  1-1:0] tx_en;
+  wire [  1-1:0] rx_en;
+  wire [MDW-1:0] wdata;
+  wire [  6-1:0] timeout_bits;
+  wire [  1-1:0] loopback_en;
+  wire [  1-1:0] glitch_filter_en;
+  wire [FAW-1:0] tx_level;
+  wire [FAW-1:0] rx_level;
+  wire [  1-1:0] rd;
+  wire [  1-1:0] wr;
+  wire [  1-1:0] tx_fifo_flush;
+  wire [  1-1:0] rx_fifo_flush;
+  wire [  4-1:0] data_size;
+  wire [  1-1:0] stop_bits_count;
+  wire [  3-1:0] parity_type;
+  wire [FAW-1:0] txfifotr;
+  wire [FAW-1:0] rxfifotr;
+  wire [MDW-1:0] match_data;
+  wire [  1-1:0] tx_empty;
+  wire [  1-1:0] tx_full;
+  wire [  1-1:0] tx_level_below;
+  wire [MDW-1:0] rdata;
+  wire [  1-1:0] rx_empty;
+  wire [  1-1:0] rx_full;
+  wire [  1-1:0] rx_level_above;
+  wire [  1-1:0] break_flag;
+  wire [  1-1:0] match_flag;
+  wire [  1-1:0] frame_error_flag;
+  wire [  1-1:0] parity_error_flag;
+  wire [  1-1:0] overrun_flag;
+  wire [  1-1:0] timeout_flag;
+
+  // Register Definitions
+  wire [MDW-1:0] RXDATA_WIRE;
+
+  wire [MDW-1:0] TXDATA_WIRE;
+
+  reg  [   15:0] PR_REG;
+  assign prescaler = PR_REG;
+  always @(posedge clk_i or posedge rst_i)
+    if (rst_i) PR_REG <= 0;
+    else if (wb_we & (adr_i[16-1:0] == PR_REG_OFFSET)) PR_REG <= dat_i[16-1:0];
+
+  reg [4:0] CTRL_REG;
+  assign en = CTRL_REG[0 : 0];
+  assign tx_en = CTRL_REG[1 : 1];
+  assign rx_en = CTRL_REG[2 : 2];
+  assign loopback_en = CTRL_REG[3 : 3];
+  assign glitch_filter_en = CTRL_REG[4 : 4];
+  always @(posedge clk_i or posedge rst_i)
+    if (rst_i) CTRL_REG <= 0;
+    else if (wb_we & (adr_i[16-1:0] == CTRL_REG_OFFSET)) CTRL_REG <= dat_i[5-1:0];
+
+  reg [13:0] CFG_REG;
+  assign data_size = CFG_REG[3 : 0];
+  assign stop_bits_count = CFG_REG[4 : 4];
+  assign parity_type = CFG_REG[7 : 5];
+  assign timeout_bits = CFG_REG[13 : 8];
+  always @(posedge clk_i or posedge rst_i)
+    if (rst_i) CFG_REG <= 'h3F08;
+    else if (wb_we & (adr_i[16-1:0] == CFG_REG_OFFSET)) CFG_REG <= dat_i[14-1:0];
+
+  reg [MDW-1:0] MATCH_REG;
+  assign match_data = MATCH_REG;
+  always @(posedge clk_i or posedge rst_i)
+    if (rst_i) MATCH_REG <= 0;
+    else if (wb_we & (adr_i[16-1:0] == MATCH_REG_OFFSET)) MATCH_REG <= dat_i[MDW-1:0];
+
+  wire [FAW-1:0] RX_FIFO_LEVEL_WIRE;
+  assign RX_FIFO_LEVEL_WIRE[(FAW-1) : 0] = rx_level;
+
+  reg [FAW-1:0] RX_FIFO_THRESHOLD_REG;
+  assign rxfifotr = RX_FIFO_THRESHOLD_REG[(FAW-1) : 0];
+  always @(posedge clk_i or posedge rst_i)
+    if (rst_i) RX_FIFO_THRESHOLD_REG <= 0;
+    else if (wb_we & (adr_i[16-1:0] == RX_FIFO_THRESHOLD_REG_OFFSET))
+      RX_FIFO_THRESHOLD_REG <= dat_i[FAW-1:0];
+
+  reg [0:0] RX_FIFO_FLUSH_REG;
+  assign rx_fifo_flush = RX_FIFO_FLUSH_REG[0 : 0];
+  always @(posedge clk_i or posedge rst_i)
+    if (rst_i) RX_FIFO_FLUSH_REG <= 0;
+    else if (wb_we & (adr_i[16-1:0] == RX_FIFO_FLUSH_REG_OFFSET)) RX_FIFO_FLUSH_REG <= dat_i[1-1:0];
+    else RX_FIFO_FLUSH_REG <= 1'h0 & RX_FIFO_FLUSH_REG;
+
+  wire [FAW-1:0] TX_FIFO_LEVEL_WIRE;
+  assign TX_FIFO_LEVEL_WIRE[(FAW-1) : 0] = tx_level;
+
+  reg [FAW-1:0] TX_FIFO_THRESHOLD_REG;
+  assign txfifotr = TX_FIFO_THRESHOLD_REG[(FAW-1) : 0];
+  always @(posedge clk_i or posedge rst_i)
+    if (rst_i) TX_FIFO_THRESHOLD_REG <= 0;
+    else if (wb_we & (adr_i[16-1:0] == TX_FIFO_THRESHOLD_REG_OFFSET))
+      TX_FIFO_THRESHOLD_REG <= dat_i[FAW-1:0];
+
+  reg [0:0] TX_FIFO_FLUSH_REG;
+  assign tx_fifo_flush = TX_FIFO_FLUSH_REG[0 : 0];
+  always @(posedge clk_i or posedge rst_i)
+    if (rst_i) TX_FIFO_FLUSH_REG <= 0;
+    else if (wb_we & (adr_i[16-1:0] == TX_FIFO_FLUSH_REG_OFFSET)) TX_FIFO_FLUSH_REG <= dat_i[1-1:0];
+    else TX_FIFO_FLUSH_REG <= 1'h0 & TX_FIFO_FLUSH_REG;
+
+  localparam GCLK_REG_OFFSET = 16'hFF10;
+  always @(posedge clk_i or posedge rst_i)
+    if (rst_i) GCLK_REG <= 0;
+    else if (wb_we & (adr_i[16-1:0] == GCLK_REG_OFFSET)) GCLK_REG <= dat_i[1-1:0];
+
+  reg  [   9:0] IM_REG;
+  reg  [   9:0] IC_REG;
+  reg  [   9:0] RIS_REG;
+
+  wire [10-1:0] MIS_REG = RIS_REG & IM_REG;
+  always @(posedge clk_i or posedge rst_i)
+    if (rst_i) IM_REG <= 0;
+    else if (wb_we & (adr_i[16-1:0] == IM_REG_OFFSET)) IM_REG <= dat_i[10-1:0];
+  always @(posedge clk_i or posedge rst_i)
+    if (rst_i) IC_REG <= 10'b0;
+    else if (wb_we & (adr_i[16-1:0] == IC_REG_OFFSET)) IC_REG <= dat_i[10-1:0];
+    else IC_REG <= 10'd0;
+
+  wire [0:0] TXE = tx_empty;
+  wire [0:0] RXF = rx_full;
+  wire [0:0] TXB = tx_level_below;
+  wire [0:0] RXA = rx_level_above;
+  wire [0:0] BRK = break_flag;
+  wire [0:0] MATCH = match_flag;
+  wire [0:0] FE = frame_error_flag;
+  wire [0:0] PRE = parity_error_flag;
+  wire [0:0] OR = overrun_flag;
+  wire [0:0] RTO = timeout_flag;
+
+
+  integer _i_;
+  always @(posedge clk_i or posedge rst_i)
+    if (rst_i) RIS_REG <= 0;
+    else begin
+      for (_i_ = 0; _i_ < 1; _i_ = _i_ + 1) begin
+        if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+        else if (TXE[_i_-0] == 1'b1) RIS_REG[_i_] <= 1'b1;
+      end
+      for (_i_ = 1; _i_ < 2; _i_ = _i_ + 1) begin
+        if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+        else if (RXF[_i_-1] == 1'b1) RIS_REG[_i_] <= 1'b1;
+      end
+      for (_i_ = 2; _i_ < 3; _i_ = _i_ + 1) begin
+        if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+        else if (TXB[_i_-2] == 1'b1) RIS_REG[_i_] <= 1'b1;
+      end
+      for (_i_ = 3; _i_ < 4; _i_ = _i_ + 1) begin
+        if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+        else if (RXA[_i_-3] == 1'b1) RIS_REG[_i_] <= 1'b1;
+      end
+      for (_i_ = 4; _i_ < 5; _i_ = _i_ + 1) begin
+        if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+        else if (BRK[_i_-4] == 1'b1) RIS_REG[_i_] <= 1'b1;
+      end
+      for (_i_ = 5; _i_ < 6; _i_ = _i_ + 1) begin
+        if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+        else if (MATCH[_i_-5] == 1'b1) RIS_REG[_i_] <= 1'b1;
+      end
+      for (_i_ = 6; _i_ < 7; _i_ = _i_ + 1) begin
+        if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+        else if (FE[_i_-6] == 1'b1) RIS_REG[_i_] <= 1'b1;
+      end
+      for (_i_ = 7; _i_ < 8; _i_ = _i_ + 1) begin
+        if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+        else if (PRE[_i_-7] == 1'b1) RIS_REG[_i_] <= 1'b1;
+      end
+      for (_i_ = 8; _i_ < 9; _i_ = _i_ + 1) begin
+        if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+        else if (OR[_i_-8] == 1'b1) RIS_REG[_i_] <= 1'b1;
+      end
+      for (_i_ = 9; _i_ < 10; _i_ = _i_ + 1) begin
+        if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+        else if (RTO[_i_-9] == 1'b1) RIS_REG[_i_] <= 1'b1;
+      end
+    end
+
+  assign IRQ = |MIS_REG;
+
+  EF_UART #(
+      .SC(SC),
+      .MDW(MDW),
+      .GFLEN(GFLEN),
+      .FAW(FAW)
+  ) instance_to_wrap (
+      .clk(clk),
+      .rst_n(rst_n),
+      .prescaler(prescaler),
+      .en(en),
+      .tx_en(tx_en),
+      .rx_en(rx_en),
+      .wdata(wdata),
+      .timeout_bits(timeout_bits),
+      .loopback_en(loopback_en),
+      .glitch_filter_en(glitch_filter_en),
+      .tx_level(tx_level),
+      .rx_level(rx_level),
+      .rd(rd),
+      .wr(wr),
+      .tx_fifo_flush(tx_fifo_flush),
+      .rx_fifo_flush(rx_fifo_flush),
+      .data_size(data_size),
+      .stop_bits_count(stop_bits_count),
+      .parity_type(parity_type),
+      .txfifotr(txfifotr),
+      .rxfifotr(rxfifotr),
+      .match_data(match_data),
+      .tx_empty(tx_empty),
+      .tx_full(tx_full),
+      .tx_level_below(tx_level_below),
+      .rdata(rdata),
+      .rx_empty(rx_empty),
+      .rx_full(rx_full),
+      .rx_level_above(rx_level_above),
+      .break_flag(break_flag),
+      .match_flag(match_flag),
+      .frame_error_flag(frame_error_flag),
+      .parity_error_flag(parity_error_flag),
+      .overrun_flag(overrun_flag),
+      .timeout_flag(timeout_flag),
+      .rx(rx),
+      .tx(tx)
+  );
+
+  assign	dat_o = 
+			(adr_i[16-1:0] == RXDATA_REG_OFFSET)	? RXDATA_WIRE :
+			(adr_i[16-1:0] == TXDATA_REG_OFFSET)	? TXDATA_WIRE :
+			(adr_i[16-1:0] == PR_REG_OFFSET)	? PR_REG :
+			(adr_i[16-1:0] == CTRL_REG_OFFSET)	? CTRL_REG :
+			(adr_i[16-1:0] == CFG_REG_OFFSET)	? CFG_REG :
+			(adr_i[16-1:0] == MATCH_REG_OFFSET)	? MATCH_REG :
+			(adr_i[16-1:0] == RX_FIFO_LEVEL_REG_OFFSET)	? RX_FIFO_LEVEL_WIRE :
+			(adr_i[16-1:0] == RX_FIFO_THRESHOLD_REG_OFFSET)	? RX_FIFO_THRESHOLD_REG :
+			(adr_i[16-1:0] == RX_FIFO_FLUSH_REG_OFFSET)	? RX_FIFO_FLUSH_REG :
+			(adr_i[16-1:0] == TX_FIFO_LEVEL_REG_OFFSET)	? TX_FIFO_LEVEL_WIRE :
+			(adr_i[16-1:0] == TX_FIFO_THRESHOLD_REG_OFFSET)	? TX_FIFO_THRESHOLD_REG :
+			(adr_i[16-1:0] == TX_FIFO_FLUSH_REG_OFFSET)	? TX_FIFO_FLUSH_REG :
+			(adr_i[16-1:0] == IM_REG_OFFSET)	? IM_REG :
+			(adr_i[16-1:0] == MIS_REG_OFFSET)	? MIS_REG :
+			(adr_i[16-1:0] == RIS_REG_OFFSET)	? RIS_REG :
+			(adr_i[16-1:0] == IC_REG_OFFSET)	? IC_REG :
+			32'hDEADBEEF;
+
+  always @(posedge clk_i or posedge rst_i)
+    if (rst_i) ack_o <= 1'b0;
+    else if (wb_valid & ~ack_o) ack_o <= 1'b1;
+    else ack_o <= 1'b0;
+  assign RXDATA_WIRE = rdata;
+  assign rd = ack_o & (wb_re & (adr_i[16-1:0] == RXDATA_REG_OFFSET));
+  assign wdata = dat_i;
+  assign wr = ack_o & (wb_we & (adr_i[16-1:0] == TXDATA_REG_OFFSET));
+endmodule
diff --git a/ip/dependencies.json b/ip/dependencies.json
index bc86f84..2474569 100644
--- a/ip/dependencies.json
+++ b/ip/dependencies.json
@@ -1,7 +1,7 @@
 {
     "IP": [
         {
-            "IP_Utilities": "v1.0.0"
+            "EF_IP_UTIL": "v1.0.0"
         }
     ]
 }
\ No newline at end of file
diff --git a/verify/uvm-python/Makefile b/verify/uvm-python/Makefile
index a89674f..6f05b7c 100644
--- a/verify/uvm-python/Makefile
+++ b/verify/uvm-python/Makefile
@@ -1,10 +1,10 @@
 PLUSARGS += "+UVM_VERBOSITY=UVM_HIGH"
 TOPLEVEL := top
 MODULE   ?= top_module
-AHB_FILES ?= $(PWD)/../../hdl/rtl/bus_wrappers/EF_UART_AHBL.pp.v
-APB_FILES ?= $(PWD)/../../hdl/rtl/bus_wrappers/EF_UART_APB.pp.v
-WB_FILES ?= $(PWD)/../../hdl/rtl/bus_wrappers/EF_UART_WB.pp.v
-HDL_FILES ?= $(PWD)/../../ip/IP_Utilities/rtl/aucohl_lib.v $(PWD)/../../ip/IP_Utilities/rtl/aucohl_rtl.vh  $(PWD)/../../hdl/rtl/EF_UART.v 
+AHB_FILES ?= $(PWD)/../../hdl/rtl/bus_wrappers/EF_UART_AHBL.v
+APB_FILES ?= $(PWD)/../../hdl/rtl/bus_wrappers/EF_UART_APB.v
+WB_FILES ?= $(PWD)/../../hdl/rtl/bus_wrappers/EF_UART_WB.v
+HDL_FILES ?= $(PWD)/../../ip/EF_IP_UTIL/hdl/ef_util_lib.v  $(PWD)/../../hdl/rtl/EF_UART.v 
 VERILOG_SOURCES ?=  $(PWD)/top.v $(AHB_FILES) $(APB_FILES) $(WB_FILES) $(HDL_FILES)
 RTL_MACROS += ""
 BUS_TYPE ?= APB