gatemate-lab/Makefile.comman at main · dpks2003/gatemate-lab · GitHub

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# ===============================
# Common GateMate FPGA Makefile (future-proof + help)
# ===============================

# Must be set in project Makefile:
#   PROJECT = project_name
#   TOP     = top_module

DEVICE  ?= CCGM1A1
OUTDIR  ?= $(CURDIR)/build
SRC     = $(wildcard $(CURDIR)/*.v)

JSON    = $(OUTDIR)/$(PROJECT).json
NETLIST = $(OUTDIR)/$(PROJECT)_post.v
CCF     = $(PROJECT).ccf
TXT     = $(OUTDIR)/$(PROJECT).txt
BIT     = $(OUTDIR)/$(PROJECT).bit

.PHONY: all build clean proj synth pnr pack help

all: build ## Default: build the full FPGA bitstream

# ------------------------------
# Build chain
# ------------------------------
build: $(BIT) ## Run synth → pnr → pack

# ------------------------------
# Rules with dependencies
# ------------------------------
synth: $(JSON) ## Run synthesis (yosys)

$(JSON) $(NETLIST): $(SRC)
	@mkdir -p $(OUTDIR)
	yosys -p "read_verilog $(SRC); synth_gatemate -top $(TOP) -luttree -nomx8; write_json $(JSON); write_verilog $(NETLIST)"

pnr: $(TXT) ## Run place & route (nextpnr)

$(TXT) $(CCF): $(JSON)
	nextpnr-himbaechel --device=$(DEVICE) --json $(JSON) \
	    -o ccf=$(CCF) -o out=$(TXT) --router router2

pack: $(BIT) ## Pack routing results into bitstream

$(BIT): $(TXT)
	gmpack $(TXT) $(BIT)

proj: $(BIT) ## Program FPGA with generated bitstream
	openFPGALoader --index-chain 0 --cable dirtyJtag $(BIT)

clean: ## Remove build artifacts
	rm -rf $(OUTDIR)

# ------------------------------
# Help system
# ------------------------------

help: ## Show this help
	@echo "Available targets:"
	@grep -hE '^[a-zA-Z_-]+:.*?## .*$$' $(MAKEFILE_LIST) | \
		awk 'BEGIN {FS = ":.*?## "}; {printf "  make %-10s # %s\n", $$1, $$2}'