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Merge pull request #839 from diffblue/verilog_event
SystemVerilog: `event` data type
2 parents 4b0c862 + d31183f commit ed80f2e

16 files changed

+136
-13
lines changed

‎CHANGELOG

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -6,7 +6,7 @@
66
* Verilog: fix for nor/nand/xnor primitive gates
77
* SystemVerilog: $bitstoreal/$bitstoshortreal, $realtobits/$shortrealtobits
88
* SystemVerilog: $itor, $rtoi
9-
* SystemVerilog: chandle
9+
* SystemVerilog: chandle, event
1010

1111
# EBMC 5.4
1212

‎regression/verilog/data-types/event1.desc

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,6 @@
1+
CORE
2+
event1.sv
3+
--bound 0
4+
^EXIT=0$
5+
^SIGNAL=0$
6+
--

‎regression/verilog/data-types/event1.sv

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,18 @@
1+
module main;
2+
3+
// IEEE 1800-2017 6.17
4+
event done;
5+
event empty = null;
6+
7+
task trigger_done;
8+
-> done;
9+
endtask
10+
11+
task wait_until_done;
12+
@ done;
13+
endtask
14+
15+
p0: assert final (empty == null);
16+
p1: assert final ($typename(event) == "event");
17+
18+
endmodule

‎src/hw_cbmc_irep_ids.h

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -106,7 +106,8 @@ IREP_ID_ONE(verilog_streaming_concatenation_left_to_right)
106106
IREP_ID_ONE(verilog_streaming_concatenation_right_to_left)
107107
IREP_ID_ONE(verilog_chandle)
108108
IREP_ID_ONE(verilog_null)
109-
IREP_ID_ONE(event)
109+
IREP_ID_ONE(verilog_event)
110+
IREP_ID_ONE(verilog_event_trigger)
110111
IREP_ID_ONE(reg)
111112
IREP_ID_ONE(macromodule)
112113
IREP_ID_ONE(output_register)

‎src/verilog/expr2verilog.cpp

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1260,7 +1260,7 @@ expr2verilogt::resultt expr2verilogt::convert_constant(
12601260

12611261
dest += '"';
12621262
}
1263-
else if(type.id() == ID_verilog_chandle)
1263+
else if(type.id() == ID_verilog_chandle || type.id() == ID_verilog_event)
12641264
{
12651265
if(src.get_value() == ID_NULL)
12661266
{
@@ -2041,6 +2041,8 @@ std::string expr2verilogt::convert(const typet &type)
20412041
}
20422042
else if(type.id() == ID_verilog_chandle)
20432043
return "chandle";
2044+
else if(type.id() == ID_verilog_event)
2045+
return "event";
20442046
else if(type.id() == ID_verilog_genvar)
20452047
return "genvar";
20462048
else if(type.id()==ID_integer)

‎src/verilog/parser.y

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1486,7 +1486,7 @@ data_type:
14861486
$$ = $2; }
14871487
// | class_type
14881488
| TOK_EVENT
1489-
{ init($$, ID_event); }
1489+
{ init($$, ID_verilog_event); }
14901490
/*
14911491
| ps_covergroup_identifier
14921492
*/
@@ -3403,7 +3403,7 @@ event_control:
34033403

34043404
ored_event_expression:
34053405
event_expression
3406-
{ init($$, ID_event); mto($$, $1); }
3406+
{ init($$, ID_verilog_event); mto($$, $1); }
34073407
| ored_event_expression TOK_OR event_expression
34083408
{ $$=$1; mto($$, $3); }
34093409
| ored_event_expression ',' event_expression
@@ -3878,6 +3878,7 @@ function_subroutine_call: subroutine_call
38783878
;
38793879

38803880
event_trigger: TOK_MINUSGREATER hierarchical_event_identifier ';'
3881+
{ init($$, ID_verilog_event_trigger); mto($$, $2); }
38813882
;
38823883

38833884
// System Verilog standard 1800-2017

‎src/verilog/verilog_elaborate.cpp

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -751,6 +751,9 @@ void verilog_typecheckt::collect_symbols(const verilog_statementt &statement)
751751
else if(statement.id() == ID_wait)
752752
{
753753
}
754+
else if(statement.id() == ID_verilog_event_trigger)
755+
{
756+
}
754757
else
755758
DATA_INVARIANT(false, "unexpected statement: " + statement.id_string());
756759
}

‎src/verilog/verilog_elaborate_type.cpp

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -302,6 +302,10 @@ typet verilog_typecheck_exprt::elaborate_type(const typet &src)
302302
result.set(ID_C_identifier, enum_type.identifier());
303303
return result.with_source_location(source_location);
304304
}
305+
else if(src.id() == ID_verilog_event)
306+
{
307+
return src;
308+
}
305309
else if(src.id() == ID_verilog_packed_array)
306310
{
307311
return convert_packed_array_type(to_type_with_subtype(src));

‎src/verilog/verilog_lowering.cpp

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -47,6 +47,10 @@ typet verilog_lowering(typet type)
4747
{
4848
return to_verilog_chandle_type(type).encoding();
4949
}
50+
else if(type.id() == ID_verilog_event)
51+
{
52+
return to_verilog_event_type(type).encoding();
53+
}
5054
else
5155
return type;
5256
}
@@ -357,6 +361,11 @@ exprt verilog_lowering(exprt expr)
357361
// this is 'null'
358362
return to_verilog_chandle_type(expr.type()).null_expr();
359363
}
364+
else if(expr.type().id() == ID_verilog_event)
365+
{
366+
// this is 'null'
367+
return to_verilog_event_type(expr.type()).null_expr();
368+
}
360369

361370
return expr;
362371
}
@@ -369,6 +378,11 @@ exprt verilog_lowering(exprt expr)
369378
return symbol_exprt{
370379
symbol_expr.get_identifier(), chandle_type.encoding()};
371380
}
381+
else if(expr.type().id() == ID_verilog_event)
382+
{
383+
auto &event_type = to_verilog_event_type(expr.type());
384+
return symbol_exprt{symbol_expr.get_identifier(), event_type.encoding()};
385+
}
372386
else
373387
return expr;
374388
}

‎src/verilog/verilog_synthesis.cpp

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3185,6 +3185,10 @@ void verilog_synthesist::synth_statement(
31853185
}
31863186
else if(statement.id() == ID_verilog_label_statement)
31873187
synth_statement(to_verilog_label_statement(statement).statement());
3188+
else if(statement.id() == ID_verilog_event_trigger)
3189+
{
3190+
// not synthesized
3191+
}
31883192
else
31893193
{
31903194
throw errort().with_location(statement.source_location())

‎src/verilog/verilog_typecheck.cpp

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1613,6 +1613,10 @@ void verilog_typecheckt::convert_statement(
16131613
else if(statement.id() == ID_wait)
16141614
{
16151615
}
1616+
else if(statement.id() == ID_verilog_event_trigger)
1617+
{
1618+
convert_expr(to_unary_expr(statement).op());
1619+
}
16161620
else
16171621
{
16181622
throw errort().with_location(statement.source_location())

‎src/verilog/verilog_typecheck_expr.cpp

Lines changed: 14 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -345,7 +345,7 @@ exprt verilog_typecheck_exprt::convert_expr_rec(exprt expr)
345345
{
346346
// variable number of operands
347347

348-
if(expr.id() == ID_event)
348+
if(expr.id() == ID_verilog_event)
349349
{
350350
expr.type() = bool_typet();
351351

@@ -757,6 +757,10 @@ exprt verilog_typecheck_exprt::typename_string(const exprt &expr)
757757
{
758758
s = "chandle";
759759
}
760+
else if(type.id() == ID_verilog_event)
761+
{
762+
s = "event";
763+
}
760764
else
761765
s = "?";
762766

@@ -2052,7 +2056,9 @@ void verilog_typecheck_exprt::implicit_typecast(
20522056
}
20532057
else if(src_type.id() == ID_verilog_null)
20542058
{
2055-
if(dest_type.id() == ID_verilog_chandle)
2059+
if(
2060+
dest_type.id() == ID_verilog_chandle ||
2061+
dest_type.id() == ID_verilog_event)
20562062
{
20572063
if(expr.id() == ID_constant)
20582064
{
@@ -2319,6 +2325,12 @@ typet verilog_typecheck_exprt::max_type(
23192325
if(vt0.is_chandle() || vt1.is_null())
23202326
return t0;
23212327

2328+
if(vt0.is_null() || vt1.is_event())
2329+
return t1;
2330+
2331+
if(vt0.is_event() || vt1.is_null())
2332+
return t0;
2333+
23222334
if(vt0.is_other() || vt1.is_other())
23232335
return static_cast<const typet &>(get_nil_irep());
23242336

‎src/verilog/verilog_types.cpp

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -14,3 +14,8 @@ constant_exprt verilog_chandle_typet::null_expr() const
1414
{
1515
return encoding().all_zeros_expr();
1616
}
17+
18+
constant_exprt verilog_event_typet::null_expr() const
19+
{
20+
return encoding().all_zeros_expr();
21+
}

‎src/verilog/verilog_types.h

Lines changed: 37 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -581,4 +581,41 @@ inline verilog_chandle_typet &to_verilog_chandle_type(typet &type)
581581
return static_cast<verilog_chandle_typet &>(type);
582582
}
583583

584+
/// The SystemVerilog event type
585+
class verilog_event_typet : public typet
586+
{
587+
public:
588+
verilog_event_typet() : typet(ID_verilog_event)
589+
{
590+
}
591+
592+
constant_exprt null_expr() const;
593+
594+
bv_typet encoding() const
595+
{
596+
return bv_typet{32};
597+
}
598+
};
599+
600+
/// \brief Cast a typet to a \ref verilog_event_typet
601+
///
602+
/// This is an unchecked conversion. \a type must be known to be \ref
603+
/// verilog_event_typet. Will fail with a precondition violation if type
604+
/// doesn't match.
605+
///
606+
/// \param type: Source type.
607+
/// \return Object of type \ref verilog_event_typet
608+
inline const verilog_event_typet &to_verilog_event_type(const typet &type)
609+
{
610+
PRECONDITION(type.id() == ID_verilog_event);
611+
return static_cast<const verilog_event_typet &>(type);
612+
}
613+
614+
/// \copydoc to_event_type(const typet &)
615+
inline verilog_event_typet &to_verilog_event_type(typet &type)
616+
{
617+
PRECONDITION(type.id() == ID_verilog_event);
618+
return static_cast<verilog_event_typet &>(type);
619+
}
620+
584621
#endif

‎src/verilog/vtype.cpp

Lines changed: 10 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -78,6 +78,11 @@ vtypet::vtypet(const typet &type)
7878
vtype = CHANDLE;
7979
width = 32;
8080
}
81+
else if(type.id() == ID_verilog_event)
82+
{
83+
vtype = EVENT;
84+
width = 32;
85+
}
8186
else
8287
{
8388
width=0;
@@ -122,16 +127,18 @@ std::ostream &operator << (std::ostream &out, const vtypet &vtype)
122127
case vtypet::VERILOG_REAL:
123128
return out << "real";
124129

130+
case vtypet::NULL_TYPE:
131+
return out << "null";
132+
125133
case vtypet::CHANDLE:
126134
return out << "chandle";
127135

128-
case vtypet::NULL_TYPE:
129-
return out << "null";
136+
case vtypet::EVENT:
137+
return out << "event";
130138

131139
case vtypet::UNKNOWN:
132140
case vtypet::OTHER:
133141
default:
134142
return out << "?";
135143
}
136144
}
137-

‎src/verilog/vtype.h

Lines changed: 8 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -31,13 +31,17 @@ class vtypet
3131
{
3232
return vtype == VERILOG_REAL;
3333
}
34+
bool is_null() const
35+
{
36+
return vtype == NULL_TYPE;
37+
}
3438
bool is_chandle() const
3539
{
3640
return vtype == CHANDLE;
3741
}
38-
bool is_null() const
42+
inline bool is_event() const
3943
{
40-
return vtype == NULL_TYPE;
44+
return vtype == EVENT;
4145
}
4246
inline bool is_other() const { return vtype==OTHER; }
4347

@@ -52,8 +56,9 @@ class vtypet
5256
VERILOG_SIGNED,
5357
VERILOG_UNSIGNED,
5458
VERILOG_REAL,
55-
CHANDLE,
5659
NULL_TYPE,
60+
CHANDLE,
61+
EVENT,
5762
OTHER
5863
} _vtypet;
5964
_vtypet vtype;

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