From 2b5ab40f9feb94d9f31081126f50aa65f2e49e63 Mon Sep 17 00:00:00 2001 From: Denis Bakhvalov Date: Sat, 14 Sep 2024 17:08:49 -0400 Subject: [PATCH] Update 4-7 Cache miss.md --- chapters/4-Terminology-And-Metrics/4-7 Cache miss.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/chapters/4-Terminology-And-Metrics/4-7 Cache miss.md b/chapters/4-Terminology-And-Metrics/4-7 Cache miss.md index 6504e7fb91..633af6f897 100644 --- a/chapters/4-Terminology-And-Metrics/4-7 Cache miss.md +++ b/chapters/4-Terminology-And-Metrics/4-7 Cache miss.md @@ -47,4 +47,4 @@ $ perf stat -e mem_load_retired.l1_miss, From this example, we can see that 37% of loads that missed in the L1 D-cache also missed in the L2 cache, thus the *L2 hit rate* is 63%. A breakdown for the L3 cache can be made similarly. [^1]: Interactive latency - [https://colin-scott.github.io/personal_website/research/interactive_latency.html](https://colin-scott.github.io/personal_website/research/interactive_latency.html) -[^2]: Careful readers may notice discrepancy in the numbers: `fb_hit + l1_hit + l1_miss = 545,820`, which doesn't exactly match `all_loads`. We did not investigate this since the numbers are very close. \ No newline at end of file +[^2]: Careful readers may notice a discrepancy in the numbers: `fb_hit + l1_hit + l1_miss = 545,820`, which doesn't exactly match `all_loads`. We did not investigate this since the numbers are very close.