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Commit 30f2e83

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[WIRED] Use prescaled GC trigger value for trigger delay logic
1 parent d37a162 commit 30f2e83

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+4
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main/wired/nsi.c

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -452,6 +452,8 @@ static void gc_pad_cmd_hdlr(uint8_t channel, uint8_t port, uint16_t item) {
452452
buf[i] = (wired_adapter.data[port].output_mask[i - 4]) ?
453453
wired_adapter.data[port].output_mask[i - 4] : wired_adapter.data[port].output[i - 4];
454454
}
455+
uint8_t trig_l = buf[10];
456+
uint8_t trig_r = buf[11];
455457

456458
/* Delay Digital trigger state until analog part is set at least 2 frames */
457459
if (gc_r_trig_prev_state[port] < 2) {
@@ -503,15 +505,15 @@ static void gc_pad_cmd_hdlr(uint8_t channel, uint8_t port, uint16_t item) {
503505
nsi_bytes_to_items_crc(channel * RMT_MEM_ITEM_NUM, &buf[4], len, &crc, STOP_BIT_2US);
504506
RMT.conf_ch[channel].conf1.tx_start = 1;
505507

506-
if (buf[10] > 0x30) {
508+
if (trig_l > 0x30) {
507509
if (gc_l_trig_prev_state[port] < 2) {
508510
gc_l_trig_prev_state[port]++;
509511
}
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}
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else {
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gc_l_trig_prev_state[port] = 0;
513515
}
514-
if (buf[11] > 0x30) {
516+
if (trig_r > 0x30) {
515517
if (gc_r_trig_prev_state[port] < 2) {
516518
gc_r_trig_prev_state[port]++;
517519
}

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