Update documentation

Author: DrChat

src/arch.rs

@@ -28,7 +28,12 @@ use crate::internal::{BeBytes, LeBytes};
 ///
 /// [single register accesses]: crate::target::ext::base::SingleRegisterAccess
 pub trait RegId: Sized + Debug {
-    /// Map raw GDB register number corresponding `RegId` and register size.
+    /// Map raw GDB register number to a corresponding `RegId` and optional
+    /// register size.
+    ///
+    /// If the register size is specified here, no more than that amount of
+    /// bytes will be permitted to be transferred on the wire for that
+    /// register.
     ///
     /// Returns `None` if the register is not available.
     fn from_raw_id(id: usize) -> Option<(Self, Option<NonZeroUsize>)>;

src/target/ext/base/single_register_access.rs

@@ -22,7 +22,7 @@ pub trait SingleRegisterAccess<Id>: Target {
     /// On single threaded targets, `tid` is set to `()` and can be ignored.
     ///
     /// Implementations should write the value of the register using target's
-    /// native byte order in the buffer `dst`.
+    /// native byte order when writing via `output`.
     ///
     /// If the requested register could not be accessed, an appropriate
     /// non-fatal error should be returned.