New Rule: procedural_continuous_assignment

[remes-codasip]

The following code contains "Procesural Continuous Assignment" statement (assign in an always block) which is not synthesizable (at least not by all tools).

module test (
    input logic clk,
    input logic a,
    input logic b,
    output logic c
);

always_ff @(posedge clk)
    assign c = a + b;


endmodule

Can you please add a rule to check for such constructs?

[DaveMcEwan]

Seems like a sensible idea. From the IEEE1800-2017, page 242:

NOTE - The procedural assign and deassign constructs are under consideration for deprecation. See Annex C.

@remes-codasip Would you like some assistance to create this rule? There are some guidelines here. I think you'd be looking to detect either ProceduralContinuousAssignmentAssign or other variants of procedural_continuous_assignment, depending on exactly what you're looking for. To implement this, you could modify this rule.

[remes-codasip]

@DaveMcEwan thanks for the hints you sent me.

I have created #276 and would welcome feedback (I think the documentation of the rule could be better, but I'm not familiar enough with SystemVerilog to write it better).

[DaveMcEwan]

@remes-codasip @dalance The PR was merged so this can be closed.