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[binutils, ARM, 7/16] New BFX and BFLX instruction for Armv8.1-M Mainline
This patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils. This patch adds the BFX and BFLX instructions. ChangeLog entries are as follows : *** gas/ChangeLog *** 2019-04-15 Sudakshina Das <[email protected]> * config/tc-arm.c (T16_32_TAB): New entries for bfx and bflx. (do_t_v8_1_branch): New switch cases for bfx and bflx. (insns): New instruction for bfx and bflx. * testsuite/gas/arm/armv8_1-m-bf-exchange.d: New. * testsuite/gas/arm/armv8_1-m-bf-exchange.s: New. * testsuite/gas/arm/armv8_1-m-bf-exchange-bad.s: New * testsuite/gas/arm/armv8_1-m-bf-exchange-bad.l: New * testsuite/gas/arm/armv8_1-m-bf-exchange-bad.d: New *** opcodes/ChangeLog *** 2019-04-15 Sudakshina Das <[email protected]> * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an Arm register with r13 and r15 unpredictable. (thumb32_opcodes): New instructions for bfx and bflx.
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‎gas/ChangeLog

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@@ -1,3 +1,14 @@
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2019-04-15 Sudakshina Das <[email protected]>
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* config/tc-arm.c (T16_32_TAB): New entries for bfx and bflx.
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(do_t_v8_1_branch): New switch cases for bfx and bflx.
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(insns): New instruction for bfx and bflx.
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* testsuite/gas/arm/armv8_1-m-bf-exchange.d: New.
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* testsuite/gas/arm/armv8_1-m-bf-exchange.s: New.
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* testsuite/gas/arm/armv8_1-m-bf-exchange-bad.s: New
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* testsuite/gas/arm/armv8_1-m-bf-exchange-bad.l: New
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* testsuite/gas/arm/armv8_1-m-bf-exchange-bad.d: New
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2019-04-15 Sudakshina Das <[email protected]>
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Andre Vieira <[email protected]>
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‎gas/config/tc-arm.c

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@@ -10506,6 +10506,8 @@ encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
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X(_b, e000, f000b000), \
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X(_bcond, d000, f0008000), \
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X(_bf, 0000, f040e001), \
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X(_bfx, 0000, f060e001), \
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X(_bflx, 0000, f070e001), \
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X(_bic, 4380, ea200000), \
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X(_bics, 4380, ea300000), \
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X(_cmn, 42c0, eb100f00), \
@@ -13362,6 +13364,11 @@ do_t_branch_future (void)
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}
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break;
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case T_MNEM_bfx:
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case T_MNEM_bflx:
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inst.instruction |= inst.operands[1].reg << 16;
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break;
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default: abort ();
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}
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}
@@ -21679,6 +21686,8 @@ static const struct asm_opcode insns[] =
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#undef THUMB_VARIANT
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#define THUMB_VARIANT & arm_ext_v8_1m_main
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toC("bf", _bf, 2, (EXPs, EXPs), t_branch_future),
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toC("bfx", _bfx, 2, (EXPs, RRnpcsp), t_branch_future),
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toC("bflx", _bflx, 2, (EXPs, RRnpcsp), t_branch_future),
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};
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#undef ARM_VARIANT
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#undef THUMB_VARIANT

‎gas/testsuite/gas/arm/armv8_1-m-bf-exchange-bad.d

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#name: Invalid Armv8.1-M Mainline BF-exchange instructions
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#source: armv8_1-m-bf-exchange-bad.s
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#as: -march=armv8.1-m.main
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#error_output: armv8_1-m-bf-exchange-bad.l

‎gas/testsuite/gas/arm/armv8_1-m-bf-exchange-bad.l

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.*: Assembler messages:
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.*:6: Error: branch out of range or not a multiple of 2
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.*:7: Error: branch out of range or not a multiple of 2
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.*:8: Error: branch out of range or not a multiple of 2
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.*:9: Error: branch out of range or not a multiple of 2
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.*:11: Error: r15 not allowed here -- `bfx 2,PC'
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.*:12: Error: r13 not allowed here -- `bflx 2,SP'

‎gas/testsuite/gas/arm/armv8_1-m-bf-exchange-bad.s

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.syntax unified
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.text
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.thumb
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foo:
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# OP0 : Unsigned, 5-bit, even
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bfx 0, r3
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bfx -2, r3
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bflx 3, r3
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bflx 32, r3
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# OP1 : no SP or PC
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bfx 2, PC
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bflx 2, SP

‎gas/testsuite/gas/arm/armv8_1-m-bf-exchange.d

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#name: Valid Armv8.1-M Mainline BF-exchange instructions
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#source: armv8_1-m-bf-exchange.s
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#as: -march=armv8.1-m.main
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#objdump: -dr --prefix-addresses --show-raw-insn
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.*: +file format .*arm.*
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Disassembly of section .text:
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0[0-9a-f]+ <[^>]+> f265 e001 bfx 8, r5
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0[0-9a-f]+ <[^>]+> 4609 mov r1, r1
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0[0-9a-f]+ <[^>]+> f173 e001 bflx 4, r3
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0[0-9a-f]+ <[^>]+> 460a mov r2, r1
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0[0-9a-f]+ <[^>]+> 4613 mov r3, r2
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0[0-9a-f]+ <[^>]+> 4614 mov r4, r2

‎gas/testsuite/gas/arm/armv8_1-m-bf-exchange.s

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.syntax unified
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.text
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.thumb
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foo:
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bfx .LB1, r5
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mov r1, r1
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bflx .LB2, r3
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mov r2, r1
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.LB1:
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mov r3, r2
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.LB2:
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mov r4, r2

‎opcodes/ChangeLog

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2019-04-15 Sudakshina Das <[email protected]>
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* arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
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Arm register with r13 and r15 unpredictable.
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(thumb32_opcodes): New instructions for bfx and bflx.
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2019-04-15 Sudakshina Das <[email protected]>
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* arm-dis.c (thumb32_opcodes): New instructions for bf.

‎opcodes/arm-dis.c

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@@ -2730,6 +2730,7 @@ static const struct opcode16 thumb_opcodes[] =
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%<bitfield>W print bitfield*4 in decimal
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%<bitfield>r print bitfield as an ARM register
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%<bitfield>R as %<>r but r15 is UNPREDICTABLE
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%<bitfield>S as %<>r but r13 and r15 is UNPREDICTABLE
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%<bitfield>c print bitfield as a condition code
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%<bitfield>'c print specified char iff bitfield is all ones
@@ -2749,6 +2750,10 @@ static const struct opcode32 thumb32_opcodes[] =
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/* Armv8.1-M Mainline instructions. */
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{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
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0xf040e001, 0xf860f001, "bf%c\t%G, %W"},
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{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
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0xf060e001, 0xf8f0f001, "bfx%c\t%G, %16-19S"},
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{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
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0xf070e001, 0xf8f0f001, "bflx%c\t%G, %16-19S"},
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/* ARMv8-M and ARMv8-M Security Extensions instructions. */
@@ -6056,6 +6061,10 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
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value_in_comment = val * 4;
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break;
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case 'S':
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if (val == 13)
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is_unpredictable = TRUE;
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/* Fall through. */
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case 'R':
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if (val == 15)
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is_unpredictable = TRUE;

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