[binutils, ARM, 9/16] New BFL instruction for Armv8.1-M Mainline

This patch is part of a series of patches to add support for Armv8.1-M Mainline
instructions to binutils.

This patch adds the BFL instruction.

*** gas/ChangeLog ***

2019-04-15  Sudakshina Das  <[email protected]>
             Andre Vieira  <[email protected]>

	* config/tc-arm.c (T16_32_TAB): New entrie for bfl.
	(do_t_v8_1_branch): New switch case for bfl.
	(insns): New instruction for bfl.
	* testsuite/gas/arm/armv8_1-m-bfl.d: New.
	* testsuite/gas/arm/armv8_1-m-bfl.s: New.
	* testsuite/gas/arm/armv8_1-m-bfl-bad.s: New.
	* testsuite/gas/arm/armv8_1-m-bfl-bad.d: New.
	* testsuite/gas/arm/armv8_1-m-bfl-bad.l: New.
	* testsuite/gas/arm/armv8_1-m-bfl-rel.d: New.
	* testsuite/gas/arm/armv8_1-m-bfl-rel.s: New.

*** ld/ChangeLog ***

2019-04-15  Sudakshina Das  <[email protected]>

	* testsuite/ld-arm/bfl.s: New.
	* testsuite/ld-arm/bfl.d: New.
	* testsuite/ld-arm/arm-elf.exp: Add above test.

*** opcodes/ChangeLog ***

2019-04-15  Sudakshina Das  <[email protected]>

	* arm-dis.c (thumb32_opcodes): New instruction bfl.

gas/ChangeLog

@@ -1,3 +1,17 @@
+2019-04-15  Sudakshina Das  <[email protected]>
+            Andre Vieira  <[email protected]>
+
+	* config/tc-arm.c (T16_32_TAB): New entrie for bfl.
+	(do_t_v8_1_branch): New switch case for bfl.
+	(insns): New instruction for bfl.
+	* testsuite/gas/arm/armv8_1-m-bfl.d: New.
+	* testsuite/gas/arm/armv8_1-m-bfl.s: New.
+	* testsuite/gas/arm/armv8_1-m-bfl-bad.s: New.
+	* testsuite/gas/arm/armv8_1-m-bfl-bad.d: New.
+	* testsuite/gas/arm/armv8_1-m-bfl-bad.l: New.
+	* testsuite/gas/arm/armv8_1-m-bfl-rel.d: New.
+	* testsuite/gas/arm/armv8_1-m-bfl-rel.s: New.
+
 2019-04-15  Sudakshina Das  <[email protected]>
 
 	* config/tc-arm.c (md_pcrel_from_section): New switch case for

gas/config/tc-arm.c

@@ -10507,6 +10507,7 @@ encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
   X(_bcond, d000, f0008000),			\
   X(_bf,    0000, f040e001),			\
   X(_bfx,   0000, f060e001),			\
+  X(_bfl,   0000, f000c001),			\
   X(_bflx,  0000, f070e001),			\
   X(_bic,   4380, ea200000),			\
   X(_bics,  4380, ea300000),			\
@@ -13364,6 +13365,25 @@ do_t_branch_future (void)
 	  }
 	break;
 
+      case T_MNEM_bfl:
+	if (inst.operands[1].hasreloc == 0)
+	  {
+	    int val = inst.operands[1].imm;
+	    if (v8_1_branch_value_check (inst.operands[1].imm, 19, TRUE) == FAIL)
+	      as_bad (BAD_BRANCH_OFF);
+
+	    int immA = (val & 0x0007f000) >> 12;
+	    int immB = (val & 0x00000ffc) >> 2;
+	    int immC = (val & 0x00000002) >> 1;
+	    inst.instruction |= (immA << 16) | (immB << 1) | (immC << 11);
+	  }
+	  else
+	  {
+	    inst.relocs[1].type = BFD_RELOC_ARM_THUMB_BF19;
+	    inst.relocs[1].pc_rel = 1;
+	  }
+	break;
+
       case T_MNEM_bfx:
       case T_MNEM_bflx:
 	inst.instruction |= inst.operands[1].reg << 16;
@@ -21687,6 +21707,7 @@ static const struct asm_opcode insns[] =
 #define THUMB_VARIANT & arm_ext_v8_1m_main
  toC("bf",     _bf,	2, (EXPs, EXPs),	     t_branch_future),
  toC("bfx",    _bfx,	2, (EXPs, RRnpcsp),	     t_branch_future),
+ toC("bfl",    _bfl,	2, (EXPs, EXPs),	     t_branch_future),
  toC("bflx",   _bflx,	2, (EXPs, RRnpcsp),	     t_branch_future),
 };
 #undef ARM_VARIANT

gas/testsuite/gas/arm/armv8_1-m-bfl-bad.d

@@ -0,0 +1,4 @@
+#name: Invalid Armv8.1-M Mainline BFL instructions
+#source: armv8_1-m-bfl-bad.s
+#as: -march=armv8.1-m.main
+#error_output: armv8_1-m-bfl-bad.l

gas/testsuite/gas/arm/armv8_1-m-bfl-bad.l

@@ -0,0 +1,9 @@
+.*: Assembler messages:
+.*:6: Error: branch out of range or not a multiple of 2
+.*:7: Error: branch out of range or not a multiple of 2
+.*:8: Error: branch out of range or not a multiple of 2
+.*:9: Error: branch out of range or not a multiple of 2
+.*:11: Error: branch out of range or not a multiple of 2
+.*:12: Error: branch out of range or not a multiple of 2
+.*:13: Error: branch out of range or not a multiple of 2
+.*:14: Error: branch out of range or not a multiple of 2

gas/testsuite/gas/arm/armv8_1-m-bfl-bad.s

@@ -0,0 +1,14 @@
+	.syntax unified
+	.text
+	.thumb
+foo:
+	# OP0 : Unsigned, 5-bit, even
+	bfl  0, 36
+	bfl -2, 36
+	bfl  3, 36
+	bfl 32, 36
+	# OP1 : signed, 19-bit, even
+	bf  2, -5
+	bf  2,  5
+	bf  2,  262144
+	bf  2, -262146

gas/testsuite/gas/arm/armv8_1-m-bfl-rel.d

@@ -0,0 +1,10 @@
+#name: Valid Armv8.1-M Mainline BFL instruction with relocation
+#as: -march=armv8.1-m.main
+#objdump: -dr --prefix-addresses --show-raw-insn
+#skip: *-*-pe *-wince-*
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0[0-9a-f]+ <[^>]+> f0ff c7ff 	bfl	2, 00000000 <.target>
+			0: R_ARM_THM_BF18	.target

gas/testsuite/gas/arm/armv8_1-m-bfl-rel.s

@@ -0,0 +1,5 @@
+	.syntax unified
+	.text
+	.thumb
+foo:
+	bfl 2, .target

gas/testsuite/gas/arm/armv8_1-m-bfl.d

@@ -0,0 +1,13 @@
+#name: Valid Armv8.1-M Mainline BFL instruction
+#as: -march=armv8.1-m.main
+#objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0[0-9a-f]+ <[^>]+> f080 c803 	bfl	2, 0000000a <foo\+0xa>
+0[0-9a-f]+ <[^>]+> 4608      	mov	r0, r1
+0[0-9a-f]+ <[^>]+> f100 c801 	bfl	4, 0000000c <foo\+0xc>
+0[0-9a-f]+ <[^>]+> 460a      	mov	r2, r1
+0[0-9a-f]+ <[^>]+> 4613      	mov	r3, r2
+0[0-9a-f]+ <[^>]+> 4614      	mov	r4, r2

gas/testsuite/gas/arm/armv8_1-m-bfl.s

@@ -0,0 +1,12 @@
+	.syntax unified
+	.text
+	.thumb
+foo:
+	bfl 2, 6
+	mov r0, r1
+	bfl .LBranch, .LB2
+	mov r2, r1
+.LB2:
+	mov r3, r2
+.LBranch:
+	mov r4, r2

ld/ChangeLog

@@ -1,3 +1,9 @@
+2019-04-15  Sudakshina Das  <[email protected]>
+
+	* testsuite/ld-arm/bfl.s: New.
+	* testsuite/ld-arm/bfl.d: New.
+	* testsuite/ld-arm/arm-elf.exp: Add above test.
+
 2019-04-15  Sudakshina Das  <[email protected]>
 
 	* testsuite/ld-arm/bf.s: New.

ld/testsuite/ld-arm/arm-elf.exp

@@ -670,6 +670,9 @@ set armeabitests_nonacl {
      {"Armv8.1-M Mainline BF" "-r -Ttext 0x1000 --section-start .foo=0x1001000" "" "-march=armv8.1-m.main" {bf.s}
       {{objdump -dr bf.d}}
      "bf"}
+     {"Armv8.1-M Mainline BFL" "-r -Ttext 0x1000 --section-start .foo=0x1001000" "" "-march=armv8.1-m.main" {bfl.s}
+      {{objdump -dr bfl.d}}
+     "bfl"}
 
     {"R_ARM_THM_JUMP24 Relocation veneers: Short 1"
      "--no-fix-arm1176 --section-start destsect=0x00009000 --section-start .text=0x8000" ""

ld/testsuite/ld-arm/bfl.d

@@ -0,0 +1,14 @@
+
+.*:     file format elf32-.*arm
+
+
+Disassembly of section .text:
+
+00001000 <_start>:
+    1000:	f0ff c7ff 	bfl	2, 1001000 <bar>
+			1000: R_ARM_THM_BF18	bar
+
+Disassembly of section .foo:
+
+01001000 <bar>:
+ 1001000:	4770      	bx	lr

ld/testsuite/ld-arm/bfl.s

@@ -0,0 +1,19 @@
+	.global _start
+	.syntax unified
+
+@ We will place the section .text at 0x1000.
+
+	.text
+	.thumb_func
+
+_start:
+	bfl 2, bar
+
+@ We will place the section .foo at 0x1001000.
+
+	.section .foo, "xa"
+	.thumb_func
+
+bar:
+	bx lr
+

opcodes/ChangeLog

@@ -1,3 +1,7 @@
+2019-04-15  Sudakshina Das  <[email protected]>
+
+	* arm-dis.c (thumb32_opcodes): New instruction bfl.
+
 2019-04-15  Sudakshina Das  <[email protected]>
 
 	* arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.

opcodes/arm-dis.c

@@ -2753,6 +2753,8 @@ static const struct opcode32 thumb32_opcodes[] =
     0xf040e001, 0xf860f001, "bf%c\t%G, %W"},
   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
     0xf060e001, 0xf8f0f001, "bfx%c\t%G, %16-19S"},
+  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+    0xf000c001, 0xf800f001, "bfl%c\t%G, %Y"},
   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
     0xf070e001, 0xf8f0f001, "bflx%c\t%G, %16-19S"},