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[binutils, ARM, 9/16] New BFL instruction for Armv8.1-M Mainline
This patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils. This patch adds the BFL instruction. *** gas/ChangeLog *** 2019-04-15 Sudakshina Das <[email protected]> Andre Vieira <[email protected]> * config/tc-arm.c (T16_32_TAB): New entrie for bfl. (do_t_v8_1_branch): New switch case for bfl. (insns): New instruction for bfl. * testsuite/gas/arm/armv8_1-m-bfl.d: New. * testsuite/gas/arm/armv8_1-m-bfl.s: New. * testsuite/gas/arm/armv8_1-m-bfl-bad.s: New. * testsuite/gas/arm/armv8_1-m-bfl-bad.d: New. * testsuite/gas/arm/armv8_1-m-bfl-bad.l: New. * testsuite/gas/arm/armv8_1-m-bfl-rel.d: New. * testsuite/gas/arm/armv8_1-m-bfl-rel.s: New. *** ld/ChangeLog *** 2019-04-15 Sudakshina Das <[email protected]> * testsuite/ld-arm/bfl.s: New. * testsuite/ld-arm/bfl.d: New. * testsuite/ld-arm/arm-elf.exp: Add above test. *** opcodes/ChangeLog *** 2019-04-15 Sudakshina Das <[email protected]> * arm-dis.c (thumb32_opcodes): New instruction bfl.
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‎gas/ChangeLog

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2019-04-15 Sudakshina Das <[email protected]>
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Andre Vieira <[email protected]>
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* config/tc-arm.c (T16_32_TAB): New entrie for bfl.
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(do_t_v8_1_branch): New switch case for bfl.
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(insns): New instruction for bfl.
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* testsuite/gas/arm/armv8_1-m-bfl.d: New.
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* testsuite/gas/arm/armv8_1-m-bfl.s: New.
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* testsuite/gas/arm/armv8_1-m-bfl-bad.s: New.
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* testsuite/gas/arm/armv8_1-m-bfl-bad.d: New.
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* testsuite/gas/arm/armv8_1-m-bfl-bad.l: New.
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* testsuite/gas/arm/armv8_1-m-bfl-rel.d: New.
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* testsuite/gas/arm/armv8_1-m-bfl-rel.s: New.
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2019-04-15 Sudakshina Das <[email protected]>
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* config/tc-arm.c (md_pcrel_from_section): New switch case for

‎gas/config/tc-arm.c

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@@ -10507,6 +10507,7 @@ encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
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X(_bcond, d000, f0008000), \
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X(_bf, 0000, f040e001), \
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X(_bfx, 0000, f060e001), \
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X(_bfl, 0000, f000c001), \
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X(_bflx, 0000, f070e001), \
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X(_bic, 4380, ea200000), \
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X(_bics, 4380, ea300000), \
@@ -13364,6 +13365,25 @@ do_t_branch_future (void)
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}
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break;
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case T_MNEM_bfl:
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if (inst.operands[1].hasreloc == 0)
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{
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int val = inst.operands[1].imm;
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if (v8_1_branch_value_check (inst.operands[1].imm, 19, TRUE) == FAIL)
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as_bad (BAD_BRANCH_OFF);
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int immA = (val & 0x0007f000) >> 12;
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int immB = (val & 0x00000ffc) >> 2;
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int immC = (val & 0x00000002) >> 1;
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inst.instruction |= (immA << 16) | (immB << 1) | (immC << 11);
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}
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else
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{
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inst.relocs[1].type = BFD_RELOC_ARM_THUMB_BF19;
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inst.relocs[1].pc_rel = 1;
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}
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break;
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case T_MNEM_bfx:
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case T_MNEM_bflx:
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inst.instruction |= inst.operands[1].reg << 16;
@@ -21687,6 +21707,7 @@ static const struct asm_opcode insns[] =
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#define THUMB_VARIANT & arm_ext_v8_1m_main
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toC("bf", _bf, 2, (EXPs, EXPs), t_branch_future),
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toC("bfx", _bfx, 2, (EXPs, RRnpcsp), t_branch_future),
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toC("bfl", _bfl, 2, (EXPs, EXPs), t_branch_future),
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toC("bflx", _bflx, 2, (EXPs, RRnpcsp), t_branch_future),
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};
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#undef ARM_VARIANT

‎gas/testsuite/gas/arm/armv8_1-m-bfl-bad.d

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#name: Invalid Armv8.1-M Mainline BFL instructions
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#source: armv8_1-m-bfl-bad.s
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#as: -march=armv8.1-m.main
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#error_output: armv8_1-m-bfl-bad.l

‎gas/testsuite/gas/arm/armv8_1-m-bfl-bad.l

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.*: Assembler messages:
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.*:6: Error: branch out of range or not a multiple of 2
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.*:7: Error: branch out of range or not a multiple of 2
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.*:8: Error: branch out of range or not a multiple of 2
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.*:9: Error: branch out of range or not a multiple of 2
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.*:11: Error: branch out of range or not a multiple of 2
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.*:12: Error: branch out of range or not a multiple of 2
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.*:13: Error: branch out of range or not a multiple of 2
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.*:14: Error: branch out of range or not a multiple of 2

‎gas/testsuite/gas/arm/armv8_1-m-bfl-bad.s

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.syntax unified
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.text
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.thumb
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foo:
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# OP0 : Unsigned, 5-bit, even
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bfl 0, 36
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bfl -2, 36
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bfl 3, 36
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bfl 32, 36
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# OP1 : signed, 19-bit, even
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bf 2, -5
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bf 2, 5
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bf 2, 262144
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bf 2, -262146

‎gas/testsuite/gas/arm/armv8_1-m-bfl-rel.d

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#name: Valid Armv8.1-M Mainline BFL instruction with relocation
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#as: -march=armv8.1-m.main
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#objdump: -dr --prefix-addresses --show-raw-insn
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#skip: *-*-pe *-wince-*
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.*: +file format .*arm.*
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Disassembly of section .text:
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0[0-9a-f]+ <[^>]+> f0ff c7ff bfl 2, 00000000 <.target>
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0: R_ARM_THM_BF18 .target

‎gas/testsuite/gas/arm/armv8_1-m-bfl-rel.s

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.syntax unified
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.text
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.thumb
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foo:
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bfl 2, .target

‎gas/testsuite/gas/arm/armv8_1-m-bfl.d

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#name: Valid Armv8.1-M Mainline BFL instruction
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#as: -march=armv8.1-m.main
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#objdump: -dr --prefix-addresses --show-raw-insn
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.*: +file format .*arm.*
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Disassembly of section .text:
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0[0-9a-f]+ <[^>]+> f080 c803 bfl 2, 0000000a <foo\+0xa>
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0[0-9a-f]+ <[^>]+> 4608 mov r0, r1
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0[0-9a-f]+ <[^>]+> f100 c801 bfl 4, 0000000c <foo\+0xc>
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0[0-9a-f]+ <[^>]+> 460a mov r2, r1
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0[0-9a-f]+ <[^>]+> 4613 mov r3, r2
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0[0-9a-f]+ <[^>]+> 4614 mov r4, r2

‎gas/testsuite/gas/arm/armv8_1-m-bfl.s

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.syntax unified
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.text
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.thumb
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foo:
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bfl 2, 6
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mov r0, r1
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bfl .LBranch, .LB2
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mov r2, r1
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.LB2:
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mov r3, r2
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.LBranch:
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mov r4, r2

‎ld/ChangeLog

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2019-04-15 Sudakshina Das <[email protected]>
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* testsuite/ld-arm/bfl.s: New.
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* testsuite/ld-arm/bfl.d: New.
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* testsuite/ld-arm/arm-elf.exp: Add above test.
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2019-04-15 Sudakshina Das <[email protected]>
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* testsuite/ld-arm/bf.s: New.

‎ld/testsuite/ld-arm/arm-elf.exp

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@@ -670,6 +670,9 @@ set armeabitests_nonacl {
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{"Armv8.1-M Mainline BF" "-r -Ttext 0x1000 --section-start .foo=0x1001000" "" "-march=armv8.1-m.main" {bf.s}
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{{objdump -dr bf.d}}
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"bf"}
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{"Armv8.1-M Mainline BFL" "-r -Ttext 0x1000 --section-start .foo=0x1001000" "" "-march=armv8.1-m.main" {bfl.s}
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{{objdump -dr bfl.d}}
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"bfl"}
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{"R_ARM_THM_JUMP24 Relocation veneers: Short 1"
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"--no-fix-arm1176 --section-start destsect=0x00009000 --section-start .text=0x8000" ""

‎ld/testsuite/ld-arm/bfl.d

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.*: file format elf32-.*arm
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Disassembly of section .text:
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00001000 <_start>:
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1000: f0ff c7ff bfl 2, 1001000 <bar>
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1000: R_ARM_THM_BF18 bar
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Disassembly of section .foo:
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01001000 <bar>:
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1001000: 4770 bx lr

‎ld/testsuite/ld-arm/bfl.s

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.global _start
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.syntax unified
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@ We will place the section .text at 0x1000.
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.text
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.thumb_func
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_start:
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bfl 2, bar
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@ We will place the section .foo at 0x1001000.
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.section .foo, "xa"
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.thumb_func
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bar:
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bx lr
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‎opcodes/ChangeLog

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2019-04-15 Sudakshina Das <[email protected]>
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* arm-dis.c (thumb32_opcodes): New instruction bfl.
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2019-04-15 Sudakshina Das <[email protected]>
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* arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.

‎opcodes/arm-dis.c

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@@ -2753,6 +2753,8 @@ static const struct opcode32 thumb32_opcodes[] =
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0xf040e001, 0xf860f001, "bf%c\t%G, %W"},
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{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
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0xf060e001, 0xf8f0f001, "bfx%c\t%G, %16-19S"},
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{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
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0xf000c001, 0xf800f001, "bfl%c\t%G, %Y"},
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{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
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0xf070e001, 0xf8f0f001, "bflx%c\t%G, %16-19S"},
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