feat: non-interactive mode support

Author: Cnily03

.github/workflows/test.yml

@@ -19,6 +19,8 @@ jobs:
         run: sudo -E apt-get -y install iverilog gtkwave
       - name: Run TestBench
         run: make
+        env:
+          DEBIAN_FRONTEND: noninteractive
       - name: Upload simulation results
         uses: actions/upload-artifact@v4
         if: always()
@@ -29,3 +31,4 @@ jobs:
             **/*.vvp
             **/*.vcd
             **/*.out
+          retention-days: 7

Makefile

@@ -11,7 +11,11 @@ NODE := node
 RM := rm -rf
 
 # Flags
+ifeq ($(DEBIAN_FRONTEND),noninteractive)
 VVP_FLAGS := -n
+else
+VVP_FLAGS :=
+endif
 
 # Color output
 BLUE := \033[34m
@@ -24,11 +28,11 @@ RESET := \033[0m
 .SECONDARY:
 
 # Default target: transform and test
-all: inst test
+all: inst $(TOP_VERILOG_FILE)
 
 # Transform instruction file only
 inst:
-	@echo "$(CYAN)Analyzing instruction file...$(RESET)"
+	@echo "$(BLUE)Analyzing and Transforming $(CYAN)$(INST_ASM_FILE)$(BLUE) ...$(RESET)"
 	@$(NODE) transform.js $(INST_ASM_FILE)
 
 # Run test only
@@ -42,12 +46,12 @@ clean:
 # Help target
 help:
 	@echo "Usage:"
-	@echo "  make            - Transform instruction file and run test"
-	@echo "  make help       - Show this help message"
-	@echo "  make inst       - Analyze instruction file only"
-	@echo "  make test       - Run test only"
-	@echo "  make clean      - Remove build artifacts (*.vvp, *.vcd, *.out)"
-	@echo "  make <file>     - Simulate specified verilog file"
+	@echo "  make             - Transform instruction file and run test"
+	@echo "  make help        - Show this help message"
+	@echo "  make inst        - Analyze and transform instruction file only"
+	@echo "  make test        - Run test only"
+	@echo "  make clean       - Remove build artifacts (*.vvp, *.vcd, *.out)"
+	@echo "  make <file>      - Simulate specified verilog file"
 	@echo "       <file>.vvp"
 
 %.vvp:

README.md

@@ -103,10 +103,10 @@ Run `make test` to simulate the CPU. If the wave cannot meet the needs, modify t
 
 For example, you can modify `N_CLOCKS` to `10'd100` to simulate the CPU per 100 clocks, then enter `cont` in the terminal prompt to continue next 100 clocks of simulation.
 
-You can modify `N_OPERATE` to `$finish` to finish and exit the simulation after N_CLOCKS clocks. In [vvp flags](https://steveicarus.github.io/iverilog/usage/vvp_flags.html), option `-n` means `non-interactive ($stop = $finish)`, you can also comment the following line in [Makefile](Makefile).
+You can modify `N_OPERATE` to `$finish` to finish and exit the simulation after N_CLOCKS clocks. Or you can set environment variable `DEBIAN_FRONTEND=noninteractive` to add `-n` to [VVP_FLAGS](https://steveicarus.github.io/iverilog/usage/vvp_flags.html), which means `non-interactive ($stop = $finish)`. For example:
 
 ```shell
-VVP_FLAGS := -n
+DEBIAN_FRONTEND=noninteractive make
 ```
 
 ## Hardware Testing