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8086(FINAL).sch
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EESchema Schematic File Version 4
EELAYER 30 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 2 16
Title "8086 and Decode"
Date ""
Rev ""
Comp "UMBC 2021"
Comment1 "Christian Lostoski"
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Entry Wire Line
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Entry Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Entry Wire Line
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Wire Wire Line
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P 10150 5400
F 0 "CPU_DDecode2" H 10150 6381 50 0000 C CNN
F 1 "74LS245" H 10150 6290 50 0000 C CNN
F 2 "Package_DIP:DIP-20_W7.62mm" H 10150 5400 50 0001 C CNN
F 3 "http://www.ti.com/lit/gpn/sn74LS245" H 10150 5400 50 0001 C CNN
1 10150 5400
1 0 0 -1
$EndComp
Entry Wire Line
9250 2950 9350 3050
Wire Wire Line
9350 3050 9650 3050
Entry Wire Line
9250 3050 9350 3150
Wire Wire Line
9350 3150 9650 3150
Entry Wire Line
9250 3150 9350 3250
Wire Wire Line
9350 3250 9650 3250
Entry Wire Line
9250 3250 9350 3350
Wire Wire Line
9350 3350 9650 3350
Entry Wire Line
9250 3350 9350 3450
Wire Wire Line
9350 3450 9650 3450
Entry Wire Line
9250 3450 9350 3550
Wire Wire Line
9350 3550 9650 3550
Entry Wire Line
9250 3550 9350 3650
Wire Wire Line
9350 3650 9650 3650
Entry Wire Line
9250 3650 9350 3750
Text Label 9400 3050 0 50 ~ 0
AD0
Text Label 9400 3150 0 50 ~ 0
AD1
Text Label 9400 3250 0 50 ~ 0
AD2
Text Label 9400 3350 0 50 ~ 0
AD3
Text Label 9400 3450 0 50 ~ 0
AD4
Text Label 9400 3550 0 50 ~ 0
AD5
Text Label 9400 3650 0 50 ~ 0
AD6
Text Label 9400 3750 0 50 ~ 0
AD7
Wire Wire Line
9650 3750 9350 3750
Entry Wire Line
9250 4800 9350 4900
Wire Wire Line
9350 4900 9650 4900
Entry Wire Line
9250 4900 9350 5000
Wire Wire Line
9350 5000 9650 5000
Entry Wire Line
9250 5000 9350 5100
Wire Wire Line
9350 5100 9650 5100
Entry Wire Line
9250 5100 9350 5200
Wire Wire Line
9350 5200 9650 5200
Entry Wire Line
9250 5200 9350 5300
Wire Wire Line
9350 5300 9650 5300
Entry Wire Line
9250 5300 9350 5400
Wire Wire Line
9350 5400 9650 5400
Entry Wire Line
9250 5400 9350 5500
Wire Wire Line
9350 5500 9650 5500
Entry Wire Line
9250 5500 9350 5600
Text Label 9400 4900 0 50 ~ 0
AD8
Text Label 9400 5000 0 50 ~ 0
AD9
Text Label 9400 5100 0 50 ~ 0
AD10
Text Label 9400 5200 0 50 ~ 0
AD11
Text Label 9400 5300 0 50 ~ 0
AD12
Text Label 9400 5400 0 50 ~ 0
AD13
Text Label 9400 5500 0 50 ~ 0
AD14
Text Label 9400 5600 0 50 ~ 0
AD15
Wire Wire Line
9650 5600 9350 5600
Text Label 9250 2850 0 50 ~ 0
AD[0..15]
Text Label 4750 1750 0 50 ~ 0
~DEN
Text Label 9650 4050 2 50 ~ 0
~DEN
Text Label 9650 3950 2 50 ~ 0
DT~R
Text Label 9650 5800 2 50 ~ 0
DT~R
Text Label 9650 5900 2 50 ~ 0
~DEN
Wire Wire Line
10150 4350 10400 4350
$Comp
L power:GND #PWR011
U 1 1 6083EB10
P 10150 6300
F 0 "#PWR011" H 10150 6050 50 0001 C CNN
F 1 "GND" H 10155 6127 50 0000 C CNN
F 2 "" H 10150 6300 50 0001 C CNN
F 3 "" H 10150 6300 50 0001 C CNN
1 10150 6300
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR012
U 1 1 6083F138
P 10400 4350
F 0 "#PWR012" H 10400 4100 50 0001 C CNN
F 1 "GND" H 10405 4177 50 0000 C CNN
F 2 "" H 10400 4350 50 0001 C CNN
F 3 "" H 10400 4350 50 0001 C CNN
1 10400 4350
1 0 0 -1
$EndComp
Text HLabel 10650 3750 2 50 Output ~ 0
D7
Text HLabel 10650 3650 2 50 Output ~ 0
D6
Text HLabel 10650 3550 2 50 Output ~ 0
D5
Text HLabel 10650 3450 2 50 Output ~ 0
D4
Text HLabel 10650 3350 2 50 Output ~ 0
D3
Text HLabel 10650 3250 2 50 Output ~ 0
D2
Text HLabel 10650 3150 2 50 Output ~ 0
D1
Text HLabel 10650 3050 2 50 Output ~ 0
D0
Text HLabel 10650 5600 2 50 Output ~ 0
D15
Text HLabel 10650 5500 2 50 Output ~ 0
D14
Text HLabel 10650 5400 2 50 Output ~ 0
D13
Text HLabel 10650 5300 2 50 Output ~ 0
D12
Text HLabel 10650 5200 2 50 Output ~ 0
D11
Text HLabel 10650 5100 2 50 Output ~ 0
D10
Text HLabel 10650 5000 2 50 Output ~ 0
D9
Text HLabel 10650 4900 2 50 Output ~ 0
D8
Text Label 3050 2050 2 50 ~ 0
RESET
Text Label 3050 1650 2 50 ~ 0
CLK
Text HLabel 3200 2550 0 50 Input ~ 0
INTR
Text HLabel 4600 4650 2 50 Output ~ 0
~INTA
NoConn ~ 3200 2850
NoConn ~ 3200 3350
NoConn ~ 3200 3550
Text HLabel 4600 1950 2 50 Output ~ 0
~BHE~S7
Text Label 3050 1850 2 50 ~ 0
READY
$Comp
L power:GND #PWR03
U 1 1 6085F789
P 3850 5150
F 0 "#PWR03" H 3850 4900 50 0001 C CNN
F 1 "GND" H 3855 4977 50 0000 C CNN
F 2 "" H 3850 5150 50 0001 C CNN
F 3 "" H 3850 5150 50 0001 C CNN
1 3850 5150
1 0 0 -1
$EndComp
Wire Wire Line
2600 2350 3200 2350
Wire Wire Line
3050 2050 3200 2050
Wire Wire Line
3200 1850 3050 1850
Wire Wire Line
3200 1650 3050 1650
$Comp
L MCU_Intel:8086_Min_Mode CPU1
U 1 1 60761E58
P 3900 3150
F 0 "CPU1" H 3900 5131 50 0000 C CNN
F 1 "8086_Min_Mode" H 3900 5040 50 0000 C CNN
F 2 "Package_DIP:DIP-40_W15.24mm" H 3950 3250 50 0001 C CIN
F 3 "http://datasheets.chipdb.org/Intel/x86/808x/datashts/8086/231455-006.pdf" H 3900 3200 50 0001 C CNN
1 3900 3150
1 0 0 -1
$EndComp
Wire Wire Line
4600 1650 4750 1650
Text Label 4750 1650 0 50 ~ 0
DT~R
Wire Wire Line
4600 1750 4750 1750
Wire Wire Line
7750 750 8650 750
Wire Wire Line
8650 750 8650 700
Wire Wire Line
7750 4600 8650 4600
Wire Wire Line
8650 4600 8650 2750
Connection ~ 8650 750
Wire Wire Line
7750 2700 8650 2700
Connection ~ 8650 2700
Wire Wire Line
10150 750 8650 750
Connection ~ 8650 2750
Wire Wire Line
8650 2750 8650 2700
Wire Wire Line
10150 4600 10900 4600
Wire Wire Line
10900 4600 10900 2750
$Sheet
S 800 5050 950 1150
U 60790D94
F0 "Clock" 50
F1 "../CLK.sch" 50
F2 "CLK" O R 1750 5150 50
F3 "RESET" O R 1750 5300 50
F4 "READY" O R 1750 5450 50
F5 "PCLK" O R 1750 5600 50
$EndSheet
Text Label 1850 5150 0 50 ~ 0
CLK
Text Label 1850 5300 0 50 ~ 0
RESET
Text Label 1850 5450 0 50 ~ 0
READY
Wire Wire Line
1750 5600 1850 5600
Text HLabel 1850 5600 2 50 Output ~ 0
PCLK
Wire Wire Line
1750 5450 1850 5450
Wire Wire Line
1750 5300 2200 5300
Text HLabel 2200 5300 2 50 Output ~ 0
RESET
Wire Wire Line
1750 5150 2200 5150
Text HLabel 2200 5150 2 50 Output ~ 0
CLK
Text Label 4750 4450 0 50 ~ 0
Write
$Comp
L power:GND #PWR0101
U 1 1 60B7CA3A
P 2200 1350
F 0 "#PWR0101" H 2200 1100 50 0001 C CNN
F 1 "GND" H 2205 1177 50 0000 C CNN
F 2 "" H 2200 1350 50 0001 C CNN
F 3 "" H 2200 1350 50 0001 C CNN
1 2200 1350
-1 0 0 1
$EndComp
$Comp
L power:VCC #PWR0120
U 1 1 61629C6A
P 3200 4650
F 0 "#PWR0120" H 3200 4500 50 0001 C CNN
F 1 "VCC" V 3215 4777 50 0000 L CNN
F 2 "" H 3200 4650 50 0001 C CNN
F 3 "" H 3200 4650 50 0001 C CNN
1 3200 4650
0 -1 -1 0
$EndComp
Wire Wire Line
7750 6200 7450 6200
Connection ~ 7450 6200
$Comp
L power:PWR_FLAG #FLG0101
U 1 1 61A61862
P 4200 1000
F 0 "#FLG0101" H 4200 1075 50 0001 C CNN
F 1 "PWR_FLAG" H 4200 1173 50 0000 C CNN
F 2 "" H 4200 1000 50 0001 C CNN
F 3 "~" H 4200 1000 50 0001 C CNN
1 4200 1000
1 0 0 -1
$EndComp
Wire Wire Line
1800 1350 2200 1350
Connection ~ 2200 1350
Wire Wire Line
3800 4950 3800 5150
Wire Wire Line
3800 5150 3850 5150
Wire Wire Line
4000 4950 4000 5150
$Comp
L power:PWR_FLAG #FLG0104
U 1 1 61A86F05
P 4000 5150
F 0 "#FLG0104" H 4000 5225 50 0001 C CNN
F 1 "PWR_FLAG" H 4000 5323 50 0000 C CNN
F 2 "" H 4000 5150 50 0001 C CNN
F 3 "~" H 4000 5150 50 0001 C CNN
1 4000 5150
0 1 1 0
$EndComp
Wire Wire Line
4000 5150 3850 5150
Connection ~ 4000 5150
Connection ~ 3850 5150
Wire Wire Line
7200 2200 7250 2200
Connection ~ 7250 2200
Wire Wire Line
7250 2200 7250 2050
Wire Wire Line
9600 2200 9650 2200
Connection ~ 9650 2200
Wire Wire Line
9650 2200 9650 2350
Wire Wire Line
3900 1000 4200 1000
Connection ~ 4200 1000
Wire Wire Line
4200 1000 4700 1000
Wire Wire Line
8650 750 8650 2700
Wire Wire Line
7250 4000 7250 4300
Wire Wire Line
10150 2750 8650 2750
Wire Wire Line
10900 2750 10150 2750
Connection ~ 10150 2750
$Comp
L 74xx:74LS245 CPU_DDecode1
U 1 1 60814065
P 10150 3550
F 0 "CPU_DDecode1" H 10150 4531 50 0000 C CNN
F 1 "74LS245" H 10150 4440 50 0000 C CNN
F 2 "Package_DIP:DIP-20_W7.62mm" H 10150 3550 50 0001 C CNN
F 3 "http://www.ti.com/lit/gpn/sn74LS245" H 10150 3550 50 0001 C CNN
1 10150 3550
1 0 0 -1
$EndComp
Wire Wire Line
7250 5900 7250 6200
Wire Wire Line
10150 6200 10150 6300
Wire Wire Line
1600 2350 1800 2350
Wire Bus Line
9250 2850 9250 5500
Wire Bus Line
6850 850 6850 5100
Wire Bus Line
4850 2000 4850 4050
$EndSCHEMATC