Merge pull request #346 from antmicro/bump-interchange

acomodi · web-flow · commit 14b8461f9ccc · 2021-09-14T09:18:22.000+02:00
bump interchange
diff --git a/.github/kokoro/steps/hostsetup.sh b/.github/kokoro/steps/hostsetup.sh
@@ -15,6 +15,7 @@ echo "Host adding PPAs"
 echo "----------------------------------------"
 wget -O - https://apt.kitware.com/keys/kitware-archive-latest.asc 2>/dev/null | sudo apt-key add -
 sudo apt-add-repository 'deb https://apt.kitware.com/ubuntu/ xenial main'
+sudo add-apt-repository ppa:openjdk-r/ppa
 echo "----------------------------------------"
 
 echo
@@ -63,6 +64,7 @@ sudo apt-get install -y \
         python3-virtualenv \
         python3-yaml \
         virtualenv \
+        openjdk-11-jdk
 
 if [ -z "${BUILD_TOOL}" ]; then
     export BUILD_TOOL=make
@@ -75,6 +77,12 @@ echo "========================================"
 echo "Setting up conda environment"
 echo "----------------------------------------"
 (
+	echo " Set JAVA 11 as default"
+	echo "----------------------------------------"
+	sudo update-alternatives --set java /usr/lib/jvm/java-11-openjdk-amd64/bin/java
+	java -version
+	echo "----------------------------------------"
+
 	echo
 	echo " Installing symbiflow and quicklogic"
 	echo "----------------------------------------"
diff --git a/.gitmodules b/.gitmodules
@@ -22,3 +22,6 @@
 [submodule "third_party/fpga-interchange-schema"]
 	path = third_party/fpga-interchange-schema
 	url = https://github.com/SymbiFlow/fpga-interchange-schema.git
+[submodule "third_party/RapidWright"]
+	path = third_party/RapidWright
+	url = https://github.com/Xilinx/RapidWright.git
diff --git a/Makefile b/Makefile
@@ -28,9 +28,10 @@ SYMBIFLOW_DEVICES = xc7a50t xc7a100t xc7a200t xc7z010 xc7z020
 QUICKLOGIC_ARCHIVE = quicklogic.tar.gz
 QUICKLOGIC_URL = https://storage.googleapis.com/symbiflow-arch-defs-install/quicklogic-arch-defs-63c3d8f9.tar.gz
 
-INTERCHANGE_BASE_URL = https://storage.googleapis.com/fpga-interchange-tests/artifacts/prod/foss-fpga-tools/fpga-interchange-tests/presubmit/143/20210715-090243
-INTERCHANGE_VERSION = b00b616
+INTERCHANGE_BASE_URL = https://storage.googleapis.com/fpga-interchange-tests/artifacts/prod/foss-fpga-tools/fpga-interchange-tests/continuous/44/20210909-090121
+INTERCHANGE_VERSION = 839e153
 INTERCHANGE_DEVICES = xc7a35t xc7a100t xc7a200t xc7z010
+RAPIDWRIGHT_PATH = $(TOP_DIR)/third_party/RapidWright
 
 
 third_party/make-env/conda.mk:
@@ -62,6 +63,9 @@ install_interchange:
 	for device in ${INTERCHANGE_DEVICES}; do \
 		wget -qO- ${INTERCHANGE_BASE_URL}/interchange-$${device}-${INTERCHANGE_VERSION}.tar.xz | tar -xJC env/interchange/devices; \
 	done
+	pushd ${RAPIDWRIGHT_PATH} && \
+		make update_jars && \
+		popd
 
 install_quicklogic:
 	mkdir -p env/quicklogic
diff --git a/conf/nextpnr/environment.yml b/conf/nextpnr/environment.yml
@@ -6,7 +6,7 @@ dependencies:
   - litex-hub::yosys=0.9_5530_gc016f6a4=20210730_085634_py37
   - litex-hub::yosys-symbiflow-plugins=1.0.0_7_368_gfc33276=20210730_085634
   - litex-hub::vtr-optimized=8.0.0_3614_gb3b34e77a=20210507_125510
-  - litex-hub::nextpnr-fpga_interchange=v0.0_3730_g0991003d=20210730_085634_py37
+  - litex-hub::nextpnr-fpga_interchange=v0.0_3787_g67bd349e=20210818_135210_py37
   - litex-hub::nextpnr-ice40=0.0.0_3403_g3fd1ee77=20210722_152338_py37
   - litex-hub::nextpnr-xilinx=v0.0_2840_g86500ec6=20210722_152338_py37
   - litex-hub::nextpnr-nexus=0.0.0_3403_g3fd1ee77=20210813_070938_py37
diff --git a/env.sh b/env.sh
@@ -37,6 +37,8 @@ path_remove ${QUICKLOGIC}/install/bin
 #Set now environment variables
 environment=${1:-xilinx-a35t}
 
+export RAPIDWRIGHT_PATH=${FPGA_TOOL_PERF_BASE_DIR}/third_party/RapidWright
+
 if [ "quicklogic" == ${environment} ]; then
     . ${FPGA_TOOL_PERF_BASE_DIR}/env/conda/bin/activate quicklogic
     export PATH=${QUICKLOGIC}/quicklogic-arch-defs/bin:${PATH}
diff --git a/infrastructure/tasks.py b/infrastructure/tasks.py
@@ -45,17 +45,14 @@ def iter_options(self):
 
                 toolchains = vendors[vendor]["toolchains"]
                 vendor_boards = vendors[vendor]["boards"]
-                blacklisted_toolchains = list()
-                if "blacklisted_toolchains" in project_dict.keys():
-                    blacklisted_toolchains = project_dict[
-                        "blacklisted_toolchains"]
+                skip_toolchains = project_dict.get("skip_toolchains", list())
 
                 boards = [
                     board for board in project_boards if board in vendor_boards
                 ]
 
                 for toolchain, board in list(product(toolchains, boards)):
-                    if toolchain not in blacklisted_toolchains:
+                    if toolchain not in skip_toolchains:
                         combinations.add((project, toolchain, board))
 
         return combinations
diff --git a/project/axi-lite-reg.json b/project/axi-lite-reg.json
@@ -8,5 +8,6 @@
     "vendors": {
         "xilinx": ["zybo"]
     },
-    "required_toolchains": ["vivado", "vpr"]
+    "required_toolchains": ["vivado", "vpr"],
+    "skip_toolchains": ["nextpnr-fpga-interchange"]
 }
diff --git a/project/daisho-usb3.json b/project/daisho-usb3.json
@@ -31,6 +31,7 @@
 	"xilinx": ["nexys-video"]
     },
 
-    "required_toolchains": ["vivado", "yosys-vivado"]
+    "required_toolchains": ["vivado", "yosys-vivado"],
+    "skip_toolchains": ["nextpnr-fpga-interchange"]
 }
 
diff --git a/project/hamsternz-hdmi.json b/project/hamsternz-hdmi.json
@@ -30,5 +30,5 @@
         "xilinx": ["nexys-video", "nexys"]
     },
     "required_toolchains": ["vivado"],
-    "blacklisted_toolchains": ["nextpnr-fpga-interchange"]
+    "skip_toolchains": ["nextpnr-fpga-interchange"]
 }
diff --git a/project/picosoc.json b/project/picosoc.json
@@ -18,5 +18,6 @@
     "vendors": {
         "xilinx": ["basys3", "nexys"]
     },
-    "required_toolchains": ["vivado", "yosys-vivado", "vpr", "vpr-fasm2bels"]
+    "required_toolchains": ["vivado", "yosys-vivado", "vpr", "vpr-fasm2bels"],
+    "skip_toolchains": ["nextpnr-fpga-interchange"]
 }
diff --git a/project/vexriscv.json b/project/vexriscv.json
@@ -14,5 +14,6 @@
     "vendors": {
         "xilinx": ["arty-a35t", "arty-a100t", "basys3", "zybo", "nexys-video"]
     },
-    "required_toolchains": ["vivado", "yosys-vivado", "vpr", "vpr-fasm2bels"]
+    "required_toolchains": ["vivado", "yosys-vivado", "vpr", "vpr-fasm2bels"],
+    "skip_toolchains": ["nextpnr-fpga-interchange"]
 }
diff --git a/third_party/RapidWright b/third_party/RapidWright
@@ -0,0 +1 @@
+Subproject commit 54d1ce7f33ef5ad44257dd4c7b643783b2f49d65
diff --git a/toolchains/symbiflow.py b/toolchains/symbiflow.py
@@ -15,7 +15,7 @@
 import edalize
 
 from toolchains.toolchain import Toolchain
-from utils.utils import Timed, have_exec, which
+from utils.utils import Timed, have_exec, which, get_vivado_max_freq
 from infrastructure.tool_parameters import ToolParametersHelper
 
 YOSYS_REGEXP = re.compile("(Yosys [a-z0-9+.]+) (\(git sha1) ([a-z0-9]+),.*")
@@ -1109,39 +1109,38 @@ def prepare_edam(self):
 
         return edam
 
+    def run_steps(self):
+        with Timed(self, 'fasm'):
+            self.backend.build_main(self.project_name + '.fasm')
+        with Timed(self, 'bitstream'):
+            self.backend.build_main(self.project_name + '.bit')
+
     def run(self):
-        NextpnrGeneric.generic_run(self, self.prepare_edam)
+        with Timed(self, 'total'):
+            with Timed(self, 'prepare'):
+                self.edam = self.prepare_edam()
+                os.environ["EDALIZE_LAUNCHER"] = f"source {self.env_script} &&"
+                self.backend = edalize.get_edatool('symbiflow')(
+                    edam=self.edam, work_root=self.out_dir
+                )
+                self.backend.configure("")
 
-    # FIXME: currently we do not have precise timing info for this variant.
-    # Fill the clock data with what we have...
-    def max_freq(self):
-        """Returns the max frequencies of the implemented design."""
-        log_file = os.path.join(self.out_dir, self.nextpnr_log)
+            self.backend.build_main(self.project_name + '.phys')
+            self.run_steps()
 
-        clocks = dict()
+        with Timed(self, 'report_timing'):
+            self.backend.build_main(self.project_name + '.timing')
 
-        with open(log_file, "r") as file:
-            for line in file:
-                if "target frequency" in line:
-                    regex = "target frequency ([0-9]*\.[0-9]*)"
-                    match = re.search(regex, line)
-                    if match:
-                        clk_name = 'clk'
-                        clk_freq = float(match.groups()[0])
-                        req_clk_freq = clk_freq
+        del os.environ["EDALIZE_LAUNCHER"]
 
-                        clocks[clk_name] = dict()
-                        clocks[clk_name]['actual'] = float(
-                            "{:.3f}".format(clk_freq)
-                        )
-                        clocks[clk_name]['requested'] = float(
-                            "{:.3f}".format(req_clk_freq)
-                        )
-                        clocks[clk_name]['met'] = True
-                        clocks[clk_name]['setup_violation'] = 0
-                        clocks[clk_name]['hold_violation'] = 0
+        self.add_runtimes()
+        self.add_wirelength()
 
-        return clocks
+    # FIXME: currently we do not have precise timing info for this variant.
+    # Fill the clock data with what we have...
+    def max_freq(self):
+        report_file = os.path.join(self.out_dir, f"{self.project_name}.timing")
+        return get_vivado_max_freq(report_file)
 
 
 class NextpnrXilinx(NextpnrGeneric):
diff --git a/toolchains/toolchain.py b/toolchains/toolchain.py
@@ -268,7 +268,11 @@ def get_runtimes(self):
             'overhead': ['overhead'],
             'checkpoint': ['open_checkpoint'],
             'bitstream': ['write_bitstream', 'bitstream'],
-            'reports': ['report_power', 'report_methodology', 'report_drc'],
+            'reports':
+                [
+                    'report_power', 'report_methodology', 'report_drc',
+                    'report_timing'
+                ],
             'total': ['total'],
             'fasm2bels': ['fasm2bels'],
             'link design': ['link_design'],

Original file line number	Diff line number	Diff line change
`@@ -8,5 +8,6 @@`
`8`	`8`	`"vendors": {`
`9`	`9`	`"xilinx": ["zybo"]`
`10`	`10`	`},`
`11`		`- "required_toolchains": ["vivado", "vpr"]`
	`11`	`+ "required_toolchains": ["vivado", "vpr"],`
	`12`	`+ "skip_toolchains": ["nextpnr-fpga-interchange"]`
`12`	`13`	`}`
Original file line number	Diff line number	Diff line change
`@@ -31,6 +31,7 @@`
`31`	`31`	`"xilinx": ["nexys-video"]`
`32`	`32`	`},`
`33`	`33`
`34`		`- "required_toolchains": ["vivado", "yosys-vivado"]`
	`34`	`+ "required_toolchains": ["vivado", "yosys-vivado"],`
	`35`	`+ "skip_toolchains": ["nextpnr-fpga-interchange"]`
`35`	`36`	`}`
`36`	`37`
Original file line number	Diff line number	Diff line change
`@@ -30,5 +30,5 @@`
`30`	`30`	`"xilinx": ["nexys-video", "nexys"]`
`31`	`31`	`},`
`32`	`32`	`"required_toolchains": ["vivado"],`
`33`		`- "blacklisted_toolchains": ["nextpnr-fpga-interchange"]`
	`33`	`+ "skip_toolchains": ["nextpnr-fpga-interchange"]`
`34`	`34`	`}`
Original file line number	Diff line number	Diff line change
`@@ -18,5 +18,6 @@`
`18`	`18`	`"vendors": {`
`19`	`19`	`"xilinx": ["basys3", "nexys"]`
`20`	`20`	`},`
`21`		`- "required_toolchains": ["vivado", "yosys-vivado", "vpr", "vpr-fasm2bels"]`
	`21`	`+ "required_toolchains": ["vivado", "yosys-vivado", "vpr", "vpr-fasm2bels"],`
	`22`	`+ "skip_toolchains": ["nextpnr-fpga-interchange"]`
`22`	`23`	`}`