Use scalautils lib to generate machine code from assembly in tests

Author: carlosedp

build.sbt

@@ -16,11 +16,12 @@ Global / semanticdbVersion                                 := "4.4.28" //scalafi
 Global / onChangedBuildSource                              := ReloadOnSourceChanges
 
 Compile / run / mainClass := Some("chiselv.Toplevel")
+Test / logBuffered        := false
 
 lazy val chiselv = (project in file("."))
   .settings(
     name         := "chiselv",
-    version      := "0.0.1",
+    version      := "1.0.0",
     scalaVersion := "2.13.6",
   )
 
@@ -30,7 +31,7 @@ val defaultVersions = Map(
   "chiseltest"       -> "0.5-SNAPSHOT",
   "scalatest"        -> "3.2.10",
   "organize-imports" -> "0.5.0",
-  "scalautils"       -> "0.5.0",
+  "scalautils"       -> "0.7.0",
 )
 
 // Import libraries

src/test/scala/CPUSingleCycleIOSpec.scala

@@ -4,7 +4,10 @@ import chiseltest._
 import chiseltest.experimental._
 import org.scalatest._
 
+import com.carlosedp.scalautils.riscvassembler._
+
 import java.io.{File, PrintWriter}
+import java.nio.file.{Files, Paths, DirectoryNotEmptyException}
 
 import flatspec._
 import matchers._
@@ -29,49 +32,64 @@ class CPUSingleCycleIOWrapper(
   val timerCounter = expose(core.timer0.counter)
 }
 
-class CPUSingleCycleIOSpec extends AnyFlatSpec with ChiselScalatestTester with should.Matchers {
+class CPUSingleCycleIOSpec
+  extends AnyFlatSpec
+  with ChiselScalatestTester
+  with BeforeAndAfterEach
+  with BeforeAndAfter
+  with should.Matchers {
   behavior of "GPIO"
 
   val cpuFrequency          = 25000000
   val bitWidth              = 32
   val instructionMemorySize = 1 * 1024
   val memorySize            = 1 * 1024
   val ms                    = cpuFrequency / 1000
+  var memoryfile            = ""
+  val tmpdir                = "tmphex"
+
+  before {
+    Files.createDirectories(Paths.get(tmpdir));
+  }
+  after {
+    try {
+      Files.deleteIfExists(Paths.get(tmpdir));
+    } catch {
+      case _: DirectoryNotEmptyException =>
+      // println("Directory not empty")
+    }
+  }
+  override def beforeEach(): Unit =
+    memoryfile =
+      Paths.get(tmpdir, scala.util.Random.alphanumeric.filter(_.isLetter).take(15).mkString + ".hex").toString()
+  override def afterEach(): Unit = {
+    val _ = new File(memoryfile).delete()
+  }
 
-  def defaultDut(memoryfile: String) =
+  def defaultDut(prog: String) = {
+    val hex = RISCVAssembler.fromString(prog)
+    new PrintWriter(new File(memoryfile)) { write(hex); close }
     test(new CPUSingleCycleIOWrapper(cpuFrequency, bitWidth, instructionMemorySize, memorySize, memoryfile))
       .withAnnotations(
         Seq(
           WriteVcdAnnotation,
           VerilatorBackendAnnotation,
         )
       )
+  }
 
   it should "write to GPIO0" in {
-    val filename = "CPUSpecMemoryTestFileGPIO0.hex"
-    /*
-            lui x1, %hi(0x30001000)
-            addi x5, x0, -1
-            addi x3, x3, 1
-            addi x4, x0, 7
-            sw x5, 0(x1)
-    loop:   add x2, x2, x3
-            sw x2, 4(x1)
-            jal x0, loop
-     */
-    new PrintWriter(new File(filename)) {
-      write("""
-      300010b7
-      fff00293
-      00118193
-      00700213
-      0050a023
-      00310133
-      0020a223
-      ff9ff06f
-    """.stripMargin); close
-    }
-    defaultDut(filename) { c =>
+    val prog = """
+    lui x1, 0x30001000
+    addi x5, x0, -1
+    addi x3, x3, 1
+    addi x4, x0, 7
+    sw x5, 0(x1)
+    add x2, x2, x3
+    sw x2, 4(x1)
+    jal x0, -8
+    """
+    defaultDut(prog) { c =>
       c.clock.setTimeout(0)
       c.registers(1).peek().litValue should be(0)
       c.registers(2).peek().litValue should be(0)
@@ -104,29 +122,18 @@ class CPUSingleCycleIOSpec extends AnyFlatSpec with ChiselScalatestTester with s
       c.clock.step(1) // sw
       c.GPIO0_value.peek().litValue should be(2)
     }
-    new File(filename).delete()
   }
 
   behavior of "Timer"
   it should "read timer and wait for 2 ms" in {
-    val filename = "CPUSpecMemoryTestFileTimer0_1.hex"
-    /*
-    main:   lui x1, %hi(0x30003000)
+    val prog = """
+    main:   lui x1, 0x30003000
             addi x2, x0, 2
     wait:   lw x3, 0(x1)
-            bne x2, x3, wait
+            bne x2, x3, -4
     cont:   addi x4, x0, 1
-     */
-    new PrintWriter(new File(filename)) {
-      write("""
-    300030b7
-    00200113
-    0000a183
-    fe311ee3
-    00100213
-    """.stripMargin); close
-    }
-    defaultDut(filename) { c =>
+    """
+    defaultDut(prog) { c =>
       c.clock.setTimeout(0)
       c.registers(1).peek().litValue should be(0)
       c.registers(2).peek().litValue should be(0)
@@ -148,34 +155,20 @@ class CPUSingleCycleIOSpec extends AnyFlatSpec with ChiselScalatestTester with s
       c.clock.step(1) // addi
       c.registers(4).peek().litValue should be(1)
     }
-    new File(filename).delete()
   }
 
   it should "reset timer after 1ms and wait for 1 ms" in {
-    val filename = "CPUSpecMemoryTestFileTimer0_2.hex"
-    /*
-    main:   lui x1, %hi(0x30003000)
+    val prog = """
+    main:   lui x1, 0x30003000
             addi x2, x0, 1
     wait:   lw x3, 0(x1)
-            bne x2, x3, wait
+            bne x2, x3, -4
     cont:   sw x0, 0(x1)
     wait2:  lw x3, 0(x1)
-            bne x2, x3, wait2
+            bne x2, x3, -4
     cont2:  addi x3, x0, 2
-     */
-    new PrintWriter(new File(filename)) {
-      write("""
-      300030b7
-      00100113
-      0000a183
-      fe311ee3
-      0000a023
-      0000a183
-      fe311ee3
-      00200193
-    """.stripMargin); close
-    }
-    defaultDut(filename) { c =>
+    """
+    defaultDut(prog) { c =>
       c.clock.setTimeout(0)
       c.registers(1).peek().litValue should be(0)
       c.registers(2).peek().litValue should be(0)
@@ -207,6 +200,5 @@ class CPUSingleCycleIOSpec extends AnyFlatSpec with ChiselScalatestTester with s
       c.clock.step(1) // addi
       c.registers(3).peek().litValue should be(2)
     }
-    new File(filename).delete()
   }
 }