Creating ports with name "primitive" leads to invalid verilog

[UnsignedByte]

Just found this issue out with @rachitnigam; Ports can be named primitive which is a reserved verilog keyword, thus leading to verilog that does not compile.

[rachitnigam]

We should add this to RESERVED_NAMES and make sure that port names go through the name generator.

[UnsignedByte]

The same is true for the port name expect