Optimizations

[sgpthomas]

FuTIL optimizations

• Redundancy elimination (smart constructors for and and or guards #141)
• Static Timing (Don't index using Id #154)
• Resource Sharing
• Pipelining (Control operator for Pipelining #200)
• Bitwidth analysis (Bitwidth Reduction #198)
• Control pipelining (Reducing control fan-out #382)

Verilog optimizations

• Don't generate priority logic for muxes. (See writeup) (Non-priority logic for guarded assignments #1423)
• Generate one-hot encoded FSM (See reasons, more explanation about FSM coding style)

[rachitnigam]

What's "redundancy elimination"?

[sampsyo]

That was the notion we discussed briefly about a "final-stage" cleanup to eliminate parts of guards like & 1 that are artifacts of earlier passes.

[rachitnigam]

Created separate issues for resource sharing (#197) and bitwidth analysis (#198). The others are either not optimizations (pipelining) or unclear how to implement them (control pipelining).

[rachitnigam]

Added one-hot encoding optimization for generated FSMs.

[rachitnigam]

This is generic and in-actionable enough that I will close this