Runtime assertion support

[rachitnigam]

One thing I often keep wanting to do is document a compilation invariant by generating an assertion checked by simulation tools. I realized one way to do this without changing the language is adding a std_assert primitive:

module std_assert(input logic in);
  always_comb begin
    if (!in)
       assert("Assertion failed")
  end
endmodule

Then, user-level programs can simply generate an assignment to the std_assert module and ensure that some condition holds:

cells {
  a0 = std_assert()
}

wires {
  a0.in = cond;
}

[sampsyo]

Yeah, seems cool. It would be great if the interpreter/debugger treated this as an automatic breakpoint (i.e., execution stops by default when one of these fails, just as if you had set a breakpoint there).

Also, maybe this goes without saying, but it would also be neat if there were a pass to remove these calls when we are generating synthesizable Verilog.