cpu: Use relaxed ordering on AArch64.

This changes the codegen for places where we call `cpu::features()` as expected.

Examples:

```
 	adrp	x8, :got:_ZN4ring3cpu3arm12featureflags8FEATURES17habb4a2487137fb15E
 	mov	x19, x0
	ldr	x8, [x8, :got_lo12:_ZN4ring3cpu3arm12featureflags8FEATURES17habb4a2487137fb15E]
-	ldar	x8, [x8]
+	ldr	x8, [x8]
 	cbz	x8, .LBB86_2
```

```
 	adrp	x8, :got:_ZN4ring3cpu3arm12featureflags8FEATURES17habb4a2487137fb15E
 	mov	x19, x4
 	mov	x20, x3
 	ldr	x8, [x8, :got_lo12:_ZN4ring3cpu3arm12featureflags8FEATURES17habb4a2487137fb15E]
 	mov	x21, x2
 	mov	x22, x0
 	sub	x23, x3, #4
-	ldar	x8, [x8]
+	ldr	x8, [x8]
 	cbz	x8, .LBB84_8
```

Author: briansmith

src/cpu/arm.rs

@@ -94,6 +94,7 @@ pub(super) mod featureflags {
         cpu,
         polyfill::{once_cell::race, usize_from_u32},
     };
+    use cfg_if::cfg_if;
     use core::num::NonZeroUsize;
     #[cfg(all(target_arch = "arm", target_endian = "little"))]
     use core::sync::atomic::{AtomicU32, Ordering};
@@ -158,7 +159,17 @@ pub(super) mod featureflags {
         features
     }
 
-    static FEATURES: race::OnceNonZeroUsize = race::OnceNonZeroUsize::new();
+    cfg_if! {
+        if #[cfg(all(target_arch = "aarch64", target_endian = "little"))] {
+            // On AArch64, we store all feature flags in `FEATURES`.
+            type FeaturesOrdering = race::Relaxed;
+        } else if #[cfg(all(target_arch = "arm", target_endian = "little"))] {
+            // On 32-bit ARM, we also have a separate flag for NEON.
+            type FeaturesOrdering = race::AcquireRelease;
+        }
+    }
+
+    static FEATURES: race::OnceNonZeroUsize<FeaturesOrdering> = race::OnceNonZeroUsize::new();
 
     // TODO(MSRV): There is no "pmull" feature listed from
     // `rustc --print cfg --target=aarch64-apple-darwin`. Originally ARMv8 tied

src/cpu/intel.rs

@@ -82,7 +82,7 @@ pub(super) mod featureflags {
         features
     }
 
-    static FEATURES: race::OnceNonZeroUsize = race::OnceNonZeroUsize::new();
+    static FEATURES: race::OnceNonZeroUsize<race::AcquireRelease> = race::OnceNonZeroUsize::new();
 
     #[cfg(target_arch = "x86")]
     #[rustfmt::skip]

src/polyfill/once_cell/race.rs

@@ -27,29 +27,61 @@
 // on another thread) using `Ordering::Release`, so we must use
 // `Ordering::Acquire` to ensure that store "happens-before" this load.
 
-use core::sync::atomic;
-
-use atomic::{AtomicUsize, Ordering};
+use cfg_if::cfg_if;
+use core::marker::PhantomData;
 use core::num::NonZeroUsize;
+use core::sync::atomic::{self, AtomicUsize};
+
+pub trait Ordering {
+    const ACQUIRE: atomic::Ordering;
+    const RELEASE: atomic::Ordering;
+}
+
+cfg_if! {
+    if #[cfg(any(all(target_arch = "arm", target_endian = "little"),
+                 target_arch = "x86",
+                 target_arch = "x86_64"))]
+    {
+        pub struct AcquireRelease(());
+
+        impl Ordering for AcquireRelease {
+            const ACQUIRE: atomic::Ordering = atomic::Ordering::Acquire;
+            const RELEASE: atomic::Ordering = atomic::Ordering::Release;
+        }
+    }
+}
+
+cfg_if! {
+    if #[cfg(all(target_arch = "aarch64", target_endian = "little"))] {
+        pub struct Relaxed(());
+
+        impl Ordering for Relaxed {
+            const ACQUIRE: atomic::Ordering = atomic::Ordering::Relaxed;
+            const RELEASE: atomic::Ordering = atomic::Ordering::Relaxed;
+        }
+    }
+}
 
 /// A thread-safe cell which can be written to only once.
-pub struct OnceNonZeroUsize {
+pub struct OnceNonZeroUsize<O> {
     inner: AtomicUsize,
+    ordering: PhantomData<O>,
 }
 
-impl OnceNonZeroUsize {
+impl<O: Ordering> OnceNonZeroUsize<O> {
     /// Creates a new empty cell.
     #[inline]
     pub const fn new() -> Self {
         Self {
             inner: AtomicUsize::new(0),
+            ordering: PhantomData,
         }
     }
 
     /// Gets the underlying value.
     #[inline]
     pub fn get(&self) -> Option<NonZeroUsize> {
-        let val = self.inner.load(Ordering::Acquire);
+        let val = self.inner.load(O::ACQUIRE);
         NonZeroUsize::new(val)
     }
 
@@ -124,6 +156,6 @@ impl OnceNonZeroUsize {
     #[inline(always)]
     fn compare_exchange(&self, val: NonZeroUsize) -> Result<usize, usize> {
         self.inner
-            .compare_exchange(0, val.get(), Ordering::Release, Ordering::Acquire)
+            .compare_exchange(0, val.get(), O::RELEASE, O::ACQUIRE)
     }
 }