What is the purpose of pin PB4 in diagram v2_1c?

[Ludovic37-center]

Hi,
I am interested in the native version of the BMP.
When I look at the v2_1 c diagram and the BMP code, I don't understand what the PB4 pin is used for.
The PB5, PB6, and PB7 pins are used to read the hardware version (platform_hwversion_init function in native/platform.c).

In the .c and .h files of the native version, what is the purpose of pin PB4 ?
Thanks

[dragonmux]

It's nTRST for the JTAG interface - it has to be held high for the processor's own debug interface to work, thus the design left the pin unused but pulled high.

[Ludovic37-center]

ok, thanks

[Ludovic37-center]

Is it possible to disable JTAG in order to recover pin PB4 ?

Maybe in platform.c, line 328: gpio_primary_remap(AFIO_MAPR_SWJ_CFG_FULL_SWJ, AFIO_MAPR_TIM1_REMAP_PARTIAL_REMAP); ?

[dragonmux]

Yes, you could do that - it technically breaks compat with the existing hardware, but:

The TRM explicitly allows this, just be advised that while the bootloader's running and before the remapping register is poked, if you do not at least use a 10k to pull the pin high, you will be out of luck for debug.