|
| 1 | +#include "general.h" |
| 2 | +#include "target.h" |
| 3 | +#include "target_internal.h" |
| 4 | +#include "cortexm.h" |
| 5 | +#include "adiv5.h" |
| 6 | + |
| 7 | +/* Non-Volatile Memory Controller (NVMC) Registers */ |
| 8 | +#define NRF91_NVMC 0x50039000U |
| 9 | +#define NRF91_NVMC_READY (NRF91_NVMC + 0x400U) |
| 10 | +#define NRF91_NVMC_CONFIG (NRF91_NVMC + 0x504U) |
| 11 | +#define NRF91_NVMC_ERASEALL (NRF91_NVMC + 0x50cU) |
| 12 | + |
| 13 | +#define NRF91_NVMC_CONFIG_REN 0x0U // Read only access |
| 14 | +#define NRF91_NVMC_CONFIG_WEN 0x1U // Write enable |
| 15 | +#define NRF91_NVMC_CONFIG_EEN 0x2U // Erase enable |
| 16 | +#define NRF91_NVMC_CONFIG_PEEN 0x3U // Partial erase enable |
| 17 | + |
| 18 | +static bool nrf91_wait_ready(target_s *const t, platform_timeout_s *const timeout) |
| 19 | +{ |
| 20 | + /* Poll for NVMC_READY */ |
| 21 | + while (target_mem_read32(t, NRF91_NVMC_READY) == 0) { |
| 22 | + if (target_check_error(t)) |
| 23 | + return false; |
| 24 | + if (timeout) |
| 25 | + target_print_progress(timeout); |
| 26 | + } |
| 27 | + return true; |
| 28 | +} |
| 29 | + |
| 30 | +static bool nrf91_flash_erase(target_flash_s *f, target_addr_t addr, size_t len) |
| 31 | +{ |
| 32 | + target_s *t = f->t; |
| 33 | + |
| 34 | + /* Enable erase */ |
| 35 | + target_mem_write32(t, NRF91_NVMC_CONFIG, NRF91_NVMC_CONFIG_EEN); |
| 36 | + if (!nrf91_wait_ready(t, NULL)) |
| 37 | + return false; |
| 38 | + |
| 39 | + for (size_t offset = 0; offset < len; offset += f->blocksize) { |
| 40 | + /* Write all ones to first word in page to erase it */ |
| 41 | + target_mem_write32(t, addr + offset, 0xffffffffU); |
| 42 | + |
| 43 | + if (!nrf91_wait_ready(t, NULL)) |
| 44 | + return false; |
| 45 | + } |
| 46 | + |
| 47 | + /* Return to read-only */ |
| 48 | + target_mem_write32(t, NRF91_NVMC_CONFIG, NRF91_NVMC_CONFIG_REN); |
| 49 | + return nrf91_wait_ready(t, NULL); |
| 50 | +} |
| 51 | + |
| 52 | +static bool nrf91_flash_write(target_flash_s *f, target_addr_t dest, const void *src, size_t len) |
| 53 | +{ |
| 54 | + target_s *t = f->t; |
| 55 | + |
| 56 | + /* Enable write */ |
| 57 | + target_mem_write32(t, NRF91_NVMC_CONFIG, NRF91_NVMC_CONFIG_WEN); |
| 58 | + if (!nrf91_wait_ready(t, NULL)) |
| 59 | + return false; |
| 60 | + /* Write the data */ |
| 61 | + target_mem_write(t, dest, src, len); |
| 62 | + if (!nrf91_wait_ready(t, NULL)) |
| 63 | + return false; |
| 64 | + /* Return to read-only */ |
| 65 | + target_mem_write32(t, NRF91_NVMC_CONFIG, NRF91_NVMC_CONFIG_REN); |
| 66 | + return true; |
| 67 | +} |
| 68 | + |
| 69 | +static void nrf91_add_flash(target_s *t, uint32_t addr, size_t length, size_t erasesize) |
| 70 | +{ |
| 71 | + target_flash_s *f = calloc(1, sizeof(*f)); |
| 72 | + if (!f) { /* calloc failed: heap exhaustion */ |
| 73 | + DEBUG_WARN("calloc: failed in %s\n", __func__); |
| 74 | + return; |
| 75 | + } |
| 76 | + |
| 77 | + f->start = addr; |
| 78 | + f->length = length; |
| 79 | + f->blocksize = erasesize; |
| 80 | + f->erase = nrf91_flash_erase; |
| 81 | + f->write = nrf91_flash_write; |
| 82 | + f->erased = 0xff; |
| 83 | + target_add_flash(t, f); |
| 84 | +} |
| 85 | + |
| 86 | +bool nrf91_probe(target_s *t) { |
| 87 | + adiv5_access_port_s *ap = cortexm_ap(t); |
| 88 | + |
| 89 | + if (ap->dp->version < 2U) { |
| 90 | + return false; |
| 91 | + } |
| 92 | + |
| 93 | + switch (ap->dp->target_partno) { |
| 94 | + case 0x90: |
| 95 | + t->driver = "Nordic nRF9160"; |
| 96 | + t->target_options |= CORTEXM_TOPT_INHIBIT_NRST; |
| 97 | + target_add_ram(t, 0x20000000, 256U * 1024U); |
| 98 | + nrf91_add_flash(t, 0, 4096U * 256U, 4096U); |
| 99 | + break; |
| 100 | + default: |
| 101 | + return false; |
| 102 | + } |
| 103 | + |
| 104 | + return true; |
| 105 | +} |
0 commit comments