Skip to content

Commit 6365bdf

Browse files
hiddemollhiddemoll
committed
Start MU in parallel with CC
For now the MU still needs to know whether clock control is finished. To achieve this the MU has access to `callistoSwClockControlC` with a wishbone arbiter. The MU must not flood this bus, as clock control is more important. Place and route could not be completed. Since the MU does not care about extra delay with regards to accessing `calistoSwClockControlC` we can safely add a register on that path.
1 parent d288ec6 commit 6365bdf

11 files changed

Lines changed: 180 additions & 129 deletions

File tree

‎bittide-instances/src/Bittide/Instances/Hitl/SoftUgnDemo/Core.hs‎

Lines changed: 13 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -24,15 +24,15 @@ import Bittide.ProcessingElement (
2424
processingElement,
2525
)
2626
import Bittide.ScatterGather
27-
import Bittide.SharedTypes (Bytes, withBittideByteOrder)
27+
import Bittide.SharedTypes (Bytes)
2828
import Bittide.Sync (Sync)
2929
import Bittide.Wishbone (readDnaPortE2WbWorker, timeWb, uartBytes, uartInterfaceWb)
3030
import Clash.Class.BitPackC (ByteOrder)
3131
import Clash.Cores.Xilinx.Unisim.DnaPortE2 (readDnaPortE2, simDna2)
3232
import Protocols.Idle (idleSink)
3333
import Protocols.MemoryMap (Mm)
3434
import Protocols.Wishbone (Wishbone, WishboneMode (Standard))
35-
import Protocols.Wishbone.Extra (delayWishboneC)
35+
import Protocols.Wishbone.Extra (delayWishbone)
3636
import VexRiscv (DumpVcd (..), Jtag)
3737

3838
import qualified Bittide.Cpus.Riscv32imc as Riscv32imc
@@ -60,8 +60,9 @@ type PeripheralsPerLink = 4
6060

6161
{- External busses:
6262
- Transceivers
63+
- Callisto
6364
-}
64-
type NmuExternalBusses = 1 + (LinkCount * PeripheralsPerLink)
65+
type NmuExternalBusses = 2 + (LinkCount * PeripheralsPerLink)
6566
type NmuRemBusWidth = RemainingBusWidth (NmuExternalBusses + NmuInternalBusses)
6667

6768
muConfig ::
@@ -145,7 +146,11 @@ managementUnit maybeDna =
145146
idC -< (localCounter, uartOut, restBusses)
146147

147148
gppe ::
148-
(HiddenClockResetEnable dom, 1 <= DomainPeriod dom) =>
149+
( HiddenClockResetEnable dom
150+
, 1 <= DomainPeriod dom
151+
, ?busByteOrder :: ByteOrder
152+
, ?regByteOrder :: ByteOrder
153+
) =>
149154
-- | DNA value
150155
Signal dom (Maybe (BitVector 96)) ->
151156
Vec LinkCount (Signal dom (BitVector 64)) ->
@@ -157,7 +162,7 @@ gppe ::
157162
( Vec LinkCount (CSignal dom (BitVector 64))
158163
, Df dom (BitVector 8)
159164
)
160-
gppe maybeDna linksIn = withBittideByteOrder $ circuit $ \(mm, nmuWbMms, jtag) -> do
165+
gppe maybeDna linksIn = circuit $ \(mm, nmuWbMms, jtag) -> do
161166
-- Core and interconnect
162167
(scatterBusses, wbs0) <- Vec.split <| processingElement NoDumpVcd gppeConfig -< (mm, jtag)
163168
(gatherBusses, wbs1) <- Vec.split -< wbs0
@@ -166,7 +171,7 @@ gppe maybeDna linksIn = withBittideByteOrder $ circuit $ \(mm, nmuWbMms, jtag) -
166171
-- Synthesis fails on timing check unless these signals are registered. Remove as soon
167172
-- as possible.
168173
(nmuMms, nmuWbs) <- Vec.unzip -< nmuWbMms
169-
nmuWbsDelayed <- repeatC delayWishboneC -< nmuWbs
174+
nmuWbsDelayed <- repeatC delayWishbone -< nmuWbs
170175
nmuWbMmsDelayed <- Vec.zip -< (nmuMms, nmuWbsDelayed)
171176

172177
-- Scatter Gather units
@@ -230,7 +235,7 @@ core (refClk, refRst) (bitClk, bitRst, bitEna) rxClocks rxResets =
230235
withBittideClockResetEnable managementUnit maybeDna -< (muMm, muJtag)
231236
(ugnWbs, muWbs1) <- Vec.split -< muWbAll
232237
(ebWbs, muWbs2) <- Vec.split -< muWbs1
233-
(muSgWbs, [muTransceiverBus]) <- Vec.split -< muWbs2
238+
(muSgWbs, [muTransceiverBus, muCallistoBus]) <- Vec.split -< muWbs2
234239
-- Stop management unit
235240

236241
-- Start internal links
@@ -271,7 +276,7 @@ core (refClk, refRst) (bitClk, bitRst, bitEna) rxClocks rxResets =
271276
rxResets
272277
NoDumpVcd
273278
ccConfig
274-
-< (ccMm, (ccJtag, mask, linksSuitableForCc))
279+
-< (ccMm, muCallistoBus, (ccJtag, mask, linksSuitableForCc))
275280

276281
withBittideClockResetEnable
277282
(wbStorage "SampleMemory")

‎bittide-instances/src/Bittide/Instances/Hitl/SoftUgnDemo/Driver.hs‎

Lines changed: 1 addition & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -116,28 +116,13 @@ driver testName targets = do
116116
brackets picocomStarts (liftIO . snd) $ \(L.map fst -> picocoms) -> do
117117
let goDumpCcSamples = dumpCcSamples hitlDir (defCcConf (natToNum @FpgaCount)) ccGdbs
118118
liftIO $ mapConcurrently_ Gdb.continue ccGdbs
119-
liftIO
120-
$ T.tryWithTimeoutOn T.PrintActionTime "Waiting for stable links" 60_000_000 goDumpCcSamples
121-
$ forConcurrently_ picocoms
122-
$ \pico ->
123-
waitForLine pico.stdoutHandle "[CC] All links stable"
124-
125119
liftIO $ mapConcurrently_ Gdb.continue muGdbs
126-
liftIO
127-
$ T.tryWithTimeoutOn
128-
T.PrintActionTime
129-
"Wait for elastic buffers to be centered"
130-
60_000_000
131-
goDumpCcSamples
132-
$ forConcurrently_ picocoms
133-
$ \pico ->
134-
waitForLine pico.stdoutHandle "[MU] All elastic buffers centered"
135120

136121
liftIO
137122
$ T.tryWithTimeoutOn
138123
T.PrintActionTime
139124
"Waiting for captured UGNs"
140-
(3 * 60_000_000)
125+
60_000_000
141126
goDumpCcSamples
142127
$ forConcurrently_ picocoms
143128
$ \pico ->

‎bittide-instances/src/Bittide/Instances/Hitl/SwitchDemo/Core.hs‎

Lines changed: 10 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -60,8 +60,9 @@ type PeripheralsPerLink = 2
6060
- ASIC PE
6161
- Switch calendar
6262
- Transceivers
63+
- Callisto
6364
-}
64-
type NmuExternalBusses = 3 + (LinkCount * PeripheralsPerLink)
65+
type NmuExternalBusses = 4 + (LinkCount * PeripheralsPerLink)
6566
type NmuRemBusWidth = RemainingBusWidth (NmuExternalBusses + NmuInternalBusses)
6667

6768
managementUnit ::
@@ -194,13 +195,13 @@ core (refClk, refRst) (bitClk, bitRst, bitEna) rxClocks rxResets =
194195
(Fwd lc, muUartBytesBittide, muWbAll) <-
195196
withBittideClockResetEnable managementUnit maybeDna -< (muMm, muJtag)
196197
(ugnWbs, muWbs1) <- Vec.split -< muWbAll
197-
( ebWbs
198-
, [ (peWbMM, peWb)
199-
, (switchWbMM, switchWb)
200-
, muTransceiverBus
201-
]
202-
) <-
203-
Vec.split -< muWbs1
198+
(ebWbs, muWbs2) <- Vec.split -< muWbs1
199+
[ (peWbMM, peWb)
200+
, (switchWbMM, switchWb)
201+
, muTransceiverBus
202+
, muCallistoBus
203+
] <-
204+
idC -< muWbs2
204205
-- Stop management unit
205206

206207
-- Start internal links
@@ -248,7 +249,7 @@ core (refClk, refRst) (bitClk, bitRst, bitEna) rxClocks rxResets =
248249
rxResets
249250
NoDumpVcd
250251
ccConfig
251-
-< (ccMm, (ccJtag, mask, linksSuitableForCc))
252+
-< (ccMm, muCallistoBus, (ccJtag, mask, linksSuitableForCc))
252253

253254
withBittideClockResetEnable
254255
(wbStorage "SampleMemory")

‎bittide-instances/src/Bittide/Instances/Hitl/SwitchDemo/Driver.hs‎

Lines changed: 1 addition & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -496,28 +496,13 @@ driver testName targets = do
496496

497497
let goDumpCcSamples = dumpCcSamples hitlDir (defCcConf (natToNum @FpgaCount)) ccGdbs
498498
liftIO $ mapConcurrently_ Gdb.continue ccGdbs
499-
liftIO
500-
$ T.tryWithTimeoutOn T.PrintActionTime "Waiting for stable links" 60_000_000 goDumpCcSamples
501-
$ forConcurrently_ picocoms
502-
$ \pico ->
503-
waitForLine pico.stdoutHandle "[CC] All links stable"
504-
505499
liftIO $ mapConcurrently_ Gdb.continue muGdbs
506-
liftIO
507-
$ T.tryWithTimeoutOn
508-
T.PrintActionTime
509-
"Wait for elastic buffers to be centered"
510-
60_000_000
511-
goDumpCcSamples
512-
$ forConcurrently_ picocoms
513-
$ \pico ->
514-
waitForLine pico.stdoutHandle "[MU] All elastic buffers centered"
515500

516501
liftIO
517502
$ T.tryWithTimeoutOn
518503
T.PrintActionTime
519504
"Waiting for captured UGNs"
520-
(3 * 60_000_000)
505+
60_000_000
521506
goDumpCcSamples
522507
$ forConcurrently_ picocoms
523508
$ \pico ->

‎bittide-instances/src/Bittide/Instances/Hitl/SwitchDemoGppe/Core.hs‎

Lines changed: 18 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -24,15 +24,15 @@ import Bittide.ProcessingElement (
2424
processingElement,
2525
)
2626
import Bittide.ScatterGather
27-
import Bittide.SharedTypes (Bytes, withBittideByteOrder)
27+
import Bittide.SharedTypes (Bytes)
2828
import Bittide.Switch (switchC)
2929
import Bittide.Sync (Sync)
3030
import Bittide.Wishbone (readDnaPortE2WbWorker, timeWb, uartBytes, uartInterfaceWb)
3131
import Clash.Class.BitPackC (ByteOrder)
3232
import Clash.Cores.Xilinx.Unisim.DnaPortE2 (readDnaPortE2, simDna2)
3333
import Protocols.MemoryMap (Mm)
3434
import Protocols.Wishbone (Wishbone, WishboneMode (Standard))
35-
import Protocols.Wishbone.Extra (delayWishboneC)
35+
import Protocols.Wishbone.Extra (delayWishbone)
3636
import VexRiscv (DumpVcd (..), Jtag)
3737

3838
import qualified Bittide.Cpus.Riscv32imc as Riscv32imc
@@ -61,8 +61,9 @@ type PeripheralsPerLink = 2
6161
- Gather calendar
6262
- Switch calendar
6363
- Transceivers
64+
- Callisto
6465
-}
65-
type NmuExternalBusses = 4 + (LinkCount * PeripheralsPerLink)
66+
type NmuExternalBusses = 5 + (LinkCount * PeripheralsPerLink)
6667
type NmuRemBusWidth = RemainingBusWidth (NmuExternalBusses + NmuInternalBusses)
6768

6869
muConfig ::
@@ -146,7 +147,11 @@ managementUnit maybeDna =
146147
idC -< (localCounter, uartOut, restBusses)
147148

148149
gppe ::
149-
(HiddenClockResetEnable dom, 1 <= DomainPeriod dom) =>
150+
( HiddenClockResetEnable dom
151+
, 1 <= DomainPeriod dom
152+
, ?busByteOrder :: ByteOrder
153+
, ?regByteOrder :: ByteOrder
154+
) =>
150155
-- | DNA value
151156
Signal dom (Maybe (BitVector 96)) ->
152157
Signal dom (BitVector 64) ->
@@ -158,15 +163,15 @@ gppe ::
158163
( CSignal dom (BitVector 64)
159164
, Df dom (BitVector 8)
160165
)
161-
gppe maybeDna linkIn = withBittideByteOrder $ circuit $ \(mm, nmuWbMms, jtag) -> do
166+
gppe maybeDna linkIn = circuit $ \(mm, nmuWbMms, jtag) -> do
162167
-- Core and interconnect
163168
[scatterBus, gatherBus, timeBus, uartBus, dnaBus] <-
164169
processingElement NoDumpVcd gppeConfig -< (mm, jtag)
165170

166171
-- Synthesis fails on timing check unless these signals are registered. Remove as soon
167172
-- as possible.
168173
(nmuMms, nmuWbs) <- Vec.unzip -< nmuWbMms
169-
nmuWbsDelayed <- repeatC delayWishboneC -< nmuWbs
174+
nmuWbsDelayed <- repeatC delayWishbone -< nmuWbs
170175
[scatterCalendarBus, gatherCalendarBus] <- Vec.zip -< (nmuMms, nmuWbsDelayed)
171176

172177
-- Scatter Gather units
@@ -256,7 +261,12 @@ core (refClk, refRst) (bitClk, bitRst, bitEna) rxClocks rxResets =
256261
withBittideClockResetEnable (managementUnit maybeDna) -< (muMM, muJtag)
257262
(ugnWbs, muWbs1) <- Vec.split -< muWbAll
258263
(ebWbs, muWbs2) <- Vec.split -< muWbs1
259-
(muSgWbs, [(switchWbMM, switchWb), muTransceiverBus]) <- Vec.split -< muWbs2
264+
(muSgWbs, muWbs3) <- Vec.split -< muWbs2
265+
[ (switchWbMM, switchWb)
266+
, muTransceiverBus
267+
, muCallistoBus
268+
] <-
269+
idC -< muWbs3
260270
-- Stop management unit
261271

262272
-- Start internal links
@@ -301,7 +311,7 @@ core (refClk, refRst) (bitClk, bitRst, bitEna) rxClocks rxResets =
301311
rxResets
302312
NoDumpVcd
303313
ccConfig
304-
-< (ccMM, (ccJtag, mask, linksSuitableForCc))
314+
-< (ccMM, muCallistoBus, (ccJtag, mask, linksSuitableForCc))
305315

306316
withBittideClockResetEnable
307317
(wbStorage "SampleMemory")

‎bittide-instances/src/Bittide/Instances/Hitl/SwitchDemoGppe/Driver.hs‎

Lines changed: 1 addition & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -117,28 +117,13 @@ driver testName targets = do
117117
brackets picocomStarts (liftIO . snd) $ \(L.map fst -> picocoms) -> do
118118
let goDumpCcSamples = dumpCcSamples hitlDir (defCcConf (natToNum @FpgaCount)) ccGdbs
119119
liftIO $ mapConcurrently_ Gdb.continue ccGdbs
120-
liftIO
121-
$ T.tryWithTimeoutOn T.PrintActionTime "Waiting for stable links" 60_000_000 goDumpCcSamples
122-
$ forConcurrently_ picocoms
123-
$ \pico ->
124-
waitForLine pico.stdoutHandle "[CC] All links stable"
125-
126120
liftIO $ mapConcurrently_ Gdb.continue muGdbs
127-
liftIO
128-
$ T.tryWithTimeoutOn
129-
T.PrintActionTime
130-
"Wait for elastic buffers to be centered"
131-
60_000_000
132-
goDumpCcSamples
133-
$ forConcurrently_ picocoms
134-
$ \pico ->
135-
waitForLine pico.stdoutHandle "[MU] All elastic buffers centered"
136121

137122
liftIO
138123
$ T.tryWithTimeoutOn
139124
T.PrintActionTime
140125
"Waiting for captured UGNs"
141-
(3 * 60_000_000)
126+
60_000_000
142127
goDumpCcSamples
143128
$ forConcurrently_ picocoms
144129
$ \pico ->

‎bittide/src/Bittide/ClockControl/CallistoSw.hs‎

Lines changed: 21 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -25,8 +25,9 @@ import Bittide.Counter (domainDiffCountersWbC)
2525
import Bittide.ProcessingElement
2626
import Bittide.SharedTypes
2727
import Bittide.Sync (Sync, syncInCounterC, syncOutGenerateWbC, toSync)
28-
import Bittide.Wishbone (timeWb)
28+
import Bittide.Wishbone (arbiterMm, extendAddressWidthWbMm, timeWb)
2929
import Protocols.MemoryMap
30+
import Protocols.Wishbone.Extra (delayWishboneMm)
3031

3132
import qualified Protocols.Vec as Vec
3233

@@ -45,10 +46,11 @@ type SwcccRemBusWidth n = 30 - PrefixWidth (n + SwcccInternalBusses)
4546
-- TODO: Make this the primary Callisto function once the reset logic is fixed
4647
-- and Callisto is detached from the ILA plotting mechanisms.
4748
callistoSwClockControlC ::
48-
forall nLinks dom free rx otherWb.
49+
forall nLinks dom free rx otherWb otherWbMu.
4950
( HiddenClockResetEnable dom
5051
, KnownNat nLinks
5152
, KnownNat otherWb
53+
, KnownNat otherWbMu
5254
, HasSynchronousReset dom
5355
, HasSynchronousReset free
5456
, HasSynchronousReset rx
@@ -71,6 +73,10 @@ callistoSwClockControlC ::
7173
PeConfig (otherWb + SwcccInternalBusses) ->
7274
Circuit
7375
( ToConstBwd Mm
76+
, -- Management unit
77+
( ToConstBwd Mm
78+
, Wishbone dom 'Standard otherWbMu (Bytes 4)
79+
)
7480
, ( Jtag dom
7581
, CSignal dom (BitVector nLinks) -- link mask
7682
, CSignal dom (BitVector nLinks) -- what links are suitable for clock control
@@ -85,9 +91,9 @@ callistoSwClockControlC ::
8591
)
8692
)
8793
callistoSwClockControlC freeClk freeRst rxClocks rxResets dumpVcd peConfig =
88-
circuit $ \(mm, (jtag, Fwd linkMask, Fwd linksOk)) -> do
94+
circuit $ \(mm, muClockControlBus, (jtag, Fwd linkMask, Fwd linksOk)) -> do
8995
allWishbone <- processingElement dumpVcd peConfig -< (mm, jtag)
90-
( [ clockControlBus
96+
( [ ccClockControlBus
9197
, timeWbBus
9298
, freezeBus
9399
, syncOutGeneratorBus
@@ -100,6 +106,17 @@ callistoSwClockControlC freeClk freeRst rxClocks rxResets dumpVcd peConfig =
100106
Fwd clockControlData <-
101107
clockControlWb linkMask linksOk (unbundle diffCounters) -< clockControlBus
102108

109+
clockControlBus <- arbiterMm -< [ccClockControlBusWide, muClockControlBusWide]
110+
-- We need to extend the width of both wishbone busses since we don't know which
111+
-- is wider.
112+
ccClockControlBusWide <-
113+
extendAddressWidthWbMm @(Max (SwcccRemBusWidth otherWb) otherWbMu)
114+
-< ccClockControlBus
115+
muClockControlBusWide <-
116+
extendAddressWidthWbMm @(Max (SwcccRemBusWidth otherWb) otherWbMu)
117+
<| delayWishboneMm
118+
-< muClockControlBus
119+
103120
freeze hasClock hasReset
104121
-< ( freezeBus
105122
, Fwd diffCounters

0 commit comments

Comments
 (0)