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.}}{\*\pnseclvl2\pnucltr\pnstart1\pnindent720\pnhang{\pntxta .}}{\*\pnseclvl3\pndec\pnstart1\pnindent720\pnhang{\pntxta .}}{\*\pnseclvl4\pnlcltr\pnstart1\pnindent720\pnhang{\pntxta )}}{\*\pnseclvl5 +\pndec\pnstart1\pnindent720\pnhang{\pntxtb (}{\pntxta )}}{\*\pnseclvl6\pnlcltr\pnstart1\pnindent720\pnhang{\pntxtb (}{\pntxta )}}{\*\pnseclvl7\pnlcrm\pnstart1\pnindent720\pnhang{\pntxtb (}{\pntxta )}}{\*\pnseclvl8\pnlcltr\pnstart1\pnindent720\pnhang +{\pntxtb (}{\pntxta )}}{\*\pnseclvl9\pnlcrm\pnstart1\pnindent720\pnhang{\pntxtb (}{\pntxta )}}\pard\plain \s19\qc\li74\ri17\sb6000\nowidctlpar\tx2835\adjustright \b\f1\fs40\lang2057 {SECTION 2}{ }{BBC Microcomputer Model B+ +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {\page }{\b BBC Microcomputer Model B+ Service Manual +\par }{Contents +\par }\pard\plain \s20\qj\sa240\nowidctlpar\tqr\tx9639\adjustright \f2\fs22\lang2057 {1 \endash Introduction\tab 1 +\par }\pard\plain \qj\sa240\nowidctlpar\tqr\tx9639\adjustright \f2\fs22\lang2057 {2 \endash Packaging and installation\tab 2 +\par }\pard \qj\nowidctlpar\tqr\tx9639\adjustright {3 \endash Specification\tab 3 +\par 3.1 The microcomputer\tab 3 +\par 3.2 Power supply\tab 5 +\par 3.3 Video outputs\tab 5 +\par 3.4 RS423\tab 5 +\par 3.5 Cassette interface\tab 6 +\par 3.6 Analogue to digital convertor\tab 6 +\par 3.7 ECONET\tab 6 +\par 3.8 CENTRONICS compatible printer interface\tab 6 +\par 3.9 Audio output\tab 6 +\par 3.10 Environnent\tab 7 +\par }\pard \qj\sa240\nowidctlpar\tqr\tx9639\adjustright {3.11 Dimensions\tab 7 +\par 4 \endash Disassembly and assembly\tab 8 +\par }\pard \qj\nowidctlpar\tqr\tx9639\adjustright {5 \endash Circuit description\tab 10 +\par 5.1 General\tab 10 +\par 5.2 CPU timing\tab 11 +\par 5.3 Reset circuitry\tab 13 +\par 5.4 Address decoding and memory\tab 13 +\par 5.4.1 ROM operation\tab 15 +\par 5.4.2 Paged RAM operation\tab 16 +\par 5.4.3 RAM. access\tab 16 +\par 5.4.4 RAM circuitry\tab 18 +\par 5.5 Disc interface\tab 19 +\par 5.5.1 8271 FDC\tab 19 +\par 5.5.2 1770 FDC\tab 21 +\par 5.6 Video circuitry\tab 21 +\par 5.6.1 RGB\tab 21 +\par 5.6.2 Composite video\tab 21 +\par 5.6.3 UHF\tab 22 +\par 5.7 CENTRONICS compatible printer interface}{\tab }{23 +\par 5.8 User port\tab 23 +\par 5.9 1MHz extension bus\tab 23 +\par 5.10 TUBE interface\tab 23 +\par 5.11 ECONET\tab 24 +\par 5.12 Cassette and RS423 ports\tab 24 +\par 5.13 Analogue to digital convertor\tab 25 +\par 5.14 Audio circuitry\tab 25 +\par }\pard \qj\sa240\nowidctlpar\tqr\tx9639\adjustright {5.15 Keyboard\tab 26 +\par }\pard \qj\nowidctlpar\tqr\tx9639\adjustright {6 \endash Upgrading the PCB\tab 27 +\par 6.1 1770 disc option\tab 27 +\par 6.2 8271 disc option\tab 28 +\par 6.3 ECONET\tab 30 +\par }\pard \qj\sa240\nowidctlpar\tqr\tx9639\adjustright {6.4 Speech\tab 31 +\par 7 - Selection links}{\tab }{33 +\par \page 8 \endash Test equipment\tab 35 +\par }\pard \qj\nowidctlpar\tqr\tx9639\adjustright {9 \endash Fault finding\tab 36 +\par 9.1 Switch on\tab 36 +\par 9.2 Power supply\tab 39 +\par 9.3 Oscillator and divider circuitry\tab 40 +\par 9.4 CPU\tab 40 +\par 9.5 ROM\tab 41 +\par 9.6 DRAMs\tab 42 +\par 9.7 Video\tab 42 +\par 9.8 Cassette interface and RS423\tab 45 +\par 9.9 Keyboard\tab 47 +\par 9.10 Disc interface\tab 48 +\par 9.11 Printer port\tab 51 +\par 9.12 User port\tab 52 +\par 9.13 1MHz extension bus\tab 53 +\par 9.14 TUBE interface\tab 54 +\par 9.15 Analogue to digital conversion}{\tab }{55 +\par }\pard \qj\sa240\nowidctlpar\tqr\tx9639\adjustright {9.16 ECONET\tab 56 +\par Appendix\tab 57 +\par }\pard \qj\nowidctlpar\tqr\tx9639\adjustright {Connector pinouts\tab 58 +\par Parts list\tab 63 +\par Glossary\tab 69 +\par IC description\tab 71 +\par Final assembly\tab 89 +\par Circuit block diagram\tab 91 +\par PCB circuit diagram\tab 93 +\par PCB layout\tab 95 +\par Keyboard circuit diagram\tab 97 +\par Power supply circuit diagram\tab 9}{\lang1033 9 +\par }\pard \qj\sa240\nowidctlpar\tx2835\adjustright {\lang1033 \page }{\fs24 WARNING: THE COMPUTER MUST BE EARTHED +\par }\pard \qj\ri115\sa240\nowidctlpar\tx2835\adjustright {IMPORTANT: The wires in the mains lead for the apparatus are coloured in accordance with the following code: +\par }\pard \qj\ri113\nowidctlpar\tx2835\adjustright {\tab \tab Green & Yellow\tab Earth +\par \tab \tab Blue\tab \tab \tab Neutral +\par }\pard \qj\ri115\sa240\nowidctlpar\tx2835\adjustright {\tab \tab Brown\tab \tab Live +\par }\pard \qj\sa240\nowidctlpar\tx2835\adjustright { +The moulded plug must be used with the fuse and fuse carrier firmly in place. The fuse carrier is of the same basic colour (though not necessarily the same shade of that colour) as the coloured insert in the base of the plu +g. Different manufacturers' plugs and fuse carriers are not interchangeable. In the event of loss of the fuse carrier, the moulded plug MUST NOT be used. Either replace the moulded plug with another conventional plug wired as detailed below, or obtain a r +eplacement fuse carrier from an authorised ACORN dealer. In the event of the fuse blowing it should be replaced, after clearing any faults, with a 3 amp fuse that is ASTA approved to BS1362. +\par }\pard \qj\ri115\sa240\nowidctlpar\tx2835\adjustright {If the socket outlet available is not suitable for the plug suppl +ied, the plug should be cut off and the appropriate plug fitted and wired as previously noted. The moulded plug which was cut off must be disposed of as it would be a potential shock hazard if it were to be plugged in with the cut off end of the mains cor +d exposed. +\par +\par As the colours of the wires may not correspond with the coloured markings identifying the terminals in your plug, proceed as follows: +\par The wire which is coloured green and yellow must be connected to the terminal in the plug which is marked by the letter E, or by the safety earth symbol }{{\field{\*\fldinst SYMBOL 94 \\f "Symbol" \\s 11}{\fldrslt\f3\fs22}}}{ + , or coloured either green or green and yellow. +\par The wire which is coloured blue must be connected to the terminal which is marked with the letter N, or coloured black. +\par The wire which is coloured brown must be connected to the terminal which is marked with the letter L, or coloured red. +\par }\pard\plain \s1\qj\sa240\nowidctlpar\tx2835\outlinelevel0\adjustright \b\f2 {\sect }\sectd \psz9\pgnrestart\linex0\headery289\footery431\colsx709\pgbrdropt32\sectdefaultcl {\footerl \pard\plain \s22\qj\sa240\nowidctlpar +\tx2835\tqc\tx4153\tqr\tx8306\adjustright \f2\fs22\lang2057 {\field{\*\fldinst {\cs21 PAGE }}{\fldrslt {\cs21\lang1024 12}}}{ +\par }}{\footerr \pard\plain \qr\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {\field{\*\fldinst {\cs21 PAGE }}{\fldrslt {\cs21\lang1024 11}}}{ +\par }}\pard\plain \s1\qj\sa240\nowidctlpar\tx2835\outlinelevel0\adjustright \b\f2 {1 Introduction +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {This manual is intended to provide the information required to diagnose and repair faults on the BBC Microcomputer Mo +del B+ which was designed by ACORN Computers Ltd of Cambridge, England. +\par The information contained in this manual is aimed at service engineers and ACORN dealers who will be servicing the BBC Microcomputer on behalf of ACORN Computers Ltd.}{\fs24 +\par }\pard\plain \s1\qj\sa240\nowidctlpar\tx2835\outlinelevel0\adjustright \b\f2 {\lang2057 \page 2 Packaging and installation +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 { +The microcomputer is supplied in a two-part moulded polystyrene packing in a cardboard box. Supplied with the microcomputer is a User Guide, an introductory cassette package, a UHF TV lead, and a guarantee registration card. Disc and Econet ve +rsions also contain a Disc Filing System User Guide and an Econet User Guide respectively. +\par The mains supply for UK models is 240V AC 50Hz. The microcomputer is supplied with a moulded l3 amp square pin plug. If this plug is unsuitable then it must be cut o +ff and thrown away. Instructions for fitting a replacement plug are given right at the front of this manual. +\par The microcomputer is turned on by a switch at the back of the microcomputer next to the mains lead. +\par Do not use the microcomputer in conditions of e +xtreme heat, cold, humidity or dust or in places subject to vibration. Do not block ventilation under or behind the computer. Ensure that no foreign objects are inserted through any openings in the microcomputer. +\par }{\fs24 +\par }\pard\plain \s1\qj\sa240\nowidctlpar\tx2835\outlinelevel0\adjustright \b\f2 {\lang2057 \page 3 Specification +\par }\pard\plain \s2\sa240\keepn\nowidctlpar\tx2835\outlinelevel1\adjustright \b\f2\lang2057 {3.1 The microcomputer +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {The microcomputer is contained in a rigid injection moulded thermoplastic case, and provides the following facilities. +\par 73 key full travel QWERTY keyboard including 10 user-definable function keys. Keyboard has two key rollover and auto repeat. +\par Fully encased internal power supply manufactured to BS 4l5 Class 1. +\par Internal loudspeaker driven from a 4-channel sound synthesis circuit with ADSR envelope control. +\par A colour television signal, for connection to a normal domestic television aerial socket, is available through a phono connector. This signal is 625 line, 50Hz, interlaced, encoded PAL A and is modulated on UHF channel 36. +\par A BNC connector supplies a composite video output to drive a black and white or PAL colour monitor. +\par 6-pin DIN connector provides separate RGB and sync outputs at TTL levels. RGB are all high true, and sync is link selectable as high or low true, pulse duration 4.0 microseconds. +\par A standard audio cassette recorder can be used to record computer programs and data at 300 or 1200 baud using the Co +mputer Users' Tape Standard tones. The cassette recorder is under automatic motor control and is connected to the computer via a 7-pin DIN connector. +\par An interrupt driven elapsed time clock (user settable). +\par 6512A processor running at 2MHz. +\par 64K of read/write Random Access Memory (RAM), allowing a shadow screen mode, and 12K paged RAM in any mode. +\par 32K Read Only Memory (ROM) integrated circuit containing the Machine Operating System and a fast BASIC interpreter. The interpreter includes a 6502/6512 assembler wh +ich enables BASIC statements to be freely mixed with 6502/6512 assembly language. Code generated using the BASIC assembler can be run on a machine with a 6512 microprocessor, or a machine with a 6502 microprocessor. +\par Up to five 32K sideways ROMs may be plug +ged into the machine at any time, having the effect of ten l6K ROM slots (eleven including BASIC). These ten 16K ROM slots are paged and may include Pascal, word processing, computer aided design software, disc and ECONET and WINCHESTER filing systems or +TELETEXT acquisition software. +\par The full-colour Teletext display of 40 characters by 25 lines, known as mode 7 has character rounding, with double height, flashing, coloured background and text plus pixel graphics \endash all to the Teletext standard. +\par The non-Teletext display modes (modes 0 to 6) provide user-definable characters in addition to the standard upper and lower case alpha-numeric font. In these modes, graphics may be mixed freely with text. +\par \page The following screen modes are available: +\par }\pard \qj\nowidctlpar\tx2835\adjustright {Mode 0: 640 x 256 2-colour graphics and 80 x 32 text (20K) +\par Mode 1: 320 x 256 4-colour graphics and 40 x 32 text (20K) +\par Mode 2: 160 x 256 16-colour graphics and 20 x 32 text (20K) +\par Mode 3: 80 x 25 2-colour text only (16K) +\par Mode 4: 320 x 256 2-colour graphics and 40 x 32 text (10K) +\par Mode 5: 160 x 256 4-colour graphics and 20 x 32 text (10K) +\par Mode 6: 40 x 25 2-colour text only (8K) +\par Mode 7: 40 x 25 Teletext display (1K) +\par Mode 128: 640 x 256 2-colour graphics and 80 x 32 text (20K) +\par Mode 129: 320 x 256 4-colour graphics and 40 x 32 text (20K) +\par Mode 130: 160 x 256 16-colour graphics and 20 x 32 text (20K) +\par Mode 131: 80 x 25 2-colour text only (16K) +\par Mode 132: 320 x 256 2-colour graphics and 40 x 32 text (10K) +\par Mode 133: 160 x 256 4-colour graphics and 20 x 32 text (10K) +\par Mode 134: 40 x 25 2-colour text only (8K) +\par }\pard \qj\sa240\nowidctlpar\tx2835\adjustright {Mode 135: 40 x 25 Teletext display (1K) +\par All graphics access is transparent. +\par Shadow mode gives 32K BASIC program RAM (less workspace) to the user in any screen mode. +\par The shadow +screen mode offers equivalent display sizes to the standard mode 0 to 7 screens, but using an auxiliary memory area, the "shadow" RAM. In shadow display modes (modes 128 to l35) BASIC or a user program is free to use all memory between OSHWM (PAGE) and &7 +FFF, plus the 12K bytes of sideways (paged) RAM. +\par The 12K paged RAM is available to the user in any screen mode, shadow or non-shadow. +\par Serial interface to RS423 standard. The new standard has been designed to be inter-operable with RS232C equipment. Baud rates are software selectable between 75 baud and 19200 baud (guaranteed up to 9600 baud). +\par An 8-bit input/output port with 2 control bits. +\par Four analogue input channels. Each channel has an input voltage range of 0V to 1.8V. The conversion time for each channel is 10 milliseconds. The resolution of the ADC chip is 10 bits. +\par 1 MHz buffered extension bus for connection to a variety of external hardware such as a TELETEXT acquisition unit, IEEE 488 interface, WINCHESTER disc drive etc. +\par Buffered interface for connection via the TUBE to a range of second processors. +\par CENTRONICS compatible printer interface. +\par The basic model B+ may have added to it a floppy disc interface using either an 8271 or 1770 controller IC. +\par Also, a low cost network interface, the Acorn ECONET, may be added. +\par Finally, a speech upgrade is available using the 5220 speech IC to generate predefined words and sounds through the built-in speaker. +\par }\pard\plain \s2\sa240\keepn\nowidctlpar\tx2835\outlinelevel1\adjustright \b\f2\lang2057 {\page 3.2 Power supply +\par }\pard\plain \qj\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {Input voltage\tab 240V AC RMS +/-10% +\par Input frequency \tab 47-53Hz +\par }\pard\plain \s20\qj\nowidctlpar\tx1080\tx2835\adjustright \f2\fs22\lang2057 { +\par +5V output voltage\tab +5V DC +/-0.1V +\par }\pard\plain \qj\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {+5V output current\tab 0.1A minimum +\par }\pard \qj\li2835\sa240\nowidctlpar\tx2835\adjustright {3.5A maximum +\par }\pard \qj\nowidctlpar\tx2835\adjustright {+12V output voltage\tab +12V DC +/-10% +\par }\pard \qj\sa240\nowidctlpar\tx2835\adjustright {+12V output current\tab 1.25A maximum +\par }\pard \qj\nowidctlpar\tx2835\adjustright {-5V output voltage\tab -5V DC +/-10% +\par -5V output current\tab 0.1A maximum +\par +\par }\pard \qj\sa240\nowidctlpar\tx2835\adjustright {Total output power \tab 35W +\par }\pard\plain \s2\sa240\keepn\nowidctlpar\tx2835\outlinelevel1\adjustright \b\f2\lang2057 {3.3 Display outputs +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {\b Modulated output (marked UHF out) +\par }\pard \qj\nowidctlpar\tx2835\adjustright {Standard\tab 625-line PAL A UHF colour television signal +\par Channel\tab E36 +\par Vision carrier\tab Nominal 591.25MHz +\par RF output\tab 1.0 to 2.5mV +\par 6db bandwidth\tab >= 8MHz +\par RF output impedance\tab 75 ohms +\par }\pard\plain \s20\qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {Connector\tab phono +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {\b Composite video (marked video out) +\par }\pard \qj\nowidctlpar\tx2835\adjustright {Output level\tab Nominal 1V peak to peak +\par Output impedance \tab Nominal 75 ohms +\par }\pard \fi-2835\li2835\nowidctlpar\tx2835\adjustright {Option\tab Chrominance information (link selectable) allows composite PAL monitors to be used +\par }\pard\plain \s20\qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {Connector\tab BNC +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {\b Colour monitor (marked RGB) +\par }\pard \qj\nowidctlpar\tx2835\adjustright {RGB signals\tab TTL type levels +\par CSYNC signal\tab TTL type level +ve/-ve going (link selectable) +\par }\pard\plain \s20\qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {Connector\tab 6-pin DIN +\par }\pard\plain \s2\sa240\keepn\nowidctlpar\tx2835\outlinelevel1\adjustright \b\f2\lang2057 {3.4 RS423 +\par }\pard\plain \qj\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {Line length\tab 1200m maximum +\par Input impedance \tab > 4k ohms +\par Baud rate\tab 19200 maximum +\par \tab (guaranteed up to 9600)}{\fs24 +\par }\pard\plain \s2\sa240\keepn\nowidctlpar\tx2835\outlinelevel1\adjustright \b\f2\lang2057 {\page 3.5 Cassette interface +\par }\pard\plain \qj\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {Output impedance \tab Less than 1k ohms +\par Input impedance \tab Greater than 100k ohms +\par Output level\tab Nominal 200mV peak to peak, 70mV RMS +\par Dynamic input range \tab Nominal 50mV to 5V peak to peak, -25 to +15dB +\par \tab 0db = 350mv RMS +\par Motor control\tab By miniature relay within computer +\par \tab Contact rating 1A at 24V DC +\par Baud rate\tab 300 or 1200 baud using standard CUTS tones +\par \tab (1200 and 2400 Hz tones) +\par }\pard \qj\sa240\nowidctlpar\tx2835\adjustright {Connector\tab 7-pin DIN +\par }\pard\plain \s2\sa240\keepn\nowidctlpar\tx2835\outlinelevel1\adjustright \b\f2\lang2057 {3.6 Analogue to digital converter +\par }\pard\plain \qj\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {Resolution\tab 10 bit +\par Full scale +\par input voltage\tab VREF +\par VREF\tab l. 8V typica1 +\par Accuracy (with +\par respect to VREF) +\par full scale error \tab 0.5% typical +\par zero scale error \tab 0.5% typical +\par Non-linearity\tab 0.1% typical +\par Temp coefficient \tab -6mV/degree C typical +\par Conversion speed \tab 10.0ms per channel typical +\par }\pard \qj\sa240\nowidctlpar\tx2835\adjustright {Input impedance \tab > 1M ohms +\par }\pard\plain \s2\sa240\keepn\nowidctlpar\tx2835\outlinelevel1\adjustright \b\f2\lang2057 {3.7 ECONET +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {Line voltages\tab 0.25V and 3V typical into 50 ohms +\par }\pard\plain \s2\sa240\keepn\nowidctlpar\tx2835\outlinelevel1\adjustright \b\f2\lang2057 {3.8 CENTRONICS compatible printer interface +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {Data strobe\tab \tab 4\'b5s pulse +\par }\pard\plain \s2\sa240\keepn\nowidctlpar\tx2835\outlinelevel1\adjustright \b\f2\lang2057 {3.9 Audio output +\par }\pard\plain \qj\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {Output power\tab 0.5W +\par Speaker impedance\tab 8 ohms +\par }\pard\plain \s2\sa240\keepn\nowidctlpar\tx2835\outlinelevel1\adjustright \b\f2\lang2057 {\page 3.10 Environment +\par }\pard\plain \qj\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {Air temperature +\par }\pard\plain \s20\qj\fi-1134\li1134\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {\tab system on \tab 0 to 35 degrees C +\par }\pard\plain \qj\fi-1134\li1134\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {\tab system off \tab -20 to 70 degrees C +\par }\pard\plain \s20\qj\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {Humidity +\par }\pard \s20\qj\li1134\nowidctlpar\tx1080\tx2835\adjustright {system on \tab 85% relative humidity at 35 degrees C +\par }\pard \s20\qj\li1134\sa240\nowidctlpar\tx1080\tx2835\adjustright {system off \tab 95% relative humidity at 35 degrees C +\par }\pard\plain \qj\nowidctlpar\tqr\tx2430\tx2835\adjustright \f2\fs22\lang2057 {Storage conditions +\par }\pard\plain \s20\qj\nowidctlpar\tqr\tx2430\tx2835\adjustright \f2\fs22\lang2057 {\tab air temperature\tab -20 to 70 degrees C +\par }\pard \s20\qj\sa240\nowidctlpar\tqr\tx2430\tx2835\adjustright {\tab humidity\tab 95% relative humidity at 55 degrees C +\par }\pard\plain \s2\sa240\keepn\nowidctlpar\tx2835\outlinelevel1\adjustright \b\f2\lang2057 {3.11 Dimensions +\par }\pard\plain \qj\nowidctlpar\tx1080\tx2835\adjustright \f2\fs22\lang2057 {Height\tab 73mm (including feet) +\par }\pard\plain \s20\qj\nowidctlpar\tx1080\tx2835\adjustright \f2\fs22\lang2057 {Width\tab 415mm +\par }\pard\plain \qj\sa240\nowidctlpar\tx1080\tx2835\adjustright \f2\fs22\lang2057 {Depth\tab 345mm +\par }\pard\plain \s1\qj\sa240\nowidctlpar\tx2835\outlinelevel0\adjustright \b\f2 {\lang2057 \page 4 Disassembly and assembly +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {To service the BBC Microcomputer B Plus, first disconnect the power supply plug from the mains and remove all peripheral connections from the computer. +\par To disassemble +\par The lid of the microcomputer case may be removed after undoing four fixing screws, two on + the rear panel and two underneath. Take care not to lose the two spire clips pushed onto the case lid, into which the rear fixing screws locate. DO NOT remove the lid with the mains power connected. +\par }\pard \qj\nowidctlpar\tx2835\adjustright {Inside the microcomputer are three main sub-assemblies: +\par }\pard \qj\sa240\nowidctlpar\tx2835\adjustright {The power supply unit, keyboard and the main printed circuit board. +\par To remove the keyboard, undo the two screws and nuts holding it to the case bottom, taking care to note the positions of the associated washers. Unplug the 17-way keyboard connector and th +e 2-way loudspeaker connector from the main printed circuit board, and the 10-way serial-ROM connector, if fitted. +\par The power supply unit is connected to the main circuit board by seven push-on connectors which may be unplugged. Three screws on the undersid +e of the case are undone allowing the unit to be removed. On reassembly, ensure that the same type of screw is used (M3x6mm). +\par The main printed circuit board can be removed after the two wires to SK2 (composite video BNC socket) have been disconnected. Undo the seven fixing screws and remove the circuit board from the case by sliding it forwards and then lifting it from the rear. + +\par To reassemble +\par Replace the main printed circuit board by putting the front edge (with connector headers) in first and pulling it fo +rwards as far as possible until the back edge drops in. Be careful not to trap the composite video wire to the BNC connector if this was removed. Replace the PCB fixing screws. +\par Reconnect the composite video and its connector. +\par Reconnect the power supply, being careful to route the wires neatly, and connect the wires (seven) to the push-on connectors on the PCB, being very careful to get the polarity right. +\par PCB connectors marked VCC must have a red wire attached (three). +\par PCB connectors marked 0V must have a black wire attached (three). +\par The connector marked -5V has the purple wire attached (one). +\par Replace the keyboard and reconnect the loudspeaker to the main PCB. Be careful to reconnect the keyboard ribbon socket so that all the pins are engaged; it is easy to +displace the connector one pin to right or left. Replace the 10-way serial-ROM connector if fitted. Replace the nuts and bolts holding the keyboard in place. +\par \page Make one final check that all reconnections have been made correctly, especially the power supplies which will short circuit if two are reversed. +\par Replace the lid and press down at the rear whilst tightening the two rear fixing screws. Finally replace the front two fixing screws. +\par }\pard\plain \s1\qj\sa240\nowidctlpar\tx2835\outlinelevel0\adjustright \b\f2 {\lang2057 \page 5 Circuit description +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 { +This circuit description has been kept as simple as possible as the detailed fault finding section (section 9) should prove to be of more use for servicing. A detailed description is given of those features of the BBC Microcomputer B+ which are new. + +\par }\pard\plain \s2\sa240\keepn\nowidctlpar\tx2835\outlinelevel1\adjustright \b\f2\lang2057 {5.1 General +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 { +The microcomputer uses the 6512 CPU (IC42) which allows more accurate timing of the logic circuitry than did the 6502, see 5.2. The 6512 requires two clock signals at 'MOS' voltage levels, in all other respects it functions in the same way as the 6502. + +\par The computer clocks are derived from a 16MHz crystal controlled oscillator circuit (X1 and half of IC26), and divider circuitry in the video processor ULA (IC53). +\par The 6512 accesses 31 1/4Kbytes of ROM, 3/4Kbyte of memory mapped input/output, and up to 44Kbytes of RAM. 64Kbytes of RAM are installed on the PCB, the extra 20Kbytes being used for the screen memory in shadow mode, see 3.1. +\par The memory mapped I/O is located in pages &FC, &FD, and &FE of the CPU address space. +\par There are five sideways ROM sockets + installed on the PCB, each capable of taking an 8, 16, or 32Kbyte ROM or EPROM (ICs 35 44 57 62 68). When used with a 32K ROM, each sideways ROM socket is decoded as two 16K sideways ROM slots. A sixth ROM socket IC71 holds a 32Kbyte ROM which contains t +he operating system and BASIC. The number of the ROM currently in use is held in the ROM select latch (IC45). +\par 64Kbytes of RAM are installed on the board in eight 64K by 1 bit DRAM chips, (ICs 55 56 60 61 64 65 66 67). Of this RAM, 32Kbytes are always access +ible to the CPU, 12Kbytes can be paged into the sideways (paged) ROM space, and the remaining 20Kbytes are used as screen memory in shadow mode. Both CPU (IC42) and 6845 cathode ray tube controller (IC78) have access to the RAM. Each can access the RAM at + full 2MHz clock speed by, interleaving the accesses on alternate phases of the 2MHz clock. The RAM is thus being accessed at 4MHz. The 6845 accessed the RAM sufficiently to perform the refresh function. +\par Screen display is provided through the 6845 (IC78), video processor (IC53), and various encoding circuits. Three display outputs are available: +\par RGB consists of CSYNC and RED GREEN BLUE at TTL voltage levels. Each colour is either on, off, or flashing, giving sixteen displayable colour effects, i.e. eight static colours and eight flashing colours. +\par VIDEO output is a summation of RGB to give a grey scale (luminance only). If link S26 is made the chrominance component (colour information) is added to the VIDEO output. +\par UHF output is obtained by mixing luminance, chrominance and SYNC signals, and then feeding the result to a UHF modulator. +\par \page Serial input/output is provided by the cassette port and RS423 port. Both are controlled by the 6850 asynchronous communications interface adapter (IC82) and a ULA called the serial processor (IC85). +\par Analogue input is fed to the four-channel 10 bit ADC chip (IC84). +\par A local area network facility is provided by the ECONET circuitry, centered on the 68B54 advanced data-link controller (IC81). +\par Two build options are available for the f +loppy disc circuitry. One is based on the 8271 floppy disc controller (IC15) as used on all BBC Microcomputers issues 1 to 7. The second option is based on the 1770 floppy disc controller (IC16). Same components are common to both options. The 1770 operat +e +s in either single density (FM) or double density (MFM) mode, and includes a data separator and disc speed decision logic. The 1770 controller interface is therefore simpler than the 8271 controller interface. ICs 1, 2, 3, 4, and 9 are not required with a + 1770. +\par The CENTRONICS compatible printer interface is based on half (the A port) of a 6522 versatile interface adapter (IC10). IC5 buffers data sent to the printer. +\par The User Port is connected directly to the B port of the same 6522 (IC10). +\par The 1MHz extension bus is a fully buffered interface to the CPU, operating with 1\'b5s transfer cycles. The bus appears as a 512 byte address block in the processor I/O space at pages &FC and &FD. +\par The TUBE interface provides buffered address and data lines for connection to a second processor. The TUBE itself is a fast parallel bidirectional FIFO and is resident in the 2nd processor unit. +\par The keyboard is read through half (the A port) of a 6522 versatile interface adapter (IC20). +\par Sound is produced by the 76489 (IC38), a four-channel sound generator chip. +\par Speech may be generated using an optional 5220 speech processor (IC29) and 6100 word PHROM (IC37). +\par }\pard\plain \s2\sa240\keepn\nowidctlpar\tx2835\outlinelevel1\adjustright \b\f2\lang2057 {5.2 CPU timing +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {A 16MHz crystal controlled oscillator (X1 and half of IC26) generates clock pulses which are divided by circuitry + within the video processor ULA (IC53). Pins 4, 5, 6, and 7 of the video processor provide 1MHz, 2MHz, 4MHz, and 8MHz outputs respectively. 8MHz, 4MHz and 2MHz are used to generate RAS and CAS for the DRAMs, and 6MHz for the TELETEXT chip IC59. 2MHz is us +ed to generate the main system clock, 2E. 1MHz is used directly by the TELETEXT chip, and also in conjunction with 2MHz to generate the phase shifted 1MHz system clock, 1E from IC25. +\par \page The CPU is normally clocked at 2MHz. The 6512 (IC42) requires a two phase non-overlapping clock on inputs phi1 (pin 3) and phi2 (pin 37), see figure 1. +\par }{\fs24 +\par }{\lang1024\cgrid {\shpgrp{\*\shpinst\shpleft1152\shptop33\shpright9117\shpbottom5588\shpfhdr0\shpbxcolumn\shpbypara\shpwr3\shpwrk0\shpfblwtxt0\shpz11\shplid1026{\sp{\sn groupLeft}{\sv 2304}}{\sp{\sn groupTop}{\sv 3168}}{\sp{\sn groupRight}{\sv 10269}} +{\sp{\sn groupBottom}{\sv 8723}}{\sp{\sn fFlipH}{\sv 0}}{\sp{\sn fFlipV}{\sv 0}}{\sp{\sn lidRegroup}{\sv 0}}{\shpgrp{\*\shpinst\shplid1027{\sp{\sn groupLeft}{\sv 2178}} +{\sp{\sn groupTop}{\sv 2880}}{\sp{\sn groupRight}{\sv 9954}}{\sp{\sn groupBottom}{\sv 4038}}{\sp{\sn relLeft}{\sv 2493}}{\sp{\sn relTop}{\sv 5403}}{\sp{\sn relRight}{\sv 10269}} +{\sp{\sn relBottom}{\sv 6561}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn lidRegroup}{\sv 0}}{\shp{\*\shpinst\shplid1028{\sp{\sn relLeft}{\sv 2178}}{\sp{\sn relTop}{\sv 4032}}{\sp{\sn relRight}{\sv 3042}}{\sp{\sn relBottom}{\sv 4032}} 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relLeft}{\sv 6624}}{\sp{\sn relTop}{\sv 2880}} +{\sp{\sn relRight}{\sv 6912}}{\sp{\sn relBottom}{\sv 4032}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 1}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}}} +{\shp{\*\shpinst\shplid1044{\sp{\sn relLeft}{\sv 6912}}{\sp{\sn relTop}{\sv 2880}}{\sp{\sn relRight}{\sv 8352}}{\sp{\sn relBottom}{\sv 2880}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}} +{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}}}{\shp{\*\shpinst\shplid1045{\sp{\sn relLeft}{\sv 8352}}{\sp{\sn relTop}{\sv 2880}}{\sp{\sn relRight}{\sv 8640}}{\sp{\sn relBottom}{\sv 4032}}{\sp{\sn fRelFlipH}{\sv 0}} +{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}}}{\shp{\*\shpinst\shplid1046{\sp{\sn relLeft}{\sv 8640}}{\sp{\sn relTop}{\sv 4032}} +{\sp{\sn relRight}{\sv 9954}}{\sp{\sn relBottom}{\sv 4038}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 1}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}}}}} +{\shpgrp{\*\shpinst\shplid1047{\sp{\sn groupLeft}{\sv 2178}}{\sp{\sn groupTop}{\sv 6202}}{\sp{\sn groupRight}{\sv 9954}}{\sp{\sn groupBottom}{\sv 7360}}{\sp{\sn relLeft}{\sv 2304}} +{\sp{\sn relTop}{\sv 7560}}{\sp{\sn relRight}{\sv 10080}}{\sp{\sn relBottom}{\sv 8718}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn lidRegroup}{\sv 0}}{\shp{\*\shpinst\shplid1048 +{\sp{\sn relLeft}{\sv 2178}}{\sp{\sn relTop}{\sv 6202}}{\sp{\sn relRight}{\sv 3168}}{\sp{\sn relBottom}{\sv 6208}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}} +{\sp{\sn fFilled}{\sv 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geoRight}{\sv 965}}{\sp{\sn geoBottom}{\sv 3540}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn pVerticies}{\sv 8;10;(635,0);(675,175);(965,665);(875,1020);(785,1375);(190,1710);(95,2130);(0,2550);(261,3246);(305,3540)}} +{\sp{\sn pSegmentInfo}{\sv 2;9;16384;44288;8193;44288;8193;44288;8193;44032;32768}}{\sp{\sn fFillOK}{\sv 1}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}{\sp{\sn lidRegroup}{\sv 0}}}} +{\shp{\*\shpinst\shplid1058{\sp{\sn relLeft}{\sv 3159}}{\sp{\sn relTop}{\sv 7310}}{\sp{\sn relRight}{\sv 3303}}{\sp{\sn relBottom}{\sv 7598}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}} +{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn lineEndArrowhead}{\sv 1}}{\sp{\sn fArrowheadsOK}{\sv 1}}}}{\shp{\*\shpinst\shplid1059{\sp{\sn relLeft}{\sv 3366}}{\sp{\sn relTop}{\sv 3651}} +{\sp{\sn relRight}{\sv 3510}}{\sp{\sn relBottom}{\sv 3795}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 3}}}}{\shp{\*\shpinst\shplid1060{\sp{\sn relLeft}{\sv 3387}}{\sp{\sn relTop}{\sv 6570}} +{\sp{\sn relRight}{\sv 3531}}{\sp{\sn relBottom}{\sv 6858}}{\sp{\sn fRelFlipH}{\sv 1}}{\sp{\sn fRelFlipV}{\sv 1}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn lineEndArrowhead}{\sv 1}} +{\sp{\sn fArrowheadsOK}{\sv 1}}}}{\shp{\*\shpinst\shplid1061{\sp{\sn relLeft}{\sv 3540}}{\sp{\sn relTop}{\sv 6855}}{\sp{\sn relRight}{\sv 3693}}{\sp{\sn relBottom}{\sv 8064}}{\sp{\sn fRelFlipH}{\sv 0}} +{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 0}}{\sp{\sn rotation}{\sv 0}}{\sp{\sn geoRight}{\sv 153}}{\sp{\sn geoBottom}{\sv 1209}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn pVerticies}{\sv 8;7;(21,1209);(42,1098);(153,741);(150,540) +;(147,339);(31,112);(0,0)}}{\sp{\sn pSegmentInfo}{\sv 2;7;16384;44288;8193;44288;8193;44032;32768}}{\sp{\sn fFillOK}{\sv 1}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}{\sp{\sn lidRegroup}{\sv 0}}}} +{\shp{\*\shpinst\shplid1062{\sp{\sn relLeft}{\sv 4953}}{\sp{\sn relTop}{\sv 5187}}{\sp{\sn relRight}{\sv 5097}}{\sp{\sn relBottom}{\sv 5475}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}} +{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn lineEndArrowhead}{\sv 1}}{\sp{\sn fArrowheadsOK}{\sv 1}}}}{\shp{\*\shpinst\shplid1063{\sp{\sn relLeft}{\sv 4887}}{\sp{\sn relTop}{\sv 8435}} +{\sp{\sn relRight}{\sv 5031}}{\sp{\sn relBottom}{\sv 8723}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn lineEndArrowhead}{\sv 1}} +{\sp{\sn fArrowheadsOK}{\sv 1}}}}{\shp{\*\shpinst\shplid1064{\sp{\sn relLeft}{\sv 4788}}{\sp{\sn relTop}{\sv 3735}}{\sp{\sn relRight}{\sv 5070}}{\sp{\sn relBottom}{\sv 5175}}{\sp{\sn fRelFlipH}{\sv 0}} +{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 0}}{\sp{\sn rotation}{\sv 0}}{\sp{\sn geoRight}{\sv 282}}{\sp{\sn geoBottom}{\sv 1440}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn pVerticies}{\sv 8;7;(282,0);(237,122);(32,495);(12,735);(0,964) +;(134,1309);(162,1440)}}{\sp{\sn pSegmentInfo}{\sv 2;7;16384;44288;8193;45824;8193;44032;32768}}{\sp{\sn fFillOK}{\sv 1}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}{\sp{\sn lidRegroup}{\sv 0}}}} +{\shp{\*\shpinst\shplid1065{\sp{\sn relLeft}{\sv 4662}}{\sp{\sn relTop}{\sv 5970}}{\sp{\sn relRight}{\sv 5175}}{\sp{\sn relBottom}{\sv 8430}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 0}}{\sp{\sn rotation}{\sv 0}} +{\sp{\sn geoRight}{\sv 513}}{\sp{\sn geoBottom}{\sv 2460}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn pVerticies}{\sv 8;7;(513,0);(436,182);(96,685);(48,1095);(0,1505);(191,2176);(228,2460)}}{\sp{\sn pSegmentInfo}{\sv 2;7;16384 +;44288;8193;44288;8193;44032;32768}}{\sp{\sn fFillOK}{\sv 1}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}{\sp{\sn lidRegroup}{\sv 0}}}}{\shp{\*\shpinst\shplid1066{\sp{\sn relLeft}{\sv 5091}}{\sp{\sn relTop}{\sv 3651}} +{\sp{\sn relRight}{\sv 5235}}{\sp{\sn relBottom}{\sv 3795}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 3}}}}{\shp{\*\shpinst\shplid1067{\sp{\sn relLeft}{\sv 3366}}{\sp{\sn relTop}{\sv 8046}} +{\sp{\sn relRight}{\sv 3510}}{\sp{\sn relBottom}{\sv 8190}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 3}}}}{\shp{\*\shpinst\shplid1068{\sp{\sn relLeft}{\sv 5151}}{\sp{\sn relTop}{\sv 5871}} +{\sp{\sn relRight}{\sv 5295}}{\sp{\sn relBottom}{\sv 6015}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 3}}}}}{\shprslt{\*\do\dobxcolumn\dobypara\dodhgt8203\dppolygon\dppolycount4\dpptx0\dppty0\dpptx7965\dppty0 +\dpptx7965\dppty5555\dpptx0\dppty5555\dpx1152\dpy33\dpxsize7965\dpysize5555\dpfillfgcr255\dpfillfgcg255\dpfillfgcb255\dpfillbgcr255\dpfillbgcg255\dpfillbgcb255\dpfillpat1\dplinew15\dplinecor0\dplinecog0\dplinecob0}}}}{\f1\fs32 2M +\par }{\fs32 +\par +\par }\pard \qj\ri8640\sa240\nowidctlpar\tx2835\adjustright {\b\fs40 +\par }\pard \qj\sa240\nowidctlpar\tx2835\adjustright {\f1\fs32 \'d81 +\par }\pard \qj\ri8640\sa240\nowidctlpar\tx2835\adjustright {\b\fs40 +\par +\par }\pard \qj\sa240\nowidctlpar\tx2835\adjustright {\f1\fs32 \'d82 +\par }{ +\par +\par Figure 1 Non-overlapping clock inputs phi1 and phi2 +\par Phi1 and phi2 are generated by IC33, two gates of which are used to build an R-S latch. Not2M from +IC26 is used to set and reset the R-S latch which toggles at 2MHz unless a third gate from IC33 blocks the not2M signal. During 2MHz operation the phi2 clock corresponds to not2M, the inverse of 2M from the video processor. +\par When accessing slow devices (1MH +z extension bus, ADC, VIAs, 6845, ACIA, and serial processor) the clock is stretched to give a pseudo 1MHz cycle. The system 1MHz clock, 1E, is generated in half of IC25 from the 1MHz and 2MHz outputs of the video processor. The other half of IC 25 is use +d + to synchronise the transition from 2MHz to 1MHz clocking. Each 1 MHz peripheral select line is connected to an input of NAND gate IC41. If any input of this NAND gate is taken to logic 0 then a 1MHz CPU cycle will occur. For 1MHz cycles phi2 is held at l +ogic 1 until the 1E signal is synchronised. The cycle ends with both phi2 and 1E falling together. +\par \page There are two ways in which the transition from 2MHz to 1MHz takes place depending on which phase 1E was on when the request was received from IC41, see figure 2. +\par }{\fs24 +\par }{\lang1024\cgrid {\shpgrp{\*\shpinst\shpleft864\shptop293\shpright9072\shpbottom1013\shpfhdr0\shpbxcolumn\shpbypara\shpwr3\shpwrk0\shpfblwtxt0\shpz14\shplid1069{\sp{\sn groupLeft}{\sv 2016}}{\sp{\sn groupTop}{\sv 2952}}{\sp{\sn groupRight}{\sv 10224}} +{\sp{\sn groupBottom}{\sv 3672}}{\sp{\sn fFlipH}{\sv 0}}{\sp{\sn fFlipV}{\sv 0}}{\sp{\sn lidRegroup}{\sv 0}}{\shpgrp{\*\shpinst\shplid1070{\sp{\sn groupLeft}{\sv 2016}} +{\sp{\sn groupTop}{\sv 2952}}{\sp{\sn groupRight}{\sv 3888}}{\sp{\sn groupBottom}{\sv 3672}}{\sp{\sn relLeft}{\sv 2016}}{\sp{\sn relTop}{\sv 2952}}{\sp{\sn relRight}{\sv 3888}} +{\sp{\sn relBottom}{\sv 3672}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn lidRegroup}{\sv 0}}{\shp{\*\shpinst\shplid1071{\sp{\sn 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+{\shp{\*\shpinst\shplid1120{\sp{\sn relLeft}{\sv 6623}}{\sp{\sn relTop}{\sv 5972}}{\sp{\sn relRight}{\sv 8495}}{\sp{\sn relBottom}{\sv 5972}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}} +{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}{\sp{\sn lidRegroup}{\sv 1}}}}{\shp{\*\shpinst\shplid1121{\sp{\sn relLeft}{\sv 8495}}{\sp{\sn relTop}{\sv 5972}} +{\sp{\sn relRight}{\sv 8639}}{\sp{\sn relBottom}{\sv 6692}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}} +{\sp{\sn lidRegroup}{\sv 1}}}}{\shp{\*\shpinst\shplid1122{\sp{\sn relLeft}{\sv 8639}}{\sp{\sn relTop}{\sv 6692}}{\sp{\sn relRight}{\sv 10223}}{\sp{\sn relBottom}{\sv 6692}}{\sp{\sn fRelFlipH}{\sv 0}} +{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}{\sp{\sn lidRegroup}{\sv 1}}}}}{\shprslt{\*\do\dobxcolumn\dobypara\dodhgt8204 +\dppolygon\dppolycount4\dpptx0\dppty0\dpptx8208\dppty0\dpptx8208\dppty722\dpptx0\dppty722\dpx864\dpy341\dpxsize8208\dpysize722 +\dpfillfgcr255\dpfillfgcg255\dpfillfgcb255\dpfillbgcr255\dpfillbgcg255\dpfillbgcb255\dpfillpat1\dplinew15\dplinecor0\dplinecog0\dplinecob0}}}}{\b\fs30 +\par }{\f1\fs32 1E +\par }{\b\fs30 +\par }{\lang1024\cgrid {\shpgrp{\*\shpinst\shpleft904\shptop290\shpright9112\shpbottom1010\shpfhdr0\shpbxcolumn\shpbypara\shpwr3\shpwrk0\shpfblwtxt0\shpz0\shplid1123{\sp{\sn groupLeft}{\sv 2016}}{\sp{\sn groupTop}{\sv 7344}}{\sp{\sn groupRight}{\sv 10224}} +{\sp{\sn groupBottom}{\sv 8064}}{\sp{\sn fFlipH}{\sv 0}}{\sp{\sn fFlipV}{\sv 0}}{\sp{\sn lidRegroup}{\sv 0}}{\shp{\*\shpinst\shplid1124{\sp{\sn relLeft}{\sv 2016}}{\sp{\sn relTop}{\sv 8064}}{\sp{\sn relRight}{\sv 5616}}{\sp{\sn relBottom}{\sv 8064}} +{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}}} +{\shp{\*\shpinst\shplid1125{\sp{\sn relLeft}{\sv 3312}}{\sp{\sn relTop}{\sv 7344}}{\sp{\sn relRight}{\sv 9648}}{\sp{\sn relBottom}{\sv 7344}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}} +{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}}}{\shp{\*\shpinst\shplid1126{\sp{\sn relLeft}{\sv 9216}}{\sp{\sn relTop}{\sv 8064}}{\sp{\sn relRight}{\sv 10224}}{\sp{\sn relBottom}{\sv 8064}}{\sp{\sn fRelFlipH}{\sv 0}} +{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}}}{\shp{\*\shpinst\shplid1127{\sp{\sn relLeft}{\sv 9072}}{\sp{\sn relTop}{\sv 7344}} +{\sp{\sn relRight}{\sv 9216}}{\sp{\sn relBottom}{\sv 8064}}{\sp{\sn fRelFlipH}{\sv 1}}{\sp{\sn fRelFlipV}{\sv 1}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}}} +{\shp{\*\shpinst\shplid1128{\sp{\sn relLeft}{\sv 9648}}{\sp{\sn relTop}{\sv 7344}}{\sp{\sn relRight}{\sv 9792}}{\sp{\sn relBottom}{\sv 8064}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}} +{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}}}{\shp{\*\shpinst\shplid1129{\sp{\sn relLeft}{\sv 3168}}{\sp{\sn relTop}{\sv 7344}}{\sp{\sn relRight}{\sv 3312}}{\sp{\sn relBottom}{\sv 8064}}{\sp{\sn fRelFlipH}{\sv 1}} +{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}}}{\shp{\*\shpinst\shplid1130{\sp{\sn relLeft}{\sv 5616}}{\sp{\sn relTop}{\sv 7344}} +{\sp{\sn relRight}{\sv 5760}}{\sp{\sn relBottom}{\sv 8064}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 1}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}}} +{\shp{\*\shpinst\shplid1131{\sp{\sn relLeft}{\sv 3312}}{\sp{\sn relTop}{\sv 7344}}{\sp{\sn relRight}{\sv 3456}}{\sp{\sn relBottom}{\sv 8064}}{\sp{\sn fRelFlipH}{\sv 1}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}} +{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}}}{\shp{\*\shpinst\shplid1132{\sp{\sn relLeft}{\sv 3456}}{\sp{\sn relTop}{\sv 7344}}{\sp{\sn relRight}{\sv 3600}}{\sp{\sn relBottom}{\sv 8064}}{\sp{\sn fRelFlipH}{\sv 1}} +{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}}}{\shp{\*\shpinst\shplid1133{\sp{\sn relLeft}{\sv 5472}}{\sp{\sn relTop}{\sv 7344}} +{\sp{\sn relRight}{\sv 5616}}{\sp{\sn relBottom}{\sv 8064}}{\sp{\sn fRelFlipH}{\sv 1}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}}} +{\shp{\*\shpinst\shplid1134{\sp{\sn relLeft}{\sv 5328}}{\sp{\sn relTop}{\sv 7344}}{\sp{\sn relRight}{\sv 5472}}{\sp{\sn relBottom}{\sv 8064}}{\sp{\sn fRelFlipH}{\sv 1}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}} +{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}}}{\shp{\*\shpinst\shplid1135{\sp{\sn relLeft}{\sv 9216}}{\sp{\sn relTop}{\sv 7344}}{\sp{\sn relRight}{\sv 9360}}{\sp{\sn relBottom}{\sv 8064}}{\sp{\sn fRelFlipH}{\sv 0}} +{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}}}{\shp{\*\shpinst\shplid1136{\sp{\sn relLeft}{\sv 9360}}{\sp{\sn relTop}{\sv 7344}} +{\sp{\sn relRight}{\sv 9504}}{\sp{\sn relBottom}{\sv 8064}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}}} +{\shp{\*\shpinst\shplid1137{\sp{\sn relLeft}{\sv 9504}}{\sp{\sn relTop}{\sv 7344}}{\sp{\sn relRight}{\sv 9648}}{\sp{\sn relBottom}{\sv 8064}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}} +{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}}}{\shp{\*\shpinst\shplid1138{\sp{\sn relLeft}{\sv 3600}}{\sp{\sn relTop}{\sv 7344}}{\sp{\sn relRight}{\sv 3744}}{\sp{\sn relBottom}{\sv 8064}}{\sp{\sn fRelFlipH}{\sv 1}} +{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}}}{\shp{\*\shpinst\shplid1139{\sp{\sn relLeft}{\sv 5184}}{\sp{\sn relTop}{\sv 7344}} +{\sp{\sn relRight}{\sv 5328}}{\sp{\sn relBottom}{\sv 8064}}{\sp{\sn fRelFlipH}{\sv 1}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}}} +}{\shprslt{\*\do\dobxcolumn\dobypara\dodhgt8192\dppolygon\dppolycount4\dpptx0\dppty0\dpptx8208\dppty0\dpptx8208\dppty720\dpptx0\dppty720\dpx904\dpy290\dpxsize8208\dpysize720 +\dpfillfgcr255\dpfillfgcg255\dpfillfgcb255\dpfillbgcr255\dpfillbgcg255\dpfillbgcb255\dpfillpat1\dplinew15\dplinecor0\dplinecog0\dplinecob0}}}}{\b\fs18 +\par }{\f1\fs32 sync 1M +\par }{\fs30 +\par }{\lang1024\cgrid {\shpgrp{\*\shpinst\shpleft864\shptop298\shpright9072\shpbottom1018\shpfhdr0\shpbxcolumn\shpbypara\shpwr3\shpwrk0\shpfblwtxt0\shpz15\shplid1140{\sp{\sn groupLeft}{\sv 2016}}{\sp{\sn groupTop}{\sv 8856}}{\sp{\sn groupRight}{\sv 10224}} +{\sp{\sn groupBottom}{\sv 9576}}{\sp{\sn fFlipH}{\sv 0}}{\sp{\sn fFlipV}{\sv 0}}{\sp{\sn lidRegroup}{\sv 0}}{\shpgrp{\*\shpinst\shplid1141{\sp{\sn groupLeft}{\sv 2016}} +{\sp{\sn groupTop}{\sv 2952}}{\sp{\sn groupRight}{\sv 3888}}{\sp{\sn groupBottom}{\sv 3672}}{\sp{\sn relLeft}{\sv 2016}}{\sp{\sn relTop}{\sv 8856}}{\sp{\sn relRight}{\sv 3888}} +{\sp{\sn relBottom}{\sv 9576}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 1}}{\sp{\sn rotation}{\sv 0}}{\sp{\sn lidRegroup}{\sv 0}}{\shp{\*\shpinst\shplid1142{\sp{\sn relLeft}{\sv 2016}}{\sp{\sn relTop}{\sv 3672}}{\sp{\sn relRight}{\sv 2736}} +{\sp{\sn relBottom}{\sv 3672}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}}} +{\shp{\*\shpinst\shplid1143{\sp{\sn relLeft}{\sv 2736}}{\sp{\sn relTop}{\sv 2952}}{\sp{\sn relRight}{\sv 2880}}{\sp{\sn relBottom}{\sv 3672}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 1}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}} +{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}}}{\shp{\*\shpinst\shplid1144{\sp{\sn relLeft}{\sv 2880}}{\sp{\sn relTop}{\sv 2952}}{\sp{\sn relRight}{\sv 3744}}{\sp{\sn relBottom}{\sv 2952}}{\sp{\sn fRelFlipH}{\sv 0}} +{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}}}{\shp{\*\shpinst\shplid1145{\sp{\sn relLeft}{\sv 3744}}{\sp{\sn relTop}{\sv 2952}} +{\sp{\sn relRight}{\sv 3888}}{\sp{\sn relBottom}{\sv 3672}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}}}}} +{\shp{\*\shpinst\shplid1146{\sp{\sn relLeft}{\sv 3888}}{\sp{\sn relTop}{\sv 8856}}{\sp{\sn relRight}{\sv 8352}}{\sp{\sn relBottom}{\sv 8856}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 1}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}} +{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}}}{\shpgrp{\*\shpinst\shplid1147{\sp{\sn groupLeft}{\sv 4608}}{\sp{\sn groupTop}{\sv 8856}} +{\sp{\sn groupRight}{\sv 5760}}{\sp{\sn groupBottom}{\sv 9576}}{\sp{\sn relLeft}{\sv 4608}}{\sp{\sn relTop}{\sv 8856}}{\sp{\sn relRight}{\sv 5760}}{\sp{\sn relBottom}{\sv 9576}} +{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn lidRegroup}{\sv 0}}{\shp{\*\shpinst\shplid1148{\sp{\sn relLeft}{\sv 4608}}{\sp{\sn relTop}{\sv 8856}}{\sp{\sn relRight}{\sv 4752}} +{\sp{\sn relBottom}{\sv 9576}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn lineDashing}{\sv 7}}{\sp{\sn fArrowheadsOK}{\sv 1}} +{\sp{\sn fLine}{\sv 1}}}}{\shp{\*\shpinst\shplid1149{\sp{\sn relLeft}{\sv 4752}}{\sp{\sn relTop}{\sv 9576}}{\sp{\sn relRight}{\sv 5616}}{\sp{\sn relBottom}{\sv 9576}}{\sp{\sn fRelFlipH}{\sv 0}} +{\sp{\sn fRelFlipV}{\sv 1}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn lineDashing}{\sv 7}}{\sp{\sn fArrowheadsOK}{\sv 1}}{\sp{\sn fLine}{\sv 1}}}} +{\shp{\*\shpinst\shplid1150{\sp{\sn relLeft}{\sv 5616}}{\sp{\sn relTop}{\sv 8856}}{\sp{\sn relRight}{\sv 5760}}{\sp{\sn relBottom}{\sv 9576}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 1}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}} +{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn lineDashing}{\sv 7}}{\sp{\sn fArrowheadsOK}{\sv 1}}{\sp{\sn fLine}{\sv 1}}}}}}{\shp{\*\shpinst\shplid1151{\sp{\sn relLeft}{\sv 8352}}{\sp{\sn relTop}{\sv 8856}} +{\sp{\sn relRight}{\sv 8496}}{\sp{\sn relBottom}{\sv 9576}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}}} +{\shp{\*\shpinst\shplid1152{\sp{\sn relLeft}{\sv 8496}}{\sp{\sn relTop}{\sv 9576}}{\sp{\sn relRight}{\sv 9360}}{\sp{\sn relBottom}{\sv 9576}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 1}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}} +{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}}}{\shp{\*\shpinst\shplid1153{\sp{\sn relLeft}{\sv 9360}}{\sp{\sn relTop}{\sv 8856}}{\sp{\sn relRight}{\sv 9504}}{\sp{\sn relBottom}{\sv 9576}}{\sp{\sn fRelFlipH}{\sv 0}} +{\sp{\sn fRelFlipV}{\sv 1}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}}}{\shp{\*\shpinst\shplid1154{\sp{\sn relLeft}{\sv 9504}}{\sp{\sn relTop}{\sv 8856}} +{\sp{\sn relRight}{\sv 10224}}{\sp{\sn relBottom}{\sv 8856}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 1}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}}} +}{\shprslt{\*\do\dobxcolumn\dobypara\dodhgt8207\dppolygon\dppolycount4\dpptx0\dppty0\dpptx8208\dppty0\dpptx8208\dppty720\dpptx0\dppty720\dpx864\dpy298\dpxsize8208\dpysize720 +\dpfillfgcr255\dpfillfgcg255\dpfillfgcb255\dpfillbgcr255\dpfillbgcg255\dpfillbgcb255\dpfillpat1\dplinew15\dplinecor0\dplinecog0\dplinecob0}}}}{ +\par }{\f1\fs32 \'d82 +\par }{ +\par Figure 2 2MHz to 1MHz transition +\par }\pard\plain \s2\sa240\keepn\nowidctlpar\tx2835\outlinelevel1\adjustright \b\f2\lang2057 {5.3 Reset circuitry +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {The system has two reset circuits, one is a general reset from a 555 timer (IC43), the other is an RC network which just resets the system VIA (IC20) on power-up. + This allows the software to detect the difference between a power-on reset and a BREAK key reset. The keyboard BREAK key connects via S10 (a PCB made link) to the 555 timer. The 555 generates reset pulse RS which is inverted to give the CPU notRS signal. + +\par }\pard\plain \s2\sa240\keepn\nowidctlpar\tx2835\outlinelevel1\adjustright \b\f2\lang2057 {5.4 Address decoding and memory +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {Figure 3 shows the memory map. +\par }{\fs24 \page +\par +\par +\par +\par +\par +\par +\par +\par +\par }\trowd \trgaph108\trleft-108\trkeep\trbrdrt\brdrs\brdrw10 \trbrdrl\brdrs\brdrw10 \trbrdrb\brdrs\brdrw10 \trbrdrr\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 \trbrdrv\brdrs\brdrw10 \clvertalt\cltxlrtb \cellx792\clvertalt\cltxlrtb \cellx2500\clvertalt\cltxlrtb +\cellx3224\clvertalt\cltxlrtb \cellx4932\clvertalt\cltxlrtb \cellx7182\clvertalc\clbrdrt\brdrs\brdrw10 \clbrdrl\brdrs\brdrw10 \clbrdrb\brdrdash\brdrw10 \clbrdrr\brdrs\brdrw10 \cltxlrtb \cellx8982\pard \qj\nowidctlpar\intbl\tx2835\adjustright { +\lang1024\cgrid {\shp{\*\shpinst\shpleft6525\shptop-80\shpright7101\shpbottom208\shpfhdr0\shpbxcolumn\shpbypara\shpwr3\shpwrk0\shpfblwtxt0\shpz16\shplid1155{\sp{\sn shapeType}{\sv 202}}{\sp{\sn fFlipH}{\sv 0}}{\sp{\sn fFlipV}{\sv 0}} +{\sp{\sn lTxid}{\sv 65536}}{\sp{\sn dxTextLeft}{\sv 0}}{\sp{\sn dyTextTop}{\sv 0}}{\sp{\sn dxTextRight}{\sv 0}}{\sp{\sn dyTextBottom}{\sv 0}}{\sp{\sn hspNext}{\sv 1155}}{\sp{\sn fLine}{\sv 0}}{\shptxt \pard\plain \qr\nowidctlpar\tx2835\adjustright +\f2\fs22\lang2057 {\lang1031 FFFF}{\b\lang1031 +\par }}}{\shprslt{\*\do\dobxcolumn\dobypara\dodhgt8208\dptxbx{\dptxbxtext\pard\plain \qr\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {\lang1031 FFFF}{\b\lang1031 +\par }}\dpx6525\dpy-80\dpxsize576\dpysize288\dpfillfgcr255\dpfillfgcg255\dpfillfgcb255\dpfillbgcr255\dpfillbgcg255\dpfillbgcb255\dpfillpat1\dplinehollow}}} +{\shp{\*\shpinst\shpleft6540\shptop412\shpright7116\shpbottom700\shpfhdr0\shpbxcolumn\shpbypara\shpwr3\shpwrk0\shpfblwtxt0\shpz17\shplid1156{\sp{\sn shapeType}{\sv 202}}{\sp{\sn fFlipH}{\sv 0}}{\sp{\sn fFlipV}{\sv 0}} +{\sp{\sn lTxid}{\sv 131072}}{\sp{\sn dxTextLeft}{\sv 0}}{\sp{\sn dyTextTop}{\sv 0}}{\sp{\sn dxTextRight}{\sv 0}}{\sp{\sn dyTextBottom}{\sv 0}}{\sp{\sn hspNext}{\sv 1156}}{\sp{\sn fLine}{\sv 0}}{\shptxt \pard\plain \qr\nowidctlpar\tx2835\adjustright +\f2\fs22\lang2057 {\lang1031 FF00}{\b\lang1031 +\par }}}{\shprslt{\*\do\dobxcolumn\dobypara\dodhgt8209\dptxbx{\dptxbxtext\pard\plain \qr\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {\lang1031 FF00}{\b\lang1031 +\par }}\dpx6540\dpy412\dpxsize576\dpysize288\dpfillfgcr255\dpfillfgcg255\dpfillfgcb255\dpfillbgcr255\dpfillbgcg255\dpfillbgcb255\dpfillpat1\dplinehollow}}}}{\fs24 \cell \cell \cell \cell }\pard \qc\nowidctlpar\intbl\tx2835\adjustright {\fs24 +\par }\pard \qr\nowidctlpar\intbl\tx2835\adjustright {\fs24 \cell }\pard \qc\nowidctlpar\intbl\tx2835\adjustright {\f1\fs20 O/S\cell }\pard \widctlpar\intbl\adjustright {\fs24 \row }\trowd \trgaph108\trrh108\trleft-108\trkeep\trbrdrt\brdrs\brdrw10 \trbrdrl +\brdrs\brdrw10 \trbrdrb\brdrs\brdrw10 \trbrdrr\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 \trbrdrv\brdrs\brdrw10 \clvertalt\cltxlrtb \cellx792\clvertalt\cltxlrtb \cellx2500\clvertalt\cltxlrtb \cellx3224\clvertalt\cltxlrtb \cellx4932\clvertalc\cltxlrtb +\cellx7182\clvertalc\clbrdrl\brdrs\brdrw10 \clbrdrb\brdrdash\brdrw10 \clbrdrr\brdrs\brdrw10 \cltxlrtb \cellx8982\pard \qj\nowidctlpar\intbl\tx2835\adjustright {\lang1024\cgrid +{\shp{\*\shpinst\shpleft6480\shptop2030\shpright7056\shpbottom2318\shpfhdr0\shpbxcolumn\shpbypara\shpwr3\shpwrk0\shpfblwtxt0\shpz19\shplid1157{\sp{\sn shapeType}{\sv 202}}{\sp{\sn fFlipH}{\sv 0}}{\sp{\sn fFlipV}{\sv 0}} +{\sp{\sn lTxid}{\sv 196608}}{\sp{\sn dxTextLeft}{\sv 0}}{\sp{\sn dyTextTop}{\sv 0}}{\sp{\sn dxTextRight}{\sv 0}}{\sp{\sn dyTextBottom}{\sv 0}}{\sp{\sn hspNext}{\sv 1157}}{\sp{\sn fLine}{\sv 0}}{\shptxt \pard\plain \qr\nowidctlpar\tx2835\adjustright +\f2\fs22\lang2057 {\lang1031 C000}{\b\lang1031 +\par }}}{\shprslt{\*\do\dobxcolumn\dobypara\dodhgt8211\dptxbx{\dptxbxtext\pard\plain \qr\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {\lang1031 C000}{\b\lang1031 +\par }}\dpx6480\dpy2030\dpxsize576\dpysize288\dpfillfgcr255\dpfillfgcg255\dpfillfgcb255\dpfillbgcr255\dpfillbgcg255\dpfillbgcb255\dpfillpat1\dplinehollow}}} +{\shp{\*\shpinst\shpleft6540\shptop161\shpright7116\shpbottom449\shpfhdr0\shpbxcolumn\shpbypara\shpwr3\shpwrk0\shpfblwtxt0\shpz18\shplid1158{\sp{\sn shapeType}{\sv 202}}{\sp{\sn fFlipH}{\sv 0}}{\sp{\sn fFlipV}{\sv 0}} +{\sp{\sn lTxid}{\sv 262144}}{\sp{\sn dxTextLeft}{\sv 0}}{\sp{\sn dyTextTop}{\sv 0}}{\sp{\sn dxTextRight}{\sv 0}}{\sp{\sn dyTextBottom}{\sv 0}}{\sp{\sn hspNext}{\sv 1158}}{\sp{\sn fLine}{\sv 0}}{\shptxt \pard\plain \qr\nowidctlpar\tx2835\adjustright +\f2\fs22\lang2057 {\lang1031 FC00}{\b\lang1031 +\par }}}{\shprslt{\*\do\dobxcolumn\dobypara\dodhgt8210\dptxbx{\dptxbxtext\pard\plain \qr\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {\lang1031 FC00}{\b\lang1031 +\par }}\dpx6540\dpy161\dpxsize576\dpysize288\dpfillfgcr255\dpfillfgcg255\dpfillfgcb255\dpfillbgcr255\dpfillbgcg255\dpfillbgcb255\dpfillpat1\dplinehollow}}}}{\fs24 \cell \cell \cell \cell }\pard \qr\nowidctlpar\intbl\tx2835\adjustright {\fs24 \cell }\pard +\qc\nowidctlpar\intbl\tx2835\adjustright {\f1\fs20 I/O\cell }\pard \widctlpar\intbl\adjustright {\fs24 \row }\trowd \trgaph108\trrh1880\trleft-108\trbrdrt\brdrs\brdrw10 \trbrdrl\brdrs\brdrw10 \trbrdrb\brdrs\brdrw10 \trbrdrr\brdrs\brdrw10 \trbrdrh +\brdrs\brdrw10 \trbrdrv\brdrs\brdrw10 \clvertalt\cltxlrtb \cellx792\clvertalt\cltxlrtb \cellx2500\clvertalt\cltxlrtb \cellx3224\clvertalt\cltxlrtb \cellx4932\clvertalt\cltxlrtb \cellx7182\clvertalc\clbrdrl\brdrs\brdrw10 \clbrdrr\brdrs\brdrw10 \cltxlrtb +\cellx8982\pard \qj\nowidctlpar\intbl\tx2835\adjustright {\fs24 \cell \cell \cell \cell }\pard \qr\nowidctlpar\intbl\tx2835\adjustright {\fs24 \cell }\pard \qc\nowidctlpar\intbl\tx2835\adjustright {\f1\fs20 OPERATING SYSTEM\cell }\pard +\widctlpar\intbl\adjustright {\fs24 \row }\trowd \trgaph108\trrh170\trleft-108\trkeep\trbrdrt\brdrs\brdrw10 \trbrdrl\brdrs\brdrw10 \trbrdrb\brdrs\brdrw10 \trbrdrr\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 \trbrdrv\brdrs\brdrw10 \clvertalb\cltxlrtb \cellx792 +\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrl\brdrdash\brdrw10 \clbrdrr\brdrdash\brdrw10 \cltxlrtb \cellx2500\clvmgf\clvertalt\cltxlrtb \cellx3224\clvmgf\clvertalc\clbrdrt\brdrs\brdrw10 \clbrdrl\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \clbrdrr\brdrs\brdrw10 +\cltxlrtb \cellx4932\clvertalb\cltxlrtb \cellx7182\clvmgf\clvertalc\clbrdrt\brdrdash\brdrw10 \clbrdrl\brdrs\brdrw10 \clbrdrr\brdrs\brdrw10 \cltxlrtb \cellx8982\pard \qr\nowidctlpar\intbl\tx2835\adjustright {\lang1024\cgrid +{\shp{\*\shpinst\shpleft2448\shptop650\shpright3168\shpbottom650\shpfhdr0\shpbxcolumn\shpbypara\shpwr3\shpwrk0\shpfblwtxt0\shpz28\shplid1159{\sp{\sn shapeType}{\sv 20}}{\sp{\sn fFlipH}{\sv 1}}{\sp{\sn fFlipV}{\sv 0}} +{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn lineEndArrowhead}{\sv 1}}{\sp{\sn fArrowheadsOK}{\sv 1}}}{\shprslt{\*\do\dobxcolumn\dobypara\dodhgt8220\dpline\dpptx720\dppty0\dpptx0\dppty0 +\dpx2448\dpy650\dpxsize720\dpysize0\dplinew15\dplinecor0\dplinecog0\dplinecob0}}}{\shp{\*\shpinst\shpleft2448\shptop2\shpright3168\shpbottom2\shpfhdr0\shpbxcolumn\shpbypara\shpwr3\shpwrk0\shpfblwtxt0\shpz29\shplid1160 +{\sp{\sn shapeType}{\sv 20}}{\sp{\sn fFlipH}{\sv 1}}{\sp{\sn fFlipV}{\sv 0}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}} +{\sp{\sn lineEndArrowhead}{\sv 1}}{\sp{\sn fArrowheadsOK}{\sv 1}}}{\shprslt{\*\do\dobxcolumn\dobypara\dodhgt8221\dpline\dpptx720\dppty0\dpptx0\dppty0\dpx2448\dpy2\dpxsize720\dpysize0\dplinew15\dplinecor0\dplinecog0\dplinecob0}}} +{\shp{\*\shpinst\shpleft2448\shptop326\shpright3168\shpbottom326\shpfhdr0\shpbxcolumn\shpbypara\shpwr3\shpwrk0\shpfblwtxt0\shpz27\shplid1161{\sp{\sn shapeType}{\sv 20}}{\sp{\sn fFlipH}{\sv 1}}{\sp{\sn fFlipV}{\sv 0}} +{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn lineEndArrowhead}{\sv 1}}{\sp{\sn fArrowheadsOK}{\sv 1}}}{\shprslt{\*\do\dobxcolumn\dobypara\dodhgt8219\dpline\dpptx720\dppty0\dpptx0\dppty0 +\dpx2448\dpy326\dpxsize720\dpysize0\dplinew15\dplinecor0\dplinecog0\dplinecob0}}}}{\f1\fs20 \cell }\pard \qc\nowidctlpar\intbl\tx2835\adjustright {\f1\fs20 4K BACKGROUND ROM\cell }\pard \qj\nowidctlpar\intbl\tx2835\adjustright {\fs24 \cell }\pard +\qc\nowidctlpar\intbl\tx2835\adjustright {\f1\fs20 16K +\par SIDEWAYS +\par ROMS +\par 2-11}{\fs24 \cell }\pard \qr\nowidctlpar\intbl\tx2835\adjustright {\fs24 +\par \cell }\pard \qc\nowidctlpar\intbl\tx2835\adjustright {\f1\fs20 BASIC +\par ROM +\par 0-1 or 14-15}{\fs24 \cell }\pard \widctlpar\intbl\adjustright {\fs24 \row }\trowd \trgaph108\trrh1277\trleft-108\trkeep\trbrdrt\brdrs\brdrw10 \trbrdrl\brdrs\brdrw10 \trbrdrb\brdrs\brdrw10 \trbrdrr\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 \trbrdrv +\brdrs\brdrw10 \clvertalb\cltxlrtb \cellx792\clvertalc\clbrdrt\brdrs\brdrw10 \clbrdrl\brdrs\brdrw10 \clbrdrb\brdrdash\brdrw10 \clbrdrr\brdrs\brdrw10 \cltxlrtb \cellx2500\clvmrg\clvertalt\cltxlrtb \cellx3224\clvmrg\clvertalt\clbrdrt\brdrdash\brdrw10 +\clbrdrl\brdrs\brdrw10 \clbrdrr\brdrs\brdrw10 \cltxlrtb \cellx4932\clvertalb\cltxlrtb \cellx7182\clvmrg\clvertalc\clbrdrl\brdrs\brdrw10 \clbrdrr\brdrs\brdrw10 \cltxlrtb \cellx8982\pard \qr\nowidctlpar\intbl\tx2835\adjustright {\lang1024\cgrid +{\shp{\*\shpinst\shpleft144\shptop1175\shpright720\shpbottom1463\shpfhdr0\shpbxcolumn\shpbypara\shpwr3\shpwrk0\shpfblwtxt0\shpz25\shplid1162{\sp{\sn shapeType}{\sv 202}}{\sp{\sn fFlipH}{\sv 0}}{\sp{\sn fFlipV}{\sv 0}} +{\sp{\sn lTxid}{\sv 327680}}{\sp{\sn dxTextLeft}{\sv 0}}{\sp{\sn dyTextTop}{\sv 0}}{\sp{\sn dxTextRight}{\sv 0}}{\sp{\sn dyTextBottom}{\sv 0}}{\sp{\sn hspNext}{\sv 1162}}{\sp{\sn fLine}{\sv 0}}{\shptxt \pard\plain \qr\nowidctlpar\tx2835\adjustright +\f2\fs22\lang2057 {\lang1031 8000}{\b\lang1031 +\par }}}{\shprslt{\*\do\dobxcolumn\dobypara\dodhgt8217\dptxbx{\dptxbxtext\pard\plain \qr\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {\lang1031 8000}{\b\lang1031 +\par }}\dpx144\dpy1175\dpxsize576\dpysize288\dpfillfgcr255\dpfillfgcg255\dpfillfgcb255\dpfillbgcr255\dpfillbgcg255\dpfillbgcb255\dpfillpat1\dplinehollow}}} +{\shp{\*\shpinst\shpleft6480\shptop1175\shpright7056\shpbottom1463\shpfhdr0\shpbxcolumn\shpbypara\shpwr3\shpwrk0\shpfblwtxt0\shpz20\shplid1163{\sp{\sn shapeType}{\sv 202}}{\sp{\sn fFlipH}{\sv 0}}{\sp{\sn fFlipV}{\sv 0}} +{\sp{\sn lTxid}{\sv 393216}}{\sp{\sn dxTextLeft}{\sv 0}}{\sp{\sn dyTextTop}{\sv 0}}{\sp{\sn dxTextRight}{\sv 0}}{\sp{\sn dyTextBottom}{\sv 0}}{\sp{\sn hspNext}{\sv 1163}}{\sp{\sn fLine}{\sv 0}}{\shptxt \pard\plain \qr\nowidctlpar\tx2835\adjustright +\f2\fs22\lang2057 {\lang1031 8000}{\b\lang1031 +\par }}}{\shprslt{\*\do\dobxcolumn\dobypara\dodhgt8212\dptxbx{\dptxbxtext\pard\plain \qr\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {\lang1031 8000}{\b\lang1031 +\par }}\dpx6480\dpy1175\dpxsize576\dpysize288\dpfillfgcr255\dpfillfgcg255\dpfillfgcb255\dpfillbgcr255\dpfillbgcg255\dpfillbgcb255\dpfillpat1\dplinehollow}}}}{\f1\fs20 \cell }\pard \qc\nowidctlpar\intbl\tx2835\adjustright {\f1\fs20 12K +\par SIDEWAYS RAM\cell }\pard \qj\nowidctlpar\intbl\tx2835\adjustright {\fs24 \cell \cell }\pard \qc\nowidctlpar\intbl\tx2835\adjustright {\fs24 \cell }{\f1\fs20 \cell }\pard \widctlpar\intbl\adjustright {\fs24 \row }\trowd \trgaph108\trleft-108\trkeep\trbrdrt +\brdrs\brdrw10 \trbrdrl\brdrs\brdrw10 \trbrdrb\brdrs\brdrw10 \trbrdrr\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 \trbrdrv\brdrs\brdrw10 \clvmgf\clvertalb\cltxlrtb \cellx792\clvmgf\clvertalc\clbrdrl\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \clbrdrr\brdrs\brdrw10 +\cltxlrtb \cellx2500\clvertalt\cltxlrtb \cellx3224\clvertalt\clbrdrt\brdrs\brdrw10 \cltxlrtb \cellx4932\clvertalt\cltxlrtb \cellx7182\clvmgf\clvertalc\clbrdrt\brdrdash\brdrw10 \clbrdrl\brdrs\brdrw10 \clbrdrr\brdrs\brdrw10 \cltxlrtb \cellx8982\pard +\qr\sa240\nowidctlpar\intbl\tx2835\adjustright {\lang1024\cgrid {\shp{\*\shpinst\shpleft144\shptop3128\shpright720\shpbottom3416\shpfhdr0\shpbxcolumn\shpbypara\shpwr3\shpwrk0\shpfblwtxt0\shpz26\shplid1164 +{\sp{\sn shapeType}{\sv 202}}{\sp{\sn fFlipH}{\sv 0}}{\sp{\sn fFlipV}{\sv 0}}{\sp{\sn lTxid}{\sv 458752}}{\sp{\sn dxTextLeft}{\sv 0}}{\sp{\sn dyTextTop}{\sv 0}}{\sp{\sn dxTextRight}{\sv 0}}{\sp{\sn dyTextBottom}{\sv 0}}{\sp{\sn hspNext}{\sv 1164}} +{\sp{\sn fLine}{\sv 0}}{\shptxt \pard\plain \qr\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {\lang1031 3000 +\par }}}{\shprslt{\*\do\dobxcolumn\dobypara\dodhgt8218\dptxbx{\dptxbxtext\pard\plain \qr\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {\lang1031 3000 +\par }}\dpx144\dpy3128\dpxsize576\dpysize288\dpfillfgcr255\dpfillfgcg255\dpfillfgcb255\dpfillbgcr255\dpfillbgcg255\dpfillbgcb255\dpfillpat1\dplinehollow}}} +{\shp{\*\shpinst\shpleft144\shptop-1408\shpright720\shpbottom-1120\shpfhdr0\shpbxcolumn\shpbypara\shpwr3\shpwrk0\shpfblwtxt0\shpz24\shplid1165{\sp{\sn shapeType}{\sv 202}}{\sp{\sn fFlipH}{\sv 0}}{\sp{\sn fFlipV}{\sv 0}} +{\sp{\sn lTxid}{\sv 524288}}{\sp{\sn dxTextLeft}{\sv 0}}{\sp{\sn dyTextTop}{\sv 0}}{\sp{\sn dxTextRight}{\sv 0}}{\sp{\sn dyTextBottom}{\sv 0}}{\sp{\sn hspNext}{\sv 1165}}{\sp{\sn fLine}{\sv 0}}{\shptxt \pard\plain \qr\nowidctlpar\tx2835\adjustright +\f2\fs22\lang2057 {\lang1031 B000}{\b\lang1031 +\par }}}{\shprslt{\*\do\dobxcolumn\dobypara\dodhgt8216\dptxbx{\dptxbxtext\pard\plain \qr\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {\lang1031 B000}{\b\lang1031 +\par }}\dpx144\dpy-1408\dpxsize576\dpysize288\dpfillfgcr255\dpfillfgcg255\dpfillfgcb255\dpfillbgcr255\dpfillbgcg255\dpfillbgcb255\dpfillpat1\dplinehollow}}} +{\shp{\*\shpinst\shpleft6480\shptop2264\shpright7056\shpbottom2552\shpfhdr0\shpbxcolumn\shpbypara\shpwr3\shpwrk0\shpfblwtxt0\shpz23\shplid1166{\sp{\sn shapeType}{\sv 202}}{\sp{\sn fFlipH}{\sv 0}}{\sp{\sn fFlipV}{\sv 0}} +{\sp{\sn lTxid}{\sv 589824}}{\sp{\sn dxTextLeft}{\sv 0}}{\sp{\sn dyTextTop}{\sv 0}}{\sp{\sn dxTextRight}{\sv 0}}{\sp{\sn dyTextBottom}{\sv 0}}{\sp{\sn hspNext}{\sv 1166}}{\sp{\sn fLine}{\sv 0}}{\shptxt \pard\plain \qr\nowidctlpar\tx2835\adjustright +\f2\fs22\lang2057 {\lang1031 3000}{\b\lang1031 +\par }}}{\shprslt{\*\do\dobxcolumn\dobypara\dodhgt8215\dptxbx{\dptxbxtext\pard\plain \qr\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {\lang1031 3000}{\b\lang1031 +\par }}\dpx6480\dpy2264\dpxsize576\dpysize288\dpfillfgcr255\dpfillfgcg255\dpfillfgcb255\dpfillbgcr255\dpfillbgcg255\dpfillbgcb255\dpfillpat1\dplinehollow}}} +{\shp{\*\shpinst\shpleft5904\shptop3128\shpright7056\shpbottom3632\shpfhdr0\shpbxcolumn\shpbypara\shpwr3\shpwrk0\shpfblwtxt0\shpz21\shplid1167{\sp{\sn shapeType}{\sv 202}}{\sp{\sn fFlipH}{\sv 0}}{\sp{\sn fFlipV}{\sv 0}} +{\sp{\sn lTxid}{\sv 655360}}{\sp{\sn dxTextLeft}{\sv 0}}{\sp{\sn dyTextTop}{\sv 0}}{\sp{\sn dxTextRight}{\sv 0}}{\sp{\sn dyTextBottom}{\sv 0}}{\sp{\sn hspNext}{\sv 1167}}{\sp{\sn fLine}{\sv 0}}{\shptxt \pard\plain \qr\nowidctlpar\tx2835\adjustright +\f2\fs22\lang2057 {\lang1031 0E00 +\par Upwards +\par }}}{\shprslt{\*\do\dobxcolumn\dobypara\dodhgt8213\dptxbx{\dptxbxtext\pard\plain \qr\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {\lang1031 0E00 +\par Upwards +\par }}\dpx5904\dpy3128\dpxsize1152\dpysize504\dpfillfgcr255\dpfillfgcg255\dpfillfgcb255\dpfillbgcr255\dpfillbgcg255\dpfillbgcb255\dpfillpat1\dplinehollow}}}}{\f1\fs20 \cell }\pard \qc\nowidctlpar\intbl\tx2835\adjustright {\fs24 20K +\par SHADOW SCREEN +\par RAM\cell }\pard \qj\nowidctlpar\intbl\tx2835\adjustright {\fs24 \cell \cell }\pard \qr\sa240\nowidctlpar\intbl\tx2835\adjustright {\fs24 \cell }\pard \qc\sa240\nowidctlpar\intbl\tx2835\adjustright {\f1\fs20 NORMAL +\par SCREEN +\par RAM}{\fs24 \cell }\pard \widctlpar\intbl\adjustright {\fs24 \row }\trowd \trgaph108\trleft-108\trkeep\trbrdrt\brdrs\brdrw10 \trbrdrl\brdrs\brdrw10 \trbrdrb\brdrs\brdrw10 \trbrdrr\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 \trbrdrv\brdrs\brdrw10 +\clvmrg\clvertalt\clbrdrt\brdrdash\brdrw10 \cltxlrtb \cellx792\clvmrg\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrl\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \clbrdrr\brdrs\brdrw10 \cltxlrtb \cellx2500\clvmgf\clvertalt\clbrdrl\brdrs\brdrw10 \cltxlrtb \cellx7182 +\clvmrg\clvertalt\clbrdrl\brdrs\brdrw10 \clbrdrr\brdrs\brdrw10 \cltxlrtb \cellx8982\pard \qj\sa240\nowidctlpar\intbl\tx2835\adjustright {\fs24 \cell \cell \cell \cell }\pard \widctlpar\intbl\adjustright {\fs24 \row }\trowd +\trgaph108\trrh917\trleft-108\trkeep\trbrdrt\brdrs\brdrw10 \trbrdrl\brdrs\brdrw10 \trbrdrb\brdrs\brdrw10 \trbrdrr\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 \trbrdrv\brdrs\brdrw10 \clvmrg\clvertalt\clbrdrt\brdrdash\brdrw10 \cltxlrtb \cellx792\clvmrg\clvertalt +\clbrdrt\brdrs\brdrw10 \clbrdrl\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \clbrdrr\brdrs\brdrw10 \cltxlrtb \cellx2500\clvmrg\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrl\brdrs\brdrw10 \cltxlrtb \cellx7182\clvmrg\clvertalt\clbrdrl\brdrs\brdrw10 \clbrdrr +\brdrs\brdrw10 \cltxlrtb \cellx8982\pard \qj\sa240\nowidctlpar\intbl\tx2835\adjustright {\fs24 \cell \cell \cell \cell }\pard \widctlpar\intbl\adjustright {\fs24 \row }\trowd \trgaph108\trrh1295\trleft-108\trkeep\trbrdrt\brdrs\brdrw10 \trbrdrl +\brdrs\brdrw10 \trbrdrb\brdrs\brdrw10 \trbrdrr\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 \trbrdrv\brdrs\brdrw10 \clvmrg\clvertalt\clbrdrt\brdrdash\brdrw10 \cltxlrtb \cellx792\clvmrg\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrl\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 +\clbrdrr\brdrs\brdrw10 \cltxlrtb \cellx2500\clvertalt\clbrdrl\brdrs\brdrw10 \cltxlrtb \cellx7182\clvmrg\clvertalt\clbrdrl\brdrs\brdrw10 \clbrdrr\brdrs\brdrw10 \cltxlrtb \cellx8982\pard \qj\sa240\nowidctlpar\intbl\tx2835\adjustright {\fs24 \cell \cell +\cell \cell }\pard \widctlpar\intbl\adjustright {\fs24 \row }\trowd \trgaph108\trrh665\trleft-108\trkeep\trbrdrt\brdrs\brdrw10 \trbrdrl\brdrs\brdrw10 \trbrdrb\brdrs\brdrw10 \trbrdrr\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 \trbrdrv\brdrs\brdrw10 +\clvertalt\cltxlrtb \cellx7182\clvertalc\clbrdrt\brdrdash\brdrw10 \clbrdrl\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \clbrdrr\brdrs\brdrw10 \cltxlrtb \cellx8982\pard \qj\sa240\nowidctlpar\intbl\tx2835\adjustright {\lang1024\cgrid +{\shp{\*\shpinst\shpleft6480\shptop500\shpright7056\shpbottom788\shpfhdr0\shpbxcolumn\shpbypara\shpwr3\shpwrk0\shpfblwtxt0\shpz22\shplid1168{\sp{\sn shapeType}{\sv 202}}{\sp{\sn fFlipH}{\sv 0}}{\sp{\sn fFlipV}{\sv 0}} +{\sp{\sn lTxid}{\sv 720896}}{\sp{\sn dxTextLeft}{\sv 0}}{\sp{\sn dyTextTop}{\sv 0}}{\sp{\sn dxTextRight}{\sv 0}}{\sp{\sn dyTextBottom}{\sv 0}}{\sp{\sn hspNext}{\sv 1168}}{\sp{\sn fLine}{\sv 0}}{\shptxt \pard\plain \qr\nowidctlpar\tx2835\adjustright +\f2\fs22\lang2057 {\lang1031 0000 +\par }}}{\shprslt{\*\do\dobxcolumn\dobypara\dodhgt8214\dptxbx{\dptxbxtext\pard\plain \qr\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {\lang1031 0000 +\par }}\dpx6480\dpy500\dpxsize576\dpysize288\dpfillfgcr255\dpfillfgcg255\dpfillfgcb255\dpfillbgcr255\dpfillbgcg255\dpfillbgcb255\dpfillpat1\dplinehollow}}}}{\fs24 \cell }\pard \qc\nowidctlpar\intbl\tx2835\adjustright {\fs24 WORKSPACE\cell }\pard +\widctlpar\intbl\adjustright {\fs24 \row }\pard \qj\sa240\nowidctlpar\tx2835\adjustright { +\par +\par }\pard\plain \s20\qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {Figure 3 Memory map +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {\fs24 \page }{At the heart of the memory selection is the progr +ammable array logic (PAL) chip IC36. It selects which screen RAM is in use (normal or shadow); it controls the sideways ROM select latch IC45; it selects the paged RAM. +\par }\pard\plain \s3\sa240\keepn\nowidctlpar\tx2835\outlinelevel2\adjustright \b\f2 {\fs22 5.4.1 ROM operation +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {Any ROM socket on the PCB can either hold an 8K, 16K or 32K BYTE de +vice. 8K or 16K IC's are paged into the memory map from &8000-&9FFF or from &8000-&BFFF respectively, a 32K device provides two 16K banks of memory paged into the memory map from &8000-&BFFF. The extra address line A14 (QA, from IC45) required by 32K devi +ces is available to each ROM slot when the appropriate molex link is altered. The ROM socket IC numbers, their corresponding ROM select numbers and their corresponding link numbers are shown in figure 4. +\par }\pard\plain \s20\qj\sa240\nowidctlpar\tx2835\tx3119\adjustright \f2\fs22\lang2057 {IC No ROM Nos Link No \tab Notes +\par }\pard\plain \qj\nowidctlpar\tx2835\tx3119\adjustright \f2\fs22\lang2057 {IC35 2/3 S9\tab Molex link made W as standard for 8K/16K use +\par IC44 4/5 S11\tab \tab \tab "\tab \tab "\tab \tab " +\par IC57 6/7 S12\tab \tab \tab "\tab \tab "\tab \tab " +\par IC62 8/9 S15\tab \tab \tab "\tab \tab "\tab \tab " +\par IC68 10/11 S18\tab \tab \tab "\tab \tab "\tab \tab " +\par IC71 0/1 or S19\tab PCB cuttable link made E as standard for 32K +\par }\pard \qj\ri720\nowidctlpar\tx2835\tx3119\adjustright { 14/15\tab (16K operating system and I/O and 16K BASIC) +\par }\pard \qj\ri720\nowidctlpar\tx2835\adjustright { +\par }\pard \qj\fi-1276\li1276\ri720\sa240\nowidctlpar\tx1276\tx2835\adjustright {Figure 4\tab ROM socket IC numbers, ROM numbers, and device selection link numbers +\par }\pard \qj\sa240\nowidctlpar\tx2835\adjustright {As can be seen from figure 4, ROM numbers range from 0 to 15. ROMs are prioritised, the highest ROM number language and filing system will be selecte +d after a 'hard' reset. 15 has the highest priority, 0 the lowest. So if two or more sideways ROMs are language ROMs, then the computer will start up in the language in the highest number ROM slot. Similarly for filing system ROMs. +\par IC35, 44, 57, 62, and 68 we shall call "user ROMs". Each user ROM socket is functionally identical and can contain language or service ROMs. IC71 we shall call the "system ROM". +\par The system ROM contains the operating system. The operating system is always in the memory map from &C +000-&FFFF and must always be fitted in IC71. As standard, the computer comes with a 32K ROM for IC71. It contains the operating system and the BASIC language. For this reason link S19 is hard wired East in the 32K position. +\par The BASIC part of the system ROM + occupies one of four sideways ROM numbers. As standard, any call made to ROM 14 or 15 selects BASIC, and any call to ROM 0 or 1 is ignored. Hence BASIC occupies the highest priority ROM slot and the computer will start up in BASIC. If molex link S13 is m +o +ved from South to North then any call made to ROM 0 or 1 will select BASIC, and any call to ROM 14 or 15 will be ignored. This allows the user to select an alternative language at power-on (the language entered at start-up will be the one with the highest + socket number when more than one language ROM is fitted). +\par }{\fs24 \page }{Address decoding is carried out by the PAL (IC36) and this then selects either the operating system (if the address is in the range &C000-&FFFF) or the current sideways ROM (if the address is in th +e range &8000-&BFFF). Part of IC40 disables the ROM output drivers when an I/O address occurs (&FC00-&FEFF). +\par The currently selected ROM number (0-15) is held in the ROM select latch IC45. The ROM select latch is mapped into the memory at address &FE30 via +the PAL IC36. When writing to this address, the four data lines D0-D3 provide the ROM number which is latched into IC45, see also 5.4.2. +\par When the PAL decodes an address from &8000-&BFFF, IC36 pin 18 goes low and enables IC46. IC46 is a three line to eight +line decoder which selects the particular IC socket allocated to the ROM number, in IC45. The least significant bit held in IC45 is fed to the relevant ROM socket only if the link for that socket is made E for a 32K device. The correct half of the 32K dev +ice is then selected to be placed in the memory map. +\par }\pard\plain \s3\sa240\keepn\nowidctlpar\tx2835\outlinelevel2\adjustright \b\f2 {5.4.2 Paged RAM operation +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {The 12K paged RAM is selected with a ROM number between 128 and 255 (D7 set). The top bit of the data bus D7 is available to the PAL IC36. Writing to the ROM select latch at addr +ess &FE30 as described in 5.4.1, will save D7 in the PAL. D0-D3 are stored as normal in IC45. If D7 is set (logic 1) then the PAL selects the 12K paged RAM when the CPU address is in the range &8000 to &AFFF. If the ROM selected by D0-D3 is present then t +h +e top 4K of that ROM will also appear in the memory map, above the 12K paged RAM, from &B000-&BFFF. As ROM 0 is not allocated as standard (it is BASIC if S13 is changed), writing 128 to the ROM select latch will merely place the 12K paged RAM into the mem +ory map and &B000-&BFFF will be vacant. +\par }\pard\plain \s3\sa240\keepn\nowidctlpar\tx2835\outlinelevel2\adjustright \b\f2 {5.4.3 RAM access +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {There is 64K of installed RAM. +\par RAM access is dependent on whether the computer is in normal mode or shadow mode, and the differences are shown in Figure 5. +\par \page +\par +\par +\par }\trowd \trgaph108\trrh760\trleft284 \clvertalb\cltxlrtb \cellx993\clvertalt\cltxlrtb \cellx2268\clvertalt\cltxlrtb \cellx3414\clvertalt\cltxlrtb \cellx4695\clvertalt\cltxlrtb \cellx6096\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrl\brdrs\brdrw10 \clbrdrb +\brdrs\brdrw10 \clbrdrr\brdrs\brdrw10 \cltxlrtb \cellx7257\clvertalt\cltxlrtb \cellx8538\clvertalt\cltxlrtb \cellx9819\pard \qj\sa240\nowidctlpar\intbl\tx2835\adjustright {\f1\fs20 64K\cell \cell \cell \cell \cell +\par PAL +\par IC36\cell \cell \cell }\pard \widctlpar\intbl\adjustright {\f1\fs20 \row }\trowd \trgaph108\trrh630\trleft284\trkeep \clvmgf\clvertalt\cltxlrtb \cellx993\clvmgf\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrl\brdrs\brdrw10 \clbrdrr\brdrs\brdrw10 +\clbgfdiag\cltxlrtb \cellx2268\clvmgf\clvertalt\cltxlrtb \cellx3414\clvertalt\cltxlrtb \cellx4054\clvertalt\cltxlrtb \cellx4695\clvertalb\cltxlrtb \cellx6096\clvertalt\cltxlrtb \cellx7230\clvertalb\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx8538 +\clvertalt\cltxlrtb \cellx9178\clvertalt\cltxlrtb \cellx9819\pard \qj\sa240\nowidctlpar\intbl\tx2835\adjustright {\lang1024\cgrid +{\shp{\*\shpinst\shpleft6625\shptop320\shpright7057\shpbottom781\shpfhdr0\shpbxcolumn\shpbypara\shpwr3\shpwrk0\shpfblwtxt0\shpz34\shplid1169{\sp{\sn shapeType}{\sv 20}}{\sp{\sn fFlipH}{\sv 0}}{\sp{\sn fFlipV}{\sv 0}} +{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn lineWidth}{\sv 22225}}{\sp{\sn fArrowheadsOK}{\sv 1}}}{\shprslt{\*\do\dobxcolumn\dobypara\dodhgt8226\dpline\dpptx0\dppty0\dpptx432\dppty461 +\dpx6625\dpy320\dpxsize432\dpysize461\dplinew35\dplinecor0\dplinecog0\dplinecob0}}}{\shp{\*\shpinst\shpleft7201\shptop608\shpright7258\shpbottom665\shpfhdr0\shpbxcolumn\shpbypara\shpwr3\shpwrk0\shpfblwtxt0\shpz33\shplid1170 +{\sp{\sn shapeType}{\sv 3}}{\sp{\sn fFlipH}{\sv 0}}{\sp{\sn fFlipV}{\sv 0}}}{\shprslt{\*\do\dobxcolumn\dobypara\dodhgt8225\dpellipse\dpx7201\dpy608\dpxsize57\dpysize57 +\dpfillfgcr255\dpfillfgcg255\dpfillfgcb255\dpfillbgcr255\dpfillbgcg255\dpfillbgcb255\dpfillpat1\dplinew15\dplinecor0\dplinecog0\dplinecob0}}} +{\shp{\*\shpinst\shpleft6049\shptop608\shpright6106\shpbottom665\shpfhdr0\shpbxcolumn\shpbypara\shpwr3\shpwrk0\shpfblwtxt0\shpz32\shplid1171 +{\sp{\sn shapeType}{\sv 3}}{\sp{\sn fFlipH}{\sv 0}}{\sp{\sn fFlipV}{\sv 0}}}{\shprslt{\*\do\dobxcolumn\dobypara\dodhgt8224\dpellipse\dpx6049\dpy608\dpxsize57\dpysize57 +\dpfillfgcr255\dpfillfgcg255\dpfillfgcb255\dpfillbgcr255\dpfillbgcg255\dpfillbgcb255\dpfillpat1\dplinew15\dplinecor0\dplinecog0\dplinecob0}}} +{\shp{\*\shpinst\shpleft6625\shptop330\shpright6682\shpbottom387\shpfhdr0\shpbxcolumn\shpbypara\shpwr3\shpwrk0\shpfblwtxt0\shpz31\shplid1172 +{\sp{\sn shapeType}{\sv 3}}{\sp{\sn fFlipH}{\sv 0}}{\sp{\sn fFlipV}{\sv 0}}}{\shprslt{\*\do\dobxcolumn\dobypara\dodhgt8223\dpellipse\dpx6625\dpy330\dpxsize57\dpysize57 +\dpfillfgcr255\dpfillfgcg255\dpfillfgcb255\dpfillbgcr255\dpfillbgcg255\dpfillbgcb255\dpfillpat1\dplinew15\dplinecor0\dplinecog0\dplinecob0}}} +{\shp{\*\shpinst\shpleft6625\shptop42\shpright6625\shpbottom330\shpfhdr0\shpbxcolumn\shpbypara\shpwr3\shpwrk0\shpfblwtxt0\shpz30\shplid1173{\sp{\sn shapeType}{\sv 20}}{\sp{\sn fFlipH}{\sv 0}}{\sp{\sn fFlipV}{\sv 0}} +{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}}{\shprslt{\*\do\dobxcolumn\dobypara\dodhgt8222\dpline\dpptx0\dppty0\dpptx0\dppty288\dpx6625\dpy42\dpxsize0\dpysize288 +\dplinew15\dplinecor0\dplinecog0\dplinecob0}}}}{\f1\fs20 \cell \cell \cell \cell \cell CPUSEL =1\cell \cell CPUSEL =0\cell \cell \cell }\pard \widctlpar\intbl\adjustright {\f1\fs20 \row }\trowd \trgaph108\trrh630\trleft284\trkeep +\clvmrg\clvertalt\cltxlrtb \cellx993\clvmrg\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrl\brdrs\brdrw10 \clbrdrr\brdrs\brdrw10 \clbgfdiag\cltxlrtb \cellx2268\clvmrg\clvertalt\cltxlrtb \cellx3414\clvertalt\cltxlrtb \cellx4054\clvertalt\clbrdrt\brdrs\brdrw10 +\clbrdrl\brdrs\brdrw10 \cltxlrtb \cellx4695\clvertalt\clbrdrt\brdrs\brdrw10 \cltxlrtb \cellx6096\clvertalt\cltxlrtb \cellx8538\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrr\brdrs\brdrw10 \cltxlrtb \cellx9178\clvertalt\cltxlrtb \cellx9819\pard +\qj\sa240\nowidctlpar\intbl\tx2835\adjustright {\f1\fs20 \cell \cell \cell \cell \cell \cell \cell \cell \cell }\pard \widctlpar\intbl\adjustright {\f1\fs20 \row }\trowd \trgaph108\trrh428\trleft284\trkeep \clvmgf\clvertalb\cltxlrtb \cellx993 +\clvmgf\clvertalt\clbrdrl\brdrs\brdrw10 \clbrdrr\brdrs\brdrw10 \cltxlrtb \cellx2268\clvmgf\clvertalt\cltxlrtb \cellx3414\clvmgf\clvertalt\cltxlrtb \cellx4054\clvmgf\clvertalt\clbrdrl\brdrs\brdrw10 \cltxlrtb \cellx4695\clvmgf\clvertalt\cltxlrtb \cellx6096 +\clvmgf\clvertalt\cltxlrtb \cellx6676\clvertalt\cltxlrtb \cellx7257\clvmgf\clvertalt\clbrdrt\brdrdash\brdrw10 \clbrdrl\brdrdash\brdrw10 \clbrdrb\brdrs\brdrw10 \clbrdrr\brdrdash\brdrw10 \cltxlrtb \cellx8538\clvmgf\clvertalt\clbrdrr\brdrs\brdrw10 \cltxlrtb +\cellx9178\clvmgf\clvertalt\cltxlrtb \cellx9819\pard \qj\sa240\nowidctlpar\intbl\tx2835\adjustright {\lang1024\cgrid +{\shp{\*\shpinst\shpleft7087\shptop470\shpright7231\shpbottom470\shpfhdr0\shpbxcolumn\shpbypara\shpwr3\shpwrk0\shpfblwtxt0\shpz35\shplid1174{\sp{\sn shapeType}{\sv 20}}{\sp{\sn fFlipH}{\sv 0}}{\sp{\sn fFlipV}{\sv 0}} +{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn lineEndArrowhead}{\sv 1}}{\sp{\sn fArrowheadsOK}{\sv 1}}}{\shprslt{\*\do\dobxcolumn\dobypara\dodhgt8227\dpline\dpptx0\dppty0\dpptx144\dppty0 +\dpx7087\dpy470\dpxsize144\dpysize0\dplinew15\dplinecor0\dplinecog0\dplinecob0}}}}{\f1\fs20 32K\cell \cell \cell \cell \cell \cell \cell \cell \cell \cell \cell }\pard \widctlpar\intbl\adjustright {\f1\fs20 \row }\trowd +\trgaph108\trrh190\trleft284\trkeep \clvmrg\clvertalb\cltxlrtb \cellx993\clvmrg\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrl\brdrs\brdrw10 \clbrdrr\brdrs\brdrw10 \cltxlrtb \cellx2268\clvmrg\clvertalt\cltxlrtb \cellx3414\clvmrg\clvertalt\cltxlrtb \cellx4054 +\clvmrg\clvertalt\clbrdrl\brdrs\brdrw10 \cltxlrtb \cellx4695\clvmrg\clvertalt\cltxlrtb \cellx6096\clvmrg\clvertalt\cltxlrtb \cellx6676\clvertalt\clbrdrt\brdrs\brdrw20 \clbrdrl\brdrs\brdrw10 \cltxlrtb \cellx7257\clvmrg\clvertalt\clbrdrt\brdrs\brdrw10 +\clbrdrl\brdrdash\brdrw10 \clbrdrb\brdrs\brdrw10 \clbrdrr\brdrdash\brdrw10 \cltxlrtb \cellx8538\clvmrg\clvertalt\clbrdrr\brdrs\brdrw10 \cltxlrtb \cellx9178\clvmrg\clvertalt\cltxlrtb \cellx9819\pard \qj\sa240\nowidctlpar\intbl\tx2835\adjustright {\f1\fs20 +\cell \cell \cell \cell \cell \cell \cell \cell \cell \cell \cell }\pard \widctlpar\intbl\adjustright {\f1\fs20 \row }\trowd \trgaph108\trrh300\trleft284\trkeep \clvmgf\clvertalt\cltxlrtb \cellx993\clvmgf\clvertalt\clbrdrt\brdrdash\brdrw10 \clbrdrl +\brdrs\brdrw10 \clbrdrr\brdrs\brdrw10 \cltxlrtb \cellx2268\clvmgf\clvertalt\cltxlrtb \cellx3414\clvmgf\clvertalt\cltxlrtb \cellx4054\clvertalt\clbrdrl\brdrs\brdrw10 \cltxlrtb \cellx4695\clvmgf\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrl\brdrs\brdrw10 +\clbrdrb\brdrs\brdrw10 \clbrdrr\brdrs\brdrw10 \cltxlrtb \cellx6096\clvmgf\clvertalt\cltxlrtb \cellx6676\clvmgf\clvertalt\clbrdrl\brdrs\brdrw10 \cltxlrtb \cellx7257\clvmgf\clvertalt\clbrdrl\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \clbrdrr\brdrs\brdrw10 +\cltxlrtb \cellx8538\clvertalt\clbrdrr\brdrs\brdrw10 \cltxlrtb \cellx9178\clvmgf\clvertalt\cltxlrtb \cellx9819\pard \qj\sa240\nowidctlpar\intbl\tx2835\adjustright {\lang1024\cgrid +{\shp{\*\shpinst\shpleft8527\shptop468\shpright9179\shpbottom475\shpfhdr0\shpbxcolumn\shpbypara\shpwr3\shpwrk0\shpfblwtxt0\shpz36\shplid1175{\sp{\sn shapeType}{\sv 20}}{\sp{\sn fFlipH}{\sv 1}}{\sp{\sn fFlipV}{\sv 1}} +{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn lineEndArrowhead}{\sv 1}}{\sp{\sn fArrowheadsOK}{\sv 1}}}{\shprslt{\*\do\dobxcolumn\dobypara\dodhgt8228\dpline\dpptx0\dppty0\dpptx652\dppty7 +\dpx8527\dpy468\dpxsize652\dpysize7\dplinew15\dplinecor0\dplinecog0\dplinecob0}}}{\shp{\*\shpinst\shpleft4063\shptop484\shpright4678\shpbottom484\shpfhdr0\shpbxcolumn\shpbypara\shpwr3\shpwrk0\shpfblwtxt0\shpz37\shplid1176 +{\sp{\sn shapeType}{\sv 20}}{\sp{\sn fFlipH}{\sv 0}}{\sp{\sn fFlipV}{\sv 0}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}} +{\sp{\sn lineEndArrowhead}{\sv 1}}{\sp{\sn fArrowheadsOK}{\sv 1}}}{\shprslt{\*\do\dobxcolumn\dobypara\dodhgt8229\dpline\dpptx0\dppty0\dpptx615\dppty0\dpx4063\dpy484\dpxsize615\dpysize0\dplinew15\dplinecor0\dplinecog0\dplinecob0}}}}{\f1\fs20 \cell +\par 44K NORMAL RAM\cell \cell \cell \cell +\par 20K SHADOW RAM\cell \cell \cell +\par 44K NORMAL RAM\cell \cell \cell }\pard \widctlpar\intbl\adjustright {\f1\fs20 \row }\trowd \trgaph108\trrh1013\trleft284\trkeep \clvmrg\clvertalt\cltxlrtb \cellx993\clvmrg\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrl\brdrs\brdrw10 \clbrdrr\brdrs\brdrw10 +\cltxlrtb \cellx2268\clvmrg\clvertalt\cltxlrtb \cellx3414\clvmrg\clvertalt\cltxlrtb \cellx4054\clvertalt\cltxlrtb \cellx4695\clvmrg\clvertalt\clbrdrt\brdrs\brdrw30 \clbrdrl\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \clbrdrr\brdrs\brdrw10 \cltxlrtb \cellx6096 +\clvmrg\clvertalt\cltxlrtb \cellx6676\clvmrg\clvertalt\clbrdrl\brdrs\brdrw10 \cltxlrtb \cellx7257\clvmrg\clvertalt\clbrdrl\brdrs\brdrw10 \clbrdrr\brdrs\brdrw10 \cltxlrtb \cellx8538\clvertalt\cltxlrtb \cellx9178\clvmrg\clvertalt\cltxlrtb \cellx9819\pard +\qj\sa240\nowidctlpar\intbl\tx2835\adjustright {\f1\fs20 \cell \cell \cell \cell \cell \cell \cell \cell \cell \cell \cell }\pard \widctlpar\intbl\adjustright {\f1\fs20 \row }\trowd \trgaph108\trrh428\trleft284\trkeep \clvmgf\clvertalb\cltxlrtb \cellx993 +\clvmgf\clvertalt\clbrdrl\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \clbrdrr\brdrs\brdrw10 \cltxlrtb \cellx2268\clvmgf\clvertalt\cltxlrtb \cellx3414\clvmgf\clvertalt\cltxlrtb \cellx4695\clvmgf\clvertalt\clbrdrl\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \clbrdrr +\brdrs\brdrw10 \cltxlrtb \cellx6096\clvertalt\clbrdrb\brdrs\brdrw10 \clbrdrr\brdrs\brdrw10 \cltxlrtb \cellx6676\clvmgf\clvertalt\cltxlrtb \cellx7257\clvmgf\clvertalt\clbrdrl\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \clbrdrr\brdrs\brdrw10 \cltxlrtb \cellx8538 +\clvmgf\clvertalt\cltxlrtb \cellx9819\pard \qj\sa240\nowidctlpar\intbl\tx2835\adjustright {\f1\fs20 0\cell \cell \cell \cell \cell \cell \cell \cell \cell }\pard \widctlpar\intbl\adjustright {\f1\fs20 \row }\trowd \trgaph108\trrh211\trleft284\trkeep +\clvmrg\clvertalb\cltxlrtb \cellx993\clvmrg\clvertalt\clbrdrl\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \clbrdrr\brdrs\brdrw10 \cltxlrtb \cellx2268\clvmrg\clvertalt\cltxlrtb \cellx3414\clvmrg\clvertalt\clbrdrt\brdrs\brdrw10 \cltxlrtb \cellx4695 +\clvmrg\clvertalt\clbrdrt\brdrdashsm\brdrw10 \clbrdrl\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \clbrdrr\brdrs\brdrw10 \cltxlrtb \cellx6096\clvertalt\cltxlrtb \cellx6676\clvmrg\clvertalt\cltxlrtb \cellx7257\clvmrg\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrl +\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \clbrdrr\brdrs\brdrw10 \cltxlrtb \cellx8538\clvmrg\clvertalt\cltxlrtb \cellx9819\pard \qj\sa240\nowidctlpar\intbl\tx2835\adjustright {\f1\fs20 \cell \cell \cell \cell \cell \cell \cell \cell \cell }\pard +\widctlpar\intbl\adjustright {\f1\fs20 \row }\pard \qj\sa240\nowidctlpar\tx2835\adjustright { +\par Figure 5 RAM access in normal and shadow modes +\par In normal mode the RAM can be thought of as 44K from address &0000-&AFFF. The top 12K of this RAM from address &8000-&AFFF is paged into the memory map when required in place of the bottom 12K of the sideways ROM space, see 5.4.2. The remaining 20K of RAM + is set aside for the shadow screen memory, while it always exists, it is not available to the system in normal mode. The bank of 44K RAM we shall call "normal RAM". In normal mode, VDUSEL (IC36 pin 17) is always zero. +\par Any code executing anywhere within normal RAM in normal mode will always access normal RAM, it cannot access shadow RAM. +\par }{\fs24 \page }{In shadow mode the RAM can be thought of as 44K from address &0000-&AFFF, plus a parallel bank of 20K RAM from address &3000-&7FFF which we shall call "shadow RAM". As in n +ormal mode, the top 12K of normal RAM is paged into the memory when required. In the address range &3000-&7FFF the PAL (IC36) is able to switch between shadow RAM and normal RAM. It selects access to the shadow memory if a) shadow mode is on b) it detects + +a VDU driver and c) the operand address is between &3000 and &7FFF, the part of the memory map used by the screen. Otherwise it selects access to normal RAM. The machines logic is set to shadow mode when logic 1 is written to D7 at address &FE34, this cau +s +es pin 17 (VDUSEL) to go high. &FE34 is the address of a register in the PAL and when D7 is set any screen access through the VDU drivers will cause the PAL to switch in the shadow memory by making pin 12 (CPUSEL) high. In shadow mode, VDUSEL is always se +t, and CPUSEL is low to access normal RAM and high to access shadow RAM. +\par When the paged RAM is selected in shadow mode, the top 4K, &A000 to &AFFF, is programmed by the PAL (IC36) to have the attributes of VDU drivers. +\par Any code executing between &0000-&9FFF in shadow mode will always access normal RAM. +\par Any code executing from sideways RAM between &A000-&AFFF will access the shadow RAN (if selected) when the operand address is between &3000-&7FFF. This special attribute is not available to any other sideways memory, ROM or RAM. +\par }\pard\plain \s3\sa240\keepn\nowidctlpar\tx2835\outlinelevel2\adjustright \b\f2 {5.4.4 RAM circuitry +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {The 64K installed RAM is provided by eight 64K by 1 dynamic memory devices ICs 55, 56, 60, 61, 64, 65, 66, and 67. Figure 6 shows the RAM timing diagram. +\par }{\lang1024\cgrid {\shpgrp{\*\shpinst\shpleft1009\shptop169\shpright7777\shpbottom889\shpfhdr0\shpbxcolumn\shpbypara\shpwr3\shpwrk0\shpfblwtxt0\shpz2\shplid1177{\sp{\sn groupLeft}{\sv 2160}}{\sp{\sn groupTop}{\sv 9942}}{\sp{\sn groupRight}{\sv 8928}} +{\sp{\sn groupBottom}{\sv 10662}}{\sp{\sn fFlipH}{\sv 0}}{\sp{\sn fFlipV}{\sv 0}}{\shp{\*\shpinst\shplid1178{\sp{\sn relLeft}{\sv 2160}}{\sp{\sn relTop}{\sv 10656}}{\sp{\sn relRight}{\sv 3024}} +{\sp{\sn relBottom}{\sv 10656}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}}} +{\shp{\*\shpinst\shplid1179{\sp{\sn relLeft}{\sv 3023}}{\sp{\sn relTop}{\sv 9942}}{\sp{\sn relRight}{\sv 3167}}{\sp{\sn relBottom}{\sv 10662}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 1}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}} +{\sp{\sn fFillOK}{\sv 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fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}}}{\shp{\*\shpinst\shplid1183{\sp{\sn relLeft}{\sv 6479}}{\sp{\sn relTop}{\sv 9942}}{\sp{\sn relRight}{\sv 6623}}{\sp{\sn relBottom}{\sv 10662}}{\sp{\sn fRelFlipH}{\sv 0}} +{\sp{\sn fRelFlipV}{\sv 1}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}}}{\shp{\*\shpinst\shplid1184{\sp{\sn relLeft}{\sv 6623}}{\sp{\sn relTop}{\sv 9942}} +{\sp{\sn relRight}{\sv 8351}}{\sp{\sn relBottom}{\sv 9942}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}}} +{\shp{\*\shpinst\shplid1185{\sp{\sn relLeft}{\sv 8351}}{\sp{\sn relTop}{\sv 9942}}{\sp{\sn relRight}{\sv 8495}}{\sp{\sn relBottom}{\sv 10662}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}} +{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}}}{\shp{\*\shpinst\shplid1186{\sp{\sn relLeft}{\sv 8496}}{\sp{\sn relTop}{\sv 10656}}{\sp{\sn relRight}{\sv 8928}}{\sp{\sn relBottom}{\sv 10656}}{\sp{\sn fRelFlipH}{\sv 0}} +{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}}}}{\shprslt{\*\do\dobxcolumn\dobypara\dodhgt8194\dppolygon\dppolycount4\dpptx0\dppty0 +\dpptx6768\dppty0\dpptx6768\dppty720\dpptx0\dppty720\dpx1009\dpy169\dpxsize6768\dpysize720\dpfillfgcr255\dpfillfgcg255\dpfillfgcb255\dpfillbgcr255\dpfillbgcg255\dpfillbgcb255\dpfillpat1\dplinew15\dplinecor0\dplinecog0\dplinecob0}}}}{\fs32 +\par }{ }{\f1\fs32 2E +\par }{ +\par }{\lang1024\cgrid {\shpgrp{\*\shpinst\shpleft1008\shptop355\shpright7776\shpbottom1229\shpfhdr0\shpbxcolumn\shpbypara\shpwr3\shpwrk0\shpfblwtxt0\shpz1\shplid1187{\sp{\sn groupLeft}{\sv 2159}}{\sp{\sn groupTop}{\sv 11491}}{\sp{\sn groupRight}{\sv 8927}} +{\sp{\sn groupBottom}{\sv 12365}}{\sp{\sn fFlipH}{\sv 0}}{\sp{\sn fFlipV}{\sv 0}}{\shp{\*\shpinst\shplid1188{\sp{\sn relLeft}{\sv 2159}}{\sp{\sn relTop}{\sv 11491}}{\sp{\sn relRight}{\sv 3455}} +{\sp{\sn relBottom}{\sv 11491}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}}} +{\shp{\*\shpinst\shplid1189{\sp{\sn relLeft}{\sv 3455}}{\sp{\sn relTop}{\sv 11491}}{\sp{\sn relRight}{\sv 3599}}{\sp{\sn relBottom}{\sv 12355}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}} +{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}}}{\shp{\*\shpinst\shplid1190{\sp{\sn relLeft}{\sv 3599}}{\sp{\sn relTop}{\sv 12365}}{\sp{\sn relRight}{\sv 4463}}{\sp{\sn relBottom}{\sv 12365}}{\sp{\sn fRelFlipH}{\sv 0}} +{\sp{\sn fRelFlipV}{\sv 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fRelFlipH}{\sv 0}} +{\sp{\sn fRelFlipV}{\sv 1}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}}}{\shp{\*\shpinst\shplid1200{\sp{\sn relLeft}{\sv 8063}}{\sp{\sn relTop}{\sv 11491}} +{\sp{\sn relRight}{\sv 8927}}{\sp{\sn relBottom}{\sv 11491}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}}} +}{\shprslt{\*\do\dobxcolumn\dobypara\dodhgt8193\dppolygon\dppolycount4\dpptx0\dppty0\dpptx6768\dppty0\dpptx6768\dppty874\dpptx0\dppty874\dpx1008\dpy355\dpxsize6768\dpysize874 +\dpfillfgcr255\dpfillfgcg255\dpfillfgcb255\dpfillbgcr255\dpfillbgcg255\dpfillbgcb255\dpfillpat1\dplinew15\dplinecor0\dplinecog0\dplinecob0}}}}{\fs32 +\par }{\f1\fs32 RAS +\par }{ +\par +\par }{\lang1024\cgrid {\shpgrp{\*\shpinst\shpleft1153\shptop101\shpright7921\shpbottom1603\shpfhdr0\shpbxcolumn\shpbypara\shpwr3\shpwrk0\shpfblwtxt0\shpz3\shplid1201{\sp{\sn groupLeft}{\sv 2304}}{\sp{\sn groupTop}{\sv 13392}}{\sp{\sn groupRight}{\sv 9072}} +{\sp{\sn groupBottom}{\sv 14894}}{\sp{\sn fFlipH}{\sv 0}}{\sp{\sn fFlipV}{\sv 0}}{\shp{\*\shpinst\shplid1202{\sp{\sn relLeft}{\sv 2304}}{\sp{\sn relTop}{\sv 14112}}{\sp{\sn relRight}{\sv 3024}} +{\sp{\sn relBottom}{\sv 14112}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}}} +{\shp{\*\shpinst\shplid1203{\sp{\sn relLeft}{\sv 3024}}{\sp{\sn relTop}{\sv 13392}}{\sp{\sn relRight}{\sv 3168}}{\sp{\sn relBottom}{\sv 14112}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 1}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}} +{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}}}{\shp{\*\shpinst\shplid1204{\sp{\sn relLeft}{\sv 3168}}{\sp{\sn relTop}{\sv 13392}}{\sp{\sn relRight}{\sv 3888}}{\sp{\sn relBottom}{\sv 13392}}{\sp{\sn fRelFlipH}{\sv 0}} +{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}}}{\shp{\*\shpinst\shplid1205{\sp{\sn relLeft}{\sv 3888}}{\sp{\sn relTop}{\sv 13392}} +{\sp{\sn relRight}{\sv 4032}}{\sp{\sn relBottom}{\sv 14112}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}}} +{\shp{\*\shpinst\shplid1206{\sp{\sn relLeft}{\sv 4032}}{\sp{\sn relTop}{\sv 14112}}{\sp{\sn relRight}{\sv 4752}}{\sp{\sn relBottom}{\sv 14112}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}} +{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}}}{\shp{\*\shpinst\shplid1207{\sp{\sn relLeft}{\sv 4752}}{\sp{\sn relTop}{\sv 13392}}{\sp{\sn relRight}{\sv 4896}}{\sp{\sn relBottom}{\sv 14112}}{\sp{\sn fRelFlipH}{\sv 0}} +{\sp{\sn fRelFlipV}{\sv 1}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}}}{\shp{\*\shpinst\shplid1208{\sp{\sn relLeft}{\sv 4896}}{\sp{\sn relTop}{\sv 13392}} +{\sp{\sn relRight}{\sv 5616}}{\sp{\sn relBottom}{\sv 13392}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}}} +{\shp{\*\shpinst\shplid1209{\sp{\sn relLeft}{\sv 5616}}{\sp{\sn relTop}{\sv 13392}}{\sp{\sn relRight}{\sv 5760}}{\sp{\sn relBottom}{\sv 14112}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}} +{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}}}{\shp{\*\shpinst\shplid1210{\sp{\sn relLeft}{\sv 5760}}{\sp{\sn relTop}{\sv 14112}}{\sp{\sn relRight}{\sv 6480}}{\sp{\sn relBottom}{\sv 14112}}{\sp{\sn fRelFlipH}{\sv 0}} +{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}}}{\shp{\*\shpinst\shplid1211{\sp{\sn relLeft}{\sv 6480}}{\sp{\sn relTop}{\sv 13392}} +{\sp{\sn relRight}{\sv 6624}}{\sp{\sn relBottom}{\sv 14112}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 1}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}}} +{\shp{\*\shpinst\shplid1212{\sp{\sn relLeft}{\sv 6624}}{\sp{\sn relTop}{\sv 13392}}{\sp{\sn relRight}{\sv 7344}}{\sp{\sn relBottom}{\sv 13392}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}} +{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn 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0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}}}{\shp{\*\shpinst\shplid1216{\sp{\sn relLeft}{\sv 8352}}{\sp{\sn relTop}{\sv 13392}}{\sp{\sn relRight}{\sv 9072}}{\sp{\sn relBottom}{\sv 13392}}{\sp{\sn fRelFlipH}{\sv 0}} +{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}}}{\shp{\*\shpinst\shplid1217{\sp{\sn relLeft}{\sv 3023}}{\sp{\sn relTop}{\sv 14462}} +{\sp{\sn relRight}{\sv 3023}}{\sp{\sn relBottom}{\sv 14894}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}}} +{\shp{\*\shpinst\shplid1218{\sp{\sn relLeft}{\sv 4751}}{\sp{\sn relTop}{\sv 14462}}{\sp{\sn relRight}{\sv 4751}}{\sp{\sn relBottom}{\sv 14894}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}} +{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}}}{\shp{\*\shpinst\shplid1219{\sp{\sn relLeft}{\sv 6479}}{\sp{\sn relTop}{\sv 14462}}{\sp{\sn relRight}{\sv 6479}}{\sp{\sn relBottom}{\sv 14894}}{\sp{\sn fRelFlipH}{\sv 0}} +{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}}}{\shp{\*\shpinst\shplid1220{\sp{\sn relLeft}{\sv 8207}}{\sp{\sn relTop}{\sv 14462}} +{\sp{\sn relRight}{\sv 8207}}{\sp{\sn relBottom}{\sv 14894}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}}} +}{\shprslt{\*\do\dobxcolumn\dobypara\dodhgt8195\dppolygon\dppolycount4\dpptx0\dppty0\dpptx6768\dppty0\dpptx6768\dppty1502\dpptx0\dppty1502\dpx1153\dpy101\dpxsize6768\dpysize1502 +\dpfillfgcr255\dpfillfgcg255\dpfillfgcb255\dpfillbgcr255\dpfillbgcg255\dpfillbgcb255\dpfillpat1\dplinew15\dplinecor0\dplinecog0\dplinecob0}}}}{\fs32 +\par }{\f1\fs32 CAS +\par }{ +\par }{\fs24 }{\fs36 CPU\tab \tab VDU\tab \tab CPU +\par }{Figure 6 RAM timing diagram +\par \page The RAM control circuit is designed to work with either 128 or 256 refresh cycle DRAMs, refresh being provided by the 6845 CRTC (IC78) in conjunction with two ex-OR gates of IC63 and an AND gate of IC34. +\par The RAM is accessed at 4MHz, the CPU and VDU each having 2MHz access. +\par The address multiplexers for the VDU cycle are ICs 72, 73, 74, and 75. Various combinations of the inputs of these ICs are used depending on the screen mode in use. In particular, TELETEXT mode 7, with its own + character generator (IC59) is markedly different from the other seven bit-mapped modes 0-6. +\par The address multiplexers for the CPU cycle are ICs 50 and 51. +\par RAM is working (being addressed and strobed) the whole time., both during CPU and VDU phases, even wh +en not required (except for the purpose of refresh). But data to or from the RAM is only available to the CPU, when the data buffer IC49 is enabled. This occurs when any input to the NAND gate in half of IC40 goes low, that is when A15 is low (address bet +w +een &0000-&7FFF) or if the paged RAM signal from IC36 is low (address between &8000-&AFFF and paged RAM selected), or if the video processor (VIDPROC) is enabled (address &FE20). RAM is disabled when the VIDPROC is written to, by holding notCAS at logic 1 + (see IC23). +\par }\pard\plain \s2\sa240\keepn\nowidctlpar\tx2835\outlinelevel1\adjustright \b\f2\lang2057 {5.5 Disc interface +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {There are two floppy disc interfaces which can be fitted to the PCB, based on either the 8271 floppy disc controller for FM only, or the 1770 floppy disc controller for FM and MFM. + +\par }\pard\plain \s2\sa240\keepn\nowidctlpar\tx2835\outlinelevel1\adjustright \b\f2\lang2057 {5.5.1 8271 FDC +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {Two open collector buffer ICs + are used to drive the disc unit. A 7416 (hex inverter, IC8) is used to invert the "true" control signals output by the controller IC15. Two gates from a 7438 (quad NAND gate, IC7) generate the two drive select signals by combining the controller's drive +select lines with the load head signal (used as a motor control line). +\par Each data pulse from the drive triggers/retriggers a monostable pulse generator IC1. The pulse clears an R-S latch formed by two cross-coupled NAND gates (IC9), and clears the bit interv +al timer formed by two divide by sixteen circuits (IC2) and a NAND gate (IC9). If the bit interval exceeds the time determined by the bit intervaltimer then the latch will be set (DW=1). The 8271 monitors the latch (the data window) and the read data puls +es to decode the serial data stream. +\par If the latch is reset (DW = 0) when a data pulse occurs, the 8271 interprets the bit value as logic 1; conversely if DW = 1 then the data bit is a logic 0. Logic 0 bits are encoded as 8\'b5s between RD pulses, logic 1s as 4\'b5 +s, and each bit interval is 8\'b5s. +\par \page The bit interval timer is designed to detect an interval of approx. 6.5\'b5s. +\par Disc speed is measured by timing the interval between index pulses, which are nominally 200ms apart. One interval timer IC4 is used for both RDY0 +and RDY1. 16/13 MHz (1.2307MHz) is used to clock a binary counter (IC4). When all drives are off, the MOTOR signal will be high (off). Motor off forces both stages of IC3 to predefined states, IC3 pin 13 is high and IC3 pin 2 (notRDY) is high. A drive is +turned on when MOTOR goes low. IC3 can now be clocked by index pulses and so detect the state of the digital timer IC4. +\par If IC4 pin 11 goes high then the interval between index pulses is greater than 213ms (2^18*812.5ns), and the disc speed is too slow. If I +C4 pin 11 is still at logic 0 when an index pulse occurs then the disc speed is taken to be almost right, so that after one additional disc revolution the speed can be assumed within working limits. IC3 pin 13 is clocked low if IC4 pin 11 is low when an i +n +dex pulse occurs. If IC3 pin 3 is still low at the next index pulse then IC3 pin 2 will go low, indicating that the drive is ready. Diode D1 and resistor R2 OR the MOTOR signal and the state of IC4 pin 11. The OR function means that whenever IC4 pin 11 go +es high it will set IC3 pin 13, and the RDY generation sequence is returned to the beginning. Resetting IC3 by IC4 pin 11 avoids a false RDY if the drive is very slow, when IC4 pin 11 might go high then low between two index pulses. +\par Communication between the 8271 disc controller and the microprocessor occurs at two levels: +\par Commands to the disc controller are made by normal program controlled accesses to the I/O space between addresses &FE80 and &FE83. +\par Bytes of data transferred between the disc and the contro +ller are processed using an NMI interrupt routine which demands immediate action from the CPU. The interrupt program code accesses the 8271 at address &FE84; this address is for DACK controlled transfers. When a DACK controlled transfer is required the 82 +7 +1 generates an interrupt by setting pin 11 high (of IC15). The interrupt request is inverted by IC7, an open collector NAND gate, to become notNMI. NotNMI is a wire NOR signal which passes directly to the CPU notNMI input (IC42 pin 6) via an AND gate (IC3 +4). +\par Address decoding for the disc controller is done by three ICs. +\par IC22 pin 8 goes low when the CPU address is greater than &FC00, and so enables the I/O decoding logic. IC21 generates the notFDC signal which is low for address values &FE80 to &FE9F. The fi +nal decode is by IC28 which splits the notFDC space into blocks of four using the A2 address. IC28 pin 12 is low for &FE80 to &FE83 which is the notCE address for the 8271 disc controller. NotDACK is low for &FE84 to &FE87. Pin 15 of IC28 is he1d permanen +tly low (link S7 West) as 8271 interface timing is controlled by not2M through the notR and notW signals (from IC27). +\par }\pard\plain \s2\sa240\keepn\nowidctlpar\tx2835\outlinelevel1\adjustright \b\f2\lang2057 {\fs22 \page }{5.5.2 1770 FDC +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {The 1770 is expected to be the standard disc interface. A 1770 operates in either single density (FM) or double density (MF +M) mode, and has data separator and disc speed decision logic built in. A much simpler disc interface results: ICs 1, 2, 3, 4 and 9 are not needed. No drive select logic is incorporated in a 1770 so IC17 is fitted for this function. IC17 also latches two +control signals which are used to select between FM and MFM operation and to reset the 1770, both under program control. +\par The control register IC17 is a write only device which occupies the address space &FE80 to &FE83. IC23 gates the decoded address signal with notW (IC27 pin 6) to form the control register clock. +\par All 1770 registers are addressed in the range &FE84 to &FE87. +\par It can be seen that the 1770 controller and the 8271 controller address space has been swapped. This is to allow the disc system software to distinguish between the two devices. +\par Two interrupt signals come from a 1770, pins 27 and 28. The two interrupts are inverted and wi +re NORed on to the notNMI line by two parts of IC7 (quad NAND gate). Link S8 selects between the single interrupt of an 8271 and dual interrupt of a 1770. When a 1770 is fitted S8 must be made. For the 1770 option link S7 is made East, this incorporates n +o +t2M into the chip select signals and so defines the timing of data transfers between the disc controller and the CPU. Link S5 is available to allow program controlled suppression of 1770 disc controller interrupts (IC17 is not present when the 8271 is fit +ted). The disable function is not used at present so S5 is not fitted. +\par }\pard\plain \s2\sa240\keepn\nowidctlpar\tx2835\outlinelevel1\adjustright \b\f2\lang2057 {5.6 Display circuitry +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {Three display outputs are provided \endash RGB, composite video, and UHF. +\par }\pard\plain \s2\sa240\keepn\nowidctlpar\tx2835\outlinelevel1\adjustright \b\f2\lang2057 {5.6.1 RGB +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {Red, green and blue signals are produced by the video processor and are then buffered +by Q1, Q2, and Q3 to be fed to the DIN socket (SK3) at TTL type levels. The fourth signal required at the RGB output is a composite SYNC (CSYNC) generated from horizontal sync and vertical sync of the 6845. CSYNC polarity can be altered using link S27. Th +e 0V and +5V power supply also appears on SK3. +\par }\pard\plain \s2\sa240\keepn\nowidctlpar\tx2835\outlinelevel1\adjustright \b\f2\lang2057 {5.6.2 Composite video +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 { +Composite video is a summation of the three primaries (red green and blue) to give a grey scale, mixed with negative CSYNC. The order from darkest to lightest is: black, blue, red, green, +magenta, cyan, yellow, white. The grey scale is set by the resistor values R101, R104, and R108. These feed Q8 which produces a 1V peak to peak signal on BNC connector SK2. The chroma component described in 5.6.3 may be added to the composite video by mak +ing link S26. The voltage ratio of chroma to luminance is defined by C48. +\par }\pard\plain \s2\sa240\keepn\nowidctlpar\tx2835\outlinelevel1\adjustright \b\f2\lang2057 {\fs22 \page }{5.6.3 UHF +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {Red green and blue are summed by resistors R82, R84, and R93 and fed into Q6 to create a grey scaled luminance (or luma) signal. Diodes D12, D13, and D14 boost the luminanc +e level for colours to compress the grey scale. Resistors R107 and R138 mix the luma and negative CSYNC respectively while R139 and R146 trim the DC level of the "video" waveform fed to the UHF modulator. Chroma is added through C49. The modulator generat +es an amplitude modulated UHF signal on TV channel E36 (591.25MHz). +\par The chroma signal is an amplitude and phase modulated 4.4336MHz simulated sine wave which is added to the video signal. For neutral colours, white/black/grey, the chroma amplitude is zero. +For other colours the phase of the chroma signal determines the colour while the chroma amplitude fixes the colour strength. The chroma phase is measured, in the TV, against a reference set by locking to the (average) colour burst. A 17,734,475Hz (+/-100H +z +) oscillator is used to generate the colour subcarrier master clock. VC1 allows adjustment of the clock frequency. Two D type registers form a ring counter which generates two phase shifted 4.4336MHz signals (IC79 pins 6 and 9). All chroma signals are der +i +ved by mixing combinations of the two master chroma signals or their inverse with a bank of ex-OR gates. For PAL (Phase Alternation by Line) the chroma signal reference phase is shifted 90 degrees on alternate lines. An exclusive-OR gate (IC83) driven fro +m half of IC69 modifies one of the ring counter outputs to cause the required phase alternation. +\par For NTSC operation, link S28 can be changed to give a constant reference phase (IC83 pin 13 to 0v) \endash R92 must be removed for NTSC, and the crystal X2 must be 4 +times the colour carrier frequency of the NTSC broadcast standard (e.g. 14.318MHz for USA). +\par The chroma waveform phase and amplitude are selected by the red green and blue (RGB) signals from the video processor. RGB controls the six ex-OR gates (IC86 and IC +83) to direct the required phase(s) of 4.4336MHz to the NAND gate array (IC87 and IC90) and to enable the appropriate NAND gates. Resistors R85 to R92 mix the NAND gate outputs to form a single chroma signal, including the colour burst. R86 and R89 are us +e +d to match the DC level from the resistor mixing network for all colours, but not the colour burst. A crude low Q tuned circuit formed by L1 and C40 filters the chroma signal before it is buffered with the emitter follower Q9. R114 and R120 bias Q9 and al +s +o offer a suitable termination to the filter. Q9 then drives the signal mixing point to form the complete colour video signal used to drive the UHF modulator. The impedance of C49 (at 4.4336MHz) fixes the voltage ratio of chroma to luma in the modulator d +rive signal. C48 serves the same purpose, when link S26 is made, in mixing chroma into the video waveform available at SK2. +\par }\pard\plain \s2\sa240\keepn\nowidctlpar\tx2835\outlinelevel1\adjustright \b\f2\lang2057 {\fs22 \page }{5.7 CENTRONICS compatible printer interface +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {The computer can drive a centronics compatible printer through IC10, a 6522 VIA. Port A +of the VIA is configured as an 8-bit output port which is buffered by IC5 and fed to PL9. Printer strobe pulses are generated by a program sequence which toggles CA2 (IC10 pin 39) high-low-high. Strobe pulses are typically 4\'b5 +s wide. ACK from the printer is connected to CA1 (IC10 pin 40). ACK is pulsed low for approximately 5\'b5s by the printer when it is ready for the next character/byte transfer. +\par }\pard\plain \s2\sa240\keepn\nowidctlpar\tx2835\outlinelevel1\adjustright \b\f2\lang2057 {5.8 User port +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {Port B of IC10 offers eight individually programmable input/output lines, and two programmable control lines, connecting to PL10. +\par }\pard\plain \s2\sa240\keepn\nowidctlpar\tx2835\outlinelevel1\adjustright \b\f2\lang2057 {5.9 1MHz extension bus +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {The 1MHz bus is a fully buffered interface to the CPU via PL11, which operates with 1\'b5 +s transfer cycles. IC12 (bi-directional buffer) is enabled when either FRED or JIM is accessed (pages &FC and &FD). +These two pages are decoded by IC22 and IC28, with signals notFRED and not JIM appearing on pins 4 and 5 respectively of IC28. When either notFRED or not JIM goes low, the 1MHz bus enable goes low (IC34 pin11), and takes low an input of the NAND gate IC41 + thus causing a 1MHz CPU cycle. +\par NotFRED (IC28 pin 4) and notJIM (IC28 pin 5), along with R/notW (IC24 pin 10) and 1MHz bus enable (IC34 pin 11) are synchronised to the 1 MHz system clock (1M) by latching them in IC32. This ensures that no glitches occur on the 1MHz bus interface. +\par }\pard\plain \s2\sa240\keepn\nowidctlpar\tx2835\outlinelevel1\adjustright \b\f2\lang2057 {5.10 TUBE interface +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 { +The TUBE interface connects to a second processor via PL12. The signals present are the eight data lines, five address lines A0 to A4, R/notW, 2E, notRS and notIRQ. The data lines are buffered by IC14, and the ad +dress lines, R/notW and 2E are buffered by IC13. The data buffer IC14 is enabled when a TUBE address (&FEE0-&FEFF) is decoded by IC21, this enable signal (notTUBE) being fed also to the TUBE connector, PL12. +\par R11 is fitted so the computer OS can detect when there is no second processor present (or powered on). +\par }\pard\plain \s2\sa240\keepn\nowidctlpar\tx2835\outlinelevel1\adjustright \b\f2\lang2057 {\fs22 \page }{5.11 ECONET +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 { +ECONET is based around the 68B54 (IC81) advanced data link controller. IC81 performs the conversions between serial and parallel data, and generates the interrupt requests which are connec +ted to NMI. Each byte transfer between network and CPU is requested by an NMI. Interrupts can be disabled by making pin 4 IC23 low thereby setting the D-type (half of IC69), which is achieved by a read of &FE18. Reading this address returns the station ID + number which is set up on the links S23. Interrupts are enabled when pin 2 IC69 goes low (a read of &FE20), which, when clocked by not2E, resets the D-type. +\par Transmit data from the 68B54 is fed to a differential line driver circuit IC91, and then through SK +7 on to the twisted pair network cable. The differential drive voltages are, typically, 0.25V and 3V. A monostable (half of IC88) is used to time-out the ECONET line driver by taking pin 9 IC91 low after approximately 4.5s (longer than the time required t +o transmit a maximum length data packet). This is designed to prevent a single computer holding its driver on and thereby bringing the whole network down. +\par Receive data is decoded by a comparator circuit IC92 and fed into the 68B54. IC93, the collision detec +t circuitry, is not fitted because the software protocols should prevent any collision. Before transmission, the line is sampled to see if it is in use. If it is, the transmission is held up until a certain time after the line is first free again. This ti +me is dependent on the station ID and so will be different for every station on the line. When required collision detect may be installed by fitting components as shown on the circuit diagram, and breaking the link S29, a PCS copper link. +\par }\pard\plain \s2\sa240\keepn\nowidctlpar\tx2835\outlinelevel1\adjustright \b\f2\lang2057 {5.12 Cassette and RS423 ports +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 { +For both the cassette (SK5) and RS423 (SK4) interfaces, a 6850 asynchronous communications interface adaptor (ACIA) IC82 is used to buffer and serialise or deserialise the data. The serial processor IC85 contains two programmable baud rate gene +rators, a cassette data/clock separator, switching to select either RS423 or cassette operations, and also a circuit to synthesize a sinewave to be fed out to the cassette recorder. +\par Note that the receive bit rate for cassette operations is derived from the FSK signal not from the serial processor control register bits used when RS423 operation is selected. +\par IC18 divides the 16MHz clock signal by 13 (1.23 MHz) and this signal is divided + further within the serial processor to produce the synthesized 2400/1200Hz cassette record signal, and the bit rate clocks. Automatic motor control of an audio cassette recorder is achieved by using a small relay driven by transistor Q7 from the serial p +rocessor. +\par \page R66 and C30 provide the necessary timing elements for delay between receiving the high tone run-in signal and asserting the data carrier detect signal to the 6850. +\par The signal coming from the cassette recorder is buffered, filtered and shaped by three stages of the LM324 amplifier IC89. +\par The RS423 data in and data out signals and the request to send output RTS and clear to send input CTS signals are interfaced by ICs 94 and 95 which translate between TTL and standard RS423 signal levels +5V and -5V. +\par RS423 signals are compatible with the RS232 signals common in computer related equipment. +\par Selection of the cassette or RS423 for input and output is by bit 6 of the serial processor control register, bit 7 is for cassette motor control. Bits 0 to 2 control the transmit bit rate, while bits 3 to 5 set the RS423 receive bit rate. +\par }\pard\plain \s2\sa240\keepn\nowidctlpar\tx2835\outlinelevel1\adjustright \b\f2\lang2057 {5.13 Analogue to digital converter +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {The A to D circuit is based on a uPD7002 IC84, which can accept up to four analogue inputs, from SK6. The voltage reference is set by three silico +n diodes, D9, D10, and D11, which gives a typical full scale voltage of 1.8V. When a conversion is complete, the CPU is interrupted via CB1 of the 6522 (IC20 pin 18) which generates an IRQ (IC20 pin 21). +\par }\pard\plain \s2\sa240\keepn\nowidctlpar\tx2835\outlinelevel1\adjustright \b\f2\lang2057 {5.14 Audio circuitry +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {IC38 is a four-channel sound ge +nerator which can be programmed to vary the frequency and volume of three independent tone generators and the amplitude of a single noise generator. The sound signal is DC "restored" by mixing in a signal derived from the sound envelope. An inverting peak + +detector (IC47 D4 C15 etc.) derives the inverted sound envelope which is then summed with the sound signal in the ratio of 2:1. Part of IC47 forms a virtual earth summing amplifier which mixes the sound, its envelope, the external audio input and an optio +n +al speech signal into one audio channel. The audio is then filtered through a second order low pass filter (approximately 7kHz bandwidth) and applied to the volume control (optional) before final amplification by IC77 an LM386. IC77 drives the internal ke +yboard mounted 8 ohm speaker via PL15. Plug S20 allows fitting of a remote volume control, when no volume control is fitted a shunt is required on S20 (south) to enable the audio. +\par The audio output of the optional speech system is filtered by an operational +amplifier second order filter (cut-off frequency of 7kHz) before mixing in with the other audio signals. Speech is generated by an optional TMS5220 with TMS6100 (or equivalent) vocabulary "PHROM". +\par }\pard\plain \s2\sa240\keepn\nowidctlpar\tx2835\outlinelevel1\adjustright \b\f2\lang2057 {\b0\fs22 \page }{5.15 Keyboard +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {The keyboard circuit is given in figure 9.6 of the Appendix. The keyboard connects to the main PCB via PL13. +\par A 1MHz clock signal 1E is fed to a 74LS163 (IC1 on keyboard) binary counter, the outputs of which are decoded by a 7445 (IC3 on keyboard) decoder driver circuit. These outputs drive the rows +of the keyboard matrix, each row being driven in turn. If any key is depressed, an 8 input NAND (IC4 on keyboard) will produce an output when that row is strobed and this will interrupt the CPU through line CA2, pin 39 of IC20 on the main computer board. +T +he interrupt tells the computer to enter the key reading software. In order to discover which key was pressed, the CPU loads directly into the 74LS163 (IC1 on keyboard) the address of a key matrix row, allowing it to interrogate each row in turn. Also, th +e + CPU drives the 74LS251 data selector (IC2 on keyboard) with the 'column address' of a single key on the selected row. In this way, the processor can interrogate each individual key in turn until it discovers which one was depressed and caused the interru +pt. Once read, the keyboard assumes its free running mode. +\par }\pard\plain \s1\qj\sa240\nowidctlpar\tx2835\outlinelevel0\adjustright \b\f2 {\page 6 Upgrading the PCB +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {The following section gives instructions for adding extra hardware to upgrade the PCB for disc, ECONET, and speech. Dealers and service centers performing these upgrades must al +so conform to upgrade procedures and requirements as notified by their supplier, and should refer to any available information updates for latest details. +\par In the following section, items marked * may already be fitted to the board. +\par All ICs are inserted with their pin 1 facing the back of the computer. +\par }\pard\plain \s2\sa240\keepn\nowidctlpar\tx2835\outlinelevel1\adjustright \b\f2\lang2057 {6.1 1770 disc option +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {FM or MFM 5 1/4 inch floppy disc interface. +\par i) The following parts are required: +\par }\pard \qj\nowidctlpar\tx2835\adjustright { IC7 7438 (must not be 74LS38) +\par IC8 7416 or 7406 +\par IC16 1770 +\par IC17 74LS174 +\par +\par *R1 150R +\par *R5 150R +\par *R6 150R +\par *R7 150R +\par *R8 150R +\par *R14 3k3 +\par }\pard \qj\sa240\nowidctlpar\tx2835\adjustright { +\par The appropriate filing system ROM +\par ii) Insert the ICs listed above into the sockets which should be provided on the main circuit board. If any sockets are missing then solder in the correct DIL socket for that IC. Note: IC16 uses two 14-pin SIL sockets. +\par iii) Except on early boards, the resistors listed above will already be in position on the PCB. Check each one, and solder in any which are missing. +\par iv) Insert the filing system ROM into a vacant sideways ROM socket (IC 35, 44, 57, 62, or 68). +\par v) Make link S7 East with a shunt (probably already in this position), or tinned copper wire if molex pins not fitted. +\par vi) Make link S8 with a shunt (probably already in this position), or tinned copper wire if molex pins not fitted. +\par vii) Test using a PORT tester. +\par Note: the 1770 disc upgrade is usually carried out without soldering. +\par }\pard\plain \s2\sa240\keepn\nowidctlpar\tx2835\outlinelevel1\adjustright \b\f2\lang2057 {\fs22 \page }{6.2 8271 disc option +\par }\pard\plain \qj\ri4320\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {i) The following parts are required: +\par }\pard \qj\li142\nowidctlpar\tx2835\adjustright {IC1 74LS123 +\par IC2 74LS393 +\par IC3 4013B +\par IC4 4521B +\par IC7 7438 (must not be 74LS38) +\par IC8 7416 or 7406 +\par IC15 8271 +\par }\pard \qj\li180\nowidctlpar\tx2835\adjustright { +\par *R1 150 R +\par *R2 10k +\par *R3 1k +\par *R5 150R +\par *R6 150R +\par *R7 150R +\par *R8 150R +\par *R9 3k3 +\par *R10 3k3 +\par *R14 3k3 +\par +\par }\pard \qj\sa240\nowidctlpar\tx2835\adjustright {*C1 1n plate ceramic 2% +\par *D1 LN4148 +\par *16K ROM (DNFS) +\par ii) Insert the ICs listed above into the sockets which should be provided on the main circuit board. If any sockets are missing then solder in the correct DIL socket for that IC. Note: IC15 uses two 14-pin SIL sockets. +\par iii) Except on early boards, the resistors, capacitor and diode listed above will already be in position on the PCB. Check each one, and solder in any which are missing. +\par iv) Insert the filing system ROM (DNFS) into a vacant sideways ROM socket (IC 35, 44, 57, 62, or 68). +\par v) Make link S7 West with a shunt, or tinned copper wire if molex pins not fitted. +\par vi) Break link S8 by removing shunt (if fitted). +\par vii) Test using a PORT tester. +\par Note: If an 8271 disc interface is being fitted as a replacement for an existing 1770 disc interface, the following items must be removed from the PCB: +\par }\pard \qj\nowidctlpar\tx2835\adjustright {IC16 1770 +\par }\pard \qj\sa240\nowidctlpar\tx2835\adjustright {IC17 LS174 +\par Link S8 must be broken. +\par }{\fs24 \page +\par }\trowd \trgaph108\trleft142 \clvertalt\clbrdrt\brdrs\brdrw30 \clbrdrl\brdrs\brdrw30 \cltxlrtb \cellx711\clvertalt\clbrdrt\brdrs\brdrw30 \clbrdrb\brdrs\brdrw30 \cltxlrtb \cellx1384\clvertalt\clbrdrt\brdrs\brdrw30 \cltxlrtb \cellx1701\clvertalt\clbrdrt +\brdrs\brdrw30 \clbrdrb\brdrs\brdrw30 \cltxlrtb \cellx2377\clvertalt\clbrdrt\brdrs\brdrw30 \cltxlrtb \cellx2694\clvertalt\clbrdrt\brdrs\brdrw30 \clbrdrb\brdrs\brdrw30 \cltxlrtb \cellx3369\clvertalt\clbrdrt\brdrs\brdrw30 \cltxlrtb \cellx3938\clvertalt +\clbrdrt\brdrs\brdrw30 \cltxlrtb \cellx4645\clvertalt\clbrdrt\brdrs\brdrw30 \cltxlrtb \cellx4924\clvertalt\clbrdrt\brdrs\brdrw30 \cltxlrtb \cellx5212\clvertalt\clbrdrt\brdrs\brdrw30 \cltxlrtb \cellx5637\clvertalt\clbrdrt\brdrs\brdrw30 \cltxlrtb \cellx6206 +\clvertalt\clbrdrt\brdrs\brdrw30 \cltxlrtb \cellx6775\clvertalt\clbrdrt\brdrs\brdrw30 \cltxlrtb \cellx7196\clvertalt\clbrdrt\brdrs\brdrw30 \cltxlrtb \cellx7480\clvertalt\clbrdrt\brdrs\brdrw30 \cltxlrtb \cellx7763\clvertalt\clbrdrt\brdrs\brdrw30 \cltxlrtb +\cellx8472\clvertalt\clbrdrt\brdrs\brdrw30 \cltxlrtb \cellx8897\clvertalt\clbrdrt\brdrs\brdrw30 \cltxlrtb \cellx9466\clvertalt\clbrdrt\brdrs\brdrw30 \cltxlrtb \cellx9889\clvertalt\clbrdrt\brdrs\brdrw30 \cltxlrtb \cellx10173\pard +\qj\li34\sa240\nowidctlpar\intbl\tx2835\adjustright {\lang1024\cgrid {\shp{\*\shpinst\shpleft1009\shptop496\shpright1122\shpbottom609\shpfhdr0\shpbxcolumn\shpbypara\shpwr3\shpwrk0\shpfblwtxt0\shpz38\shplid1221 +{\sp{\sn shapeType}{\sv 3}}{\sp{\sn fFlipH}{\sv 0}}{\sp{\sn fFlipV}{\sv 0}}}{\shprslt{\*\do\dobxcolumn\dobypara\dodhgt8230\dpellipse\dpx1009\dpy496\dpxsize113\dpysize113 +\dpfillfgcr255\dpfillfgcg255\dpfillfgcb255\dpfillbgcr255\dpfillbgcg255\dpfillbgcb255\dpfillpat1\dplinew15\dplinecor0\dplinecog0\dplinecob0}}} +{\shp{\*\shpinst\shpleft2017\shptop496\shpright2130\shpbottom609\shpfhdr0\shpbxcolumn\shpbypara\shpwr3\shpwrk0\shpfblwtxt0\shpz39\shplid1222 +{\sp{\sn shapeType}{\sv 3}}{\sp{\sn fFlipH}{\sv 0}}{\sp{\sn fFlipV}{\sv 0}}}{\shprslt{\*\do\dobxcolumn\dobypara\dodhgt8231\dpellipse\dpx2017\dpy496\dpxsize113\dpysize113 +\dpfillfgcr255\dpfillfgcg255\dpfillfgcb255\dpfillbgcr255\dpfillbgcg255\dpfillbgcb255\dpfillpat1\dplinew15\dplinecor0\dplinecog0\dplinecob0}}} +{\shp{\*\shpinst\shpleft3025\shptop496\shpright3138\shpbottom609\shpfhdr0\shpbxcolumn\shpbypara\shpwr3\shpwrk0\shpfblwtxt0\shpz40\shplid1223 +{\sp{\sn shapeType}{\sv 3}}{\sp{\sn fFlipH}{\sv 0}}{\sp{\sn fFlipV}{\sv 0}}}{\shprslt{\*\do\dobxcolumn\dobypara\dodhgt8232\dpellipse\dpx3025\dpy496\dpxsize113\dpysize113 +\dpfillfgcr255\dpfillfgcg255\dpfillfgcb255\dpfillbgcr255\dpfillbgcg255\dpfillbgcb255\dpfillpat1\dplinew15\dplinecor0\dplinecog0\dplinecob0}}}}{\f0\fs24 \cell }\pard \qj\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell \cell \cell \cell \cell +\cell \cell \cell \cell \cell \cell \cell \cell \cell \cell }\pard \qj\ri-108\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard \qj\ri-106\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard \qj\sa240\nowidctlpar\intbl +\tx2835\adjustright {\f0\fs24 \cell \cell }\pard \qj\li-108\ri-108\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard \widctlpar\intbl\adjustright {\f0\fs24 \row }\trowd \trgaph108\trleft142\trkeep \clvertalt\clbrdrl\brdrs\brdrw30 +\cltxlrtb \cellx711\clvmgf\clvertalb\clbrdrl\brdrs\brdrw30 \clbrdrr\brdrs\brdrw30 \cltxlrtb \cellx1384\clvertalt\cltxlrtb \cellx1701\clvmgf\clvertalb\clbrdrl\brdrs\brdrw30 \clbrdrr\brdrs\brdrw30 \cltxlrtb \cellx2377\clvertalt\cltxlrtb \cellx2694 +\clvmgf\clvertalb\clbrdrl\brdrs\brdrw30 \clbrdrr\brdrs\brdrw30 \cltxlrtb \cellx3369\clvertalt\cltxlrtb \cellx3938\clvertalt\cltxlrtb \cellx4645\clvertalt\cltxlrtb \cellx4924\clvertalt\cltxlrtb \cellx5212\clvertalt\cltxlrtb \cellx5637\clvertalt\cltxlrtb +\cellx6206\clvertalt\cltxlrtb \cellx6775\clvertalt\cltxlrtb \cellx7196\clvertalt\cltxlrtb \cellx7480\clvertalt\cltxlrtb \cellx7763\clvertalt\cltxlrtb \cellx8472\clvertalt\cltxlrtb \cellx8897\clvertalt\cltxlrtb \cellx9466\clvertalt\cltxlrtb \cellx9889 +\clvertalt\cltxlrtb \cellx10173\pard \qj\li34\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard \qj\ri-108\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 IC62\cell }\pard \qj\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 +\cell }\pard \qj\ri-108\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 IC68\cell }\pard \qj\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard \qc\li-108\ri-108\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 OS/ +\par }\pard \qc\li-108\ri-141\nowidctlpar\intbl\tx2835\adjustright {\f0\fs20 BASIC +\par }\pard \qc\li-108\ri-141\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 IC71\cell }\pard \qj\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell \cell \cell \cell \cell \cell \cell \cell \cell \cell }\pard \qj\ri-108\sa240\nowidctlpar\intbl +\tx2835\adjustright {\f0\fs24 \cell }\pard \qj\ri-106\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard \qj\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell \cell }\pard \qj\li-108\ri-108\sa240\nowidctlpar\intbl +\tx2835\adjustright {\f0\fs24 \cell }\pard \widctlpar\intbl\adjustright {\f0\fs24 \row }\trowd \trgaph108\trrh255\trleft142\trkeep \clvmgf\clvertalt\clbrdrl\brdrs\brdrw30 \cltxlrtb \cellx711\clvmrg\clvertalt\clbrdrl\brdrs\brdrw30 \clbrdrr\brdrs\brdrw30 +\cltxlrtb \cellx1384\clvmgf\clvertalt\cltxlrtb \cellx1701\clvmrg\clvertalt\clbrdrl\brdrs\brdrw30 \clbrdrr\brdrs\brdrw30 \cltxlrtb \cellx2377\clvmgf\clvertalt\cltxlrtb \cellx2694\clvmrg\clvertalt\clbrdrl\brdrs\brdrw30 \clbrdrr\brdrs\brdrw30 \cltxlrtb +\cellx3369\clvmgf\clvertalt\cltxlrtb \cellx3938\clvmgf\clvertalt\cltxlrtb \cellx4645\clvmgf\clvertalt\cltxlrtb \cellx4924\clvmgf\clvertalt\cltxlrtb \cellx5212\clvmgf\clvertalt\cltxlrtb \cellx5637\clvmgf\clvertalt\cltxlrtb \cellx6206 +\clvmgf\clvertalt\cltxlrtb \cellx6775\clvertalt\cltxlrtb \cellx7480\clvmgf\clvertalt\cltxlrtb \cellx7763\clvmgf\clvertalt\cltxlrtb \cellx8472\clvmgf\clvertalt\cltxlrtb \cellx8897\clvmgf\clvertalt\cltxlrtb \cellx9466\clvmgf\clvertalt\cltxlrtb \cellx9889 +\clvmgf\clvertalt\cltxlrtb \cellx10173\pard \qj\li34\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard \qj\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell \cell \cell \cell \cell \cell \cell \cell \cell \cell \cell \cell }\pard +\qj\li-108\ri-108\nowidctlpar\intbl\tx2835\adjustright {\f0\fs20 (WEST)\cell }\pard \qj\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard \qj\ri-108\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard +\qj\ri-106\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard \qj\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell \cell }\pard \qj\li-108\ri-108\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard +\widctlpar\intbl\adjustright {\f0\fs24 \row }\trowd \trgaph108\trrh255\trleft142\trkeep \clvmrg\clvertalt\clbrdrl\brdrs\brdrw30 \cltxlrtb \cellx711\clvmrg\clvertalt\clbrdrl\brdrs\brdrw30 \clbrdrr\brdrs\brdrw30 \cltxlrtb \cellx1384 +\clvmrg\clvertalt\cltxlrtb \cellx1701\clvmrg\clvertalt\clbrdrl\brdrs\brdrw30 \clbrdrr\brdrs\brdrw30 \cltxlrtb \cellx2377\clvmrg\clvertalt\cltxlrtb \cellx2694\clvmrg\clvertalt\clbrdrl\brdrs\brdrw30 \clbrdrr\brdrs\brdrw30 \cltxlrtb \cellx3369 +\clvmrg\clvertalt\cltxlrtb \cellx3938\clvmrg\clvertalt\cltxlrtb \cellx4645\clvmrg\clvertalt\cltxlrtb \cellx4924\clvmrg\clvertalt\cltxlrtb \cellx5212\clvmrg\clvertalt\cltxlrtb \cellx5637\clvmrg\clvertalt\cltxlrtb \cellx6206\clvmrg\clvertalt\cltxlrtb +\cellx6775\clvertalt\clbrdrt\brdrs\brdrw20 \clbrdrl\brdrs\brdrw20 \clbrdrb\brdrs\brdrw20 \clbrdrr\brdrs\brdrw20 \clcbpat1\cltxlrtb \cellx7196\clvertalt\clbrdrt\brdrs\brdrw20 \clbrdrb\brdrs\brdrw20 \clbrdrr\brdrs\brdrw20 \cltxlrtb \cellx7480 +\clvmrg\clvertalt\cltxlrtb \cellx7763\clvmrg\clvertalt\cltxlrtb \cellx8472\clvmrg\clvertalt\cltxlrtb \cellx8897\clvmrg\clvertalt\cltxlrtb \cellx9466\clvmrg\clvertalt\cltxlrtb \cellx9889\clvmrg\clvertalt\cltxlrtb \cellx10173\pard +\qj\li34\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard \qj\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell \cell \cell \cell \cell \cell \cell \cell \cell \cell \cell \cell }\pard \qj\nowidctlpar\intbl\tx2835\adjustright { +\f0\fs24 \cell }\pard \qj\li-108\ri-108\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard \qj\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard \qj\ri-108\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard +\qj\ri-106\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard \qj\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell \cell }\pard \qj\li-108\ri-108\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard +\widctlpar\intbl\adjustright {\f0\fs24 \row }\trowd \trgaph108\trleft142\trkeep \clvertalt\clbrdrl\brdrs\brdrw30 \cltxlrtb \cellx711\clvmrg\clvertalt\clbrdrl\brdrs\brdrw30 \clbrdrb\brdrs\brdrw30 \clbrdrr\brdrs\brdrw30 \cltxlrtb \cellx1384 +\clvertalt\cltxlrtb \cellx1701\clvmrg\clvertalt\clbrdrl\brdrs\brdrw30 \clbrdrb\brdrs\brdrw30 \clbrdrr\brdrs\brdrw30 \cltxlrtb \cellx2377\clvertalt\cltxlrtb \cellx2694\clvmrg\clvertalt\clbrdrl\brdrs\brdrw30 \clbrdrb\brdrs\brdrw30 \clbrdrr\brdrs\brdrw30 +\cltxlrtb \cellx3369\clvertalt\cltxlrtb \cellx3938\clvertalt\cltxlrtb \cellx4645\clvertalt\cltxlrtb \cellx4924\clvertalt\cltxlrtb \cellx5212\clvertalt\cltxlrtb \cellx5637\clvertalt\cltxlrtb \cellx6206\clvertalt\cltxlrtb \cellx6775\clvertalt\cltxlrtb +\cellx7196\clvertalt\cltxlrtb \cellx7480\clvertalt\cltxlrtb \cellx7763\clvertalt\cltxlrtb \cellx8472\clvertalt\cltxlrtb \cellx8897\clvertalt\cltxlrtb \cellx9466\clvertalt\cltxlrtb \cellx9889\clvertalt\cltxlrtb \cellx10173\pard +\qj\li34\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard \qj\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell \cell \cell \cell \cell \cell \cell \cell \cell \cell \cell \cell }\pard \qj\ri-108\sa240\nowidctlpar\intbl +\tx2835\adjustright {\f0\fs24 S7\cell }\pard \qj\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell \cell }\pard \qj\ri-108\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard \qj\ri-106\sa240\nowidctlpar\intbl\tx2835\adjustright { +\f0\fs24 \cell }\pard \qj\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell \cell }\pard \qj\li-108\ri-108\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard \widctlpar\intbl\adjustright {\f0\fs24 \row }\trowd \trgaph108\trleft142 +\clvertalt\clbrdrl\brdrs\brdrw30 \cltxlrtb \cellx711\clvertalt\cltxlrtb \cellx1384\clvertalt\cltxlrtb \cellx1701\clvertalt\cltxlrtb \cellx2377\clvertalt\cltxlrtb \cellx2694\clvertalt\cltxlrtb \cellx3369\clvertalt\cltxlrtb \cellx3938\clvertalt\cltxlrtb +\cellx4645\clvertalt\cltxlrtb \cellx4924\clvertalt\cltxlrtb \cellx5212\clvertalt\cltxlrtb \cellx5637\clvertalt\cltxlrtb \cellx6206\clvertalt\cltxlrtb \cellx6775\clvertalt\cltxlrtb \cellx7196\clvertalt\cltxlrtb \cellx7480\clvertalt\cltxlrtb \cellx7763 +\clvertalt\cltxlrtb \cellx8472\clvertalt\cltxlrtb \cellx8897\clvertalt\cltxlrtb \cellx9466\clvertalt\cltxlrtb \cellx9889\clvertalt\cltxlrtb \cellx10173\pard \qj\li34\sa240\nowidctlpar\intbl\tx2835\adjustright {\lang1024\cgrid +{\shp{\*\shpinst\shpleft3025\shptop507\shpright3138\shpbottom620\shpfhdr0\shpbxcolumn\shpbypara\shpwr3\shpwrk0\shpfblwtxt0\shpz43\shplid1224 +{\sp{\sn shapeType}{\sv 3}}{\sp{\sn fFlipH}{\sv 0}}{\sp{\sn fFlipV}{\sv 0}}}{\shprslt{\*\do\dobxcolumn\dobypara\dodhgt8235\dpellipse\dpx3025\dpy507\dpxsize113\dpysize113 +\dpfillfgcr255\dpfillfgcg255\dpfillfgcb255\dpfillbgcr255\dpfillbgcg255\dpfillbgcb255\dpfillpat1\dplinew15\dplinecor0\dplinecog0\dplinecob0}}} +{\shp{\*\shpinst\shpleft2017\shptop507\shpright2130\shpbottom620\shpfhdr0\shpbxcolumn\shpbypara\shpwr3\shpwrk0\shpfblwtxt0\shpz42\shplid1225 +{\sp{\sn shapeType}{\sv 3}}{\sp{\sn fFlipH}{\sv 0}}{\sp{\sn fFlipV}{\sv 0}}}{\shprslt{\*\do\dobxcolumn\dobypara\dodhgt8234\dpellipse\dpx2017\dpy507\dpxsize113\dpysize113 +\dpfillfgcr255\dpfillfgcg255\dpfillfgcb255\dpfillbgcr255\dpfillbgcg255\dpfillbgcb255\dpfillpat1\dplinew15\dplinecor0\dplinecog0\dplinecob0}}} +{\shp{\*\shpinst\shpleft1009\shptop507\shpright1122\shpbottom620\shpfhdr0\shpbxcolumn\shpbypara\shpwr3\shpwrk0\shpfblwtxt0\shpz41\shplid1226 +{\sp{\sn shapeType}{\sv 3}}{\sp{\sn fFlipH}{\sv 0}}{\sp{\sn fFlipV}{\sv 0}}}{\shprslt{\*\do\dobxcolumn\dobypara\dodhgt8233\dpellipse\dpx1009\dpy507\dpxsize113\dpysize113 +\dpfillfgcr255\dpfillfgcg255\dpfillfgcb255\dpfillbgcr255\dpfillbgcg255\dpfillbgcb255\dpfillpat1\dplinew15\dplinecor0\dplinecog0\dplinecob0}}}}{\f0\fs24 \cell }\pard \qj\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell \cell \cell \cell \cell +\cell \cell \cell \cell \cell \cell \cell \cell \cell \cell }\pard \qj\ri-108\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard \qj\ri-106\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard \qj\sa240\nowidctlpar\intbl +\tx2835\adjustright {\f0\fs24 \cell \cell }\pard \qj\li-108\ri-108\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard \widctlpar\intbl\adjustright {\f0\fs24 \row }\trowd \trgaph108\trleft142\trkeep \clvertalt\clbrdrl\brdrs\brdrw30 +\cltxlrtb \cellx711\clvmgf\clvertalb\clbrdrt\brdrs\brdrw30 \clbrdrl\brdrs\brdrw30 \clbrdrb\brdrs\brdrw30 \clbrdrr\brdrs\brdrw30 \cltxlrtb \cellx1384\clvertalt\cltxlrtb \cellx1701\clvmgf\clvertalb\clbrdrt\brdrs\brdrw30 \clbrdrl\brdrs\brdrw30 \clbrdrb +\brdrs\brdrw30 \clbrdrr\brdrs\brdrw30 \cltxlrtb \cellx2377\clvertalt\cltxlrtb \cellx2694\clvmgf\clvertalb\clbrdrt\brdrs\brdrw30 \clbrdrl\brdrs\brdrw30 \clbrdrb\brdrs\brdrw30 \clbrdrr\brdrs\brdrw30 \cltxlrtb \cellx3369\clvertalt\cltxlrtb \cellx3938 +\clvertalt\cltxlrtb \cellx4645\clvertalt\cltxlrtb \cellx4924\clvertalt\cltxlrtb \cellx5212\clvertalt\cltxlrtb \cellx5637\clvertalt\cltxlrtb \cellx6206\clvertalt\cltxlrtb \cellx6775\clvertalt\cltxlrtb \cellx7196\clvertalt\cltxlrtb \cellx7480 +\clvertalt\cltxlrtb \cellx7763\clvertalt\cltxlrtb \cellx8472\clvertalt\cltxlrtb \cellx8897\clvertalt\cltxlrtb \cellx9466\clvertalt\cltxlrtb \cellx9889\clvertalt\cltxlrtb \cellx10173\pard \qj\li34\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell +}\pard \qj\ri-108\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 IC35\cell }\pard \qj\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard \qj\ri-141\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 IC44\cell }\pard +\qj\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard \qj\ri-141\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 IC57\cell }\pard \qj\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell \cell \cell \cell \cell \cell \cell +\cell \cell \cell }\pard \qj\ri-108\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard \qj\ri-106\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard \qj\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell \cell }\pard +\qj\li-108\ri-108\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard \widctlpar\intbl\adjustright {\f0\fs24 \row }\trowd \trgaph108\trleft142\trkeep \clvertalt\clbrdrl\brdrs\brdrw30 \cltxlrtb \cellx711\clvmrg\clvertalt\clbrdrl +\brdrs\brdrw30 \clbrdrb\brdrs\brdrw30 \clbrdrr\brdrs\brdrw30 \cltxlrtb \cellx1384\clvertalt\cltxlrtb \cellx1701\clvmrg\clvertalt\clbrdrl\brdrs\brdrw30 \clbrdrb\brdrs\brdrw30 \clbrdrr\brdrs\brdrw30 \cltxlrtb \cellx2377\clvertalt\cltxlrtb \cellx2694 +\clvmrg\clvertalt\clbrdrl\brdrs\brdrw30 \clbrdrb\brdrs\brdrw30 \clbrdrr\brdrs\brdrw30 \cltxlrtb \cellx3369\clvertalt\cltxlrtb \cellx3938\clvertalt\cltxlrtb \cellx4645\clvertalt\cltxlrtb \cellx4924\clvertalt\cltxlrtb \cellx5212\clvertalt\cltxlrtb +\cellx5637\clvertalt\cltxlrtb \cellx6206\clvertalt\cltxlrtb \cellx6775\clvertalt\cltxlrtb \cellx7196\clvertalt\cltxlrtb \cellx7480\clvertalt\cltxlrtb \cellx7763\clvertalt\cltxlrtb \cellx8472\clvertalt\cltxlrtb \cellx8897\clvertalt\cltxlrtb \cellx9466 +\clvertalt\cltxlrtb \cellx9889\clvertalt\cltxlrtb \cellx10173\pard \qj\li34\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard \qj\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell \cell \cell \cell \cell \cell \cell \cell \cell +\cell \cell \cell \cell \cell \cell }\pard \qj\ri-108\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard \qj\ri-106\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard \qj\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 +\cell \cell }\pard \qj\li-108\ri-108\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard \widctlpar\intbl\adjustright {\f0\fs24 \row }\trowd \trgaph108\trleft142\trkeep \clvertalt\clbrdrl\brdrs\brdrw30 \cltxlrtb \cellx711\clvmrg\clvertalt +\clbrdrl\brdrs\brdrw30 \clbrdrb\brdrs\brdrw30 \clbrdrr\brdrs\brdrw30 \cltxlrtb \cellx1384\clvertalt\cltxlrtb \cellx1701\clvmrg\clvertalt\clbrdrl\brdrs\brdrw30 \clbrdrb\brdrs\brdrw30 \clbrdrr\brdrs\brdrw30 \cltxlrtb \cellx2377\clvertalt\cltxlrtb \cellx2694 +\clvmrg\clvertalt\clbrdrl\brdrs\brdrw30 \clbrdrb\brdrs\brdrw30 \clbrdrr\brdrs\brdrw30 \cltxlrtb \cellx3369\clvertalt\cltxlrtb \cellx3938\clvertalt\cltxlrtb \cellx4645\clvertalt\cltxlrtb \cellx4924\clvertalt\cltxlrtb \cellx5212\clvmgf\clvertalt\clbrdrt +\brdrs\brdrw30 \clbrdrl\brdrs\brdrw30 \clbrdrb\brdrs\brdrw30 \clbrdrr\brdrs\brdrw30 \cltxbtlr \cellx5637\clvertalt\cltxlrtb \cellx6206\clvertalt\cltxlrtb \cellx6775\clvmgf\clvertalt\clbrdrt\brdrs\brdrw30 \clbrdrl\brdrs\brdrw30 \clbrdrb\brdrs\brdrw30 +\clbrdrr\brdrs\brdrw30 \cltxbtlr \cellx7196\clvertalt\cltxlrtb \cellx7480\clvertalt\cltxlrtb \cellx7763\clvertalt\cltxlrtb \cellx8472\clvmgf\clvertalt\clbrdrt\brdrs\brdrw30 \clbrdrl\brdrs\brdrw30 \clbrdrb\brdrs\brdrw30 \clbrdrr\brdrs\brdrw30 \cltxbtlr +\cellx8897\clvertalt\cltxlrtb \cellx9466\clvertalt\cltxlrtb \cellx9889\clvertalt\clbrdrt\brdrs\brdrw20 \clbrdrl\brdrs\brdrw20 \clbrdrb\brdrs\brdrw20 \clbrdrr\brdrs\brdrw20 \clcbpat13\cltxlrtb \cellx10173\pard \qj\li34\sa240\nowidctlpar\intbl +\tx2835\adjustright {\lang1024\cgrid {\shp{\*\shpinst\shpleft8641\shptop21\shpright8754\shpbottom134\shpfhdr0\shpbxcolumn\shpbypara\shpwr3\shpwrk0\shpfblwtxt0\shpz46\shplid1227 +{\sp{\sn shapeType}{\sv 3}}{\sp{\sn fFlipH}{\sv 0}}{\sp{\sn fFlipV}{\sv 0}}}{\shprslt{\*\do\dobxcolumn\dobypara\dodhgt8238\dpellipse\dpx8641\dpy21\dpxsize113\dpysize113 +\dpfillfgcr255\dpfillfgcg255\dpfillfgcb255\dpfillbgcr255\dpfillbgcg255\dpfillbgcb255\dpfillpat1\dplinew15\dplinecor0\dplinecog0\dplinecob0}}} +{\shp{\*\shpinst\shpleft6913\shptop21\shpright7026\shpbottom134\shpfhdr0\shpbxcolumn\shpbypara\shpwr3\shpwrk0\shpfblwtxt0\shpz45\shplid1228 +{\sp{\sn shapeType}{\sv 3}}{\sp{\sn fFlipH}{\sv 0}}{\sp{\sn fFlipV}{\sv 0}}}{\shprslt{\*\do\dobxcolumn\dobypara\dodhgt8237\dpellipse\dpx6913\dpy21\dpxsize113\dpysize113 +\dpfillfgcr255\dpfillfgcg255\dpfillfgcb255\dpfillbgcr255\dpfillbgcg255\dpfillbgcb255\dpfillpat1\dplinew15\dplinecor0\dplinecog0\dplinecob0}}} +{\shp{\*\shpinst\shpleft5329\shptop21\shpright5442\shpbottom134\shpfhdr0\shpbxcolumn\shpbypara\shpwr3\shpwrk0\shpfblwtxt0\shpz44\shplid1229 +{\sp{\sn shapeType}{\sv 3}}{\sp{\sn fFlipH}{\sv 0}}{\sp{\sn fFlipV}{\sv 0}}}{\shprslt{\*\do\dobxcolumn\dobypara\dodhgt8236\dpellipse\dpx5329\dpy21\dpxsize113\dpysize113 +\dpfillfgcr255\dpfillfgcg255\dpfillfgcb255\dpfillbgcr255\dpfillbgcg255\dpfillbgcb255\dpfillpat1\dplinew15\dplinecor0\dplinecog0\dplinecob0}}}}{\f0\fs24 \cell }\pard \qj\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell \cell \cell \cell \cell +\cell \cell \cell \cell }\pard \qj\li113\ri113\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 IC9 74LS00\cell }\pard \qj\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell \cell }\pard \qj\li113\ri113\sa240\nowidctlpar\intbl +\tx2835\adjustright {\f0\fs24 IC3 4013B\cell }\pard \qj\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell \cell }\pard \qj\ri-108\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard \qj\li113\ri-106\sa240\nowidctlpar\intbl +\tx2835\adjustright {\f0\fs24 IC4 4521B\cell }\pard \qj\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard \qj\li-108\ri-108\nowidctlpar\intbl\tx2835\adjustright {\f0 R10 +\par 3k3\cell }\pard \qj\li-108\ri-108\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard \widctlpar\intbl\adjustright {\f0\fs24 \row }\trowd \trgaph108\trleft142\trkeep \clvertalt\clbrdrl\brdrs\brdrw30 \cltxlrtb \cellx711\clvertalt\cltxlrtb +\cellx1384\clvertalt\cltxlrtb \cellx1701\clvertalt\cltxlrtb \cellx2377\clvertalt\cltxlrtb \cellx2694\clvertalt\cltxlrtb \cellx3369\clvertalt\cltxlrtb \cellx3938\clvertalt\cltxlrtb \cellx4645\clvertalt\clbrdrt\brdrs\brdrw20 \clbrdrl\brdrs\brdrw20 \clbrdrb +\brdrs\brdrw20 \clbrdrr\brdrs\brdrw20 \clcbpat13\cltxlrtb \cellx4924\clvertalt\cltxlrtb \cellx5212\clvmrg\clvertalt\clbrdrl\brdrs\brdrw30 \clbrdrb\brdrs\brdrw30 \clbrdrr\brdrs\brdrw30 \cltxlrtb \cellx5637\clvertalt\cltxlrtb \cellx6206\clvertalt\cltxlrtb +\cellx6775\clvmrg\clvertalt\clbrdrl\brdrs\brdrw30 \clbrdrb\brdrs\brdrw30 \clbrdrr\brdrs\brdrw30 \cltxlrtb \cellx7196\clvertalt\cltxlrtb \cellx7480\clvertalt\cltxlrtb \cellx7763\clvertalt\cltxlrtb \cellx8472\clvmrg\clvertalt\clbrdrl\brdrs\brdrw30 \clbrdrb +\brdrs\brdrw30 \clbrdrr\brdrs\brdrw30 \cltxlrtb \cellx8897\clvertalt\cltxlrtb \cellx9466\clvertalt\cltxlrtb \cellx9889\clvertalt\cltxlrtb \cellx10173\pard \qj\li34\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard +\qj\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell \cell \cell \cell \cell \cell }\pard \qj\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 R9 +\par 3k3\cell }\pard \qj\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell \cell \cell \cell \cell \cell \cell \cell }\pard \qj\ri-108\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard \qj\ri-106\sa240\nowidctlpar\intbl +\tx2835\adjustright {\f0\fs24 \cell }\pard \qj\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell \cell }\pard \qj\li-108\ri-108\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard \widctlpar\intbl\adjustright {\f0\fs24 \row }\trowd +\trgaph108\trleft142\trkeep \clvertalt\clbrdrl\brdrs\brdrw30 \cltxlrtb \cellx711\clvertalt\cltxlrtb \cellx1384\clvertalt\cltxlrtb \cellx1701\clvertalt\cltxlrtb \cellx2377\clvertalt\cltxlrtb \cellx2694\clvertalt\cltxlrtb \cellx3369\clvertalt\cltxlrtb +\cellx3938\clvertalt\cltxlrtb \cellx4645\clvertalt\cltxlrtb \cellx4924\clvertalt\cltxlrtb \cellx5212\clvmrg\clvertalt\clbrdrl\brdrs\brdrw30 \clbrdrb\brdrs\brdrw30 \clbrdrr\brdrs\brdrw30 \cltxlrtb \cellx5637\clvertalt\cltxlrtb \cellx6206 +\clvertalt\cltxlrtb \cellx6775\clvmrg\clvertalt\clbrdrl\brdrs\brdrw30 \clbrdrb\brdrs\brdrw30 \clbrdrr\brdrs\brdrw30 \cltxlrtb \cellx7196\clvertalt\cltxlrtb \cellx7480\clvertalt\clbrdrt\brdrs\brdrw20 \clbrdrl\brdrs\brdrw20 \clbrdrb\brdrs\brdrw20 \clbrdrr +\brdrs\brdrw20 \clcbpat11\cltxlrtb \cellx7763\clvertalt\cltxlrtb \cellx8472\clvmrg\clvertalt\clbrdrl\brdrs\brdrw30 \clbrdrb\brdrs\brdrw30 \clbrdrr\brdrs\brdrw30 \cltxlrtb \cellx8897\clvertalt\cltxlrtb \cellx9466\clvertalt\cltxlrtb \cellx9889 +\clvertalt\cltxlrtb \cellx10173\pard \qj\li34\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard \qj\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell \cell \cell \cell \cell \cell \cell \cell \cell \cell \cell \cell \cell \cell +\cell }\pard \qj\li-108\ri-108\nowidctlpar\intbl\tx2835\adjustright {\f0\fs20 D1 +\par 1N414B}{\f0\fs24 \cell }\pard \qj\ri-106\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard \qj\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell \cell }\pard \qj\li-108\ri-108\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 +\cell }\pard \widctlpar\intbl\adjustright {\f0\fs24 \row }\trowd \trgaph108\trrh261\trleft142 \clvertalt\clbrdrl\brdrs\brdrw30 \cltxlrtb \cellx711\clvertalt\cltxlrtb \cellx1384\clvertalt\cltxlrtb \cellx1701\clvertalt\cltxlrtb \cellx2377 +\clvertalt\cltxlrtb \cellx2694\clvertalt\cltxlrtb \cellx3369\clvertalt\cltxlrtb \cellx3938\clvertalt\cltxlrtb \cellx4645\clvertalt\cltxlrtb \cellx4924\clvertalt\cltxlrtb \cellx5212\clvertalt\cltxlrtb \cellx5637\clvertalt\cltxlrtb \cellx6206 +\clvertalt\cltxlrtb \cellx6775\clvertalt\cltxlrtb \cellx7196\clvertalt\cltxlrtb \cellx7480\clvertalt\cltxlrtb \cellx7763\clvertalt\cltxlrtb \cellx8472\clvertalt\cltxlrtb \cellx8897\clvertalt\cltxlrtb \cellx9466\clvertalt\cltxlrtb \cellx9889 +\clvertalt\cltxlrtb \cellx10173\pard \qj\li34\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard \qj\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell \cell \cell \cell \cell \cell \cell \cell \cell \cell \cell \cell }\pard +\qj\ri-108\nowidctlpar\intbl\tx2835\adjustright {\f0\fs20 R2\cell }\pard \qj\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell \cell }\pard \qj\ri-108\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard \qj\ri-106\nowidctlpar\intbl +\tx2835\adjustright {\f0\fs24 \cell }\pard \qj\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell \cell }\pard \qj\li-108\ri-108\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard \widctlpar\intbl\adjustright {\f0\fs24 \row }\trowd +\trgaph108\trrh138\trleft142 \clvertalt\clbrdrl\brdrs\brdrw30 \cltxlrtb \cellx711\clvertalt\cltxlrtb \cellx1384\clvertalt\cltxlrtb \cellx1701\clvertalt\cltxlrtb \cellx2377\clvertalt\cltxlrtb \cellx2694\clvertalt\cltxlrtb \cellx3369\clvertalt\cltxlrtb +\cellx3938\clvertalt\cltxlrtb \cellx4645\clvertalt\cltxlrtb \cellx4924\clvertalt\cltxlrtb \cellx5212\clvertalt\cltxlrtb \cellx5637\clvertalt\cltxlrtb \cellx6206\clvertalt\cltxlrtb \cellx6775\clvertalt\clbrdrt\brdrs\brdrw20 \clbrdrl\brdrs\brdrw20 \clbrdrb +\brdrs\brdrw20 \clbrdrr\brdrs\brdrw20 \clcbpat13\cltxlrtb \cellx7196\clvertalt\cltxlrtb \cellx7480\clvertalt\cltxlrtb \cellx7763\clvertalt\cltxlrtb \cellx8472\clvertalt\cltxlrtb \cellx8897\clvertalt\cltxlrtb \cellx9466\clvertalt\cltxlrtb \cellx9889 +\clvertalt\cltxlrtb \cellx10173\pard \qj\li34\nowidctlpar\intbl\tx2835\adjustright {\lang1024\cgrid {\shp{\*\shpinst\shpleft9649\shptop165\shpright9762\shpbottom278\shpfhdr0\shpbxcolumn\shpbypara\shpwr3\shpwrk0\shpfblwtxt0\shpz47\shplid1230 +{\sp{\sn shapeType}{\sv 3}}{\sp{\sn fFlipH}{\sv 0}}{\sp{\sn fFlipV}{\sv 0}}}{\shprslt{\*\do\dobxcolumn\dobypara\dodhgt8239\dpellipse\dpx9649\dpy165\dpxsize113\dpysize113 +\dpfillfgcr255\dpfillfgcg255\dpfillfgcb255\dpfillbgcr255\dpfillbgcg255\dpfillbgcb255\dpfillpat1\dplinew15\dplinecor0\dplinecog0\dplinecob0}}}}{\f0\fs16 \cell }\pard \qj\nowidctlpar\intbl\tx2835\adjustright {\f0\fs16 \cell \cell \cell \cell \cell \cell +\cell \cell \cell \cell \cell \cell \cell \cell \cell }\pard \qj\ri-108\nowidctlpar\intbl\tx2835\adjustright {\f0\fs16 \cell }\pard \qj\ri-106\nowidctlpar\intbl\tx2835\adjustright {\f0\fs16 \cell }\pard \qj\nowidctlpar\intbl\tx2835\adjustright {\f0\fs16 +\cell \cell }\pard \qj\li-108\ri-108\nowidctlpar\intbl\tx2835\adjustright {\f0\fs16 \cell }\pard \widctlpar\intbl\adjustright {\f0\fs16 \row }\trowd \trgaph108\trleft142\trkeep \clvertalt\clbrdrl\brdrs\brdrw30 \cltxlrtb \cellx711\clvertalt\cltxlrtb +\cellx1384\clvertalt\cltxlrtb \cellx1701\clvertalt\cltxlrtb \cellx2377\clvertalt\cltxlrtb \cellx2694\clvertalt\cltxlrtb \cellx3369\clvertalt\cltxlrtb \cellx3938\clvertalt\cltxlrtb \cellx4645\clvertalt\cltxlrtb \cellx4924\clvertalt\cltxlrtb \cellx5212 +\clvertalt\cltxlrtb \cellx5637\clvertalt\cltxlrtb \cellx6206\clvertalt\cltxlrtb \cellx6775\clvertalt\cltxlrtb \cellx7196\clvertalt\cltxlrtb \cellx7480\clvertalt\cltxlrtb \cellx7763\clvertalt\cltxlrtb \cellx8472\clvertalt\cltxlrtb \cellx8897 +\clvertalt\cltxlrtb \cellx9466\clvmgf\clvertalt\clbrdrt\brdrs\brdrw30 \clbrdrl\brdrs\brdrw30 \clbrdrb\brdrs\brdrw30 \clbrdrr\brdrs\brdrw30 \cltxbtlr \cellx9889\clvertalt\cltxlrtb \cellx10173\pard \qj\li34\sa240\nowidctlpar\intbl\tx2835\adjustright { +\lang1024\cgrid {\shp{\*\shpinst\shpleft3601\shptop538\shpright3714\shpbottom651\shpfhdr0\shpbxcolumn\shpbypara\shpwr3\shpwrk0\shpfblwtxt0\shpz48\shplid1231 +{\sp{\sn shapeType}{\sv 3}}{\sp{\sn fFlipH}{\sv 0}}{\sp{\sn fFlipV}{\sv 0}}}{\shprslt{\*\do\dobxcolumn\dobypara\dodhgt8240\dpellipse\dpx3601\dpy538\dpxsize113\dpysize113 +\dpfillfgcr255\dpfillfgcg255\dpfillfgcb255\dpfillbgcr255\dpfillbgcg255\dpfillbgcb255\dpfillpat1\dplinew15\dplinecor0\dplinecog0\dplinecob0}}}}{\f0\fs24 \cell }\pard \qj\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell \cell \cell \cell \cell +\cell }\pard \qr\nowidctlpar\intbl\tx2835\adjustright {\f0\fs20 R8, +\par }\pard \qr\li-77\nowidctlpar\intbl\tx2835\adjustright {\f0\fs20 3X150\cell }\pard \qj\li-74\ri-147\nowidctlpar\intbl\tx2835\adjustright {\f0\fs20 6,\cell }\pard \qj\li-70\ri-141\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs20 5}{\f0\fs24 \cell +}\pard \qj\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell \cell \cell }\pard \qj\li-112\ri-108\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 10k\cell }\pard \qj\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell \cell }\pard +\qj\ri-108\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard \qj\ri-106\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard \qj\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard +\qj\li113\ri113\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 IC2 74LS393\cell }\pard \qj\li-108\ri-108\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard \widctlpar\intbl\adjustright {\f0\fs24 \row }\trowd +\trgaph108\trleft142\trkeep \clvertalt\clbrdrl\brdrs\brdrw30 \cltxlrtb \cellx711\clvertalt\cltxlrtb \cellx1384\clvertalt\cltxlrtb \cellx1701\clvertalt\cltxlrtb \cellx2377\clvertalt\cltxlrtb \cellx2694\clvertalt\cltxlrtb \cellx3369\clvmgf\clvertalt\clbrdrt +\brdrdb\brdrw30 \clbrdrl\brdrdb\brdrw30 \clbrdrr\brdrdb\brdrw30 \cltxbtlr \cellx3938\clvertalt\cltxlrtb \cellx4395\clvertalt\clbrdrt\brdrs\brdrw20 \clbrdrl\brdrs\brdrw20 \clbrdrb\brdrs\brdrw20 \clbrdrr\brdrs\brdrw15 \clcbpat13\cltxlrtb \cellx4645 +\clvertalt\clbrdrt\brdrs\brdrw20 \clbrdrl\brdrs\brdrw15 \clbrdrb\brdrs\brdrw20 \clbrdrr\brdrs\brdrw15 \clcbpat13\cltxlrtb \cellx4924\clvertalt\clbrdrt\brdrs\brdrw20 \clbrdrl\brdrs\brdrw15 \clbrdrb\brdrs\brdrw20 \clbrdrr\brdrs\brdrw20 \clcbpat13\cltxlrtb +\cellx5212\clvertalt\cltxlrtb \cellx5637\clvertalt\cltxlrtb \cellx6206\clvertalt\cltxlrtb \cellx6775\clvertalt\cltxlrtb \cellx7196\clvertalt\cltxlrtb \cellx7480\clvertalt\cltxlrtb \cellx7763\clvertalt\cltxlrtb \cellx8472\clvertalt\cltxlrtb \cellx8897 +\clvertalt\cltxlrtb \cellx9466\clvmrg\clvertalt\clbrdrl\brdrs\brdrw30 \clbrdrb\brdrs\brdrw30 \clbrdrr\brdrs\brdrw30 \cltxlrtb \cellx9889\clvertalt\cltxlrtb \cellx10173\pard \qj\li34\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard +\qj\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell \cell \cell \cell \cell }\pard \qj\li113\ri113\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 IC15 8271\cell }\pard \qj\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 +\cell \cell \cell \cell \cell \cell \cell \cell \cell \cell }\pard \qj\ri-108\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard \qj\ri-106\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard \qj\sa240\nowidctlpar\intbl +\tx2835\adjustright {\f0\fs24 \cell \cell }\pard \qj\li-108\ri-108\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard \widctlpar\intbl\adjustright {\f0\fs24 \row }\trowd \trgaph108\trleft142\trkeep \clvertalt\clbrdrl\brdrs\brdrw30 +\cltxlrtb \cellx711\clvertalt\cltxlrtb \cellx1384\clvertalt\cltxlrtb \cellx1701\clvertalt\cltxlrtb \cellx2377\clvertalt\clbrdrt\brdrs\brdrw20 \clbrdrl\brdrs\brdrw20 \clbrdrb\brdrs\brdrw20 \clbrdrr\brdrs\brdrw20 \clcbpat13\cltxlrtb \cellx2694 +\clvertalt\cltxlrtb \cellx3369\clvmrg\clvertalt\clbrdrl\brdrdb\brdrw30 \clbrdrr\brdrdb\brdrw30 \cltxlrtb \cellx3938\clvertalt\cltxlrtb \cellx4645\clvertalt\cltxlrtb \cellx4924\clvertalt\cltxlrtb \cellx5212\clvertalt\cltxlrtb \cellx5637\clvertalt\cltxlrtb +\cellx6206\clvertalt\cltxlrtb \cellx6775\clvertalt\cltxlrtb \cellx7196\clvertalt\cltxlrtb \cellx7480\clvertalt\cltxlrtb \cellx7763\clvertalt\cltxlrtb \cellx8472\clvertalt\cltxlrtb \cellx8897\clvertalt\cltxlrtb \cellx9466\clvmrg\clvertalt\clbrdrl +\brdrs\brdrw30 \clbrdrb\brdrs\brdrw30 \clbrdrr\brdrs\brdrw30 \cltxlrtb \cellx9889\clvertalt\cltxlrtb \cellx10173\pard \qj\li34\sa240\nowidctlpar\intbl\tx2835\adjustright {\lang1024\cgrid +{\shp{\*\shpinst\shpleft5329\shptop521\shpright5442\shpbottom634\shpfhdr0\shpbxcolumn\shpbypara\shpwr3\shpwrk0\shpfblwtxt0\shpz49\shplid1232 +{\sp{\sn shapeType}{\sv 3}}{\sp{\sn fFlipH}{\sv 0}}{\sp{\sn fFlipV}{\sv 0}}}{\shprslt{\*\do\dobxcolumn\dobypara\dodhgt8241\dpellipse\dpx5329\dpy521\dpxsize113\dpysize113 +\dpfillfgcr255\dpfillfgcg255\dpfillfgcb255\dpfillbgcr255\dpfillbgcg255\dpfillbgcb255\dpfillpat1\dplinew15\dplinecor0\dplinecog0\dplinecob0}}}}{\f0\fs24 \cell }\pard \qj\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell \cell }\pard +\qj\nowidctlpar\intbl\tx2835\adjustright {\f0\fs20 R1 +\par 150\cell }\pard \qj\li-217\ri-108\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs16 \cell }\pard \qj\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell \cell \cell \cell \cell \cell \cell \cell \cell \cell \cell }\pard +\qj\ri-108\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard \qj\ri-106\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard \qj\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell \cell }\pard +\qj\li-108\ri-108\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard \widctlpar\intbl\adjustright {\f0\fs24 \row }\trowd \trgaph108\trleft142\trkeep \clvertalt\clbrdrl\brdrs\brdrw30 \cltxlrtb \cellx711\clvertalt\cltxlrtb \cellx1384 +\clvertalt\cltxlrtb \cellx1701\clvertalt\cltxlrtb \cellx2377\clvertalt\cltxlrtb \cellx2694\clvertalt\cltxlrtb \cellx3369\clvmrg\clvertalt\clbrdrl\brdrdb\brdrw30 \clbrdrr\brdrdb\brdrw30 \cltxlrtb \cellx3938\clvertalt\cltxlrtb \cellx4645\clvertalt\cltxlrtb +\cellx4924\clvertalt\cltxlrtb \cellx5212\clvmgf\clvertalt\clbrdrt\brdrs\brdrw30 \clbrdrl\brdrs\brdrw30 \clbrdrr\brdrs\brdrw30 \cltxbtlr \cellx5637\clvertalt\cltxlrtb \cellx6206\clvertalt\cltxlrtb \cellx6775\clvertalt\cltxlrtb \cellx7196 +\clvertalt\cltxlrtb \cellx7480\clvertalt\cltxlrtb \cellx7763\clvertalt\cltxlrtb \cellx8472\clvertalt\cltxlrtb \cellx8897\clvertalt\cltxlrtb \cellx9466\clvertalt\cltxlrtb \cellx9889\clvertalt\cltxlrtb \cellx10173\pard \qj\li34\sa240\nowidctlpar\intbl +\tx2835\adjustright {\f0\fs24 \cell }\pard \qj\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell \cell \cell \cell }\pard \qj\nowidctlpar\intbl\tx2835\adjustright {\f0\fs20 R14 +\par 3k3\cell }\pard \qj\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell \cell \cell \cell }\pard \qj\li113\ri113\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 IC1 74LS123\cell }\pard \qj\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 +\cell \cell \cell \cell \cell }\pard \qj\ri-108\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard \qj\ri-106\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard \qj\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell +\cell }\pard \qj\li-108\ri-108\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard \widctlpar\intbl\adjustright {\f0\fs24 \row }\trowd \trgaph108\trleft142\trkeep \clvertalt\clbrdrl\brdrs\brdrw30 \cltxlrtb \cellx711\clvertalt\cltxlrtb +\cellx1384\clvertalt\cltxlrtb \cellx1701\clvertalt\cltxlrtb \cellx2377\clvertalt\cltxlrtb \cellx2694\clvertalt\clbrdrt\brdrs\brdrw20 \clbrdrl\brdrs\brdrw20 \clbrdrb\brdrs\brdrw20 \clbrdrr\brdrs\brdrw20 \clcbpat13\cltxlrtb \cellx3031\clvertalt\cltxlrtb +\cellx3369\clvmrg\clvertalt\clbrdrl\brdrdb\brdrw30 \clbrdrr\brdrdb\brdrw30 \cltxlrtb \cellx3938\clvertalt\cltxlrtb \cellx4645\clvertalt\cltxlrtb \cellx4924\clvertalt\cltxlrtb \cellx5212\clvmrg\clvertalt\clbrdrl\brdrs\brdrw30 \clbrdrr\brdrs\brdrw30 +\cltxlrtb \cellx5637\clvertalt\cltxlrtb \cellx6206\clvertalt\cltxlrtb \cellx6775\clvertalt\cltxlrtb \cellx7196\clvertalt\cltxlrtb \cellx7480\clvertalt\cltxlrtb \cellx7763\clvertalt\cltxlrtb \cellx8472\clvertalt\cltxlrtb \cellx8897\clvertalt\cltxlrtb +\cellx9466\clvertalt\cltxlrtb \cellx9889\clvertalt\cltxlrtb \cellx10173\pard \qj\li34\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard \qj\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell \cell \cell \cell \cell \cell \cell +\cell \cell \cell \cell \cell \cell \cell \cell \cell }\pard \qj\ri-108\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard \qj\ri-106\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard \qj\sa240\nowidctlpar\intbl +\tx2835\adjustright {\f0\fs24 \cell \cell }\pard \qj\li-108\ri-108\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard \widctlpar\intbl\adjustright {\f0\fs24 \row }\trowd \trgaph108\trrh177\trleft142\trkeep \clvmgf\clvertalt\clbrdrl +\brdrs\brdrw30 \cltxlrtb \cellx711\clvmgf\clvertalt\cltxlrtb \cellx1384\clvmgf\clvertalt\cltxlrtb \cellx1701\clvmgf\clvertalt\cltxlrtb \cellx2377\clvmgf\clvertalt\cltxlrtb \cellx2694\clvmgf\clvertalt\cltxlrtb \cellx3369\clvmrg\clvertalt\clbrdrl +\brdrdb\brdrw30 \clbrdrr\brdrdb\brdrw30 \cltxlrtb \cellx3938\clvmgf\clvertalt\cltxlrtb \cellx4645\clvmgf\clvertalt\clbrdrt\brdrs\brdrw20 \clbrdrl\brdrs\brdrw20 \clbrdrr\brdrs\brdrw20 \clcbpat13\cltxlrtb \cellx4924\clvmgf\clvertalt\cltxlrtb \cellx5212 +\clvmrg\clvertalt\clbrdrl\brdrs\brdrw30 \clbrdrr\brdrs\brdrw30 \cltxlrtb \cellx5637\clvmgf\clvertalt\cltxlrtb \cellx6206\clvertalt\cltxlrtb \cellx6490\clvertalt\cltxlrtb \cellx6775\clvmgf\clvertalt\cltxlrtb \cellx7196\clvmgf\clvertalt\cltxlrtb \cellx7480 +\clvmgf\clvertalt\cltxlrtb \cellx7763\clvmgf\clvertalt\cltxlrtb \cellx8472\clvmgf\clvertalt\cltxlrtb \cellx8897\clvmgf\clvertalt\cltxlrtb \cellx9466\clvmgf\clvertalt\cltxlrtb \cellx9889\clvmgf\clvertalt\cltxlrtb \cellx10173\pard +\qj\li34\sa240\nowidctlpar\intbl\tx2835\adjustright {\lang1024\cgrid {\shp{\*\shpinst\shpleft1441\shptop592\shpright1554\shpbottom705\shpfhdr0\shpbxcolumn\shpbypara\shpwr3\shpwrk0\shpfblwtxt0\shpz50\shplid1233 +{\sp{\sn shapeType}{\sv 3}}{\sp{\sn fFlipH}{\sv 0}}{\sp{\sn fFlipV}{\sv 0}}}{\shprslt{\*\do\dobxcolumn\dobypara\dodhgt8242\dpellipse\dpx1441\dpy592\dpxsize113\dpysize113 +\dpfillfgcr255\dpfillfgcg255\dpfillfgcb255\dpfillbgcr255\dpfillbgcg255\dpfillbgcb255\dpfillpat1\dplinew15\dplinecor0\dplinecog0\dplinecob0}}} +{\shp{\*\shpinst\shpleft2449\shptop592\shpright2562\shpbottom705\shpfhdr0\shpbxcolumn\shpbypara\shpwr3\shpwrk0\shpfblwtxt0\shpz51\shplid1234 +{\sp{\sn shapeType}{\sv 3}}{\sp{\sn fFlipH}{\sv 0}}{\sp{\sn fFlipV}{\sv 0}}}{\shprslt{\*\do\dobxcolumn\dobypara\dodhgt8243\dpellipse\dpx2449\dpy592\dpxsize113\dpysize113 +\dpfillfgcr255\dpfillfgcg255\dpfillfgcb255\dpfillbgcr255\dpfillbgcg255\dpfillbgcb255\dpfillpat1\dplinew15\dplinecor0\dplinecog0\dplinecob0}}}}{\f0\fs24 \cell }\pard \qj\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell \cell \cell \cell \cell +\cell }\pard \qr\nowidctlpar\intbl\tx2835\adjustright {\f0\fs20 R7 +\par 150\cell }\pard \qj\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell \cell \cell \cell }\pard \qj\sl120\slmult0\nowidctlpar\intbl\tx2835\adjustright {\f0\fs16 \cell }\pard \qj\li-77\ri-137\sl120\slmult0\nowidctlpar\intbl\tx2835\adjustright { +\f0\fs20 C1\cell }\pard \qj\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell \cell \cell }\pard \qj\ri-108\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard \qj\ri-106\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell +}\pard \qj\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell \cell }\pard \qj\li-108\ri-108\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard \widctlpar\intbl\adjustright {\f0\fs24 \row }\trowd \trgaph108\trrh255\trleft142\trkeep +\clvmrg\clvertalt\clbrdrl\brdrs\brdrw30 \cltxlrtb \cellx711\clvmrg\clvertalt\cltxlrtb \cellx1384\clvmrg\clvertalt\cltxlrtb \cellx1701\clvmrg\clvertalt\cltxlrtb \cellx2377\clvmrg\clvertalt\cltxlrtb \cellx2694\clvmrg\clvertalt\cltxlrtb \cellx3369 +\clvmrg\clvertalt\clbrdrl\brdrdb\brdrw30 \clbrdrb\brdrdb\brdrw30 \clbrdrr\brdrdb\brdrw30 \cltxlrtb \cellx3938\clvmrg\clvertalt\cltxlrtb \cellx4645\clvmrg\clvertalt\clbrdrl\brdrs\brdrw20 \clbrdrb\brdrs\brdrw20 \clbrdrr\brdrs\brdrw20 \clcbpat13\cltxlrtb +\cellx4924\clvmrg\clvertalt\cltxlrtb \cellx5212\clvmrg\clvertalt\clbrdrl\brdrs\brdrw30 \clbrdrb\brdrs\brdrw30 \clbrdrr\brdrs\brdrw30 \cltxlrtb \cellx5637\clvmrg\clvertalt\cltxlrtb \cellx6206\clvertalt\cltxlrtb \cellx6490\clvertalt\clbrdrt\brdrs\brdrw20 +\clbrdrl\brdrs\brdrw20 \clbrdrb\brdrs\brdrw20 \clbrdrr\brdrs\brdrw20 \clcbpat10\cltxlrtb \cellx6775\clvmrg\clvertalt\cltxlrtb \cellx7196\clvmrg\clvertalt\cltxlrtb \cellx7480\clvmrg\clvertalt\cltxlrtb \cellx7763\clvmrg\clvertalt\cltxlrtb \cellx8472 +\clvmrg\clvertalt\cltxlrtb \cellx8897\clvmrg\clvertalt\cltxlrtb \cellx9466\clvmrg\clvertalt\cltxlrtb \cellx9889\clvmrg\clvertalt\cltxlrtb \cellx10173\pard \qj\li34\sa240\nowidctlpar\intbl\tx2835\adjustright {\cgrid \cell }\pard \qj\sa240\nowidctlpar\intbl +\tx2835\adjustright {\f0\fs24 \cell \cell \cell \cell \cell \cell }\pard \qr\nowidctlpar\intbl\tx2835\adjustright {\f0\fs20 \cell }\pard \qj\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell \cell \cell \cell }\pard \qj\sl120\slmult0 +\nowidctlpar\intbl\tx2835\adjustright {\f0\fs16 \cell }\pard \qj\li-77\sl120\slmult0\nowidctlpar\intbl\tx2835\adjustright {\f0\fs16 \cell }\pard \qj\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell \cell \cell }\pard +\qj\ri-108\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard \qj\ri-106\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard \qj\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell \cell }\pard +\qj\li-108\ri-108\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard \widctlpar\intbl\adjustright {\f0\fs24 \row }\trowd \trgaph108\trrh255\trleft142\trkeep \clvmgf\clvertalt\clbrdrl\brdrs\brdrw30 \cltxlrtb \cellx711 +\clvmgf\clvertalt\cltxlrtb \cellx1384\clvmgf\clvertalt\clbrdrt\brdrs\brdrw30 \clbrdrl\brdrs\brdrw30 \clbrdrr\brdrs\brdrw30 \cltxbtlr \cellx1701\clvmgf\clvertalt\cltxlrtb \cellx2377\clvmgf\clvertalt\clbrdrt\brdrs\brdrw30 \clbrdrl\brdrs\brdrw30 \clbrdrr +\brdrs\brdrw30 \cltxbtlr \cellx2694\clvmgf\clvertalt\cltxlrtb \cellx3369\clvmgf\clvertalt\cltxlrtb \cellx3938\clvmgf\clvertalt\cltxlrtb \cellx4645\clvmgf\clvertalt\cltxlrtb \cellx4924\clvmgf\clvertalt\cltxlrtb \cellx5212\clvmgf\clvertalt\cltxlrtb +\cellx5637\clvertalt\cltxlrtb \cellx6206\clvmgf\clvertalt\cltxlrtb \cellx6775\clvmgf\clvertalt\cltxlrtb \cellx7196\clvmgf\clvertalt\cltxlrtb \cellx7480\clvmgf\clvertalt\cltxlrtb \cellx7763\clvmgf\clvertalt\cltxlrtb \cellx8472\clvmgf\clvertalt\cltxlrtb +\cellx8897\clvmgf\clvertalt\cltxlrtb \cellx9466\clvmgf\clvertalt\cltxlrtb \cellx9889\clvmgf\clvertalt\cltxlrtb \cellx10173\pard \qj\li34\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard \qj\sa240\nowidctlpar\intbl\tx2835\adjustright { +\f0\fs24 \cell }\pard \qj\li-74\ri-142\nowidctlpar\intbl\tx2835\adjustright {\f0\fs18 IC8 7416\cell }\pard \qj\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard \li113\ri-113\sl180\slmult0\nowidctlpar\intbl\tx2835\adjustright {\f0\fs20 +IC7 7438\cell }\pard \qj\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell \cell \cell \cell \cell \cell }\pard \qj\nowidctlpar\intbl\tx2835\adjustright {\f0\fs20 R3\cell }\pard \qr\li-79\ri-57\nowidctlpar\intbl\tx2835\adjustright {\f0\fs20 1n0 +\cell }\pard \qj\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell \cell \cell }\pard \qj\ri-108\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard \qj\ri-106\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard +\qj\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell \cell }\pard \qj\li-108\ri-108\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard \widctlpar\intbl\adjustright {\f0\fs24 \row }\trowd \trgaph108\trrh255\trleft142\trkeep +\clvmrg\clvertalt\clbrdrl\brdrs\brdrw30 \cltxlrtb \cellx711\clvmrg\clvertalt\cltxlrtb \cellx1384\clvmrg\clvertalt\clbrdrl\brdrs\brdrw30 \clbrdrr\brdrs\brdrw30 \cltxbtlr \cellx1701\clvmrg\clvertalt\cltxlrtb \cellx2377\clvmrg\clvertalt\clbrdrl +\brdrs\brdrw30 \clbrdrr\brdrs\brdrw30 \cltxbtlr \cellx2694\clvmrg\clvertalt\cltxlrtb \cellx3369\clvmrg\clvertalt\cltxlrtb \cellx3938\clvmrg\clvertalt\cltxlrtb \cellx4645\clvmrg\clvertalt\cltxlrtb \cellx4924\clvmrg\clvertalt\cltxlrtb \cellx5212 +\clvmrg\clvertalt\cltxlrtb \cellx5637\clvertalt\clbrdrt\brdrs\brdrw20 \clbrdrl\brdrs\brdrw20 \clbrdrb\brdrs\brdrw20 \clbrdrr\brdrs\brdrw20 \clcbpat13\cltxlrtb \cellx6206\clvmrg\clvertalt\cltxlrtb \cellx6775\clvmrg\clvertalt\cltxlrtb \cellx7196 +\clvmrg\clvertalt\cltxlrtb \cellx7480\clvmrg\clvertalt\cltxlrtb \cellx7763\clvmrg\clvertalt\cltxlrtb \cellx8472\clvmrg\clvertalt\cltxlrtb \cellx8897\clvmrg\clvertalt\cltxlrtb \cellx9466\clvmrg\clvertalt\cltxlrtb \cellx9889\clvmrg\clvertalt\cltxlrtb +\cellx10173\pard \qj\li34\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard \qj\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard \qj\li-74\ri-142\nowidctlpar\intbl\tx2835\adjustright {\f0\fs18 \cell }\pard +\qj\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard \li113\ri-113\sl180\slmult0\nowidctlpar\intbl\tx2835\adjustright {\f0\fs20 \cell }\pard \qj\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell \cell \cell \cell \cell \cell +}\pard \qj\nowidctlpar\intbl\tx2835\adjustright {\f0\fs20 \cell }\pard \qj\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell \cell \cell \cell }\pard \qj\ri-108\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard +\qj\ri-106\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard \qj\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell \cell }\pard \qj\li-108\ri-108\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard +\widctlpar\intbl\adjustright {\f0\fs24 \row }\trowd \trgaph108\trleft142\trkeep \clvertalt\clbrdrl\brdrs\brdrw30 \cltxlrtb \cellx711\clvertalt\cltxlrtb \cellx1384\clvmrg\clvertalt\clbrdrl\brdrs\brdrw30 \clbrdrb\brdrs\brdrw30 \clbrdrr\brdrs\brdrw30 +\cltxlrtb \cellx1701\clvertalt\cltxlrtb \cellx2377\clvmrg\clvertalt\clbrdrl\brdrs\brdrw30 \clbrdrb\brdrs\brdrw30 \clbrdrr\brdrs\brdrw30 \cltxlrtb \cellx2694\clvertalt\cltxlrtb \cellx3369\clvertalt\cltxlrtb \cellx3938\clvertalt\cltxlrtb \cellx4645 +\clvertalt\cltxlrtb \cellx4924\clvertalt\cltxlrtb \cellx5212\clvertalt\cltxlrtb \cellx5637\clvertalt\cltxlrtb \cellx6206\clvertalt\cltxlrtb \cellx6775\clvertalt\cltxlrtb \cellx7196\clvertalt\cltxlrtb \cellx7480\clvertalt\cltxlrtb \cellx7763 +\clvertalt\cltxlrtb \cellx8472\clvertalt\cltxlrtb \cellx8897\clvertalt\cltxlrtb \cellx9466\clvertalt\cltxlrtb \cellx9889\clvertalt\cltxlrtb \cellx10173\pard \qj\li34\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard +\qj\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard \qj\li-74\ri-141\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard \qj\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard +\qj\li-75\ri-142\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard \qj\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell \cell \cell \cell \cell \cell }{\f0\fs20 1k\cell }{\f0\fs24 \cell \cell \cell \cell }\pard +\qj\ri-108\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard \qj\ri-106\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard \qj\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell \cell }\pard +\qj\li-108\ri-108\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard \widctlpar\intbl\adjustright {\f0\fs24 \row }\trowd \trgaph108\trleft142 \clvertalt\clbrdrl\brdrs\brdrw30 \cltxlrtb \cellx711\clvertalt\cltxlrtb \cellx1384 +\clvertalt\cltxlrtb \cellx1701\clvertalt\cltxlrtb \cellx2377\clvertalt\cltxlrtb \cellx2694\clvertalt\cltxlrtb \cellx3369\clvertalt\cltxlrtb \cellx3938\clvertalt\cltxlrtb \cellx4645\clvertalt\cltxlrtb \cellx4924\clvertalt\cltxlrtb \cellx5212 +\clvertalt\cltxlrtb \cellx5637\clvertalt\cltxlrtb \cellx6206\clvertalt\cltxlrtb \cellx6775\clvertalt\cltxlrtb \cellx7196\clvertalt\cltxlrtb \cellx7480\clvertalt\cltxlrtb \cellx7763\clvertalt\cltxlrtb \cellx8472\clvertalt\cltxlrtb \cellx8897 +\clvertalt\cltxlrtb \cellx9466\clvertalt\cltxlrtb \cellx9889\clvertalt\cltxlrtb \cellx10173\pard \qj\li34\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard \qj\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell \cell \cell \cell +\cell \cell \cell \cell \cell \cell \cell \cell \cell \cell \cell }\pard \qj\ri-108\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard \qj\ri-106\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard \qj\sa240\nowidctlpar\intbl +\tx2835\adjustright {\f0\fs24 \cell \cell }\pard \qj\li-108\ri-108\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard \widctlpar\intbl\adjustright {\f0\fs24 \row }\trowd \trgaph108\trleft142\trkeep \clvertalt\clbrdrl\brdrs\brdrw30 \clbrdrb +\brdrs\brdrw30 \cltxlrtb \cellx711\clvertalt\clbrdrt\brdrs\brdrw30 \clbrdrl\brdrs\brdrw30 \clbrdrb\brdrs\brdrw30 \clbrdrr\brdrs\brdrw30 \cltxlrtb \cellx3369\clvertalt\clbrdrb\brdrs\brdrw30 \cltxlrtb \cellx3938\clvertalt\clbrdrb\brdrs\brdrw30 \cltxlrtb +\cellx4645\clvertalt\clbrdrb\brdrs\brdrw30 \cltxlrtb \cellx4924\clvertalt\clbrdrb\brdrs\brdrw30 \cltxlrtb \cellx5212\clvertalt\clbrdrb\brdrs\brdrw30 \cltxlrtb \cellx5637\clvertalt\clbrdrb\brdrs\brdrw30 \cltxlrtb \cellx6206\clvertalt\clbrdrb\brdrs\brdrw30 +\cltxlrtb \cellx6775\clvertalt\clbrdrt\brdrs\brdrw30 \clbrdrl\brdrs\brdrw30 \clbrdrr\brdrs\brdrw30 \cltxlrtb \cellx7480\clvertalt\clbrdrb\brdrs\brdrw30 \cltxlrtb \cellx7763\clvertalt\clbrdrb\brdrs\brdrw30 \cltxlrtb \cellx8472\clvertalt\clbrdrb +\brdrs\brdrw30 \cltxlrtb \cellx8897\clvertalt\clbrdrb\brdrs\brdrw30 \cltxlrtb \cellx9466\clvertalt\clbrdrb\brdrs\brdrw30 \cltxlrtb \cellx9889\clvertalt\clbrdrb\brdrs\brdrw30 \cltxlrtb \cellx10173\pard \qj\li34\sa240\nowidctlpar\intbl\tx2835\adjustright { +\f0\fs24 \cell }\pard \qc\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 PL 8 (34 WAY)\cell }\pard \qj\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell \cell \cell \cell \cell \cell \cell \cell \cell }\pard +\qj\ri-108\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard \qj\ri-106\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard \qj\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell \cell }\pard +\qj\li-108\ri-108\sa240\nowidctlpar\intbl\tx2835\adjustright {\f0\fs24 \cell }\pard \widctlpar\intbl\adjustright {\f0\fs24 \row }\pard \qj\sa240\nowidctlpar\tx2835\adjustright {\fs24 +\par +\par }{Figure 6. 8271 Disc Interface components. +\par }\pard\plain \s2\sa240\keepn\nowidctlpar\tx2835\outlinelevel1\adjustright \b\f2\lang2057 {\page 6.3 ECONET +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {Local area network interface +\par Due to the complexity of this upgrade and the specialised test equ +ipment required, it should only be carried out by ACORN Approved ECONET Service Centers, with the appropriate test equipment. Upgrade procedures and requirements, as notified by suppliers, should also be adhered to and reference should be made to any avai +lable information updates for latest details. +\par i) The following items, from the ECONET Hardware Upgrade Kit, are required to upgrade model B+: +\par }\pard \qj\li288\sa240\nowidctlpar\tx2835\adjustright {QTY DESCRIPTION\tab \tab \tab CIRCUIT REFERENCE +\par }\pard \qj\li448\nowidctlpar\tx2835\adjustright {3 RESISTOR 1K0 \tab 0.25W 5%\tab \tab R63,73,148 +\par 1 RESISTOR 1K5 \tab 0.25W 5%\tab \tab R147 +\par 1 RESISTOR 4K7 \tab 0.25W 5%\tab \tab R59 +\par 4 RESISTOR 10K \tab 0.25W 2%\tab \tab R140,141,142,143 +\par 1 RESISTOR 39K \tab 0.25W 5%\tab \tab R64 +\par 4 RESISTOR 100K \tab 0.25W 2%\tab \tab R106,110,125,134 +\par 1 RESISTOR 220K \tab 0.25W 5%\tab \tab R77 +\par 2 RESISTOR 1M5 \tab 0.25W 5%\tab \tab R78,79 +\par 1 RESISTOR PACK \tab 8 x 22K \tab \tab RP2 +\par 1 CAPACITOR 10u \tab 6V3 TANT\tab \tab C57 +\par 1 CAPACITOR 47u \tab 10V TANT\tab \tab C37 +\par 1 CAPACITOR 2n2 \tab CER PL 2% \tab C26 +\par 1 IC 68B54\tab \tab \tab \tab IC81 +\par 1 IC 75159\tab \tab \tab \tab IC91 +\par 1 IC 74LS123\tab \tab \tab \tab IC88 +\par 1 IC 74LS132\tab \tab \tab \tab IC70 +\par 1 IC 74LS244\tab \tab \tab \tab IC80 +\par 1 IC LM319\tab \tab \tab \tab IC92 +\par 1 SOCKET DIN 5 PIN 180 DEGREE\tab SK7 +\par 2 CONNECTOR 8 WAY WAFER\tab \tab S23 +\par 7 SHUNT\tab \tab \tab \tab FOR S23 +\par 2 SOCKET 14 PIN DIL\tab \tab \tab FOR IC91,92 +\par 1 SOCKET 28 PIN DIL\tab \tab \tab FOR IC81 (OPTION) +\par 1 CONNECTING LEAD ECONET +\par }\pard \qj\li448\sa240\nowidctlpar\tx2835\adjustright {1 Current network filing system ROM (e.g. DNFS) +\par }\pard \qj\sa240\nowidctlpar\tx2835\adjustright {IMPORTANT NOTE: Collision detect circuitry is not included in the model B+ ECONET u +pgrade. It has been found, following exhaustive tests, that this feature is not required when a BBC Microcomputer is operating within -an ACORN ECONET environment. However, it may be required where an ECONET machine is used with equipment which does not i +nclude the ACORN NFS software and provision is made for this circuitry to be fitted to the PCB. See below. +\par ii) If collision detect circuitry is to be fitted, the track link at S29 should be cut before proceeding (see below). +\par iii) Solder the 14 pin DIL sockets into positions IC91 and 92. +\par iv)Insert ICs 91 and 92 into their sockets. +\par }\pard \qj\ri720\sa240\nowidctlpar\tx2835\adjustright {\page v) Solder all the remaining ICs, resistors and capacitors into their correct positions on the PCB. IC81 may be socketed as an option, though this may degrade reliability. +\par vi) Solder the two 8 way wafer connectors into the PCB in their correct positions and then push the seven shunts onto all but the North-most pins. +\par vii) Solder the DIN socket into the PCB. +\par viii) Insert the filing system ROM (e.g. DNFS) into a vacant sideways ROM socket. Note that, where a B+ machine is already fitted with the 1770 Disc Interface, a DNFS ROM must be fitted in addition to the l770 DFS ROM already installed. +\par ix) If collision detect circuitry is required, the additional components given below must be fitted: +\par }\pard \qj\ri720\sa240\nowidctlpar\tx851\tx2835\adjustright {\tab QTY \tab DESCRIPTION\tab \tab \tab CIRCUIT REFERENCE +\par }\pard \qj\ri720\nowidctlpar\tx851\tx2835\adjustright {\tab 1 \tab RESISTOR 1K0 0.25W 5%\tab \tab R68 +\par \tab 4 \tab RESISTOR 56K 0.25W 2%\tab \tab R95,96,98,99 +\par \tab 1 \tab RESISTOR 1M5 0.25W 5%\tab \tab R97 +\par \tab 1 \tab CRPACITOR l0nF CER PLT\tab \tab C28 +\par \tab 1 \tab IC LM319\tab \tab \tab \tab \tab IC93 +\par }\pard \qj\ri720\sa240\nowidctlpar\tx851\tx2835\adjustright {\tab 2 \tab SOCKET 14 PIN DIL\tab \tab \tab FOR IC93 +\par }\pard \qj\ri720\sa240\nowidctlpar\tx2835\adjustright {In addition, the track link at S29 should be cut. +\par x) In order to complete the ECONET upgrade, the machine must be tested using the approved ACORN ECONET test kit. +\par }\pard\plain \s2\sa240\keepn\nowidctlpar\tx2835\outlinelevel1\adjustright \b\f2\lang2057 {6.4 SPEECH. +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {Speech synthesizer, word PHROM, and serial ROM socket +\par i) The following parts are required: +\par }\pard \qj\li567\nowidctlpar\tx1701\adjustright {IC29 \tab 5220 +\par }\pard \qj\li567\sa240\nowidctlpar\tx1701\adjustright {IC37 \tab 6100 PHROM +\par 15-way single sided edgecard socket (2 off) +\par 10-way right angle wafer plug +\par 10-way connecting lead with sockets fitted +\par 100n disc ceramic capacitor (2 off) +\par ROM socket cover +\par }\pard \qj\ri720\sa240\nowidctlpar\tx2835\adjustright {ii) Add components other than ICs listed above to keyboard assembly as shown in figure 7. +\par }\pard\plain \s20\qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {\page }{\fs26 +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {\lang1024\cgrid {\shpgrp{\*\shpinst\shpleft1026\shptop-267\shpright10225\shpbottom5225\shpfhdr0\shpbxcolumn\shpbypara\shpwr3\shpwrk0\shpfblwtxt0\shpz4\shplid1235 +{\sp{\sn groupLeft}{\sv 2177}}{\sp{\sn groupTop}{\sv 988}}{\sp{\sn groupRight}{\sv 11376}}{\sp{\sn groupBottom}{\sv 6480}}{\sp{\sn fFlipH}{\sv 0}}{\sp{\sn fFlipV}{\sv 0}}{\shp{\*\shpinst\shplid1236 +{\sp{\sn relLeft}{\sv 2304}}{\sp{\sn relTop}{\sv 3099}}{\sp{\sn relRight}{\sv 11376}}{\sp{\sn relBottom}{\sv 6480}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 1}}{\sp{\sn lidRegroup}{\sv 20}}}} +{\shp{\*\shpinst\shplid1237{\sp{\sn relLeft}{\sv 3456}}{\sp{\sn relTop}{\sv 4250}}{\sp{\sn relRight}{\sv 3456}}{\sp{\sn relBottom}{\sv 6410}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}} +{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}{\sp{\sn lidRegroup}{\sv 20}}}}{\shp{\*\shpinst\shplid1238{\sp{\sn relLeft}{\sv 3456}}{\sp{\sn relTop}{\sv 4250}} +{\sp{\sn relRight}{\sv 4320}}{\sp{\sn relBottom}{\sv 4250}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}} +{\sp{\sn lidRegroup}{\sv 20}}}}{\shp{\*\shpinst\shplid1239{\sp{\sn relLeft}{\sv 4337}}{\sp{\sn relTop}{\sv 3510}}{\sp{\sn relRight}{\sv 4337}}{\sp{\sn relBottom}{\sv 4259}}{\sp{\sn fRelFlipH}{\sv 0}} +{\sp{\sn fRelFlipV}{\sv 1}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}{\sp{\sn lidRegroup}{\sv 20}}}} +{\shp{\*\shpinst\shplid1240{\sp{\sn relLeft}{\sv 4337}}{\sp{\sn relTop}{\sv 3510}}{\sp{\sn relRight}{\sv 11249}}{\sp{\sn relBottom}{\sv 3510}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}} +{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}{\sp{\sn lidRegroup}{\sv 20}}}}{\shp{\*\shpinst\shplid1241{\sp{\sn relLeft}{\sv 11249}}{\sp{\sn relTop}{\sv 3539}} +{\sp{\sn relRight}{\sv 11249}}{\sp{\sn relBottom}{\sv 5123}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}} +{\sp{\sn lidRegroup}{\sv 20}}}}{\shp{\*\shpinst\shplid1242{\sp{\sn relLeft}{\sv 10944}}{\sp{\sn relTop}{\sv 5114}}{\sp{\sn relRight}{\sv 11232}}{\sp{\sn relBottom}{\sv 5114}}{\sp{\sn fRelFlipH}{\sv 1}} +{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}{\sp{\sn lidRegroup}{\sv 20}}}} +{\shp{\*\shpinst\shplid1243{\sp{\sn relLeft}{\sv 10944}}{\sp{\sn relTop}{\sv 5114}}{\sp{\sn relRight}{\sv 10944}}{\sp{\sn relBottom}{\sv 5546}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}} +{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}{\sp{\sn lidRegroup}{\sv 20}}}}{\shp{\*\shpinst\shplid1244{\sp{\sn relLeft}{\sv 10224}}{\sp{\sn relTop}{\sv 5546}} +{\sp{\sn relRight}{\sv 10944}}{\sp{\sn relBottom}{\sv 5546}}{\sp{\sn fRelFlipH}{\sv 1}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}} +{\sp{\sn lidRegroup}{\sv 20}}}}{\shp{\*\shpinst\shplid1245{\sp{\sn relLeft}{\sv 10224}}{\sp{\sn relTop}{\sv 5546}}{\sp{\sn relRight}{\sv 10224}}{\sp{\sn relBottom}{\sv 6427}}{\sp{\sn fRelFlipH}{\sv 0}} +{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}{\sp{\sn lidRegroup}{\sv 20}}}} +{\shp{\*\shpinst\shplid1246{\sp{\sn relLeft}{\sv 5328}}{\sp{\sn relTop}{\sv 5979}}{\sp{\sn relRight}{\sv 8784}}{\sp{\sn relBottom}{\sv 6267}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 1}}{\sp{\sn lidRegroup}{\sv 20}}}} +{\shp{\*\shpinst\shplid1247{\sp{\sn relLeft}{\sv 4769}}{\sp{\sn relTop}{\sv 3604}}{\sp{\sn relRight}{\sv 5057}}{\sp{\sn relBottom}{\sv 3892}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 1}}{\sp{\sn lidRegroup}{\sv 20}}}} +{\shp{\*\shpinst\shplid1248{\sp{\sn relLeft}{\sv 4769}}{\sp{\sn relTop}{\sv 3604}}{\sp{\sn relRight}{\sv 5057}}{\sp{\sn relBottom}{\sv 3892}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 1}}{\sp{\sn lidRegroup}{\sv 20}}}} +{\shp{\*\shpinst\shplid1249{\sp{\sn relLeft}{\sv 5201}}{\sp{\sn relTop}{\sv 3604}}{\sp{\sn relRight}{\sv 5489}}{\sp{\sn relBottom}{\sv 3892}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 1}}{\sp{\sn lidRegroup}{\sv 20}}}} +{\shp{\*\shpinst\shplid1250{\sp{\sn relLeft}{\sv 5633}}{\sp{\sn relTop}{\sv 3604}}{\sp{\sn relRight}{\sv 5921}}{\sp{\sn relBottom}{\sv 3892}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 1}}{\sp{\sn lidRegroup}{\sv 20}}}} +{\shp{\*\shpinst\shplid1251{\sp{\sn relLeft}{\sv 6065}}{\sp{\sn relTop}{\sv 3604}}{\sp{\sn relRight}{\sv 6353}}{\sp{\sn relBottom}{\sv 3892}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 1}}{\sp{\sn lidRegroup}{\sv 20}}}} +{\shp{\*\shpinst\shplid1252{\sp{\sn relLeft}{\sv 6497}}{\sp{\sn relTop}{\sv 3604}}{\sp{\sn relRight}{\sv 6785}}{\sp{\sn relBottom}{\sv 3892}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 1}}{\sp{\sn lidRegroup}{\sv 20}}}} +{\shp{\*\shpinst\shplid1253{\sp{\sn relLeft}{\sv 6929}}{\sp{\sn relTop}{\sv 3604}}{\sp{\sn relRight}{\sv 7217}}{\sp{\sn relBottom}{\sv 3892}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 1}}{\sp{\sn lidRegroup}{\sv 20}}}} +{\shp{\*\shpinst\shplid1254{\sp{\sn relLeft}{\sv 7361}}{\sp{\sn relTop}{\sv 3604}}{\sp{\sn relRight}{\sv 7649}}{\sp{\sn relBottom}{\sv 3892}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 1}}{\sp{\sn lidRegroup}{\sv 20}}}} +{\shp{\*\shpinst\shplid1255{\sp{\sn relLeft}{\sv 7793}}{\sp{\sn relTop}{\sv 3604}}{\sp{\sn relRight}{\sv 8081}}{\sp{\sn relBottom}{\sv 3892}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 1}}{\sp{\sn lidRegroup}{\sv 20}}}} +{\shp{\*\shpinst\shplid1256{\sp{\sn relLeft}{\sv 8225}}{\sp{\sn relTop}{\sv 3604}}{\sp{\sn relRight}{\sv 8513}}{\sp{\sn relBottom}{\sv 3892}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 1}}{\sp{\sn lidRegroup}{\sv 20}}}} +{\shp{\*\shpinst\shplid1257{\sp{\sn relLeft}{\sv 8657}}{\sp{\sn relTop}{\sv 3604}}{\sp{\sn relRight}{\sv 8945}}{\sp{\sn relBottom}{\sv 3892}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 1}}{\sp{\sn lidRegroup}{\sv 20}}}} +{\shp{\*\shpinst\shplid1258{\sp{\sn relLeft}{\sv 9089}}{\sp{\sn relTop}{\sv 3604}}{\sp{\sn relRight}{\sv 9377}}{\sp{\sn relBottom}{\sv 3892}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 1}}{\sp{\sn lidRegroup}{\sv 20}}}} +{\shp{\*\shpinst\shplid1259{\sp{\sn relLeft}{\sv 2753}}{\sp{\sn relTop}{\sv 6115}}{\sp{\sn relRight}{\sv 2980}}{\sp{\sn relBottom}{\sv 6342}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 3}}{\sp{\sn lidRegroup}{\sv 20}}}} +{\shp{\*\shpinst\shplid1260{\sp{\sn relLeft}{\sv 2753}}{\sp{\sn relTop}{\sv 4326}}{\sp{\sn relRight}{\sv 3329}}{\sp{\sn relBottom}{\sv 5190}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 1}}{\sp{\sn lidRegroup}{\sv 20}}}} +{\shp{\*\shpinst\shplid1261{\sp{\sn relLeft}{\sv 3041}}{\sp{\sn relTop}{\sv 4326}}{\sp{\sn relRight}{\sv 3041}}{\sp{\sn relBottom}{\sv 5190}}{\sp{\sn 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0}} +{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}{\sp{\sn lidRegroup}{\sv 20}}}} +{\shp{\*\shpinst\shplid1265{\sp{\sn relLeft}{\sv 4481}}{\sp{\sn relTop}{\sv 2890}}{\sp{\sn relRight}{\sv 4481}}{\sp{\sn relBottom}{\sv 3178}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}} +{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}{\sp{\sn lidRegroup}{\sv 20}}}}{\shp{\*\shpinst\shplid1266{\sp{\sn relLeft}{\sv 4625}}{\sp{\sn relTop}{\sv 2890}} +{\sp{\sn relRight}{\sv 4625}}{\sp{\sn relBottom}{\sv 3178}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}} +{\sp{\sn lidRegroup}{\sv 20}}}}{\shp{\*\shpinst\shplid1267{\sp{\sn relLeft}{\sv 4769}}{\sp{\sn relTop}{\sv 2890}}{\sp{\sn relRight}{\sv 4769}}{\sp{\sn relBottom}{\sv 3178}}{\sp{\sn fRelFlipH}{\sv 0}} +{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}{\sp{\sn lidRegroup}{\sv 20}}}} +{\shp{\*\shpinst\shplid1268{\sp{\sn relLeft}{\sv 4913}}{\sp{\sn relTop}{\sv 2890}}{\sp{\sn relRight}{\sv 4913}}{\sp{\sn relBottom}{\sv 3178}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}} +{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}{\sp{\sn lidRegroup}{\sv 20}}}}{\shp{\*\shpinst\shplid1269{\sp{\sn relLeft}{\sv 5057}}{\sp{\sn relTop}{\sv 2890}} +{\sp{\sn relRight}{\sv 5057}}{\sp{\sn relBottom}{\sv 3178}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}} +{\sp{\sn lidRegroup}{\sv 20}}}}{\shp{\*\shpinst\shplid1270{\sp{\sn relLeft}{\sv 5201}}{\sp{\sn relTop}{\sv 2890}}{\sp{\sn relRight}{\sv 5201}}{\sp{\sn relBottom}{\sv 3178}}{\sp{\sn fRelFlipH}{\sv 0}} +{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}{\sp{\sn lidRegroup}{\sv 20}}}} +{\shp{\*\shpinst\shplid1271{\sp{\sn relLeft}{\sv 5345}}{\sp{\sn relTop}{\sv 2890}}{\sp{\sn relRight}{\sv 5345}}{\sp{\sn relBottom}{\sv 3178}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}} +{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}{\sp{\sn lidRegroup}{\sv 20}}}}{\shp{\*\shpinst\shplid1272{\sp{\sn relLeft}{\sv 5489}}{\sp{\sn relTop}{\sv 2890}} +{\sp{\sn relRight}{\sv 5489}}{\sp{\sn relBottom}{\sv 3178}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}} +{\sp{\sn lidRegroup}{\sv 20}}}}{\shp{\*\shpinst\shplid1273{\sp{\sn relLeft}{\sv 5489}}{\sp{\sn relTop}{\sv 2522}}{\sp{\sn relRight}{\sv 7344}}{\sp{\sn relBottom}{\sv 3177}}{\sp{\sn fRelFlipH}{\sv 0}} +{\sp{\sn fRelFlipV}{\sv 1}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn lineWidth}{\sv 15875}}{\sp{\sn fArrowheadsOK}{\sv 1}}{\sp{\sn fLine}{\sv 1}}{\sp{\sn lidRegroup}{\sv 20}}}} +{\shp{\*\shpinst\shplid1274{\sp{\sn relLeft}{\sv 4176}}{\sp{\sn relTop}{\sv 1515}}{\sp{\sn relRight}{\sv 5472}}{\sp{\sn relBottom}{\sv 1947}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 1}}{\sp{\sn lidRegroup}{\sv 20}}}} +{\shp{\*\shpinst\shplid1275{\sp{\sn relLeft}{\sv 4337}}{\sp{\sn relTop}{\sv 1030}}{\sp{\sn relRight}{\sv 4337}}{\sp{\sn relBottom}{\sv 1462}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 1}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}} +{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}{\sp{\sn lidRegroup}{\sv 20}}}}{\shp{\*\shpinst\shplid1276{\sp{\sn relLeft}{\sv 5345}}{\sp{\sn relTop}{\sv 1030}} +{\sp{\sn relRight}{\sv 5345}}{\sp{\sn relBottom}{\sv 1462}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 1}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}} +{\sp{\sn lidRegroup}{\sv 20}}}}{\shp{\*\shpinst\shplid1277{\sp{\sn relLeft}{\sv 4337}}{\sp{\sn relTop}{\sv 988}}{\sp{\sn relRight}{\sv 5345}}{\sp{\sn relBottom}{\sv 1062}}{\sp{\sn fRelFlipH}{\sv 0}} +{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 0}}{\sp{\sn rotation}{\sv 0}}{\sp{\sn geoRight}{\sv 1008}}{\sp{\sn geoBottom}{\sv 74}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn pVerticies}{\sv 8;13;(1008,42);(838,0);(863,12);(608,26) +;(486,67);(545,51);(432,74);(288,38);(346,56);(256,26);(11,42);(96,42);(0,42)}}{\sp{\sn pSegmentInfo}{\sv 2;11;16384;44800;8193;44800;8193;44800;8193;44800;8193;44032;32768}}{\sp{\sn fFillOK}{\sv 1}}{\sp{\sn fFilled}{\sv 0}} +{\sp{\sn fArrowheadsOK}{\sv 1}}{\sp{\sn lidRegroup}{\sv 20}}}}{\shp{\*\shpinst\shplid1278{\sp{\sn relLeft}{\sv 2321}}{\sp{\sn relTop}{\sv 3802}}{\sp{\sn relRight}{\sv 2897}}{\sp{\sn relBottom}{\sv 4666}}{\sp{\sn fRelFlipH}{\sv 0}} +{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn lineWidth}{\sv 19050}}{\sp{\sn fArrowheadsOK}{\sv 1}}{\sp{\sn fLine}{\sv 1}}{\sp{\sn lidRegroup}{\sv 20}}}} +{\shp{\*\shpinst\shplid1279{\sp{\sn relLeft}{\sv 2321}}{\sp{\sn relTop}{\sv 3708}}{\sp{\sn relRight}{\sv 3185}}{\sp{\sn relBottom}{\sv 4428}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}} +{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn lineWidth}{\sv 19050}}{\sp{\sn fArrowheadsOK}{\sv 1}}{\sp{\sn fLine}{\sv 1}}{\sp{\sn lidRegroup}{\sv 20}}}}{\shp{\*\shpinst\shplid1280{\sp{\sn relLeft}{\sv 2609}}{\sp{\sn relTop}{\sv 5778}} +{\sp{\sn relRight}{\sv 2897}}{\sp{\sn relBottom}{\sv 5778}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn lineWidth}{\sv 57150}} +{\sp{\sn fArrowheadsOK}{\sv 1}}{\sp{\sn fLine}{\sv 1}}{\sp{\sn lidRegroup}{\sv 20}}}}{\shp{\*\shpinst\shplid1281{\sp{\sn relLeft}{\sv 2609}}{\sp{\sn relTop}{\sv 5922}}{\sp{\sn relRight}{\sv 2897}}{\sp{\sn relBottom}{\sv 5922}}{\sp{\sn fRelFlipH}{\sv 0}} +{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn lineWidth}{\sv 57150}}{\sp{\sn fArrowheadsOK}{\sv 1}}{\sp{\sn fLine}{\sv 1}}{\sp{\sn lidRegroup}{\sv 20}}}} +{\shp{\*\shpinst\shplid1282{\sp{\sn relLeft}{\sv 2321}}{\sp{\sn relTop}{\sv 5661}}{\sp{\sn relRight}{\sv 2609}}{\sp{\sn relBottom}{\sv 5805}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}} +{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn lineWidth}{\sv 12700}}{\sp{\sn fArrowheadsOK}{\sv 1}}{\sp{\sn fLine}{\sv 1}}{\sp{\sn lidRegroup}{\sv 20}}}}{\shp{\*\shpinst\shplid1283{\sp{\sn relLeft}{\sv 2177}}{\sp{\sn relTop}{\sv 5661}} +{\sp{\sn relRight}{\sv 2609}}{\sp{\sn relBottom}{\sv 5949}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn lineWidth}{\sv 12700}} +{\sp{\sn fArrowheadsOK}{\sv 1}}{\sp{\sn fLine}{\sv 1}}{\sp{\sn lidRegroup}{\sv 20}}}}{\shp{\*\shpinst\shplid1284{\sp{\sn relLeft}{\sv 4032}}{\sp{\sn relTop}{\sv 6123}}{\sp{\sn relRight}{\sv 4145}}{\sp{\sn relBottom}{\sv 6236}}{\sp{\sn fRelFlipH}{\sv 0}} +{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 3}}{\sp{\sn lidRegroup}{\sv 20}}}}{\shp{\*\shpinst\shplid1285{\sp{\sn relLeft}{\sv 4320}}{\sp{\sn relTop}{\sv 6123}}{\sp{\sn relRight}{\sv 4433}}{\sp{\sn relBottom}{\sv 6236}}{\sp{\sn fRelFlipH}{\sv 0}} +{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 3}}{\sp{\sn lidRegroup}{\sv 20}}}}{\shp{\*\shpinst\shplid1286{\sp{\sn relLeft}{\sv 4608}}{\sp{\sn relTop}{\sv 6123}}{\sp{\sn relRight}{\sv 4721}}{\sp{\sn relBottom}{\sv 6236}}{\sp{\sn fRelFlipH}{\sv 0}} +{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 3}}{\sp{\sn lidRegroup}{\sv 20}}}}}{\shprslt{\*\do\dobxcolumn\dobypara\dodhgt8196\dppolygon\dppolycount4\dpptx0\dppty0\dpptx9199\dppty0\dpptx9199\dppty5492\dpptx0\dppty5492 +\dpx1026\dpy-267\dpxsize9199\dpysize5492\dpfillfgcr255\dpfillfgcg255\dpfillfgcb255\dpfillbgcr255\dpfillbgcg255\dpfillbgcb255\dpfillpat1\dplinew15\dplinecor0\dplinecog0\dplinecob0}}}}{\fs26 \tab \tab \tab \tab }{10-WAY CONNECTING LEAD WITH SOCKETS +\par }{\fs26 +\par }\pard \qj\fi720\li4320\sa240\nowidctlpar\tx2835\adjustright {10-WAY RIGHT ANGLE WAFER PLUG +\par }\pard \qj\nowidctlpar\tx2835\adjustright {15-WAY SINGLE}{\cgrid }{ +\par SIDED}{\cgrid }{ +\par EDGECARD}{\cgrid }{ +\par }\pard \qj\nowidctlpar\tx1134\tx2835\adjustright {SOCKETS}{\fs26 +\par }\pard\plain \s20\qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {\fs26\cgrid +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {\fs26 +\par +\par }\pard \qj\nowidctlpar\tx2835\adjustright {\fs24 100nDisc}{\fs26 +\par }{\fs18 CERAMIC}{\fs18\cgrid }{\fs18 +\par CAPACITORS}{\fs18\cgrid }{\fs18 +\par }\pard \qj\sa240\nowidctlpar\tx2835\adjustright {\fs26 +\par }\pard \qj\li2591\nowidctlpar\tx2835\adjustright {\fs24 +\par }\pard \qj\sa240\nowidctlpar\tx2835\adjustright {Figure 7 Keyboard assembly +\par iii) Plug the other end of the ribbon cable into PL14 on the PCB. +\par iv) Test for continuity between the following points for each edge connector in turn: +\par }\pard \qj\ri-28\nowidctlpar\tx2835\adjustright {Edge connector pin number \tab 6 7 8 9 10 11 12 13 14 15 +\par }\pard \qj\ri-27\sa240\nowidctlpar\tx2835\adjustright { IC37 pin number \tab 1 3 4 5 6 7 10 11 13 14 +\par }\pard \qj\sa240\nowidctlpar\tx2835\adjustright {Note: on the edge connector pin 1 is nearest the loudspeaker, thus the polarising key is pin 3, and pins 4 and 5 are empty. +\par Also check that there are no short circuits between any of the edge connector pins. +\par v) Insert IC29 and IC37 into their sockets on the PCB. +\par vi) Turn the computer on and type: +\par REPEAT SOUND-1, GET, 0, 0: UNTIL0 +\par and press the RETURN key. +\par Any key now pressed should cause the system to utter a word or sound. +\par vii) Adjust VR1 until the speech is at the correct pitch. This can be measured by connecting a frequency meter to pin 3 IC29. Adjust VR1 until the meter reads 160kHz +/-100Hz. +\par viii) Remove the perforated section from the left of the case lid, fit the ROM socket cover, and reassemble the machine. +\par ix) Test using a PORT tester. +\par }\pard\plain \s1\qj\sa240\nowidctlpar\tx2835\outlinelevel0\adjustright \b\f2 {\fs22 \page }{7 Selection links +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {This section describes the function of each of the links on the PCB, the type of link, and its position as standard. +\par S1 PCB track, made West: West for 5 1/4 disc drive, East for 8". +\par S2 PCB track, made North: North for 5 1/4" disc drive, South for 8". +\par S3 PCB track, made South: South for 5 1/4" disc drive, North for 8". +\par S4 PCB track, made South: South for 5 1/4" disc drive, North for 8". +\par S5 wire link, not fitted: allows disc filing system to disable NMI. This feature is not supported by current disc software. +\par S6 PCB track, made South: South for 5 1/4" disc drive, North for 8". +\par S7 plug, made East: East for 1770 floppy disc controller, West for 8271. +\par S8 plug, fitted: fitted for 1770 floppy disc controller, removed for 8271. +\par S9 plug, made West: West for 8K/16K ROM/EPROM in IC35, East for 32K ROM/EPROM in IC35. +\par S10 PCB track, made East: East enables keyboard BREAK key, West forces permanent reset, broken (neither East nor West) disables BREAK key. +\par S11 plug, made West: West for 8K/16K ROM/EPROM in IC44, East for 32K ROM/EPROM in IC44. +\par S12 plug, made West: West for 8K/16K ROM/EPROM in IC57, East for 32K ROM/EPROM in IC57. +\par S13 plug, made South: South causes BASIC to take high priority ROM numbers 14/15, North causes BASIC to take low priority ROM numbers 0/1. +\par S14 plug, made North: North gives white on black video, South gives black on white video. Beware monitor performance in the latter configuration. +\par S15 plug, made West: West for 8K/l6K ROM/EPROM in IC62, East for 32K ROM/EPROM in IC62. +\par S16 \endash test link not present on issue 2 or later PCB. +\par S17 PCB track, made North: North configures 1MHz bus audio for input, South for output. +\par S18 plug, made West: West for 8K/16K ROM/EPROM in IC68, East for 32K ROM/EPROM in IC68. +\par \page S19 PCB track, made East: East enables BASIC part of OS/BASIC, West disables BASIC and leaves just the operating system. +\par S20 plug, made South: South gives full volume on audio. Remove if VR2 fitted. +\par S21 \endash optional audio output prior to volume control. +\par S22 \endash +\par S23 eight plugs, seven shunts: ECONET ID number set up as binary number by user. Only fitted if ECONET interface fitted. +\par S24 wire link, not fitted: optional termination resistor for RS423. Should not be fitted for correct operation of RS423. +\par S25 wire link, not fitted: optional termination resistor for RS423. Should not be fitted for correct operation of RS423. +\par S26 wire link, not fitted: made adds chrominance component to composite video output. +\par S27 plug, made South: South gives negative-going CSYNC for RGB, North gives positive-going CSYNC. +\par S28 PCB track, made North: North for PAL video circuitry, South for NTSC. Note: for NTSC operation R92 must be cut out. The modulator may need changing for TVs which cannot receive channel 36. +\par S29 PCB track, made: made for operating ECONET without collision detect hardware. Collisions are detected by software protocols. +\par S30 PCB link, made: always made for 6512 CPU. +\par }\pard\plain \s1\qj\sa240\nowidctlpar\tx2835\outlinelevel0\adjustright \b\f2 {\page 8 Test equipment +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {A PORT tester is available for the microcomputer. This is an uprated version of the old + FIT tester. It will check the DRAMs, and all the I/O ports on the microcomputer: disc, printer, user, 1MHz bus, TUBE, UHF, video, RGB, RS423, cassette, A to D, and ECONET. To use this tester, the microcomputer must at least have the CPU running and the M +OS/BASIC ROM working and some of the RAM working. +\par Full operating instructions are supplied with the equipment. +\par }\pard\plain \s1\qj\sa240\nowidctlpar\tx2835\outlinelevel0\adjustright \b\f2 {\page 9 Fault finding +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {This section goes step by step through fault finding in each section of hardware. It should be studied in conjunction with the circuit diagram and block diagram in the Appendix. + +\par If any part of the machine is suspected of being faulty, the following points should always be checked first: +\par 1 no loose connectors and broken cables +\par 2 no broken or shorting tracks +\par 3 ICs plugged into their sockets correctly +\par 4 power supply working and reaching the components concerned +\par 5 all digital signals are at clean TTL logic levels (greater than 2.4V for 1, less than 0.5V for 0). On timed signals this must be true for the period 150ns before phi2 on read cycles and 300ns before phi2 on write cycles. +\par The following items of test equipment are required for fault finding: +\par PORT tester +\par 10A Multimeter +\par logic probe +\par 20MHz dual beam oscilloscope +\par TV, composite monitor, colour monitor +\par cassette player +\par disc drive +\par frequency counter +\par 5 ohm 5W resistor +\par }\pard\plain \s2\sa240\keepn\nowidctlpar\tx2835\outlinelevel1\adjustright \b\f2\lang2057 {9.1 Switch on +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {Connect the suspect microcomputer to a UHF TV and an RGB monitor. Connect the mains supply and switch on both the monitors and the computer. One of the following will happen. +\par a) There is noise on the monitor screens (no signal from computer). There is no power-on beep sound (there may be a continuous noise), and the LEDs do not light, or light incorrectly. +\par Results: either power supply is dead, or there is a fault in the heart of the microcomputer. +\par }{\b \page }{Follow the sequence of checks shown below. +\par 1 If there is no noise on power-up, and no LEDs light up then check the power supply (see 9.2). +\par 2 If a PET tester is available then use it. The PET tester will work on the B+ providing the CPU is running and it can access +the ROM, although it may give strange screen output, and some of the tests will fail. Please refer to the information manual supplied to dealers for details of the operation of the PET tester when used with the B+. If PET will not work at all then either +the CPU isn't running or it cannot access the ROM. +\par 3 Check HS and VS signals (pin 39 and pin 40 IC78) using an oscilloscope. HS and VS should be clean TTL voltage levels, HS pulsing every 64\'b5s and VS pulsing every 20ms. +\par Results: if they are stuck or floatin +g then carry on with the checks be1ow. If they are working then the CPU must have programmed the 6845 and so must have gained access to the OS ROM. Check using PET (see information manual supplied to dealers). If the signals are there but are not pulsing +at the correct intervals then look for a data line fault to CRTC. +\par 4 Check that the notRS pin of the CPU (pin 40 IC42) is high when the computer is switched on. It should pulse low on power-up and when the BREAK key is pressed. If it is stuck low then look for shorts or damaged components around the 555. +\par 5 Check that there is activity on the SYNC (pin 7 IC42) and the R/notW (pin 34 IC42) lines of the CPU. If SYNC is stuck then the CPU has stalled, and R/notW won't be working anyway. Check for address and data + bus short or open circuit, or a complete failure to select the OS ROM (see 9.5). +\par 6 Check the CPU clocks. Phi1 and phi2 should be as shown in figure 1 (see section 5.2). If not then check the 2M circuitry from the video processor IC53. IC33 pin 3 should be + low. If not then check SYNC 1M at pin 8 IC41 which should also be low. If SYNC 1M is high then check IC25. If SYNC 1M is stuck high then find which one of the inputs to IC41 is stuck low. The 1MHz device attached to this input must be checked. +\par 7 Check act +ivity on the CPU address lines. If after a BREAK the activity starts and then stops, this suggests that the CPU cannot read the OS ROM. Check the OS ROM by replacing it with a known good one. Check that it is enabled and that all address lines are present +. Check following BREAK that notOE pulses low at 2MHz (inverse of phi2), and notCS goes low and stays low for a time. +\par 8 Check all clocks from video processor 8M 4M 2M 1M, see 9.3. +\par 9 After BREAK check CRTC notCS pin pulses low (pin 25 IC78). +\par If all the above checks pass then the machine should do more than exhibit the symptoms stated in (a). +\par }{\b \page }{b) The screen synchronises (no noise) but there is only a flashing cursor in the top left corner. +\par Results: usually caused by a keyboard fault. +\par Check that the keyboard is connected correctly, see 9.9. +\par c) The banner message appears, but is incorrect or incomplete. +\par The correct banner message is: +\par Acorn OS 64K +\par +\par +\par > +\par For example, with a 1770 FM disc filing system and BASIC language the correct banner message is: +\par Acorn OS 64K +\par 1770 DFS +\par BASIC +\par > +\par Results: the CPU is running and is accessing the OS. Use a PET tester if available (see information manua1 supplied to dealers). If the banner message is fragmented then check the CRTC address lines for shorts. If the message gives the prompt +\par Language? +\par where BASIC is fitted in the example above check S13 and also check the Pg latch. Language? cannot occur when it is a badly fitted IC since the OS and the BASIC are in the same ROM. A badly fitted OS/ROM would prevent the machine powering up. +\par d) The machine does a start-up beep, and the caps lock LED comes on, but there is no display, or no display on the UHF monitor. +\par Results: the video circuitry is faulty, see 9.7. +\par e) There is no fault on power-up. +\par Results: most I/O faults will not stop the computer and display from working. Use a PORT tester to find out which I/O circuit is faulty. +\par }\pard\plain \s2\sa240\keepn\nowidctlpar\tx2835\outlinelevel1\adjustright \b\f2\lang2057 {\fs22 \page }{9.2 Power supply +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {With the power supply turned off, unplug the three black 0V leads and the three red +5V leads and the single purple -5V lead from the PCB. +\par Connect a 5 ohm 5W resistor across one pair of red and black leads (a pair that were together on the board) and tape the other leads with insulating tap +e to stop them shorting. Turn on the power supply and measure the voltage across the resistor using an oscilloscope. The voltage must be in the range 4.9V to 5.1V, with a maximum noise of 50mV peak to peak. WARNING: the resistor will get hot. +\par Repeat the test with the other two pairs of red and black leads. +\par Results: if any one pair measures zero or a very low voltage then one of the leads is damaged. If all are out of spec then the power supply unit must be changed. +\par If the +5V lines are good, leave the resis +tor in place on the last pair and using the other trace on the oscilloscope measure the -5V voltage. Connect both probes to 0V and superimpose the traces in the center of the CRT. Connect one probe to +5V (across the resistor) and the other to -5V (the pu +rple lead). The two traces should deflect in opposite directions, the -5V being between -4.75V and -5.25V. +\par When all the voltages are correct, switch off the power supply and reconnect the black leads to the PCB on the connectors marked 0V. +\par Set the multimete +r to a 10A DC scale and connect it between one of the connectors on the PCB marked VCC and all three red wires together. Turn on the power supply just long enough to measure the current (any length of time may heat up the PCB tracks excessively). The boar +d should draw from 1.5 to 2.2A, depending on its upgrade state. +\par Repeat the test, after turning off the power supply, for each of the three +5V connectors on the PCB in turn. +\par Results: if the current at any one connector is zero or very low then look for a br +oken lead, connector, or PCB track. If all results are zero then there is either a short circuit and the power supply has cut out (likely) or the whole power network has gone open circuit (unlikely). This can be checked by measuring the +5V voltage across + the board. Zero voltage means short circuit, +5V means open circuit. +\par Replace all the power supply leads in their correct positions, red to VCC, black to 0V, and the purple lead to -5V. +\par As a final check, measure the voltage across the power supply pins of a few ICs around the board and check that it is in spec. +\par }\pard\plain \s2\sa240\keepn\nowidctlpar\tx2835\outlinelevel1\adjustright \b\f2\lang2057 {\b0\fs22 \page }{9.3 Oscillator and divider circuitry +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {Using the oscilloscope, check that 8MHz, 4MHz, 2MHz, and 1MHz are available from pins 7, 6, 5, and 4 respectively of the video processor IC53. +\par Results: if these signals are not present then check that 16MHz is available at pin 8 IC53. If it is then replace IC53. If not then check the crystal controlled oscillator circuit formed by half of IC26 and X1. +\par Check that the CPU has two non-overlapping 2MHz clock inputs on pins 3 (phi1) and 37 (phi2) of IC42, as shown in figure 1. +\par Check that 1E is available at pin 6 IC25. This signal should be phase shifted in relation to 1M at pin 4 IC53 as shown in figure 8. +\par }{\fs24 +\par }{\lang1024\cgrid {\shpgrp{\*\shpinst\shpleft865\shptop24\shpright9217\shpbottom930\shpfhdr0\shpbxcolumn\shpbypara\shpwr3\shpwrk0\shpfblwtxt0\shpz5\shplid1287{\sp{\sn groupLeft}{\sv 2016}}{\sp{\sn groupTop}{\sv 5718}}{\sp{\sn groupRight}{\sv 10368}} +{\sp{\sn groupBottom}{\sv 6624}}{\sp{\sn fFlipH}{\sv 0}}{\sp{\sn fFlipV}{\sv 0}}{\shp{\*\shpinst\shplid1288{\sp{\sn relLeft}{\sv 2016}}{\sp{\sn relTop}{\sv 6624}}{\sp{\sn relRight}{\sv 2592}} +{\sp{\sn relBottom}{\sv 6624}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}}} +{\shp{\*\shpinst\shplid1289{\sp{\sn relLeft}{\sv 2609}}{\sp{\sn relTop}{\sv 5718}}{\sp{\sn relRight}{\sv 2753}}{\sp{\sn relBottom}{\sv 6582}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 1}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}} +{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}}}{\shp{\*\shpinst\shplid1290{\sp{\sn relLeft}{\sv 2753}}{\sp{\sn relTop}{\sv 5718}}{\sp{\sn relRight}{\sv 4769}}{\sp{\sn relBottom}{\sv 5718}}{\sp{\sn fRelFlipH}{\sv 0}} +{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}}}{\shp{\*\shpinst\shplid1291{\sp{\sn relLeft}{\sv 4769}}{\sp{\sn relTop}{\sv 5718}} +{\sp{\sn relRight}{\sv 4913}}{\sp{\sn relBottom}{\sv 6582}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}}} +{\shp{\*\shpinst\shplid1292{\sp{\sn relLeft}{\sv 4896}}{\sp{\sn relTop}{\sv 6624}}{\sp{\sn relRight}{\sv 7056}}{\sp{\sn relBottom}{\sv 6624}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}} +{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}}}{\shp{\*\shpinst\shplid1293{\sp{\sn relLeft}{\sv 7073}}{\sp{\sn relTop}{\sv 5718}}{\sp{\sn relRight}{\sv 7217}}{\sp{\sn relBottom}{\sv 6582}}{\sp{\sn fRelFlipH}{\sv 0}} +{\sp{\sn fRelFlipV}{\sv 1}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}}}{\shp{\*\shpinst\shplid1294{\sp{\sn relLeft}{\sv 7217}}{\sp{\sn relTop}{\sv 5718}} +{\sp{\sn relRight}{\sv 9377}}{\sp{\sn relBottom}{\sv 5718}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}}} +{\shp{\*\shpinst\shplid1295{\sp{\sn relLeft}{\sv 9377}}{\sp{\sn relTop}{\sv 5718}}{\sp{\sn relRight}{\sv 9521}}{\sp{\sn relBottom}{\sv 6582}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}} +{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}}}{\shp{\*\shpinst\shplid1296{\sp{\sn relLeft}{\sv 9504}}{\sp{\sn relTop}{\sv 6624}}{\sp{\sn relRight}{\sv 10368}}{\sp{\sn relBottom}{\sv 6624}}{\sp{\sn fRelFlipH}{\sv 0}} +{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}}}}{\shprslt{\*\do\dobxcolumn\dobypara\dodhgt8197\dppolygon\dppolycount4\dpptx0\dppty0 +\dpptx8352\dppty0\dpptx8352\dppty906\dpptx0\dppty906\dpx865\dpy24\dpxsize8352\dpysize906\dpfillfgcr255\dpfillfgcg255\dpfillfgcb255\dpfillbgcr255\dpfillbgcg255\dpfillbgcb255\dpfillpat1\dplinew15\dplinecor0\dplinecog0\dplinecob0}}}}{\fs24 +\par }{\f1\fs32 1M +\par }{\fs30 +\par }{\lang1024\cgrid {\shpgrp{\*\shpinst\shpleft865\shptop9\shpright9234\shpbottom729\shpfhdr0\shpbxcolumn\shpbypara\shpwr3\shpwrk0\shpfblwtxt0\shpz6\shplid1297{\sp{\sn groupLeft}{\sv 2016}}{\sp{\sn groupTop}{\sv 7375}}{\sp{\sn groupRight}{\sv 10385}} +{\sp{\sn groupBottom}{\sv 8095}}{\sp{\sn fFlipH}{\sv 0}}{\sp{\sn fFlipV}{\sv 0}}{\shp{\*\shpinst\shplid1298{\sp{\sn relLeft}{\sv 2016}}{\sp{\sn relTop}{\sv 8064}}{\sp{\sn relRight}{\sv 3600}} +{\sp{\sn relBottom}{\sv 8064}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}}} +{\shp{\*\shpinst\shplid1299{\sp{\sn relLeft}{\sv 3617}}{\sp{\sn relTop}{\sv 7375}}{\sp{\sn relRight}{\sv 3761}}{\sp{\sn relBottom}{\sv 8095}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 1}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}} +{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}}}{\shp{\*\shpinst\shplid1300{\sp{\sn relLeft}{\sv 3761}}{\sp{\sn relTop}{\sv 7375}}{\sp{\sn relRight}{\sv 5921}}{\sp{\sn relBottom}{\sv 7375}}{\sp{\sn fRelFlipH}{\sv 0}} +{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}}}{\shp{\*\shpinst\shplid1301{\sp{\sn relLeft}{\sv 5921}}{\sp{\sn relTop}{\sv 7375}} +{\sp{\sn relRight}{\sv 6065}}{\sp{\sn relBottom}{\sv 8095}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}}} +{\shp{\*\shpinst\shplid1302{\sp{\sn relLeft}{\sv 6048}}{\sp{\sn relTop}{\sv 8064}}{\sp{\sn relRight}{\sv 8352}}{\sp{\sn relBottom}{\sv 8064}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}} +{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}}}{\shp{\*\shpinst\shplid1303{\sp{\sn relLeft}{\sv 8369}}{\sp{\sn relTop}{\sv 7375}}{\sp{\sn relRight}{\sv 8513}}{\sp{\sn relBottom}{\sv 8095}}{\sp{\sn fRelFlipH}{\sv 0}} +{\sp{\sn fRelFlipV}{\sv 1}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}}}{\shp{\*\shpinst\shplid1304{\sp{\sn relLeft}{\sv 8513}}{\sp{\sn relTop}{\sv 7375}} +{\sp{\sn relRight}{\sv 10385}}{\sp{\sn relBottom}{\sv 7375}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}}} +}{\shprslt{\*\do\dobxcolumn\dobypara\dodhgt8198\dppolygon\dppolycount4\dpptx0\dppty0\dpptx8369\dppty0\dpptx8369\dppty720\dpptx0\dppty720\dpx865\dpy9\dpxsize8369\dpysize720 +\dpfillfgcr255\dpfillfgcg255\dpfillfgcb255\dpfillbgcr255\dpfillbgcg255\dpfillbgcb255\dpfillpat1\dplinew15\dplinecor0\dplinecog0\dplinecob0}}}}{\f1\fs32 1E +\par }{ +\par Figure 8 1M/1E +\par }\pard\plain \s20\qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 { +\par }\pard\plain \s2\sa240\keepn\nowidctlpar\tx2835\outlinelevel1\adjustright \b\f2\lang2057 {9.4 CPU +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {Test pin 40 IC42 (reset pin) and check that it is high. Press the BREAK key and make sure that pin 40 goes low for a reset and then high again on release. +\par Results: if pin 40 is stuck low then check for a short circuit on the main PCB, the keyboard, BREAK key, keyboa +rd connectors or the resistors and capacitors of the 555 reset circuitry. If it is stuck high then check the 555 timer circuit (IC43), the keyboard ribbon cable and connectors, and the BREAK key itself. +\par Check that notIRQ (pin 4) and R/notW (pin 34) are wobbling. If not then test SYNC (pin 7). If SYNC is stuck either high or low then the processor is stalled. +\par Results: if CPU is stalled then check that ROMs are plugged in their sockets correctly. Check for address and data bus short or open circuit. +\par }\pard\plain \s2\sa240\keepn\nowidctlpar\tx2835\outlinelevel1\adjustright \b\f2\lang2057 {\fs22 \page }{9.5 ROM +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {If ROM circuitry is not functioning then the CPU will not operate. Check that all ROMs are inserted with all the pins correctly in their sockets. +\par Use a PET tester if available (see information manual supplied to dealers). If this runs then the CPU is functioning correctly. +\par If the CPU cannot access the OS, check that the OS ROM is enabled and that all address lines are present. Check following BREAK that notOE pulses low at 2MHz (inverse of phi2), and notCS goes low and stays low for a time. Replace the OS/B +ASIC ROM with a known good one. Make sure that S19 is made East. +\par If machine works, but sideways ROM selection is faulty, then run the following program to test the ROM select latch. +\par }\pard\plain \s25\qj\li284\nowidctlpar\tx284\tx2835\adjustright \f2\fs22\lang2057 {\tab 10 romsel% = &FE30 +\par \tab 20 INPUT romnumber% +\par \tab 30 DIM P% 100 +\par \tab 40 [ +\par \tab 50 .start% +\par \tab 60 LDA# romnumber% +\par \tab 70 STA romsel% +\par \tab 80 RTS +\par \tab 90 ] +\par }\pard \s25\qj\li284\sa240\nowidctlpar\tx284\tx2835\adjustright {\tab 100 CALL start% +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {Run the program and type in a number between 0 and 15 (&0 and &F). Check using a logic probe or oscilloscope that the binary representation of this number appea +rs on pins 11 (most significant), 12, 13, and 14 (least significant) of IC45. +\par Results: if the ROM numbers are not getting through to the ROM latch then alter line 80 of the program to +\par 80 JMP start% +\par and re-run the program. +\par Check with an oscilloscope that notPGLD from pin 13 IC36 is wobbling. If not then check for shorted track. If notPGLD is working then replace IC45. +\par If ROM latch contains correct ROM number but sideways ROMs still do not work then check decoder IC46. +\par }\pard\plain \s2\sa240\keepn\nowidctlpar\tx2835\outlinelevel1\adjustright \b\f2\lang2057 {\fs22 \page }{9.6 DRAMs +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {Use a PORT tester to carry out a RAM check. +\par Check that RAS and CAS (pins 4 and 15 respectively of the eight DRAM ICs) are wobbling. +\par Results: if RAS is stalled low then the DRAM ICs may be destroyed. Check the circuitry for generating RAS and CAS (the video processor IC53 8M, 4M, and 2M, half of IC31, and various gates). Check that RAS and CAS timing is as shown in figure 6. +\par Check that RAM data lines are wobbling. +\par Check that the data bus buffer is being enabled, pin 19 IC49. +\par }\pard\plain \s2\sa240\keepn\nowidctlpar\tx2835\outlinelevel1\adjustright \b\f2\lang2057 {9.7 Video +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {Look at the displays from the three monitors (UHF, video, and RGB) and see which of the following, (a), (b), (c), or (d) best describes them. +\par a) None of the monitors operate. +\par Results: there are incorrect signals coming from the video processor. Replace the video processor IC53. +\par Run the following program and check that video processor is being selected (pin 3 IC53 is wobbling). +\par }\pard\plain \s25\qj\li284\nowidctlpar\tx284\tx2835\adjustright \f2\fs22\lang2057 {\tab 10 vidproc% = &FE20 +\par \tab 20 DIM P% 100 +\par \tab 30 [ +\par \tab 40 . start% +\par \tab 50 STA vidproc% +\par \tab 60 JMP start% +\par \tab 70 ] +\par }\pard \s25\qj\li284\sa240\nowidctlpar\tx284\tx2835\adjustright {\tab 80 CALL start% +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {b) The RGB works but the UHF doesn't. Test the UHF modulator input voltage +using an oscilloscope. Set the oscilloscope to 50mV per division, 10 microseconds per division, auto trigger, and attach the probe to the wire running through the white plastic boss in the center of the left side of the modulator. +\par \page Press the BREAK key and check that the PAL voltage waveform looks something like figure 9. +\par }{\lang1024\cgrid {\shpgrp{\*\shpinst\shpleft1\shptop66\shpright9074\shpbottom4446\shpfhdr0\shpbxcolumn\shpbypara\shpwr3\shpwrk0\shpfblwtxt0\shpz52\shplid1305{\sp{\sn groupLeft}{\sv 1152}}{\sp{\sn groupTop}{\sv 1524}}{\sp{\sn groupRight}{\sv 10225}} +{\sp{\sn groupBottom}{\sv 5904}}{\sp{\sn fFlipH}{\sv 0}}{\sp{\sn fFlipV}{\sv 0}}{\shp{\*\shpinst\shplid1306{\sp{\sn relLeft}{\sv 1296}}{\sp{\sn relTop}{\sv 1682}}{\sp{\sn relRight}{\sv 1296}} +{\sp{\sn relBottom}{\sv 4706}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}{\sp{\sn lidRegroup}{\sv 4}}}} +{\shp{\*\shpinst\shplid1307{\sp{\sn relLeft}{\sv 1169}}{\sp{\sn relTop}{\sv 1659}}{\sp{\sn relRight}{\sv 1457}}{\sp{\sn relBottom}{\sv 1659}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}} +{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}{\sp{\sn lidRegroup}{\sv 4}}}}{\shp{\*\shpinst\shplid1308{\sp{\sn relLeft}{\sv 1152}}{\sp{\sn relTop}{\sv 2546}} +{\sp{\sn relRight}{\sv 1440}}{\sp{\sn relBottom}{\sv 2546}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}} +{\sp{\sn lidRegroup}{\sv 4}}}}{\shp{\*\shpinst\shplid1309{\sp{\sn relLeft}{\sv 1152}}{\sp{\sn relTop}{\sv 3698}}{\sp{\sn relRight}{\sv 1440}}{\sp{\sn relBottom}{\sv 3698}}{\sp{\sn fRelFlipH}{\sv 0}} +{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}{\sp{\sn lidRegroup}{\sv 4}}}} +{\shp{\*\shpinst\shplid1310{\sp{\sn relLeft}{\sv 1152}}{\sp{\sn relTop}{\sv 4706}}{\sp{\sn relRight}{\sv 1440}}{\sp{\sn relBottom}{\sv 4706}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}} +{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}{\sp{\sn lidRegroup}{\sv 4}}}}{\shp{\*\shpinst\shplid1311{\sp{\sn relLeft}{\sv 2304}}{\sp{\sn relTop}{\sv 2546}} +{\sp{\sn relRight}{\sv 4176}}{\sp{\sn relBottom}{\sv 2546}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}} +{\sp{\sn lidRegroup}{\sv 4}}}}{\shp{\*\shpinst\shplid1312{\sp{\sn relLeft}{\sv 4176}}{\sp{\sn relTop}{\sv 2546}}{\sp{\sn relRight}{\sv 4176}}{\sp{\sn relBottom}{\sv 4562}}{\sp{\sn fRelFlipH}{\sv 0}} +{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}{\sp{\sn lidRegroup}{\sv 4}}}} +{\shp{\*\shpinst\shplid1313{\sp{\sn relLeft}{\sv 4162}}{\sp{\sn relTop}{\sv 4562}}{\sp{\sn relRight}{\sv 4450}}{\sp{\sn relBottom}{\sv 4562}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}} +{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}{\sp{\sn lidRegroup}{\sv 4}}}}{\shp{\*\shpinst\shplid1314{\sp{\sn relLeft}{\sv 4464}}{\sp{\sn relTop}{\sv 1643}} +{\sp{\sn relRight}{\sv 4630}}{\sp{\sn relBottom}{\sv 4562}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 1}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}} +{\sp{\sn lidRegroup}{\sv 4}}}}{\shp{\*\shpinst\shplid1315{\sp{\sn relLeft}{\sv 4625}}{\sp{\sn relTop}{\sv 1614}}{\sp{\sn relRight}{\sv 4625}}{\sp{\sn relBottom}{\sv 3486}}{\sp{\sn fRelFlipH}{\sv 0}} +{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}{\sp{\sn lidRegroup}{\sv 4}}}} +{\shp{\*\shpinst\shplid1316{\sp{\sn relLeft}{\sv 4625}}{\sp{\sn relTop}{\sv 1614}}{\sp{\sn relRight}{\sv 4769}}{\sp{\sn relBottom}{\sv 3486}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 1}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}} +{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}{\sp{\sn lidRegroup}{\sv 4}}}}{\shp{\*\shpinst\shplid1317{\sp{\sn relLeft}{\sv 4769}}{\sp{\sn relTop}{\sv 1614}} +{\sp{\sn relRight}{\sv 4769}}{\sp{\sn relBottom}{\sv 3486}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn 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0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}} +{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}{\sp{\sn lidRegroup}{\sv 4}}}}{\shp{\*\shpinst\shplid1329{\sp{\sn relLeft}{\sv 9930}}{\sp{\sn relTop}{\sv 4609}} +{\sp{\sn relRight}{\sv 9930}}{\sp{\sn relBottom}{\sv 5693}}{\sp{\sn fRelFlipH}{\sv 1}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}} +{\sp{\sn lidRegroup}{\sv 4}}}}{\shp{\*\shpinst\shplid1330{\sp{\sn relLeft}{\sv 4450}}{\sp{\sn relTop}{\sv 4654}}{\sp{\sn relRight}{\sv 4451}}{\sp{\sn relBottom}{\sv 5110}}{\sp{\sn fRelFlipH}{\sv 0}} +{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}{\sp{\sn lidRegroup}{\sv 4}}}} +{\shp{\*\shpinst\shplid1331{\sp{\sn relLeft}{\sv 4458}}{\sp{\sn relTop}{\sv 5065}}{\sp{\sn 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fFilled}{\sv 0}}{\sp{\sn lineEndArrowhead}{\sv 1}}{\sp{\sn fArrowheadsOK}{\sv 1}}{\sp{\sn lidRegroup}{\sv 4}}}} +{\shp{\*\shpinst\shplid1334{\sp{\sn relLeft}{\sv 4163}}{\sp{\sn relTop}{\sv 5745}}{\sp{\sn relRight}{\sv 6467}}{\sp{\sn relBottom}{\sv 5745}}{\sp{\sn fRelFlipH}{\sv 1}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}} +{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn lineEndArrowhead}{\sv 1}}{\sp{\sn fArrowheadsOK}{\sv 1}}{\sp{\sn lidRegroup}{\sv 4}}}}{\shp{\*\shpinst\shplid1335{\sp{\sn relLeft}{\sv 1584}}{\sp{\sn relTop}{\sv 1524}} +{\sp{\sn relRight}{\sv 2304}}{\sp{\sn relBottom}{\sv 1812}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 202}}{\sp{\sn lTxid}{\sv 786432}}{\sp{\sn dxTextLeft}{\sv 0}}{\sp{\sn dyTextTop}{\sv 0}}{\sp{\sn dxTextRight}{\sv 0}} +{\sp{\sn dyTextBottom}{\sv 0}}{\sp{\sn hspNext}{\sv 1335}}{\sp{\sn fLine}{\sv 0}}{\sp{\sn lidRegroup}{\sv 4}}{\shptxt \pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {\f1\fs24\lang3079 3.05V +\par }}}}{\shp{\*\shpinst\shplid1336{\sp{\sn relLeft}{\sv 1584}}{\sp{\sn relTop}{\sv 2418}}{\sp{\sn relRight}{\sv 2304}}{\sp{\sn relBottom}{\sv 2706}}{\sp{\sn fRelFlipH}{\sv 0}} +{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 202}}{\sp{\sn lTxid}{\sv 851968}}{\sp{\sn dxTextLeft}{\sv 0}}{\sp{\sn dyTextTop}{\sv 0}}{\sp{\sn dxTextRight}{\sv 0}}{\sp{\sn dyTextBottom}{\sv 0}}{\sp{\sn hspNext}{\sv 1336}}{\sp{\sn fLine}{\sv 0}} +{\sp{\sn lidRegroup}{\sv 4}}{\shptxt \pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {\f1\fs24\lang3079 2.9V +\par }}}}{\shp{\*\shpinst\shplid1337{\sp{\sn relLeft}{\sv 1584}}{\sp{\sn relTop}{\sv 3555}}{\sp{\sn relRight}{\sv 2304}}{\sp{\sn relBottom}{\sv 3843}}{\sp{\sn fRelFlipH}{\sv 0}} +{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 202}}{\sp{\sn lTxid}{\sv 917504}}{\sp{\sn dxTextLeft}{\sv 0}}{\sp{\sn dyTextTop}{\sv 0}}{\sp{\sn dxTextRight}{\sv 0}}{\sp{\sn dyTextBottom}{\sv 0}}{\sp{\sn hspNext}{\sv 1337}}{\sp{\sn fLine}{\sv 0}} +{\sp{\sn lidRegroup}{\sv 4}}{\shptxt \pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {\f1\fs24\lang3079 2.75V +\par }}}}{\shp{\*\shpinst\shplid1338{\sp{\sn relLeft}{\sv 1584}}{\sp{\sn relTop}{\sv 4563}}{\sp{\sn relRight}{\sv 2304}}{\sp{\sn relBottom}{\sv 4851}}{\sp{\sn fRelFlipH}{\sv 0}} +{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 202}}{\sp{\sn lTxid}{\sv 983040}}{\sp{\sn dxTextLeft}{\sv 0}}{\sp{\sn dyTextTop}{\sv 0}}{\sp{\sn dxTextRight}{\sv 0}}{\sp{\sn dyTextBottom}{\sv 0}}{\sp{\sn hspNext}{\sv 1338}}{\sp{\sn fLine}{\sv 0}} +{\sp{\sn lidRegroup}{\sv 4}}{\shptxt \pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {\f1\fs24\lang3079 2.6V +\par }}}}{\shp{\*\shpinst\shplid1339{\sp{\sn relLeft}{\sv 6147}}{\sp{\sn relTop}{\sv 1971}}{\sp{\sn relRight}{\sv 7587}}{\sp{\sn relBottom}{\sv 2259}}{\sp{\sn fRelFlipH}{\sv 0}} +{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn 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relTop}{\sv 4941}}{\sp{\sn relRight}{\sv 5730}}{\sp{\sn relBottom}{\sv 5229}}{\sp{\sn fRelFlipH}{\sv 0}} +{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 202}}{\sp{\sn lTxid}{\sv 1179648}}{\sp{\sn dxTextLeft}{\sv 0}}{\sp{\sn dyTextTop}{\sv 0}}{\sp{\sn dxTextRight}{\sv 0}}{\sp{\sn dyTextBottom}{\sv 0}}{\sp{\sn hspNext}{\sv 1341}}{\sp{\sn fLine}{\sv 0}} +{\sp{\sn lidRegroup}{\sv 4}}{\shptxt \pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {\f1\fs24\lang3079 4 \'b5s +\par }}}}{\shp{\*\shpinst\shplid1342{\sp{\sn relLeft}{\sv 6594}}{\sp{\sn relTop}{\sv 5616}}{\sp{\sn relRight}{\sv 7314}}{\sp{\sn relBottom}{\sv 5904}}{\sp{\sn fRelFlipH}{\sv 0}} +{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 202}}{\sp{\sn lTxid}{\sv 1245184}}{\sp{\sn dxTextLeft}{\sv 0}}{\sp{\sn dyTextTop}{\sv 0}}{\sp{\sn dxTextRight}{\sv 0}}{\sp{\sn dyTextBottom}{\sv 0}}{\sp{\sn hspNext}{\sv 1342}}{\sp{\sn fLine}{\sv 0}} +{\sp{\sn lidRegroup}{\sv 4}}{\shptxt \pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {\f1\fs24\lang3079 64 \'b5s +\par }}}}{\shp{\*\shpinst\shplid1343{\sp{\sn relLeft}{\sv 4620}}{\sp{\sn relTop}{\sv 1613}}{\sp{\sn relRight}{\sv 5183}}{\sp{\sn relBottom}{\sv 1620}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}} +{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}{\sp{\sn lidRegroup}{\sv 4}}}}{\shp{\*\shpinst\shplid1344{\sp{\sn relLeft}{\sv 4635}}{\sp{\sn relTop}{\sv 3488}} +{\sp{\sn relRight}{\sv 5055}}{\sp{\sn relBottom}{\sv 3488}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}} +{\sp{\sn lidRegroup}{\sv 4}}}}{\shp{\*\shpinst\shplid1345{\sp{\sn relLeft}{\sv 4920}}{\sp{\sn relTop}{\sv 1615}}{\sp{\sn relRight}{\sv 4920}}{\sp{\sn relBottom}{\sv 3487}}{\sp{\sn fRelFlipH}{\sv 0}} +{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}{\sp{\sn lidRegroup}{\sv 4}}}} +{\shp{\*\shpinst\shplid1346{\sp{\sn relLeft}{\sv 4920}}{\sp{\sn relTop}{\sv 1615}}{\sp{\sn relRight}{\sv 5064}}{\sp{\sn relBottom}{\sv 3487}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 1}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}} +{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}{\sp{\sn lidRegroup}{\sv 4}}}}}{\shprslt{\*\do\dobxcolumn\dobypara\dodhgt8244\dppolygon\dppolycount4\dpptx0\dppty0\dpptx9073\dppty0\dpptx9073\dppty4380\dpptx0\dppty4380 +\dpx1\dpy66\dpxsize9073\dpysize4380\dpfillfgcr255\dpfillfgcg255\dpfillfgcb255\dpfillbgcr255\dpfillbgcg255\dpfillbgcb255\dpfillpat1\dplinew15\dplinecor0\dplinecog0\dplinecob0}}}}{\f1\fs24 \tab \tab +\par }{\fs24 +\par +\par +\par +\par +\par +\par +\par +\par +\par }{Figure 9. Black PAL voltage waveform +\par Type in the following: +\par COLOUR 129 : CLS +\par and press RETURN +\par The waveform should now look something like figure 10. +\par }{\lang1024\cgrid {\shpgrp{\*\shpinst\shpleft16\shptop-12\shpright9089\shpbottom4001\shpfhdr0\shpbxcolumn\shpbypara\shpwr3\shpwrk0\shpfblwtxt0\shpz53\shplid1347{\sp{\sn groupLeft}{\sv 1167}}{\sp{\sn groupTop}{\sv 9129}}{\sp{\sn groupRight}{\sv 10240}} +{\sp{\sn groupBottom}{\sv 13142}}{\sp{\sn fFlipH}{\sv 0}}{\sp{\sn fFlipV}{\sv 0}}{\shp{\*\shpinst\shplid1348{\sp{\sn relLeft}{\sv 1311}}{\sp{\sn relTop}{\sv 9287}}{\sp{\sn relRight}{\sv 1311}} +{\sp{\sn relBottom}{\sv 13106}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}{\sp{\sn lidRegroup}{\sv 3}}}} +{\shp{\*\shpinst\shplid1349{\sp{\sn relLeft}{\sv 1184}}{\sp{\sn relTop}{\sv 9264}}{\sp{\sn relRight}{\sv 1472}}{\sp{\sn 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fRelFlipH}{\sv 0}} +{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}{\sp{\sn lidRegroup}{\sv 3}}}} +{\shp{\*\shpinst\shplid1358{\sp{\sn relLeft}{\sv 4784}}{\sp{\sn relTop}{\sv 10194}}{\sp{\sn relRight}{\sv 4928}}{\sp{\sn relBottom}{\sv 12066}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 1}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}} +{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}{\sp{\sn lidRegroup}{\sv 3}}}}{\shp{\*\shpinst\shplid1359{\sp{\sn relLeft}{\sv 5078}}{\sp{\sn relTop}{\sv 10194}} +{\sp{\sn relRight}{\sv 5078}}{\sp{\sn relBottom}{\sv 12066}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}} +{\sp{\sn lidRegroup}{\sv 3}}}}{\shp{\*\shpinst\shplid1360{\sp{\sn relLeft}{\sv 5078}}{\sp{\sn relTop}{\sv 10194}}{\sp{\sn relRight}{\sv 5222}}{\sp{\sn relBottom}{\sv 12066}}{\sp{\sn fRelFlipH}{\sv 0}} +{\sp{\sn fRelFlipV}{\sv 1}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}{\sp{\sn lidRegroup}{\sv 3}}}} +{\shp{\*\shpinst\shplid1361{\sp{\sn relLeft}{\sv 5222}}{\sp{\sn relTop}{\sv 10194}}{\sp{\sn relRight}{\sv 5222}}{\sp{\sn relBottom}{\sv 11105}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}} +{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}{\sp{\sn lidRegroup}{\sv 3}}}}{\shp{\*\shpinst\shplid1362{\sp{\sn relLeft}{\sv 5210}}{\sp{\sn relTop}{\sv 11126}} +{\sp{\sn relRight}{\sv 9919}}{\sp{\sn relBottom}{\sv 11126}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}} +{\sp{\sn lidRegroup}{\sv 3}}}}{\shp{\*\shpinst\shplid1363{\sp{\sn relLeft}{\sv 9951}}{\sp{\sn relTop}{\sv 11126}}{\sp{\sn relRight}{\sv 9951}}{\sp{\sn relBottom}{\sv 13142}}{\sp{\sn fRelFlipH}{\sv 0}} +{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}{\sp{\sn lidRegroup}{\sv 3}}}} +{\shp{\*\shpinst\shplid1364{\sp{\sn relLeft}{\sv 9952}}{\sp{\sn relTop}{\sv 13142}}{\sp{\sn relRight}{\sv 10240}}{\sp{\sn relBottom}{\sv 13142}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}} +{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}{\sp{\sn lidRegroup}{\sv 3}}}}{\shp{\*\shpinst\shplid1365{\sp{\sn relLeft}{\sv 10239}}{\sp{\sn relTop}{\sv 11126}} +{\sp{\sn relRight}{\sv 10239}}{\sp{\sn relBottom}{\sv 13142}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 1}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}} +{\sp{\sn lidRegroup}{\sv 3}}}}{\shp{\*\shpinst\shplid1366{\sp{\sn relLeft}{\sv 1599}}{\sp{\sn relTop}{\sv 9129}}{\sp{\sn relRight}{\sv 2319}}{\sp{\sn relBottom}{\sv 9417}}{\sp{\sn fRelFlipH}{\sv 0}} +{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 202}}{\sp{\sn lTxid}{\sv 1310720}}{\sp{\sn dxTextLeft}{\sv 0}}{\sp{\sn dyTextTop}{\sv 0}}{\sp{\sn dxTextRight}{\sv 0}}{\sp{\sn dyTextBottom}{\sv 0}}{\sp{\sn hspNext}{\sv 1366}}{\sp{\sn fLine}{\sv 0}} +{\sp{\sn lidRegroup}{\sv 3}}{\shptxt \pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {\f1\fs24\lang3079 3.3V +\par }}}}{\shp{\*\shpinst\shplid1367{\sp{\sn relLeft}{\sv 4635}}{\sp{\sn relTop}{\sv 10193}}{\sp{\sn relRight}{\sv 5198}}{\sp{\sn relBottom}{\sv 10200}}{\sp{\sn fRelFlipH}{\sv 0}} +{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}{\sp{\sn lidRegroup}{\sv 3}}}} +{\shp{\*\shpinst\shplid1368{\sp{\sn relLeft}{\sv 4650}}{\sp{\sn relTop}{\sv 12068}}{\sp{\sn relRight}{\sv 5070}}{\sp{\sn relBottom}{\sv 12068}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}} +{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}{\sp{\sn lidRegroup}{\sv 3}}}}{\shp{\*\shpinst\shplid1369{\sp{\sn relLeft}{\sv 4935}}{\sp{\sn relTop}{\sv 10195}} +{\sp{\sn relRight}{\sv 4935}}{\sp{\sn relBottom}{\sv 12067}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}} +{\sp{\sn lidRegroup}{\sv 3}}}}{\shp{\*\shpinst\shplid1370{\sp{\sn relLeft}{\sv 4935}}{\sp{\sn relTop}{\sv 10195}}{\sp{\sn relRight}{\sv 5079}}{\sp{\sn relBottom}{\sv 12067}}{\sp{\sn fRelFlipH}{\sv 0}} +{\sp{\sn fRelFlipV}{\sv 1}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}{\sp{\sn lidRegroup}{\sv 3}}}} +{\shp{\*\shpinst\shplid1371{\sp{\sn relLeft}{\sv 6045}}{\sp{\sn relTop}{\sv 9420}}{\sp{\sn relRight}{\sv 9555}}{\sp{\sn relBottom}{\sv 11130}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 1}}}} +}{\shprslt{\*\do\dobxcolumn\dobypara\dodhgt8245\dppolygon\dppolycount4\dpptx0\dppty0\dpptx9073\dppty0\dpptx9073\dppty4013\dpptx0\dppty4013\dpx16\dpy-12\dpxsize9073\dpysize4013 +\dpfillfgcr255\dpfillfgcg255\dpfillfgcb255\dpfillbgcr255\dpfillbgcg255\dpfillbgcb255\dpfillpat1\dplinew15\dplinecor0\dplinecog0\dplinecob0}}}}{\fs24 +\par +\par +\par +\par +\par +\par +\par +\par +\par }{Figure 10 White PAL voltage waveform +\par }{\fs24 \page }{Results: if the two waveforms are correct and the UHF monitor does not give a display then the UHF modulator is faulty and should be replaced. +\par If the colour burst part of the waveforms is missing then the fault lies in the chrominance circuitry, see (c). +\par If any other part of the waveforms is incorrect, make link S26 temporarily and test the composite video output with an oscilloscope. The waveforms should be similar to those indicated in figures 9 and 10, but of reduced amplitude (1V peak to peak). +\par If the composite output waveforms are good with link S26 made (including colour burst), but the UHF output does not work, then the fault lies in the UHF l +uminance circuitry (Q6, D12, D13, D14, C36 and associated resistors). Check that diodes D12, D13, and D14 are inserted the correct way round (the PCB is marked +). +\par If the video output waveforms are bad then the video luminance circuitry (Q8 and associated resistors) may be faulty, and possibly chrominance circuitry also, see (c). +\par A composite colour monitor can be used to test the video output with link S26 made. If the composite colour monitor works in black and white only then the chrominance circuitry is faulty, see (c). +\par c) RGB works; UHF works in black and white only. +\par Results: the chrominance circuitry is faulty. Test pin 3 of IC87 with a frequency counter. The mea +sured frequency must be 17.7345MHz +/-400Hz, and can be adjusted using VC1. If there is no signal on pin 3 IC87 then check the oscillator circuit formed by X2, Q10 and associated components. +\par IC79 is a 74S74. A 74LS74 in this position can cause the circuit to fail. Check that there are signals from pins 9 and 6 of IC79 (4.4336MHz) and also a signal from pin 9 IC69 (7.7kHz approximately). +\par Check that L1 has not gone open circuit and that C49 has not failed, and check Q9. +\par Failing all this check the logic circuit formed by ICs 83, 86, 87, and 90, and resistors R85 to R92. +\par d) The RGB picture is distorted. +\par Results: either the DIN plug is incorrectly fitted to the monitor socket, or CSYNC must be inverted by altering S27. +\par }\pard\plain \s2\sa240\keepn\nowidctlpar\tx2835\outlinelevel1\adjustright \b\f2\lang2057 {\fs22 \page }{9.8 Cassette interface and RS423 +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {These two interfaces are examined together because they share two major components, the UART or ACIA IC82 and the serial processor or SERPROC IC85. +\par If both the cassette interface and RS423 fail (shown up by the PORT tester) then it is likely that the fault is with one of the above ICs or its address decoding. +\par a) Cassette interface +\par Use a PORT tester to verify that the cassette interface is faulty. +\par All tests on the cassette interface must be carried out using a known working cassette recorder and tape. The co +mmonest fault is the user's cassette recorder and the azimuth adjustment should be checked. The tape recorder's volume control should be set for an output of 300mV peak to peak. +\par Test pin 25 IC85 (the serial processor) and check that 16MHz/13 (812ns period) is arriving at that pin. This signal must be stable and accurate. If not, the divide by 13 circuitry formed by IC18 is faulty. +\par If the cassette fails to LOAD, look at the following pins while attempting to LOAD: +\par IC89 pin 8 should show high and low tones of equal amplitude, symmetrical about 0V. If there is a marked displacement then replace IC89. +\par IC89 pin 14 should be similar to pin 8, with maximum 50mV displacement. +\par IC89 pin 1 should show a 1.4V peak to peak square wave with an even mark/space ratio. Reduce the volume of the cassette recorder until this is so. Maximum 50mV displacement. +\par Check that pins 2 and 3 of IC82 are wobbling. +\par Check that both IC82 and IC85 can be selected by running the following program. +\par }\pard\plain \s25\qj\li284\nowidctlpar\tx284\tx2835\adjustright \f2\fs22\lang2057 {10 acia% = &FE08 +\par 20 serproc% = &FE10 +\par 30 DIM P% 100 +\par 40 [ +\par 50 . start% +\par 60 LDA acia% +\par 70 LDA serproc% +\par 80 JMP start% +\par 90 ] +\par }\pard \s25\qj\li284\sa240\nowidctlpar\tx284\tx2835\adjustright {100 CALL start% +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {Monitor the two chip selects, pin 9 IC82 and pin 9 IC85. These should be wobbling. If one is faulty t +hen check the address decoding IC21 and IC39, and the connections from pin 5 and pin 6 IC39. +\par If the cassette fails to SAVE, then SAVE a section of ROM and check if there is a synthesized sine-wave signal from IC85 pin 27 of around ???? peak to peak. If not then replace IC85. If there is then replace the LM324 (IC89). +\par b) RS423 +\par Use a PORT tester to verify that the RS423 is faulty. +\par One way of checking the operation of the RS423 is to connect the suspect microcomputer to a known working microcomputer via their RS423 ports. The connections must be made as follows +\par Din to Dout \tab pin A to pin B +\par }\pard \qj\nowidctlpar\tx2835\adjustright {Dout to Din \tab pin B to pin A +\par 0v to 0v \tab pin C to pin C +\par CTS to RTS \tab pin D to pin E +\par }\pard \qj\sa240\nowidctlpar\tx2835\adjustright {RTS to CTS \tab pin E to pin D +\par Once the two machines are connected, switch on the power for both and configure the known working microcomputer to accept RS423 as input by typing +\par *FX2,2 +\par This command will cause the microcomputer to accept input from both the keyboard and RS423, so keyboard commands will still work. +\par Now type the following BASIC program into the suspect microcomputer +\par }\pard\plain \s25\qj\li284\nowidctlpar\tx284\tx2835\adjustright \f2\fs22\lang2057 {10 *FX3,5 +\par 20 REPEAT +\par 30 PRINT "U"; +\par }\pard \s25\qj\li284\sa240\nowidctlpar\tx284\tx2835\adjustright {40 UNTIL 0 +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 { +This program configures the suspect microcomputer to give output to the RS423 and to the screen. It then prints the character "U", whose ASCII code is &55. &55 is a good number for testing the RS423 because it consists of alternating bits 01010101. +\par RUN the program. +\par If the known working microcomputer starts printing UUUUUUUUUUUUUUUUUUUU etc across the screen then the RS423 is working as a transmitter. If it works then go on to test it as a receiver. +\par If no output appears then test the suspect RS423 circuit as follows. +\par Check the Dout line either side of the driver, pins 2 and 15 of IC95. Pin 2 should be oscillating at normal TTL logic levels 0V/+5V. Pin 15 should be oscillating in phase wi +th pin 2 but at RS423 logic levels -5V/+5V. If pin 2 is active but pin 15 is not then replace the driver IC95. +\par \page Check that the SERPROC IC85 is sending the transmit clock TXCK and receiving transmit data TXD from the 6850 IC82. These signals are on pins 26 +and 22 respectively of IC85. If these signals are inactive then it is like1y that the SERPROC is faulty or cannot be addressed. Use the test program given in the cassette section above to check that the address decoding for the SERPROC and 6850 is working +. +\par Now press CTRL BREAK on each microcomputer and swap the configurations, so that the good computer is the transmitter and the suspect computer is the receiver. +\par If "U" characters are output on to the monitor by the suspect computer then its RS423 is working as a receiver. +\par If no output appears then test the suspect RS423 circuit as follows. +\par Check the Din line either side of the receiver, pins 4 and 7 of IC94. Pin 4 + should be oscillating at RS423 logic levels -5V/+5V. Pin 7 should be oscillating in phase with pin 4 but at normal TTL logic levels 0V/+5V. If pin 4 is active but pin 7 is not then replace the receiver IC94. +\par Check that the SERPROC IC85 is sending the rece +ive clock RXCK and receive data RXD to the 6850 IC82. These signals are on pins 26 and 22 respectively of IC85. If these signals are inactive then it is likely that the SERPROC is faulty or cannot be addressed. Use the test program given in the cassette s +ection above to check that the address decoding for the SERPROC and 6850 is working. +\par The alternative way of testing RS423 without using another microcomputer is to connect RTS to CTS and Dout to Din. Then if the BASIC program above is used to transmit data +its path can be followed from the data bus through the 6850, SERPROC, drivers, out through the connector and back again through the receivers, SERPROC and through RXD back to the 6850. This loop allows all the components of the RS423 circuit to be checked + as above. +\par }\pard\plain \s2\sa240\keepn\nowidctlpar\tx2835\outlinelevel1\adjustright \b\f2\lang2057 {9.9 Keyboard +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {Keyboard problems either show up as a single key which won't work reliably, or a whole group of keys which refuses to operate. +\par The single key fault is caused by that particular switch having worn out, or the track becoming broken by excess force. Replace the key or solder the track. +\par For multiple key problems, the first thing to check is that the connectors are inserted correctly. It is easy to displace either connector of the keyboard ribbon cable one pin to the left or right. If the +connections are good then check that one of the wires in the cable itself hasn't been broken where it is held by the connector. Replace the ribbon cable with a good one. Try replacing the whole keyboard assembly with a good one. If it still doesn't work t +hen there is probably a fault in the computer itself. Use a PORT tester. +\par }\pard\plain \s2\sa240\keepn\nowidctlpar\tx2835\outlinelevel1\adjustright \b\f2\lang2057 {\fs22 \page }{9.10 Disc interface +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {8271: check all links are in correct position for 8271 operation: +\par }\pard \qj\nowidctlpar\tx2835\adjustright {S1 North (PCB LINK) +\par S2 North (PCB LINK) +\par S3 South (PCB LINK) +\par S4 South (PCB LINK) +\par S6 South (PCB LINK) +\par }\pard\plain \s20\qj\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {S7 West +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {S8 open circuit +\par Check that all ICs and passives are fitted and inserted correctly, see 8271 disc upgrade, section 6.2. +\par Use a PORT tester to check that the disc interface is the problem. +\par Check that a disc filing system ROM has been fitted e.g. DNFS. If the filing system is stored in an EPROM (as opposed to a mask ROM) then make sure that pin 27 is connected to 5V. +\par Connect a known working dual 80 track disc drive. +\par Turn the microcomputer on. Check that the start-up message indicates a filing system ROM is present. +\par Acorn OS 64K +\par Acorn DFS +\par BASIC +\par > +\par Results: If the message does not report the "Acorn DFS" then check the IC socket by fitting a known good language ROM. Check the DFS (or DNFS) ROM in another machine. If both are OK then check the 8271 (IC15) +and the chip select logic, check for correct data, address, RD and WR signals at IC15. Check for 2MHz on pin 3 and for a reset pulse on pin 4 (when break key used) of IC15. +\par Press SHIFT and BREAK, then release BREAK while holding SHIFT down. Drive 0 should start (the LED on the front of the drive comes on). +\par Results: if the drive fails to come on then test that pin 38 IC15 is high (pin 10 IC8 low). +\par Results: if pin 10 IC8 goes low then check the connection from IC8 to PL8. If pin 10 IC8 is high th +en first check that a DNFS ROM is fitted and is plugged in correctly. Try fitting a good 8271. Then run the following program and check that the 8271 is being selected using an oscillosope on IC15 pin 24. +\par }\pard\plain \s25\qj\li284\nowidctlpar\tx284\tx2835\adjustright \f2\fs22\lang2057 {10 fdc% = &FE80 +\par 20 DIM P% 100 +\par 30 [ +\par 40 . start% +\par 50 LDA fdc% +\par 60 JMP start% +\par 70 ] +\par }\pard \s25\qj\li284\sa240\nowidctlpar\tx284\tx2835\adjustright {80 CALL start% +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 { +If drive does come on with SHIFT BREAK then insert a known good 80 track disc into drive 0. Use a disc which has a number of files on it, and make sure that a write protect tab is fitted. Shut the drive door. +\par Try *CAT to get a catalogue of the disc. If no catalogue appears then check that S7 is fitted West. Check that notCS pulses low (pin 24 IC15). If not then check decoder IC28. +\par Check that after a BREAK a pulse occurs on pin 7 IC15. If not then check decoder IC28. +\par Check that RDY pins 5 and 32 of IC15 are low. If RDY is high then check S2, and for 2MHz at pin 3 IC15. If 2MHz is missing then link S6 is probably open circuit, if 4MHz then S6 set incorrectly. Check that index pulses are reaching IC3 pins 3 and 11. If n +ot then either S4 is wrong or the disc drive is faulty. If index pulses are reaching IC3 but RDY is not going low then the disc may not be reaching speed. Measure the index pulse frequency. It should be 5Hz +/-3%. +\par Use an oscilloscope to monitor data on the signal end of R7. The data should be negative-going 1\'b5s pulses with intervals of 4 or 8\'b5s between them. If not then check connections to PL8. +\par 1770: check all links are in correct position for l770 operation: +\par }\pard \qj\nowidctlpar\tx2835\adjustright {S3 South (PCB LINK) +\par S4 South (PCB LINK) +\par S5 broken +\par S7 East +\par }\pard \qj\sa240\nowidctlpar\tx2835\adjustright {S8 made +\par Check that all ICs and passives are fitted and inserted correctly, see 1770 disc upgrade, section 6.1. +\par Use a PORT tester to check that the disc interface is the problem. +\par Check that a disc filing system ROM has been fitted, e.g. 1770 DFS +or ADFS. If the filing system is stored in an EPROM, check that pin 27 of the EPROM is connected to 5V. For tests that follow we shall assume the use of the 1770 DFS, so fit this ROM if it is not already in place. +\par \page Connect a known working dual 80 track disc drive. +\par Turn the microcomputer on. Check that the start-up message indicates a filing system ROM is present. +\par Acorn OS 64K +\par 1770 DFS +\par BASIC +\par > +\par Results: if the message fails to say 1770 DFS then check the ROM socket and the ROM. If the ROM works OK + then check that the data, address and control signals are reaching the 1770, IC16. Check for pulses on pin 1 of IC15 after a break. If there are none, check the address decoding logic. +\par Press SHIFT and BREAK, then release BREAK while holding SHIFT down. Drive 0 should start (the LED on the front of the drive comes on). +\par Results: if drive doesn't come on then check using an oscilloscope or logic probe that M0 (pin 20 IC16) is high, notMOTOR (pin 10 IC8) is low. Check that S0 (pin 7 IC17) is high, notS0 (pin 8 + IC7) is low. If the above signals are correct then check the connection from IC7 and IC8 to connector PL8. If the above signals are wrong then try a good 1770 and check IC17. Check that IC17 is reset after a BREAK (all outputs low). Check IC17 function b +y poking values between 0 and 64 into location &FE80. Check that the correct bit pattern appears on the outputs. +\par If drive does come on with SHIFT BREAK then insert a known good 80 track disc into drive 0. Use a disc which has a number of files on it, and make sure that a write protect tab is fitted. Shut the drive door. +\par Try *CAT to get a catalogue of the disc. If no catalogue appears then check that S7 is fitted East. If an incorrect catalogue is obtained then check that S8 is fitted. This fault is unlikely +if the disc system has worked before, but likely after an upgrade. +\par Check that after a BREAK a chip select (notCS) pulse occurs on pin 1 IC16. If not then check decoder IC28. +\par Use an oscilloscope to monitor read data (notRD) on pin 19 IC16, or the signal end of R7. The data should be negative-going pulses of period 4\'b5s or 8\'b5s. If not then check connections to PL8. Replace 1770. +\par }\pard\plain \s2\sa240\keepn\nowidctlpar\tx2835\outlinelevel1\adjustright \b\f2\lang2057 {\page 9.11 Printer port +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {Use a PORT tester to check that the printer port is faulty. +\par Test the VIA (IC10) by writing values to it and testing the outputs. First configure all the data lines as outputs by writing &FF to the data direction register A (DDRA) +\par ?&FE63=&FF +\par Then write &00 to the output register +\par ?&FE61=&00 +\par All the data lines to the printer connector PL9 should now be low, pins 3 5 7 9 +11 13 15 and 17. If they are not all zero then check them at the VIA itself, pins 2 3 4 5 6 7 8 and 9 of IC10. If these are all low then the buffer IC5 is faulty. Otherwise check for open circuit tracks on data lines on both the printer side and the CPU s +ide of the VIA. +\par Now write &FF to the output register +\par ?&FE61=&FF +\par All the data lines to the printer connector PL9 should now be high, pins 3 5 7 9 11 13 15 and 17. If they are not all 1 then check them at the VIA itself, pins 2 3 4 5 6 7 8 and 9 of IC10. If t +hese are all high then the buffer IC5 is faulty. Otherwise check for short circuit tracks on data lines on both the printer side and the CPU side of the VIA. +\par A better test is to use the binary configuration 10101010 on the outputs, and then change it to 01010101. These correspond to the values &AA and &55. This way short circuits are more likely to give the wrong value in the tests. +\par Connect a known good printer to the microcomputer. Check that the printer strobe output from the VIA pin 39 IC10 gives a 4\'b5s n +egative going pulse when the computer is instructed to print. If it does then check this pulse at pin 14 IC13. If the printer interface is working correctly then there should be regular strobe pulses until the printer buffer is full. If there is only a si +n +gle pulse then check the printer ACK input pin 40 IC10. These two lines together (strobe and ACK) perform the data control handshake and, on being instructed to print, the two signals ought to alternate until the printer buffer is full. If the computer is + sending a strobe pulse but no ACK is coming back from the printer then the connections to the edge connector PL9 are faulty. If the strobe pulse is not being sent then the fault is either a broken track or the VIA chip itself. +\par }\pard\plain \s2\sa240\keepn\nowidctlpar\tx2835\outlinelevel1\adjustright \b\f2\lang2057 {\fs22 \page }{9.12 User port +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {Use a PORT tester to check that the user port is faulty. +\par Test the VIA (IC10) by writing values to it and testing the outputs. First configure all the data lines as outputs by writing &FF to the data direction register B (DDRB) +\par ? &FE62=&FF +\par Then write &00 to the output register +\par ?&FE60=&00 +\par All the data lines to the user connector PL10 should now be low, pins 6, 8, 10, 12, 14, 16, 18 and 20. If they are not all zero then check for open circuit tracks on data lines on both the printer side and the CPU side of the VIA. +\par Now write &FF to the output register +\par ?&FE60=&FF +\par All the data lines to the user connector PL10 should now be high. If they are not all 1 then check for short circuit tracks on data lines on both the printer side and the CPU side of the VIA. +\par A better test is to use the binary configuration 10101010 on the outputs, and then change it to 01010101. These correspond to the values &AA and &55. This way short circuits are more likely to give the wrong value in the tests. +\par }\pard\plain \s2\sa240\keepn\nowidctlpar\tx2835\outlinelevel1\adjustright \b\f2\lang2057 {\b0 \page }{9.13 1MHz extension bus +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {Use a PORT tester. If the 1MHz extension bus is faulty then the PORT tester may show up all kinds of errors, because it is driven through the 1MHz bus. +\par Use the following program to exercise the FRED and JIM address decoding. +\par }\pard\plain \s25\qj\li284\nowidctlpar\tx284\tx2835\adjustright \f2\fs22\lang2057 {10 fred% = &FC00 +\par 20 jim% = &FD00 +\par 30 DIM P% 100 +\par 40 [ +\par 50 . start% +\par 60 LDA# &00 +\par 70 .loop% +\par 80 STA fred% +\par 90 STA jim% +\par 100 JMP loop% +\par 110 ] +\par }\pard \s25\qj\li284\sa240\nowidctlpar\tx284\tx2835\adjustright {120 CALL start% +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {RUN the program and test pins 4 and 5 IC28 for the FRED and JIM signals, which should be pulsing low for 1\'b5s or 1.5\'b5s (depending on the CPU's synchronisation t +o 1M). If not then replace IC28. If the signals are good then test them at pins 16 and 14 IC6. +\par Check that the ROM output enable pin 6 IC40 is high (ROM disabled) when either FRED or JIM is low. +\par Check that SYNC 1M pin 8 IC41 is high when either FRED or JIM is low. +\par Check that the data bus buffer enable pin 19 IC12 is low (enabled) when either FRED or JIM is low. +\par All the above three signals come indirectly from pin 11 IC34. +\par Check that the data bus D0-D7 goes low both sides of the buffer at some point after the buffer is enabled (pin 19 IC12 goes low). +\par }\pard\plain \s2\sa240\keepn\nowidctlpar\tx2835\outlinelevel1\adjustright \b\f2\lang2057 {\page 9.14 TUBE interface +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {Use a PORT tester to check that the TUBE interface is faulty. +\par Run the following test program +\par }\pard\plain \s25\qj\li284\nowidctlpar\tx284\tx2835\adjustright \f2\fs22\lang2057 {10 tube% = &FFE0 +\par 20 DIM P% 100 +\par 30 [ +\par 40 . start% +\par 50 LDA# &00 +\par 60 .loop% +\par 70 STA tube% +\par 80 JMP loop% +\par 90 ] +\par }\pard \s25\qj\li284\sa240\nowidctlpar\tx284\tx2835\adjustright {100 CALL start% +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {Test the enable pin 19 IC14 with an oscilloscope and check that the signal is wobbling. If not then check the address decoding performed by IC21 and IC22. +\par Check that all data lines both sides of the buffer pins 11-18 and pins 9-2 of IC14 (D0-D7) go low at some point after the enable pin 19 IC14 goes low. +\par Change line 50 of the program to +\par 50 LDA# &FF +\par and check that all the buffered data lines go high at some point after the enable pin 19 IC14 goes low. +\par If these tests do not give correct results then check the data bus buffer IC14 and the PCB tracks and connections to PL12. +\par 50 LDA# &AA +\par and +\par 50 LDA# &55 +\par can also be tried. These correspond to output bit patterns 10101010 and 01010101. +\par A0-A4, R/notW, and 2E can be looked for on pins 12 9 7 5 3 16 and 18 of IC13. These signals should be the same as the system signals, but delayed by 10-15ns. +\par }\pard\plain \s2\sa240\keepn\nowidctlpar\tx2835\outlinelevel1\adjustright \b\f2\lang2057 {\page 9.15 Analogue to digital conversion +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {Use a PORT tester to verify that the ADC circuit is faulty. +\par Check VREF by measuring the voltage between pin 8 IC84 and ground. This voltage should be approximately 1.8V. Look for shorted or broken tracks if it is not. +\par Connect two known working 2-way joysticks to the D-type connector SK6 used for the ADC. Type in and RUN the following program. +\par }\pard\plain \s25\qj\li284\nowidctlpar\tx284\tx2835\adjustright \f2\fs22\lang2057 {10 VDU 23,1,0;0;0;0; +\par 20 CLS +\par 30 REPEAT +\par 40 PRINT TAB(0,0); ADVAL(1); SPC(4) +\par 50 PRINT TAB(0,2); ADVAL(2); SPC(4) +\par 60 PRINT TAB(0,4); ADVAL(3); SPC(4) +\par 70 PRINT TAB(0,6); ADVAL(4); SPC(4) +\par }\pard \s25\qj\li284\sa240\nowidctlpar\tx284\tx2835\adjustright {80 UNTIL 0 +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {Move the joysticks and see if you can get numbers in the r +ange 0 to 65520 on each of the 4 channels. (In practice it may well not be possible to get near either one or both of the end values, but a good range of numbers on each channel is sufficient to show that the converter is working.) +\par If this experiment does not work then check that the ADC IC can be accessed by running the following program. +\par }\pard\plain \s25\qj\li284\nowidctlpar\tx284\tx2835\adjustright \f2\fs22\lang2057 {10 adc% = &FEC0 +\par 20 DIM P% 100 +\par 30 [ +\par 40 . start% +\par 50 LDA adc% +\par 60 JMP start% +\par 70 ] +\par }\pard \s25\qj\li284\sa240\nowidctlpar\tx284\tx2835\adjustright {80 CALL start% +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {Check that pin 23 IC84 is active. If not then check the address decoding and connections from pin 9 IC21. +\par Press CTRL BREAK and look at the signal on pin 28 IC84. This line signals the end of a conversion and should be pulsing low approximately once every 10ms. If it is, but there is still a problem with A to D conversion, then chec +k that the EOC signal is reaching pin 18 IC20. +\par }\pard\plain \s2\sa240\keepn\nowidctlpar\tx2835\outlinelevel1\adjustright \b\f2\lang2057 {\fs22 \page }{9.16 ECONET +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 { +ECONET can only be serviced properly by ECONET service centers, who will have the necessary test equipment to check the system thoroughly. However, there are a few simple things which can be checked without the test equipment. +\par Check that all the ECONET components are installed and have been fitted correctly, see 6.3. +\par Check that notNMI on the CPU pin 6 IC42 is not being held low. +\par If the system will not give a correct ID number then use the shunts S23 to find which track is broken or shorting. +\par }{\fs24 \page +\par +\par +\par }\pard \qc\sa240\nowidctlpar\tx2835\adjustright {\fs24 +\par +\par +\par +\par +\par +\par +\par +\par }\pard \qc\sa240\nowidctlpar\tx2835\outlinelevel0\adjustright {\b\fs52 A P P E N D I X +\par }\pard \qj\sa240\nowidctlpar\tx2835\adjustright {\fs24 +\par +\par }\pard\plain \s1\qj\sa240\nowidctlpar\tx2835\outlinelevel0\adjustright \b\f2 {\page Connector pinouts +\par }\pard\plain \s4\qj\keepn\nowidctlpar\tx2835\outlinelevel3\adjustright \f2\fs22\lang2057 {SK1 UHF out +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {phono +\par }\pard \qj\ri6481\nowidctlpar\tx2835\adjustright {outer: ground +\par }\pard \qj\ri6480\sa240\nowidctlpar\tx2835\adjustright {inner: UHF +\par }\pard\plain \s4\qj\keepn\nowidctlpar\tx2835\outlinelevel3\adjustright \f2\fs22\lang2057 {SK2 video out +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {BNC +\par }\pard \qj\nowidctlpar\tx2835\adjustright {outer: ground +\par }\pard\plain \s20\qj\sa240\nowidctlpar\tx2835\tx9993\tx10384\adjustright \f2\fs22\lang2057 {inner: VIDEO +\par }\pard\plain \s4\qj\keepn\nowidctlpar\tx2835\outlinelevel3\adjustright \f2\fs22\lang2057 {\lang1024\cgrid {\shpgrp{\*\shpinst\shpleft5707\shptop194\shpright9742\shpbottom3389\shpfhdr0\shpbxcolumn\shpbypara\shpwr3\shpwrk0\shpfblwtxt0\shpz59\shplid1372 +{\sp{\sn groupLeft}{\sv 6963}}{\sp{\sn groupTop}{\sv 4320}}{\sp{\sn groupRight}{\sv 10998}}{\sp{\sn groupBottom}{\sv 7515}}{\sp{\sn fFlipH}{\sv 0}}{\sp{\sn fFlipV}{\sv 0}}{\sp{\sn rotation}{\sv 0}}{\sp{\sn lidRegroup}{\sv 19}}{\shp{\*\shpinst\shplid1373 +{\sp{\sn relLeft}{\sv 7640}}{\sp{\sn relTop}{\sv 4932}}{\sp{\sn relRight}{\sv 9944}}{\sp{\sn relBottom}{\sv 7236}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 3}}{\sp{\sn lineWidth}{\sv 38100}}{\sp{\sn lineStyle}{\sv 1}} +{\sp{\sn fLine}{\sv 1}}{\sp{\sn lidRegroup}{\sv 5}}}}{\shp{\*\shpinst\shplid1374{\sp{\sn relLeft}{\sv 8648}}{\sp{\sn relTop}{\sv 4935}}{\sp{\sn relRight}{\sv 8936}}{\sp{\sn relBottom}{\sv 5079}}{\sp{\sn fRelFlipH}{\sv 0}} +{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 1}}{\sp{\sn lidRegroup}{\sv 5}}}}{\shp{\*\shpinst\shplid1375{\sp{\sn relLeft}{\sv 8792}}{\sp{\sn relTop}{\sv 6007}}{\sp{\sn relRight}{\sv 8905}}{\sp{\sn relBottom}{\sv 6120}}{\sp{\sn fRelFlipH}{\sv 0}} +{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 3}}{\sp{\sn lidRegroup}{\sv 5}}}}{\shp{\*\shpinst\shplid1376{\sp{\sn relLeft}{\sv 8199}}{\sp{\sn relTop}{\sv 6315}}{\sp{\sn relRight}{\sv 8312}}{\sp{\sn relBottom}{\sv 6428}}{\sp{\sn fRelFlipH}{\sv 0}} +{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 3}}{\sp{\sn lidRegroup}{\sv 5}}}}{\shp{\*\shpinst\shplid1377{\sp{\sn relLeft}{\sv 9351}}{\sp{\sn relTop}{\sv 6315}}{\sp{\sn relRight}{\sv 9464}}{\sp{\sn relBottom}{\sv 6428}}{\sp{\sn fRelFlipH}{\sv 0}} +{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 3}}{\sp{\sn lidRegroup}{\sv 5}}}}{\shp{\*\shpinst\shplid1378{\sp{\sn relLeft}{\sv 8775}}{\sp{\sn relTop}{\sv 6747}}{\sp{\sn relRight}{\sv 8888}}{\sp{\sn relBottom}{\sv 6860}}{\sp{\sn fRelFlipH}{\sv 0}} +{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 3}}{\sp{\sn lidRegroup}{\sv 5}}}}{\shp{\*\shpinst\shplid1379{\sp{\sn relLeft}{\sv 9207}}{\sp{\sn relTop}{\sv 5451}}{\sp{\sn relRight}{\sv 9320}}{\sp{\sn relBottom}{\sv 5564}}{\sp{\sn fRelFlipH}{\sv 0}} +{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 3}}{\sp{\sn lidRegroup}{\sv 5}}}}{\shp{\*\shpinst\shplid1380{\sp{\sn relLeft}{\sv 8343}}{\sp{\sn relTop}{\sv 5451}}{\sp{\sn relRight}{\sv 8456}}{\sp{\sn relBottom}{\sv 5564}}{\sp{\sn fRelFlipH}{\sv 0}} +{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 3}}{\sp{\sn lidRegroup}{\sv 5}}}}{\shp{\*\shpinst\shplid1381{\sp{\sn relLeft}{\sv 8865}}{\sp{\sn relTop}{\sv 4725}}{\sp{\sn relRight}{\sv 9270}}{\sp{\sn relBottom}{\sv 5895}}{\sp{\sn fRelFlipH}{\sv 0}} +{\sp{\sn fRelFlipV}{\sv 1}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn fAutoTextMargin}{\sv 0}}{\sp{\sn fRotateText}{\sv 0}}{\sp{\sn fFitShapeToText}{\sv 0}}{\sp{\sn fFitTextToShape}{\sv 0}} +{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}{\sp{\sn fHitTestLine}{\sv 1}}{\sp{\sn lineFillShape}{\sv 1}}{\sp{\sn fShadow}{\sv 0}}{\sp{\sn fshadowObscured}{\sv 0}}{\sp{\sn f3D}{\sv 0}} +{\sp{\sn fc3DMetallic}{\sv 0}}{\sp{\sn fc3DUseExtrusionColor}{\sv 0}}{\sp{\sn fc3DLightFace}{\sv 1}}{\sp{\sn fc3DConstrainRotation}{\sv 1}}{\sp{\sn fc3DRotationCenterAuto}{\sv 0}}{\sp{\sn fc3DParallel}{\sv 1}} +{\sp{\sn fc3DKeyHarsh}{\sv 1}}{\sp{\sn fc3DFillHarsh}{\sv 0}}{\sp{\sn fCalloutMinusX}{\sv 0}}{\sp{\sn fCalloutMinusY}{\sv 0}}{\sp{\sn fCalloutDropAuto}{\sv 0}}{\sp{\sn fCalloutLengthSpecified}{\sv 0}}{\sp{\sn lidRegroup}{\sv 5}}}} +{\shp{\*\shpinst\shplid1382{\sp{\sn relLeft}{\sv 9495}}{\sp{\sn relTop}{\sv 5190}}{\sp{\sn relRight}{\sv 9915}}{\sp{\sn relBottom}{\sv 5370}}{\sp{\sn fRelFlipH}{\sv 0}} +{\sp{\sn fRelFlipV}{\sv 1}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn fAutoTextMargin}{\sv 0}}{\sp{\sn fRotateText}{\sv 0}}{\sp{\sn fFitShapeToText}{\sv 0}}{\sp{\sn fFitTextToShape}{\sv 0}} +{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}{\sp{\sn fHitTestLine}{\sv 1}}{\sp{\sn lineFillShape}{\sv 1}}{\sp{\sn fShadow}{\sv 0}}{\sp{\sn fshadowObscured}{\sv 0}}{\sp{\sn f3D}{\sv 0}} +{\sp{\sn fc3DMetallic}{\sv 0}}{\sp{\sn fc3DUseExtrusionColor}{\sv 0}}{\sp{\sn fc3DLightFace}{\sv 1}}{\sp{\sn fc3DConstrainRotation}{\sv 1}}{\sp{\sn fc3DRotationCenterAuto}{\sv 0}}{\sp{\sn fc3DParallel}{\sv 1}} +{\sp{\sn fc3DKeyHarsh}{\sv 1}}{\sp{\sn fc3DFillHarsh}{\sv 0}}{\sp{\sn fCalloutMinusX}{\sv 0}}{\sp{\sn fCalloutMinusY}{\sv 0}}{\sp{\sn fCalloutDropAuto}{\sv 0}}{\sp{\sn fCalloutLengthSpecified}{\sv 0}}{\sp{\sn lidRegroup}{\sv 5}}}} +{\shp{\*\shpinst\shplid1383{\sp{\sn relLeft}{\sv 9585}}{\sp{\sn relTop}{\sv 6420}}{\sp{\sn relRight}{\sv 10200}}{\sp{\sn relBottom}{\sv 6420}}{\sp{\sn fRelFlipH}{\sv 0}} +{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn fAutoTextMargin}{\sv 0}}{\sp{\sn fRotateText}{\sv 0}}{\sp{\sn fFitShapeToText}{\sv 0}}{\sp{\sn fFitTextToShape}{\sv 0}} +{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}{\sp{\sn fHitTestLine}{\sv 1}}{\sp{\sn lineFillShape}{\sv 1}}{\sp{\sn fShadow}{\sv 0}}{\sp{\sn fshadowObscured}{\sv 0}}{\sp{\sn f3D}{\sv 0}} +{\sp{\sn fc3DMetallic}{\sv 0}}{\sp{\sn fc3DUseExtrusionColor}{\sv 0}}{\sp{\sn fc3DLightFace}{\sv 1}}{\sp{\sn fc3DConstrainRotation}{\sv 1}}{\sp{\sn fc3DRotationCenterAuto}{\sv 0}}{\sp{\sn fc3DParallel}{\sv 1}} +{\sp{\sn fc3DKeyHarsh}{\sv 1}}{\sp{\sn fc3DFillHarsh}{\sv 0}}{\sp{\sn fCalloutMinusX}{\sv 0}}{\sp{\sn fCalloutMinusY}{\sv 0}}{\sp{\sn fCalloutDropAuto}{\sv 0}}{\sp{\sn fCalloutLengthSpecified}{\sv 0}}{\sp{\sn lidRegroup}{\sv 5}}}} +{\shp{\*\shpinst\shplid1384{\sp{\sn relLeft}{\sv 8955}}{\sp{\sn relTop}{\sv 6930}}{\sp{\sn relRight}{\sv 9435}}{\sp{\sn relBottom}{\sv 7260}}{\sp{\sn fRelFlipH}{\sv 0}} +{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn fAutoTextMargin}{\sv 0}}{\sp{\sn fRotateText}{\sv 0}}{\sp{\sn fFitShapeToText}{\sv 0}}{\sp{\sn fFitTextToShape}{\sv 0}} +{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}{\sp{\sn fHitTestLine}{\sv 1}}{\sp{\sn lineFillShape}{\sv 1}}{\sp{\sn fShadow}{\sv 0}}{\sp{\sn fshadowObscured}{\sv 0}}{\sp{\sn f3D}{\sv 0}} +{\sp{\sn fc3DMetallic}{\sv 0}}{\sp{\sn fc3DUseExtrusionColor}{\sv 0}}{\sp{\sn fc3DLightFace}{\sv 1}}{\sp{\sn fc3DConstrainRotation}{\sv 1}}{\sp{\sn fc3DRotationCenterAuto}{\sv 0}}{\sp{\sn fc3DParallel}{\sv 1}} +{\sp{\sn fc3DKeyHarsh}{\sv 1}}{\sp{\sn fc3DFillHarsh}{\sv 0}}{\sp{\sn fCalloutMinusX}{\sv 0}}{\sp{\sn fCalloutMinusY}{\sv 0}}{\sp{\sn fCalloutDropAuto}{\sv 0}}{\sp{\sn fCalloutLengthSpecified}{\sv 0}}{\sp{\sn lidRegroup}{\sv 5}}}} +{\shp{\*\shpinst\shplid1385{\sp{\sn relLeft}{\sv 7605}}{\sp{\sn relTop}{\sv 6540}}{\sp{\sn relRight}{\sv 8115}}{\sp{\sn relBottom}{\sv 7020}}{\sp{\sn fRelFlipH}{\sv 1}} +{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn fAutoTextMargin}{\sv 0}}{\sp{\sn fRotateText}{\sv 0}}{\sp{\sn fFitShapeToText}{\sv 0}}{\sp{\sn fFitTextToShape}{\sv 0}} +{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}{\sp{\sn fHitTestLine}{\sv 1}}{\sp{\sn lineFillShape}{\sv 1}}{\sp{\sn fShadow}{\sv 0}}{\sp{\sn fshadowObscured}{\sv 0}}{\sp{\sn f3D}{\sv 0}} +{\sp{\sn fc3DMetallic}{\sv 0}}{\sp{\sn fc3DUseExtrusionColor}{\sv 0}}{\sp{\sn fc3DLightFace}{\sv 1}}{\sp{\sn fc3DConstrainRotation}{\sv 1}}{\sp{\sn fc3DRotationCenterAuto}{\sv 0}}{\sp{\sn fc3DParallel}{\sv 1}} +{\sp{\sn fc3DKeyHarsh}{\sv 1}}{\sp{\sn fc3DFillHarsh}{\sv 0}}{\sp{\sn fCalloutMinusX}{\sv 0}}{\sp{\sn fCalloutMinusY}{\sv 0}}{\sp{\sn fCalloutDropAuto}{\sv 0}}{\sp{\sn fCalloutLengthSpecified}{\sv 0}}{\sp{\sn lidRegroup}{\sv 5}}}} +{\shp{\*\shpinst\shplid1386{\sp{\sn relLeft}{\sv 7440}}{\sp{\sn relTop}{\sv 5265}}{\sp{\sn relRight}{\sv 8175}}{\sp{\sn relBottom}{\sv 5505}}{\sp{\sn fRelFlipH}{\sv 1}} +{\sp{\sn fRelFlipV}{\sv 1}}{\sp{\sn shapeType}{\sv 20}}{\sp{\sn fAutoTextMargin}{\sv 0}}{\sp{\sn fRotateText}{\sv 0}}{\sp{\sn fFitShapeToText}{\sv 0}}{\sp{\sn fFitTextToShape}{\sv 0}} +{\sp{\sn shapePath}{\sv 4}}{\sp{\sn fFillOK}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fArrowheadsOK}{\sv 1}}{\sp{\sn fHitTestLine}{\sv 1}}{\sp{\sn lineFillShape}{\sv 1}}{\sp{\sn fShadow}{\sv 0}}{\sp{\sn fshadowObscured}{\sv 0}}{\sp{\sn f3D}{\sv 0}} +{\sp{\sn fc3DMetallic}{\sv 0}}{\sp{\sn fc3DUseExtrusionColor}{\sv 0}}{\sp{\sn fc3DLightFace}{\sv 1}}{\sp{\sn fc3DConstrainRotation}{\sv 1}}{\sp{\sn fc3DRotationCenterAuto}{\sv 0}}{\sp{\sn fc3DParallel}{\sv 1}} +{\sp{\sn fc3DKeyHarsh}{\sv 1}}{\sp{\sn fc3DFillHarsh}{\sv 0}}{\sp{\sn fCalloutMinusX}{\sv 0}}{\sp{\sn fCalloutMinusY}{\sv 0}}{\sp{\sn fCalloutDropAuto}{\sv 0}}{\sp{\sn fCalloutLengthSpecified}{\sv 0}}{\sp{\sn lidRegroup}{\sv 5}}}} +{\shp{\*\shpinst\shplid1387{\sp{\sn relLeft}{\sv 7128}}{\sp{\sn relTop}{\sv 5070}}{\sp{\sn relRight}{\sv 7368}}{\sp{\sn relBottom}{\sv 5445}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 202}}{\sp{\sn lTxid}{\sv 1376256}} +{\sp{\sn dxTextLeft}{\sv 0}}{\sp{\sn dxTextRight}{\sv 0}}{\sp{\sn hspNext}{\sv 1387}}{\sp{\sn fAutoTextMargin}{\sv 0}}{\sp{\sn fRotateText}{\sv 0}}{\sp{\sn fFitShapeToText}{\sv 0}} +{\sp{\sn fFitTextToShape}{\sv 0}}{\sp{\sn fLine}{\sv 0}}{\sp{\sn fHitTestLine}{\sv 1}}{\sp{\sn lineFillShape}{\sv 1}}{\sp{\sn fShadow}{\sv 0}}{\sp{\sn fshadowObscured}{\sv 0}} +{\sp{\sn f3D}{\sv 0}}{\sp{\sn fc3DMetallic}{\sv 0}}{\sp{\sn fc3DUseExtrusionColor}{\sv 0}}{\sp{\sn fc3DLightFace}{\sv 1}}{\sp{\sn fc3DConstrainRotation}{\sv 1}}{\sp{\sn fc3DRotationCenterAuto}{\sv 0}}{\sp{\sn fc3DParallel}{\sv 1}} +{\sp{\sn fc3DKeyHarsh}{\sv 1}}{\sp{\sn fc3DFillHarsh}{\sv 0}}{\sp{\sn fCalloutMinusX}{\sv 0}}{\sp{\sn fCalloutMinusY}{\sv 0}}{\sp{\sn fCalloutDropAuto}{\sv 0}}{\sp{\sn fCalloutLengthSpecified}{\sv 0}}{\sp{\sn lidRegroup}{\sv 5}}{\shptxt \pard\plain +\qr\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {\f1\lang3079 5 +\par }}}}{\shp{\*\shpinst\shplid1388{\sp{\sn relLeft}{\sv 6963}}{\sp{\sn relTop}{\sv 6795}}{\sp{\sn relRight}{\sv 7533}}{\sp{\sn relBottom}{\sv 7170}}{\sp{\sn fRelFlipH}{\sv 0}} +{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 202}}{\sp{\sn lTxid}{\sv 1441792}}{\sp{\sn dxTextLeft}{\sv 0}}{\sp{\sn dxTextRight}{\sv 0}}{\sp{\sn hspNext}{\sv 1388}} +{\sp{\sn fAutoTextMargin}{\sv 0}}{\sp{\sn fRotateText}{\sv 0}}{\sp{\sn fFitShapeToText}{\sv 0}}{\sp{\sn fFitTextToShape}{\sv 0}}{\sp{\sn fLine}{\sv 0}}{\sp{\sn fHitTestLine}{\sv 1}} +{\sp{\sn lineFillShape}{\sv 1}}{\sp{\sn fShadow}{\sv 0}}{\sp{\sn fshadowObscured}{\sv 0}}{\sp{\sn f3D}{\sv 0}}{\sp{\sn fc3DMetallic}{\sv 0}}{\sp{\sn fc3DUseExtrusionColor}{\sv 0}}{\sp{\sn fc3DLightFace}{\sv 1}}{\sp{\sn fc3DConstrainRotation}{\sv 1}} +{\sp{\sn fc3DRotationCenterAuto}{\sv 0}}{\sp{\sn fc3DParallel}{\sv 1}}{\sp{\sn fc3DKeyHarsh}{\sv 1}}{\sp{\sn fc3DFillHarsh}{\sv 0}}{\sp{\sn fCalloutMinusX}{\sv 0}}{\sp{\sn fCalloutMinusY}{\sv 0}}{\sp{\sn fCalloutDropAuto}{\sv 0}} +{\sp{\sn fCalloutLengthSpecified}{\sv 0}}{\sp{\sn lidRegroup}{\sv 5}}{\shptxt \pard\plain \qr\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {\f1\lang3079 4 +\par }}}}{\shp{\*\shpinst\shplid1389{\sp{\sn relLeft}{\sv 9558}}{\sp{\sn relTop}{\sv 7140}}{\sp{\sn relRight}{\sv 10008}}{\sp{\sn relBottom}{\sv 7515}}{\sp{\sn fRelFlipH}{\sv 0}} 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{\lang1024\cgrid {\shpgrp{\*\shpinst\shpleft1774\shptop25\shpright8059\shpbottom1300\shpfhdr0\shpbxcolumn\shpbypara\shpwr3\shpwrk0\shpfblwtxt0\shpz7\shplid1705 +{\sp{\sn groupLeft}{\sv 2925}}{\sp{\sn groupTop}{\sv 1755}}{\sp{\sn groupRight}{\sv 9210}}{\sp{\sn groupBottom}{\sv 3030}}{\sp{\sn fFlipH}{\sv 0}}{\sp{\sn fFlipV}{\sv 0}}{\shp{\*\shpinst\shplid1706 +{\sp{\sn relLeft}{\sv 2925}}{\sp{\sn relTop}{\sv 1755}}{\sp{\sn relRight}{\sv 9210}}{\sp{\sn relBottom}{\sv 3030}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 2}}}} +{\shp{\*\shpinst\shplid1707{\sp{\sn relLeft}{\sv 3329}}{\sp{\sn relTop}{\sv 1910}}{\sp{\sn relRight}{\sv 3386}}{\sp{\sn relBottom}{\sv 1967}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 3}}{\sp{\sn fillColor}{\sv 0}} +{\sp{\sn fFilled}{\sv 1}}{\sp{\sn lidRegroup}{\sv 11}}}}{\shp{\*\shpinst\shplid1708{\sp{\sn relLeft}{\sv 3617}}{\sp{\sn relTop}{\sv 1910}}{\sp{\sn relRight}{\sv 3674}}{\sp{\sn relBottom}{\sv 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1}}{\sp{\sn lidRegroup}{\sv 11}}}}{\shp{\*\shpinst\shplid1715{\sp{\sn relLeft}{\sv 6209}}{\sp{\sn relTop}{\sv 1910}} +{\sp{\sn relRight}{\sv 6266}}{\sp{\sn relBottom}{\sv 1967}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 3}}{\sp{\sn fillColor}{\sv 0}}{\sp{\sn fFilled}{\sv 1}}{\sp{\sn lidRegroup}{\sv 11}}}} +{\shp{\*\shpinst\shplid1716{\sp{\sn relLeft}{\sv 5921}}{\sp{\sn relTop}{\sv 1910}}{\sp{\sn relRight}{\sv 5978}}{\sp{\sn relBottom}{\sv 1967}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 3}}{\sp{\sn fillColor}{\sv 0}} +{\sp{\sn fFilled}{\sv 1}}{\sp{\sn lidRegroup}{\sv 11}}}}{\shp{\*\shpinst\shplid1717{\sp{\sn relLeft}{\sv 5633}}{\sp{\sn relTop}{\sv 1910}}{\sp{\sn relRight}{\sv 5690}}{\sp{\sn relBottom}{\sv 1967}}{\sp{\sn fRelFlipH}{\sv 0}} +{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 3}}{\sp{\sn fillColor}{\sv 0}}{\sp{\sn fFilled}{\sv 1}}{\sp{\sn lidRegroup}{\sv 11}}}}{\shp{\*\shpinst\shplid1718{\sp{\sn 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0}}{\sp{\sn fFilled}{\sv 1}}{\sp{\sn lidRegroup}{\sv 11}}}} +{\shp{\*\shpinst\shplid1728{\sp{\sn relLeft}{\sv 7937}}{\sp{\sn relTop}{\sv 2761}}{\sp{\sn relRight}{\sv 7994}}{\sp{\sn relBottom}{\sv 2818}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 3}}{\sp{\sn fillColor}{\sv 0}} +{\sp{\sn fFilled}{\sv 1}}{\sp{\sn lidRegroup}{\sv 11}}}}{\shp{\*\shpinst\shplid1729{\sp{\sn relLeft}{\sv 8225}}{\sp{\sn relTop}{\sv 2761}}{\sp{\sn relRight}{\sv 8282}}{\sp{\sn relBottom}{\sv 2818}}{\sp{\sn fRelFlipH}{\sv 0}} +{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 3}}{\sp{\sn fillColor}{\sv 0}}{\sp{\sn fFilled}{\sv 1}}{\sp{\sn lidRegroup}{\sv 11}}}}{\shp{\*\shpinst\shplid1730{\sp{\sn relLeft}{\sv 8513}}{\sp{\sn relTop}{\sv 2761}} +{\sp{\sn relRight}{\sv 8570}}{\sp{\sn relBottom}{\sv 2818}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 3}}{\sp{\sn fillColor}{\sv 0}}{\sp{\sn fFilled}{\sv 1}}{\sp{\sn lidRegroup}{\sv 11}}}} +{\shp{\*\shpinst\shplid1731{\sp{\sn relLeft}{\sv 8801}}{\sp{\sn relTop}{\sv 2761}}{\sp{\sn relRight}{\sv 8858}}{\sp{\sn relBottom}{\sv 2818}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 3}}{\sp{\sn fillColor}{\sv 0}} +{\sp{\sn fFilled}{\sv 1}}{\sp{\sn lidRegroup}{\sv 11}}}}{\shp{\*\shpinst\shplid1732{\sp{\sn relLeft}{\sv 6209}}{\sp{\sn relTop}{\sv 2761}}{\sp{\sn relRight}{\sv 6266}}{\sp{\sn relBottom}{\sv 2818}}{\sp{\sn fRelFlipH}{\sv 0}} +{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 3}}{\sp{\sn fillColor}{\sv 0}}{\sp{\sn fFilled}{\sv 1}}{\sp{\sn lidRegroup}{\sv 11}}}}{\shp{\*\shpinst\shplid1733{\sp{\sn relLeft}{\sv 6497}}{\sp{\sn relTop}{\sv 2761}} +{\sp{\sn relRight}{\sv 6554}}{\sp{\sn relBottom}{\sv 2818}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 3}}{\sp{\sn fillColor}{\sv 0}}{\sp{\sn fFilled}{\sv 1}}{\sp{\sn lidRegroup}{\sv 11}}}} +{\shp{\*\shpinst\shplid1734{\sp{\sn relLeft}{\sv 6785}}{\sp{\sn relTop}{\sv 2761}}{\sp{\sn relRight}{\sv 6842}}{\sp{\sn relBottom}{\sv 2818}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 3}}{\sp{\sn fillColor}{\sv 0}} +{\sp{\sn fFilled}{\sv 1}}{\sp{\sn lidRegroup}{\sv 11}}}}{\shp{\*\shpinst\shplid1735{\sp{\sn relLeft}{\sv 7073}}{\sp{\sn relTop}{\sv 2761}}{\sp{\sn relRight}{\sv 7130}}{\sp{\sn relBottom}{\sv 2818}}{\sp{\sn fRelFlipH}{\sv 0}} +{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 3}}{\sp{\sn fillColor}{\sv 0}}{\sp{\sn fFilled}{\sv 1}}{\sp{\sn lidRegroup}{\sv 11}}}}{\shp{\*\shpinst\shplid1736{\sp{\sn relLeft}{\sv 7361}}{\sp{\sn relTop}{\sv 2761}} +{\sp{\sn relRight}{\sv 7418}}{\sp{\sn relBottom}{\sv 2818}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 3}}{\sp{\sn fillColor}{\sv 0}}{\sp{\sn fFilled}{\sv 1}}{\sp{\sn lidRegroup}{\sv 11}}}} +{\shp{\*\shpinst\shplid1737{\sp{\sn relLeft}{\sv 4769}}{\sp{\sn relTop}{\sv 2761}}{\sp{\sn relRight}{\sv 4826}}{\sp{\sn relBottom}{\sv 2818}}{\sp{\sn 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lidRegroup}{\sv 11}}}}{\shp{\*\shpinst\shplid1744{\sp{\sn relLeft}{\sv 3905}}{\sp{\sn relTop}{\sv 2761}}{\sp{\sn relRight}{\sv 3962}}{\sp{\sn relBottom}{\sv 2818}}{\sp{\sn fRelFlipH}{\sv 0}} +{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 3}}{\sp{\sn fillColor}{\sv 0}}{\sp{\sn fFilled}{\sv 1}}{\sp{\sn lidRegroup}{\sv 11}}}}{\shp{\*\shpinst\shplid1745{\sp{\sn relLeft}{\sv 4193}}{\sp{\sn relTop}{\sv 2761}} +{\sp{\sn relRight}{\sv 4250}}{\sp{\sn relBottom}{\sv 2818}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 3}}{\sp{\sn fillColor}{\sv 0}}{\sp{\sn fFilled}{\sv 1}}{\sp{\sn lidRegroup}{\sv 11}}}} +{\shp{\*\shpinst\shplid1746{\sp{\sn relLeft}{\sv 4481}}{\sp{\sn relTop}{\sv 2761}}{\sp{\sn relRight}{\sv 4538}}{\sp{\sn relBottom}{\sv 2818}}{\sp{\sn fRelFlipH}{\sv 0}}{\sp{\sn fRelFlipV}{\sv 0}}{\sp{\sn shapeType}{\sv 3}}{\sp{\sn fillColor}{\sv 0}} +{\sp{\sn fFilled}{\sv 1}}{\sp{\sn lidRegroup}{\sv 11}}}}}{\shprslt{\*\do\dobxcolumn\dobypara\dodhgt8199\dppolygon\dppolycount4\dpptx0\dppty0\dpptx6285\dppty0\dpptx6285\dppty1275\dpptx0\dppty1275\dpx1774\dpy25\dpxsize6285\dpysize1275 +\dpfillfgcr255\dpfillfgcg255\dpfillfgcb255\dpfillbgcr255\dpfillbgcg255\dpfillbgcb255\dpfillpat1\dplinew15\dplinecor0\dplinecog0\dplinecob0}}}}{\fs24 +\par +\par +\par +\par +\par }\pard \qj\fi720\li720\nowidctlpar\tx2835\adjustright {\fs24 40\endash \endash \endash \endash \endash \endash \endash \endash \endash \endash \endash \endash \endash \endash \endash \endash \endash \endash \endash \endash \endash \endash \endash +\endash \endash \endash \endash \endash \endash --------2 +\par }\pard \qj\nowidctlpar\tx426\tx1985\tx2835\adjustright { +\par }\pard\plain \s20\qj\nowidctlpar\tx567\tx1985\tx2835\adjustright \f2\fs22\lang2057 { 1 \tab 0V \tab \tab 2 R/notW +\par }\pard\plain \qj\nowidctlpar\tx567\tx1985\tx2835\adjustright \f2\fs22\lang2057 { 3 \tab 0V\tab \tab 4 2E +\par 5 \tab 0V\tab \tab 6 notIRQ +\par 7 \tab 0V\tab \tab 8 notTUBE +\par 9 \tab 0V\tab \tab 10 notRS +\par 11 \tab 0V \tab \tab 12 D0 +\par 13\tab 0V \tab \tab 14 D1 +\par 15\tab 0V\tab \tab 16 D2 +\par 17 \tab 0V \tab \tab 18 D3 +\par 19\tab 0V\tab \tab 20 D4 +\par 21\tab 0V \tab \tab 22 D5 +\par 23 \tab 0V\tab \tab 24 D6 +\par 25 \tab 0V \tab \tab 26 D7 +\par 27 \tab 0V\tab \tab 28 A0 +\par 29 \tab 0V\tab \tab 30 A1 +\par 31 \tab +5V \tab \tab 32 A2 +\par 33 \tab +5V \tab \tab 34 A3 +\par 35 \tab +5V \tab \tab 36 A4 +\par 37 \tab +5V \tab \tab 38 NC +\par 39 \tab +5V \tab \tab 40 NC}{\fs24 +\par }\pard \qj\sa240\nowidctlpar\tx2835\adjustright {\fs24 +\par }\pard\plain \s4\qj\keepn\nowidctlpar\tx2835\outlinelevel3\adjustright \f2\fs22\lang2057 {PL13 keyboard +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {17-pin molex +\par }\pard\plain \s20\qj\nowidctlpar\tx567\tx2835\adjustright \f2\fs22\lang2057 { 1 \tab 0V +\par }\pard\plain \qj\nowidctlpar\tx567\tx2835\adjustright \f2\fs22\lang2057 { 2 \tab BREAK +\par 3 \tab 1E +\par 4 \tab keyboard enable +\par 5 \tab SD4 +\par 6 \tab SD5 +\par 7 \tab SD6 +\par 8 \tab SD0 +\par }\pard\plain \s20\qj\nowidctlpar\tx567\tx2835\adjustright \f2\fs22\lang2057 { 9 \tab SD1 +\par 10 \tab SD2 +\par }\pard\plain \qj\nowidctlpar\tx567\tx2835\adjustright \f2\fs22\lang2057 {11 \tab SD3 +\par 12 \tab SD7 +\par 13 \tab cassette LED +\par 14 \tab CA2 (to generate IRQ) +\par 15 \tab +5V +\par 16 \tab shift lock LED +\par 17 \tab caps lock LED +\par }\pard\plain \s1\qj\sa240\nowidctlpar\tx2835\outlinelevel0\adjustright \b\f2 {\page Parts list +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {NOTE: Items identified by * are normally available as spare parts \endash please contact your supplier for details of availability. +\par }\pard \qj\sa240\nowidctlpar\tx851\tx2268\tx2835\tx6237\tx6804\adjustright {ITEM PART NO\tab \tab DESCRIPTION\tab QTY\tab REMARKS +\par }\pard\plain \s20\qj\sa240\nowidctlpar\tx851\tx2268\tx2835\tx6237\tx6804\adjustright \f2\fs22\lang2057 {BBC Microcomputer Model B+ PCB Assembly +\par }\pard\plain \qj\nowidctlpar\tx851\tx2268\tx2835\tx6237\tx6804\adjustright \f2\fs22\lang2057 {1 +\par 2 +\par 3 +\par 4\tab \tab \tab RESISTOR SOT 0.25W 5%\tab 1\tab R76 TYP 3k3 to 6k8 +\par 5\tab 0502,100\tab \tab RESISTOR 10R 0.25W 5%\tab 4\tab R58,121,122,153 +\par 6\tab 0502,330\tab \tab RESISTOR 33R 0.25W 5%\tab 3\tab R53-55 +\par 7\tab 0502,680\tab \tab RESISTOR 68R 0.25W 5%\tab 6\tab R94,l09,112,128-130 +\par 8\tab 0502,820\tab \tab RESISTOR 82R 0.25W 5%\tab 3\tab R62,65,67 +\par 9\tab 0502,101\tab \tab RESISTOR 100R 0.25W 5%\tab 6\tab R31,45-47,57,61 +\par 10\tab 0502,151\tab \tab RESISTOR 150R 0.25W 5%\tab 5\tab R1,5-8 +\par }\pard\plain \s20\qj\nowidctlpar\tx851\tx2268\tx2835\tx6237\tx6804\adjustright \f2\fs22\lang2057 {11\tab 0502,180\tab \tab RESISTOR 18R 1W 10%\tab 1\tab R37 +\par }\pard\plain \qj\nowidctlpar\tx851\tx2268\tx2835\tx6237\tx6804\adjustright \f2\fs22\lang2057 {\tab \tab \tab \tab \tab FERRANTI IC53 ONLY +\par 12\tab 0502,271\tab \tab RESISTOR 270R 0.25W 5%\tab 3\tab R20,21,40 +\par 13\tab 0502,331\tab \tab RESISTOR 330R 0.25W 5%\tab 2\tab R30,35 +\par 14\tab 0502,471\tab \tab RESISTOR 470R 0.25W 5%\tab 4\tab R49,75,88,102 +\par 15\tab 0502,681\tab \tab RESISTOR 680R 0.25W 5%\tab 3\tab R85,91,92 +\par 16\tab 0502,821\tab \tab RESISTOR 820R 0.25W 5%\tab 1\tab R86 +\par 17 +\par 18 +\par 19 +\par 20 +\par 21\tab 0502,102\tab \tab RESISTOR 1K 0.25W5%\tab 16\tab R3#,11,16,36,38, +\par \tab \tab \tab \tab \tab R63,68,73,84,104, +\par \tab \tab \tab \tab \tab R105,107,131-133,148 +\par 22\tab 0502,122\tab \tab RESISTOR 1K2 0.25W 5%\tab 1\tab R89 +\par 23\tab 0502,152\tab \tab RESISTOR 1K5 0.25W 5%\tab 4\tab R82,146,147,154 +\par 24\tab 0502,182\tab \tab RESISTOR 1K8 0.25W 5%\tab 3\tab R50-52 +\par 25\tab 0502,222\tab \tab RESISTOR 2K2 0.25W 5%\tab 8\tab R74,80,87,101,114, +\par \tab \tab \tab \tab \tab R120, 124,149 +\par 26\tab 0502,272\tab \tab RESISTOR 2K7 0.25W 5%\tab 2\tab R69,138 +\par 27\tab 0502,332\tab \tab RESISTOR 3K3 0.25W 5%\tab 10\tab R9#,10#,14,18,19, +\par \tab \tab \tab \tab \tab R56,71,90,118,152 +\par 28\tab 0502,392\tab \tab RESISTOR 3K9 0.25W 5%\tab 4\tab R93,108,139,150 +\par 29\tab 0502,472\tab \tab RESISTOR 4K7 0.25W 5%\tab 7\tab R4,23,43,48, +\par \tab \tab \tab \tab \tab R59,60,100 +\par 30\tab 0502,562\tab \tab RESISTOR 5K6 0.25W 5%\tab 1\tab R103 +\par 31\tab 0502,822\tab \tab RESISTOR 8K2 0.25W 5%\tab 2\tab Rl23,127 +\par 32 +\par 33\tab 0502,103\tab \tab RESISTOR 10K 0.25W 5%\tab 13\tab R2#,22,26,27,29, +\par \tab \tab \tab \tab \tab R34,42,44,81,\tab \tab \tab \tab \tab \tab \tab R111,126,144,151 +\par 34\tab 0502,123\tab \tab RESISTOR 12K 0.25W 5%\tab 1\tab R116 +\par 35\tab 0502,153\tab \tab RESISTOR 15K 0.25W 5%\tab 1\tab R115 +\par 36\tab 0502,223\tab \tab RESISTOR 22K 0.25W 5%\tab 1\tab R72 +\par +\par Components marked # are fitted only with 8271 disc interface. +\par \page 37\tab 0502,393\tab \tab RESISTOR 39K 0.25W 5%\tab 2\tab R64,117 +\par 38\tab 0502,563\tab \tab RESISTOR 56K 0.25W 5%\tab 1\tab R15 +\par 39\tab 0502,623\tab \tab RESISTOR 62K 0.25W 5%\tab 1\tab R33 +\par 40\tab 0502,823\tab \tab RESISTOR 82K 0.25W 5%\tab 1\tab R66 +\par 41\tab 0502,104\tab \tab RESISTOR 100K 0.25W 5%\tab 3\tab R28,41,70 +\par 42\tab 0502,154\tab \tab RESISTOR 150K 0.25W 5%\tab 2\tab R137,145 +\par 43\tab 0502,224\tab \tab RESISTOR 220K 0.25W 5%\tab 3\tab R39,77,136 +\par 44\tab 0502,274\tab \tab RESISTOR 270K 0.25W 5%\tab 1\tab R83 +\par 45\tab 0502,824\tab \tab RESISTOR 820K 0.25W 5%\tab 1\tab R135 +\par 46\tab 0505,103\tab \tab RESISTOR 10K 0.25W 2%\tab 4\tab R140-143 +\par 47\tab 0505,563\tab \tab RESISTOR 56K 0.25W 2%\tab 4\tab R95,96,98,99 +\par 48\tab 0505,104\tab \tab RESISTOR 100K 0.25W 2%\tab 4\tab R106,110,125,134 +\par 49 +\par 50\tab 0502,105\tab \tab RESISTOR 1M0 0.25W 5%\tab 3\tab R17,24,25 +\par 51\tab 0502,155\tab \tab RESISTOR 1M5 0.25W 5%\tab 3\tab R78,79,97 +\par 52 +\par 53\tab 0520,180\tab \tab RESISTOR 18R 1W0 10%\tab 1\tab R37 +\par 54\tab 0581,103\tab \tab POTENTIOMETER 10K 20%\tab 1\tab VR2 +\par 55\tab 0581,104\tab \tab POTENTIOMETER 100K 20%\tab 1\tab VR1 +\par }\pard \qj\ri7920\nowidctlpar\tx851\tx2268\tx2835\tx6237\tx6804\adjustright {56 +\par 57 +\par }\pard \qj\ri720\nowidctlpar\tx851\tx2268\tx2835\tx6237\tx6804\adjustright {58\tab 0590,223\tab \tab RESISTOR PACK SIL 22Kx8\tab 1\tab RP2 +\par 59\tab 0590,682\tab \tab RESISTOR PACK SIL 6K8x9\tab 1\tab RP1 +\par }\pard \qj\ri7920\nowidctlpar\tx851\tx2268\tx2835\tx6237\tx6804\adjustright {60 +\par 61 +\par 62 +\par 63 +\par 64 +\par 65 +\par }\pard \qj\nowidctlpar\tx851\tx2268\tx2835\tx6237\tx6804\adjustright {66\tab 0631,010\tab \tab CAPACITOR 10pF CERAMIC\tab 1\tab C39 +\par 67\tab 0631,033\tab \tab CAPACITOR 33pF CERAMIC\tab 2\tab C12,16 +\par 68\tab 0631,039\tab \tab CAPACITOR 39pF CERAMIC\tab 1\tab C40 +\par 69 \tab 0631,047\tab \tab CAPACITOR 47pF CERAMIC\tab 3\tab C44,45,49 +\par 70 \tab 0631,068\tab \tab CAPACITOR 68pF CERAMIC\tab 3\tab C4,17,18 +\par 71\tab 0631,100\tab \tab CAPACITOR 100pF CERAMIC\tab 3\tab C20,53,55 +\par 72 +\par 73\tab 0631,150\tab \tab CAPACITOR 150pF CERAMIC\tab 1\tab C36 +\par 74\tab 0631,270\tab \tab CAPACITOR 270pF CERAMIC\tab 1\tab C22 +\par 75\tab 0630,039\tab \tab CAPACITOR 390pF CERAMIC\tab 1\tab C47 +\par 76\tab 0630,047\tab \tab CAPACITOR 470pF CERAMIC\tab 1\tab C48 +\par 77\tab 0630,082\tab \tab CAPACITOR 820pF CERAMIC\tab 2\tab C58,59 +\par }\pard \qj\ri7920\nowidctlpar\tx851\tx2268\tx2835\tx6237\tx6804\adjustright {78 +\par 79 +\par }\pard \qj\nowidctlpar\tx851\tx2268\tx2835\tx6237\tx6804\adjustright {80\tab 0630,100\tab \tab CAPACITOR 1n0F CERAMIC\tab 1\tab C1# +\par 81\tab 0630,150\tab \tab CAPACITOR 1n5F CERAMIC\tab 1\tab C11 +\par 82\tab 0630,220\tab \tab CAPACITOR 2n2F CERAMIC\tab 4\tab C26,31,34,35 +\par 83\tab 0630,330\tab \tab CAPACITOR 3n3F CERAMIC\tab 1\tab C8 +\par 84\tab 0630,470\tab \tab CAPACITOR 4n7F CERAMIC\tab 5\tab C19, 21, 32, 42, 43 +\par 85\tab 0629,0l0\tab \tab CAPACITOR 10nF CERAMIC\tab 3\tab C3,13,28 +\par 86\tab 0650,333\tab \tab CAPACITOR 33nF POLY\tab 1\tab C29 +\par }\pard \qj\sa240\nowidctlpar\tx851\tx2268\tx2835\tx6237\tx6804\adjustright { +\par Components marked # are fitted only with 8271 disc interface. +\par }\pard \qj\nowidctlpar\tx851\tx2268\tx2835\tx6237\tx6804\adjustright {\page 87\tab 0680,002\tab \tab CAPACITOR 33/47nF DECUP\tab 64/67 A +\par 88\tab 0640,473\tab \tab CAPACITOR 47nF CERAMIC\tab 1\tab C24 +\par 89\tab 0640,104\tab \tab CAPACITOR 100nF CERAMIC\tab 5\tab C5-7,9,23 +\par 90\tab 0651,224\tab \tab CAPACITOR 220nF CERAMIC\tab 2\tab C38,41 +\par 91 +\par }\pard\plain \s20\qj\nowidctlpar\tx851\tx2268\tx2835\tx6237\tx6804\adjustright \f2\fs22\lang2057 {92\tab 0613,100\tab \tab CAPACITOR 1uF TANT\tab 1\tab C33 +\par }\pard\plain \qj\nowidctlpar\tx851\tx2268\tx2835\tx6237\tx6804\adjustright \f2\fs22\lang2057 {93\tab 0635,047\tab \tab CAPACITOR 4u7F 16V ELEC\tab 1\tab C30 +\par \tab \tab \tab RADIAL +\par 94\tab 0635,100\tab \tab CAPACITOR 10uF 16V ELEC\tab 3\tab C27,51,52 +\par \tab \tab \tab RADIAL +\par 95\tab 0621,047\tab \tab CAPACITOR 4u7F 10V ELEC\tab 1\tab Cl5 +\par \tab \tab \tab AXIAL +\par 96\tab 0610,010\tab \tab CAPACITOR 10uF 10V TANT\tab 1\tab C57 +\par 97\tab 0621,470\tab \tab CAPACITOR 47uF 10V ELEC\tab 6\tab C25,46,50,54,56,60 +\par \tab \tab \tab AXIAL +\par 98\tab 0610,047\tab \tab CAPACITOR 47uF 10V TANT\tab 1\tab C37 +\par 99\tab 0620,100\tab \tab CAPACITOR 10uF 6V3 ELEC\tab 1\tab C14 +\par \tab \tab \tab AXIAL +\par 100 +\par 101\tab 0699,003\tab *\tab CAPACITOR TRIM 5-65pF\tab 1\tab VC1 +\par 102 +\par 103 +\par 104\tab 0860,005\tab *\tab CHOKE 33uH\tab 1\tab L1 +\par 105 +\par 106 +\par 107\tab 0820,160\tab *\tab CRYSTAL 16MHZ\tab 1\tab X1 +\par 108\tab 0820,177\tab *\tab CRYSTAL 17.734475MHZ\tab 1\tab X2 +\par 109 +\par 110 +\par 111\tab 0810,001\tab *\tab RELAY 5V\tab 1\tab RL1 +\par 112 +\par 113 +\par 114\tab 0780,239\tab *\tab TRANSISTOR BC239\tab 7\tab Q1-5,7,9 +\par 115\tab 0780,309\tab *\tab TRANSISTOR BC309\tab 2\tab Q6,8 +\par 116 +\par }\pard\plain \s20\qj\nowidctlpar\tx851\tx2268\tx2835\tx6237\tx6804\adjustright \f2\fs22\lang2057 {117\tab 0783,906\tab *\tab TRANSISTOR 2N3906 \tab 1\tab Q10 +\par }\pard\plain \qj\nowidctlpar\tx851\tx2268\tx2835\tx6237\tx6804\adjustright \f2\fs22\lang2057 {118 +\par 119 +\par 120\tab 0794,148\tab *\tab DIODE 1N4148\tab 14\tab D1#,D2-4,8-18 +\par 121\tab 0794,001\tab \tab DIODE IN4001\tab 3\tab D5-7 +\par 122 +\par 123 +\par 124\tab 0740,016\tab *\tab IC 7416\tab 1\tab IC8 +\par \tab 0740.006\tab *\tab IC 7406\tab 1\tab IC8 OPTION +\par 125\tab 0740,038\tab *\tab IC 7438\tab 1\tab IC7 +\par 126\tab 0741,000\tab *\tab IC 74S00\tab 1\tab IC52 +\par 127\tab 0742,000\tab *\tab IC 74LS00\tab 5\tab IC9#,19,27,87,90 +\par 128\tab 0741,002\tab *\tab IC 74S02\tab 1\tab IC33 +\par }\pard \qj\sa240\nowidctlpar\tx851\tx2268\tx2835\tx6237\tx6804\adjustright { +\par Components marked # are fitted only with 8271 disc interface; +\par }\pard \qj\nowidctlpar\tx851\tx2268\tx2835\tx6237\tx6804\adjustright {\page 129\tab 0742,002\tab *\tab IC 74LS02\tab 1\tab IC58 +\par 130\tab 0741,004\tab *\tab IC 74S04\tab 1\tab IC26 +\par 131\tab 0742,004\tab *\tab IC 74LS0\tab 1\tab IC24 +\par 132\tab 0742,008\tab *\tab IC 74LS0\tab 1\tab IC34 +\par 133\tab 0742,010\tab *\tab IC 74LS1\tab 1\tab IC48 +\par 134\tab 0742,020\tab *\tab IC 74LS2\tab 1\tab IC40 +\par 135\tab 0742,030\tab *\tab IC 74LS3\tab 2\tab IC22,41 +\par 136\tab 0742,032\tab *\tab IC 74LS32\tab 1\tab IC23 +\par 137\tab 0741,074\tab *\tab IC 74S74\tab 2\tab IC31,79 +\par 138\tab 0742,074\tab *\tab IC 74LS7\tab 1\tab IC69 +\par 139\tab 0742,086\tab *\tab IC 74LS86\tab 3\tab IC63,83,86 +\par 140\tab 0742,109\tab *\tab IC 74LS109\tab 1\tab IC25 +\par 141\tab 0742,123\tab *\tab IC 74LS123\tab 2\tab IC1#,88 +\par 142\tab 0742,132\tab *\tab IC 74LS132\tab 1\tab IC70 +\par 143 \tab 0742,138\tab *\tab IC 74LS138\tab 2\tab IC21,46 +\par 144\tab 0742,139\tab *\tab IC 74LS139\tab 2\tab IC28,39 +\par 145\tab 0742,163\tab *\tab IC 74LS163\tab 2\tab IC18,45 +\par 146\tab 0742,174\tab *\tab IC 74LS174\tab 1\tab IC17 1770 ONLY +\par 147\tab 0742,244\tab *\tab IC 74LS244\tab 4\tab IC5,6,13,80 +\par 148\tab 0742,245\tab *\tab IC 74LS245\tab 3\tab IC12,14,49 +\par 149\tab 0742,253\tab *\tab IC 74LS253\tab 4\tab IC72-75 +\par 150\tab 0742,257\tab *\tab IC 74LS257\tab 2\tab IC50, 51 +\par 151\tab 0742,259\tab *\tab IC 74IS259\tab 1\tab IC30 +\par 152\tab 0742,273\tab *\tab IC 74LS273\tab 1\tab IC54 +\par 153\tab 0742,283\tab *\tab IC 74LS283\tab 1\tab IC76 +\par 154\tab 0742,374\tab *\tab IC 74LS374\tab 2\tab IC11,32 +\par 155\tab 0742,393\tab *\tab IC 74LS393\tab 1\tab IC2# +\par 156\tab 0739,120\tab *\tab IC DS88LS120N\tab 1\tab IC94 +\par 157\tab 0770,319\tab *\tab IC LM319\tab 2\tab IC92,93 +\par 158\tab 0770,324\tab *\tab IC LM324\tab 2\tab IC47,89 +\par 159\tab 0770,386\tab *\tab IC LM386\tab 1\tab IC77 +\par 160\tab 0733,691\tab *\tab IC DS3691N\tab 1\tab IC95 +\par 161\tab 0704,865\tab *\tab IC 4164-12\tab 8\tab IC55,56,60,61,64-67 +\par \tab \tab \tab IC TM4164EK8-12\tab 1\tab IC96 OPTIONAL +\par 162 \tab 0706,511\tab *\tab IC 6512A\tab 1\tab IC42 +\par 163 \tab 0706,522\tab *\tab IC 6522\tab 2\tab IC10,20 +\par 164 \tab 0706,845\tab *\tab IC 6845\tab 1\tab IC78 +\par 165\tab 0706,850\tab *\tab IC 6850\tab 1\tab IC82 +\par 166 \tab 0707,002\tab *\tab IC uPD7002\tab 1\tab IC84 +\par 167\tab 0735,159\tab *\tab IC SN75159N\tab 1\tab IC91 +\par 168\tab 0706,490\tab *\tab IC SN76489N\tab 1\tab IC38 +\par 169\tab 0708,271\tab *\tab IC 8271\tab 1\tab IC15# +\par 170 \tab 0706,854\tab *\tab IC 68B54\tab 1\tab IC81 +\par 171\tab 0753,521\tab \tab IC HEF 4521B\tab 1\tab IC4# +\par 172\tab 0754,013\tab *\tab IC HEF 4013B\tab 1\tab IC3# +\par 173 \tab 0705,050\tab *\tab IC SAA 5050\tab 1\tab IC59 +\par 174 \tab 0201,241\tab *\tab IC OS/BASIC ROM (B+)\tab 1\tab IC71 +\par 175 \tab 0201,666\tab *\tab IC DNFS 3.0 ROM \tab 1\tab IC35# +\par }\pard \qj\sa240\nowidctlpar\tx851\tx2268\tx2835\tx6237\tx6804\adjustright { +\par Components marked # are fitted only with 8271 disc interface. +\par IC35 is also fitted for ECONET. +\par }\pard \qj\nowidctlpar\tx851\tx2268\tx2835\tx6237\tx6804\adjustright {\page 176\tab 2201,113\tab *\tab IC 1770 DFS ROM\tab 1\tab IC57 1770 ONLY +\par 177\tab 0201,274\tab *\tab IC ADFS ROM\tab 1\tab IC44 +\par 178 +\par 179 +\par 180\tab 0201,647\tab *\tab IC V10 V2 PROC\tab 1\tab IC53 +\par 181\tab 0201,648\tab *\tab IC SERPROC\tab 1\tab IC85 +\par \tab 0201,602\tab \tab IC 2C199\tab 1\tab OPTION FOR IC85 +\par 182\tab 0770,555\tab *\tab IC LM555\tab 1\tab IC43 +\par 183\tab 0201,880\tab *\tab IC PAL 16R4\tab 1\tab IC36 +\par 184\tab 0701,770\tab *\tab IC 1770\tab 1\tab IC16 +\par 185 +\par 186 +\par 187 +\par 188 +\par 189 +\par 190 +\par 191\tab 0800,114\tab *\tab IC SOCKET DIL 14P\tab \tab OPTION +\par 192\tab 0800,116\tab *\tab IC SOCKET DIL 16P\tab \tab OPTION +\par 193 +\par 194 +\par 195\tab 0800,128\tab *\tab IC SOCKET DIL 28P\tab 9\tab IC29,35.37,44,53, +\par \tab \tab \tab \tab \tab IC57,62,68,71 +\par 196 +\par 197\tab 0800,006\tab *\tab CONNECTOR IDC 34 WAY\tab 2\tab PL8,11 +\par 198\tab 0800,007\tab *\tab CONNECTOR IDC 40 WAY\tab 1\tab PL12 +\par 199\tab 0800,008\tab *\tab CONNECTOR IDC 26 WAY\tab 1\tab PL9 +\par 200\tab 0800,050\tab *\tab PLUG 2 WAY\tab 3\tab PL15, S26 +\par 201\tab 0800,051\tab *\tab PLUG 3 WAY\tab 4\tab S13,14,20,27 +\par 202\tab 0800,052\tab *\tab PLUG 5 WAY\tab 3\tab SK3/A,S9,11,12,15,18 +\par 203\tab 0800,054\tab *\tab PLUG 8 WAY\tab 2\tab S23 +\par 204\tab 0800,055\tab *\tab PLUG 10 WAY\tab 1\tab PL14 +\par 205\tab 0800,059\tab *\tab PLUG 17 WAY\tab 1\tab PL13 +\par 206 +\par }\pard\plain \s20\qj\nowidctlpar\tx851\tx2268\tx2835\tx6237\tx6804\adjustright \f2\fs22\lang2057 {207\tab 0800,009\tab *\tab CONNECTOR IDC 20 WAY\tab 1\tab PL10 +\par }\pard\plain \qj\nowidctlpar\tx851\tx2268\tx2835\tx6237\tx6804\adjustright \f2\fs22\lang2057 {208 +\par 209\tab 0800,070\tab *\tab SHUNTS\tab 16\tab S9,11-15,18,20, +\par \tab \tab \tab \tab \tab S23(7off),27 +\par 210\tab 0870,420\tab \tab TINNED COPPER WIRE\tab A/R\tab S7,8,16,R12,32 +\par 211 +\par 212\tab 0800,200\tab *\tab FASTON TABS\tab 7\tab +5V(3) 0V(3) -5V(1) +\par 213 +\par 214 +\par 215\tab 0800,004\tab *\tab SOCKET DIN 5 WAY\tab 1\tab SK7 +\par }\pard \qj\nowidctlpar\tx2835\adjustright {216 +\par }\pard \qj\nowidctlpar\tx851\tx2268\tx2835\tx6237\tx6804\adjustright {217\tab 0800,002\tab *\tab SOCKET DIN 6 WAY\tab 1\tab SK3 +\par 218\tab 0800,001\tab *\tab SOCKET DIN 5 WAY DOMINO\tab 1\tab SK4 +\par 219\tab 0800,003\tab *\tab SOCKET DIN 7 WAY\tab 1\tab SK5 +\par 220\tab 0800,304\tab *\tab SOCKET D TYPE 15 WAY\tab 1\tab SK6 +\par 221 +\par \page 222\tab 0825,000\tab *\tab MODULATOR UM 1233 E36\tab 1\tab SK1 +\par 223 +\par 224 +\par 225 +\par 226\tab 0705,220\tab *\tab IC TMS 5220 (SPEECH)\tab 1\tab IC29 +\par 227\tab 0201,608\tab *\tab IC SPEECH PHROM V1 6100\tab 1\tab IC37 +\par 228 +\par }\pard \qj\sa240\nowidctlpar\tx851\tx2268\tx2835\tx6237\tx6804\adjustright { +\par NOTE: SOT denotes Select On Test and therefore the value of the component will vary from machine to machine. +\par BBC Microcomputer Model B+ General Assembly +\par }\pard\plain \s20\qj\nowidctlpar\tx851\tx2268\tx2835\tx6521\adjustright \f2\fs22\lang2057 {1\tab 0103,001\tab *\tab KEYBOARD ISS 2\tab 1 +\par }\pard\plain \qj\nowidctlpar\tx851\tx2268\tx2835\tx6521\adjustright \f2\fs22\lang2057 {\tab \tab \tab (INC. SPEAKER) +\par 2\tab 0201,233\tab *\tab CASE UPPER ISS 5\tab 1 +\par 3\tab 0201,232\tab *\tab CASE LOWER ISS 4\tab 1 +\par 4\tab 0201,098\tab *\tab REAR ACCESS IABEL ISS 6\tab 1 +\par 5\tab 0201,111\tab *\tab BOTTOM ACCESS LABL ISS4\tab 1 +\par 6\tab 0201,096\tab *\tab KEYBOARD LABEL ISS. 4\tab 1 +\par 7\tab 0800,600\tab *\tab BNC CONNECTOR 75R\tab 1 +\par 8\tab 0890,000\tab *\tab 'STICK ON' FOOT\tab 4 +\par 9\tab 0882,988\tab \tab 4BA INT WASHER\tab 2 +\par 10\tab 0882,986\tab \tab NYLON WASHER 1/D 5\tab 5 +\par 11\tab 0882,948\tab \tab No 8 SPIRE NUT\tab 2 +\par 12\tab 0882,914\tab \tab 4BA NUT FULL\tab 2 +\par 13\tab 0882,712\tab \tab No 4x7/16" PAN HD SUPER\tab 2 +\par 14\tab 0882,649\tab \tab No 8x19 FL HD POSI\tab 4 +\par }\pard\plain \s20\qj\nowidctlpar\tx851\tx2268\tx2835\tx6521\adjustright \f2\fs22\lang2057 {15\tab 0882,644\tab \tab No 8x9.5 FL HD POSI\tab 5 +\par }\pard\plain \qj\nowidctlpar\tx851\tx2268\tx2835\tx6521\adjustright \f2\fs22\lang2057 {16\tab 0882,343\tab \tab 4BA x 5/8 PAN HD POSI\tab 2 +\par 17\tab 0882,122\tab \tab M3 x 8 PAN HD POSI\tab 3 +\par }\pard\plain \s20\qj\nowidctlpar\tx851\tx2268\tx2835\tx6521\adjustright \f2\fs22\lang2057 {18\tab 0831,105\tab *\tab P.S.U \tab 1 +\par }\pard\plain \s1\qj\sa240\nowidctlpar\tx2835\outlinelevel0\adjustright \b\f2 {\fs22 \page }{Glossary +\par }\pard\plain \qj\ri824\nowidctlpar\tx1418\tx2835\adjustright \f2\fs22\lang2057 {ACK\tab ACKnowledge line on the printer port +\par }\pard \qj\fi-1440\li1440\ri824\nowidctlpar\tx1418\tx2835\adjustright {ACIA\tab Asynchronous Communications Interface Adaptor \endash serial to parallel and parallel to serial converter (6850) +\par }\pard \qj\ri824\nowidctlpar\tx1418\tx2835\adjustright {ADC\tab Analogue to Digital Converter +\par ADLC\tab Advanced Data Link Controller \endash ECONET control IC (68B54) +\par }\pard \qj\fi-1440\li1440\ri824\nowidctlpar\tx1418\tx2835\adjustright {ADSR\tab Attack, Decay, Sustain, Release \endash defining the envelope of a sound +\par ASCII\tab American Standard Code for Information Interchange \endash binary code for representing alphanumeric characters. +\par }\pard \qj\ri824\nowidctlpar\tx1418\tx2835\adjustright {BASIC\tab Beginners All-purpose Symbolic Instruction Code +\par BBC\tab British Broadcasting Corporation +\par }\pard \qj\ri824\sa240\nowidctlpar\tx1418\tx2835\adjustright {BNC\tab Bayonet-Neill-Concelman \endash the type of bayonet connector used for the video output +\par }\pard \qj\ri824\nowidctlpar\tx1418\tx2835\adjustright {CA1/2\tab Control lines associated with the PA port on a VIA +\par CAS\tab Column Address Strobe \endash control line for the DRAM +\par CB1/2\tab ontrol lines associated with the PB port on a VIA +\par CPU\tab Central Processor Unit (6512) +\par CR\tab Capacitor Resistor network +\par CRT\tab Cathode Ray Tube +\par CRTC\tab Cathode Ray Tube Controller IC (6845) +\par CSYNC\tab Composite SYNChronisation pulse train for video/TV display +\par CTS\tab Clear To Send \endash control input on the RS423 port +\par CUTS\tab Computer Users Tape Standard +\par }\pard \qj\fi-1440\li1440\ri824\nowidctlpar\tx1418\tx2835\adjustright {DIN\tab European standard connector family used for the cassette socket, RGB socket etc +\par }\pard \qj\ri824\nowidctlpar\tx1418\tx2835\adjustright {DRAM\tab Dynamic Random Access Memory +\par EPROM\tab Erasable Programmable Read Only Memory +\par FIT\tab Final Inspection Tester +\par FDC\tab Floppy Disc Controller (1770 or 8271) +\par IC\tab Integrated Circuit +\par }\pard \qj\fi-1440\li1440\ri824\nowidctlpar\tx1418\tx2835\adjustright {ID\tab IDentity \endash refers to the unique number of a given ECONET station or paged ROM +\par IDC\tab Insulation Displacement Connectors \endash parallel cable connectors underneath the computer +\par IEEE488\tab A parallel interface usually associated with automatically controlled test instruments +\par }\pard \qj\ri824\nowidctlpar\tx1418\tx2835\adjustright {I/O\tab Input Output +\par IRQ\tab Interrupt ReQuest \endash control line on the 6512 processor +\par MOS/OS\tab Machine Operating System or OS +\par MPU\tab MicroProcessor Unit \endash same as CPU +\par NMI\tab Non-Maskable Interrupt \endash control line on the 6512 processor +\par PA\tab Port A \endash One of the two ports of a VIA +\par }\pard \qj\fi-1440\li1440\ri824\nowidctlpar\tx1418\tx2835\adjustright {PAL\tab i) A feature of the British television colour system where colour information phase is varied on alternate lines. Hence Phase Alternate Line +\par PAL\tab ii) Abbreviation for a type of logic integrated circuit (IC) which is programmed by fusing microscopic links in the IC. Programmable Array Logic circuits are used to reduce the number of ICs needed on a circuit board +\par }\pard \qj\ri824\nowidctlpar\tx1418\tx2835\adjustright {PB\tab Port B \endash The other port of a VIA +\par PCB\tab Printed Circuit Board +\par }\pard \qj\fi-1440\li1440\ri824\nowidctlpar\tx1418\tx2835\adjustright {\page PET\tab Test device designed for use with BBC Microcomputer Model B. Will work on the B+ but with different results, see information manual supplied to dealers +\par }\pard \qj\ri824\nowidctlpar\tx1418\tx2835\adjustright {PHI1\tab CPU clock input \endash nonoverlapping with PHI2 +\par PHI2\tab CPU clock input also called 2E +\par PL\tab Header PLug +\par PORT\tab Test device for use with BBC Microcomputer Model B+ +\par PSU\tab Power Supply Unit +\par Q1 etc\tab Transistor numbers +\par QWERTY\tab Signifies a standard typewriter key layout +\par RAM\tab Random Access read/write Memory +\par RAS\tab Row Address Strobe \endash control line for the DRAM +\par RC\tab Resistor Capacitor network +\par RGB\tab Red Green Blue \endash individual colour signals for the VDU +\par ROM\tab Read Only Memory +\par ROMSEL\tab ROM SELect latch +\par }\pard \qj\fi-1440\li1440\ri824\nowidctlpar\tx1418\tx2835\adjustright {RS423\tab An internationally defined convention for serial transmission of data +\par }\pard \qj\ri824\nowidctlpar\tx1418\tx2835\adjustright {RTS\tab Ready To Send \endash control output on RS423 port +\par S1-30\tab PCB links +\par SK\tab Socket +\par }\pard \qj\fi-1440\li1440\ri824\nowidctlpar\tx1418\tx2835\adjustright {TTL\tab Transistor Transistor Logic \endash a standard type of digital IC (74- series) +\par UHF\tab Ultra High Frequency \endash signal for input to a TV aerial socket +\par }\pard \qj\ri824\nowidctlpar\tx1418\tx2835\adjustright {ULA\tab Uncommitted Logic Array \endash semi-custom IC +\par VC\tab Variable Capacitor +\par VDU\tab Visual Display Unit +\par VIA\tab Versatile Interface Adaptor (6522) +\par VR\tab Variable Resistor +\par }\pard \qj\ri824\sa240\nowidctlpar\tx2835\adjustright {1E\tab A synchronous enable or clock for 65xx/68xx family peripheral ICs. 1E is a continuous 1MHz square wave +\par }\pard \qj\ri824\nowidctlpar\tx1418\tx2835\adjustright {1M\tab 1 MegaHertz from video processor +\par }\pard \qj\fi-1440\li1440\ri824\nowidctlpar\tx1418\tx2835\adjustright {2E\tab A synchronous enable or clock for 65xx/68xx family peripheral ICs. 2E may have two or three half cycles suppressed to synchronise it to 1E +\par }\pard \qj\ri824\nowidctlpar\tx1418\tx2835\adjustright {2M\tab 2 MegaHertz from video processor +\par 4M\tab 4 MegaHertz from video processor +\par 8M\tab 8 MegaHertz from video processor +\par }\pard\plain \s1\qj\sa240\nowidctlpar\tx2835\outlinelevel0\adjustright \b\f2 {\fs22 \page }{IC description +\par }\pard\plain \s15\qj\ri-27\sa240\keepn\nowidctlpar\tx1134\tx2835\tx3119\outlinelevel5\adjustright \f2\fs22 {IC1\tab 74LS123\tab Dual monostable (one half used, 8271 FDC only) +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 { +Required only by 8271 disc interface. This monostable defines the pulse width of data pulses from the disc drive during disc read operations. Pin 9 receives negative pulses from the disc drive, the monostable +triggers on falling edges and generates a negative pulse of about 0.9\'b5s on pin 12. +\par }\pard\plain \s15\qj\ri-27\sa240\keepn\nowidctlpar\tx1134\tx2835\tx3119\outlinelevel5\adjustright \f2\fs22 {IC2\tab 74LS393\tab Dual divide by 16 (8271 FDC only) +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {This IC receives an 8MHz clock. Along with a NAND gate (part of IC9) this chip forms a digital timer/monostable. It is set to about 6.5\'b5 +s and gives the decision point between logic 0 and logic 1 data bits from the disc drive. +\par }\pard\plain \s15\qj\ri-27\sa240\keepn\nowidctlpar\tx1134\tx2835\tx3119\outlinelevel5\adjustright \f2\fs22 {IC3\tab 4013\tab CMOS dual J-K flip-flop (8271 PDC only) +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {The two J-Ks are used to detect disc speed. When a drive is off, pin 13 is set to logic 1 by the logic 1 not +MOTOR signal fed through resistor R2. Pin 2 is held at 1 by the first J-K. Q19 of IC4 (pin 11) has no effect as D1 will always be biased off. When a drive starts, notMOTOR goes low allowing the first J-K to be clocked by index pulses. If an index pulse oc +c +urs when Q19 of IC4 is at 1 then the first J-K will stay set, which means the disc is slow. If Q19 is 0 when an index pulse occurs, the J-K will reset and allow the second J-K to be clocked. The next index pulse will set the second J-K (pin 2 goes low) in +dicating drive ready. This state is inhibited if the disc speed is slow, as the first J-K will be immediately set and so force the second J-K to reset (pin 2 high). +\par }\pard\plain \s15\qj\ri-27\sa240\keepn\nowidctlpar\tx1134\tx2835\tx3119\outlinelevel5\adjustright \f2\fs22 {IC4\tab 4521\tab CMOS 24 stage binary divider (8271 FDC only) +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {Used as a 2 to the power 18 divider. I +t counts cycles of 16/13 MHz to time a period of about 213ms (2^18*812ns). The divider is reset by each index pulse, so if Q19 goes high then the disc is slow. If the disc is very slow, such that Q19 goes low high low between index pulses, the diode Dl en +sures that the J-K (IC3) remains set. +\par }\pard\plain \s15\qj\ri-27\sa240\keepn\nowidctlpar\tx1134\tx2835\tx3119\outlinelevel5\adjustright \f2\fs22 {IC5\tab 74LS244\tab Octal buffer +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {Permanently enabled buffer for the CENTRONICS compatible printer interface data lines. +\par }\pard\plain \s15\qj\ri-27\sa240\keepn\nowidctlpar\tx1134\tx2835\tx3119\outlinelevel5\adjustright \f2\fs22 {IC6\tab 74LS244\tab Octal buffer +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {Permanently enabled buffer for the 1MHz extension bus. Buffered lines are four address lines LA0 to LA3, notPAGEFD, notPAGEFC, 1MHzE, and RnotW. +\par }\pard\plain \s15\qj\ri-27\sa240\keepn\nowidctlpar\tx1134\tx2835\tx3119\outlinelevel5\adjustright \f2\fs22 {\page IC7\tab 7438\tab Quad 2 input o/c NAND (either disc interface) +\par }\pard\plain \qj\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {1) o/p pin 6 is drive select 1. Gates motor control and drive select from controller circuitry to form the external drive select. Must be + able to drive a 150 ohm pull-up resistor hence cannot be LS TTL. +\par 2) o/p pin 8 is drive select 0 (see above). +\par 3) o/p pin 11 is used to buffer and invert the disc controller interrupt signal on to the wire-NOR notNMI interrupt line. +\par 4) o/p pin 3 gates the 1770 DRQ on to the interrupt line. Used only with 1770 hence link S8 used to select 1770 (made) or 8271 (broken) option. +\par }\pard \qj\sa240\nowidctlpar\tx2835\adjustright {If IC7 is fitted and the disc controller is not, then IC7 pin 13 or pin 2 (or R14) must be pulled low to avoid notNMI being held low permanently which would stop the ECONET hardware from working. +\par }\pard\plain \s15\qj\ri-27\sa240\keepn\nowidctlpar\tx1134\tx2835\tx3119\outlinelevel5\adjustright \f2\fs22 {IC8\tab 7416\tab Hex o/c inverter +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {Converts active high signals from disc control circuitry into the active low signals required by the disc drive. Also gives increased signal drive capability. +\par }\pard\plain \s15\qj\ri-27\sa240\keepn\nowidctlpar\tx1134\tx2835\tx3119\outlinelevel5\adjustright \f2\fs22 {IC9\tab 74LS00\tab Quad 2 input NAND (8271 FDC only) +\par }\pard\plain \qj\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {1) o/p pin 11 decodes the 6.5\'b5s time counted by IC2. +\par 2) o/p pins 6 and 8 form an R-S latch. This latch generates the data window for the 8271 disc controller. When the interval between data pulses is 8\'b5s (logic 0 data) the +n the data window latch is set (pin 8 high) when the next data pulse is received. The data pulse always resets the latch. If the data pulse interval is 4\'b5s (logic 1 data) then the latch stays reset. +\par }\pard \qj\sa240\nowidctlpar\tx2835\adjustright {3) o/p pin 3 is used as an inverter to form the positive going index pulses needed to reset the CMOS counters used for disc speed timing. +\par }\pard\plain \s15\qj\ri-27\sa240\keepn\nowidctlpar\tx1134\tx2835\tx3119\outlinelevel5\adjustright \f2\fs22 {IC10\tab 6522\tab Printer/user VIA +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {This is a versatile interface adapter (VIA) IC. Half of it (A) provides a CENTRONICS compatible printer interface buffered via IC5. Handshaking is c +arried out via CA2 (strobe output buffered in IC13) and CA1 (ACK input). The (B) half is connected directly to PL10 and is called the User Port. +\par }\pard\plain \s15\qj\ri-27\sa240\keepn\nowidctlpar\tx1134\tx2835\tx3119\outlinelevel5\adjustright \f2\fs22 {IC11\tab 74LS374\tab Octal latch +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {This IC latches the low address signals A0 to A7. These are used by 1MHz peripherals. +The main function of the latch is to buffer the lines, but it also synchronises the lines so that changes can occur only while 1E is inactive (low). The latch is clocked by 1M, see also IC32. +\par }\pard\plain \s15\qj\ri-27\sa240\keepn\nowidctlpar\tx1134\tx2835\tx3119\outlinelevel5\adjustright \f2\fs22 {IC12\tab 74LS245\tab Octal bi-directional buffer +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {Used to buffer the 8 data lines from the data bus to the 1MHz expansion bus. Data direction is controlled by the de-glitched P/notW signal. +\par }\pard\plain \s15\qj\ri-27\sa240\keepn\nowidctlpar\tx1134\tx2835\tx3119\outlinelevel5\adjustright \f2\fs22 {\page IC13\tab 74LS244\tab Octal buffer +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {Used to buffer five address lines A0-A4, R/notW, and not2M for the TUBE interface. Also buffers the strobe handshake line for the CENTRONICS compatible printer interface. +\par }\pard\plain \s15\qj\ri-27\sa240\keepn\nowidctlpar\tx1134\tx2835\tx3119\outlinelevel5\adjustright \f2\fs22 {IC14\tab 74LS245\tab Octal bidirectional buffer +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {Used to buffer 8 data lines from the data bus to the TUBE interface. Is enabled only when TUBE is addressed. +\par }\pard\plain \s15\qj\ri-27\sa240\keepn\nowidctlpar\tx1134\tx2835\tx3119\outlinelevel5\adjustright \f2\fs22 {IC15\tab 8271\tab FM floppy disc controller (8271 FDC only) +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {Driven by the ACORN disc filing system software (FM \endash + single density recording) to control 40 track or 80 track disc drives. Note the disc interface can be changed for 8 inch drive operation. +\par }\pard\plain \s15\qj\ri-27\sa240\keepn\nowidctlpar\tx1134\tx2835\tx3119\outlinelevel5\adjustright \f2\fs22 {IC16\tab l770\tab FM / MFM floppy disc controller (1770 FDC only) +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {Driven by either the ACORN 1770 disc filing system software (for FM \endash single density recording) or by the ACORN advanced disc filing system software (for MFM \endash + double density recording) to control 40 track or 80 track 5.25 inch disc drives (or any compatible alternative). The 1770 disc controller cannot be used in conjunction with 8" disc drives. +\par }\pard\plain \s15\qj\ri-27\sa240\keepn\nowidctlpar\tx1134\tx2835\tx3119\outlinelevel5\adjustright \f2\fs22 {IC17\tab 74LS174\tab Hex D-type (1770 FDC only) +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {This hex D-type latch is used for the disc control signals not generated by the 1770. Motor on/off, t +wo drive select signals, and one side select signal are held in the latch. Also the disc format mode (single/double density) and a 1770 master reset signal are held in this latch. All these signals are under direct program control. The latch is addressed +at &FE80. +\par }\pard\plain \s15\qj\ri-27\sa240\keepn\nowidctlpar\tx1134\tx2835\tx3119\outlinelevel5\adjustright \f2\fs22 {IC18\tab 74LS163\tab Presettable 4-bit counter +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {Configured as a divide by 13 to give 16MHz/13 clock for cassette and RS423 baud rate generation and disc speed detection. +\par }\pard\plain \s15\qj\ri-27\sa240\keepn\nowidctlpar\tx1134\tx2835\tx3119\outlinelevel5\adjustright \f2\fs22 {IC19\tab 74LS00\tab Quad 2 input NAND +\par }\pard\plain \qj\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {1) o/p pin 11 detects a count of 12 on IC18 and generates a synchronous load pulse so that IC18 divides by 13. +\par 2) o/p pin 8 is used as an inverter to generate notW for the system RAM. +\par 3) o/p pins 3 and 6 are part of the decoder that converts the 2-bit code for display RAM size (from the addressable latch IC30) to the 4-bit code fed to the adder IC76. +\par }\pard\plain \s15\qj\ri-27\sa240\keepn\nowidctlpar\tx1134\tx2835\tx3119\outlinelevel5\adjustright \f2\fs22 {\page IC20\tab 6522\tab System VIA +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 { +This is a versatile interface adapter (VIA) IC. The A data lines are used for communication with the keyboard, speech system, and sound. CA1 is VSYNC from the CRTC, which interrupts the CPU eve +ry 20ms. CA2 generates an interrupt when a key is pressed. PB0-PB3 drive the addressable latch IC30. PB4 and PB5 are inputs from the joystick fire buttons. PB6 and PB7 are inputs from the speech processor. CB1 is the end of conversion signal from the anal +ogue to digital converter IC84. CB2 is the light pen strobe signal from pin 9 of the 15-way D-type connector (SK6) used for analogue in. +\par }\pard\plain \s15\qj\ri-27\sa240\keepn\nowidctlpar\tx1134\tx2835\tx3119\outlinelevel5\adjustright \f2\fs22 {IC21\tab 74LS138\tab 3 to 8 line decoder +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {This IC is enabled for address values &FE** (page FE), the Sheila I/O space. It is enab +led when A8 is low and A9-A15 are high. The Sheila space is decoded into 8 blocks of 16 bytes. Each block is enabled when the corresponding decoder output is low. +\par }\pard\plain \s15\qj\ri-27\sa240\keepn\nowidctlpar\tx1134\tx2835\tx3119\outlinelevel5\adjustright \f2\fs22 {IC22\tab 74LS30\tab 8 input NAND +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {Detects address values of &FC00 and greater. It forms the first stage of the I/O space address decoder logic. +\par }\pard\plain \s15\qj\ri-27\sa240\keepn\nowidctlpar\tx1134\tx2835\tx3119\outlinelevel5\adjustright \f2\fs22 {IC23\tab 74LS32\tab Quad 2 input OR +\par }\pard\plain \qj\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {1) o/p pin 3 gates notW with the notFDC enable (address &FE80) to form the disc control latch clock. +\par 2) o/p pin 6 gates notINTOFF/notSTATID with not2E to give a glitch-free active low preset signal for the ECONET NMI control latch. +\par 3) o/p pin 8 gates the 2M clock with notVIDPROC to form CAS enable signal which can only be active (high) during CPU RAM access (phi2 high). +\par }\pard \qj\sa240\nowidctlpar\tx2835\adjustright {4) o/p pin 11 gates notDEN with the latched D6 RAM data. So "D6" received by the Teletext generator chip IC59 will be forced high during display blanking. +\par }\pard\plain \s15\qj\ri-27\sa240\keepn\nowidctlpar\tx1134\tx2835\tx3119\outlinelevel5\adjustright \f2\fs22 {IC24\tab 74LS04\tab Hex inverter +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {Used for inverting various signals around the board. +\par }\pard\plain \s15\qj\ri-27\sa240\keepn\nowidctlpar\tx1134\tx2835\tx3119\outlinelevel5\adjustright \f2\fs22 {IC25\tab 74LS109\tab Dual J-notK flip-flop +\par }\pard\plain \qj\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {1) o/p pin 6 is a flip-flop clocked at 2M and samples the 1M signal to form the internal 1E and not1E clocks. +\par }\pard \qj\sa240\nowidctlpar\tx2835\adjustright {2) o/p pin 10 is used as a state machine to process 1 MHz cycle requests. When pin 10 is high it holds phi2 high until phi2 and 1E syncronise. +\par }\pard\plain \s15\qj\ri-27\sa240\keepn\nowidctlpar\tx1134\tx2835\tx3119\outlinelevel5\adjustright \f2\fs22 {IC26\tab 74S04\tab Hex inverter +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {Three parts are used in a ring of two, plus buffer, 16 MHz oscillator. The remaining three are used where inversion is needed on time critical signals. +\par }\pard\plain \s15\qj\ri-27\sa240\keepn\nowidctlpar\tx1134\tx2835\tx3119\outlinelevel5\adjustright \f2\fs22 {\page IC27\tab 74LS00\tab Quad NAND +\par }\pard\plain \qj\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {1) o/p pin 3 is used to gate 2M with R/notW to form notR, a synchronous read enable used by the ADC and 8271 disc controller (if fitted). +\par 2) o/p pin 6 is used to gate 2M with notR/W to form notW, a synchronous write signal used by the ADC and the 8271 disc controller (if fitted). +\par 3) o/p pin 8 is used as an inverter to generate notRS, the system master reset. +\par }\pard \qj\sa240\nowidctlpar\tx2835\adjustright {4) o/p pin 11 is a spare gate. Inputs are tied to +5V. +\par }\pard\plain \s15\qj\ri-27\sa240\keepn\nowidctlpar\tx1134\tx2835\tx3119\outlinelevel5\adjustright \f2\fs22 {IC28\tab 74LS139\tab Dual 2 to 4 line decoder +\par }\pard\plain \qj\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {1) o/p pins 10 and 12 split the FDC address space into two parts. Uses A2 and notFDC so that o/p 10 is low + for address values &FE84 to &FE87 and o/p 12 is low for &FE80 to &FE83. The o/p's repeat in blocks of 4 up to address &FE9F. When S7 is East (1770 disc controller) 2M is used to enable the device o/p's so the enable signals are effectively synchronous wi +th phi2. +\par }\pard \qj\sa240\nowidctlpar\tx2835\adjustright {2) o/p pins 4,5 and 6 decode the I/O pages FRED JIM and SHEILA. The decoder uses the I/O enable from IC22 and A8 and A9 to detect the 256 byte I/O blocks. +\par }\pard\plain \s25\qj\li284\nowidctlpar\tx284\tx2835\adjustright \f2\fs22\lang2057 {o/p 4 is FRED \tab \tab &FC** +\par o/p 5 is JIM \tab \tab &FD** +\par }\pard \s25\qj\li284\sa240\nowidctlpar\tx284\tx2835\adjustright {o/p 6 is SHEILA. \tab &FE** +\par }\pard\plain \s15\qj\ri-27\sa240\keepn\nowidctlpar\tx1134\tx2835\tx3119\outlinelevel5\adjustright \f2\fs22 {IC29\tab TMS5220\tab Speech synthesizer (optional) +\par IC30\tab 74LS259\tab Octal addressable latch +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {This device expands the number of output bits available for system control functions. It is driven by the operating system through the system VIA (IC20). +\par }\pard\plain \s15\qj\ri-27\sa240\keepn\nowidctlpar\tx1134\tx2835\tx3119\outlinelevel5\adjustright \f2\fs22 {IC31\tab 74S74\tab Dual D-type flip-flop +\par }\pard\plain \qj\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {1) o/p pin 6 di +sables the addressable latch IC30 during a CPU access of the system VIA, to avoid VIA o/p glitches disturbing the latch (IC30) contents. The function does not need schottky speed. +\par }\pard \qj\sa240\nowidctlpar\tx2835\adjustright {2) o/p pins 8 and 9 generate timing for RAS, the RAM row address clock. RAS +is a delayed 4M clock, the delay being nominally 62.5ns (half period of 8M). This device is schottky to minimise device delay uncertainty. +\par }\pard\plain \s15\qj\ri-27\sa240\keepn\nowidctlpar\tx1134\tx2835\tx3119\outlinelevel5\adjustright \f2\fs22 {IC32\tab 74LS374\tab Octal D-type +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {This device is used to sychronise and de-glitch the 1MHz device control signals. By using 1M to clock the register, signal changes can only occur while 1E is low (inactive). +\par }\pard\plain \s15\qj\ri-27\sa240\keepn\nowidctlpar\tx1134\tx2835\tx3119\outlinelevel5\adjustright \f2\fs22 {\page IC33\tab 74S02\tab Quad 2 input NOR +\par }\pard\plain \qj\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {1) o/p + pins 1,4 and 10 form the CPU clock generator. Outputs 4 and 10 are connected as an R-S flip-flop, which generates a non-overlapping two phase clock. Schottky is used for minimum gate delays and to allow low value pull-up resistors to be used. The pull-up +s (R20 and R21) ensure the MOS logic 1 voltages needed by the 6512A CPU. +\par }\pard \qj\sa240\nowidctlpar\tx2835\adjustright {2) o/p pin 13 inverts the RAS timing signal to form notRAS, the RAM row address clock. The delayed RAS signal (RSL) is used to modify the high/law ratio of notRAS. NotRAS is held low f +or an extra 10nS (approx.) to meet the longest known Trsh spec of 120ns DRAMs. RSL controls the ROW/COLUMN address switching. The small delay between notRAS and RSL helps ensure the minimum RAM RAS address hold time is exceeded. +\par }\pard\plain \s15\qj\ri-27\sa240\keepn\nowidctlpar\tx1134\tx2835\tx3119\outlinelevel5\adjustright \f2\fs22 {IC34\tab 74LS08\tab Quad 2 input AND +\par }\pard\plain \qj\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {1) o/p pin 3 combines the operating system enable with the BASIC language enable, so either will select the 32Kbyte ROM IC71. logic 0 active. +\par 2) o/p pin 6 combines two "NMI" signals (notNMI and notINT) to form the complete notNMI interrupt for the CPU. +\par 3) o/p pin 8 operates with 2 EX-OR gates (IC63) to reduce the refresh address cycle time when in display mode 7. +\par }\pard \qj\sa240\nowidctlpar\tx2835\adjustright {4) o/p pin 11 combines the JIM and FRED enables. This signal, active low, indicates a 1MHz bus cycle is in progress. +\par }\pard\plain \s15\qj\ri-27\sa240\keepn\nowidctlpar\tx1134\tx2835\tx3119\outlinelevel5\adjustright \f2\fs22 {IC35\tab various\tab 64K, 128K or 256Kbit paged ROM +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 { +A 32Kbyte device in this socket appears in sideways ROM slots 2 and 3 (link S9 East). Link S9 West allows 8 or 16Kbyte EPROMs/ROMs to be fitted. IC35 can be any ROM or EPROM with a notCE access time less than 250ns. +\par }\pard\plain \s15\qj\ri-28\keepn\nowidctlpar\tx1134\tx2835\tx3119\outlinelevel5\adjustright \f2\fs22 {IC36\tab 16R4\tab Programmable array logic (PAL) IC +\par }\pard\plain \qj\li3119\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {(ACORN no 0201,880) +\par }\pard \qj\nowidctlpar\tx2835\adjustright {This device generates 4 enable signals: +\par 1) A14 and A15 are decoded to form notOS, which is low when A14 AND A15 are logic 1. +\par 2) A14 (low) AND A15 (high) are decoded to form notPG, the current sideways ROM enable. If sideways RAM is enabled (SRAM=1) then notPG is forced high while A12 OR A13 is low. +\par 3) [A12 (low) OR A13 (low)] AND A14 (low) AND A15 (high) are decoded. The address decoded is ANDed with the sideways RAM enable bit (SRAM) to form notPGRAM. NotPGRAM will +be low (active) if sideways RAM enable (SRAM) is logic 1 and the current address is between &8000 and &AFFF. +\par 4) notPGLD is formed by decoding notROMSEL and A2. NotPGLD is low (active) when notROMSEL is low AND A2 is low. +\par +\par }\pard \qj\nowidctlpar\tx2835\tx2880\adjustright {The PAL contains two addressable 1 bit latches (write only): +\par }\pard \qj\nowidctlpar\tx2835\adjustright {1) VDUSEL is addressed at &FE34, and latches the value of D7. VDUSEL is the hardware SHADOW mode switch. Logic 0 is normal mode, which emulates the standard model B microcomputer VDU operation. +\par }\pard \qj\sa240\nowidctlpar\tx2835\adjustright {2) SRAM is addressed at &FE30. SRAM is an extension to the ROM select latch and holds the value of D7. This bit is the sideways RAM select flag. The signal is labeled "Qh" in the PAL spec (0201,880). +\par }\pard \qj\nowidctlpar\tx2835\adjustright {\page The PAL monitors the state of VDUSEL to determine if a shadow display mode is active. When + VDUSEL is high (shadow active), the PAL checks the address of each CPU opcode fetch. If the opcode address is in the VDU driver code space then a temporary 1-bit flag is set (in the PAL). The flag remains set until an opcode outside the VDU driver code s +p +ace is read. While the flag is set, all CPU access to memory between &3000 and &7FFF is redirected to the shadow RAM. The redirection is achieved by manipulating the "A15" RAM address line. The RAM A15 address is generated by the PAL, and is the signal CP +U +SEL. Normally CPUSEL is the same as the CPU A15 address signal. When the flag is set, the PAL tests each CPU address and forces CPUSEL high if the address is in the range &3000 to &7FFF. So in shadow mode the CPU will access the shadow screen RAM for VDU +o +perations and normal RAM for all other operations. VDU driver code is identified by its memory address. All code between address &C000 and &DFFF is treated as a VDU driver. Also, code in the paged RAM between &A000 and &AFFF is treated as a VDU driver (bu +t not in paged ROM). +\par }\pard \qj\sa240\nowidctlpar\tx2835\adjustright { +\par From the above it is apparent that any program code in the VDU code spaces must not address RAM between &3000 and &7FFF unless it intends to write to the shadow RAM (screen). +\par }\pard\plain \s15\qj\ri-27\sa240\keepn\nowidctlpar\tx1134\tx2835\tx3119\outlinelevel5\adjustright \f2\fs22 {IC37\tab TMS6100\tab Speech PHROM +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {A serial ROM which contains the speech vocabulary data, used by IC29. +\par }\pard\plain \s15\qj\ri-27\sa240\keepn\nowidctlpar\tx1134\tx2835\tx3119\outlinelevel5\adjustright \f2\fs22 {IC38\tab SN76489\tab Sound generator +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {This IC contains three sound channels and one noise channel. The sound pitch, attack, sustain, decay, and release are independently programmable from BASIC o +r machine code. Control is exercised through the system VIA IC20. +\par }\pard\plain \s15\qj\ri-27\sa240\keepn\nowidctlpar\tx1134\tx2835\tx3119\outlinelevel5\adjustright \f2\fs22 {IC39\tab 74LS139\tab Dual 2 to 4 line decoder +\par }\pard\plain \qj\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {1) o/p pins 4,5,6 and 7. This decoder is enabled by IC21, for I/O address values between &FE00 and &FE1F. The IC uses address lines A3 and A4 to complet +e the I/O address decoding for the CRTC (&FE00/1), ACIA (&FE08/9), SERPROC (&FE10) and the ECONET control signal notINTOFF/notSTATID (&FE18). +\par }\pard \qj\sa240\nowidctlpar\tx2835\adjustright {2) o/p pins 9,10,11 and 12 decode address values &FE20 to &FE3F into 2 write only blocks and 2 read only blocks (o +nly one is used). At &FE20 (WR) is the VIDPROC. &FE20 (RD) is INTON, an ECONET control. &FE30 to &FE3F (WR) is "ROMSEL" space, see PAL IC36. +\par }\pard\plain \s15\qj\ri-27\sa240\keepn\nowidctlpar\tx1134\tx2835\tx3119\outlinelevel5\adjustright \f2\fs22 {IC40\tab 74LS20\tab Dual 4 input NAND +\par }\pard\plain \qj\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {1) o/p pin 6 controls the paged ROM notOE signal. All paged ROMs are disabled during +CPU write cycles by this gate (R/notW i/p). ROMs are also disabled for the I/O address space (FRED, JIM and SHEILA). The not2M clock ensures ROMs can only drive the data bus during phi2 which avoids bus drive conflicts during address changes. +\par }\pard \qj\sa240\nowidctlpar\tx2835\adjustright {2) o/p pin 8 "ORs" three active low signals to form an active high RAM data request signal. A15 low OR notPGRAM low OR notVIDPROC low will enable the RAM data buffer IC49, see IC48 o/p 12. +\par }\pard\plain \s15\qj\ri-27\sa240\keepn\nowidctlpar\tx1134\tx2835\tx3119\outlinelevel5\adjustright \f2\fs22 {\page IC41\tab 74LS30\tab 8 input NAND +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {ORs five I/O enable signals to form the active high 1M +Hz cycle signal SYNC 1M. This signal is used by IC25 to trigger 1E and phi2 clock syncronisation. The five input signals correspond to the various I/O devices which operate with 1MHz (1E) interface timing. +\par }\pard\plain \s15\qj\ri-27\sa240\keepn\nowidctlpar\tx1134\tx2835\tx3119\outlinelevel5\adjustright \f2\fs22 {IC42\tab 6512A\tab CPU +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {The 6512A is a member of the NMOS 6 +500 processor family. This IC is functionally similar to a 6502A, the only significant difference being the clock drive. A 6512A uses MOS level clocks (phi1 and phi2) and so gives more precise system timing than is possible with the TTL "phi in" clock of +the 6502A. +\par THE TWO PROCESSOR TYPES ARE NOT INTERCHANGEABLE. +\par This microcomputer can use 2,3 or 4 MHz CPU parts (6512A/B/C) +\par }\pard\plain \s15\qj\ri-27\sa240\keepn\nowidctlpar\tx1134\tx2835\tx3119\outlinelevel5\adjustright \f2\fs22 {IC43\tab NE555\tab Monostable IC +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {The 555 is used as a monostable for generation of the microprocessor system reset pulse. It is triggered at po +wer-on or by the keyboard BREAK key. A logic 1 active output pulse is generated and part of IC27 inverts RS to form notRS, the CPU reset. +\par }\pard\plain \s15\qj\ri-27\sa240\keepn\nowidctlpar\tx1134\tx2835\tx3119\outlinelevel5\adjustright \f2\fs22 {IC44\tab various\tab 64K,128K or 256Kbit paged ROM +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {A 32Kbyte device in this socket appears in sideways ROM slots 4 and 5 (link + S11 East). Link S11 West allows 8 or 16Kbyte EPROMs/ROMs to be fitted. This device can be any ROM or EPROM with a notCE access time less than 250ns. +\par }\pard\plain \s15\qj\ri-27\sa240\keepn\nowidctlpar\tx1134\tx2835\tx3119\outlinelevel5\adjustright \f2\fs22 {IC45\tab 74LS163\tab Synchronous divide by 16 counter +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {Used as a 4-bit latch which holds the paged ROM ID. The IC i +s clocked by not2E. When the latch is addressed, at &FE30, its ID enable is taken low (active) and the write data on the CPU data lines D0 to D3 is latched. The load event is effectively when phi2 falls. The QA output (latched D0) is used as a pseudo addr +ess line for 32Kbyte ROMs/EPROMs and so splits these devices into two 16Kbyte pages. +\par }\pard\plain \s15\qj\ri-27\sa240\keepn\nowidctlpar\tx1134\tx2835\tx3119\outlinelevel5\adjustright \f2\fs22 {IC46\tab 74LS138\tab 3 to 8 line decoder +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {This decoder is enabled by the notPG signal from the PAL (IC36). When enabled the decoder selects one of the ROM sockets, according to the +code held in IC45. Each enable output is active for 2 paged ROM IDs as the decoder uses the latched values of Dl to D3. S13 is used to select the page number for the "language" half of IC71 (normally BASIC II). S13 North selects page 0/1. South selects pa +ge 14/15. +\par }\pard\plain \s15\qj\ri-27\sa240\keepn\nowidctlpar\tx1134\tx2835\tx3119\outlinelevel5\adjustright \f2\fs22 {\page IC47\tab LM324\tab Quad operational amplifier +\par }\pard\plain \qj\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {The four parts of this IC are used to filter and amplify the speech and sound signals before they reach the volume control. +\par 1) o/p pin 1 is the final filter stage, nominal bandwidth of 7kHz. +\par 2) o/p pin 7 is the speech audio filter stage, approximately 7kHz bandwidth. +\par 3) o/p pin 8 is the summing stage, mixes sound, speech, speech envelope and user audio inputs into one channel. +\par }\pard \qj\sa240\nowidctlpar\tx2835\adjustright { +4) o/p pin 14 extracts the sound channel envelope. The op amp inverts the sound signal and charges C15 through D4. R34 discharges C15 "slowly", so C15 holds the sound envelope voltage (inverted). When the envelope is added to the sound audio, the resultin +g signal is \ldblquote AC\rdblquote , that is symmetric about 0V. +\par }\pard\plain \s15\qj\ri-27\sa240\keepn\nowidctlpar\tx1134\tx2835\tx3119\outlinelevel5\adjustright \f2\fs22 {IC48\tab 74LS10\tab Triple 3 input NAND +\par }\pard\plain \qj\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {1) o/p pins 6 and 8 are part of the hardware scroll wrap around logic. With parts of IC19 they decode the screen size code, C0 and C1 from IC30, to drive the offset adder IC76. +\par }\pard \qj\sa240\nowidctlpar\tx2835\adjustright {2) + o/p pin 12 enables the RAM data bus buffer IC49 and the RAM write signal. The logic 1 request input from IC40 pin 8 is gated with not2M to form notENM, the 0 active RAM enable signal. Not2M is used to ensure the enable is only active during the CPU phase +, + i.e. while phi2 is high. This avoids bus conflicts during phi1. Also it forces the RAM to be "read only" during VDU cycles. Note the buffer is active for RAM or VIDPROC access. During a VIDPROC write the RAM is disabled by holding notCAS at logic 1 (see +IC23 and IC52). +\par }\pard\plain \s15\qj\ri-27\sa240\keepn\nowidctlpar\tx1134\tx2835\tx3119\outlinelevel5\adjustright \f2\fs22 {IC49\tab 74LS245\tab Octal buffer +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 { +The RAM and VIDPROC data bus buffer. This IC isolates the RAM data bus from the CPU data bus to allow VDU read cycles to occur without interference from the CPU data bus, particularly during 1MHz device cycles. Anot +her important function of the buffer is to reduce the CPU data bus loading by isolating the RAM and VIDPROC etc. +\par }\pard\plain \s15\qj\ri-27\sa240\keepn\nowidctlpar\tx1134\tx2835\tx3119\outlinelevel5\adjustright \f2\fs22 {IC50 and IC51 74LS257\tab Quad two to one data selector +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {These two ICs select the RAS and CAS address signals from the CPU address lines. The CPU A1 +5 is not used. The "A15" input is the CPUSEL signal from the PAL IC36. The CPU address is only valid during phi2 high because IC50 and IC51 are disable (held tristate) while phi2 is low. phi2 low is the VDU RAM access period. 2M is used as an enable to av +oid loading the phi clocks. +\par }\pard\plain \s15\qj\ri-27\sa240\keepn\nowidctlpar\tx1134\tx2835\tx3119\outlinelevel5\adjustright \f2\fs22 {IC52\tab 74S00\tab Quad 2 input NAND +\par }\pard\plain \qj\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 { +1) o/p pins 3 and 6 connected as an R-S flip-flop. The set and reset signals are the inverted and delayed 4M and 8M clocks respectively. The output signal on pin 3 is the precursor of the 6MHz clock used by the TELETEXT display circuit. See IC63 o/p 3. + +\par 2) o/p pin 8 is used to drive the RAM notCAS clock. NotCAS is timed from the system 4M clock. notCAS is held high, if the CPU cycle is a VIDPROC write, by a logic low from IC23 pin 8. +\par }\pard \qj\sa240\nowidctlpar\tx2835\adjustright {3) o/p pin 11 is used to modify the duty cycle of the 16MHz clock to suit the needs of the Ferranti ULA (IC53). Note the passives R36,R37,R38, C14,D5,D6,D7 may also be needed for the Ferranti IC. +\par }\pard\plain \s15\qj\ri-27\sa240\keepn\nowidctlpar\tx1134\tx2835\tx3119\outlinelevel5\adjustright \f2\fs22 {\page IC53\tab ULA\tab Video processor IC +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {This component contains a 4-bit divider which gene +rates the 8/4/2 and 1MHz system clocks. It also selects the RGB signals, internal for modes 0 to 6 and external, from IC 59, for mode 7. The RGB can be inverted if link S14 is made South. The main function of the IC is parallel to serial conversion of the + display data read from RAM and the logical translation of the pixel code to the 3-bit RGB "code" of each display pixel. The translation process varies with screen resolution (mode). A pixel may be represented in RAM by 1,2 or 4 bits of data. +\par }\pard\plain \s15\qj\ri-27\sa240\keepn\nowidctlpar\tx1134\tx2835\tx3119\outlinelevel5\adjustright \f2\fs22 {IC54\tab 74LS273\tab Octal D-type +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 { +This IC latches the RAM data at the end of alternate VDU phases. It is needed to hold the data for the Teletext IC which has long data setup and hold times. The latch is clocked 500ns before the SAA5050 IC59, giving equal setup and hold times of 500ns. + +\par }\pard\plain \s15\qj\ri-27\sa240\keepn\nowidctlpar\tx1134\tx2835\tx3119\outlinelevel5\adjustright \f2\fs22 {IC55,56,60,61,64,65,66,67 4164 64Kxl bit 120ns access DRAMs +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 { +These eight ICs are the system memory. The RAM appears as a 32Kbyte block from &0000 to &7FFF. A further 20Kbytes are used for a "SHADOW" screen memory. The remaining 12Kbytes is PAGED in + under program control as a sideways RAM. Note IC96, a DRAM ' SIL pack, may be supplied instead of these ICs. +\par }\pard\plain \s15\qj\ri-27\sa240\keepn\nowidctlpar\tx1134\tx2835\tx3119\outlinelevel5\adjustright \f2\fs22 {IC57\tab various\tab 64K,128K or 256Kbit paged ROM +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {A 32Kbyte device in this socket appears in sideways ROM slots 6 and 7 (link S12 East). Link S12 West al +lows 8 or 16Kbyte EPROMs/ROMs to be fitted. This device can be any ROM or EPROM with a notCE access time less than 250ns. +\par }\pard\plain \s15\qj\ri-27\sa240\keepn\nowidctlpar\tx1134\tx2835\tx3119\outlinelevel5\adjustright \f2\fs22 {IC58\tab 74LS02\tab Quad 2 input NOR +\par }\pard\plain \qj\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {l) o/p pin 1 mixes the video display sync pulses HS and VS to form notCSYNC. The HS pulse is nominally 4\'b5s long. VS is nominally 132\'b5s (2 TV rasters) long. +\par 2) o/p pin 4 gates the buffered CPU R/notW with notENM to form the DRAM W signal, which is buffered and inverted by IC19 to form notDW. +\par 3) o/p pin 10 gates notDEN and RA3 (from the CRTC) to form the DIS EN + signal. DIS EN high enables the VIDPROC generated RGB signals. It does not affect mode 7. This signal is used to blank the display: notDEN is high for periods outside the display window and so blanks the graphic mode borders. RA3 is only active for the t +e +xt only "graphic" screen modes (modes 3,6,131 and 134), when the signal causes a 2 raster space between each text row. In modes 3,6,131 and 134 the CRTC RA lines count from 0 to 9. The other modes have only 8 raster lines per character row so the RA lines + count from 0 to 7, therefore RA3 only goes high for modes 3,6,131 and 134. +\par }\pard \qj\sa240\nowidctlpar\tx2835\adjustright {4) o/p pin 13 is part of the colour burst monostable. The o/p signal enables the colour subcarrier during the colour burst interval. R76 and C32 determine the pulse duration which i +s set at manufacture to be in the range 4 to 6\'b5s. D15 is used to discharge C32 quickly during the HS pulse period. The monostable is "triggered" at the end of the HS pulse. +\par }\pard\plain \s15\qj\ri-27\sa240\keepn\nowidctlpar\tx1134\tx2835\tx3119\outlinelevel5\adjustright \f2\fs22 {\page IC59\tab SAA5050\tab The Teletext display generator +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {The SAA5050 contains the character loo +k up ROM, the raster counter and general control logic needed to generate the pixel information for mode 7. The IC receives character data codes from IC54, at a rate of 1MHz. VS is used to reset the IC at the start of each TV field and so maintain display + synchronisation, particularly with the internal raster counter. Character rounding is permanently on. The notRA0 line, from the CRTC via IC24, gives the SAA5050 information on the current TV display field, odd or even, to allow character rounding. +\par }\pard\plain \s15\qj\ri-27\sa240\keepn\nowidctlpar\tx1134\tx2835\tx3119\outlinelevel5\adjustright \f2\fs22 {IC62\tab various\tab 64K,128K or 256Kbit paged ROM +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {A 32Kbyte device in this socket appears in sideways ROM slots 8 and 9 (link S15 Eas +t). Link S15 West allows 8 or 16Kbyte EPROMs/ROMs to be fitted. This device can be any ROM or EPROM with a notCE access time less than 250ns. +\par }\pard\plain \s15\qj\ri-27\sa240\keepn\nowidctlpar\tx1134\tx2835\tx3119\outlinelevel5\adjustright \f2\fs22 {IC63\tab 74LS86\tab Quad 2 input EX OR +\par }\pard\plain \qj\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {1) o/p pin 3 is part of the 6MHz clock circuit. +\par 2) o/p pins 6 and 8 are used to modify the CRTC address during the unused read cycle of mode 7 VDU cycles. Along with IC34 o/p pin 8 these gates form a circuit which reduces the time taken to cycle through the refresh address sequence when in mode 7. + +\par }\pard \qj\sa240\nowidctlpar\tx2835\adjustright {3) o/p pin 11 is a spare gate, inputs tied to +5V. +\par }\pard\plain \s15\qj\ri-27\sa240\keepn\nowidctlpar\tx1134\tx2835\tx3119\outlinelevel5\adjustright \f2\fs22 {IC68\tab various\tab 64K,128K or 256Kbit paged ROM +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 { +A 32Kbyte device in this socket appears in sideways ROM slots 10 and 11 (link S18 East). Link S18 West allows 8 or 16Kbyte EPROMs/ROMs to be fitted. This device can be any ROM or EPROM with a notCE access time less than 250ns. +\par }\pard\plain \s15\qj\ri-27\sa240\keepn\nowidctlpar\tx1134\tx2835\tx3119\outlinelevel5\adjustright \f2\fs22 {IC69\tab 74LS74\tab Dual D-type flip-flop +\par }\pard\plain \qj\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 { +1) o/p pin 6; this flip-flop holds the ECONET NMI enable signal. The flip-flop is used as an R-S latch. When address &FE18 is read/written, the latch is set (o/p 6 low), which disables ECONET NMIs. + IC23 o/p 6 gates not2E with the decoded address to give a glitch-free preset pulse. To enable the NMIs, address &FE20 is read. The decoded address signal appears as logic 0 on the D i/p and is clocked through by the rising edge of not2E (e.g. when phi2 f +a +lls). This clears the D-type (pin 6 high) and by the feedback action of Q connected to notCL locks the D-type in the reset state (i.e. notINTON high will not cause the D-type to become set). Note as notPR (pin 4) acts directly on the Q o/p it can defeat t +he notCL i/p and set the device. +\par }\pard \qj\sa240\nowidctlpar\tx2835\adjustright { +2) o/p pin 9 generates the alternate line signal which is used by the PAL encoding logic to encode the chroma signal. The D-type is clocked by HS and so changes state at the start of each TV raster line (divides the line fre +quency by two). Link S28 (made with a PCB track) allows the alternating line signal to be disconnected, for NTSC operation. Note: for NTSC R92 should be removed and an appropriate colour subcarrier crystal fitted. X2 should be four times the colour subcar +rier frequency. The RF modulator must also be chosen to suit the destination country. +\par }\pard\plain \s15\qj\ri-27\sa240\keepn\nowidctlpar\tx1134\tx2835\tx3119\outlinelevel5\adjustright \f2\fs22 {\page IC70\tab 74LS132\tab Quad 2 input Schmidt trigger NAND (ECONET only) +\par }\pard\plain \qj\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {Note: when collision detect is not used (IC93 not fitted) IC70 can be the cheaper 74LS00. +\par 1) o/p pin 3 inverts notRTS. If the collision detect circuit is fitted, this gate buffers IC93 to give a true "no collision" signal. Its main purpose is to give clean TTL level signals with normal TTL transition times. +\par 2) o/p pin 6 forms the notCTS signal used by IC81 to check for network collisions. Input 5 ensures the signal is always false if the network clock is not present. +\par 3) o/p pin 8 gates the network NMI enable with the true "INT" signal to form notINT. NotINT is the ECONET notNMI signal which is passed to the CPU via IC34. R56 is only needed on machines built without an ECONET interface. +\par }\pard \qj\sa240\nowidctlpar\tx2835\adjustright {4) o/p pin 11 inverts notIRQ from IC81 to form IRQ. This signal is treated as an NMI by the system (when enabled by IC69). NotINT is an open drain o/p so R59 is needed as a logic high pull-up. +\par }\pard\plain \s15\qj\ri-27\sa240\keepn\nowidctlpar\tx1134\tx2835\tx3119\outlinelevel5\adjustright \f2\fs22 {IC71\tab \tab OS/BASIC +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 { +A 32Kbyte ROM. The top half addressed from &C000 to &FFFF (except for 0.75Kbyte I/O) contains the machine operating system program. The bottom ha1f is a paged ROM containing BBC BASIC II. Link S13 selects the BASIC ROM slot number +: South selects slots 14/15 (standard configuration, high priority), North selects slots 0/1 (low priority). Link S19 is permanently made East for CPU address A14 to pin 27 of ROM IC. +\par }\pard\plain \s15\qj\ri-27\sa240\keepn\nowidctlpar\tx1134\tx2835\tx3119\outlinelevel5\adjustright \f2\fs22 {IC72,73,74,75 74LS253\tab Dual 4 to 1 data selector +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {These four ICs select th +e DRAM address signals according to the current display mode and RAS/CAS state. Not2M enables the four ICs during the VDU RAM read phase. RSL drives pin 14 to select the RAS or CAS address signals, RSL low selects the raw address (notRAS clock). MA13 from + the CRTC IC78 selects the mode 7 address group when high. MA13 is low during all the "graphics" screen modes. The VDUSEL signal from IC36 is low for normal screen modes and high for all shadow screen modes. +\par }\pard\plain \s15\qj\ri-27\sa240\keepn\nowidctlpar\tx1134\tx2835\tx3119\outlinelevel5\adjustright \f2\fs22 {IC76\tab 74LS283\tab 4-bit adder +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {The adder is used to mod +ify the natural display address from the CRTC IC78. Take mode 0 as an example. Mode 0 uses 20Kbytes of RAM from &3000 to &7FFF. If the CRTC display is scrolled (in hardware) then the address from the CRTC will be, say, &4000 to &8FFF (assumes a scroll ste +p + of &1000). The display memory must still be &3000 to &7FFF. To keep the CRTC address, as seen by the RAM multiplexer, correct, an offset is conditionally added to the actual CRTC address. The offset is 12K. As the address logic does not generate an addre +s +s above &8000 there is no use for address line A15 (MA11). Thus when the CRTC scrolls above &8000 it appears to address &0000 upwards. By adding "12K" the RAM address becomes &3000 upwards. So although the CRTC outputs an address outside the allowed RAM a +ddress, the adder causes the true address to remain in the allowed range of &3000 to &7FFF. This principle is used for all graphic screen modes (i.e. all but mode 7). +\par \page There are four different graphic screen sizes, 8/10/16/20Kbytes. The adder therefore need +s to add an offset of 24K/22K/16K/12K respectively. The operating system gives a 2-bit code labeled C0,C1 which is decoded to give the adder offset for the current screen mode. +\par }\trowd \trgaph108\trleft-108 \clvertalt\cltxlrtb \cellx567\clvertalt\cltxlrtb \cellx1701\clvertalt\cltxlrtb \cellx2835\clvertalt\cltxlrtb \cellx4962\clvertalt\cltxlrtb \cellx5529\clvertalt\cltxlrtb \cellx6096\clvertalt\cltxlrtb \cellx6663 +\clvertalt\cltxlrtb \cellx7371\pard \qj\nowidctlpar\intbl\tx2835\adjustright {C1\cell C0\cell Offset\cell adder input\cell B4\cell B3\cell B2\cell B1\cell }\pard \widctlpar\intbl\adjustright {\row }\trowd \trgaph108\trleft-108 \clvertalt\cltxlrtb +\cellx567\clvertalt\cltxlrtb \cellx1701\clvertalt\cltxlrtb \cellx2835\clvertalt\cltxlrtb \cellx4962\clvertalt\cltxlrtb \cellx5529\clvertalt\cltxlrtb \cellx6096\clvertalt\cltxlrtb \cellx6663\clvertalt\cltxlrtb \cellx7371\pard \qj\nowidctlpar\intbl +\tx2835\adjustright {0\cell 0\cell 16K\cell \cell 0\cell 1\cell 1\cell 1\cell }\pard \widctlpar\intbl\adjustright {\row }\pard \qj\nowidctlpar\intbl\tx2835\adjustright {0\cell 1\cell 8K\cell \cell 1\cell 0\cell 1\cell 1\cell }\pard +\widctlpar\intbl\adjustright {\row }\pard \qj\nowidctlpar\intbl\tx2835\adjustright {1\cell 0\cell 20K\cell \cell }\pard\plain \s20\qj\nowidctlpar\intbl\tx2835\adjustright \f2\fs22\lang2057 {0\cell }\pard\plain \qj\nowidctlpar\intbl\tx2835\adjustright +\f2\fs22\lang2057 {1\cell 0\cell 1\cell }\pard \widctlpar\intbl\adjustright {\row }\trowd \trgaph108\trrh303\trleft-108 \clvertalt\cltxlrtb \cellx567\clvertalt\cltxlrtb \cellx1701\clvertalt\cltxlrtb \cellx2835\clvertalt\cltxlrtb \cellx4962 +\clvertalt\cltxlrtb \cellx5529\clvertalt\cltxlrtb \cellx6096\clvertalt\cltxlrtb \cellx6663\clvertalt\cltxlrtb \cellx7371\pard \qj\nowidctlpar\intbl\tx2835\adjustright {1\cell 1\cell 10K\cell }\pard\plain \s20\qj\nowidctlpar\intbl\tx2835\adjustright +\f2\fs22\lang2057 {\cell }\pard\plain \qj\nowidctlpar\intbl\tx2835\adjustright \f2\fs22\lang2057 {1\cell 0\cell 1\cell 0\cell }\pard \widctlpar\intbl\adjustright {\row }\pard\plain \s20\qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 { +\par }\pard\plain \s15\qj\ri-27\sa240\keepn\nowidctlpar\tx1134\tx2835\tx3119\outlinelevel5\adjustright \f2\fs22 {IC77\tab LM386\tab Audio power amplifier +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {This IC is a low-cost amplifier with a fixed voltage gain of about 26db. C24 and R58 are needed to give load independent output stability (freedom from parasitic oscillation). +\par }\pard\plain \s15\qj\ri-27\sa240\keepn\nowidctlpar\tx1134\tx2835\tx3119\outlinelevel5\adjustright \f2\fs22 {IC78\tab 6845\tab CRTC controller +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 { +The CRTC is responsible for all VDU address generation. It is a programmable device which, once set up, independently generates the RAM address sequence for a wide range of display formats. The IC can "scroll" the display by responding to a + change in the value of the display start address. A programmable cursor and the horizontal and vertical sync pulses are also generated by this IC. Included in the IC is an address latch which is used with the "light pen" input to save the character addre +ss at the time of a trigger event on pin 3 of the IC. The device is accessed at 1MHz by the CPU at &FE00/1. A character clock of 1 or 2MHz is supplied by the VIDPROC, depending on the VDU mode. +\par }\pard\plain \s15\qj\ri-27\sa240\keepn\nowidctlpar\tx1134\tx2835\tx3119\outlinelevel5\adjustright \f2\fs22 {IC79\tab 74S74\tab Dual schottky D-type flip-flop +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {The two parts of this + IC are used in a ring counter which is clocked at four times the colour subcarrier frequency (17.734475MHz). Each D-type generates an output at the colour subcarrier frequency (4.43361875MHz). The two signals are in phase quadrature (90 degrees apart) an +d form the master signals for the PAL chroma encoding logic. The signal on pin 8 is set to 4.4336MHz +/-100Hz by adjustment of VC1. +\par }\pard\plain \s15\qj\ri-27\sa240\keepn\nowidctlpar\tx1134\tx2835\tx3119\outlinelevel5\adjustright \f2\fs22 {IC80\tab 74LS244\tab Octal 3-state buffer +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {The 8 buffers in this IC are used to drive the CPU data b +us with the ECONET station ID. The buffers are enabled when the CPU reads address &FE18. A write to &FE18 will result in a data bus drive conflict and should not be attempted. Link S23 sets the station ID. Each link has a binary value with the largest, 12 +8 (decimal), at the North end of the row. A broken link (shunt removed) adds the link value to the station ID e.g. all links fitted gives 0. +\par }\pard\plain \s15\qj\ri-27\sa240\keepn\nowidctlpar\tx1134\tx2835\tx3119\outlinelevel5\adjustright \f2\fs22 {\page IC81\tab 68B54\tab Serial data link controller (ECONET only) +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {This IC is an ADLC (advanced data link controller). It is resp +onsible for transmitting and receiving serial data to and from the ECONET. Each byte of an ECONET transfer is under interrupt control, and is managed by a network filing system. The notRTS signal is controlled by software. It enables the ECONET line drive +r + IC91. NotDCD is driven by a clock detection circuit to allow a program to detect the network clock. NotCTS is tested to check for network data packet collisions, see comments on collision detection under IC93. NotIRQ is used as an NMI interrupt, which is + enabled/disabled under program control (see IC69 and IC70). A 4k7 pull-up resistor R59 is fitted when IC81 is present, as notIRQ is an open drain output. +\par }\pard\plain \s15\qj\ri-27\sa240\keepn\nowidctlpar\tx1134\tx2835\tx3119\outlinelevel5\adjustright \f2\fs22 {IC82\tab 6850\tab ACIA (UART) +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {A UART is a serial asynchronous interface circuit which can both transmit and re +ceive data. The 6850 is used for parallel to serial data conversion for either the cassette interface or the RS423 interface. Three handshake signals are available, notDCD, notRTS, and notCTS. These can be tested by the controlling program to determine in +terface status. Two clock inputs allow the transmit and receive bit rates to be set independently. The two clocks are generated in the SERPROC IC85. +\par }\pard\plain \s15\qj\ri-27\sa240\keepn\nowidctlpar\tx1134\tx2835\tx3119\outlinelevel5\adjustright \f2\fs22 {IC83\tab 74LS86\tab Quad two input EXOR +\par }\pard\plain \qj\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {1) o/p pin 3 is part of the TV colour (PAL) encoder circuit. One of four EXO +Rs is used to select the phase of the colour subcarrier reference needed to synthesize the colour subcarrier for a particular colour. +\par 2) o/p pin 6 see above (o/p pin 3). +\par 3) o/p pin 8 is used to select the polarity of the CSYNC signal on the RGB connector SK3. With link S27 set North, positive syncs are generated. S27 South (the normal setting) gives negative syncs. +\par }\pard \qj\sa240\nowidctlpar\tx2835\adjustright {4) o/p pin 11; this gate is driven by the alternate line divider IC69 and shifts one of the master colour subcarrier references by 180 degrees t +o give the phase alternating line (PAL) subcarrier. PAL can be disabled by making S28 South. +\par }\pard\plain \s15\qj\ri-27\sa240\keepn\nowidctlpar\tx1134\tx2835\tx3119\outlinelevel5\adjustright \f2\fs22 {IC84\tab upD7002\tab 4-channel analogue to digital converter +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {Analogue signals input via SK6 are converted (about 10ms per channel) to a 12-bit digital value. The ADC infor +ms the processor of a completed conversion by interrupting it (IRQ). Interrupts are generated by the system VIA IC20 when it receives an active notEOC signal. Three diodes (D9 D10 D11) in series are used for the voltage reference which is typically 1.8 vo +lts with a ~6mV per degree C temperature coefficient. Note that the accuracy of the ADC part is equivalent to a resolution of about 8 bits. +\par }\pard\plain \s15\qj\ri-27\sa240\keepn\nowidctlpar\tx1134\tx2835\tx3119\outlinelevel5\adjustright \f2\fs22 {\page IC85\tab ULA\tab Serial processor IC +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {The SERPROC handles the RS423 and cassette interface circuits. Built into the IC are pr +ogrammable clock generators which set the serial bit rate. Signals from the selected interface (RS423 or cassette) are routed to/from the 6850 IC82 by this IC. The replay cassette signals are demodulated in IC85 and a bit clock signal is recovered. A prea +m +ble tone is timed to initialise data reception. When fitted, R66 and C30 are used to time the preamble tone. Motor control of a cassette recorder is managed by the SERPROC. A control bit in the IC controls the relay RL1. The control signal on pin 11 is bu +ffered by Q7 which switches the relay coil (50 ohm). +\par }\pard\plain \s15\qj\ri-27\sa240\keepn\nowidctlpar\tx1134\tx2835\tx3119\outlinelevel5\adjustright \f2\fs22 {IC86\tab 74LS86\tab Quad two input EXOR +\par }\pard\plain \qj\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {1) o/p pin 3 generates a colour subcarrier reference component according to the current display colour. +\par 2) o/p pin 6 is one of three gates which generate control signals to gate the subcarrier component signals into the resistor matrix, by enabling or disabling NAND gates in IC90. +\par 3) o/p pin 8 see o/p pin 6 +\par }\pard \qj\sa240\nowidctlpar\tx2835\adjustright {4) o/p pin 11 see o/p pin 6 +\par }\pard\plain \s15\qj\ri-27\sa240\keepn\nowidctlpar\tx1134\tx2835\tx3119\outlinelevel5\adjustright \f2\fs22 {IC87\tab 74LS00\tab Quad two input NAND +\par }\pard\plain \qj\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {1) o/p pin 3 buffers the colour reference oscillator to ensure TTL levels. +\par 2) o/p pin 6 is used as an inverter. It drives the colour burst timing components R76 and C32 with notHS, see IC58 o/p pin 13. +\par 3) o/p pin 8 is one of two gates which drive the colour subcarrier resistor matrix with the colour burst subcarrier components. Input pin 10 receives an enable pulse from the colour burst monostable. +\par }\pard \qj\sa240\nowidctlpar\tx2835\adjustright {4) o/p pin 11 is the second gate of the colour burst generator. +\par }\pard\plain \s15\qj\ri-27\sa240\keepn\nowidctlpar\tx1134\tx2835\tx3119\outlinelevel5\adjustright \f2\fs22 {IC88\tab 74LS123\tab Dual monostable (ECONET only) +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {1) o/p pin 5 determines the maximum allowed transmission perio +d for an ECONET data packet. The monostable's duration is set to about 4.5s and is triggered by the inverted ECONET controller notRTS signal (which previously directly enabled the line driver). While triggered the monostable enables the line driver IC91. +A +t the end of a transmission the monostable is cleared. Normally the monostable output (pin 4) appears logically to follow the RTS signal. The real purpose of this circuit is to stop a micro from permanently driving the ECONET line as a result of, say, a u +ser program crash. +\par 2) o/p pins 4,13; this monostable is triggered by the received clock from an ECONET line. While the clock is present the monostable remains triggered, o/p pin 4 low. If the clock is not present or is very slow, then o/p pin 4 will oscilla +te or stay set. The state of the monostable can be checked directly, by the ECONET filing system testing the 68B54 notDCD signal. +\par }\pard\plain \s15\qj\ri-27\sa240\keepn\nowidctlpar\tx1134\tx2835\tx3119\outlinelevel5\adjustright \f2\fs22 {\page IC89\tab LM324\tab Quad operational amplifier +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {1) o/p pins 1,8,14 give two stages of filtering and + one limiting amplifier stage for the received cassette audio signal. When the audio is present, a 1.2 volt (approx.) square wave will be presented to the SERPROC. +\par 2) o/p pin 7 buffers the audio output to the cassette recorder. +\par }\pard\plain \s15\qj\ri-27\sa240\keepn\nowidctlpar\tx1134\tx2835\tx3119\outlinelevel5\adjustright \f2\fs22 {IC90\tab 74LS00\tab Quad two input NAND +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 { +o/p pins 3,6,8,11 are four gates which are selectively enabled to drive the colour subcarrier resistor mixing matrix, to generate the colour subcarrier phase for the current display colour. L1, C40 and R113 in parallel with R114 form a simple low Q ban +d pass filter tuned to the colour subcarrier frequency (4.43MHz), which reduces the harmonics of the chroma (colour) signal. +\par }\pard\plain \s15\qj\ri-27\sa240\keepn\nowidctlpar\tx1134\tx2835\tx3119\outlinelevel5\adjustright \f2\fs22 {IC91\tab 75159\tab Dual RS422 line driver (ECONET only) +\par }\pard\plain \qj\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {1) o/p pin 2 used as an inverter. Forms a true RTS signal to trigger/clear the ECONET timer monostable. +\par }\pard \qj\sa240\nowidctlpar\tx2835\adjustright { +2) o/p pins 12,13 drive the ECONET data lines with an RS422 differential signal. An RS422 signal has nominal TTL logic levels; two lines are driven to opposite logic states, to give differential signal transmission. The gate is capable + of driving a 50 ohm load tied to 2.5 volts. When the ECONET interface is inactive (not transmitting) the driver is in a high impedance state. A logic 1 on pin 9 enables the driver. +\par }\pard\plain \s15\qj\ri-27\sa240\keepn\nowidctlpar\tx1134\tx2835\tx3119\outlinelevel5\adjustright \f2\fs22 {IC92\tab LM319\tab Dual analogue comparator (ECONET only) +\par }\pard\plain \qj\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {1) o/p pin 7 senses the +ECONET clock signal. R78 introduces a small amount of hysteresis to avoid self-oscillation of the comparator when no signal is present (which would result in permanent clock present indication). R63 is a pull-up, the comparator has an open collector outpu +t +. The comparator receives an attenuated clock signal which is also positively biased. R125,134,140,141 form an attenuator (approximately 10:1). R147 with R148 sets a bias of about 2 volts so the comparator input signals stay within the supply voltage (5 v +olts). +\par }\pard \qj\sa240\nowidctlpar\tx2835\adjustright { +2) o/p pin 12; this comparator receives data from the ECONET line. R73 is a pull-up and R79 gives the comparator hysteresis. R106,110,142,143 form an attenuator (approximately 10:1). Again the inputs are biased to nominally 2 volts. The comparator co +nverts the differential ECONET data signal to single ended TTL which is decoded in IC81, the ADLC. The LM319 comparator is sufficiently sensitive to allow high impedance attenuators to be used while still detecting the ECONET idle line state. An idle line + has a differential voltage of about 0.6 volts impressed on it by the ECONET line termination networks (not part of the micro). +\par }\pard\plain \s15\qj\ri-27\sa240\keepn\nowidctlpar\tx1134\tx2835\tx3119\outlinelevel5\adjustright \f2\fs22 {\page IC93\tab LM319\tab Dual analogue comparator (not normally fitted) +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {This comparator circuit is not normally fitted. When fitted its purpos +e is to detect data packet collisions on the ECONET. Collisions are normally avoided by the network filing system protocol, and so are rare. When a collision occurs it will result in data corruption (detected by the filing system error checks when collisi +on detection hardware is not fitted). If collision detection should be required then link S29 should be broken and IC93 and its associated components fitted. +\par }\pard\plain \s15\qj\ri-27\sa240\keepn\nowidctlpar\tx1134\tx2835\tx3119\outlinelevel5\adjustright \f2\fs22 {IC94\tab 88LS120 \tab Dual RS423 receiver circuit +\par }\pard\plain \qj\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {1) o/p pin 7 receives the RS423 port data signal. This in +put is also compatible with RS232 data. To reduce the voltage swing the signal is attenuated by R124,118. C31 reduces the signal bandwidth and so reduces the risk of glitches in the received signal presented to the SERPROC. +\par }\pard \qj\sa240\nowidctlpar\tx2835\adjustright {2) o/p pin 9 receives the RS423 notCTS control signal. R149,152 attenuate the voltage levels while C35 "filters" the signal. +\par S24 and S25 are optional links which connect internal termination resistors to ground. These links should not be fitted. +\par }\pard\plain \s15\qj\ri-27\sa240\keepn\nowidctlpar\tx1134\tx2835\tx3119\outlinelevel5\adjustright \f2\fs22 {IC95\tab 3691\tab Dual RS423 line driver +\par }\pard\plain \qj\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {1) o/p pi +n 10 drives the notRTS control line with an RS423 compatible signal. C45 slew limits the signal to reduce electromagnetic radiation which might cause interference to other equipment. Note in most applications this line can interface to an RS232 device. + +\par }\pard \qj\sa240\nowidctlpar\tx2835\adjustright {2) o/p pin 15 drives the data line of an RS423 interface. C44 slew limits the signal. +\par }\pard\plain \s15\qj\ri-27\sa240\keepn\nowidctlpar\tx1134\tx2835\tx3119\outlinelevel5\adjustright \f2\fs22 {IC96\tab 4164EK8\tab SIL pack 64Kbyte DRAM, 120ns access +\par }\pard\plain \qj\sa240\nowidctlpar\tx2835\adjustright \f2\fs22\lang2057 {This device can be fitted as an alternative to 8 off 64Kx1 DRAM integrated circuits ICs 55,56,60,61,64,65,66,67. +\par }} \ No newline at end of file diff --git a/B+/BPlusServiceManual/BBC+S89.tif b/B+/BPlusServiceManual/BBC+S89.tif new file mode 100755 index 0000000..97beaeb Binary files /dev/null and b/B+/BPlusServiceManual/BBC+S89.tif differ diff --git a/B+/BPlusServiceManual/BBC+S91.tif b/B+/BPlusServiceManual/BBC+S91.tif new file mode 100755 index 0000000..f4964c1 Binary files /dev/null and b/B+/BPlusServiceManual/BBC+S91.tif differ diff --git a/B+/BPlusServiceManual/BBC+S95.tif b/B+/BPlusServiceManual/BBC+S95.tif new file mode 100755 index 0000000..a6068e0 Binary files /dev/null and b/B+/BPlusServiceManual/BBC+S95.tif differ diff --git a/B+/BPlusServiceManual/BBC+S97.tif b/B+/BPlusServiceManual/BBC+S97.tif new file mode 100755 index 0000000..4f7ebd1 Binary files /dev/null and b/B+/BPlusServiceManual/BBC+S97.tif differ diff --git a/B+/BPlusServiceManual/BBC+S99.tif b/B+/BPlusServiceManual/BBC+S99.tif new file mode 100755 index 0000000..66e78ef Binary files /dev/null and b/B+/BPlusServiceManual/BBC+S99.tif differ diff --git a/B+/BPlusServiceManual/Thumbs.db b/B+/BPlusServiceManual/Thumbs.db new file mode 100755 index 0000000..facc646 Binary files /dev/null and b/B+/BPlusServiceManual/Thumbs.db differ diff --git a/B/BBC-circuit-diagram.png b/B/BBC-circuit-diagram.png new file mode 100755 index 0000000..a3319aa Binary files /dev/null and b/B/BBC-circuit-diagram.png differ diff --git a/B/BBCServiceManual.pdf b/B/BBCServiceManual.pdf new file mode 100755 index 0000000..28ef0ef Binary files /dev/null and b/B/BBCServiceManual.pdf differ diff --git a/B/os/Microbase b/B/os/Microbase new file mode 100755 index 0000000..3251a42 --- /dev/null +++ b/B/os/Microbase @@ -0,0 +1,1682 @@ +BBC MICROBASE SERIES +BBC 6502 Machine Code by Geoff Cox +---------------------------------- +This series was first published on Micronet +between April and October 1991 + +The BBC Micro Operating System +Part One: The moving electron writes +------------------------------------ +In the last series we reviewed the basics of machine code programming +using the 6502. You will have noticed that not too many examples of +programming were given. This is because there are two levels of +programming on any machine, machine level and operating system level. + +Operating Systems +----------------- +An operating system is basically a group of routines that sit between +the user and the electronics of the computer. To illustrate what an +operating system does we have to turn briefly from the path of the +series. + +We'll imagine that you want to write the letter A on the screen of +your monitor. First we have to work out the shape of the character and +slice it horizontally into eight sections, one for each of eight +screen scanning lines on the monitor. + +Now we need to detect when the frame synchronising pulse for the +monitor is sent by the computer. Next we need to count the line +synchronising pulses to find the one corresponding to the start of the +first line of the character. + +Then we must time from this pulse to the start of the first line of +the character, turn on the appropriate electron guns in the monitor +and turn them off at the correct time for the end of the of the +character. Finally we have a few microseconds to do it all again for +the next line. That's more or less what happens fifty times a second +on your monitor screen. + +Mapped Screens +-------------- +This makes even the easiest task very complex. We can make life easier +by storing a picture or map of the screen in memory and writing the +character shape to the appropriate map locations. + +The map can then be scanned in synchronisation with the electron beam +on the monitor. This can either be via a clever piece of electronics +or a software routine. + +To illustrate the BBC map, type the following program on any 6502- +based BBC without screen RAM shadowing. + +10 MODE 0 +20 ?&7D00=65 + +You should see two little white dots towards the bottom right of the +screen. Now two dots are not the letter A so if we want to write A we +have to designthe character and write it to the map. This program does +just that. + +10 MODE 0 +20 FOR A=&7D00 TO &7D07 +30 READ B +40 ?A=B +50 NEXT +60 DATA &3C, &66, &66, &7E +70 DATA &66, &66, &66, &00 + +The sharp-eyed among you will have spotted something a little odd +here. The screen seems to be arranged in blocks of eight bytes in this +mode. Don't worry about this - it simply makes character table design +simpler. + +Character Tables +---------------- +We can make life even easier by designing a set of characters and +putting them in an area of memory where they can be looked up. In the +BBC B this area is in ROM starting at &C000. + +A quick diversion here. If we have to have a series of character +designs in memory it helps to have a standard method of accessing +them. + +The standard character ordering is called ASCII. A space has ASCII +number 32 and this is the first "printable" character in the set. The +last is 127 (Delete). There are eight bytes in each character matrix +so the design for any character is at &C000+(8*(ASCII - 32)). + +This program examines the ROM character table and shows how characters +are arranged. + +10 MODE 0 +20 PRINT "CHARACTER ?" +30 A$=GET$ +40 PRINT A$ +50 START=(8(ASC(A$)-32))+&C000 +60 FIN=START+7 +70 FOR BYTE=START TO FIN +80 PEEK=?BYTE +90 PROC_BIN +100 PRINT~BYTE;TAB(15);~?BYTE;TAB(20); +110 NEXT +120 END +130 DEFPROC_BIN +140 A$="" +150 FOR BIT=7 TO 0 STEP-1 +160 X=(PEEK AND 2^BIT) +170 IF X>1 THEN A$=A$+"" ELSE A$=A$+"." +180 NEXT +190 ENDPROC + +As you will often want to write characters on the screen it makes a +lot of sense to have a little routine to take a character from a +register and print it on the screen. + +The routine will look up a character in the table and print it to the +appropriate position on the screen. There will also need to be a +record of the cursor position on the screen. + +Routines for printing and moving a cursor on the screen will also be +useful. You could, of course, write all of these routines yourself as +part of every program but as the computer manufacturer has to provide +them in order to tell you the machine is working he usually leaves an +access point for you to use the routines yourself. + +Incidentally if you rewrite the first program but change line 10 to +read MODE 7 you will see a letter A on the screen. + +This is an example of clever electronics. A chip on the BBC board +contains a character generator. Instead of the character design being +stored in the screen map the character's ASCII value is stored. This +is read by the electronics and used to generate characters directly on +the screen. This allows a 40 x 80 text and block graphics screen to be +generated in just 1K of RAM. + +Using the Operating System +-------------------------- +The screen handling routines and several others make up an operating +system. In the BBC micro the series of routines that write a character +on the screen can be accessed though a point called OSWRCH at &FFFE. + +So instead of having to design characters, time lines and do all of +the other things, you can output a letter A to the screen simply +using: + +LDA #65 +JSR &FFEE ;OSWRCH + +and leave the operating system to do the rest. + + +BBC 6502 Machine Code +Part Two: In the beginning +-------------------------- +Last week we looked at the reasons for an operating system and how it +can simplify the programmer's task. Unfortunately you will not always +be able to use the operating system. There may not be a suitable +routine or it may be too slow. In these cases you have to write to the +device itself. So to continue our look at machine code we need to +examine programming with device handling and the operating system. + +This series will attempt to kill two birds with one stone by taking +avery close look at Acorn's OS 1.20 used on Model Bs. + +This changed little for the B+ and Master so while the routines may be +in a slightly different place the basic system will be the same. The +Master uses 65C02 code which has a few extra instructions so there may +be some differences in the length of the code. + +What you will need +------------------ +A disassembler or machine code monitor that can handle 6502 or 65C02 +codes. If If you don't have either you can use: + +PRINT ~?address + +to get the hexadecimal codes which you can then look up in the back of +the BBC User Guide to get the relevant command. + +Suitable Monitors are EXMON, BBC Monitor or the SYSTEM monitor. (I use +"Maxim" - Ed.) If you have a single- stepping monitor like one of +these, you will be able to trace some of the routines for yourself. + +For this series we will use standard 6502 mnemonics except that DB and +DW will be used to show byte assignments rather than EQUS, EQUW and +EQUB. This is because the disassembler I am using produces these codes +and it's a lot easier to follow than convoluted BBC-type statements. + +First things first +------------------ +Remember that an operating system is not a program in the usual sense. +Normal programs have a defined entry and exit routines. An operating +system can have a large number of entry and exit points as well as +interlocking routines. So to examine the operating system we need a +starting point. + +The 6502 regards memory as a series of 256-byte pages 0 to &FF (255). +Any address can be considered to be a page number plus an offset +within the page. Both figures can be represented by a single byte. So +address &FF01 is on Page &FF offset 01. The concept of offsets is very +useful if you ever get involved in 80n86 programming. + +The BBC Manual gives a series of system entry points on page FF. Most +of these are indirected through Page 2 and as we cannot guarantee what +the contents of Page 2 should be (the vectors can be and are changed) +these are useless as starting points. This leaves three sensible entry +points. + +6502 Vectors +FFFA DW &0D00 ;NMI address +FFFC DW &D9CD ;RESET address +FFFE DW &DC1C ;IRQ address + +The NMI address is in RAM so no joy there, but the other two look +fine. The best is RESET as this is where the machine starts when it is +turned on or BREAK is pressed. In the case of Model B and OS 1.20 that +address is &D9CD, so what happens? + +In the beginning +---------------- +Reset can be effected by turning on the computer or pressing BREAK. If +it is a power-up then the system VIA and processor are reset +electronically. + +If this is a power on situation then nothing has been set up. The +first thing that happens when power is turned on is that the 6522 +VIAs, the processor and the floppy disc controller are reset. This is +done by means of one of three printed circuit tracks. The tracks are +RSTA, RST and NOTRESET. + +RSTA is only connected to the system 6522 Versatile Interface adaptor +(VIA). This operates through a little resistor/capacitor circuit that +only works when the power is turned on. The effect of this is that the +6522 System VIA Interrupt Enable Register (IER) bits 0 to 6 will be +clear (0) only if the reset is caused by a power on condition. + +If the Reset is caused by BREAK being pressed then the machine must +have been on and therefore one or more of the System VIA IER bits will +be set (to 1). If one or more bits are set then bit 7 of the VIA will +also be set. This is used to determine the type of Reset. So let's +look at the operating system more closely. + +D9CD LDA #&40 ;set NMI first instruction to RTI +D9CF STA &0D00 ;NMI RAM start + +RESET is the ultimate Act of God as far as the machine is concerned. +Anything could be happening so the operating system has to clean up +the system as its first act. + +These first instructions just make sure that if a disc is running no +more information will be read or written from or to the disc. This +illustrates why you shouldn't press BREAK when a disc is being +accessed! + +The next section sets up the stack: + ++ +D9D2 SEI ;disable interrupts just in case +D9D3 CLD ;clear decimal flag +D9D4 LDX #&FF ;reset stack to where it should be +D9D6 TXS ;(&1FF) + +Next find out if a power-up reset or a BREAK press by examining the +System VIA IER register. + +D9D7 LDA &FE4E ;read interrupt enable register of the system VIA +D9DA ASL ;shift bit 7 into carry +D9DB PHA ;save what's left +D9DC BEQ &D9E7 ;if Power up A=0 so go to D9E7 to clear memory + +That's probably enough for this time. Don't worry! I don't intend to +do a complete disassembly of the operating system in this series but +we will follow through the power-on sequence to the end because a lot +of interesting things happen at this time. + +We'll take a look at D9E7 and the next routine in this sequence (D9DE) +in the next part. + + +BBC 6502 Machine Code +Part Three: Cleaning up the mess +-------------------------------- +In the last part we looked at what happens when you press BREAK or +switch on the machine. We'll now continue with a look at an +undocumented (at least officially) routine. + +The byte at &258 can be used to contain information about what the +machine should do if BREAK is pressed. FX200,n is used to set this +byte. If n=2 or n=3 then the memory must be cleared. This is often +used in program protection. + +D9DE LDA &0258 ;else if BREAK pressed read BREAK Action flags (set by FX200,n) +D9E1 LSR ;divide by 2 +D9E2 CMP #&01 ;if &0258 <> 2 or 3 +D9E4 BNE &DA03 ;then Goto &DA03 +D9E6 LSR ;divide A by 2 again (A=0 if FX200,2/3 else A=n/4 + +Pages 4-&7F are cleared by a simple loop if &258=2 or 3 or it is a +power on reset. Look out for the clever way of avoiding problems on +16K machines. + +D9E7 LDX #&04 ;get page to start clearance from (4) +D9E9 STX &01 ;store it in ZP 01 +D9EB STA &00 ;store A at 00 +D9ED TAY ;and in Y to set loop counter + ;LOOP STARTS +D9EE STA (&00),Y ;clear RAM +D9F0 CMP &01 ;until page address (in &01) =0 +D9F2 BEQ &D9FD ; +D9F4 INY ;increment pointer +D9F5 BNE &D9EE ;if not zero loop round again +D9F7 INY ;else increment again (Y=1) this avoids overwriting the RTI + ;instruction at &D00 +D9F8 INX ;increment X +D9F9 INC &01 ;increment &01 +D9FB BPL &D9EE ;loop until Page (in 01)=&80 then exit + +Note that RAM addressing for 16K loops around to &4000=&00 hence the +checking of &01 for 00. This avoids overwriting zero page on BREAK +which would cause the machine to crash! + +D9FD STX &028E ;writes marker for available RAM 40 =16K,80=32 +DA00 STX &0284 ;write soft key consistency flag + +This routine shows the basic structure of a loop. Those of you who +program in BASIC will recognise it as a very simple structure: + +10 A=A+1 +20 IF A<20 GOTO 10 + +The loop uses zero page addressing with the target address in 00 and +01 (Page) and the index in Y. + +The loop is exited when the value in 01 becomes negative. Remember +that all values between 0 and &7F are considered to be positive, so +the BPL instruction can be used to exit the loop at page &80, the +first negative number. This is the first of the useful loop techniques +we'll see in this series. + +Notice that the first byte of each page is left unchanged. This is +useful if you want information to survive a BREAK of this type. This +clearing of memory is not normally carried out. + +Next week we'll have a look at the normal RESET path. + +BBC 6502 Machine Code +Part Four: Cleaning up even more mess +------------------------------------- +As we saw last week, a normal warm reset avoids the memory clearance +and proceeds to set up the System VIA. + +DA03 LDX #&0F ;set PORT B data direction register to output on bits + ;0-3 and input bits 4-7 +DA05 STX &FE42 ; + +The next bit is a little more complicated and is intimately bound up +with hardware. The function is to set up the addressable latch IC 32 +for peripherals via PORT B. + +The latch value is written by writing the value to &FE40 bits 0 to 2 +and either a 1 or 0 to bit 3. + +Writing the value + 8 therefore writes a 1 to the latched address, +otherwise a 0 is written. + +Value Peripheral Effect ++ 0 8 + +0 Sound chip Enabled Disabled + Speech Chip +1 (RS) Low High +2 (WS) Low High +2 (WS) Low High +3 Keyboard + Write Disabled Enabled +4 C0 address + modifier Low High +5 C1 address + modifier Low High +6 Caps LED On Off +7 Shift LED On Off + +C0 and C1 are involved with hardware scroll screen address. + + ;X=&F on entry +DA08 DEX ;loop start +DA09 STX &FE40 ;Write latch IC32 +DA0C CPX #&09 ;Is it 9? +DA0E BCS &DA08 ;If not go back and do it again + ;X=8 at this point + ;Caps Lock On, SHIFT Lock undetermined + ;Keyboard Autoscan on + ;Sound disabled (may still sound) + +Next the keyboard is scanned to determine the values of the keyboard +links and whether a Ctrl-Break has been performed. + +Remember that although we have spent a lot of time reading this, we +are probably less than 200 microseconds after BREAK was pressed. + +The check for Ctrl-Break is effectively looking for simultaneous +keypresses. + +DA10 INX ;X=9 +DA11 TXA ;A=X +DA12 JSR &F02A ;Interrogate keyboard +DA15 CPX #&80 ;for keyboard links 9-2 and CTRL key (1) +DA17 ROR &FC ;rotate MSB into bit 7 of &FC + +DA19 TAX ;Get back value of X for loop +DA1A DEX ;Decrement it +DA1B BNE &DA11 ;and if >0 do loop again + ;On exit if Carry set link 3 is made + ;link 2 = bit 0 of &FC and so on + ;If CTRL pressed bit 7 of &FC=1 X=0 +DA1D STX &028D ;Clear last BREAK flag +DA20 ROL &FC ;CTRL is now in carry &FC is keyboard links +DA22 JSR &EEEB ;Set LEDs + ;Carry set on entry is in bit 7 of A on exit +DA25 ROR ;Get carry back into carry flag + +To review what the operating system has done so far, about 400 +microseconds after a BREAK press or about 2 milliseconds from a power +on. Memory may have been cleared, NMIs have been short circuited, IRQs +disabled. The keyboard has been scanned for made links and for Ctrl +being pressed. + +We have also located two important and undocumented subroutines: &F02A +to scan the keyboard and &EEEB to set the keyboard LEDs. + +The F02A routine scans for the key whose code is in X being pressed: + +F02A LDY #&03 ;Stop Auto scan +F02C STY &FE40 ;by writing to system VIA +F02F LDY #&7F ;Set bits 0 to 6 of port A to input on bit 7. + ;Output on bits 0 to 6 +F031 STY &FE43 ; +F034 STX &FE4F ;Write X to Port A system VIA (key to check) +F037 LDX &FE4F ;Read back &80 if key pressed (M set) +F03A RTS ;And return + +The routine at &EEEB switches on the selected keyboard lights. + +EEEB PHP ;Save flags +EEEC LDA &025A ;Read keyboard status + ;Bit 7=1 shift enabled + ;Bit 6=1 control pressed + ;Bit 5 =0 shift lock + ;Bit 4 =0 Caps lock + ;Bit 3 =1 shift pressed +EEEF LSR ;Shift Caps bit into bit 3 +EEF0 AND #&18 ;Mask out all but 4 and 3 +EEF2 ORA #&06 ;Returns 6 if caps lock OFF &E if on. + ;Remember add 8 to the value for the addressable + ;latch to send a 1. +EEF4 STA &FE40 ;Turn on or off caps light if required +EEF7 LSR ;Bring shift bit into bit 3 +EEF8 ORA #&07 ; +EEFA STA &FE40 ;Turn on or off shift lock light +EEFD JSR &F12E ;Set keyboard counter +EF00 PLA ;Get back flags into A +EF01 RTS ;Return + +In this part we've had a look at subroutines using JSR and RTS, the +machine code equivalent of GOSUB, PROC or FN. Subroutines are often +used in machine code to perform such frequently needed functions as +scanning a keyboard or turning on and off lights. + +We've also discovered that the byte at &25A contains the keyboard +status. Try changing it for yourself. You can therefore use OR and AND +to set the shift and Caps lock status of the machine for a particular +program. + +Next week we'll examine setting up the default vector table in memory. + +BBC 6502 Machine Code +Part Five: Vectors Victor +------------------------- +The next stage is to set up the vectors on page 2. + +DA26 LDX #&9C ; +DA28 LDY #&8D ; +DA2A PLA ;Get back A from &D9DB +DA2B BEQ &DA36 ;If A=0 power up reset so go to DA36 with X=&9C + ;Y=&8D +DA2D LDY #&7E ;else let Y=&7E +DA2F BCC &DA42 ;and if not CTRL- BREAK go to DA42 for a WARM RESET +DA31 LDY #&87 ;else Y=&87 COLD RESET +DA33 INC &028D ;&28D=1 +DA36 INC &028D ;&28D=&28D+1 +DA39 LDA &FC ;Get keyboard links set +DA3B EOR #&FF ;Invert +DA3D STA &028F ;and store at &28F +DA40 LDX #&90 ;X=&90 + +What we have done is to set up the high water marks for the reset of +vectors. + +&28D=0 Warm reset, X=&9C, Y=&7E +&28D=1 Power up , X=&90, Y=&8D +&28D=2 Cold reset, X=&9C, Y=&87 + +DA42 LDA #&00 ;A=0 +DA44 CPX #&CE ;zero &200+X to &2CD +DA46 BCC &DA4A ; +DA48 LDA #&FF ;then set &2CE to &2FF to &FF +DA4A STA &0200,X ; +DA4D INX ; +DA4E BNE &DA44 ; + ;A=&FF X=0 + +This is another IF-GOTO loop, but in this case it is a double function +loop. The test at DA44 to DA46 means that A is 0 only for values of X +between the high water mark and &CD. Above this value A is set to &FF +by the instruction at &DA48. This saves a few bytes of space, +essential when writing a tightly-filled ROM. + +The next instructions set up the printer port. The only reason for +doing this now is to save two bytes. A must be &FF at this point so it +is used to set up the User VIA for outputs as the printer port. + +DA50 STA &FE63 ;Set port A of user VIA to all outputs (printer out) +DA53 TXA ;A=0 +DA54 LDX #&E2 ;X=&E2 + +START OF LOOP +DA56 STA &00,X ;set zero page addresses &E2 to &FF to zero +DA58 INX ; +DA59 BNE &DA56 ;X=0 + +Now set up the vectors in page 2 from the table at &D940: + +DA5B LDA &D93F,Y ;copy data from &D93F+Y +DA5E STA &01FF,Y ;to &1FF+Y +DA61 DEY ;until +DA62 BNE &DA5B ;1FF+Y=&200 + +Note that this is a decrementing loop which, for loops ending when an +index register reaches zero, is faster and shorter because no compare +is needed. More space saved! + +Now the RS423 port is set up via a subroutine affecting the ACIA. +(Asynchronous Communications Interface Adaptor) + +DA64 LDA #&62 ;A=&62 +DA66 STA &ED ;store in &ED +DA68 JSR &FB0A ;set up ACIA ;X=0 + +Now Acorn clears the interrupt and enable registers of both VIAs. + +DA6B LDA #&7F ;bit 7 is 0! +DA6D INX ; +DA6E STA &FE4D,X ; +DA71 STA &FE6D,X ; +DA74 DEX ; +DA75 BPL &DA6E ; + ;This loop only has two passes as X=0 on entry. +DA77 CLI ;Briefly allow interrupts to clear anything + ;pending +DA78 SEI ;Disallow again NB: all VIA IRQs are disabled +DA79 BIT &FC ;If bit 6=1 then JSR &F055 as there must be a + ;hardware interrupt! +DA7B BVC &DA80 ;else DA80 +DA7D JSR &F055 ; + +What have we here? Another undocumented routine. If bit 6 of &FC is +set there must have been a hardware interrupt when the SEI occurred. + +From the circuit diagram the only place that this IRQ could have come +from is the 1MHz bus - let's have a look at the routine at &F055. + +F055 JMP (&FDFE) ;Jim paged entry vector + +So we jump to some piece of hardware on the 1MHz bus. This would +probably be a ROM which would take over the system at power on and +Break. This has some very interesting applications. It was designed by +Acorn to provide a crude Econet facility to allow a batch of machines +to be functionally tested without the need to install a full Econet +kit. + +Next week we shall examine the VIA bus. + +BBC 6502 Machine Code +Part Six: The VIA bus +--------------------- +The next interesting routine we find in the BBC operating system is +the one that sets up the system VIA interrupts. It is located at +&DA80. Refer to the manual for the meanings of Sheila addresses. + +DA80 LDX #&F2 ;Enable interrupts 1,4,5,6 of system VIA +DA82 STX &FE4E ; + ;0 Keyboard enabled as needed + ;1 Frame sync pulse + ;4 End of A/D conversion + ;5 T2 counter (for speech) + ;6 T1 counter (10 mSec intervals) + +DA85 LDX #&04 ;set system VIA PCR +DA87 STX &FE4C ; + ;CA1 Interrupt on negative edge (Frame sync) + ;CA2 Handshake output for keyboard + ;CB1 Interrupt on negative edge (end of conversion) + ;CB2 Negative edge (Light pen strobe) +DA8A LDA #&60 ;Set system VIA ACR +DA8C STA &FE4B ; + ;Disable latching + ;Disable shift register + ;T1 counter continuous interrupts + ;T2 counter timed interrupt + +DA8F LDA #&0E ;Set system VIA T1 counter (low) +DA91 STA &FE46 ; + ;This becomes effective when T1 hi set +DA94 STA &FE6C ;Set user VIA PCR + ;CA1 interrupt on -ve edge (Printer Acknowledge) +DA80 LDX #&F2 ;enable interrupts + ;CA2 High output (printer strobe) + ;CB1 Interrupt on -ve edge (user port) + ;CB2 Negative edge (user port) +DA97 STA &FEC0 ;Set up A/D converter Bits 0 and 1 determine + ;channel selected + ;If Bit 3=0 it is set for an 8-bit conversion. + ;If bit 3=1 12-bit conversion. + +Now although the machine now knows how much RAM it has it still +doesn't know if it's a Model A or Model B, so it does not know if a +user VIA is present at &FE60-FE6F. + +The next routine tests for the presence of a user VIA. The system +timers are then set up to interrupt every 10mSec. Sound channels are +cleared and the serial ULA is set up. Then the function keys are +reset. + +Now we need a catalogue of sideways ROMS. This is not a catalogue in +the conventional sense as the ROM title is always at the same place in +the ROM itself and can be read from there. It is a catalogue of the +ROM types and positions. + +There is a ROM latch at &FE30. Writing a number between 0 and 15 to +this switches the corresponding ROM into the area between &8000 and +&BFFF. A short subroutine does this and maintains a copy of the +current ROM in zero page at location &F4. + + ;on entry X=required ROM number +DC16 STX &F4 ;RAM copy of ROM latch +DC18 STX &FE30 ;Write to ROM latch +DC1B RTS ;and return + +You should use this subroutine if you want to switch ROMs. Now we can +look at the ROM cataloguing routines; + +A ROM is considered to be valid if it contains a string identical to +astring at location &DF0C in the Operating System ROM. + +DF0C DB ')C(' ; +DF0F DB 0 ; + +The location of this string is pointed to by an offset byte located at +&8007. + +;X=0 on entry +DABD JSR &DC16 ;Set up ROM latch and RAM copy to X +DAC0 LDX #&03 ;Set X to point to offset in table +DA80 LDX #&F2 ;Enable interrupts +DAC2 LDY &8007 ;Get copyright offset from ROM +DAC5 LDA &8000,Y ;Get first byte +DAC8 CMP &DF0C,X ;Compare it with table byte +DACB BNE &DAFB ;If not the same then goto DAFB +DACD INY ;Point to next byte +DACE DEX ;(s) +DACF BPL &DAC5 ;and if still +ve go back to check next byte. + ;This point is reached if 4 bytes indicate + ;valid ROM + +Next the first 1K of each ROM is checked against higher priority ROMs +to ensure that there are no matches. If a match is found, the lower +priority ROM is ignored. + +A ROM type byte is located at &8006. A catalogue of these bytes is +held at &2A1-&2B0. If bit 7 of this byte is 0 then the ROM is BASIC. +The position of this ROM is stored at &24B. + +Now the ROMs are catalogued it is time to set up the speech system and +screen. More about that next week. + +BBC 6502 Machine Code +Part Seven: Talk to me +---------------------- +The operating system start-up routines next checks the SPEECH system. +At this point the X register is set to 16 (&10) by previous routines. + +This is one of the reasons why this routine is inserted here. Setting +X to the required value would use two more bytes. This is not much +space but it can make the difference between all of the OS fitting +into a single ROM and a complete hardware or software redesign. + +DB11 BIT &FE40 ;If bit 7 low then we have speech system fitted +DB14 BMI &DB27 ;else goto DB27 for screen set up routine. +DB16 DEC &027B ;(027B)=&FF a RAM flag that indicates that a speech + ;chip is present. +DB19 LDY #&FF ;Y=&FF +DB1B JSR &EE7F ;Initialise speech generator +DB1E DEX ;via this +DB1F BNE &DB19 ;loop + +Now X = 0 so: + +DB21 STX &FE48 ;Set T2 timer for speech +DB24 STX &FE49 ; + +Screen set-up +------------- +X=0 on entry to this routine which gets the default screen mode and +then goes off to the screen setup routine. + +DB27 LDA &028F ;Get back start up options (mode) +DB2A JSR &C300 ;then jump to initialise screen. + +One of the things that I wondered when I got a BBC was how the RESET +key could possibly act as a soft key. As we all know BREAK acts as +soft key 10. But the keyboard buffer is cleared by the Reset. Tucked +away is the five-byte routine that makes the BREAK key act as soft +key 10. + +Soft keys work by inserting a byte greater than 127 into the keyboard +buffer. &CA is the code for key 10. + +DB2D LDY #&CA ;Y=&CA +DB2F JSR &E4F1 ;to enter this value in the keyboard buffer + +Simple isn't it? You can use the routine yourself although further +investigation will show that E4F1 is part of an OSbyte call. Remember +that the keyboard buffer is buffer 0. + +E4F1 LDX #&00 ;X=0 keyboard buffer + +************************************** +* * +* OSBYTE 153 Put byte in input * +* Buffer checking for ESCAPE * +* * +************************************** + +On entry X = buffer number which is either 0 or 1. If it's 0 then the +keyboard buffer is selected. If it's 1 then it is the RS423 buffer. + +Notice that the JSR to EF41 ensures that ONLY the keyboard buffer can +be selected. Once again we are looking at coding economy, in this case +with a specific keyboard buffer entry routine. Y contains the +character to be written. + +E4F3 TXA ;A=buffer number +E4F4 AND &0245 ;and with RS423 mode (0 treat as keyboard 1 ignore + ;Escapes no events no soft keys) +E4F7 BNE &E4AF ;so if RS423 buffer AND RS423 in normal mode (1) E4AF + ; +E4F9 TYA ;else Y=A character to write +E4FA EOR &026C ;compare with current escape ASCII code (0=match) +E4FD ORA &0275 ;or with current ESCAPE status (0=ESC, 1=ASCII) +E500 BNE &E4A8 ;if ASCII or no match E4A8 to enter byte in buffer +E502 LDA &0258 ;else get ESCAPE / BREAK action byte +E505 ROR ;Rotate to get ESCAPE bit into carry +E506 TYA ;get character back in A +E507 BCS &E513 ;and if escape disabled exit with carry clear +E509 LDY #&06 ;else signal EVENT 6 Escape pressed +E50B JSR &E494 ; +E50E BCC &E513 ;if event handles ESCAPE then exit with carry clear +E510 JSR &E674 ;else set ESCAPE flag +E513 CLC ;clear carry +E514 RTS ;and exit + +This routine will normally be accessed by assembly language +programmers by OSbyte 138 which calls EF43. + +BBC 6502 Machine Code +Part Eight: Breaker Break +------------------------- +One of the 'secret' features of the BBC Micro OS 1.20 when it was +arrived was the BREAK intercept. This is a useful method of taking +over the machine and is sometimes used by ROM software. + +There are two entry points, entered with the carry flag reset to 0 and +set to 1 respectively. The first call comes before sideways ROM calls. + +Enter BREAK intercept with Carry Clear + +DB32 JSR &EAD9 ;check to see if BOOT address is set up if so + ;JMP to it + +The address &287 is written by OSbyte 247 and the jump addresses in +&288 and &289 by OSbytes 248 and 249. The machine code for JMP is &4C. + +EAD9 LDA &0287 ;get BREAK vector code +EADC EOR #&4C ;produces 0 if JP (4C) not in &287 +EADE BNE &EAF3 ;if not goto EAF3 +EAE0 JMP &0287 ;else jump to use BREAK code +EAF3 RTS ;Return + +The RTS at the end of another routine is used because it saves code. + +Frequently you will find machine code routines where a lot of branches +go to a single RTS for just this reason. If you are writing your own +code remember that the RTS must be within range of the branch. One of +the most common assembler errors is a branch out of range that in turn +causes more errors when you add an extra RTS. + +Obviously at this point the machine could be totally in your control. +You can return control to the OS with an RTS or just continue on your +merry way. + +Remember that the sideways ROMs don't have any workspace yet and you +can't really run BASIC or any other language as the workspace will not +exist. But, assuming that you don't want to do any of this, let's go +back to the OS routines after testing for BREAK intercept. + +DB35 JSR &F140 ;set up cassette options +DB38 LDA #&81 ;test for tube to FIFO buffer 1 +DB3A STA &FEE0 ; +DB3D LDA &FEE0 ; +DB40 ROR ;put bit 0 into carry +DB41 BCC &DB4D ;if no tube then DB4D +DB43 LDX #&FF ;else +DB45 JSR &F168 ;issue ROM service call &FF to initialise TUBE system +DB48 BNE &DB4D ;if not 0 on exit (tube not initialised) DB4D +DB4A DEC &027A ;else set tube flag to show its active + +Now the Tube is flagged as active, or not as the case may be. We +continue next week, with the setup routines for the sideways ROMs. + +BBC 6502 Machine Code +Part Nine: A ROM with a view +----------------------------- +Now we nearly have a working system, we are, perhaps, 400 milliseconds +into the Power up routine. Now is the time to set up all of those nice +sideways ROMs we catalogued earlier. + +First we set up workspace and hence the value of BASIC's PAGE +variable. The call to ROMs is made via F168. This is available to the +programmer as OSBYTE 143. + +A ROM can have a number between 0 and 15 and will have two entry +points - a Service entry at &8003 and a Language entry at &8000. If +the ROM does not contain language code it will not have a language +entry. + +ROMs are paged into main memory by writing the ROM number to a latch +at &FE30. Hardware could be arranged to allow 256 ROMs although the +operating system does not support this. + +The Break Intercept code could be used to make drastic hardware +modifications like this. + +************************************** +* * +* OSBYTE 143 * +* Pass service commands * +* to sideways ROMs * +* * +************************************** + ;on entry X=command number +F168 LDA &F4 ;get current ROM number +F16A PHA ;store it +F16B TXA ;command in A +F16C LDX #&0F ;set X=15 + +The next bit of code is a countdown loop to send the command code to +each enabled ROM in turn. The Map at &2A1 is used to decide which ROMs +are active. Note the use of a countdown loop. This gives code economy +and explains why the highest ROM number has priority. + +F16E INC &02A1,X ;read bit 7 on ROM map (no ROM has type 254 &FE) +F171 DEC &02A1,X ; +F174 BPL &F183 ;if not set (+ve result) +F176 STX &F4 ;else store ROM number in &F4 +F178 STX &FE30 ;switch in paged ROM +F17B JSR &8003 ;and jump to service entry +F17E TAX ;on exit put A in X +F17F BEQ &F186 ;if 0 (command recognised by ROM) reset ROMs & exit +F181 LDX &F4 ;else point to next lower ROM +F183 DEX ; +F184 BPL &F16E ;and go round loop again +F186 PLA ;get back original ROM number +F187 STA &F4 ;store it in RAM copy +F189 STA &FE30 ;select original page +F18C TXA ;put X back in A +F18D RTS ;and return + +Couldn't be easier! So we can now return to the main body of the +routine. + +DB4D LDY #&0E ;set current value of PAGE +DB4F LDX #&01 ;issue call to claim absolute workspace +DB51 JSR &F168 ;via F168 +DB54 LDX #&02 ;send private workspace claim call +DB56 JSR &F168 ;via F168 + +OSHWM is OS High Water Mark. The highest address used by the operating +system. + +DB59 STY &0243 ;set primary OSHWM +DB5C STY &0244 ;set current OSHWM +DB5F LDX #&FE ;issue call for Tube to explode character set etc. +DB61 LDY &027A ;Y=FF if tube present else Y=0 +DB64 JSR &F168 ;and make call via F168 + +We now have the machine set up to enter a language, all the filing +systems have been set up and the sideways ROMs activated. + +Next week we finally start the screen messages. + +BBC 6502 Machine Code +Part Ten: Stringing it along +----------------------------- +The next routine shows why the Machine start up message is not always +seen on third-party kit. + +DB67 AND &0267 ;if A=&FE and bit 7 of 0267 is set then continue +DB6A BPL &DB87 ;else ignore start up message +DB6C LDY #&02 ;output to screen +DB6E JSR &DEA9 ;'BBC Computer ' message + +Looking at the routine in DEA9 we find a very useful string printing +routine. Remember that Y = 2 on entry. + +DEA9 LDA #&C3 ;point to start &C300 +DEAB STA &FE ;store it +DEAD LDA #&00 ;point to lo byte +DEAF STA &FD ;store it and start loop with Y=2 +DEB1 INY ;print character in string +DEB2 LDA (&FD),Y ;pointed to by &FD/E +Y +DEB4 JSR OSASCI ;print it expanding Carriage returns +DEB7 TAX ;store A in X +DEB8 BNE &DEB1 ;and loop again if not =0 +DEBA RTS ;else exit + +Here is the string delimited by BRK. The code for BRK is 00. Y is 3 +when the first character is read so its address is &C303. + +C303 DB 13 ;Carriage Return +C304 DB 'BBC Computer ' +C311 BRK + +Notice that the routine uses TAX to set the zero flag which marks the +end of the string. This is a useful tip. + +The next part of the Operating system deals with printing correct +messages on the screen. + +DB71 LDA &028D ;0=warm reset, If a cold reset continue +DB74 BEQ &DB82 ; +DB76 LDY #&16 ;by checking length of RAM +DB78 BIT &028E ; +DB7B BMI &DB7F ;and either +DB7D LDY #&11 ; +DB7F JSR &DEA9 ;finishing message with '16K' or '32K' +DB82 LDY #&1B ;and two new lines +DB84 JSR &DEA9 ; + +Notice that Y is used to pick the appropriate message. + +C312 DB '16K' +C315 DB 7 ;Bell +C316 BRK +C317 DB '32K' +C31A DB 7 ;Bell +C31B BRK +C31C DB 08,0D,0D + +Notice the BBC Beep at this point indicates that nearly all set up +procedures have been finished. + +The hum is generated by the Sound channel which is reset as part of +the start routine. Hence the HUM-BEEP start up. If the machine does +not start properly the sound signals give a strong clue to the nature +of the problem. Having got this far the OS gives us another chance to +take control. + +Enter BREAK INTERCEPT ROUTINE WITH CARRY SET (call 1) + +DB87 SEC ; +DB88 JSR &EAD9 ;look for break intercept jump + ;SEE EARLIER PART + +Next we set up the keyboard lights + +DB8B JSR &E9D9 ;set up LEDs in accordance with keyboard status + +This is another 'undocumented' OSBYTE call. + +************************************** +* * +* OSBYTE &76 (118) * +* SET LEDs to Keyboard Status * +* * +************************************** +;osbyte entry with carry set +E9D9 PHP ;PUSH P +E9DA SEI ;DISABLE INTERRUPTS +E9DB LDA #&40 ;switch on CAPS and SHIFT lock lights +E9DD JSR &E9EA ;via subroutine +E9E0 BMI &E9E7 ;if ESCAPE exists (M set) E9E7 +E9E2 CLC ;else clear V and C +E9E3 CLV ;before calling main keyboard routine to +E9E4 JSR &F068 ;switch on lights as required +E9E7 PLP ;get back flags +E9E8 ROL ;and rotate carry into bit 0 +E9E9 RTS ;Return to calling routine + ; +* Turn on keyboard lights and +* Test Escape flag + ; +E9EA BCC &E9F5 ;if carry clear +E9EC LDY #&07 ;switch on shift lock light +E9EE STY &FE40 ; +E9F1 DEY ;Y=6 +E9F2 STY &FE40 ;switch on Caps lock light +E9F5 BIT &FF ;set minus flag if bit 7 of &00FF is set indicating +E9F7 RTS ;that ESCAPE condition exists, then return + +The Keyboard routine continues via the KEYV. This is a little long to +include here so we'll leave it until a later part. So back to the +Start up routine next week with the cassette system. + +BBC 6502 Machine Code +Part Eleven: Language! +---------------------- +Having got the keyboard nicely set up the machine proceeds to +initialise a filing system and run a !BOOT file if one exists. The +start up options are already read from the keyboard links. + +DB8E PHP ;save flags +DB8F PLA ;and get back in A +DB90 LSR ;zero bits 4-7 and bits 0-2 bit 4 which was bit 7 +DB91 LSR ;may be set +DB92 LSR ; +DB93 LSR ; +DB94 EOR &028F ;EOR with start up options which may or may not +DB97 AND #&08 ;invert bit 4 +DB99 TAY ;Y=A +DB9A LDX #&03 ;make initialisation call, if Y=0 on entry +DB9C JSR &F168 ;RUN, EXEC or LOAD !BOOT file from a filing system. +DB9F BEQ &DBBE ;if a ROM accepts this call then DBBE +DBA1 TYA ;else put Y in A +DBA2 BNE &DBB8 ;if Y<>0 DBB8 +DBA4 LDA #&8D ;else set up standard cassette baud rates +DBA6 JSR &F135 ;via &F135 which is OSBYTE 140. +DBA9 LDX #&D2 ; +DBAB LDY #&EA ; +DBAD DEC &0267 ;decrement ignore start up message flag +DBB0 JSR OSCLI ;and execute /!BOOT +DBB3 INC &0267 ;restore start up message flag +DBB6 BNE &DBBE ;if not zero then DBBE +DBB8 LDA #&00 ;else A=0 +DBBA TAX ;X=0 +DBBB JSR &F137 ;set tape speed via OSBYTE 140. + +We now have an active filing system. The next job is to preserve the +current language on soft RESET. + +DBBE LDA &028D ;get last RESET Type +DBC1 BNE &DBC8 ;if not soft reset DBC8 +DBC3 LDX &028C ;else get current language ROM address +DBC6 BPL &DBE6 ;if +ve (language available) then skip search + ;routine +For a cold break we search for the language with the highest priority. + +DBC8 LDX #&0F ;set pointer to highest available ROM +DBCA LDA &02A1,X ;get ROM type from map +DBCD ROL ;put hi-bit into carry, bit 6 into bit 7 +DBCE BMI &DBE6 ;if bit 7 set then ROM has a language entry so DBE6 +DBD0 DEX ;else search for language until X=&ff + +Check for Tube if no language found. + +DBD1 BPL &DBCA ;check if tube present +DBD3 LDA #&00 ;if bit 7 of tube flag is set BMI succeeds +DBD5 BIT &027A ;and TUBE is connected else +DBD8 BMI &DC08 ;make error + +No language error + +DBDA BRK ; +DBDB DB &F9 ;error number +DBDC DB 'Language?' ;message +DBE5 BRK ; + +This might seem odd as BRK is handled by the current language BRK +handler, but we don't have a language! We need to investigate further +in another part. + +DBE6 CLC ; + +OSBYTE 142 enter Language ROM at &8000 X=ROM number. Carry is set if +this is an OSBYTE call and clear if this is an initialisation routine. + +DBE7 PHP ;save flags +DBE8 STX &028C ;put X in current ROM page +DBEB JSR &DC16 ;select that ROM +DBEE LDA #&80 ;A=128 +DBF0 LDY #&08 ;Y=8 +DBF2 JSR &DEAB ;display text string held in ROM at &8008,Y +DBF5 STY &FD ;save Y on exit (end of language string) +DBF7 JSR OSNEWL ;two line feeds +DBFA JSR OSNEWL ;are output +DBFD PLP ;then get back flags +DBFE LDA #&01 ;A=1 required for language entry +DC00 BIT &027A ;check if tube exists +DC03 BMI &DC08 ;and goto DC08 if it does +DC05 JMP &8000 ;else enter language at &8000 + +TUBE FOUND enter tube software + +DC08 JMP &0400 ;enter tube environment + +The Tube initialisation would have read the language across to the +TUBE usually but it could be loaded by a !BOOT file from the filing +system initialisation. + +The operating system now stops general control of the system and hands +this to the language which looks after command lines etc. The OS +however still handles the screen, keyboard and much else. + +Notice how every possible eventuality was taken into account during +the initialisation routine. This is one of the things that made the +Beeb a very powerful machine. + +Next week we'll have a look at the Interrupt code. + +BBC 6502 Machine Code +Part Twelve: Pardon me! +----------------------- +We finished the last part at the point where the operating systems +power up routine handed over control to the language. We'll write our +own language later in the series but for now let's dive into another +entry point. + +When the processor's IRQ pin (4) goes low (0V) the processor finishes +off the current instruction and then goes off to run some microcode of +its own. This checks that the RDY (2) pin is high and that the +interrupt flag in the status register is 0 (not set). If it is set the +interrupt is ignored and the processor goes to the next instruction. +This continues when the IRQ pin is low. + +If the flag is clear then the processor stores the program counter and +status register on the stack and sets the interrupt flag. The 6502 +then gets the address stored in &FFFE and &FFFF and executes this +instruction next. + +If a BRK instruction is found in executing code then the processor +performs exactly the same actions except that it does not check the +status register for the interrupt flag, it does set a flag in the +status register, the BRK flag. + +The main entry point for IRQ (and BRK) for OS 1.20 is &DC51. + +MAIN IRQ Entry point + +;ON ENTRY STACK contains STATUS REGISTER,PCH,PCL +DC1C STA &FC ;save A +DC1E PLA ;get back status (flags) +DC1F PHA ;and save again +DC20 AND #&10 ;check if BRK flag set +DC22 BNE &DC27 ;if so goto DC27 +DC24 JMP (&0204) ;else JUMP through IRQ1V + +That's pretty straightforward so far. As you can see IRQ1V allows you +to put your own hardware at a higher priority than anything else in +the machine. + +You can also write your own hardware interrupt handler if you wish. +This is the flexibility that made the BBC machine so remarkably +successful among knowledgeable users. + +Let's look at the BRK handler now. + +* BRK handling routine * +DC27 TXA ;save X on stack +DC28 PHA ; +DC29 TSX ;get status pointer +DC2A LDA &0103,X ;get Program Counter low byte +DC2D CLD ; +DC2E SEC ;set carry +DC2F SBC #&01 ;subtract 2 (1+carry) +DC31 STA &FD ;and store it in &FD +DC33 LDA &0104,X ;get hi byte +DC36 SBC #&00 ;subtract 1 if necessary +DC38 STA &FE ;and store in &FE +DC3A LDA &F4 ;get currently active ROM +DC3C STA &024A ;and store it in &24A +DC3F STX &F0 ;store stack pointer in &F0 +DC41 LDX #&06 ;and issue ROM service call 6 +DC43 JSR &F168 ;(User BRK) to ROMs + ;now &FD/E points to byte after BRK + ;ROMS may use BRK for their own purposes + ;and many do! + +It's interesting to see what happens with the ROM handler. This is +also an entry point for OSBYTE 143 so you can use this in your own +code. + +* OSBYTE 143 * +*Pass service commands to sideways ROMs * + ;on entry X=command number +F168 LDA &F4 ;get current ROM number +F16A PHA ;store it +F16B TXA ;command in A +F16C LDX #&0F ;set X=15 + ;send commands loop +F16E INC &02A1,X ;read bit 7 on ROM map (no ROM has + ;type 254 &FE) +F171 DEC &02A1,X ; +F174 BPL &F183 ;if not set (+ve result) +F176 STX &F4 ;else store ROM number in &F4 +F178 STX &FE30 ;switch in paged ROM +F17B JSR &8003 ;and jump to service entry +F17E TAX ;on exit put A in X +F17F BEQ &F186 ;if 0 (command recognised by ROM) + ;reset ROMs & exit +F181 LDX &F4 ;else point to next lower ROM +F183 DEX ; +F184 BPL &F16E ;and go round loop again +F186 PLA ;get back original ROM number +F187 STA &F4 ;store it in RAM copy +F189 STA &FE30 ;select original page +F18C TXA ;put X back in A +F18D RTS ;and return + +Useful little routine that. So back to the BRK handler. + +DC46 LDX &028C ;get current language +DC49 JSR &DC16 ;and activate it +DC4C PLA ;get back original value of X +DC4D TAX ; +DC4E LDA &FC ;get back original value of A +DC50 CLI ;allow interrupts +DC51 JMP (&0202) ;and JUMP via BRKV (normally into current language) + +Next week we'll carry on by taking a look at the BRK handler. + +BBC 6502 Machine Code +Part Thirteen: Give us a BRK +---------------------------- +BRK is usually handled by the default language (or by a Sideways ROM). +However, it may be that you are running a machine code program before +a current language is set up or perhaps your language doesn't handle +BRK (it should but you never know). + +That's when a default BRK handler takes over. + +* DEFAULT BRK HANDLER * + +DC54 LDY #&00 ;Y=0 to point to byte after BRK +DC56 JSR &DEB1 ;print message + +Let's have a look at the print routine. Remember that the error- +handling layout is: + +BRK +Error Number (1 byte) +Message +BRK + +Y plus the address in &FD &FE points to the error message on entry. + +DEB1 INY ;point to first ;character in string +DEB2 LDA (&FD),Y +DEB4 JSR OSASCI ;print it + ;expanding + ;Carriage + ;returns +DEB7 TAX ;store A in X to change flags +DEB8 BNE &DEB1 ;and loop again if not =0 +DEBA RTS ;else exit + +A standard print routine, nothing out of the ordinary but nice and +compact. + +You can use this in your own print routines by changing the zero page +values. Back to the default BRK handler and an interesting bit of +code. + +DC59 LDA &0267 ;if BIT 0 set and DISK EXEC error +DC5C ROR ;occurs +DC5D BCS &DC5D ;hang up machine! + +Nasty! But the machine has to be in a pretty unusual configuration for +this to happen. Mind you, setting 0267 then doing a JSR to DC59 would +confuse the average user. + +DC5F JSR OSNEWL ;else print two newlines +DC62 JSR OSNEWL ; +DC65 JMP &DBB8 ;and set tape speed before entering the current + ;language +DBB8 LDA #&00 ;else A=0 +DBBA TAX ;X=0 +DBBB JSR &F137 ;set tape speed via OSBYTE 141. + +There's the end of the BRK handling code. As I said before this is +generally handled by the default language but you can arrange for your +own code or a Sideways ROM to handle it. + +Next week we'll return to the interrupt system with a look at the +default entry point for IRQ1. + +BBC 6502 Machine Code +Part Fourteen: The story so far... +---------------------------------- +We left the interrupt-handling routine just after it had gone off to +the IRQ1V vector. If you don't change the vector the code continues +from DC93. + +One very important thing to remember about an interrupt-driven machine +like the BBC is that the interrupt flag is not set for too long. If it +is the machine could crash. This means that interrupt routines are +short and snappy. + +* Main IRQ Handling routines, default IRQIV destination * + +DC93 CLD ;clear decimal flag +DC94 LDA &FC ;get original value of A +DC96 PHA ;save it +DC97 TXA ;save X +DC98 PHA ; +DC99 TYA ;and Y +DC9A PHA ;on the stack + ;note the pre-CMOS code! +DC9B LDA #&DE ;A=&DE +DC9D PHA ;store it +DC9E LDA #&81 ;save &81 +DCA0 PHA ;store it (a RTS will now jump to DE82) + +This is quite a useful technique as we will see later. If we now use +JMP to go to an OS routine we can ensure that the routine, which ends +with an RTS, causes execution to go to a specified point. + +This saves a lot of code as it can be arranged that the first device +found that called the interrupt will be the only one handled. This, in +turn, saves time! + +We now poll the hardware looking for who caused it. The first routine +deals with the serial/tape system. + +DCA1 CLV ;clear V flag +DCA2 LDA &FE08 ;get value of status register of ACIA +DCA5 BVS &DCA9 ;if this was source then DCA9 to process +DCA7 BPL &DD06 ;else if no interrupt requested DD06 +DCA9 LDX &EA ;read RS423 timeout counter +DCAB DEX ;decrement it +DCAC BMI &DCDE ;and if <0 DCDE +DCAE BVS &DCDD ;else if >&40 DCDD (RTS to DE82) +DCB0 JMP &F588 ;else read ACIA via F588 + ;RTS ends routine!! +DCB3 LDY &FE09 ;read ACIA data +DCB6 ROL ; +DCB7 ASL ; +DCB8 TAX ;X=A +DCB9 TYA ;A=Y +DCBA LDY #&07 ;Y=07 +DCBC JMP &E494 ;check and service EVENT 7 RS423 error +DCBF LDX #&02 ;read RS423 output buffer +DCC1 JSR &E460 ; +DCC4 BCC &DCD6 ;if C=0 buffer is not empty goto DCD6 +DCC6 LDA &0285 ;else read printer destination +DCC9 CMP #&02 ;is it serial printer?? +DCCB BNE &DC68 ;if not DC68 +DCCD INX ;else X=3 +DCCE JSR &E460 ;read printer buffer +DCD1 ROR &02D2 ;rotate to pass carry into bit 7 +DCD4 BMI &DC68 ;if set then DC68 +DCD6 STA &FE09 ;pass either printer or RS423 data to ACIA +DCD9 LDA #&E7 ;set timeout counter to stored value +DCDB STA &EA ; +DCDD RTS ;and exit (to DE82) + + ;A contains ACIA status +DCDE AND &0278 ;AND with ACIA bit mask (normally FF) +DCE1 LSR ;rotate right to put bit 0 in carry +DCE2 BCC &DCEB ;if carry clear receive register not full so DCEB +DCE4 BVS &DCEB ;if V is set then DCEB +DCE6 LDY &0250 ;else Y=ACIA control setting +DCE9 BMI &DC7D ;if bit 7 set receive interrupt is enabled so DC7D + +DCEB LSR ;put BIT 2 of ACIA status into +DCEC ROR ;carry if set then Data Carrier Detected applies +DCED BCS &DCB3 ;jump to DCB3 + +DCEF BMI &DCBF ;if original bit 1 is set TDR is empty so DCBF +DCF1 BVS &DCDD ;if V is set then exit to DE82 + +DCF3 LDX #&05 ;X=5 +DCF5 JSR &F168 ;issue ROM call 5 'unrecognised ;interrupt' + +We've seen this ROM service routine call before. + +DCF8 BEQ &DCDD ;if a ROM recognises it then exit to DE82 +DCFA PLA ;otherwise get back DE82 address from stack +DCFB PLA ; +DCFC PLA ;and get back X, Y and A +DCFD TAY ; +DCFE PLA ; +DCFF TAX ; +DD00 PLA ; +DD01 STA &FC ;&FC=A +DD03 JMP (&0206) ;and offer to the user via IRQ2V + +That was a little convoluted, to say the least. Next week we look at how the +VIAs are dealt with. + +BBC 6502 Machine Code +Part Fifteen: Hardware VIA interrupts +------------------------------------- +After deciding that it wasn't the ACIA that caused the interrupt, the +VIAs are the next port of inquisition. + +* VIA INTERRUPTS ROUTINES * + +DD06 LDA &FE4D ;read system VIA interrupt flag register +DD09 BPL &DD47 ;if bit 7=0 the VIA has not caused interrupt goto DD47 + +DD0B AND &0279 ;mask with VIA bit mask +DD0E AND &FE4E ;and interrupt enable register +DD11 ROR ;rotate right twice to ;check for IRQ 1 (frame sync) + +DD12 ROR ; +DD13 BCC &DD69 ;if carry clear then no IRQ 1, else IRQ 1 means + ;interrupt request 1. This is different from the + ;vector IRQ1. + +DD15 DEC &0240 ;decrement vertical sync counter +DD18 LDA &EA ;A=RS423 Timeout counter +DD1A BPL &DD1E ;if +ve then DD1E +DD1C INC &EA ;else increment it +DD1E LDA &0251 ;load flash character counter +DD21 BEQ &DD3D ;if 0 then flash system is not in use, ignore it +DD23 DEC &0251 ;else decrement counter +DD26 BNE &DD3D ;and if not 0 go on past reset routine + +This routine resets the flashing character system. + +DD28 LDX &0252 ;get mark period count in X +DD2B LDA &0248 ;current VIDEO ULA control setting in A +DD2E LSR ;shift bit 0 into C to ;check if first colour +DD2F BCC &DD34 ;is effective if so C=0. Jump to DD34 +DD31 LDX &0253 ;else get space period count in X +DD34 ROL ;restore bit +DD35 EOR #&01 ;and invert it +DD37 JSR &EA00 ;then change colour + +DD3A STX &0251 ;&0251=X resetting the counter + +DD3D LDY #&04 ;Y=4 and call E494 to check and implement vertical +DD3F JSR &E494 ;sync event (4) if necessary +DD42 LDA #&02 ;A=2 +DD44 JMP &DE6E ;clear interrupt 1 and exit + +Remember the RTS routine last time? + +* PRINTER INTERRUPT USER VIA 1 * + +DD47 LDA &FE6D ;Check USER VIA interrupt flags register +DD4A BPL &DCF3 ;if +ve USER VIA did not call interrupt +DD4C AND &0277 ;else check for USER IRQ 1 printer interrupt. +DD4F AND &FE6E ; +DD52 ROR ; +DD53 ROR ; +DD54 BCC &DCF3 ;if bit 1=0 then no ;interrupt 1 so DCF3 +DD56 LDY &0285 ;else get printer type +DD59 DEY ;decrement +DD5A BNE &DCF3 ;if not parallel then :CF3 +DD5C LDA #&02 ;reset interrupt 1 flag +DD5E STA &FE6D ; +DD61 STA &FE6E ;disable interrupt 1 +DD64 LDX #&03 ;and output data to parallel printer +DD66 JMP &E13A ;and exit via RTS + +* SYSTEM INTERRUPT 5 Speech * + +DD69 ROL ;get bit 5 into bit 7 +DD6A ROL ; +DD6B ROL ; +DD6C ROL ; +DD6D BPL &DDCA ;if not set this is not ;a speech interrupt so DDCA +DD6F LDA #&20 ; +DD71 LDX #&00 ; +DD73 STA &FE4D ; +DD76 STX &FE49 ;and zero high byte of Timer t2 +DD79 LDX #&08 ;&FB=8 +DD7B STX &FB ; +DD7D JSR &E45B ;and examine buffer 8 +DD80 ROR &02D7 ;shift carry into bit 7 +DD83 BMI &DDC9 ;and if set buffer is empty so exit +DD85 TAY ;else Y=A +DD86 BEQ &DD8D ; +DD88 JSR &EE6D ;control speech chip +DD8B BMI &DDC9 ;if negative exit +DD8D JSR &E460 ;else get a byte from buffer +DD90 STA &F5 ;store it to indicate speech or file ROM +DD92 JSR &E460 ;get another byte +DD95 STA &F7 ;store it +DD97 JSR &E460 ;and another +DD9A STA &F6 ;giving address to be accessed in paged ROM +DD9C LDY &F5 ;Y=&F5 +DD9E BEQ &DDBB ;and if =0 then DDBB +DDA0 BPL &DDB8 ;else if +ve DDB8 +DDA2 BIT &F5 ;if bit 6 of F5 =1 (&F5)>&40 +DDA4 BVS &DDAB ;then DDAB +DDA6 JSR &EEBB ;else continue for more speech processing +DDA9 BVC &DDB2 ;if bit 6 clear then DDB2 +DDAB ASL &F6 ;else double address in &F6/7 +DDAD ROL &F7 ; +DDAF JSR &EE3B ;and call EE3B +DDB2 LDY &0261 ;get speech enable/disable flag into Y +DDB5 JMP &EE7F ;and JMP to EE7F + +DDB8 JSR &EE7F ;Call EE7F +DDBB LDY &F6 ;get address pointer in Y +DDBD JSR &EE7F ; +DDC0 LDY &F7 ;get address pointer high in Y +DDC2 JSR &EE7F ; +DDC5 LSR &FB ; +DDC7 BNE &DD7D ; +DDC9 RTS ;and exit + +Next week we continue with a look at the remaining System Interrupts. + +BBC 6502 Machine Code +Part Sixteen: Timers and Keyboard Interrupts +-------------------------------------------- +The last part showed how the BBC Micro handles some of the system +interrupt calls. Most of these are pretty routine so we won't continue +with an interminable list. + +The next interesting routines concern how the timers and keyboard +interrupts are handled. + +* SYSTEM INTERRUPT 6 10mS Clock * + +DDCA BCC &DE47 ;bit 6 is in carry so if clear there is no 6 so go + ;on to DE47 +DDCC LDA #&40 ;Clear interrupt 6 +DDCE STA &FE4D ; + +This is the start of the update timers routine, This is interesting +because of the way that the timer information is stored. It's very +clever. There are two timer stores, &292-6 and &297-B. These are +updated by adding 1 to the current timer and storing the result in the +other, the direction of transfer being changed each time of update. + +This ensures that at least one timer is valid at any call as the +current timer only is read. Other methods would cause inaccuracies if +a timer was read while being updated. + +DDD1 LDA &0283 ;get current system clock store pointer (5,or 10) +DDD4 TAX ;put A in X +DDD5 EOR #&0F ;and invert lo nybble (5becomes 10 and vv) +DDD7 PHA ;store A +DDD8 TAY ;put A in Y. Carry is always set at this point +DDD9 LDA &0291,X ;get timer value +DDDC ADC #&00 ;update it +DDDE STA &0291,Y ;store result in alternate +DDE1 DEX ;decrement X +DDE2 BEQ &DDE7 ;if 0 exit +DDE4 DEY ;else decrement Y +DDE5 BNE &DDD9 ;and go back and do next byte +DDE7 PLA ;get back A +DDE8 STA &0283 ;and store back in clock pointer (ie. inverse + ;previous contents) +DDEB LDX #&05 ;set loop pointer for countdown timer +DDED INC &029B,X ;increment byte and +DDF0 BNE &DDFA ;if not 0 then DDFA +DDF2 DEX ;else decrement pointer +DDF3 BNE &DDED ;and if not 0 do it again +DDF5 LDY #&05 ;process EVENT 5 interrupt timer +DDF7 JSR &E494 ; +DDFA LDA &02B1 ;get byte of inkey countdown timer +DDFD BNE &DE07 ;if not 0 then DE07 +DDFF LDA &02B2 ;else get next byte +DE02 BEQ &DE0A ;if 0 DE0A +DE04 DEC &02B2 ;decrement 2B2 +DE07 DEC &02B1 ;and 2B1 +DE0A BIT &02CE ;read bit 7 of envelope processing byte +DE0D BPL &DE1A ;if 0 then DE1A +DE0F INC &02CE ;else increment to 0 +DE12 CLI ;allow interrupts +DE13 JSR &EB47 ;and do routine sound processes +DE16 SEI ;bar interrupts +DE17 DEC &02CE ;DEC envelope processing byte back to 0 +DE1A BIT &02D7 ;read speech buffer busy flag +DE1D BMI &DE2B ;if set speech buffer is empty, skip routine +DE1F JSR &EE6D ;update speech system variables +DE22 EOR #&A0 ; +DE24 CMP #&60 ; +DE26 BCC &DE2B ;if result >=&60 DE2B +DE28 JSR &DD79 ;else more speech work +DE2B BIT &D9B7 ;set V and C +DE2E JSR &DCA2 ;check if ACIA needs attention +DE31 LDA &EC ;check if key has been pressed +DE33 ORA &ED ; +DE35 AND &0242 ;(this is 0 if keyboard is to be ignored, else + ;&FF) +DE38 BEQ &DE3E ;if 0 ignore keyboard +DE3A SEC ;else set carry +DE3B JSR &F065 ;and call keyboard +DE3E JSR &E19B ;check for data in use defined printer channel +DE41 BIT &FEC0 ;if ADC bit 6 is set ADC is not busy +DE44 BVS &DE4A ;so DE4A +DE46 RTS ;else return + +* SYSTEM INTERRUPT 4 ADC end of conversion * + +DE47 ROL ;put original bit 4 from FE4D into bit 7 of A +DE48 BPL &DE72 ;if not set DE72 +DE4A LDX &024C ;else get current ADC channel +DE4D BEQ &DE6C ;if 0 DE6C +DE4F LDA &FEC2 ;read low data byte +DE52 STA &02B5,X ;store it in &2B6,7,8 or 9 +DE55 LDA &FEC1 ;get high data byte +DE58 STA &02B9,X ;and store it in hi byte +DE5B STX &02BE ;store in Analogue system flag marking last channel +DE5E LDY #&03 ;handle event 3 conversion complete +DE60 JSR &E494 ; +DE63 DEX ;decrement X +DE64 BNE &DE69 ;if X=0 +DE66 LDX &024D ;get highest ADC channel present +DE69 JSR &DE8F ;and start new conversion +DE6C LDA #&10 ;reset interrupt 4 +DE6E STA &FE4D ; +DE71 RTS ;and return + +* SYSTEM INTERRUPT 0 Keyboard * + +DE72 ROL ;get original bit 0 in bit 7 position +DE73 ROL ; +DE74 ROL ; +DE75 ROL ; +DE76 BPL &DE7F ;if bit 7 clear not a keyboard interrupt +DE78 JSR &F065 ;else scan keyboard +DE7B LDA #&01 ;A=1 +DE7D BNE &DE6E ;and off to reset interrupt and exit +DE7F JMP &DCF3 ;and again a subroutine to exit. + +Now we come to the point you've all been waiting for. This mystery +RTSreturns all subroutines to &DE82. + +************** exit routine +DE82 PLA ;restore registers +DE83 TAY ; +DE84 PLA ; +DE85 TAX ; +DE86 PLA ; +DE87 STA &FC ;store A + +* IRQ2V default entry * + +DE89 LDA &FC ;get back original value of A +DE8B RTI ;and return to calling routine. + +NEXT WEEK: OSBYTE entry. + +BBC 6502 Machine Code +Part Seventeen: The BBC Operating System +---------------------------------------- +We've been examining the BBC operating system in some detail over the +last few weeks. Unfortunately the demise of Micronet means that we +cannot finish completely, as we hoped. So we've put together the next +twenty weeks' articles in the form of a completely commented +disassembly of OS 1.20. + +This is an excellent example of BBC programming and is full of tips. + +Just to remind you of the main points of the software. Entry points +are pointed to by a jump table in the last six bytes of the ROM. + +The font characters are located from &C000 to &C2FF. + +OK, so here it is all commented and ready for you to peruse. + +Ed says: I have uploaded the series of disassembly articles as ten + short TSW files. Look on Micronet on 700100239 (before it's + too late!) + + *********** THE END ********** + diff --git a/B/os/os.txt b/B/os/os.txt new file mode 100755 index 0000000..4df97da --- /dev/null +++ b/B/os/os.txt @@ -0,0 +1,12411 @@ +BBC Operating System OS 1.20 +============================ +Commented disassembly by Geoff Cox, originally published on Micronet. +Additional comments by J.G.Harston. + +***************** VDU CHARACTER FONT LOOK UP TABLE **************************** + +These are the default definitions for characters 32-127. The are accessed with +OSWORD 10 (read character definition) and reprogrammed with VDU 23 (define +character). If the character set is not exploded, then a block of 32 characters +is copied to the soft character buffer at &0C00 when a character is defined. + +C000 DB 00 ;00000000 ........ &20 32 - ' ' +C001 DB 00 ;00000000 ........ +C002 DB 00 ;00000000 ........ +C003 DB 00 ;00000000 ........ +C004 DB 00 ;00000000 ........ +C005 DB 00 ;00000000 ........ +C006 DB 00 ;00000000 ........ +C007 DB 00 ;00000000 ........ + +C008 DB 18 ;00011000 ...**... &21 33 - '!' +C009 DB 18 ;00011000 ...**... +C00A DB 18 ;00011000 ...**... +C00B DB 18 ;00011000 ...**... +C00C DB 18 ;00011000 ...**... +C00D DB 00 ;00000000 ........ +C00E DB 18 ;00011000 ...**... +C00F DB 00 ;00000000 ........ + +C010 DB 6C ;01101100 .**.**.. &22 34 - '"' +C011 DB 6C ;01101100 .**.**.. +C012 DB 6C ;01101100 .**.**.. +C013 DB 00 ;00000000 ........ +C014 DB 00 ;00000000 ........ +C015 DB 00 ;00000000 ........ +C016 DB 00 ;00000000 ........ +C017 DB 00 ;00000000 ........ + +C018 DB 36 ;00110110 ..**.**. &23 35 - '#' +C019 DB 36 ;00110110 ..**.**. +C01A DB 7F ;01111111 .******* +C01B DB 36 ;00110110 ..**.**. +C01C DB 7F ;01111111 .******* +C01D DB 36 ;00110110 ..**.**. +C01E DB 36 ;00110110 ..**.**. +C01F DB 00 ;00000000 ........ + +C020 DB 0C ;00001100 ....**.. &24 36 - '$' +C021 DB 3F ;00111111 ..****** +C022 DB 68 ;01101000 .**.*... +C023 DB 3E ;00111110 ..*****. +C024 DB 0B ;00001011 ....*.** +C025 DB 7E ;01111110 .******. +C026 DB 18 ;00011000 ...**... +C027 DB 00 ;00000000 ........ + +C028 DB 60 ;01100000 .**..... &25 37 - '%' +C029 DB 66 ;01100110 .**..**. +C02A DB 0C ;00001100 ....**.. +C02B DB 18 ;00011000 ...**... +C02C DB 30 ;00110000 ..**.... +C02D DB 66 ;01100110 .**..**. +C02E DB 06 ;00000110 .....**. +C02F DB 00 ;00000000 ........ + +C030 DB 38 ;00111000 ..***... &26 38 - '&' +C031 DB 6C ;01101100 .**.**.. +C032 DB 6C ;01101100 .**.**.. +C033 DB 38 ;00111000 ..***... +C034 DB 6D ;01101101 .**.**.* +C035 DB 66 ;01100110 .**..**. +C036 DB 3B ;00111011 ..***.** +C037 DB 00 ;00000000 ........ + +C038 DB 0C ;00001100 ....**.. &27 39 - ''' +C039 DB 18 ;00011000 ...**... +C03A DB 30 ;00110000 ..**.... +C03B DB 00 ;00000000 ........ +C03C DB 00 ;00000000 ........ +C03D DB 00 ;00000000 ........ +C03E DB 00 ;00000000 ........ +C03F DB 00 ;00000000 ........ + +C040 DB 0C ;00001100 ....**.. &28 40 - '(' +C041 DB 18 ;00011000 ...**... +C042 DB 30 ;00110000 ..**.... +C043 DB 30 ;00110000 ..**.... +C044 DB 30 ;00110000 ..**.... +C045 DB 18 ;00011000 ...**... +C046 DB 0C ;00001100 ....**.. +C047 DB 00 ;00000000 ........ + +C048 DB 30 ;00110000 ..**.... &29 41 - ')' +C049 DB 18 ;00011000 ...**... +C04A DB 0C ;00001100 ....**.. +C04B DB 0C ;00001100 ....**.. +C04C DB 0C ;00001100 ....**.. +C04D DB 18 ;00011000 ...**... +C04E DB 30 ;00110000 ..**.... +C04F DB 00 ;00000000 ........ + +C050 DB 00 ;00000000 ........ &2A 42 - '*' +C051 DB 18 ;00011000 ...**... +C052 DB 7E ;01111110 .******. +C053 DB 3C ;00111100 ..****.. +C054 DB 7E ;01111110 .******. +C055 DB 18 ;00011000 ...**... +C056 DB 00 ;00000000 ........ +C057 DB 00 ;00000000 ........ + +C058 DB 00 ;00000000 ........ &2B 43 - '+' +C059 DB 18 ;00011000 ...**... +C05A DB 18 ;00011000 ...**... +C05B DB 7E ;01111110 .******. +C05C DB 18 ;00011000 ...**... +C05D DB 18 ;00011000 ...**... +C05E DB 00 ;00000000 ........ +C05F DB 00 ;00000000 ........ + +C060 DB 00 ;00000000 ........ &2C 44 - ',' +C061 DB 00 ;00000000 ........ +C062 DB 00 ;00000000 ........ +C063 DB 00 ;00000000 ........ +C064 DB 00 ;00000000 ........ +C065 DB 18 ;00011000 ...**... +C066 DB 18 ;00011000 ...**... +C067 DB 30 ;00110000 ..**.... + +C068 DB 00 ;00000000 ........ &2D 45 - '-' +C069 DB 00 ;00000000 ........ +C06A DB 00 ;00000000 ........ +C06B DB 7E ;01111110 .******. +C06C DB 00 ;00000000 ........ +C06D DB 00 ;00000000 ........ +C06E DB 00 ;00000000 ........ +C06F DB 00 ;00000000 ........ + +C070 DB 00 ;00000000 ........ &2E 46 - '.' +C071 DB 00 ;00000000 ........ +C072 DB 00 ;00000000 ........ +C073 DB 00 ;00000000 ........ +C074 DB 00 ;00000000 ........ +C075 DB 18 ;00011000 ...**... +C076 DB 18 ;00011000 ...**... +C077 DB 00 ;00000000 ........ + +C078 DB 00 ;00000000 ........ &2F 47 - '/' +C079 DB 06 ;00000110 .....**. +C07A DB 0C ;00001100 ....**.. +C07B DB 18 ;00011000 ...**... +C07C DB 30 ;00110000 ..**.... +C07D DB 60 ;01100000 .**..... +C07E DB 00 ;00000000 ........ +C07F DB 00 ;00000000 ........ + +C080 DB 3C ;00111100 ..****.. &30 48 - '0' +C081 DB 66 ;01100110 .**..**. +C082 DB 6E ;01101110 .**.***. +C083 DB 7E ;01111110 .******. +C084 DB 76 ;01110110 .***.**. +C085 DB 66 ;01100110 .**..**. +C086 DB 3C ;00111100 ..****.. +C087 DB 00 ;00000000 ........ + +C088 DB 18 ;00011000 ...**... &31 49 - '1' +C089 DB 38 ;00111000 ..***... +C08A DB 18 ;00011000 ...**... +C08B DB 18 ;00011000 ...**... +C08C DB 18 ;00011000 ...**... +C08D DB 18 ;00011000 ...**... +C08E DB 7E ;01111110 .******. +C08F DB 00 ;00000000 ........ + +C090 DB 3C ;00111100 ..****.. &32 50 - '2' +C091 DB 66 ;01100110 .**..**. +C092 DB 06 ;00000110 .....**. +C093 DB 0C ;00001100 ....**.. +C094 DB 18 ;00011000 ...**... +C095 DB 30 ;00110000 ..**.... +C096 DB 7E ;01111110 .******. +C097 DB 00 ;00000000 ........ + +C098 DB 3C ;00111100 ..****.. &33 51 - '3' +C099 DB 66 ;01100110 .**..**. +C09A DB 06 ;00000110 .....**. +C09B DB 1C ;00011100 ...***.. +C09C DB 06 ;00000110 .....**. +C09D DB 66 ;01100110 .**..**. +C09E DB 3C ;00111100 ..****.. +C09F DB 00 ;00000000 ........ + +C0A0 DB 0C ;00001100 ....**.. &34 52 - '4' +C0A1 DB 1C ;00011100 ...***.. +C0A2 DB 3C ;00111100 ..****.. +C0A3 DB 6C ;01101100 .**.**.. +C0A4 DB 7E ;01111110 .******. +C0A5 DB 0C ;00001100 ....**.. +C0A6 DB 0C ;00001100 ....**.. +C0A7 DB 00 ;00000000 ........ + +C0A8 DB 7E ;01111110 .******. &35 53 - '5' +C0A9 DB 60 ;01100000 .**..... +C0AA DB 7C ;01111100 .*****.. +C0AB DB 06 ;00000110 .....**. +C0AC DB 06 ;00000110 .....**. +C0AD DB 66 ;01100110 .**..**. +C0AE DB 3C ;00111100 ..****.. +C0AF DB 00 ;00000000 ........ + +C0B0 DB 1C ;00011100 ...***.. &36 54 - '6' +C0B1 DB 30 ;00110000 ..**.... +C0B2 DB 60 ;01100000 .**..... +C0B3 DB 7C ;01111100 .*****.. +C0B4 DB 66 ;01100110 .**..**. +C0B5 DB 66 ;01100110 .**..**. +C0B6 DB 3C ;00111100 ..****.. +C0B7 DB 00 ;00000000 ........ + +C0B8 DB 7E ;01111110 .******. &37 55 - '7' +C0B9 DB 06 ;00000110 .....**. +C0BA DB 0C ;00001100 ....**.. +C0BB DB 18 ;00011000 ...**... +C0BC DB 30 ;00110000 ..**.... +C0BD DB 30 ;00110000 ..**.... +C0BE DB 30 ;00110000 ..**.... +C0BF DB 00 ;00000000 ........ + +C0C0 DB 3C ;00111100 ..****.. &38 56 - '8' +C0C1 DB 66 ;01100110 .**..**. +C0C2 DB 66 ;01100110 .**..**. +C0C3 DB 3C ;00111100 ..****.. +C0C4 DB 66 ;01100110 .**..**. +C0C5 DB 66 ;01100110 .**..**. +C0C6 DB 3C ;00111100 ..****.. +C0C7 DB 00 ;00000000 ........ + +C0C8 DB 3C ;00111100 ..****.. &39 57 - '9' +C0C9 DB 66 ;01100110 .**..**. +C0CA DB 66 ;01100110 .**..**. +C0CB DB 3E ;00111110 ..*****. +C0CC DB 06 ;00000110 .....**. +C0CD DB 0C ;00001100 ....**.. +C0CE DB 38 ;00111000 ..***... +C0CF DB 00 ;00000000 ........ + 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00 ;00000000 ........ + +C298 DB 00 ;00000000 ........ &73 115 - 's' +C299 DB 00 ;00000000 ........ +C29A DB 3E ;00111110 ..*****. +C29B DB 60 ;01100000 .**..... +C29C DB 3C ;00111100 ..****.. +C29D DB 06 ;00000110 .....**. +C29E DB 7C ;01111100 .*****.. +C29F DB 00 ;00000000 ........ + +C2A0 DB 30 ;00110000 ..**.... &74 116 - 't' +C2A1 DB 30 ;00110000 ..**.... +C2A2 DB 7C ;01111100 .*****.. +C2A3 DB 30 ;00110000 ..**.... +C2A4 DB 30 ;00110000 ..**.... +C2A5 DB 30 ;00110000 ..**.... +C2A6 DB 1C ;00011100 ...***.. +C2A7 DB 00 ;00000000 ........ + +C2A8 DB 00 ;00000000 ........ &75 117 - 'u' +C2A9 DB 00 ;00000000 ........ +C2AA DB 66 ;01100110 .**..**. +C2AB DB 66 ;01100110 .**..**. +C2AC DB 66 ;01100110 .**..**. +C2AD DB 66 ;01100110 .**..**. +C2AE DB 3E ;00111110 ..*****. +C2AF DB 00 ;00000000 ........ + +C2B0 DB 00 ;00000000 ........ &76 118 - 'v' +C2B1 DB 00 ;00000000 ........ +C2B2 DB 66 ;01100110 .**..**. +C2B3 DB 66 ;01100110 .**..**. +C2B4 DB 66 ;01100110 .**..**. +C2B5 DB 3C ;00111100 ..****.. +C2B6 DB 18 ;00011000 ...**... +C2B7 DB 00 ;00000000 ........ + +C2B8 DB 00 ;00000000 ........ &77 119 - 'w' +C2B9 DB 00 ;00000000 ........ +C2BA DB 63 ;01100011 .**...** +C2BB DB 6B ;01101011 .**.*.** +C2BC DB 6B ;01101011 .**.*.** +C2BD DB 7F ;01111111 .******* +C2BE DB 36 ;00110110 ..**.**. +C2BF DB 00 ;00000000 ........ + +C2C0 DB 00 ;00000000 ........ &78 120 - 'x' +C2C1 DB 00 ;00000000 ........ +C2C2 DB 66 ;01100110 .**..**. +C2C3 DB 3C ;00111100 ..****.. +C2C4 DB 18 ;00011000 ...**... +C2C5 DB 3C ;00111100 ..****.. +C2C6 DB 66 ;01100110 .**..**. +C2C7 DB 00 ;00000000 ........ + +C2C8 DB 00 ;00000000 ........ &79 121 - 'y' +C2C9 DB 00 ;00000000 ........ +C2CA DB 66 ;01100110 .**..**. +C2CB DB 66 ;01100110 .**..**. +C2CC DB 66 ;01100110 .**..**. +C2CD DB 3E ;00111110 ..*****. +C2CE DB 06 ;00000110 .....**. +C2CF DB 3C ;00111100 ..****.. + +C2D0 DB 00 ;00000000 ........ &7A 122 - 'z' +C2D1 DB 00 ;00000000 ........ +C2D2 DB 7E ;01111110 .******. +C2D3 DB 0C ;00001100 ....**.. +C2D4 DB 18 ;00011000 ...**... +C2D5 DB 30 ;00110000 ..**.... +C2D6 DB 7E ;01111110 .******. +C2D7 DB 00 ;00000000 ........ + +C2D8 DB 0C ;00001100 ....**.. &7B 123 - '{' +C2D9 DB 18 ;00011000 ...**... +C2DA DB 18 ;00011000 ...**... +C2DB DB 70 ;01110000 .***.... +C2DC DB 18 ;00011000 ...**... +C2DD DB 18 ;00011000 ...**... +C2DE DB 0C ;00001100 ....**.. +C2DF DB 00 ;00000000 ........ + +C2E0 DB 18 ;00011000 ...**... &7C 124 - '|' +C2E1 DB 18 ;00011000 ...**... +C2E2 DB 18 ;00011000 ...**... +C2E3 DB 00 ;00000000 ........ +C2E4 DB 18 ;00011000 ...**... +C2E5 DB 18 ;00011000 ...**... +C2E6 DB 18 ;00011000 ...**... +C2E7 DB 00 ;00000000 ........ + +C2E8 DB 30 ;00110000 ..**.... &7D 125 - '}' +C2E9 DB 18 ;00011000 ...**... +C2EA DB 18 ;00011000 ...**... +C2EB DB 0E ;00001110 ....***. +C2EC DB 18 ;00011000 ...**... +C2ED DB 18 ;00011000 ...**... +C2EE DB 30 ;00110000 ..**.... +C2EF DB 00 ;00000000 ........ + +C2F0 DB 31 ;00110001 ..**...* &7E 126 - '~' +C2F1 DB 6B ;01101011 .**.*.** +C2F2 DB 46 ;01000110 .*...**. +C2F3 DB 00 ;00000000 ........ +C2F4 DB 00 ;00000000 ........ +C2F5 DB 00 ;00000000 ........ +C2F6 DB 00 ;00000000 ........ +C2F7 DB 00 ;00000000 ........ + +C2F8 DB FF ;11111111 ******** &7F 127 - DEL +C2F9 DB FF ;11111111 ******** +C2FA DB FF ;11111111 ******** +C2FB DB FF ;11111111 ******** +C2FC DB FF ;11111111 ******** +C2FD DB FF ;11111111 ******** +C2FE DB FF ;11111111 ******** +C2FF DB FF ;11111111 ******** + +BBC Operation System OS 1.20 Startup Strings and Tables + +C300 JMP &CB1D ;Initialise screen with mode in A. + +C303 DB 13,'BBC Computer ',0 + +C312 DB '16K',7,0 + +C317 DB '32K',7,0 + +C31C DB 08,0D,0D ;Termination byte in next table + + +****** 16 COLOUR MODE BYTE MASK LOOK UP TABLE****** + +C31F DB 00 ;00000000 +C320 DB 11 ;00010001 +C321 DB 22 ;00100010 +C322 DB 33 ;00110011 +C323 DB 44 ;01000100 +C324 DB 55 ;01010101 +C325 DB 66 ;01100110 +C326 DB 77 ;01110111 +C327 DB 88 ;10001000 +C328 DB 99 ;10011001 +C329 DB AA ;10101010 +C32A DB BB ;10111011 +C32B DB CC ;11001100 +C32C DB DD ;11011101 +C32D DB EE ;11101110 +C32E DB FF ;11111111 + + +****** 4 COLOUR MODE BYTE MASK LOOK UP TABLE****** + +C32F DB 00 ;00000000 +C330 DB 55 ;01010101 +C331 DB AA ;10101010 +C332 DB FF ;11111111 + + +****** VDU ENTRY POINT LO LOOK UP TABLE****** + +C333 DB 11 ;00010001 +C334 DB 3B ;00111011 +C335 DB 96 ;10010110 +C336 DB A1 ;10100001 +C337 DB AD ;10101101 +C338 DB B9 ;10111001 +C339 DB 11 ;00010001 +C33A DB 6F ;01101111 +C33B DB C5 ;11000101 +C33C DB 64 ;01100100 +C33D DB F0 ;11110000 +C33E DB 5B ;01011011 +C33F DB 59 ;01011001 +C340 DB AF ;10101111 +C341 DB 8D ;10001101 +C342 DB A6 ;10100110 +C343 DB C0 ;11000000 +C344 DB F9 ;11111001 +C345 DB FD ;11111101 +C346 DB 92 ;10010010 +C347 DB 39 ;00111001 +C348 DB 9B ;10011011 +C349 DB EB ;11101011 +C34A DB F1 ;11110001 +C34B DB 39 ;00111001 +C34C DB 8C ;10001100 +C34D DB BD ;10111101 +C34E DB 11 ;00010001 +C34F DB FA ;11111010 +C350 DB A2 ;10100010 +C351 DB 79 ;01111001 +C352 DB 87 ;10000111 +C353 DB AC ;10101100 + + +****** VDU ENTRY POINT HI PARAMETER LOOK UP TABLE****** + +; 1xxxxxxx - no parameters, address high byte +; 0aaapppp - parameter count 16-p, address high byte &C3+a + +C354 DB C5 ;11000101 VDU 0 - &C511, no parameters +C355 DB 2F ;00101111 VDU 1 - &C53B, 1 parameter +C356 DB C5 ;11000101 VDU 2 - &C596, no parameters +C357 DB C5 ;11000101 VDU 3 - &C5A1, no parameters +C358 DB C5 ;11000101 VDU 4 - &C5AD, no parameters +C359 DB C5 ;11000101 VDU 5 - &C5B9, no parameters +C35A DB C5 ;11000101 VDU 6 - &C511, no parameters +C35B DB E8 ;11101000 VDU 7 - &E86F, no parameters +C35C DB C5 ;11000101 VDU 8 - &C5C5, no parameters +C35D DB C6 ;11000110 VDU 9 - &C664, no parameters +C35E DB C6 ;11000110 VDU 10 - &C6F0, no parameters +C35F DB C6 ;11000110 VDU 11 - &C65B, no parameters +C360 DB C7 ;11000111 VDU 12 - &C759, no parameters +C361 DB C7 ;11000111 VDU 13 - &C7AF, no parameters +C362 DB C5 ;11000101 VDU 14 - &C58D, no parameters +C363 DB C5 ;11000101 VDU 15 - &C5A6, no parameters +C364 DB C7 ;11000111 VDU 16 - &C7C0, no parameters +C365 DB 4F ;01001111 VDU 17 - &C7F9, 1 parameter +C366 DB 4E ;01001110 VDU 18 - &C7FD, 2 parameters +C367 DB 5B ;01011011 VDU 19 - &C892, 5 parameters +C368 DB C8 ;11001000 VDU 20 - &C839, no parameters +C369 DB C5 ;11000101 VDU 21 - &C59B, no parameters +C36A DB 5F ;01011111 VDU 22 - &C8EB, 1 parameter +C36B DB 57 ;01010111 VDU 23 - &C8F1, 9 parameters +C36C DB 78 ;01111000 VDU 24 - &CA39, 8 parameters +C36D DB 6B ;01101011 VDU 25 - &C9AC, 5 parameters +C36E DB C9 ;11001001 VDU 26 - &C9BD, no parameters +C36F DB C5 ;11000101 VDU 27 - &C511, no parameters +C370 DB 3C ;00111100 VDU 28 - &C6FA, 4 parameters +C371 DB 7C ;01111100 VDU 29 - &CAA2, 4 parameters +C372 DB C7 ;11000111 VDU 30 - &C779, no parameters +C373 DB 4E ;01001110 VDU 31 - &C787, 2 parameters +C374 DB CA ;11001010 VDU 127 - &CAAC, no parameters + + +****** 640 MULTIPLICATION TABLE 40COL, 80COL MODES HIBYTE, LOBYTE ****** + +C375 DW 0000 ; 0*640 = &0000 +C377 DW 8002 ; 1*640 = &0280 +C379 DW 0005 ; 2*640 = &0500 +C37B DW 8007 ; 3*640 = &0780 +C37D DW 000A ; 4* +C37F DW 800C ; 5* +C381 DW 000F ; 6* +C383 DW 8011 ; 7* +C385 DW 0014 ; 8* +C387 DW 8016 ; 9* +C389 DW 0019 ; 10* +C38B DW 801B ; 11* +C38D DW 001E ; 12* +C38F DW 8020 ; 13* +C391 DW 0023 ; 14* +C393 DW 8025 ; 15* +C395 DW 0028 ; 16* +C397 DW 802A ; 17* +C399 DW 002D ; 18* +C39B DW 802F ; 19* +C39D DW 0032 ; 20* +C39F DW 8034 ; 21* +C3A1 DW 0037 ; 22* +C3A3 DW 8039 ; 23* +C3A5 DW 003C ; 24* +C3A7 DW 803E ; 25* +C3A9 DW 0041 ; 26* +C3AB DW 8043 ; 27* +C3AD DW 0046 ; 28* +C3AF DW 8048 ; 29* +C3B1 DW 004B ; 30* +C3B3 DW 804D ; 31*640 = &4D80 + + +****** *40 MULTIPLICATION TABLE TELETEXT MODE HIBYTE, LOBYTE ****** + +C3B5 DW 0000 ; 0*40 = &0000 +C3B7 DW 2800 ; 1*40 = &0028 +C3B9 DW 5000 ; 2 +C3BB DW 7800 ; 3 +C3BD DW A000 ; 4 +C3BF DW C800 ; 5 +C3C1 DW F000 ; 6 +C3C3 DW 1801 ; 7 +C3C5 DW 4001 ; 8 +C3C7 DW 6801 ; 9 +C3C9 DW 9001 ; 10 +C3CB DW B801 ; 11 +C3CD DW E001 ; 12 +C3CF DW 0802 ; 13 +C3D1 DW 3002 ; 14 +C3D3 DW 5802 ; 15 +C3D5 DW 8002 ; 16 +C3D7 DW A802 ; 17 +C3D9 DW D002 ; 18 +C3DB DW F802 ; 19 +C3DD DW 2003 ; 20 +C3DF DW 4803 ; 21 +C3E1 DW 7003 ; 22 +C3E3 DW 9803 ; 23*40 = &0398 +C3E5 DW C003 ; 24*40 = &03C0 + + +****** TEXT WINDOW -BOTTOM ROW LOOK UP TABLE ****** + +C3E7 DB 1F ; MODE 0 - 32 ROWS +C3E8 DB 1F ; MODE 1 - 32 ROWS +C3E9 DB 1F ; MODE 2 - 32 ROWS +C3EA DB 18 ; MODE 3 - 25 ROWS +C3EB DB 1F ; MODE 4 - 32 ROWS +C3EC DB 1F ; MODE 5 - 32 ROWS +C3ED DB 18 ; MODE 6 - 25 ROWS +C3EE DB 18 ; MODE 7 - 25 ROWS + + +****** TEXT WINDOW -RIGHT HAND COLUMN LOOK UP TABLE ****** + +C3EF DB 4F ; MODE 0 - 80 COLUMNS +C3F0 DB 27 ; MODE 1 - 40 COLUMNS +C3F1 DB 13 ; MODE 2 - 20 COLUMNS +C3F2 DB 4F ; MODE 3 - 80 COLUMNS +C3F3 DB 27 ; MODE 4 - 40 COLUMNS +C3F4 DB 13 ; MODE 5 - 20 COLUMNS +C3F5 DB 27 ; MODE 6 - 40 COLUMNS +C3F6 DB 27 ; MODE 7 - 40 COLUMNS + + +************************************************************************* +* * +* SEVERAL OF THE FOLLOWING TABLES OVERLAP EACH OTHER * +* SOME ARE DUAL PURPOSE * +* * +************************************************************************* + +************** VIDEO ULA CONTROL REGISTER SETTINGS *********************** + +C3F7 DB 9C ;10011100 +C3F8 DB D8 ;11011000 +C3F9 DB F4 ;11110100 +C3FA DB 9C ;10011100 +C3FB DB 88 ;10001000 +C3FC DB C4 ;11000100 +C3FD DB 88 ;10001000 +C3FE DB 4B ;01001011 + + +******** NUMBER OF BYTES PER CHARACTER FOR EACH DISPLAY MODE ************ + +C3FF DB 08 ;00001000 +C400 DB 10 ;00010000 +C401 DB 20 ;00100000 +C402 DB 08 ;00001000 +C403 DB 08 ;00001000 +C404 DB 10 ;00010000 +C405 DB 08 ;00001000 +C406 DB 01 ;00000001 + + +******************* MASK TABLE FOR 2 COLOUR MODES ********************** + +C407 DB AA ;10101010 +C408 DB 55 ;01010101 + + +****************** MASK TABLE FOR 4 COLOUR MODES *********************** + +C409 DB 88 ;10001000 +C40A DB 44 ;01000100 +C40B DB 22 ;00100010 +C40C DB 11 ;00010001 + + +********** MASK TABLE FOR 4 COLOUR MODES FONT FLAG MASK TABLE ********** + +C40D DB 80 ;10000000 +C40E DB 40 ;01000000 +C40F DB 20 ;00100000 +C410 DB 10 ;00010000 +C411 DB 08 ;00001000 +C412 DB 04 ;00000100 +C413 DB 02 ;00000010 - NEXT BYTE IN FOLLOWING TABLE + + +********* NUMBER OF TEXT COLOURS -1 FOR EACH MODE ************************ + +C414 DB 01 ; MODE 0 - 2 COLOURS +C415 DB 03 ; MODE 1 - 4 COLOURS +C416 DB 0F ; MODE 2 - 16 COLOURS +C417 DB 01 ; MODE 3 - 2 COLOURS +C418 DB 01 ; MODE 4 - 2 COLOURS +C419 DB 03 ; MODE 5 - 4 COLOURS +C41A DB 01 ; MODE 6 - 2 COLOURS +C41B DB 00 ; MODE 7 - 1 'COLOUR' + + +************** GCOL PLOT OPTIONS PROCESSING LOOK UP TABLE *************** + +C41C DB FF ;11111111 +C41D DB 00 ;00000000 +C41E DB 00 ;00000000 +C41F DB FF ;11111111 +C420 DB FF ;11111111 +C421 DB FF ;11111111 +C422 DB FF ;11111111 +C423 DB 00 ;00000000 + + +********** 2 COLOUR MODES PARAMETER LOOK UP TABLE WITHIN TABLE ********** + +C424 DB 00 ;00000000 +C425 DB FF ;11111111 + + +*************** 4 COLOUR MODES PARAMETER LOOK UP TABLE ****************** + +C426 DB 00 ;00000000 +C427 DB 0F ;00001111 +C428 DB F0 ;11110000 +C429 DB FF ;11111111 + + +***************16 COLOUR MODES PARAMETER LOOK UP TABLE ****************** + +C42A DB 00 ;00000000 +C42B DB 03 ;00000011 +C42C DB 0C ;00001100 +C42D DB 0F ;00001111 +C42E DB 30 ;00110000 +C42F DB 33 ;00110011 +C430 DB 3C ;00111100 +C431 DB 3F ;00111111 +C432 DB C0 ;11000000 +C433 DB C3 ;11000011 +C434 DB CC ;11001100 +C435 DB CF ;11001111 +C436 DB F0 ;11110000 +C437 DB F3 ;11110011 +C438 DB FC ;11111100 +C439 DB FF ;11111111 + + +********** DISPLAY MODE PIXELS/BYTE-1 TABLE ********************* + +C43A DB 07 ; MODE 0 - 8 PIXELS/BYTE +C43B DB 03 ; MODE 1 - 4 PIXELS/BYTE +C43C DB 01 ; MODE 2 - 2 PIXELS/BYTE +C43D DB 00 ; MODE 3 - 1 PIXEL/BYTE (NON-GRAPHICS) +C43E DB 07 ; MODE 4 - 8 PIXELS/BYTE +C43F DB 03 ; MODE 5 - 4 PIXELS/BYTE + +********* SCREEN DISPLAY MEMORY TYPE TABLE OVERLAPS ************ + +C440 DB 00 ; MODE 6 - 1 PIXEL/BYTE // MODE 0 - TYPE 0 + +***** SOUND PITCH OFFSET BY CHANNEL TABLE WITHIN TABLE ********** + +C441 DB 00 ; MODE 7 - 1 PIXEL/BYTE // MODE 1 - TYPE 0 // CHANNEL 0 +C442 DB 00 ; // MODE 2 - TYPE 0 // CHANNEL 1 +C443 DB 01 ; // MODE 3 - TYPE 1 // CHANNEL 2 +C444 DB 02 ; // MODE 4 - TYPE 2 // CHANNEL 3 + +**** REST OF DISPLAY MEMORY TYPE TABLE **** + +C445 DB 02 ; // MODE 5 - TYPE 2 +C446 DB 03 ; // MODE 6 - TYPE 3 + +***************** VDU SECTION CONTROL NUMBERS *************************** + +C447 DB 04 ;00000100 // MODE 7 - TYPE 4 +C448 DB 00 ;00000000 +C449 DB 06 ;00000110 +C44A DB 02 ;00000010 + +*********** CRTC SETUP PARAMETERS TABLE 1 WITHIN TABLE ****************** + +C44B DB 0D ;00001101 +C44C DB 05 ;00000101 +C44D DB 0D ;00001101 +C44E DB 05 ;00000101 + +*********** CRTC SETUP PARAMETERS TABLE 2 WITHIN TABLE ***************** + +C44F DB 04 ;00000100 +C450 DB 04 ;00000100 +C451 DB 0C ;00001100 +C452 DB 0C ;00001100 +C453 DB 04 ;00000100 + +**** REST OF VDU SECTION CONTROL NUMBERS **** + +C454 DB 02 ;00000010 +C455 DB 32 ;00110010 +C456 DB 7A ;01111010 +C457 DB 92 ;10010010 +C458 DB E6 ;11100110 + + +************** MSB OF MEMORY OCCUPIED BY SCREEN BUFFER ***************** + +C459 DB 50 ; Type 0: &5000 - 20K +C45A DB 40 ; Type 1: &4000 - 16K +C45B DB 28 ; Type 2: &2800 - 10K +C45C DB 20 ; Type 3: &2000 - 8K +C45D DB 04 ; Type 4: &0400 - 1K + + +************ MSB OF FIRST LOCATION OCCUPIED BY SCREEN BUFFER ************ + +C45E DB 30 ; Type 0: &3000 +C45F DB 40 ; Type 1: &4000 +C460 DB 58 ; Type 2: &5800 +C461 DB 60 ; Type 3: &6000 +C462 DB 7C ; Type 4: &7C00 + + +***************** NUMBER OF BYTES PER ROW ******************************* + +C463 DB 28 ;00101000 +C464 DB 40 ;01000000 +C465 DB 80 ;10000000 + + +******** ROW MULTIPLIACTION TABLE POINTER TO LOOK UP TABLE ************** + +C466 DB B5 ;10110101 +C467 DB 75 ;01110101 +C468 DB 75 ;01110101 + + +********** CRTC CURSOR END REGISTER SETTING LOOK UP TABLE *************** + +C469 DB 0B ;00001011 +C46A DB 17 ;00010111 +C46B DB 23 ;00100011 +C46C DB 2F ;00101111 +C46D DB 3B ;00111011 + + +************* 6845 REGISTERS 0-11 FOR SCREEN TYPE 0 - MODES 0-2 ********* + +C46E DB 7F ; 0 Horizontal Total =128 +C46F DB 50 ; 1 Horizontal Displayed =80 +C470 DB 62 ; 2 Horizontal Sync =&62 +C471 DB 28 ; 3 HSync Width+VSync =&28 VSync=2, HSync Width=8 +C472 DB 26 ; 4 Vertical Total =38 +C473 DB 00 ; 5 Vertial Adjust =0 +C474 DB 20 ; 6 Vertical Displayed =32 +C475 DB 22 ; 7 VSync Position =&22 +C476 DB 01 ; 8 Interlace+Cursor =&01 Cursor=0, Display=0, Interlace=Sync +C477 DB 07 ; 9 Scan Lines/Character =8 +C478 DB 67 ;10 Cursor Start Line =&67 Blink=On, Speed=1/32, Line=7 +C479 DB 08 ;11 Cursor End Line =8 + + +************* 6845 REGISTERS 0-11 FOR SCREEN TYPE 1 - MODE 3 ************ + +C47A DB 7F ; 0 Horizontal Total =128 +C47B DB 50 ; 1 Horizontal Displayed =80 +C47C DB 62 ; 2 Horizontal Sync =&62 +C47D DB 28 ; 3 HSync Width+VSync =&28 VSync=2, HSync=8 +C47E DB 1E ; 4 Vertical Total =30 +C47F DB 02 ; 5 Vertical Adjust =2 +C480 DB 19 ; 6 Vertical Displayed =25 +C481 DB 1B ; 7 VSync Position =&1B +C482 DB 01 ; 8 Interlace+Cursor =&01 Cursor=0, Display=0, Interlace=Sync +C483 DB 09 ; 9 Scan Lines/Character =10 +C484 DB 67 ;10 Cursor Start Line =&67 Blink=On, Speed=1/32, Line=7 +C485 DB 09 ;11 Cursor End Line =9 + + +************ 6845 REGISTERS 0-11 FOR SCREEN TYPE 2 - MODES 4-5 ********** + +C486 DB 3F ; 0 Horizontal Total =64 +C487 DB 28 ; 1 Horizontal Displayed =40 +C488 DB 31 ; 2 Horizontal Sync =&31 +C489 DB 24 ; 3 HSync Width+VSync =&24 VSync=2, HSync=4 +C48A DB 26 ; 4 Vertical Total =38 +C48B DB 00 ; 5 Vertical Adjust =0 +C48C DB 20 ; 6 Vertical Displayed =32 +C48D DB 22 ; 7 VSync Position =&22 +C48E DB 01 ; 8 Interlace+Cursor =&01 Cursor=0, Display=0, Interlace=Sync +C48F DB 07 ; 9 Scan Lines/Character =8 +C490 DB 67 ;10 Cursor Start Line =&67 Blink=On, Speed=1/32, Line=7 +C491 DB 08 ;11 Cursor End Line =8 + + +********** 6845 REGISTERS 0-11 FOR SCREEN TYPE 3 - MODE 6 *************** + +C492 DB 3F ; 0 Horizontal Total =64 +C493 DB 28 ; 1 Horizontal Displayed =40 +C494 DB 31 ; 2 Horizontal Sync =&31 +C495 DB 24 ; 3 HSync Width+VSync =&24 VSync=2, HSync=4 +C496 DB 1E ; 4 Vertical Total =30 +C497 DB 02 ; 5 Vertical Adjust =0 +C498 DB 19 ; 6 Vertical Displayed =25 +C499 DB 1B ; 7 VSync Position =&1B +C49A DB 01 ; 8 Interlace+Cursor =&01 Cursor=0, Display=0, Interlace=Sync +C49B DB 09 ; 9 Scan Lines/Character =10 +C49C DB 67 ;10 Cursor Start Line =&67 Blink=On, Speed=1/32, Line=7 +C49D DB 09 ;11 Cursor End Line =9 + + +********* 6845 REGISTERS 0-11 FOR SCREEN TYPE 4 - MODE 7 **************** + +C49E DB 3F ; 0 Horizontal Total =64 +C49F DB 28 ; 1 Horizontal Displayed =40 +C4A0 DB 33 ; 2 Horizontal Sync =&33 Note: &31 is a better value +C4A1 DB 24 ; 3 HSync Width+VSync =&24 VSync=2, HSync=4 +C4A2 DB 1E ; 4 Vertical Total =30 +C4A3 DB 02 ; 5 Vertical Adjust =2 +C4A4 DB 19 ; 6 Vertical Displayed =25 +C4A5 DB 1B ; 7 VSync Position =&1B +C4A6 DB 93 ; 8 Interlace+Cursor =&93 Cursor=2, Display=1, Interlace=Sync+Video +C4A7 DB 12 ; 9 Scan Lines/Character =19 +C4A8 DB 72 ;10 Cursor Start Line =&72 Blink=On, Speed=1/32, Line=18 +C4A9 DB 13 ;11 Cursor End Line =19 + + +************* VDU ROUTINE VECTOR ADDRESSES ****************************** + +C4AA DB 86 ;10000110 +C4AB DB D3 ;11010011 +C4AC DB 7E ;01111110 +C4AD DB D3 ;11010011 + + +************ VDU ROUTINE BRANCH VECTOR ADDRESS LO *********************** + +C4AE DB 6A ;01101010 +C4AF DB 74 ;01110100 +C4B0 DB 42 ;01000010 +C4B1 DB 4B ;01001011 + + +************ VDU ROUTINE BRANCH VECTOR ADDRESS HI *********************** + +C4B2 DB D3 ;11010011 +C4B3 DB D3 ;11010011 +C4B4 DB D3 ;11010011 +C4B5 DB D3 ;11010011 + + +*********** TELETEXT CHARACTER CONVERSION TABLE ************************ + +C4B6 DB 23 ; '#' -> '_' +C4B7 DB 5F ; '_' -> '`' +C4B8 DB 60 ; '`' -> '#' +C4B9 DB 23 ; '#' + + +*********** SOFT CHARACTER RAM ALLOCATION ***************************** + +C4BA DB 04 ; &20-&3F - OSHWM+&0400 +C4BB DB 05 ; &40-&5F - OSHWM+&0500 +C4BC DB 06 ; &60-&7F - OSHWM+&0600 +C4BD DB 00 ; &80-&9F - OSHWM+&0000 +C4BE DB 01 ; &A0-&BF - OSHWM+&0100 +C4BF DB 02 ; &C0-&DF - OSHWM+&0200 + +************************************************************************* +* * +* VDU FUNCTION ADDRESSES * +* * +************************************************************************* + + ; VDU Address Parameters function + + ; 0 &C511 0 does nothing + ; 1 &C53B 1 next character to printer only + ; 2 &C596 0 enable printer + ; 3 &C5A1 0 disable printer + ; 4 &C5AD 0 select text cursor + ; 5 &C5B9 0 select graphics cursor + ; 6 &C511 0 enable display + ; 7 &E86F 0 bell + ; 8 &C5C5 0 cursor left + ; 9 &C664 0 cursor right + ; 10 &C6F0 0 cursor down + ; 11 &C65B 0 cursor up + ; 12 &C759 0 clear text window + ; 13 &C7AF 0 newline + ; 14 &C58D 0 select paged mode + ; 15 &C5A6 0 cancel paged mode + ; 16 &C7C0 0 clear graphics screen + ; 17 &C7F9 1 define text colour + ; 18 &C7FD 2 define graphics colour + ; 19 &C892 5 define logical colour + ; 20 &C839 0 restore default colours + ; 21 &C59B 0 disable display + ; 22 &C8EB 1 select screen MODE + ; 23 &C8F1 9 define character + ; 24 &CA39 8 define graphics window + ; 25 &C98C 5 PLOT + ; 26 &C9BD 0 set default windows + ; 27 &C511 0 ESCAPE (does nothing) + ; 28 &C6FA 4 define text window + ; 29 &CAA2 4 define graphics origin + ; 30 &C779 0 home cursor + ; 31 &C787 2 position text cursor (TAB) + ;127 &CAAC 0 delete + +************************************************************************* +* * +* VDU Variables * +* * +************************************************************************* + + ;D0 VDU status + ;Bit 0 printer output enabled + ; 1 scrolling disabled + ; 2 paged scrolling enabled + ; 3 software scrolling selected + ; 4 not used + ; 5 printing at graphics cursor enabled + ; 6 cursor editing mode enabled + ; 7 screen disabled + + ;D1 byte mask for current graphics point + ;D2/3 text colour bytes to be ORed and EORed into memory + ;D4/5 graphics colour bytes to be ORed and EORed into memory + ;D6/7 address of top line of current graphics cell + ;D8/9 address of top scan line of current text character + ;DA/F temporary workspace + ;E0/1 CRTC row multiplication table pointer + + + ;246 Character definition explosion switch + + ;248 current video ULA control regiter setting + ;249 current pallette setting + + ;251 flash counter + ;252 mark-space count + ;253 space period count + + ;256 EXEC file handle + ;257 SPOOL file handle + + ;260 Econet OSWRCH interception flag + ;267 bit 7 set ignore start up message + ;268 length of key string + ;269 print line counter + ;26A number of items in VDU queque + ;26B TAB key value + ;26C ESCAPE character + + ;27D cursor editing status + + ;28F start up options (Keyboard links) + bits 0-2 default screen Mode + 3 reverse SHIFT/BREAK + 4-5 disc timing parameters + ;290 screen display vertical adjustment + ;291 interlace toggle flag + + ;300/1 graphics window left + ;302/3 graphics window bottom + ;304/5 graphics window right + ;306/7 graphics window top + ;308 text window left + ;309 text window bottom + ;30A text window right + ;30B text window top + ;30C/D graphics origin, horizontal (external values) + ;30E/F graphics origin, vertical (external values) + + ;310/1 current graphics cursor, horizontal (external values) + ;312/3 current graphics cursor, vertical (external values) + ;314/5 last graphics cursor, horizontal (external values) + ;316/7 last graphics cursor, vertical (external values) + ;318 text column + ;319 text line + ;31A graphics scan line expressed as line of character + ;31B-323 VDU parameters, last parameter in &323 + ;324/5 current graphics cursor, horizontal (internal values) + ;316/7 current graphics cursor, vertical (internal values) + ;328-349 general workspace + ;34A/B text cursor address to CRT controller + ;34C/D width of text window in bytes + ;34E hi byte of address of screen RAM start + ;34F bytes per character + ;350/1 address of window area start + ;352/3 bytes per character row + ;354 high byte of screen RAM size + ;355 Mode + ;356 memory map type + ;357/35A current colours + ;35B/C graphics plot mode + ;35D/E jump vector + ;35F last setting of CRTC Cursor start register + ;360 number of logical colours less 1 + ;361 pixels per byte (0 in text only modes) + ;362/3 colour masks + ;364/5 X/Y for text input cursor + ;366 output cursor character for MODE 7 + ;367 Font flag + ;368/E font location bytes + ;36F-37E Colour palette +BBC Operation System OS 1.20 VDU Main Routines + +************************************************************************** +************************************************************************** +** ** +** OSWRCH MAIN ROUTINE entry from E0C5 ** +** ** +** output a byte via the VDU stream ** +** ** +************************************************************************** +************************************************************************** +;This routine takes up over 40% of the operating system ROM +;Entry points are variable, as are the results achieved. +;Tracing any particular path is relatively easy but generalising for +;commenting is not. For clarity comments will not be as detailed as +;for later parts of the Operating System. + +C4C0 LDX &026A ;get number of items in VDU queue +C4C3 BNE &C512 ;if parameters needed then C512 +C4C5 BIT &D0 ;else check status byte +C4C7 BVC &C4D8 ;if cursor editing enabled two cursors exist +C4C9 JSR &C568 ;swap values +C4CC JSR &CD6A ;then set up write cursor +C4CF BMI &C4D8 ;if display disabled C4D8 +C4D1 CMP #&0D ;else if character in A=RETURN teminate edit +C4D3 BNE &C4D8 ;else C4D8 + +C4D5 JSR &D918 ;terminate edit + +C4D8 CMP #&7F ;is character DELETE ? +C4DA BEQ &C4ED ;if so C4ED + +C4DC CMP #&20 ;is it less than space? (i.e. VDU control code) +C4DE BCC &C4EF ;if so C4EF +C4E0 BIT &D0 ;else check VDU byte ahain +C4E2 BMI &C4EA ;if screen disabled C4EA +C4E4 JSR &CFB7 ;else display a character +C4E7 JSR &C664 ;and cursor right +C4EA JMP &C55E ; + +********* read link addresses and number of parameters ***************** + +C4ED LDA #&20 ;to replace delete character + +********* read link addresses and number of parameters ***************** + +C4EF TAY ;Y=A +C4F0 LDA &C333,Y ;get lo byte of link address +C4F3 STA &035D ;store it in jump vector +C4F6 LDA &C354,Y ;get hi byte +C4F9 BMI &C545 ;if negative (as it will be if a direct address) + ;there are no parameters needed + ;so C545 +C4FB TAX ;else X=A +C4FC ORA #&F0 ;set up negated parameter count +C4FE STA &026A ;store it as number of items in VDU queue +C501 TXA ;get back A +C502 LSR ;A=A/16 +C503 LSR ; +C504 LSR ; +C505 LSR ; +C506 CLC ;clear carry +C507 ADC #&C3 ;add &C3 to get hi byte of link address +C509 STA &035E ; +C50C BIT &D0 ;check if cursor editing enabled +C50E BVS &C52F ;if so re-exchange pointers +C510 CLC ;clear carry +C511 RTS ;and exit + +;return with carry clear indicates that printer action not required. +; +********** parameters are outstanding *********************************** +X=&26A = 2 complement of number of parameters X=&FF for 1, FE for 2 etc. + +C512 STA &0224,X ;store parameter in queue +C515 INX ;increment X +C516 STX &026A ;store it as VDU queue +C519 BNE &C532 ;if not 0 C532 as more parameters are needed +C51B BIT &D0 ;get VDU status byte +C51D BMI &C534 ;if screen disabled C534 +C51F BVS &C526 ;else if cursor editing C526 +C521 JSR &CCF5 ;execute required function +C524 CLC ;clear carry +C525 RTS ;and exit +; +C526 JSR &C568 ;swap values of cursors +C529 JSR &CD6A ;set up write cursor +C52C JSR &CCF5 ;execute required function +C52F JSR &C565 ;re-exchange pointers + +C532 CLC ;carry clear +C533 RTS ;exit + +************************************************************************* +* * +* VDU 1 - SEND NEXT CHARACTER TO PRINTER * +* * +* 1 parameter required * +* * +************************************************************************* +; +C534 LDY &035E ;if upper byte of link address not &C5 +C537 CPY #&C5 ;printer is not interested +C539 BNE &C532 ;so C532 +C53B TAX ;else X=A +C53C LDA &D0 ;A=VDU status byte +C53E LSR ;get bit 0 into carry +C53F BCC &C511 ;if printer not enabled exit +C541 TXA ;restore A +C542 JMP &E11E ;else send byte in A (next byte) to printer + +*********** if explicit link address found, no parameters *************** + +C545 STA &035E ;upper byte of link address +C548 TYA ;restore A +C549 CMP #&08 ;is it 7 or less? +C54B BCC &C553 ;if so C553 +C54D EOR #&FF ;invert it +C54F CMP #&F2 ;c is set if A >&0D +C551 EOR #&FF ;re invert + +C553 BIT &D0 ;VDU status byte +C555 BMI &C580 ;if display disabled C580 +C557 PHP ;push processor flags +C558 JSR &CCF5 ;execute required function +C55B PLP ;get back flags +C55C BCC &C561 ;if carry clear (from C54B/F) + +**************** main exit routine ************************************** + +C55E LDA &D0 ;VDU status byte +C560 LSR ;Carry is set if printer is enabled +C561 BIT &D0 ;VDU status byte +C563 BVC &C511 ;if no cursor editing C511 to exit + +***************** cursor editing routines ******************************* + +C565 JSR &CD7A ;restore normal write cursor + +C568 PHP ;save flags and +C569 PHA ;A +C56A LDX #&18 ;X=&18 +C56C LDY #&64 ;Y=&64 +C56E JSR &CDDE ;exchange &300/1+X with &300/1+Y +C571 JSR &CF06 ;set up display address +C574 JSR &CA02 ;set cursor position +C577 LDA &D0 ;VDU status byte +C579 EOR #&02 ;invert bit 1 to allow or bar scrolling +C57B STA &D0 ;VDU status byte +C57D PLA ;restore flags and A +C57E PLP ; +C57F RTS ;and exit +; +C580 EOR #&06 ;if A<>6 +C582 BNE &C58C ;return via C58C +C584 LDA #&7F ;A=&7F +C586 BCC &C5A8 ;and goto C5A8 ALWAYS!! + +******************* check text cursor in use *************************** + +C588 LDA &D0 ;VDU status byte +C58A AND #&20 ;set A from bit 5 of status byte +C58C RTS ;and exit + +A=0 if text cursor, &20 if graphics + +************************************************************************* +* * +* VDU 14 - SET PAGED MODE * +* * +************************************************************************* +; +C58D LDY #&00 ;Y=0 +C58F STY &0269 ;paged mode counter +C592 LDA #&04 ;A=04 +C594 BNE &C59D ;jump to C59D + +************************************************************************* +* * +* VDU 2 - PRINTER ON (START PRINT JOB) * +* * +************************************************************************* + +C596 JSR &E1A2 ;select printer buffer and output character +C599 LDA #&94 ;A=&94 + ;when inverted at C59B this becomes =&01 + +************************************************************************* +* * +* VDU 21 - DISABLE DISPLAY * +* * +************************************************************************* + +C59B EOR #&95 ;if A=&15 A now =&80: if A=&94 A now =1 + +C59D ORA &D0 ;VDU status byte set bit 0 or bit 7 +C59F BNE &C5AA ;branch forward to store + + + +************************************************************************* +* * +* VDU 3 - PRINTER OFF (END PRINT JOB) * +* * +************************************************************************* + +C5A1 JSR &E1A2 ;select printer buffer and output character +C5A4 LDA #&0A ;A=10 to clear status bits below... + +************************************************************************* +* * +* VDU 15 - PAGED MODE OFF * +* * +************************************************************************* +; A=&F or &A + +C5A6 EOR #&F4 ;convert to &FB or &FE +C5A8 AND &D0 ;VDU status byte clear bit 0 or bit 2 of status +C5AA STA &D0 ;VDU status byte +C5AC RTS ;exit + +************************************************************************* +* * +* VDU 4 - OUTPUT AT TEXT CURSOR * +* * +************************************************************************* +; +C5AD LDA &0361 ;pixels per byte +C5B0 BEQ &C5AC ;if no graphics in current mode C5AC +C5B2 JSR &C951 ;set CRT controller for text cursor +C5B5 LDA #&DF ;this to clear bit 5 of status byte +C5B7 BNE &C5A8 ;via C5A8 exit + +************************************************************************* +* * +* VDU 5 - OUTPUT AT GRAPHICS CURSOR * +* * +************************************************************************* + +C5B9 LDA &0361 ;pixels per byte +C5BC BEQ &C5AC ;if none this is text mode so exit +C5BE LDA #&20 ;set up graphics cursor +C5C0 JSR &C954 ;via C954 +C5C3 BNE &C59D ;set bit 5 via exit C59D + +************************************************************************* +* * +* VDU 8 - CURSOR LEFT * +* * +************************************************************************* + +C5C5 JSR &C588 ;A=0 if text cursor A=&20 if graphics cursor +C5C8 BNE &C61F ;move cursor left 8 pixels if graphics +C5CA DEC &0318 ;else decrement text column +C5CD LDX &0318 ;store new text column +C5D0 CPX &0308 ;if it is less than text window left +C5D3 BMI &C5EE ;do wraparound cursor to rt of screen 1 line up +C5D5 LDA &034A ;text cursor 6845 address +C5D8 SEC ;subtract +C5D9 SBC &034F ;bytes per character +C5DC TAX ;put in X +C5DD LDA &034B ;get text cursor 6845 address +C5E0 SBC #&00 ;subtract 0 +C5E2 CMP &034E ;compare with hi byte of screen RAM address +C5E5 BCS &C5EA ;if = or greater +C5E7 ADC &0354 ;add screen RAM size hi byte to wrap around +C5EA TAY ;Y=A +C5EB JMP &C9F6 ;Y hi and X lo byte of cursor position + +***************** execute wraparound left-up***************************** + +C5EE LDA &030A ;text window right +C5F1 STA &0318 ;text column + +*************** cursor up *********************************************** + +C5F4 DEC &0269 ;paged mode counter +C5F7 BPL &C5FC ;if still greater than 0 skip next instruction +C5F9 INC &0269 ;paged mode counter to restore X=0 +C5FC LDX &0319 ;current text line +C5FF CPX &030B ;top of text window +C602 BEQ &C60A ;if its at top of window C60A +C604 DEC &0319 ;else decrement current text line +C607 JMP &C6AF ;and carry on moving cursor + +******** cursor at top of window **************************************** + +C60A CLC ;clear carry +C60B JSR &CD3F ;check for window violatations +C60E LDA #&08 ;A=8 to check for software scrolling +C610 BIT &D0 ;compare against VDU status byte +C612 BNE &C619 ;if not enabled C619 +C614 JSR &C994 ;set screen start register and adjust RAM +C617 BNE &C61C ;jump C61C + +C619 JSR &CDA4 ;soft scroll 1 line +C61C JMP &C6AC ;and exit + +**********cursor left and down with graphics cursor in use ************** + +C61F LDX #&00 ;X=0 to select horizontal parameters + +********** cursor down with graphics in use ***************************** +;X=2 for vertical or 0 for horizontal + +C621 STX &DB ;store X +C623 JSR &D10D ;check for window violations +C626 LDX &DB ;restore X +C628 SEC ;set carry +C629 LDA &0324,X ;current graphics cursor X>1=vertical +C62C SBC #&08 ;subtract 8 to move back 1 character +C62E STA &0324,X ;store in current graphics cursor X>1=verticaal +C631 BCS &C636 ;if carry set skip next +C633 DEC &0325,X ;current graphics cursor hi -1 +C636 LDA &DA ;&DA=0 if no violation else 1 if vert violation + ;2 if horizontal violation +C638 BNE &C658 ;if violation C658 +C63A JSR &D10D ;check for window violations +C63D BEQ &C658 ;if none C658 + +C63F LDX &DB ;else get back X +C641 LDA &0304,X ;graphics window rt X=0 top X=2 +C644 CPX #&01 ;is X=0 +C646 BCS &C64A ;if not C64A +C648 SBC #&06 ;else subtract 7 + +C64A STA &0324,X ;current graphics cursor X>1=vertical +C64D LDA &0305,X ;graphics window hi rt X=0 top X=2 +C650 SBC #&00 ;subtract carry +C652 STA &0325,X ;current graphics cursor X<2=horizontal else vertical +C655 TXA ;A=X +C656 BEQ &C660 ;cursor up +C658 JMP &D1B8 ;set up external coordinates for graphics + +************************************************************************* +* * +* VDU 11 - CURSOR UP * +* * +************************************************************************* + +C65B JSR &C588 ;A=0 if text cursor A=&20 if graphics cursor +C65E BEQ &C5F4 ;if text cursor then C5F4 +C660 LDX #&02 ;else X=2 +C662 BNE &C6B6 ;goto C6B6 + +************************************************************************* +* * +* VDU 9 - CURSOR RIGHT * +* * +************************************************************************* + +C664 LDA &D0 ;VDU status byte +C666 AND #&20 ;check bit 5 +C668 BNE &C6B4 ;if set then graphics cursor in use so C6B4 +C66A LDX &0318 ;text column +C66D CPX &030A ;text window right +C670 BCS &C684 ;if X exceeds window right then C684 +C672 INC &0318 ;text column +C675 LDA &034A ;text cursor 6845 address +C678 ADC &034F ;add bytes per character +C67B TAX ;X=A +C67C LDA &034B ;text cursor 6845 address +C67F ADC #&00 ;add carry if set +C681 JMP &C9F6 ;use X and Y to set new cursor address + +********: text cursor down and right ************************************* + +C684 LDA &0308 ;text window left +C687 STA &0318 ;text column + +********: text cursor down ************************************* + +C68A CLC ;clear carry +C68B JSR &CAE3 ;check bottom margin, X=line count +C68E LDX &0319 ;current text line +C691 CPX &0309 ;bottom margin +C694 BCS &C69B ;if X=>current bottom margin C69B +C696 INC &0319 ;else increment current text line +C699 BCC &C6AF ; +C69B JSR &CD3F ;check for window violations +C69E LDA #&08 ;check bit 3 +C6A0 BIT &D0 ;VDU status byte +C6A2 BNE &C6A9 ;if software scrolling enabled C6A9 +C6A4 JSR &C9A4 ;perform hardware scroll +C6A7 BNE &C6AC ; +C6A9 JSR &CDFF ;execute upward scroll +C6AC JSR &CEAC ;clear a line + +C6AF JSR &CF06 ;set up display address +C6B2 BCC &C732 ; + +*********** graphic cursor right **************************************** + +C6B4 LDX #&00 ; + +************** graphic cursor up (X=2) ********************************** + +C6B6 STX &DB ;store X +C6B8 JSR &D10D ;check for window violations +C6BB LDX &DB ;get back X +C6BD CLC ;clear carry +C6BE LDA &0324,X ;current graphics cursor X>1=vertical +C6C1 ADC #&08 ;Add 8 pixels +C6C3 STA &0324,X ;current graphics cursor X>1=vertical +C6C6 BCC &C6CB ; +C6C8 INC &0325,X ;current graphics cursor X<2=horizontal else vertical +C6CB LDA &DA ;A=0 no window violations 1 or 2 indicates violation +C6CD BNE &C658 ;if outside window C658 +C6CF JSR &D10D ;check for window violations +C6D2 BEQ &C658 ;if no violations C658 + +C6D4 LDX &DB ;get back X +C6D6 LDA &0300,X ;graphics window X<2 =left else bottom +C6D9 CPX #&01 ;If X=0 +C6DB BCC &C6DF ;C6DF +C6DD ADC #&06 ;else add 7 +C6DF STA &0324,X ;current graphics cursor X>1=vertical +C6E2 LDA &0301,X ;graphics window hi X<2 =left else bottom +C6E5 ADC #&00 ;add anny carry +C6E7 STA &0325,X ;current graphics cursor X<2=horizontal else vertical +C6EA TXA ;A=X +C6EB BEQ &C6F5 ;if X=0 C6F5 cursor down +C6ED JMP &D1B8 ;set up external coordinates for graphics + +************************************************************************* +* * +* VDU 10 - CURSOR DOWN * +* * +************************************************************************* + +C6F0 JSR &C588 ;A=0 if text cursor A=&20 if graphics cursor +C6F3 BEQ &C68A ;if text cursor back to C68A +C6F5 LDX #&02 ;else X=2 to indicate vertical movement +C6F7 JMP &C621 ;move graphics cursor down + +************************************************************************* +* * +* VDU 28 - DEFINE TEXT WINDOW * +* * +* 4 parameters * +* * +************************************************************************* +;parameters are set up thus +;0320 P1 left margin +;0321 P2 bottom margin +;0322 P3 right margin +;0323 P4 top margin +;Note that last parameter is always in 0323 + +C6FA LDX &0355 ;screen mode +C6FD LDA &0321 ;get bottom margin +C700 CMP &0323 ;compare with top margin +C703 BCC &C758 ;if bottom margin exceeds top return +C705 CMP &C3E7,X ;text window bottom margin maximum +C708 BEQ &C70C ;if equal then its OK +C70A BCS &C758 ;else exit + +C70C LDA &0322 ;get right margin +C70F TAY ;put it in Y +C710 CMP C3EF,X ;text window right hand margin maximum +C713 BEQ &C717 ;if equal then OK +C715 BCS &C758 ;if greater than maximum exit + +C717 SEC ;set carry to subtract +C718 SBC &0320 ;left margin +C71B BMI &C758 ;if left greater than right exit +C71D TAY ;else A=Y (window width) +C71E JSR &CA88 ;calculate number of bytes in a line +C721 LDA #&08 ;A=8 to set bit of &D0 +C723 JSR &C59D ;indicating that text window is defined +C726 LDX #&20 ;point to parameters +C728 LDY #&08 ;point to text window margins +C72A JSR &D48A ;(&300/3+Y)=(&300/3+X) +C72D JSR &CEE8 ;set up screen address +C730 BCS &C779 ;home cursor within window +C732 JMP &CA02 ;set cursor position + +************************************************************************* +* * +* OSWORD 9 - READ A PIXEL * +* =POINT(X,Y) * +* * +************************************************************************* +;on entry &EF=A=9 +; &F0=X=low byte of parameter block address +; &F1=Y=high byte of parameter block address +; PARAMETER BLOCK +; 0,1=X coordinate +; 2,3=Y coordinate +;on exit, result in BLOCK+4 +; =&FF if point was of screen or logical colour of point if on screen +; +C735 LDY #&03 ;Y=3 to point to hi byte of Y coordinate +C737 LDA (&F0),Y ;get it +C739 STA &0328,Y ;store it +C73C DEY ;point to next byte +C73D BPL &C737 ;transfer till Y=&FF lo byte of X coordinate in &328 +C73F LDA #&28 ; +C741 JSR &D839 ;check window boundaries +C744 LDY #&04 ;Y=4 +C746 BNE &C750 ;jump to C750 + + +************************************************************************* +* * +* OSWORD 11 - READ PALLETTE * +* * +************************************************************************* +;on entry &EF=A=11 +; &F0=X=low byte of parameter block address +; &F1=Y=high byte of parameter block address +; PARAMETER BLOCK +; 0=logical colour to read +;on exit, result in BLOCK +; 0=logical colour +; 1=physical colour +; 2=red colour component \ +; 3=green colour component } when set using analogue colours +; 4=blue colour component / + +C748 AND &0360 ;number of logical colours less 1 +C74B TAX ;put it in X +C74C LDA &036F,X ;colour pallette +C74F INY ;increment Y to point to byte 1 + +C750 STA (&F0),Y ;store data +C752 LDA #&00 ;issue 0s +C754 CPY #&04 ;to next bytes until Y=4 +C756 BNE &C74F ; + +C758 RTS ;and exit + + +************************************************************************* +* * +* VDU 12 - CLEAR TEXT SCREEN * +* CLS * +* * +************************************************************************* +; +C759 JSR &C588 ;A=0 if text cursor A=&20 if graphics cursor +C75C BNE &C7BD ;if graphics cursor &C7BD +C75E LDA &D0 ;VDU status byte +C760 AND #&08 ;check if software scrolling (text window set) +C762 BNE &C767 ;if so C767 +C764 JMP &CBC1 ;initialise screen display and home cursor + +C767 LDX &030B ;top of text window +C76A STX &0319 ;current text line +C76D JSR &CEAC ;clear a line + +C770 LDX &0319 ;current text line +C773 CPX &0309 ;bottom margin +C776 INX ;X=X+1 +C777 BCC &C76A ;if X at compare is less than bottom margin clear next + + +************************************************************************* +* * +* VDU 30 - HOME CURSOR * +* * +************************************************************************* + +C779 JSR &C588 ;A=0 if text cursor A=&20 if graphics cursor +C77C BEQ &C781 ;if text cursor C781 +C77E JMP &CFA6 ;home graphic cursor if graphic +C781 STA &0323 ;store 0 in last two parameters +C784 STA &0322 ; + + +************************************************************************* +* * +* VDU 31 - POSITION TEXT CURSOR * +* TAB(X,Y) * +* * +* 2 parameters * +* * +************************************************************************* +;0322 = supplied X coordinate +;0323 = supplied Y coordinate + +C787 JSR &C588 ;A=0 if text cursor A=&20 if graphics cursor +C78A BNE &C758 ;exit +C78C JSR &C7A8 ;exchange text column/line with workspace 0328/9 +C78F CLC ;clear carry +C790 LDA &0322 ;get X coordinate +C793 ADC &0308 ;add to text window left +C796 STA &0318 ;store as text column +C799 LDA &0323 ;get Y coordinate +C79C CLC ; +C79D ADC &030B ;add top of text window +C7A0 STA &0319 ;current text line +C7A3 JSR &CEE8 ;set up screen address +C7A6 BCC &C732 ;set cursor position if C=0 (point on screen) +C7A8 LDX #&18 ;else point to workspace +C7AA LDY #&28 ;and line/column to restore old values +C7AC JMP &CDDE ;exchange &300/1+X with &300/1+Y + + +************************************************************************* +* * +* VDU 13 - CARRIAGE RETURN * +* * +************************************************************************* + +C7AF JSR &C588 ;A=0 if text cursor A=&20 if graphics cursor +C7B2 BEQ &C7B7 ;if text C7B7 +C7B4 JMP &CFAD ;else set graphics cursor to left hand columm + +C7B7 JSR &CE6E ;set text column to left hand column +C7BA JMP &C6AF ;set up cursor and display address + +C7BD JSR &CFA6 ;home graphic cursor + + +************************************************************************* +* * +* VDU 16 - CLEAR GRAPHICS SCREEN * +* CLG * +* * +************************************************************************* + +C7C0 LDA &0361 ;pixels per byte +C7C3 BEQ &C7F8 ;if 0 current mode has no graphics so exit +C7C5 LDX &035A ;Background graphics colour +C7C8 LDY &035C ;background graphics plot mode (GCOL n) +C7CB JSR &D0B3 ;set graphics byte mask in &D4/5 +C7CE LDX #&00 ;graphics window +C7D0 LDY #&28 ;workspace +C7D2 JSR &D47C ;set(300/7+Y) from (300/7+X) +C7D5 SEC ;set carry +C7D6 LDA &0306 ;graphics window top lo. +C7D9 SBC &0302 ;graphics window bottom lo +C7DC TAY ;Y=difference +C7DD INY ;increment +C7DE STY &0330 ;and store in workspace (this is line count) +C7E1 LDX #&2C ; +C7E3 LDY #&28 ; +C7E5 JSR &D6A6 ;clear line +C7E8 LDA &032E ;decrement window height in pixels +C7EB BNE &C7F0 ; +C7ED DEC &032F ; +C7F0 DEC &032E ; +C7F3 DEC &0330 ;decrement line count +C7F6 BNE &C7E1 ;if <>0 then do it again +C7F8 RTS ;exit + + +************************************************************************* +* * +* VDU 17 - DEFINE TEXT COLOUR * +* COLOUR n * +* * +* 1 parameter * +* * +************************************************************************* +;parameter in &0323 + +C7F9 LDY #&00 ;Y=0 +C7FB BEQ &C7FF ;jump to C7FF + + +************************************************************************* +* * +* VDU 18 - DEFINE GRAPHICS COLOUR * +* GCOL k,c * +* * +* 2 parameters * +* * +************************************************************************* +;parameters in 323,322 + +C7FD LDY #&02 ;Y=2 + +C7FF LDA &0323 ;get last parameter +C802 BPL &C805 ;if +ve it's foreground colour so C805 +C804 INY ;else Y=Y+1 +C805 AND &0360 ;number of logical colours less 1 +C808 STA &DA ;store it +C80A LDA &0360 ;number of logical colours less 1 +C80D BEQ &C82B ;if none exit +C80F AND #&07 ;else limit to an available colour and clear M +C811 CLC ;clear carry +C812 ADC &DA ;Add last parameter to get pointer to table +C814 TAX ;pointer into X + +C815 LDA &C423,X ;get plot options from table +C818 STA &0357,Y ; colour Y=0=text fgnd 1= text bkgnd 2=graphics fg etc +C81B CPY #&02 ;If Y>1 +C81D BCS &C82C ;then its graphics so C82C else +C81F LDA &0357 ;foreground text colour +C822 EOR #&FF ;invert +C824 STA &D3 ;text colour byte to be orred or EORed into memory +C826 EOR &0358 ;background text colour +C829 STA &D2 ;text colour byte to be orred or EORed into memory +C82B RTS ;and exit +; +C82C LDA &0322 ;get first parameter +C82F STA &0359,Y ;text colour Y=0=foreground 1=background etc. +C832 RTS ;exit +; +C833 LDA #&20 ; +C835 STA &0358 ;background text colour +C838 RTS ; + + +************************************************************************* +* * +* VDU 20 - RESTORE DEFAULT COLOURS * +* * +************************************************************************* +; +C839 LDX #&05 ;X=5 + +C83B LDA #&00 ;A=0 +C83D STA &0357,X ;zero all colours +C840 DEX ; +C841 BPL &C83D ;until X=&FF +C843 LDX &0360 ;number of logical colours less 1 +C846 BEQ &C833 ;if none its MODE 7 so C833 +C848 LDA #&FF ;A=&FF +C84A CPX #&0F ;if not mode 2 (16 colours) +C84C BNE &C850 ;goto C850 + +C84E LDA #&3F ;else A=&3F +C850 STA &0357 ;foreground text colour +C853 STA &0359 ;foreground graphics colour +C856 EOR #&FF ;invert A +C858 STA &D2 ;text colour byte to be orred or EORed into memory +C85A STA &D3 ;text colour byte to be orred or EORed into memory +C85C STX &031F ;set first parameter of 5 +C85F CPX #&03 ;if there are 4 colours +C861 BEQ &C874 ;goto C874 +C863 BCC &C885 ;if less there are 2 colours goto C885 + ;else there are 16 colours +C865 STX &0320 ;set second parameter +C868 JSR &C892 ;do VDU 19 etc +C86B DEC &0320 ;decrement first parameter +C86E DEC &031F ;and last parameter +C871 BPL &C868 ; +C873 RTS ; +; +********* 4 colour mode ************************************************* + +C874 LDX #&07 ;X=7 +C876 STX &0320 ;set first parameter +C879 JSR &C892 ;and do VDU 19 +C87C LSR &0320 ; +C87F DEC &031F ; +C882 BPL &C879 ; +C884 RTS ;exit + +;********* 2 colour mode ************************************************ + +C885 LDX #&07 ;X=7 +C887 JSR &C88F ;execute VDU 19 +C88A LDX #&00 ;X=0 +C88C STX &031F ;store it as +C88F STX &0320 ;both parameters + + +************************************************************************* +* * +* VDU 19 - DEFINE COLOURS * +* [COLOUR l,p] * +* [COLOUR l,r,g,b] * +* * +* 5 parameters * +* * +************************************************************************* +;&31F=first parameter logical colour +;&320=second physical colour + +C892 PHP ;push processor flags +C893 SEI ;disable interrupts +C894 LDA &031F ;get first parameter and +C897 AND &0360 ;number of logical colours less 1 +C89A TAX ;toi make legal X=A +C89B LDA &0320 ;A=second parameter +C89E AND #&0F ;make legal +C8A0 STA &036F,X ;colour pallette +C8A3 TAY ;Y=A +C8A4 LDA &0360 ;number of logical colours less 1 +C8A7 STA &FA ;store it +C8A9 CMP #&03 ;is it 4 colour mode?? +C8AB PHP ;save flags +C8AC TXA ;A=X +C8AD ROR ;rotate A into &FA +C8AE ROR &FA ; +C8B0 BCS &C8AD ; +C8B2 ASL &FA ; +C8B4 TYA ;A=Y +C8B5 ORA &FA ; +C8B7 TAX ; +C8B8 LDY #&00 ;Y=0 +C8BA PLP ;check flags +C8BB PHP ; +C8BC BNE &C8CC ;if A<>3 earlier C8CC +C8BE AND #&60 ;else A=&60 to test bits 5 and 6 +C8C0 BEQ &C8CB ;if not set C8CB +C8C2 CMP #&60 ;else if both set +C8C4 BEQ &C8CB ;C8CB +C8C6 TXA ;A=X +C8C7 EOR #&60 ;invert +C8C9 BNE &C8CC ;and if not 0 C8CC + +C8CB TXA ;X=A +C8CC JSR &EA11 ;call Osbyte 155 pass data to pallette register +C8CF TYA ; +C8D0 SEC ; +C8D1 ADC &0360 ;number of logical colours less 1 +C8D4 TAY ; +C8D5 TXA ; +C8D6 ADC #&10 ; +C8D8 TAX ; +C8D9 CPY #&10 ;if Y<16 do it again +C8DB BCC &C8BA ; +C8DD PLP ;pull flags twice +C8DE PLP ; +C8DF RTS ;and exit + + +************************************************************************* +* * +* OSWORD 12 - WRITE PALLETTE * +* * +************************************************************************* +;on entry X=&F0:Y=&F1:YX points to parameter block +;byte 0 = logical colour; byte 1 physical colour; bytes 2-4=0 + +C8E0 PHP ;push flags +C8E1 AND &0360 ;and with number of logical colours less 1 +C8E4 TAX ;X=A +C8E5 INY ;Y=Y+1 +C8E6 LDA (&F0),Y ;get phsical colour +C8E8 JMP &C89E ;do VDU19 with parameters in X and A + + +************************************************************************* +* * +* VDU 22 - SELECT MODE * +* MODE n * +* * +* 1 parameter * +* * +************************************************************************* +;parameter in &323 + +C8EB LDA &0323 ;get parameter +C8EE JMP &CB33 ;goto CB33 + + +************************************************************************* +* * +* VDU 23 - DEFINE CHARACTERS * +* * +* 9 parameters * +* * +************************************************************************* +;parameters are:- +;31B character to define +;31C to 323 definition + +C8F1 LDA &031B ;get character to define +C8F4 CMP #&20 ;is it ' ' +C8F6 BCC &C93F ;if less then it is a control instruction, goto C93F +C8F8 PHA ;else save parameter +C8F9 LSR ;A=A/32 +C8FA LSR ; +C8FB LSR ; +C8FC LSR ; +C8FD LSR ; +C8FE TAX ;X=A +C8FF LDA &C40D,X ;get font flag mask from table (A=&80/2^X) +C902 BIT &0367 ;font flag +C905 BNE &C927 ;and if A<>0 C927 storage area is established already +C907 ORA &0367 ;or with font flag to set bit found to be 0 +C90A STA &0367 ;font flag +C90D TXA ;get back A +C90E AND #&03 ;And 3 to clear all but bits 0 and 1 +C910 CLC ;clear carry +C911 ADC #&BF ;add &BF (A=&C0,&C1,&C2) to select a character page +C913 STA &DF ;store it +C915 LDA &0367,X ;get font location byte (normally &0C) +C918 STA &DD ;store it +C91A LDY #&00 ;Y=0 so (&DE) holds (&C000 -&C2FF) +C91C STY &DC ; +C91E STY &DE ; +C920 LDA (&DE),Y ;transfer page to storage area +C922 STA (&DC),Y ; +C924 DEY ; +C925 BNE &C920 ; + +C927 PLA ;get back A +C928 JSR &D03E ;set up character definition pointers + +C92B LDY #&07 ;Y=7 +C92D LDA &031C,Y ;transfer definition parameters +C930 STA (&DE),Y ;to RAM definition +C932 DEY ; +C933 BPL &C92D ; +C935 RTS ;and exit +; +C936 PLA ;Pull A +C937 RTS ;and exit + + +************ VDU EXTENSION ********************************************** + +C938 LDA &031F ;A=fifth VDU parameter +C93B CLC ;clear carry +C93C JMP (&0226) ;jump via VDUV vector + +********** VDU control commands ***************************************** + +C93F CMP #&01 ;is A=1 +C941 BCC &C958 ;if less (0) then set CRT register directly + +C943 BNE &C93C ;if not 1 jump to VDUV for VDU extension + +********** turn cursor on/off ******************************************* + +C945 JSR &C588 ;A=0 if text cursor, A=&20 if graphics cursor +C948 BNE &C937 ;if graphics exit +C94A LDA #&20 ;A=&20 - preload to turn cursor off +C94C LDY &031C ;Y=second VDU parameter +C94F BEQ &C954 ;if 0, jump to C954 to turn cursor off +C951 LDA &035F ;get last setting of CRT controller register + ;for cursor on +C954 LDY #&0A ;Y=10 - cursor control register number +C956 BNE &C985 ;jump to C985, Y=register, Y=value + +********** set CRT controller ******************************************* + +C958 LDA &031D ;get third +C95B LDY &031C ;and second parameter +C95E CPY #&07 ;is Y=7 +C960 BCC &C985 ;if less C985 +C962 BNE &C967 ;else if >7 C967 +C964 ADC &0290 ;else ADD screen vertical display adjustment + +C967 CPY #&08 ;If Y<>8 +C969 BNE &C972 ;C972 +C96B ORA #&00 ;if bit 7 set +C96D BMI &C972 ;C972 +C96F EOR &0291 ;else EOR with interlace toggle + +C972 CPY #&0A ;Y=10?? +C974 BNE &C985 ;if not C985 +C976 STA &035F ;last setting of CRT controller register +C979 TAY ;Y=A +C97A LDA &D0 ;VDU status byte +C97C AND #&20 ;check bit 5 printing at graphics cursor?? +C97E PHP ;push flags +C97F TYA ;Y=A +C980 LDY #&0A ;Y=10 +C982 PLP ;pull flags +C983 BNE &C98B ;if graphics in use then C98B + + +C985 STY &FE00 ;else set CRTC address register +C988 STA &FE01 ;and poke new value to register Y +C98B RTS ;exit + + +************************************************************************* +* * +* VDU 25 - PLOT * +* PLOT k,x,y * +* DRAW x,y * +* MOVE x,y * +* PLOT x,y * +* 5 parameters * +* * +************************************************************************* +; +C98C LDX &0361 ;pixels per byte +C98F BEQ &C938 ;if no graphics available go to VDU Extension +C991 JMP &D060 ;else enter Plot routine at D060 + +********** adjust screen RAM addresses ********************************** + +C994 LDX &0350 ;window area start address lo +C997 LDA &0351 ;window area start address hi +C99A JSR &CCF8 ;subtract bytes per character row from this +C99D BCS &C9B3 ;if no wraparound needed C9B3 + +C99F ADC &0354 ;screen RAM size hi byte to wrap around +C9A2 BCC &C9B3 ; + +C9A4 LDX &0350 ;window area start address lo +C9A7 LDA &0351 ;window area start address hi +C9AA JSR &CAD4 ;add bytes per char. row +C9AD BPL &C9B3 ; + +C9AF SEC ;wrap around i other direction +C9B0 SBC &0354 ;screen RAM size hi byte +C9B3 STA &0351 ;window area start address hi +C9B6 STX &0350 ;window area start address lo +C9B9 LDY #&0C ;Y=12 +C9BB BNE &CA0E ;jump to CA0E + + +************************************************************************* +* * +* VDU 26 - SET DEFAULT WINDOWS * +* * +************************************************************************* + +C9BD LDA #&00 ;A=0 +C9BF LDX #&2C ;X=&2C + +C9C1 STA &0300,X ;clear all windows +C9C4 DEX ; +C9C5 BPL &C9C1 ;until X=&FF + +C9C7 LDX &0355 ;screen mode +C9CA LDY C3EF,X ;text window right hand margin maximum +C9CD STY &030A ;text window right +C9D0 JSR &CA88 ;calculate number of bytes in a line +C9D3 LDY &C3E7,X ;text window bottom margin maximum +C9D6 STY &0309 ;bottom margin +C9D9 LDY #&03 ;Y=3 +C9DB STY &0323 ;set as last parameter +C9DE INY ;increment Y +C9DF STY &0321 ;set parameters +C9E2 DEC &0322 ; +C9E5 DEC &0320 ; +C9E8 JSR &CA39 ;and do VDU 24 +C9EB LDA #&F7 ; +C9ED JSR &C5A8 ;clear bit 3 of &D0 +C9F0 LDX &0350 ;window area start address lo +C9F3 LDA &0351 ;window area start address hi +C9F6 STX &034A ;text cursor 6845 address +C9F9 STA &034B ;text cursor 6845 address +C9FC BPL &CA02 ;set cursor position +C9FE SEC ; +C9FF SBC &0354 ;screen RAM size hi byte + +**************** set cursor position ************************************ + +CA02 STX &D8 ;set &D8/9 from X/A +CA04 STA &D9 ; +CA06 LDX &034A ;text cursor 6845 address +CA09 LDA &034B ;text cursor 6845 address +CA0C LDY #&0E ;Y=15 +CA0E PHA ;Push A +CA0F LDA &0355 ;screen mode +CA12 CMP #&07 ;is it mode 7? +CA14 PLA ;get back A +CA15 BCS &CA27 ;if mode 7 selected CA27 +CA17 STX &DA ;else store X +CA19 LSR ;divide X/A by 8 +CA1A ROR &DA ; +CA1C LSR ; +CA1D ROR &DA ; +CA1F LSR ; +CA20 ROR &DA ; +CA22 LDX &DA ; +CA24 JMP &CA2B ;goto CA2B + +CA27 SBC #&74 ;mode 7 subtract &74 +CA29 EOR #&20 ;EOR with &20 +CA2B STY &FE00 ;write to CRTC address file register +CA2E STA &FE01 ;and to relevant address (register 14) +CA31 INY ;Increment Y +CA32 STY &FE00 ;write to CRTC address file register +CA35 STX &FE01 ;and to relevant address (register 15) +CA38 RTS ;and RETURN +************************************************************************* +* * +* VDU 24 - DEFINE GRAPHICS WINDOW * +* * +* 8 parameters * +* * +************************************************************************* +;&31C/D Left margin +;&31E/F Bottom margin +;&320/1 Right margin +;&322/3 Top margin + +CA39 JSR &CA81 ;exchange 310/3 with 328/3 +CA3C LDX #&1C ; +CA3E LDY #&2C ; +CA40 JSR &D411 ;calculate width=right - left + ; height = top-bottom +CA43 ORA &032D ; +CA46 BMI &CA81 ;exchange 310/3 with 328/3 and exit +CA48 LDX #&20 ;X=&20 +CA4A JSR &D149 ;scale pointers to mode +CA4D LDX #&1C ;X=&1C +CA4F JSR &D149 ;scale pointers to mode +CA52 LDA &031F ;check for negative margins +CA55 ORA &031D ; +CA58 BMI &CA81 ;if found exchange 310/3 with 328/3 and exit +CA5A LDA &0323 ; +CA5D BNE &CA81 ;exchange 310/3 with 328/3 and exit +CA5F LDX &0355 ;screen mode +CA62 LDA &0321 ;right margin hi +CA65 STA &DA ;store it +CA67 LDA &0320 ;right margin lo +CA6A LSR &DA ;/2 +CA6C ROR ;A=A/2 +CA6D LSR &DA ;/2 +CA6F BNE &CA81 ;exchange 310/3 with 328/3 +CA71 ROR ;A=A/2 +CA72 LSR ;A=A/2 +CA73 CMP C3EF,X ;text window right hand margin maximum +CA76 BEQ &CA7A ;if equal CA7A +CA78 BPL &CA81 ;exchange 310/3 with 328/3 + +CA7A LDY #&00 ;Y=0 +CA7C LDX #&1C ;X=&1C +CA7E JSR &D47C ;set(300/7+Y) from (300/7+X) + +***************** exchange 310/3 with 328/3 ***************************** + +CA81 LDX #&10 ;X=10 +CA83 LDY #&28 ;Y=&28 +CA85 JMP &CDE6 ;exchange 300/3+Y and 300/3+X + +CA88 INY ;Y=Y+1 +CA89 TYA ;A=Y +CA8A LDY #&00 ;Y=0 +CA8C STY &034D ;text window width hi (bytes) +CA8F STA &034C ;text window width lo (bytes) +CA92 LDA &034F ;bytes per character +CA95 LSR ;/2 +CA96 BEQ &CAA1 ;if 0 exit +CA98 ASL &034C ;text window width lo (bytes) +CA9B ROL &034D ;text window width hi (bytes) +CA9E LSR ;/2 +CA9F BCC &CA98 ; +CAA1 RTS ; + + +************************************************************************* +* * +* VDU 29 - SET GRAPHICS ORIGIN * +* * +* 4 parameters * +* * +************************************************************************* +; +CAA2 LDX #&20 ; +CAA4 LDY #&0C ; +CAA6 JSR &D48A ;(&300/3+Y)=(&300/3+X) +CAA9 JMP &D1B8 ;set up external coordinates for graphics + + +************************************************************************* +* * +* VDU 127 (&7F) - DELETE (entry 32) * +* * +************************************************************************* + +CAAC JSR &C5C5 ;cursor left +CAAF JSR &C588 ;A=0 if text cursor A=&20 if graphics cursor +CAB2 BNE &CAC7 ;if graphics then CAC7 +CAB4 LDX &0360 ;number of logical colours less 1 +CAB7 BEQ &CAC2 ;if mode 7 CAC2 +CAB9 STA &DE ;else store A (always 0) +CABB LDA #&C0 ;A=&C0 +CABD STA &DF ;store in &DF (&DE) now points to C300 SPACE pattern +CABF JMP &CFBF ;display a space + +CAC2 LDA #&20 ;A=&20 +CAC4 JMP &CFDC ;and return to display a space + +CAC7 LDA #&7F ;for graphics cursor +CAC9 JSR &D03E ;set up character definition pointers +CACC LDX &035A ;Background graphics colour +CACF LDY #&00 ;Y=0 +CAD1 JMP &CF63 ;invert pattern data (to background colour) + +***** Add number of bytes in a line to X/A ****************************** + +CAD4 PHA ;store A +CAD5 TXA ;A=X +CAD6 CLC ;clear carry +CAD7 ADC &0352 ;bytes per character row +CADA TAX ;X=A +CADB PLA ;get back A +CADC ADC &0353 ;bytes per character row +CADF RTS ;and return +; +********* control scrolling in paged mode ******************************* + +CAE0 JSR &CB14 ;zero paged mode line counter +CAE3 JSR &E9D9 ;osbyte 118 check keyboard status; set LEDs +CAE6 BCC &CAEA ;if carry clear CAEA +CAE8 BMI &CAE0 ;if M set CAE0 do it again + +CAEA LDA &D0 ;VDU status byte +CAEC EOR #&04 ;invert bit 2 paged scrolling +CAEE AND #&46 ;and if 2 cursors, paged mode off, or scrolling +CAF0 BNE &CB1C ;barred then CB1C to exit + +CAF2 LDA &0269 ;paged mode counter +CAF5 BMI &CB19 ;if negative then exit via CB19 + +CAF7 LDA &0319 ;current text line +CAFA CMP &0309 ;bottom margin +CAFD BCC &CB19 ;increment line counter and exit + +CAFF LSR ;A=A/4 +CB00 LSR ; +CB01 SEC ;set carry +CB02 ADC &0269 ;paged mode counter +CB05 ADC &030B ;top of text window +CB08 CMP &0309 ;bottom margin +CB0B BCC &CB19 ;increment line counter and exit + +CB0D CLC ;clear carry +CB0E JSR &E9D9 ;osbyte 118 check keyboard status; set LEDs +CB11 SEC ;set carry +CB12 BPL &CB0E ;if +ve result then loop till shift pressed + +**************** zero paged mode counter ******************************* + +CB14 LDA #&FF ; +CB16 STA &0269 ;paged mode counter +CB19 INC &0269 ;paged mode counter +CB1C RTS ; + +*********part of intitialisation routines ****************************** + +CB1D PHA ;save A +CB1E LDX #&7F ;X=&7F +CB20 LDA #&00 ;A=0 +CB22 STA &D0 ;VDU status byte to set default conditions + +CB24 STA &02FF,X ;zero 300,37E +CB27 DEX ;with this loop +CB28 BNE &CB24 ; + +CB2A JSR &CD07 ;implode character definitions +CB2D PLA ;get back A +CB2E LDX #&7F ;X=&7F +CB30 STX &0366 ;mode 7 write cursor character +CB33 BIT &028E ;available RAM pages +CB36 BMI &CB3A ;if 32k CB3A + +CB38 ORA #&04 ;ensure only modes 4-7 are available + +CB3A AND #&07 ;X=A and 7 ensure legal mode +CB3C TAX ;X=mode +CB3D STX &0355 ;set screen mode flag +CB40 LDA &C414,X ;no. of colours -1 in mode table +CB43 STA &0360 ;number of logical colours less 1 +CB46 LDA &C3FF,X ;number of bytes /character for each mode +CB49 STA &034F ;bytes per character +CB4C LDA &C43A,X ;display mode pixels/byte table +CB4F STA &0361 ;pixels per byte +CB52 BNE &CB56 ;if <> 0 CB56 +CB54 LDA #&07 ;else A=7 + +CB56 ASL ;A=A*2 +CB57 TAY ;Y=A + +CB58 LDA &C406,Y ;mask table +CB5B STA &0363 ;colour mask left +CB5E ASL ;A=A*2 +CB5F BPL &CB5E ;If still +ve CB5E +CB61 STA &0362 ;colour mask right +CB64 LDY &C440,X ;screen display memory index table +CB67 STY &0356 ;memory map type +CB6A LDA &C44F,Y ;VDU section control +CB6D JSR &E9F8 ;set hardware scrolling to VIA +CB70 LDA &C44B,Y ;VDU section control +CB73 JSR &E9F8 ;set hardware scrolling to VIA +CB76 LDA &C459,Y ;Screen RAM size hi byte table +CB79 STA &0354 ;screen RAM size hi byte +CB7C LDA &C45E,Y ;screen ram address hi byte +CB7F STA &034E ;hi byte of screen RAM address +CB82 TYA ;Y=A +CB83 ADC #&02 ;Add 2 +CB85 EOR #&07 ; +CB87 LSR ;/2 +CB88 TAX ;X=A +CB89 LDA &C466,X ;row multiplication table pointer +CB8C STA &E0 ;store it +CB8E LDA #&C3 ;A=&C3 +CB90 STA &E1 ;store it (&E0) now points to C3B5 or C375 +CB92 LDA &C463,X ;get nuber of bytes per row from table +CB95 STA &0352 ;store as bytes per character row +CB98 STX &0353 ;bytes per character row +CB9B LDA #&43 ;A=&43 +CB9D JSR &C5A8 ;A=A and &D0:&D0=A +CBA0 LDX &0355 ;screen mode +CBA3 LDA &C3F7,X ;get video ULA control setting +CBA6 JSR &EA00 ;set video ULA using osbyte 154 +CBA9 PHP ;push flags +CBAA SEI ;set interrupts +CBAB LDX &C469,Y ;get cursor end register data from table +CBAE LDY #&0B ;Y=11 + +CBB0 LDA &C46E,X ;get end of 6845 registers 0-11 table +CBB3 JSR &C95E ;set register Y +CBB6 DEX ;reduce pointers +CBB7 DEY ; +CBB8 BPL &CBB0 ;and if still >0 do it again + +CBBA PLP ;pull flags +CBBB JSR &C839 ;set default colours +CBBE JSR &C9BD ;set default windows + +CBC1 LDX #&00 ;X=0 +CBC3 LDA &034E ;hi byte of screen RAM address +CBC6 STX &0350 ;window area start address lo +CBC9 STA &0351 ;window area start address hi +CBCC JSR &C9F6 ;use X and Y to set new cursor address +CBCF LDY #&0C ;Y=12 +CBD1 JSR &CA2B ;set registers 12 and 13 in CRTC +CBD4 LDA &0358 ;background text colour +CBD7 LDX &0356 ;memory map type +CBDA LDY &C454,X ;get section control number +CBDD STY &035D ;set it in jump vector lo +CBE0 LDY #&CC ;Y=&CC +CBE2 STY &035E ;upper byte of link address +CBE5 LDX #&00 ;X=0 +CBE7 STX &0269 ;paged mode counter +CBEA STX &0318 ;text column +CBED STX &0319 ;current text line +CBF0 JMP (&035D) ;jump vector set up previously + + +************************************************************************* +* * +* OSWORD 10 - READ CHARACTER DEFINITION * +* * +************************************************************************* +;&EF=A:&F0=X:&F1=Y, on entry YX contains character number to be read +;(&DE) points to address +;on exit byte YX+1 to YX+8 contain definition + +CBF3 JSR &D03E ;set up character definition pointers +CBF6 LDY #&00 ;Y=0 +CBF8 LDA (&DE),Y ;get first byte +CBFA INY ;Y=Y+1 +CBFB STA (&F0),Y ;store it in YX +CBFD CPY #&08 ;until Y=8 +CBFF BNE &CBF8 ; +CC01 RTS ;then exit + + +************************************************************************* +* * +* MAIN SCREEN CLEARANCE ROUTINE * +* * +************************************************************************* +;on entry A contains background colour which is set in every byte +;of the screen + +************************ Mode 0,1,2 entry point ************************* + +CC02 STA &3000,X ; +CC05 STA &3100,X ; +CC08 STA &3200,X ; +CC0B STA &3300,X ; +CC0E STA &3400,X ; +CC11 STA &3500,X ; +CC14 STA &3600,X ; +CC17 STA &3700,X ; +CC1A STA &3800,X ; +CC1D STA &3900,X ; +CC20 STA &3A00,X ; +CC23 STA &3B00,X ; +CC26 STA &3C00,X ; +CC29 STA &3D00,X ; +CC2C STA &3E00,X ; +CC2F STA &3F00,X ; + +************************ Mode 3 entry point ***************************** + +CC32 STA &4000,X ; +CC35 STA &4100,X ; +CC38 STA &4200,X ; +CC3B STA &4300,X ; +CC3E STA &4400,X ; +CC41 STA &4500,X ; +CC44 STA &4600,X ; +CC47 STA &4700,X ; +CC4A STA &4800,X ; +CC4D STA &4900,X ; +CC50 STA &4A00,X ; +CC53 STA &4B00,X ; +CC56 STA &4C00,X ; +CC59 STA &4D00,X ; +CC5C STA &4E00,X ; +CC5F STA &4F00,X ; +CC62 STA &5000,X ; +CC65 STA &5100,X ; +CC68 STA &5200,X ; +CC6B STA &5300,X ; +CC6E STA &5400,X ; +CC71 STA &5500,X ; +CC74 STA &5600,X ; +CC77 STA &5700,X ; + +************************ Mode 4,5 entry point *************************** + +CC7A STA &5800,X ; +CC7D STA &5900,X ; +CC80 STA &5A00,X ; +CC83 STA &5B00,X ; +CC86 STA &5C00,X ; +CC89 STA &5D00,X ; +CC8C STA &5E00,X ; +CC8F STA &5F00,X ; + +************************ Mode 6 entry point ***************************** + +CC92 STA &6000,X ; +CC95 STA &6100,X ; +CC98 STA &6200,X ; +CC9B STA &6300,X ; +CC9E STA &6400,X ; +CCA1 STA &6500,X ; +CCA4 STA &6600,X ; +CCA7 STA &6700,X ; +CCAA STA &6800,X ; +CCAD STA &6900,X ; +CCB0 STA &6A00,X ; +CCB3 STA &6B00,X ; +CCB6 STA &6C00,X ; +CCB9 STA &6D00,X ; +CCBC STA &6E00,X ; +CCBF STA &6F00,X ; +CCC2 STA &7000,X ; +CCC5 STA &7100,X ; +CCC8 STA &7200,X ; +CCCB STA &7300,X ; +CCCE STA &7400,X ; +CCD1 STA &7500,X ; +CCD4 STA &7600,X ; +CCD7 STA &7700,X ; +CCDA STA &7800,X ; +CCDD STA &7900,X ; +CCE0 STA &7A00,X ; +CCE3 STA &7B00,X ; + +************************ Mode 7 entry point ***************************** + +CCE6 STA &7C00,X ; +CCE9 STA &7D00,X ; +CCEC STA &7E00,X ; +CCEF STA &7F00,X ; +CCF2 INX ; +CCF3 BEQ &CD65 ;exit + +****************** execute required function **************************** + +CCF5 JMP (&035D) ;jump vector set up previously + +********* subtract bytes per line from X/A ****************************** + +CCF8 PHA ;Push A +CCF9 TXA ;A=X +CCFA SEC ;set carry for subtraction +CCFB SBC &0352 ;bytes per character row +CCFE TAX ;restore X +CCFF PLA ;and A +CD00 SBC &0353 ;bytes per character row +CD03 CMP &034E ;hi byte of screen RAM address +CD06 RTS ;return + + +************************************************************************* +* * +* OSBYTE 20 - EXPLODE CHARACTERS * +* * +************************************************************************* +; +CD07 LDA #&0F ;A=15 +CD09 STA &0367 ;font flag indicating that page &0C,&C0-&C2 are + ;used for user defined characters +CD0C LDA #&0C ;A=&0C +CD0E LDY #&06 ;set loop counter + +CD10 STA &0368,Y ;set all font location bytes +CD13 DEY ;to page &0C to indicate only page available +CD14 BPL &CD10 ;for user character definitions + +CD16 CPX #&07 ;is X= 7 or greater +CD18 BCC &CD1C ;if not CD1C +CD1A LDX #&06 ;else X=6 +CD1C STX &0246 ;character definition explosion switch +CD1F LDA &0243 ;A=primary OSHWM +CD22 LDX #&00 ;X=0 + +CD24 CPX &0246 ;character definition explosion switch +CD27 BCS &CD34 ; +CD29 LDY &C4BA,X ;get soft character RAM allocation +CD2C STA &0368,Y ;font location bytes +CD2F ADC #&01 ;Add 1 +CD31 INX ;X=X+1 +CD32 BNE &CD24 ;if X<>0 then CD24 + +CD34 STA &0244 ;current value of page (OSHWM) +CD37 TAY ;Y=A +CD38 BEQ &CD06 ;return via CD06 (ERROR?) + +CD3A LDX #&11 ;X=&11 +CD3C JMP &F168 ;issue paged ROM service call &11 + ;font implosion/explosion warning + +******** move text cursor to next line ********************************** + +CD3F LDA #&02 ;A=2 to check if scrolling disabled +CD41 BIT &D0 ;VDU status byte +CD43 BNE &CD47 ;if scrolling is barred CD47 +CD45 BVC &CD79 ;if cursor editing mode disabled RETURN + +CD47 LDA &0309 ;bottom margin +CD4A BCC &CD4F ;if carry clear on entry CD4F +CD4C LDA &030B ;else if carry set get top of text window +CD4F BVS &CD59 ;and if cursor editing enabled CD59 +CD51 STA &0319 ;get current text line +CD54 PLA ;pull return link from stack +CD55 PLA ; +CD56 JMP &C6AF ;set up cursor and display address + +CD59 PHP ;push flags +CD5A CMP &0365 ;Y coordinate of text input cursor +CD5D BEQ &CD78 ;if A=line count of text input cursor CD78 to exit +CD5F PLP ;get back flags +CD60 BCC &CD66 ; +CD62 DEC &0365 ;Y coordinate of text input cursor + +CD65 RTS ;exit +; +CD66 INC &0365 ;Y coordinate of text input cursor +CD69 RTS ;exit + +*********************** set up write cursor ******************************** + +CD6A PHP ;save flags +CD6B PHA ;save A +CD6C LDY &034F ;bytes per character +CD6F DEY ;Y=Y-1 +CD70 BNE &CD8F ;if Y=0 Mode 7 is in use + +CD72 LDA &0338 ;so get mode 7 write character cursor character &7F +CD75 STA (&D8),Y ;store it at top scan line of current character +CD77 PLA ;pull A +CD78 PLP ;pull flags +CD79 RTS ;and exit +; +CD7A PHP ;push flags +CD7B PHA ;push A +CD7C LDY &034F ;bytes per character +CD7F DEY ; +CD80 BNE &CD8F ;if not mode 7 +CD82 LDA (&D8),Y ;get cursor from top scan line +CD84 STA &0338 ;store it +CD87 LDA &0366 ;mode 7 write cursor character +CD8A STA (&D8),Y ;store it at scan line +CD8C JMP &CD77 ;and exit + +CD8F LDA #&FF ;A=&FF =cursor +CD91 CPY #&1F ;except in mode 2 (Y=&1F) +CD93 BNE &CD97 ;if not CD97 +CD95 LDA #&3F ;load cursor byte mask + +********** produce white block write cursor ***************************** + +CD97 STA &DA ;store it +CD99 LDA (&D8),Y ;get scan line byte +CD9B EOR &DA ;invert it +CD9D STA (&D8),Y ;store it on scan line +CD9F DEY ;decrement scan line counter +CDA0 BPL &CD99 ;do it again +CDA2 BMI &CD77 ;then jump to &CD77 + +CDA4 JSR &CE5B ;exchange line and column cursors with workspace copies +CDA7 LDA &0309 ;bottom margin +CDAA STA &0319 ;current text line +CDAD JSR &CF06 ;set up display address +CDB0 JSR &CCF8 ;subtract bytes per character row from this +CDB3 BCS &CDB8 ;wraparound if necessary +CDB5 ADC &0354 ;screen RAM size hi byte +CDB8 STA &DB ;store A +CDBA STX &DA ;X +CDBC STA &DC ;A again +CDBE BCS &CDC6 ;if C set there was no wraparound so CDC6 +CDC0 JSR &CE73 ;copy line to new position + ;using (&DA) for read + ;and (&D8) for write +CDC3 JMP &CDCE ; + +CDC6 JSR &CCF8 ;subtract bytes per character row from X/A +CDC9 BCC &CDC0 ;if a result is outside screen RAM CDC0 +CDCB JSR &CE38 ;perform a copy + +CDCE LDA &DC ;set write pointer from read pointer +CDD0 LDX &DA ; +CDD2 STA &D9 ; +CDD4 STX &D8 ; +CDD6 DEC &DE ;decrement window height +CDD8 BNE &CDB0 ;and if not zero CDB0 +CDDA LDX #&28 ;point to workspace +CDDC LDY #&18 ;point to text column/line +CDDE LDA #&02 ;number of bytes to swap +CDE0 BNE &CDE8 ;exchange (328/9)+Y with (318/9)+X +CDE2 LDX #&24 ;point to graphics cursor +CDE4 LDY #&14 ;point to last graphics cursor + ;A=4 to swap X and Y coordinates + +*************** exchange 300/3+Y with 300/3+X *************************** + +CDE6 LDA #&04 ;A =4 + +************** exchange (300/300+A)+Y with (300/300+A)+X ***************** + +CDE8 STA &DA ;store it as loop counter + +CDEA LDA &0300,X ;get byte +CDED PHA ;store it +CDEE LDA &0300,Y ;get byte pointed to by Y +CDF1 STA &0300,X ;put it in 300+X +CDF4 PLA ;get back A +CDF5 STA &0300,Y ;put it in 300+Y +CDF8 INX ;increment pointers +CDF9 INY ; +CDFA DEC &DA ;decrement loop counter +CDFC BNE &CDEA ;and if not 0 do it again +CDFE RTS ;and exit + +******** execute upward scroll ****************************************** +; +CDFF JSR &CE5B ;exchange line and column cursors with workspace copies +CE02 LDY &030B ;top of text window +CE05 STY &0319 ;current text line +CE08 JSR &CF06 ;set up display address +CE0B JSR &CAD4 ;add bytes per char. row +CE0E BPL &CE14 ; +CE10 SEC ; +CE11 SBC &0354 ;screen RAM size hi byte + +CE14 STA &DB ;(&DA)=X/A +CE16 STX &DA ; +CE18 STA &DC ;&DC=A +CE1A BCC &CE22 ; +CE1C JSR &CE73 ;copy line to new position + ;using (&DA) for read + ;and (&D8) for write +CE1F JMP &CE2A ;exit + +CE22 JSR &CAD4 ;add bytes per char. row +CE25 BMI &CE1C ;if outside screen RAM CE1C +CE27 JSR &CE38 ;perform a copy +CE2A LDA &DC ; +CE2C LDX &DA ; +CE2E STA &D9 ; +CE30 STX &D8 ; +CE32 DEC &DE ;decrement window height +CE34 BNE &CE0B ;CE0B if not 0 +CE36 BEQ &CDDA ;exchange text column/linelse CDDA + +*********** copy routines *********************************************** + +CE38 LDX &034D ;text window width hi (bytes) +CE3B BEQ &CE4D ;if no more than 256 bytes to copy X=0 so CE4D + +CE3D LDY #&00 ;Y=0 to set loop counter + +CE3F LDA (&DA),Y ;copy 256 bytes +CE41 STA (&D8),Y ; +CE43 INY ; +CE44 BNE &CE3F ;Till Y=0 again +CE46 INC &D9 ;increment hi bytes +CE48 INC &DB ; +CE4A DEX ;decrement window width +CE4B BNE &CE3F ;if not 0 go back and do loop again + +CE4D LDY &034C ;text window width lo (bytes) +CE50 BEQ &CE5A ;if Y=0 CE5A + +CE52 DEY ;else Y=Y-1 +CE53 LDA (&DA),Y ;copy Y bytes +CE55 STA (&D8),Y ; +CE57 TYA ;A=Y +CE58 BNE &CE52 ;if not 0 CE52 +CE5A RTS ;and exit + +CE5B JSR &CDDA ;exchange text column/line with workspace +CE5E SEC ;set carry +CE5F LDA &0309 ;bottom margin +CE62 SBC &030B ;top of text window +CE65 STA &DE ;store it +CE67 BNE &CE6E ;set text column to left hand column +CE69 PLA ;get back return address +CE6A PLA ; +CE6B JMP &CDDA ;exchange text column/line with workspace + +CE6E LDA &0308 ;text window left +CE71 BPL &CEE3 ;Jump CEE3 always! + +CE73 LDA &DA ;get back A +CE75 PHA ;push A +CE76 SEC ;set carry +CE77 LDA &030A ;text window right +CE7A SBC &0308 ;text window left +CE7D STA &DF ; +CE7F LDY &034F ;bytes per character to set loop counter + +CE82 DEY ;copy loop +CE83 LDA (&DA),Y ; +CE85 STA (&D8),Y ; +CE87 DEY ; +CE88 BPL &CE83 ; + +CE8A LDX #&02 ;X=2 +CE8C CLC ;clear carry +CE8D LDA &D8,X ; +CE8F ADC &034F ;bytes per character +CE92 STA &D8,X ; +CE94 LDA &D9,X ; +CE96 ADC #&00 ; +CE98 BPL &CE9E ;if this remains in screen RAM OK + +CE9A SEC ;else wrap around screen +CE9B SBC &0354 ;screen RAM size hi byte +CE9E STA &D9,X ; +CEA0 DEX ;X=X-2 +CEA1 DEX ; +CEA2 BEQ &CE8C ;if X=0 adjust second set of pointers +CEA4 DEC &DF ;decrement window width +CEA6 BPL &CE7F ;and if still +ve do it all again +CEA8 PLA ;get back A +CEA9 STA &DA ;and store it +CEAB RTS ;then exit + +*********** clear a line ************************************************ + +CEAC LDA &0318 ;text column +CEAF PHA ;save it +CEB0 JSR &CE6E ;set text column to left hand column +CEB3 JSR &CF06 ;set up display address +CEB6 SEC ;set carry +CEB7 LDA &030A ;text window right +CEBA SBC &0308 ;text window left +CEBD STA &DC ;as window width +CEBF LDA &0358 ;background text colour +CEC2 LDY &034F ;bytes per character + +CEC5 DEY ;Y=Y-1 decrementing loop counter +CEC6 STA (&D8),Y ;store background colour at this point on screen +CEC8 BNE &CEC5 ;if Y<>0 do it again +CECA TXA ;else A=X +CECB CLC ;clear carry to add +CECC ADC &034F ;bytes per character +CECF TAX ;X=A restoring it +CED0 LDA &D9 ;get hi byte +CED2 ADC #&00 ;Add carry if any +CED4 BPL &CEDA ;if +ve CeDA +CED6 SEC ;else wrap around +CED7 SBC &0354 ;screen RAM size hi byte + +CEDA STX &D8 ;restore D8/9 +CEDC STA &D9 ; +CEDE DEC &DC ;decrement window width +CEE0 BPL &CEBF ;ind if not 0 do it all again +CEE2 PLA ;get back A +CEE3 STA &0318 ;restore text column +CEE6 SEC ;set carry +CEE7 RTS ;and exit + +CEE8 LDX &0318 ;text column +CEEB CPX &0308 ;text window left +CEEE BMI &CEE6 ;if less than left margin return with carry set +CEF0 CPX &030A ;text window right +CEF3 BEQ &CEF7 ;if equal to right margin thats OK +CEF5 BPL &CEE6 ;if greater than right margin return with carry set + +CEF7 LDX &0319 ;current text line +CEFA CPX &030B ;top of text window +CEFD BMI &CEE6 ;if less than top margin +CEFF CPX &0309 ;bottom margin +CF02 BEQ &CF06 ;set up display address +CF04 BPL &CEE6 ;or greater than bottom margin return with carry set + +************:set up display address ************************************* + +;Mode 0: (0319)*640+(0318)* 8 +;Mode 1: (0319)*640+(0318)*16 +;Mode 2: (0319)*640+(0318)*32 +;Mode 3: (0319)*640+(0318)* 8 +;Mode 4: (0319)*320+(0318)* 8 +;Mode 5: (0319)*320+(0318)*16 +;Mode 6: (0319)*320+(0318)* 8 +;Mode 7: (0319)* 40+(0318) +; +;this gives a displacement relative to the screen RAM start address +;which is added to the calculated number and stored in in 34A/B +;if the result is less than &8000, the top of screen RAM it is copied into X/A +;and D8/9. +;if the result is greater than &7FFF the hi byte of screen RAM size is +;subtracted to wraparound the screen. X/A, D8/9 are then set from this + +CF06 LDA &0319 ;current text line +CF09 ASL ;A=A*2 +CF0A TAY ;Y=A +CF0B LDA (&E0),Y ;get CRTC multiplication table pointer +CF0D STA &D9 ;&D9=A +CF0F INY ;Y=Y+1 +CF10 LDA #&02 ;A=2 +CF12 AND &0356 ;memory map type +CF15 PHP ;save flags +CF16 LDA (&E0),Y ;get CRTC multiplication table pointer +CF18 PLP ;pull flags +CF19 BEQ &CF1E ; +CF1B LSR &D9 ;&D9=&D9/2 +CF1D ROR ;A=A/2 +(128*carry) +CF1E ADC &0350 ;window area start address lo +CF21 STA &D8 ;store it +CF23 LDA &D9 ; +CF25 ADC &0351 ;window area start address hi +CF28 TAY ; +CF29 LDA &0318 ;text column +CF2C LDX &034F ;bytes per character +CF2F DEX ;X=X-1 +CF30 BEQ &CF44 ;if X=0 mode 7 CF44 +CF32 CPX #&0F ;is it mode 1 or mode 5? +CF34 BEQ &CF39 ;yes CF39 with carry set +CF36 BCC &CF3A ;if its less (mode 0,3,4,6) CF3A +CF38 ASL ;A=A*16 if entered here (mode 2) + +CF39 ASL ;A=A*8 if entered here + +CF3A ASL ;A=A*4 if entered here +CF3B ASL ; +CF3C BCC &CF40 ;if carry clear +CF3E INY ;Y=Y+2 +CF3F INY ; +CF40 ASL ;A=A*2 +CF41 BCC &CF45 ;if carry clear add to &D8 +CF43 INY ;if not Y=Y+1 + +CF44 CLC ;clear carry +CF45 ADC &D8 ;add to &D8 +CF47 STA &D8 ;and store it +CF49 STA &034A ;text cursor 6845 address +CF4C TAX ;X=A +CF4D TYA ;A=Y +CF4E ADC #&00 ;Add carry if set +CF50 STA &034B ;text cursor 6845 address +CF53 BPL &CF59 ;if less than &800 goto &CF59 +CF55 SEC ;else wrap around +CF56 SBC &0354 ;screen RAM size hi byte + +CF59 STA &D9 ;store in high byte +CF5B CLC ;clear carry +CF5C RTS ;and exit + +******** Graphics cursor display routine ******************************** + +CF5D LDX &0359 ;foreground graphics colour +CF60 LDY &035B ;foreground graphics plot mode (GCOL n) +CF63 JSR &D0B3 ;set graphics byte mask in &D4/5 +CF66 JSR &D486 ;copy (324/7) graphics cursor to workspace (328/B) +CF69 LDY #&00 ;Y=0 +CF6B STY &DC ;&DC=Y +CF6D LDY &DC ;Y=&DC +CF6F LDA (&DE),Y ;get pattern byte +CF71 BEQ &CF86 ;if A=0 CF86 +CF73 STA &DD ;else &DD=A +CF75 BPL &CF7A ;and if >0 CF7A +CF77 JSR &D0E3 ;else display a pixel +CF7A INC &0324 ;current horizontal graphics cursor +CF7D BNE &CF82 ; +CF7F INC &0325 ;current horizontal graphics cursor + +CF82 ASL &DD ;&DD=&DD*2 +CF84 BNE &CF75 ;and if<>0 CF75 +CF86 LDX #&28 ;point to workspace +CF88 LDY #&24 ;point to horizontal graphics cursor +CF8A JSR &D482 ;0300/1+Y=0300/1+X +CF8D LDY &0326 ;current vertical graphics cursor +CF90 BNE &CF95 ; +CF92 DEC &0327 ;current vertical graphics cursor +CF95 DEC &0326 ;current vertical graphics cursor +CF98 LDY &DC ; +CF9A INY ; +CF9B CPY #&08 ;if Y<8 then do loop again +CF9D BNE &CF6B ;else +CF9F LDX #&28 ;point to workspace +CFA1 LDY #&24 ;point to graphics cursor +CFA3 JMP &D48A ;(&300/3+Y)=(&300/3+X) + +*********** home graphics cursor *************************************** + +CFA6 LDX #&06 ;point to graphics window TOP +CFA8 LDY #&26 ;point to workspace +CFAA JSR &D482 ;0300/1+Y=0300/1+X + +************* set graphics cursor to left hand column ******************* + +CFAD LDX #&00 ;X=0 point to graphics window left +CFAF LDY #&24 ;Y=&24 +CFB1 JSR &D482 ;0300/1+Y=0300/1+X +CFB4 JMP &D1B8 ;set up external coordinates for graphics +CFB7 LDX &0360 ;number of logical colours less 1 +CFBA BEQ &CFDC ;if MODE 7 CFDC + +CFBC JSR &D03E ;set up character definition pointers +CFBF LDX &0360 ;number of logical colours less 1 +CFC2 LDA &D0 ;VDU status byte +CFC4 AND #&20 ;and out bit 5 printing at graphics cursor +CFC6 BNE &CF5D ;if set CF5D +CFC8 LDY #&07 ;else Y=7 +CFCA CPX #&03 ;if X=3 +CFCC BEQ &CFEE ;goto CFEE to handle 4 colour modes +CFCE BCS &D01E ;else if X>3 D01E to deal with 16 colours + +CFD0 LDA (&DE),Y ;get pattern byte +CFD2 ORA &D2 ;text colour byte to be orred or EORed into memory +CFD4 EOR &D3 ;text colour byte to be orred or EORed into memory +CFD6 STA (&D8),Y ; write to screen +CFD8 DEY ;Y=Y-1 +CFD9 BPL &CFD0 ;if still +ve do loop again +CFDB RTS ;and exit + +******* convert teletext characters ************************************* +;mode 7 +CFDC LDY #&02 ;Y=2 +CFDE CMP &C4B6,Y ;compare with teletext conversion table +CFE1 BEQ &CFE9 ;if equal then CFE9 +CFE3 DEY ;else Y=Y-1 +CFE4 BPL &CFDE ;and if +ve CFDE + +CFE6 STA (&D8,X) ;if not write byte to screen +CFE8 RTS ;and exit + +CFE9 LDA &C4B7,Y ;convert with teletext conversion table +CFEC BNE &CFE6 ;and write it + +***********four colour modes ******************************************** + +CFEE LDA (&DE),Y ;get pattern byte +CFF0 PHA ;save it +CFF1 LSR ;move hi nybble to lo +CFF2 LSR ; +CFF3 LSR ; +CFF4 LSR ; +CFF5 TAX ;X=A +CFF6 LDA &C31F,X ;4 colour mode byte mask look up table +CFF9 ORA &D2 ;text colour byte to be orred or EORed into memory +CFFB EOR &D3 ;text colour byte to be orred or EORed into memory +CFFD STA (&D8),Y ; write to screen +CFFF TYA ;A=Y + +D000 CLC ;clear carry +D001 ADC #&08 ;add 8 to move screen RAM pointer 8 bytes +D003 TAY ;Y=A +D004 PLA ;get back A +D005 AND #&0F ;clear high nybble +D007 TAX ;X=A +D008 LDA &C31F,X ;4 colour mode byte mask look up table +D00B ORA &D2 ;text colour byte to be orred or EORed into memory +D00D EOR &D3 ;text colour byte to be orred or EORed into memory +D00F STA (&D8),Y ; write to screen +D011 TYA ;A=Y +D012 SBC #&08 ;A=A-9 +D014 TAY ;Y=A +D015 BPL &CFEE ;if +ve do loop again +D017 RTS ;exit + +D018 TYA ;Y=Y-&21 +D019 SBC #&21 ; +D01B BMI &D017 ;IF Y IS negative then RETURN +D01D TAY ;else A=Y + +******* 16 COLOUR MODES ************************************************* + +D01E LDA (&DE),Y ;get pattern byte +D020 STA &DC ;store it +D022 SEC ;set carry +D023 LDA #&00 ;A=0 +D025 ROL &DC ;carry now occupies bit 0 of DC +D027 BEQ &D018 ;when DC=0 again D018 to deal with next pattern byte +D029 ROL ;get bit 7 from &DC into A bit 0 +D02A ASL &DC ;rotate again to get second +D02C ROL ;bit into A +D02D TAX ;and store result in X +D02E LDA &C32F,X ;multiply by &55 using look up table +D031 ORA &D2 ;and set colour factors +D033 EOR &D3 ; +D035 STA (&D8),Y ;and store result +D037 CLC ;clear carry +D038 TYA ;Y=Y+8 moving screen RAM pointer on 8 bytes +D039 ADC #&08 ; +D03B TAY ; +D03C BCC &D023 ;iloop to D023 to deal with next bit pair + +************* calculate pattern address for given code ****************** +;A contains code on entry = 12345678 + +D03E ASL ;23456780 C holds 1 +D03F ROL ;34567801 C holds 2 +D040 ROL ;45678012 C holds 3 +D041 STA &DE ;save this pattern +D043 AND #&03 ;00000012 +D045 ROL ;00000123 C=0 +D046 TAX ;X=A=0 - 7 +D047 AND #&03 ;A=00000023 +D049 ADC #&BF ;A=&BF,C0 or C1 +D04B TAY ;this is used as a pointer +D04C LDA &C40D,X ;A=&80/2^X i.e.1,2,4,8,&10,&20,&40, or &80 +D04F BIT &0367 ;with font flag +D052 BEQ &D057 ;if 0 D057 +D054 LDY &0367,X ;else get hi byte from table +D057 STY &DF ;store Y +D059 LDA &DE ;get back pattern +D05B AND #&F8 ;convert to 45678000 +D05D STA &DE ;and re store it +D05F RTS ;exit + + +************************************************************************* +************************************************************************* +** ** +** ** +** PLOT ROUTINES ENTER HERE ** +** ** +** ** +************************************************************************* +************************************************************************* +;on entry ADDRESS PARAMETER DESCRIPTION +; 031F 1 plot type +; 0320/1 2,3 X coordinate +; 0322/3 4,5 Y coordinate + +D060 LDX #&20 ;X=&20 +D062 JSR &D14D ;translate coordinates + +D065 LDA &031F ;get plot type +D068 CMP #&04 ;if its 4 +D06A BEQ &D0D9 ;D0D9 move absolute +D06C LDY #&05 ;Y=5 +D06E AND #&03 ;mask only bits 0 and 1 +D070 BEQ &D080 ;if result is 0 then its a move (multiple of 8) +D072 LSR ;else move bit 0 int C +D073 BCS &D078 ;if set then D078 graphics colour required +D075 DEY ;Y=4 +D076 BNE &D080 ;logic inverse colour must be wanted + +******** graphics colour wanted ***************************************** + +D078 TAX ;X=A if A=0 its a foreground colour 1 its background +D079 LDY &035B,X ;get fore or background graphics PLOT mode +D07C LDA &0359,X ;get fore or background graphics colour +D07F TAX ;X=A + +D080 JSR &D0B3 ;set up colour masks in D4/5 + +D083 LDA &031F ;get plot type +D086 BMI &D0AB ;if &80-&FF then D0AB type not implemented +D088 ASL ;bit 7=bit 6 +D089 BPL &D0C6 ;if bit 6 is 0 then plot type is 0-63 so D0C6 +D08B AND #&F0 ;else mask out lower nybble +D08D ASL ;shift old bit 6 into C bit old 5 into bit 7 +D08E BEQ &D0D6 ;if 0 then type 64-71 was called single point plot + ;goto D0D6 +D090 EOR #&40 ;if bit 6 NOT set type &80-&87 fill triangle +D092 BEQ &D0A8 ;so D0A8 +D094 PHA ;else push A +D095 JSR &D0DC ;copy 0320/3 to 0324/7 setting XY in current graphics + ;coordinates +D098 PLA ;get back A +D099 EOR #&60 ;if BITS 6 and 5 NOT SET type 72-79 lateral fill +D09B BEQ &D0AE ;so D0AE +D09D CMP #&40 ;if type 88-95 horizontal line blanking +D09F BNE &D0AB ;so D0AB + +D0A1 LDA #&02 ;else A=2 +D0A3 STA &DC ;store it +D0A5 JMP &D506 ;and jump to D506 type not implemented + +D0A8 JMP &D5EA ;to fill triangle routine + +D0AB JMP &C938 ;VDU extension access entry + +D0AE STA &DC ;store A +D0B0 JMP &D4BF ; + +*********:set colour masks ********************************************** +;graphics mode in Y +;colour in X + +D0B3 TXA ;A=X +D0B4 ORA &C41C,Y ;or with GCOL plot options table byte +D0B7 EOR &C41D,Y ;EOR with following byte +D0BA STA &D4 ;and store it +D0BC TXA ;A=X +D0BD ORA &C41B,Y ; +D0C0 EOR &C420,Y ; +D0C3 STA &D5 ; +D0C5 RTS ;exit with masks in &D4/5 + +************** analyse first parameter in 0-63 range ******************** + ; +D0C6 ASL ;shift left again +D0C7 BMI &D0AB ;if -ve options are in range 32-63 not implemented +D0C9 ASL ;shift left twice more +D0CA ASL ; +D0CB BPL &D0D0 ;if still +ve type is 0-7 or 16-23 so D0D0 +D0CD JSR &D0EB ;else display a point + +D0D0 JSR &D1ED ;perform calculations +D0D3 JMP &D0D9 ; + + +************************************************************************* +* * +* PLOT A SINGLE POINT * +* * +************************************************************************* + +D0D6 JSR &D0EB ;display a point +D0D9 JSR &CDE2 ;swap current and last graphics position +D0DC LDY #&24 ;Y=&24 +D0DE LDX #&20 ;X=&20 +D0E0 JMP &D48A ;copy parameters to 324/7 (300/3 +Y) + +D0E3 LDX #&24 ; +D0E5 JSR &D85F ;calculate position +D0E8 BEQ &D0F0 ;if result =0 then D0F0 +D0EA RTS ;else exit + ; +D0EB JSR &D85D ;calculate position +D0EE BNE &D103 ;if A<>0 D103 and return +D0F0 LDY &031A ;else get current graphics scan line +D0F3 LDA &D1 ;pick up and modify screen byte +D0F5 AND &D4 ; +D0F7 ORA (&D6),Y ; +D0F9 STA &DA ; +D0FB LDA &D5 ; +D0FD AND &D1 ; +D0FF EOR &DA ; +D101 STA (&D6),Y ;put it back again +D103 RTS ;and exit + +D104 LDA (&D6),Y ;this is a more simplistic version of the above +D106 ORA &D4 ; +D108 EOR &D5 ; +D10A STA (&D6),Y ; +D10C RTS ;and exit + +************************** Check window limits ************************* + ; +D10D LDX #&24 ;X=&24 +D10F LDY #&00 ;Y=0 +D111 STY &DA ;&DA=0 +D113 LDY #&02 ;Y=2 +D115 JSR &D128 ;check vertical graphics position 326/7 + ;bottom and top margins 302/3, 306/7 +D118 ASL &DA ;DATA is set in &DA bits 0 and 1 then shift left +D11A ASL &DA ;twice to make room for next pass +D11C DEX ;X=&22 +D11D DEX ; +D11E LDY #&00 ;Y=0 +D120 JSR &D128 ;left and right margins 300/1, 304/5 + ;cursor horizontal position 324/5 +D123 INX ;X=X+2 +D124 INX ; +D125 LDA &DA ;A=&DA +D127 RTS ;exit + +*** cursor and margins check ****************************************** + ; +D128 LDA &0302,X ;check for window violation +D12B CMP &0300,Y ;300/1 +Y > 302/3+X +D12E LDA &0303,X ;then window fault +D131 SBC &0301,Y ; +D134 BMI &D146 ;so D146 + +D136 LDA &0304,Y ;check other windows +D139 CMP &0302,X ; +D13C LDA &0305,Y ; +D13F SBC &0303,X ; +D142 BPL &D148 ;if no violation exit +D144 INC &DA ;else DA=DA+1 + +D146 INC &DA ;DA=DA+1 +D148 RTS ;and exit DA=0 no problems DA=1 first check 2, 2nd + +***********set up and adjust positional data **************************** + +D149 LDA #&FF ;A=&FF +D14B BNE &D150 ;then &D150 + +D14D LDA &031F ;get first parameter in plot + +D150 STA &DA ;store in &DA +D152 LDY #&02 ;Y=2 +D154 JSR &D176 ;set up vertical coordinates/2 +D157 JSR &D1AD ;/2 again to convert 1023 to 0-255 for internal use + ;this is why minimum vertical plot separation is 4 +D15A LDY #&00 ;Y=0 +D15C DEX ;X=x-2 +D15D DEX ; +D15E JSR &D176 ;set up horiz. coordinates/2 this is OK for mode0,4 +D161 LDY &0361 ;get number of pixels/byte (-1) +D164 CPY #&03 ;if Y=3 (modes 1 and 5) +D166 BEQ &D16D ;D16D +D168 BCS &D170 ;for modes 0 & 4 this is 7 so D170 +D16A JSR &D1AD ;for other modes divide by 2 twice + +D16D JSR &D1AD ;divide by 2 +D170 LDA &0356 ;get screen display type +D173 BNE &D1AD ;if not 0 (modes 3-7) divide by 2 again +D175 RTS ;and exit + +;for mode 0 1 division 1280 becomes 640 = horizontal resolution +;for mode 1 2 divisions 1280 becomes 320 = horizontal resolution +;for mode 2 3 divisions 1280 becomes 160 = horizontal resolution +;for mode 4 2 divisions 1280 becomes 320 = horizontal resolution +;for mode 5 3 divisions 1280 becomes 160 = horizontal resolution + +********** calculate external coordinates in internal format *********** +;on entry X is usually &1E or &20 + +D176 CLC ;clear carry +D177 LDA &DA ;get &DA +D179 AND #&04 ;if bit 2=0 +D17B BEQ &D186 ;then D186 to calculate relative coordinates +D17D LDA &0302,X ;else get coordinate +D180 PHA ; +D181 LDA &0303,X ; +D184 BCC &D194 ;and goto D194 + +D186 LDA &0302,X ;get coordinate +D189 ADC &0310,Y ;add cursor position +D18C PHA ;save it +D18D LDA &0303,X ; +D190 ADC &0311,Y ;add cursor +D193 CLC ;clear carry + +D194 STA &0311,Y ;save new cursor +D197 ADC &030D,Y ;add graphics origin +D19A STA &0303,X ;store it +D19D PLA ;get back lo byte +D19E STA &0310,Y ;save it in new cursor lo +D1A1 CLC ;clear carry +D1A2 ADC &030C,Y ;add to graphics orgin +D1A5 STA &0302,X ;store it +D1A8 BCC &D1AD ;if carry set +D1AA INC &0303,X ;increment hi byte as you would expect! + +D1AD LDA &0303,X ;get hi byte +D1B0 ASL ; +D1B1 ROR &0303,X ;divide by 2 +D1B4 ROR &0302,X ; +D1B7 RTS ;and exit + +***** calculate external coordinates from internal coordinates************ + +D1B8 LDY #&10 ;Y=10 +D1BA JSR &D488 ;copy 324/7 to 310/3 i.e.current graphics cursor + ;position to position in external values +D1BD LDX #&02 ;X=2 +D1BF LDY #&02 ;Y=2 +D1C1 JSR &D1D5 ;multiply 312/3 by 4 and subtract graphics origin +D1C4 LDX #&00 ;X=0 +D1C6 LDY #&04 ;Y=4 +D1C8 LDA &0361 ;get number of pixels/byte +D1CB DEY ;Y=Y-1 +D1CC LSR ;divide by 2 +D1CD BNE &D1CB ;if result not 0 D1CB +D1CF LDA &0356 ;else get screen display type +D1D2 BEQ &D1D5 ;and if 0 D1D5 +D1D4 INY ; + +D1D5 ASL &0310,X ;multiply coordinate by 2 +D1D8 ROL &0311,X ; +D1DB DEY ;Y-Y-1 +D1DC BNE &D1D5 ;and if Y<>0 do it again +D1DE SEC ;set carry +D1DF JSR &D1E3 ; +D1E2 INX ;increment X + +D1E3 LDA &0310,X ;get current graphics position in external coordinates +D1E6 SBC &030C,X ;subtract origin +D1E9 STA &0310,X ;store in graphics position +D1EC RTS ;and exit + +************* compare X and Y PLOT spans ******************************** + +D1ED JSR &D40D ;Set X and Y spans in workspace 328/9 32A/B +D1F0 LDA &032B ;compare spans +D1F3 EOR &0329 ;if result -ve spans are different in sign so +D1F6 BMI &D207 ;goto D207 +D1F8 LDA &032A ;else A=hi byte of difference in spans +D1FB CMP &0328 ; +D1FE LDA &032B ; +D201 SBC &0329 ; +D204 JMP &D214 ;and goto D214 + +D207 LDA &0328 ;A = hi byte of SUM of spans +D20A CLC ; +D20B ADC &032A ; +D20E LDA &0329 ; +D211 ADC &032B ; + +D214 ROR ;A=A/2 +D215 LDX #&00 ;X=0 +D217 EOR &032B ; +D21A BPL &D21E ;if positive result D21E + +D21C LDX #&02 ;else X=2 + +D21E STX &DE ;store it +D220 LDA &C4AA,X ;set up vector address +D223 STA &035D ;in 35D +D226 LDA &C4AB,X ; +D229 STA &035E ;and 35E +D22C LDA &0329,X ;get hi byte of span +D22F BPL &D235 ;if +ve D235 +D231 LDX #&24 ;X=&24 +D233 BNE &D237 ;jump to D237 + +D235 LDX #&20 ;X=&20 +D237 STX &DF ;store it +D239 LDY #&2C ;Y=&2C +D23B JSR &D48A ;get X coordinate data or horizontal coord of + ;curent graphics cursor +D23E LDA &DF ;get back original X +D240 EOR #&04 ;covert &20 to &24 and vice versa +D242 STA &DD ; +D244 ORA &DE ; +D246 TAX ; +D247 JSR &D480 ;copy 330/1 to 300/1+X +D24A LDA &031F ;get plot type +D24D AND #&10 ;check bit 4 +D24F ASL ; +D250 ASL ; +D251 ASL ;move to bit 7 +D252 STA &DB ;store it +D254 LDX #&2C ;X=&2C +D256 JSR &D10F ;check for window violations +D259 STA &DC ; +D25B BEQ &D263 ;if none then D263 +D25D LDA #&40 ;else set bit 6 of &DB +D25F ORA &DB ; +D261 STA &DB ; + +D263 LDX &DD ; +D265 JSR &D10F ;check window violations again +D268 BIT &DC ;if bit 7 of &DC NOT set +D26A BEQ &D26D ;D26D +D26C RTS ;else exit + ; +D26D LDX &DE ;X=&DE +D26F BEQ &D273 ;if X=0 D273 +D271 LSR ;A=A/2 +D272 LSR ;A=A/2 + +D273 AND #&02 ;clear all but bit 2 +D275 BEQ &D27E ;if bit 2 set D27E +D277 TXA ;else A=X +D278 ORA #&04 ;A=A or 4 setting bit 3 +D27A TAX ;X=A +D27B JSR &D480 ;set 300/1+x to 330/1 +D27E JSR &D42C ;more calcualtions +D281 LDA &DE ;A=&DE EOR 2 +D283 EOR #&02 ; +D285 TAX ;X=A +D286 TAY ;Y=A +D287 LDA &0329 ;compare upper byte of spans +D28A EOR &032B ; +D28D BPL &D290 ;if signs are the same D290 +D28F INX ;else X=X+1 +D290 LDA &C4AE,X ;get vector addresses and store 332/3 +D293 STA &0332 ; +D296 LDA &C4B2,X ; +D299 STA &0333 ; + +D29C LDA #&7F ;A=&7F +D29E STA &0334 ;store it +D2A1 BIT &DB ;if bit 6 set +D2A3 BVS &D2CE ;the D2CE +D2A5 LDA &C447,X ;get VDU section number +D2A8 TAX ;X=A +D2A9 SEC ;set carry +D2AA LDA &0300,X ;subtract coordinates +D2AD SBC &032C,Y ; +D2B0 STA &DA ; +D2B2 LDA &0301,X ; +D2B5 SBC &032D,Y ; +D2B8 LDY &DA ;Y=hi +D2BA TAX ;X=lo=A +D2BB BPL &D2C0 ;and if A+Ve D2C0 +D2BD JSR &D49B ;negate Y/A + +D2C0 TAX ;X=A increment Y/A +D2C1 INY ;Y=Y+1 +D2C2 BNE &D2C5 ; +D2C4 INX ;X=X+1 +D2C5 TXA ;A=X +D2C6 BEQ &D2CA ;if A=0 D2CA +D2C8 LDY #&00 ;else Y=0 + +D2CA STY &DF ;&DF=Y +D2CC BEQ &D2D7 ;if 0 then D2D7 +D2CE TXA ;A=X +D2CF LSR ;A=A/4 +D2D0 ROR ; +D2D1 ORA #&02 ;bit 1 set +D2D3 EOR &DE ; +D2D5 STA &DE ;and store +D2D7 LDX #&2C ;X=&2C +D2D9 JSR &D864 ; +D2DC LDX &DC ; +D2DE BNE &D2E2 ; +D2E0 DEC &DD ; +D2E2 DEX ;X=X-1 +D2E3 LDA &DB ;A=&3B +D2E5 BEQ &D306 ;if 0 D306 +D2E7 BPL &D2F9 ;else if +ve D2F9 +D2E9 BIT &0334 ; +D2EC BPL &D2F3 ;if bit 7=0 D2F3 +D2EE DEC &0334 ;else decrement +D2F1 BNE &D316 ;and if not 0 D316 + +D2F3 INC &0334 ; +D2F6 ASL ;A=A*2 +D2F7 BPL &D306 ;if +ve D306 +D2F9 STX &DC ; +D2FB LDX #&2C ; +D2FD JSR &D85F ;calcualte screen position +D300 LDX &DC ;get back original X +D302 ORA #&00 ; +D304 BNE &D316 ; +D306 LDA &D1 ;byte mask for current graphics point +D308 AND &D4 ;and with graphics colour byte +D30A ORA (&D6),Y ;or with curent graphics cell line +D30C STA &DA ;store result +D30E LDA &D5 ;same again with next byte (hi??) +D310 AND &D1 ; +D312 EOR &DA ; +D314 STA (&D6),Y ;then store it inm current graphics line +D316 SEC ;set carry +D317 LDA &0335 ;A=&335/6-&337/8 +D31A SBC &0337 ; +D31D STA &0335 ; +D320 LDA &0336 ; +D323 SBC &0338 ; +D326 BCS &D339 ;if carry set D339 +D328 STA &DA ; +D32A LDA &0335 ; +D32D ADC &0339 ; +D330 STA &0335 ; +D333 LDA &DA ; +D335 ADC &033A ; +D338 CLC ; +D339 STA &0336 ; +D33C PHP ; +D33D BCS &D348 ;if carry clear jump to VDU routine else D348 +D33F JMP (&0332) ; + +****** vertical scan module 1****************************************** + +D342 DEY ;Y=Y-1 +D343 BPL &D348 ;if + D348 +D345 JSR &D3D3 ;else d3d3 to advance pointers +D348 JMP (&035D) ;and JUMP (&35D) + +****** vertical scan module 2****************************************** + +D34B INY ;Y=Y+1 +D34C CPY #&08 ;if Y<>8 +D34E BNE &D348 ;then D348 +D350 CLC ;else clear carry +D351 LDA &D6 ;get address of top line of cuirrent graphics cell +D353 ADC &0352 ;add number of bytes/character row +D356 STA &D6 ;store it +D358 LDA &D7 ;do same for hibyte +D35A ADC &0353 ; +D35D BPL &D363 ;if result -ve then we are above screen RAM +D35F SEC ;so +D360 SBC &0354 ;subtract screen memory size hi +D363 STA &D7 ;store it this wraps around point to screen RAM +D365 LDY #&00 ;Y=0 +D367 JMP (&035D) ; + +****** horizontal scan module 1****************************************** + +D36A LSR &D1 ;shift byte mask +D36C BCC &D348 ;if carry clear (&D1 was +ve) goto D348 +D36E JSR &D3ED ;else reset pointers +D371 JMP (&035D) ;and off to do more + +****** horizontal scan module 2****************************************** + +D374 ASL &D1 ;shift byte mask +D376 BCC &D348 ;if carry clear (&D1 was +ve) goto D348 +D378 JSR &D3FD ;else reset pointers +D37B JMP (&035D) ;and off to do more + +D37E DEY ;Y=Y-1 +D37F BPL &D38D ;if +ve D38D +D381 JSR &D3D3 ;advance pointers +D384 BNE &D38D ;goto D38D normally +D386 LSR &D1 ;shift byte mask +D388 BCC &D38D ;if carry clear (&D1 was +ve) goto D348 +D38A JSR &D3ED ;else reset pointers +D38D PLP ;pull flags +D38E INX ;X=X+1 +D38F BNE &D395 ;if X>0 D395 +D391 INC &DD ;else increment &DD +D393 BEQ &D39F ;and if not 0 D39F +D395 BIT &DB ;else if BIT 6 = 1 +D397 BVS &D3A0 ;goto D3A0 +D399 BCS &D3D0 ;if BIT 7=1 D3D0 +D39B DEC &DF ;else Decrement &DF +D39D BNE &D3D0 ;and if not Zero D3D0 +D39F RTS ;else return + ; +D3A0 LDA &DE ;A=&DE +D3A2 STX &DC ;&DC=X +D3A4 AND #&02 ;clear all but bit 1 +D3A6 TAX ;X=A +D3A7 BCS &D3C2 ;and if carry set goto D3C2 +D3A9 BIT &DE ;if Bit 7 of &DE =1 +D3AB BMI &D3B7 ;then D3B7 +D3AD INC &032C,X ;else increment +D3B0 BNE &D3C2 ;and if not 0 D3C2 +D3B2 INC &032D,X ;else increment hi byte +D3B5 BCC &D3C2 ;and if carry clear D3C2 +D3B7 LDA &032C,X ;esle A=32C,X +D3BA BNE &D3BF ;and if not 0 D3BF +D3BC DEC &032D,X ;decrement hi byte +D3BF DEC &032C,X ;decrement lo byte + +D3C2 TXA ;A=X +D3C3 EOR #&02 ;invert bit 2 +D3C5 TAX ;X=A +D3C6 INC &032C,X ;Increment 32C/D +D3C9 BNE &D3CE ; +D3CB INC &032D,X ; +D3CE LDX &DC ;X=&DC +D3D0 JMP &D2E3 ;jump to D2E3 + +**********move display point up a line ********************************** +D3D3 SEC ;SET CARRY +D3D4 LDA &D6 ;subtract number of bytes/line from address of +D3D6 SBC &0352 ;top line of current graphics cell +D3D9 STA &D6 ; +D3DB LDA &D7 ; +D3DD SBC &0353 ; +D3E0 CMP &034E ;compare with bottom of screen memory +D3E3 BCS &D3E8 ;if outside screen RAM +D3E5 ADC &0354 ;add screen memory size to wrap it around +D3E8 STA &D7 ;store in current address of graphics cell top line +D3EA LDY #&07 ;Y=7 +D3EC RTS ;and RETURN + +D3ED LDA &0362 ;get current left colour mask +D3F0 STA &D1 ;store it +D3F2 LDA &D6 ;get current top line of graphics cell +D3F4 ADC #&07 ;ADD 7 +D3F6 STA &D6 ; +D3F8 BCC &D3FC ; +D3FA INC &D7 ; +D3FC RTS ;and return + +D3FD LDA &0363 ;get right colour mask +D400 STA &D1 ;store it +D402 LDA &D6 ;A=top line graphics cell low +D404 BNE &D408 ;if not 0 D408 +D406 DEC &D7 ;else decrement hi byte + +D408 SBC #&08 ;subtract 9 (8 + carry) +D40A STA &D6 ;and store in low byte +D40C RTS ;return + +********:: coordinate subtraction *************************************** + +D40D LDY #&28 ;X=&28 +D40F LDX #&20 ;Y=&20 +D411 JSR &D418 ; +D414 INX ;X=X+2 +D415 INX ; +D416 INY ;Y=Y+2 +D417 INY ; + +D418 SEC ;set carry +D419 LDA &0304,X ;subtract coordinates +D41C SBC &0300,X ; +D41F STA &0300,Y ; +D422 LDA &0305,X ; +D425 SBC &0301,X ; +D428 STA &0301,Y ; +D42B RTS ;and return + +D42C LDA &DE ;A=&DE +D42E BNE &D437 ;if A=0 D437 +D430 LDX #&28 ;X=&28 +D432 LDY #&2A ;Y=&2A +D434 JSR &CDDE ;exchange 300/1+Y with 300/1+X + ;IN THIS CASE THE X AND Y SPANS! + +D437 LDX #&28 ;X=&28 +D439 LDY #&37 ;Y=&37 +D43B JSR &D48A ;copy &300/4+Y to &300/4+X + ;transferring X and Y spans in this case +D43E SEC ;set carry +D43F LDX &DE ;X=&DE +D441 LDA &0330 ;subtract 32C/D,X from 330/1 +D444 SBC &032C,X ; +D447 TAY ;partial answer in Y +D448 LDA &0331 ; +D44B SBC &032D,X ; +D44E BMI &D453 ;if -ve D453 +D450 JSR &D49B ;else negate Y/A + +D453 STA &DD ;store A +D455 STY &DC ;and Y +D457 LDX #&35 ;X=&35 +D459 JSR &D467 ;get coordinates +D45C LSR ; +D45D STA &0301,X ; +D460 TYA ; +D461 ROR ; +D462 STA &0300,X ; +D465 DEX ; +D466 DEX ; + +D467 LDY &0304,X ; +D46A LDA &0305,X ; +D46D BPL &D47B ;if A is +ve RETURN +D46F JSR &D49B ;else negate Y/A +D472 STA &0305,X ;store back again +D475 PHA ; +D476 TYA ; +D477 STA &0304,X ; +D47A PLA ;get back A +D47B RTS ;and exit + ; +D47C LDA #&08 ;A=8 +D47E BNE &D48C ;copy 8 bytes +D480 LDY #&30 ;Y=&30 +D482 LDA #&02 ;A=2 +D484 BNE &D48C ;copy 2 bytes +D486 LDY #&28 ;copy 4 bytes from 324/7 to 328/B +D488 LDX #&24 ; +D48A LDA #&04 ; + +***********copy A bytes from 300,X to 300,Y *************************** + +D48C STA &DA ; +D48E LDA &0300,X ; +D491 STA &0300,Y ; +D494 INX ; +D495 INY ; +D496 DEC &DA ; +D498 BNE &D48E ; +D49A RTS ;and return + +************* negation routine ****************************************** + +D49B PHA ;save A +D49C TYA ;A=Y +D49D EOR #&FF ;invert +D49F TAY ;Y=A +D4A0 PLA ;get back A +D4A1 EOR #&FF ;invert +D4A3 INY ;Y=Y+1 +D4A4 BNE &D4A9 ;if not 0 exit +D4A6 CLC ;else +D4A7 ADC #&01 ;add 1 to A +D4A9 RTS ;return + ; +D4AA JSR &D85D ;check window boundaries and set up screen pointer +D4AD BNE &D4B7 ;if A<>0 D4B7 +D4AF LDA (&D6),Y ;else get byte from current graphics cell +D4B1 EOR &035A ;compare with current background colour +D4B4 STA &DA ;store it +D4B6 RTS ;and RETURN + +D4B7 PLA ;get back return link +D4B8 PLA ; +D4B9 INC &0326 ;increment current graphics cursor vertical lo +D4BC JMP &D545 ; + +OS SERIES IV +GEOFF COX + +************************************************************************* +* * +* LATERAL FILL ROUTINE * +* * +************************************************************************* + +D4BF JSR &D4AA ;check current screen state +D4C2 AND &D1 ;if A and &D1 <> 0 a plotted point has been found +D4C4 BNE &D4B9 ;so D4B9 +D4C6 LDX #&00 ;X=0 +D4C8 JSR &D592 ;update pointers +D4CB BEQ &D4FA ;if 0 then D4FA +D4CD LDY &031A ;else Y=graphics scan line +D4D0 ASL &D1 ; +D4D2 BCS &D4D9 ;if carry set D4D9 +D4D4 JSR &D574 ;else D574 +D4D7 BCC &D4FA ;if carry clear D4FA +D4D9 JSR &D3FD ;else D3FD to pick up colour multiplier +D4DC LDA (&D6),Y ;get graphics cell line +D4DE EOR &035A ;EOR with background colour +D4E1 STA &DA ;and store +D4E3 BNE &D4F7 ;if not 0 D4F7 +D4E5 SEC ;else set carry +D4E6 TXA ;A=X +D4E7 ADC &0361 ;add pixels/byte +D4EA BCC &D4F0 ;and if carry clear D4F0 +D4EC INC &DB ;else increment &DB +D4EE BPL &D4F7 ;and if +ve D4F7 + +D4F0 TAX ;else X=A +D4F1 JSR &D104 ;display a pixel +D4F4 SEC ;set carry +D4F5 BCS &D4D9 ;goto D4D9 + +D4F7 JSR &D574 ; +D4FA LDY #&00 ;Y=0 +D4FC JSR &D5AC ; +D4FF LDY #&20 ; +D501 LDX #&24 ; +D503 JSR &CDE6 ;exchange 300/3 +Y with 300/3+X +D506 JSR &D4AA ;check screen pixel +D509 LDX #&04 ;Y=5 +D50B JSR &D592 ; +D50E TXA ;A=x +D50F BNE &D513 ;if A<>0 d513 +D511 DEC &DB ;else &DB=&dB-1 + +D513 DEX ;X=X-1 +D514 JSR &D54B ; +D517 BCC &D540 ; +D519 JSR &D3ED ;update pointers +D51C LDA (&D6),Y ;get byte from graphics line +D51E EOR &035A ;EOR with background colour +D521 STA &DA ;and store it +D523 LDA &DC ; +D525 BNE &D514 ;If A-0 back to D514 +D527 LDA &DA ;else A=&DA +D529 BNE &D53D ;if A<>d53D +D52B SEC ;else set carry +D52C TXA ;A=x +D52D ADC &0361 ;Add number of pixels/byte +D530 BCC &D536 ;and if carry clear D536 +D532 INC &DB ;else inc DB +D534 BPL &D53D ;and if +ve D53D +D536 TAX ;get back X +D537 JSR &D104 ;display a point +D53A SEC ;set carry +D53B BCS &D519 ;goto D519 + +D53D JSR &D54B ; +D540 LDY #&04 ; +D542 JSR &D5AC ; + +D545 JSR &D0D9 ; +D548 JMP &D1B8 ;scale pointers + +D54B LDA &D1 ;get byte mask +D54D PHA ;save it +D54E CLC ;clear carry +D54F BCC &D560 ; + +D551 PLA ;get back A +D552 INX ;X=X+1 +D553 BNE &D559 ;if not 0 D559 +D555 INC &DB ;else inc &DB +D557 BPL &D56F ;if +ve D56F +D559 LSR &D1 ; +D55B BCS &D56F ;if Bit 7 D1 set D56F +D55D ORA &D1 ;else or withA +D55F PHA ;save result +D560 LDA &D1 ;A=&D1 +D562 BIT &DA ;test bits 6 and 7 of &DA +D564 PHP ;save flags +D565 PLA ;get into A +D566 EOR &DC ;EOR and DC +D568 PHA ;save A +D569 PLP ; +D56A BEQ &D551 ; + +D56C PLA ;A=A EOR &D1 (byte mask) +D56D EOR &D1 ; +D56F STA &D1 ;store it +D571 JMP &D0F0 ;and display a pixel + +D574 LDA #&00 ;A=0 +D576 CLC ;Clear carry + +D577 BCC &D583 ;goto D583 if carry clear + +D579 INX ;X=X+1 +D57A BNE &D580 ;If <>0 D580 +D57C INC &DB ;else inc &DB +D57E BPL &D56F ;and if +ve d56F + +D580 ASL ;A=A*2 +D581 BCS &D58E ;if C set D58E +D583 ORA &D1 ;else A=A OR (&D1) +D585 BIT &DA ;set V and M from &DA b6 b7 +D587 BEQ &D579 ; +D589 EOR &D1 ;A=AEOR &D1 +D58B LSR ;/2 +D58C BCC &D56F ;if carry clear D56F +D58E ROR ;*2 +D58F SEC ;set carry +D590 BCS &D56F ;to D56F + +D592 LDA &0300,X ;Y/A=(&300/1 +X)-(&320/1) +D595 SEC ; +D596 SBC &0320 ; +D599 TAY ; +D59A LDA &0301,X ; +D59D SBC &0321 ; +D5A0 BMI &D5A5 ;if result -ve D5A5 +D5A2 JSR &D49B ;or negate Y/A +D5A5 STA &DB ;store A +D5A7 TYA ;A=Y +D5A8 TAX ;X=A +D5A9 ORA &DB ; +D5AB RTS ;exit + +D5AC STY &DA ;Y=&DA +D5AE TXA ;A=X +D5AF TAY ;Y=A +D5B0 LDA &DB ;A=&DB +D5B2 BMI &D5B6 ;if -ve D5B6 +D5B4 LDA #&00 ;A=0 +D5B6 LDX &DA ;X=&DA +D5B8 BNE &D5BD ;if <>0 D5BD +D5BA JSR &D49B ;negate +D5BD PHA ; +D5BE CLC ; +D5BF TYA ; +D5C0 ADC &0300,X ;Y/A+(&300/1 +X)=(&320/1) +D5C3 STA &0320 ; +D5C6 PLA ; +D5C7 ADC &0301,X ; +D5CA STA &0321 ; +D5CD RTS ;return + + +************************************************************************* +* * +* OSWORD 13 - READ LAST TWO GRAPHIC CURSOR POSITIONS * +* * +************************************************************************* + ; +D5CE LDA #&03 ;A=3 +D5D0 JSR &D5D5 ; +D5D3 LDA #&07 ;A=7 +D5D5 PHA ;Save A +D5D6 JSR &CDE2 ;exchange last 2 graphics cursor coordinates with + ;current coordinates +D5D9 JSR &D1B8 ;convert to external coordinates +D5DC LDX #&03 ;X=3 +D5DE PLA ;save A +D5DF TAY ;Y=A +D5E0 LDA &0310,X ;get graphics coordinate +D5E3 STA (&F0),Y ;store it in OS buffer +D5E5 DEY ;decrement Y and X +D5E6 DEX ; +D5E7 BPL &D5E0 ;if +ve do it again +D5E9 RTS ;then Exit + + +************************************************************************* +* * +* PLOT Fill triangle routine * +* * +************************************************************************* + +D5EA LDX #&20 ;X=&20 +D5EC LDY #&3E ;Y=&3E +D5EE JSR &D47C ;copy 300/7+X to 300/7+Y + ;this gets XY data parameters and current graphics + ;cursor position +D5F1 JSR &D632 ;exchange 320/3 with 324/7 if 316/7=<322/3 +D5F4 LDX #&14 ;X=&14 +D5F6 LDY #&24 ;Y=&24 +D5F8 JSR &D636 ; +D5FB JSR &D632 ; + +D5FE LDX #&20 ; +D600 LDY #&2A ; +D602 JSR &D411 ;calculate 032A/B-(324/5-320/1) +D605 LDA &032B ;and store +D608 STA &0332 ;result + +D60B LDX #&28 ;set pointers +D60D JSR &D459 ; +D610 LDY #&2E ; + +D612 JSR &D0DE ;copy 320/3 32/31 +D615 JSR &CDE2 ;exchange 314/7 with 324/7 +D618 CLC ; +D619 JSR &D658 ;execute fill routine + +D61C JSR &CDE2 ; +D61F LDX #&20 ; +D621 JSR &CDE4 ; +D624 SEC ; +D625 JSR &D658 ; + +D628 LDX #&3E ;;X=&3E +D62A LDY #&20 ;;Y=&20 +D62C JSR &D47C ;;copy 300/7+X to 300/7+Y +D62F JMP &D0D9 ;;this gets XY data parameters and current graphics + ;cursor position + +D632 LDX #&20 ;X=&20 +D634 LDY #&14 ;Y=&14 +D636 LDA &0302,X ; +D639 CMP &0302,Y ; +D63C LDA &0303,X ; +D63F SBC &0303,Y ; +D642 BMI &D657 ;if 302/3+Y>302/3+X return +D644 JMP &CDE6 ;else swap 302/3+X with 302/3+Y + + +************************************************************************* +* * +* OSBYTE 134 - READ CURSOR POSITION * +* * +************************************************************************* + +D647 LDA &0318 ;read current text cursor (X) +D64A SEC ;set carry +D64B SBC &0308 ;subtract left hand column of current text window +D64E TAX ;X=A +D64F LDA &0319 ;get current text cursor (Y) +D652 SEC ; +D653 SBC &030B ;suptract top row of current window +D656 TAY ;Y=A +D657 RTS ;and exit + + ;PLOT routines continue + ;many of the following routines are just manipulations + ;only points of interest will be explained +D658 PHP ;store flags +D659 LDX #&20 ;X=&20 +D65B LDY #&35 ;Y=&35 +D65D JSR &D411 ;335/6=(324/5+X-320/1) +D660 LDA &0336 ; +D663 STA &033D ; +D666 LDX #&33 ; +D668 JSR &D459 ;set pointers + +D66B LDY #&39 ;set 339/C=320/3 +D66D JSR &D0DE ; +D670 SEC ; +D671 LDA &0322 ; +D674 SBC &0326 ; +D677 STA &031B ; +D67A LDA &0323 ; +D67D SBC &0327 ; +D680 STA &031C ; +D683 ORA &031B ;check VDU queque +D686 BEQ &D69F ; + +D688 JSR &D6A2 ;display a line +D68B LDX #&33 ; +D68D JSR &D774 ;update pointers +D690 LDX #&28 ; +D692 JSR &D774 ;and again! +D695 INC &031B ;update VDU queque +D698 BNE &D688 ;and if not empty do it again +D69A INC &031C ;else increment next byte +D69D BNE &D688 ;and do it again + +D69F PLP ;pull flags +D6A0 BCC &D657 ;if carry clear exit +D6A2 LDX #&39 ; +D6A4 LDY #&2E ; +D6A6 STX &DE ; +D6A8 LDA &0300,X ;is 300/1+x<300/1+Y +D6AB CMP &0300,Y ; +D6AE LDA &0301,X ; +D6B1 SBC &0301,Y ; +D6B4 BMI &D6BC ;if so D6BC +D6B6 TYA ;else A=Y +D6B7 LDY &DE ;Y=&DE +D6B9 TAX ;X=A +D6BA STX &DE ;&DE=X +D6BC STY &DF ;&DF=Y +D6BE LDA &0300,Y ; +D6C1 PHA ; +D6C2 LDA &0301,Y ; +D6C5 PHA ; +D6C6 LDX &DF ; +D6C8 JSR &D10F ;check for window violations +D6CB BEQ &D6DA ; +D6CD CMP #&02 ; +D6CF BNE &D70E ; +D6D1 LDX #&04 ; +D6D3 LDY &DF ; +D6D5 JSR &D482 ; +D6D8 LDX &DF ; +D6DA JSR &D864 ;set a screen address +D6DD LDX &DE ;X=&DE +D6DF JSR &D10F ;check for window violations +D6E2 LSR ;A=A/2 +D6E3 BNE &D70E ;if A<>0 then exit +D6E5 BCC &D6E9 ;else if C clear D6E9 +D6E7 LDX #&00 ; +D6E9 LDY &DF ; +D6EB SEC ; +D6EC LDA &0300,Y ; +D6EF SBC &0300,X ; +D6F2 STA &DC ; +D6F4 LDA &0301,Y ; +D6F7 SBC &0301,X ; +D6FA STA &DD ; +D6FC LDA #&00 ; +D6FE ASL ; +D6FF ORA &D1 ; +D701 LDY &DC ; +D703 BNE &D719 ; +D705 DEC &DD ; +D707 BPL &D719 ; +D709 STA &D1 ; +D70B JSR &D0F0 ;display a point +D70E LDX &DF ;restore X +D710 PLA ;and A +D711 STA &0301,X ;store it +D714 PLA ;get back A +D715 STA &0300,X ;and store it +D718 RTS ;exit + ; +D719 DEC &DC ; +D71B TAX ; +D71C BPL &D6FE ; +D71E STA &D1 ; +D720 JSR &D0F0 ;display a point +D723 LDX &DC ; +D725 INX ; +D726 BNE &D72A ; +D728 INC &DD ; +D72A TXA ; +D72B PHA ; +D72C LSR &DD ; +D72E ROR ; +D72F LDY &0361 ;number of pixels/byte +D732 CPY #&03 ;if 3 mode = goto D73B +D734 BEQ &D73B ; +D736 BCC &D73E ;else if <3 mode 2 goto D73E +D738 LSR &DD ;else rotate bottom bit of &DD +D73A ROR ;into Accumulator + +D73B LSR &DD ;rotate bottom bit of &DD +D73D LSR ;into Accumulator +D73E LDY &031A ;Y=line in current graphics cell containing current + ;point +D741 TAX ;X=A +D742 BEQ &D753 ; +D744 TYA ;Y=Y-8 +D745 SEC ; +D746 SBC #&08 ; +D748 TAY ; + +D749 BCS &D74D ; +D74B DEC &D7 ;decrement byte of top line off current graphics cell +D74D JSR &D104 ;display a point +D750 DEX ; +D751 BNE &D744 ; +D753 PLA ; +D754 AND &0361 ;pixels/byte +D757 BEQ &D70E ; +D759 TAX ; +D75A LDA #&00 ;A=0 +D75C ASL ; +D75D ORA &0363 ;or with right colour mask +D760 DEX ; +D761 BNE &D75C ; +D763 STA &D1 ;store as byte mask +D765 TYA ;Y=Y-8 +D766 SEC ; +D767 SBC #&08 ; +D769 TAY ; +D76A BCS &D76E ;if carry clear +D76C DEC &D7 ;decrement byte of top line off current graphics cell +D76E JSR &D0F3 ;display a point +D771 JMP &D70E ;and exit via D70E + +D774 INC &0308,X ; +D777 BNE &D77C ; +D779 INC &0309,X ; +D77C SEC ; +D77D LDA &0300,X ; +D780 SBC &0302,X ; +D783 STA &0300,X ; +D786 LDA &0301,X ; +D789 SBC &0303,X ; +D78C STA &0301,X ; +D78F BPL &D7C1 ; +D791 LDA &030A,X ; +D794 BMI &D7A1 ; +D796 INC &0306,X ; +D799 BNE &D7AC ; +D79B INC &0307,X ; +D79E JMP &D7AC ; +D7A1 LDA &0306,X ; +D7A4 BNE &D7A9 ; +D7A6 DEC &0307,X ; +D7A9 DEC &0306,X ; +D7AC CLC ; +D7AD LDA &0300,X ; +D7B0 ADC &0304,X ; +D7B3 STA &0300,X ; +D7B6 LDA &0301,X ; +D7B9 ADC &0305,X ; +D7BC STA &0301,X ; +D7BF BMI &D791 ; +D7C1 RTS ; + + +************************************************************************* +* * +* OSBYTE 135 - READ CHARACTER AT TEXT CURSOR POSITION * +* * +************************************************************************* + +D7C2 LDY &0360 ;get number of logical colours +D7C5 BNE &D7DC ;if Y<>0 mode <>7 so D7DC +D7C7 LDA (&D8),Y ;get address of top scan line of current text chr +D7C9 LDY #&02 ;Y=2 +D7CB CMP &C4B7,Y ;compare with conversion table +D7CE BNE &D7D4 ;if not equal D7d4 +D7D0 LDA &C4B6,Y ;else get next lower byte from table +D7D3 DEY ;Y=Y-1 +D7D4 DEY ;Y=Y-1 +D7D5 BPL &D7CB ;and if +ve do it again +D7D7 LDY &0355 ;Y=current screen mode +D7DA TAX ;return with character in X +D7DB RTS ; + ; +D7DC JSR &D808 ;set up copy of the pattern bytes at text cursor +D7DF LDX #&20 ;X=&20 +D7E1 TXA ;A=&20 +D7E2 PHA ;Save it +D7E3 JSR &D03E ;get pattern address for code in A +D7E6 PLA ;get back A +D7E7 TAX ;and X +D7E8 LDY #&07 ;Y=7 +D7EA LDA &0328,Y ;get byte in pattern copy +D7ED CMP (&DE),Y ;check against pattern source +D7EF BNE &D7F9 ;if not the same D7F9 +D7F1 DEY ;else Y=Y-1 +D7F2 BPL &D7EA ;and if +ve D7EA +D7F4 TXA ;A=X +D7F5 CPX #&7F ;is X=&7F (delete) +D7F7 BNE &D7D7 ;if not D7D7 +D7F9 INX ;else X=X+1 +D7FA LDA &DE ;get byte lo address +D7FC CLC ;clear carry +D7FD ADC #&08 ;add 8 +D7FF STA &DE ;store it +D801 BNE &D7E8 ;and go back to check next character if <>0 + +D803 TXA ;A=X +D804 BNE &D7E1 ;if <>0 D7E1 +D806 BEQ &D7D7 ;else D7D7 + +***************** set up pattern copy *********************************** + +D808 LDY #&07 ;Y=7 + +D80A STY &DA ;&DA=Y +D80C LDA #&01 ;A=1 +D80E STA &DB ;&DB=A +D810 LDA &0362 ;A=left colour mask +D813 STA &DC ;store an &DC +D815 LDA (&D8),Y ;get a byte from current text character +D817 EOR &0358 ;EOR with text background colour +D81A CLC ;clear carry +D81B BIT &DC ;and check bits of colour mask +D81D BEQ &D820 ;if result =0 then D820 +D81F SEC ;else set carry +D820 ROL &DB ;&DB=&DB+Carry +D822 BCS &D82E ;if carry now set (bit 7 DB originally set) D82E +D824 LSR &DC ;else &DC=&DC/2 +D826 BCC &D81B ;if carry clear D81B +D828 TYA ;A=Y +D829 ADC #&07 ;ADD ( (7+carry) +D82B TAY ;Y=A +D82C BCC &D810 ; +D82E LDY &DA ;read modified values into Y and A +D830 LDA &DB ; +D832 STA &0328,Y ;store copy +D835 DEY ;and do it again +D836 BPL &D80A ;until 8 bytes copied +D838 RTS ;exit + +********* pixel reading ************************************************* + +D839 PHA ;store A +D83A TAX ;X=A +D83B JSR &D149 ;set up positional data +D83E PLA ;get back A +D83F TAX ;X=A +D840 JSR &D85F ;set a screen address after checking for window + ;violations +D843 BNE &D85A ;if A<>0 D85A to exit with A=&FF +D845 LDA (&D6),Y ;else get top line of current graphics cell +D847 ASL ;A=A*2 C=bit 7 +D848 ROL &DA ;&DA=&DA+2 +C C=bit 7 &DA +D84A ASL &D1 ;byte mask=bM*2 +carry from &DA +D84C PHP ;save flags +D84D BCS &D851 ;if carry set D851 +D84F LSR &DA ;else restore &DA with bit '=0 +D851 PLP ;pull flags +D852 BNE &D847 ;if Z set D847 +D854 LDA &DA ;else A=&DA AND number of colours in current mode -1 +D856 AND &0360 ; +D859 RTS ;then exit + ; +D85A LDA #&FF ;A=&FF +D85C RTS ;exit + +********** check for window violations and set up screen address ********** + +D85D LDX #&20 ;X=&20 +D85F JSR &D10F ; +D862 BNE &D85C ;if A<>0 there is a window violation so D85C +D864 LDA &0302,X ;else set up graphics scan line variable +D867 EOR #&FF ; +D869 TAY ; +D86A AND #&07 ; +D86C STA &031A ;in 31A +D86F TYA ;A=Y +D870 LSR ;A=A/2 +D871 LSR ;A=A/2 +D872 LSR ;A=A/2 +D873 ASL ;A=A*2 this gives integer value bit 0 =0 +D874 TAY ;Y=A +D875 LDA (&E0),Y ;get high byte of offset from screen RAM start +D877 STA &DA ;store it +D879 INY ;Y=Y+1 +D87A LDA (&E0),Y ;get lo byte +D87C LDY &0356 ;get screen map type +D87F BEQ &D884 ;if 0 (modes 0,1,2) goto D884 +D881 LSR &DA ;else &DA=&DA/2 +D883 ROR ;and A=A/2 +C if set + ;so 2 byte offset =offset/2 + +D884 ADC &0350 ;add screen top left hand corner lo +D887 STA &D6 ;store it +D889 LDA &DA ;get high byte +D88B ADC &0351 ;add top left hi +D88E STA &D7 ;store it +D890 LDA &0301,X ; +D893 STA &DA ; +D895 LDA &0300,X ; +D898 PHA ; +D899 AND &0361 ;and then Add pixels per byte-1 +D89C ADC &0361 ; +D89F TAY ;Y=A +D8A0 LDA &C406,Y ;A=&80 /2^Y using look up table +D8A3 STA &D1 ;store it +D8A5 PLA ;get back A +D8A6 LDY &0361 ;Y=&number of pixels/byte +D8A9 CPY #&03 ;is Y=3 (modes 1,6) +D8AB BEQ &D8B2 ;goto D8B2 +D8AD BCS &D8B5 ;if mode =1 or 4 D8B5 +D8AF ASL ;A/&DA =A/&DA *2 +D8B0 ROL &DA ; + +D8B2 ASL ; +D8B3 ROL &DA ; + +D8B5 AND #&F8 ;clear bits 0-2 +D8B7 CLC ;clear carry + +D8B8 ADC &D6 ;add A/&DA to &D6/7 +D8BA STA &D6 ; +D8BC LDA &DA ; +D8BE ADC &D7 ; +D8C0 BPL &D8C6 ;if result +ve D8C6 +D8C2 SEC ;else set carry +D8C3 SBC &0354 ;and subtract screen memory size making it wrap round + +D8C6 STA &D7 ;store it in &D7 +D8C8 LDY &031A ;get line in graphics cell containing current graphics +D8CB LDA #&00 ;point A=0 +D8CD RTS ;And exit + ; +D8CE PHA ;Push A +D8CF LDA #&A0 ;A=&A0 +D8D1 LDX &026A ;X=number of items in VDU queque +D8D4 BNE &D916 ;if not 0 D916 +D8D6 BIT &D0 ;else check VDU status byte +D8D8 BNE &D916 ;if either VDU is disabled or plot to graphics + ;cursor enabled then D916 +D8DA BVS &D8F5 ;if cursor editing enabled D8F5 +D8DC LDA &035F ;else get 6845 register start setting +D8DF AND #&9F ;clear bits 5 and 6 +D8E1 ORA #&40 ;set bit 6 to modify last cursor size setting +D8E3 JSR &C954 ;change write cursor format +D8E6 LDX #&18 ;X=&18 +D8E8 LDY #&64 ;Y=&64 +D8EA JSR &D482 ;set text input cursor from text output cursor +D8ED JSR &CD7A ;modify character at cursor poistion +D8F0 LDA #&02 ;A=2 +D8F2 JSR &C59D ;bit 1 of VDU status is set to bar scrolling + + +D8F5 LDA #&BF ;A=&BF +D8F7 JSR &C5A8 ;bit 6 of VDU status =0 +D8FA PLA ;Pull A +D8FB AND #&7F ;clear hi bit (7) +D8FD JSR &C4C0 ;entire VDU routine !! +D900 LDA #&40 ;A=&40 +D902 JMP &C59D ;exit + + +D905 LDA #&20 ;A=&20 +D907 BIT &D0 ;if bit 6 cursor editing is set +D909 BVC &D8CB ; +D90B BNE &D8CB ;or bit 5 is set exit &D8CB +D90D JSR &D7C2 ;read a character from the screen +D910 BEQ &D917 ;if A=0 on return exit via D917 +D912 PHA ;else store A +D913 JSR &C664 ;perform cursor right + +D916 PLA ;restore A +D917 RTS ;and exit + ; +D918 LDA #&BD ;zero bits 2 and 6 of VDU status +D91A JSR &C5A8 ; +D91D JSR &C951 ;set normal cursor +D920 LDA #&0D ;A=&0D +D922 RTS ;and return + ;this is response of CR as end of edit line + + +************************************************************************* +* * +* OSBYTE 132 - READ BOTTOM OF DISPLAY RAM * +* * +************************************************************************* + +D923 LDX &0355 ; Get current screen mode + + +************************************************************************* +* * +* OSBYTE 133 - READ LOWEST ADDRESS FOR GIVEN MODE * +* * +************************************************************************* + +D926 TXA ; A=X +D927 AND #&07 ; Ensure mode 0-7 +D929 TAY ; Pass to Y into index into screen size table +D92A LDX &C440,Y ; X=screen size type, 0-4 +D92D LDA &C45E,X ; A=high byte of start address for screen type +D930 LDX #&00 ; Returned address is &xx00 +D932 BIT &028E ; Check available RAM +D935 BMI &D93E ; If bit 7 set then 32K RAM, so return address +D937 AND #&3F ; 16K RAM, so drop address to bottom 16K +D939 CPY #&04 ; Check screen mode +D93B BCS &D93E ; If mode 4-7, return the address +D93D TXA ; If mode 0-3, return &0000 as not enough memory +; exit +D93E TAY ; Pass high byte of address to Y +D93F RTS ; and return address in YX + +************************************************************************* +************************************************************************* +** ** +** SYSTEM STARTUP ** +** ** +************************************************************************* +************************************************************************* + +* DEFAULT PAGE &02 SETTINGS (VECTORS, OSBYTE VARIABLES) +* RESET CODE + +************************************************************************* +* * +* DEFAULT SYSTEM SETTINGS FOR PAGE &02 * +* * +************************************************************************* + +------------------------------------------------------------------------- +| | +| DEFAULT VECTOR TABLE | +| | +------------------------------------------------------------------------- + +D940 DW &E310 ; USERV &200 +D942 DW &DC54 ; BRKV &202 +D944 DW &DC93 ; IRQ1V &204 +D946 DW &DE89 ; IRQ2V &206 +D948 DW &DF89 ; CLIV &208 +D94A DW &E772 ; BYTEV &20A +D94C DW &E7EB ; WORDV &20C +D94E DW &E0A4 ; WRCHV &20E +D950 DW &DEC5 ; RDCHV &210 +D952 DW &F27D ; FILEV &212 +D954 DW &F18E ; ARGSV &214 +D956 DW &F4C9 ; BGETV &216 +D958 DW &F529 ; BPUTV &218 +D95A DW &FFA6 ; GBPBV &21A +D95C DW &F3CA ; FINDV &21C +D95E DW &F1B1 ; FSCV &21E +D960 DW &FFA6 ; EVNTV &220 +D962 DW &FFA6 ; UPTV &222 +D964 DW &FFA6 ; NETV &224 +D966 DW &FFA6 ; VDUV &226 +D968 DW &EF02 ; KEYV &228 +D96A DW &E4B3 ; INSBV &22A +D96C DW &E464 ; REMVB &22C +D96E DW &E1D1 ; CNPV &22E +D970 DW &FFA6 ; IND1V &230 +D972 DW &FFA6 ; IND2V &232 +D974 DW &FFA6 ; IND3V &234 + +------------------------------------------------------------------------- +| | +| DEFAULT MOS VARIABLES SETTINGS | +| | +------------------------------------------------------------------------- + +* Read/Written by OSBYTE &A6 to &FC + +D976 DW &0190 ; OSBYTE variables base address &236 *FX166/7 + ; (address to add to osbyte number) +D978 DB &0D9F ; Address of extended vectors &238 *FX168/9 +D97A DB &02A1 ; Address of ROM information table &23A *FX170/1 +D97C DB &F02B ; Address of key translation table &23C *FX172/3 +D97E DB &0300 ; Address of VDU variables &23E *FX174/5 + +D980 DB &00 ; CFS/Vertical sync Timeout counter &240 *FX176 +D981 DB &00 ; Current input buffer number &241 *FX177 +D982 DB &FF ; Keyboard interrupt processing flag &242 *FX178 +D983 DB &00 ; Primary OSHWM (default PAGE) &243 *FX179 +D984 DB &00 ; Current OSHWM (PAGE) &244 *FX180 +D985 DB &01 ; RS423 input mode &245 *FX181 +D986 DB &00 ; Character explosion state &246 *FX182 +D987 DB &00 ; CFS/RFS selection, CFS=0 ROM=2 &247 *FX183 +D988 DB &00 ; Video ULA control register copy &248 *FX184 +D989 DB &00 ; Pallette setting copy &249 *FX185 +D98A DB &00 ; ROM number selected at last BRK &24A *FX186 +D98B DB &FF ; BASIC ROM number &24B *FX187 +D98C DB &04 ; Current ADC channel number &24C *FX188 +D98D DB &04 ; Maximum ADC channel number &24D *FX189 +D98E DB &00 ; ADC conversion 0/8bit/12bit &24E *FX190 +D98F DB &FF ; RS423 busy flag (bit 7=0, busy) &24F *FX191 + +D990 DB &56 ; ACIA control register copy &250 *FX192 +D991 DB &19 ; Flash counter &251 *FX193 +D992 DB &19 ; Flash mark period count &252 *FX194 +D993 DB &19 ; Flash space period count &253 *FX195 +D994 DB &32 ; Keyboard auto-repeat delay &254 *FX196 +D995 DB &08 ; Keyboard auto-repeat rate &255 *FX197 +D996 DB &00 ; *EXEC file handle &256 *FX198 +D997 DB &00 ; *SPOOL file handle &257 *FX199 +D998 DB &00 ; Break/Escape handing &258 *FX200 +D999 DB &00 ; Econet keyboard disable flag &259 *FX201 +D99A DB &20 ; Keyboard status &25A *FX202 + ; bit 3=1 shift pressed + ; bit 4=0 caps lock + ; bit 5=0 shift lock + ; bit 6=1 control bit + ; bit 7=1 shift enabled +D99B DB &09 ; Serial input buffer full threshold &25B *FX203 +D99C DB &00 ; Serial input suppression flag &25C *FX204 +D99D DB &00 ; Cassette/RS423 flag (0=CFS, &40=RS423) &25D *FX205 +D99E DB &00 ; Econet OSBYTE/OSWORD interception flag &25E *FX206 +D99F DB &00 ; Econet OSRDCH interception flag &25F *FX207 + +D9A0 DB &00 ; Econet OSWRCH interception flag &260 *FX208 +D9A1 DB &50 ; Speech enable/disable flag (&20/&50) &261 *FX209 +D9A2 DB &00 ; Sound output disable flag &262 *FX210 +D9A3 DB &03 ; BELL channel number &263 *FX211 +D9A4 DB &90 ; BELL amplitude/Envelope number &264 *FX212 +D9A5 DB &64 ; BELL frequency &265 *FX213 +D9A6 DB &06 ; BELL duration &266 *FX214 +D9A7 DB &81 ; Startup message/!BOOT error status &267 *FX215 +D9A8 DB &00 ; Length of current soft key string &268 *FX216 +D9A9 DB &00 ; Lines printed since last paged halt &269 *FX217 +D9AA DB &00 ; 0-(Number of items in VDU queue) &26A *FX218 +D9AB DB &09 ; TAB key value &26B *FX219 +D9AC DB &1B ; ESCAPE character &26C *FX220 + + ; The following are input buffer code interpretation variables for + ; bytes entered into the input buffer with b7 set (is 128-255). + ; The standard keyboard only enters characters &80-&BF with the + ; function keys, but other characters can be entered, for instance + ; via serial input of via other keyboard input systems. + ; 0=ignore key + ; 1=expand as soft key + ; 2-FF add to base for ASCII code +D9AD DB &01 ; C0-&CF &26D *FX221 +D9AE DB &D0 ; D0-&DF &26E *FX222 +D9AF DB &E0 ; E0-&EF &26F *FX223 +D9B0 DB &F0 ; F0-&FF &270 *FX224 +D9B1 DB &01 ; 80-&8F function key &271 *FX225 +D9B2 DB &80 ; 90-&9F Shift+function key &272 *FX226 +D9B3 DB &90 ; A0-&AF Ctrl+function key &273 *FX227 +D9B4 DB &00 ; B0-&BF Shift+Ctrl+function key &274 *FX228 + +D9B5 DB &00 ; ESCAPE key status (0=ESC, 1=ASCII) &275 *FX229 +D9B6 DB &00 ; ESCAPE action &276 *FX230 +D9B7 DB &FF ; USER 6522 Bit IRQ mask &277 *FX231 +D9B8 DB &FF ; 6850 ACIA Bit IRQ bit mask &278 *FX232 +D9B9 DB &FF ; System 6522 IRQ bit mask &279 *FX233 +D9BA DB &00 ; Tube prescence flag &27A *FX234 +D9BB DB &00 ; Speech processor prescence flag &27B *FX235 +D9BC DB &00 ; Character destination status &27C *FX236 +D9BD DB &00 ; Cursor editing status &27D *FX237 + +****************** Soft Reset high water mark *************************** + +D9BE DB &00 ; unused &27E *FX238 +D9BF DB &00 ; unused &27F *FX239 +D9C0 DB &00 ; Country code &280 *FX240 +D9C1 DB &00 ; User flag &281 *FX241 +D9C2 DB &64 ; Serial ULA control register copy &282 *FX242 +D9C3 DB &05 ; Current system clock state &283 *FX243 +D9C4 DB &FF ; Soft key consitancy flag &284 *FX244 +D9C5 DB &01 ; Printer destination &285 *FX245 +D9C6 DB &0A ; Printer ignore character &286 *FX246 + +****************** Hard Reset High water mark *************************** + +D9C7 DB &00 ; Break Intercept Vector JMP opcode &288 *FX247 +D9C8 DB &00 ; Break Intercept Vector address low &288 *FX248 +D9C9 DB &00 ; Break Intercept Vector address high &289 *FX249 +D9CA DB &00 ; unused (memory used for VDU) &28A *FX250 +D9CB DB &00 ; unused (memory used for display) &28B *FX251 +D9CC DB &FF ; Current language ROM number &28C *FX252 + +****************** Power-On Reset High Water mark *********************** + + +************************************************************************** +************************************************************************** +** ** +** RESET (BREAK) ENTRY POINT ** +** ** +** Power up Enter with nothing set, 6522 System VIA IER bits ** +** 0 to 6 will be clear ** +** ** +** BREAK IER bits 0 to 6 one or more will be set 6522 IER ** +** not reset by BREAK ** +** ** +************************************************************************** +************************************************************************** + +D9CD LDA #&40 ;set NMI first instruction to RTI +D9CF STA &0D00 ;NMI ram start + +D9D2 SEI ;disable interrupts just in case +D9D3 CLD ;clear decimal flag +D9D4 LDX #&FF ;reset stack to where it should be +D9D6 TXS ;(&1FF) +D9D7 LDA &FE4E ;read interupt enable register of the system VIA +D9DA ASL ;shift bit 7 into carry +D9DB PHA ;save what's left +D9DC BEQ &D9E7 ;if Power up A=0 so D9E7 +D9DE LDA &0258 ;else if BREAK pressed read BREAK Action flags (set by + ;*FX200,n) +D9E1 LSR ;divide by 2 +D9E2 CMP #&01 ;if (bit 1 not set by *FX200) +D9E4 BNE &DA03 ;then &DA03 +D9E6 LSR ;divide A by 2 again (A=0 if *FX200,2/3 else A=n/4 + +********** clear memory routine ****************************************** + +D9E7 LDX #&04 ;get page to start clearance from (4) +D9E9 STX &01 ;store it in ZP 01 +D9EB STA &00 ;store A at 00 + +D9ED TAY ;and in Y to set loop counter + +D9EE STA (&00),Y ;clear store +D9F0 CMP &01 ;until address &01 =0 +D9F2 BEQ &D9FD ; +D9F4 INY ;increment pointer +D9F5 BNE &D9EE ;if not zero loop round again +D9F7 INY ;else increment again (Y=1) this avoids overwriting + ;RTI instruction at &D00 +D9F8 INX ;increment X +D9F9 INC &01 ;increment &01 +D9FB BPL &D9EE ;loop until A=&80 then exit + ;note that RAM addressing for 16k loops around so + ;&4000=&00 hence checking &01 for 00. This avoids + ;overwriting zero page on BREAK + + +D9FD STX &028E ;writes marker for available RAM 40 =16k,80=32 +DA00 STX &0284 ;write soft key consistency flag + +**+********** set up system VIA ***************************************** + +DA03 LDX #&0F ;set PORT B to output on bits 0-3 Input 4-7 +DA05 STX &FE42 ; + + +************************************************************************* +* * +* set addressable latch IC 32 for peripherals via PORT B * +* * +* ;bit 3 set sets addressed latch high adds 8 to VIA address * +* ;bit 3 reset sets addressed latch low * +* * +* Peripheral VIA bit 3=0 VIA bit 3=1 * +* * +* Sound chip Enabled Disabled * +* speech chip (RS) Low High * +* speech chip (WS) Low High * +* Keyboard Auto Scan Disabled Enabled * +* C0 address modifier Low High * +* C1 address modifier Low High * +* Caps lock LED ON OFF * +* Shift lock LED ON OFF * +* * +* C0 & C1 are involved with hardware scroll screen address * +************************************************************************* + + ;X=&F on entry + +DA08 DEX ;loop start +DA09 STX &FE40 ;write latch IC32 +DA0C CPX #&09 ;is it 9 +DA0E BCS &DA08 ;if so go back and do it again + ;X=8 at this point + ;Caps lock On, SHIFT lock undetermined + ;Keyboard Autoscan on + ;sound disabled (may still sound) +DA10 INX ;X=9 +DA11 TXA ;A=X +DA12 JSR &F02A ;interrogate keyboard +DA15 CPX #&80 ;for keyboard links 9-2 and CTRL key (1) +DA17 ROR &FC ;rotate MSB into bit 7 of &FC + +DA19 TAX ;get back value of X for loop +DA1A DEX ;decrement it +DA1B BNE &DA11 ;and if >0 do loop again + ; on exit if Carry set link 3 made + ;link 2 = bit 0 of &FC and so on + ;if CTRL pressed bit 7 of &FC=1 + ;X=0 +DA1D STX &028D ;clear last BREAK flag +DA20 ROL &FC ;CTRL is now in carry &FC is keyboard links +DA22 JSR &EEEB ;set LEDs carry on entry bit 7 of A on exit +DA25 ROR ;get carry back into carry flag + +****** set up page 2 **************************************************** + +DA26 LDX #&9C ; +DA28 LDY #&8D ; +DA2A PLA ;get back A from &D9DB +DA2B BEQ &DA36 ;if A=0 power up reset so DA36 with X=&9C Y=&8D +DA2D LDY #&7E ;else Y=&7E +DA2F BCC &DA42 ;and if not CTRL-BREAK DA42 WARM RESET +DA31 LDY #&87 ;else Y=&87 COLD RESET +DA33 INC &028D ;&28D=1 + +DA36 INC &028D ;&28D=&28D+1 +DA39 LDA &FC ;get keyboard links set +DA3B EOR #&FF ;invert +DA3D STA &028F ;and store at &28F +DA40 LDX #&90 ;X=&90 + +**********: set up page 2 ************************************************* + + ;on entry &28D=0 Warm reset, X=&9C, Y=&7E + ;&28D=1 Power up , X=&90, Y=&8D + ;&28D=2 Cold reset, X=&9C, Y=&87 + +DA42 LDA #&00 ;A=0 +DA44 CPX #&CE ;zero &200+X to &2CD +DA46 BCC &DA4A ; +DA48 LDA #&FF ;then set &2CE to &2FF to &FF +DA4A STA &0200,X ; +DA4D INX ; +DA4E BNE &DA44 ; + ;A=&FF X=0 +DA50 STA &FE63 ;set port A of user via to all outputs (printer out) + +DA53 TXA ;A=0 +DA54 LDX #&E2 ;X=&E2 +DA56 STA &00,X ;zero zeropage &E2 to &FF +DA58 INX ; +DA59 BNE &DA56 ;X=0 + +DA5B LDA &D93F,Y ;copy data from &D93F+Y +DA5E STA &01FF,Y ;to &1FF+Y +DA61 DEY ;until +DA62 BNE &DA5B ;1FF+Y=&200 + +DA64 LDA #&62 ;A=&62 +DA66 STA &ED ;store in &ED +DA68 JSR &FB0A ;set up ACIA + ;X=0 + +************** clear interrupt and enable registers of Both VIAs ******** + +DA6B LDA #&7F ; +DA6D INX ; +DA6E STA &FE4D,X ; +DA71 STA &FE6D,X ; +DA74 DEX ; +DA75 BPL &DA6E ; + +DA77 CLI ;briefly allow interrupts to clear anything pending +DA78 SEI ;disallow again N.B. All VIA IRQs are disabled +DA79 BIT &FC ;if bit 6=1 then JSR &F055 (normally 0) +DA7B BVC &DA80 ;else DA80 +DA7D JSR &F055 ;F055 JMP (&FDFE) probably causes a BRK unless + ;hardware there redirects it. + ; +DA80 LDX #&F2 ;enable interrupts 1,4,5,6 of system VIA +DA82 STX &FE4E ; + ;0 Keyboard enabled as needed + ;1 Frame sync pulse + ;4 End of A/D conversion + ;5 T2 counter (for speech) + ;6 T1 counter (10 mSec intervals) + ; +DA85 LDX #&04 ;set system VIA PCR +DA87 STX &FE4C ; + ;CA1 to interrupt on negative edge (Frame sync) + ;CA2 Handshake output for Keyboard + ;CB1 interrupt on negative edge (end of conversion) + ;CB2 Negative edge (Light pen strobe) + ; +DA8A LDA #&60 ;set system VIA ACR +DA8C STA &FE4B ; + ;disable latching + ;disable shift register + ;T1 counter continuous interrupts + ;T2 counter timed interrupt + +DA8F LDA #&0E ;set system VIA T1 counter (Low) +DA91 STA &FE46 ; + ;this becomes effective when T1 hi set + +DA94 STA &FE6C ;set user VIA PCR + ;CA1 interrupt on -ve edge (Printer Acknowledge) + ;CA2 High output (printer strobe) + ;CB1 Interrupt on -ve edge (user port) + ;CB2 Negative edge (user port) + +DA97 STA &FEC0 ;set up A/D converter + ;Bits 0 & 1 determine channel selected + ;Bit 3=0 8 bit conversion bit 3=1 12 bit + +DA9A CMP &FE6C ;read user VIA IER if = &0E then DAA2 chip present +DA9D BEQ &DAA2 ;so goto DAA2 +DA9F INC &0277 ;else increment user VIA mask to 0 to bar all + ;user VIA interrupts + +DAA2 LDA #&27 ;set T1 (hi) to &27 this sets T1 to &270E (9998 uS) +DAA4 STA &FE47 ;or 10msec, interrupts occur every 10msec therefore +DAA7 STA &FE45 ; + +DAAA JSR &EC60 ;clear the sound channels + +DAAD LDA &0282 ;read serial ULA control register +DAB0 AND #&7F ;zero bit 7 +DAB2 JSR &E6A7 ;and set up serial ULA + +DAB5 LDX &0284 ;get soft key status flag +DAB8 BEQ &DABD ;if 0 (keys OK) then DABD +DABA JSR &E9C8 ;else reset function keys + + +************************************************************************* +* * +* Check sideways ROMs and make ROM list * +* * +************************************************************************* + + ;X=0 +DABD JSR &DC16 ;set up ROM latch and RAM copy to X +DAC0 LDX #&03 ;set X to point to offset in table +DAC2 LDY &8007 ;get copyright offset from ROM + + ; DF0C = ")C(",0 +DAC5 LDA &8000,Y ;get first byte +DAC8 CMP &DF0C,X ;compare it with table byte +DACB BNE &DAFB ;if not the same then goto DAFB +DACD INY ;point to next byte +DACE DEX ;(s) +DACF BPL &DAC5 ;and if still +ve go back to check next byte + + ;this point is reached if 5 bytes indicate valid + ;ROM (offset +4 in (C) string) + + +************************************************************************* +* Check first 1K of each ROM against higher priority ROMs to ensure that* +* there are no duplicates, if duplicate found ignore lower priority ROM * +************************************************************************* + +DAD1 LDX &F4 ;get RAM copy of ROM No. in X +DAD3 LDY &F4 ;and Y + +DAD5 INY ;increment Y to check +DAD6 CPY #&10 ;if ROM 15 is current ROM +DAD8 BCS &DAFF ;if equal or more than 16 goto &DAFF + ;to store catalogue byte +DADA TYA ;else put Y in A +DADB EOR #&FF ;invert it +DADD STA &FA ;and store at &FA +DADF LDA #&7F ;store &7F at +DAE1 STA &FB ;&FB to get address &7FFF-Y + +DAE3 STY &FE30 ;set new ROM +DAE6 LDA (&FA),Y ;Get byte +DAE8 STX &FE30 ;switch back to previous ROM +DAEB CMP (&FA),Y ;and compare with previous byte called +DAED BNE &DAD5 ;if not the same then go back and do it again + ;with next rom up +DAEF INC &FA ;else increment &FA to point to new location +DAF1 BNE &DAE3 ;if &FA<>0 then check next byte +DAF3 INC &FB ;else inc &FB +DAF5 LDA &FB ;and check that it doesn't exceed +DAF7 CMP #&84 ;&84 (1k checked) +DAF9 BCC &DAE3 ;then check next byte(s) + +DAFB LDX &F4 ;X=(&F4) +DAFD BPL &DB0C ;if +ve then &DB0C + +DAFF LDA &8006 ;get rom type +DB02 STA &02A1,X ;store it in catalogue +DB05 AND #&8F ;check for BASIC (bit 7 not set) +DB07 BNE &DB0C ;if not BASIC the DB0C +DB09 STX &024B ;else store X at BASIC pointer + +DB0C INX ;increment X to point to next ROM +DB0D CPX #&10 ;is it 15 or less +DB0F BCC &DABD ;if so goto &DABD for next ROM + +OS SERIES V +GEOFF COX +************************************************************************* +* * +* Check SPEECH System * +* * +************************************************************************* + + ;X=&10 +DB11 BIT &FE40 ;if bit 7 low then we have speech system fitted +DB14 BMI &DB27 ;else goto DB27 + +DB16 DEC &027B ;(027B)=&FF to indicate speech present + +DB19 LDY #&FF ;Y=&FF +DB1B JSR &EE7F ;initialise speech generator +DB1E DEX ;via this +DB1F BNE &DB19 ;loop + ;X=0 +DB21 STX &FE48 ;set T2 timer for speech +DB24 STX &FE49 ; + +*********** SCREEN SET UP ********************************************** + ;X=0 +DB27 LDA &028F ;get back start up options (mode) +DB2A JSR &C300 ;then jump to screen initialisation + +DB2D LDY #&CA ;Y=&CA +DB2F JSR &E4F1 ;to enter this in keyboard buffer + ;this enables the *KEY 10 facility + +********* enter BREAK intercept with Carry Clear ************************ + +DB32 JSR &EAD9 ;check to see if BOOT address is set up, if so + ;JMP to it + +DB35 JSR &F140 ;set up cassette options +DB38 LDA #&81 ;test for tube to FIFO buffer 1 +DB3A STA &FEE0 ; +DB3D LDA &FEE0 ; +DB40 ROR ;put bit 0 into carry +DB41 BCC &DB4D ;if no tube then DB4D +DB43 LDX #&FF ;else +DB45 JSR &F168 ;issue ROM service call &FF + ;to initialise TUBE system +DB48 BNE &DB4D ;if not 0 on exit (Tube not initialised) DB4D +DB4A DEC &027A ;else set tube flag to show it's active + +DB4D LDY #&0E ;set current value of PAGE +DB4F LDX #&01 ;issue claim absolute workspace call +DB51 JSR &F168 ;via F168 +DB54 LDX #&02 ;send private workspace claim call +DB56 JSR &F168 ;via F168 +DB59 STY &0243 ;set primary OSHWM +DB5C STY &0244 ;set current OSHWM +DB5F LDX #&FE ;issue call for Tube to explode character set etc. +DB61 LDY &027A ;Y=FF if tube present else Y=0 +DB64 JSR &F168 ;and make call via F168 + +DB67 AND &0267 ;if A=&FE and bit 7 of 0267 is set then continue +DB6A BPL &DB87 ;else ignore start up message +DB6C LDY #&02 ;output to screen +DB6E JSR &DEA9 ;'BBC Computer ' message +DB71 LDA &028D ;0=warm reset, anything else continue +DB74 BEQ &DB82 ; +DB76 LDY #&16 ;by checking length of RAM +DB78 BIT &028E ; +DB7B BMI &DB7F ;and either +DB7D LDY #&11 ; +DB7F JSR &DEA9 ;finishing message with '16K' or '32K' +DB82 LDY #&1B ;and two newlines +DB84 JSR &DEA9 ; + +*********: enter BREAK INTERCEPT ROUTINE WITH CARRY SET (call 1) + +DB87 SEC ; +DB88 JSR &EAD9 ;look for break intercept jump do *TV etc +DB8B JSR &E9D9 ;set up LEDs in accordance with keyboard status +DB8E PHP ;save flags +DB8F PLA ;and get back in A +DB90 LSR ;zero bits 4-7 and bits 0-2 bit 4 which was bit 7 +DB91 LSR ;may be set +DB92 LSR ; +DB93 LSR ; +DB94 EOR &028F ;eor with start-up options which may or may not +DB97 AND #&08 ;invert bit 4 +DB99 TAY ;Y=A +DB9A LDX #&03 ;make fs initialisation call, passing boot option in Y +DB9C JSR &F168 ;Eg, RUN, EXEC or LOAD !BOOT file +DB9F BEQ &DBBE ;if a ROM accepts this call then DBBE +DBA1 TYA ;else put Y in A +DBA2 BNE &DBB8 ;if Y<>0 DBB8 +DBA4 LDA #&8D ;else set up standard cassete baud rates +DBA6 JSR &F135 ;via &F135 + +DBA9 LDX #&D2 ; +DBAB LDY #&EA ; +DBAD DEC &0267 ;decrement ignore start up message flag +DBB0 JSR OSCLI ;and execute */!BOOT +DBB3 INC &0267 ;restore start up message flag +DBB6 BNE &DBBE ;if not zero then DBBE + +DBB8 LDA #&00 ;else A=0 +DBBA TAX ;X=0 +DBBB JSR &F137 ;set tape speed + +******** Preserve current language on soft RESET ************************ + +DBBE LDA &028D ;get last RESET Type +DBC1 BNE &DBC8 ;if not soft reset DBC8 + +DBC3 LDX &028C ;else get current language ROM address +DBC6 BPL &DBE6 ;if +ve (language available) then skip search routine + + +************************************************************************* +* * +* SEARCH FOR LANGUAGE TO ENTER (Highest priority) * +* * +************************************************************************* + +DBC8 LDX #&0F ;set pointer to highest available rom + +DBCA LDA &02A1,X ;get rom type from map +DBCD ROL ;put hi-bit into carry, bit 6 into bit 7 +DBCE BMI &DBE6 ;if bit 7 set then ROM has a language entry so DBE6 + +DBD0 DEX ;else search for language until X=&ff +DBD1 BPL &DBCA ; + +*************** check if tube present *********************************** + +DBD3 LDA #&00 ;if bit 7 of tube flag is set BMI succeeds +DBD5 BIT &027A ;and TUBE is connected else +DBD8 BMI &DC08 ;make error + +********* no language error *********************************************** + +DBDA BRK ; +DBDB DB &F9 ;error number +DBDC DB 'Language?' ;message +DBE5 BRK ; + +DBE6 CLC ; + + +************************************************************************* +* * +* OSBYTE 142 - ENTER LANGUAGE ROM AT &8000 * +* * +* X=rom number C set if OSBYTE call clear if initialisation * +* * +************************************************************************* + +DBE7 PHP ;save flags +DBE8 STX &028C ;put X in current ROM page +DBEB JSR &DC16 ;select that ROM +DBEE LDA #&80 ;A=128 +DBF0 LDY #&08 ;Y=8 +DBF2 JSR &DEAB ;display text string held in ROM at &8008,Y +DBF5 STY &FD ;save Y on exit (end of language string) +DBF7 JSR OSNEWL ;two line feeds +DBFA JSR OSNEWL ;are output +DBFD PLP ;then get back flags +DBFE LDA #&01 ;A=1 required for language entry +DC00 BIT &027A ;check if tube exists +DC03 BMI &DC08 ;and goto DC08 if it does +DC05 JMP &8000 ;else enter language at &8000 + + +************************************************************************* +* * +* TUBE FOUND, ENTER TUBE SOFTWARE * +* * +************************************************************************* + +DC08 JMP &0400 ;enter tube environment + + +************************************************************************* +* * +* OSRDRM entry point * +* * +* get byte from PHROM or page ROM * +* Y= rom number, address is in &F6/7 * +************************************************************************* + +DC0B LDX &F4 ;get current ROM number into X +DC0D STY &F4 ;store new number in &F4 +DC0F STY &FE30 ;switch in ROM +DC12 LDY #&00 ;get current PHROM address +DC14 LDA (&F6),Y ;and get byte + +******** Set up Sideways ROM latch and RAM copy ************************* + ;on entry X=ROM number + +DC16 STX &F4 ;RAM copy of rom latch +DC18 STX &FE30 ;write to rom latch +DC1B RTS ;and return + +************************************************************************** +************************************************************************** +** ** +** MAIN IRQ Entry point ** +** ** +** ** +************************************************************************** +************************************************************************** +;ON ENTRY STACK contains STATUS REGISTER,PCH,PCL ; + +DC1C STA &FC ;save A +DC1E PLA ;get back status (flags) +DC1F PHA ;and save again +DC20 AND #&10 ;check if BRK flag set +DC22 BNE &DC27 ;if so goto DC27 +DC24 JMP (&0204) ;else JMP (IRQ1V) + + +************************************************************************* +* * +* BRK handling routine * +* * +************************************************************************* + +DC27 TXA ;save X on stack +DC28 PHA ; +DC29 TSX ;get status pointer +DC2A LDA &0103,X ;get Program Counter lo +DC2D CLD ; +DC2E SEC ;set carry +DC2F SBC #&01 ;subtract 2 (1+carry) +DC31 STA &FD ;and store it in &FD +DC33 LDA &0104,X ;get hi byte +DC36 SBC #&00 ;subtract 1 if necessary +DC38 STA &FE ;and store in &FE +DC3A LDA &F4 ;get currently active ROM +DC3C STA &024A ;and store it in &24A +DC3F STX &F0 ;store stack pointer in &F0 +DC41 LDX #&06 ;and issue ROM service call 6 +DC43 JSR &F168 ;(User BRK) to ROMs + ;at this point &FD/E point to byte after BRK + ;ROMS may use BRK for their own purposes + +DC46 LDX &028C ;get current language +DC49 JSR &DC16 ;and activate it +DC4C PLA ;get back original value of X +DC4D TAX ; +DC4E LDA &FC ;get back original value of A +DC50 CLI ;allow interrupts +DC51 JMP (&0202) ;and JUMP via BRKV (normally into current language) + + +************************************************************************* +* * +* DEFAULT BRK HANDLER * +* * +************************************************************************* + +DC54 LDY #&00 ;Y=0 to point to byte after BRK +DC56 JSR &DEB1 ;print message + +DC59 LDA &0267 ;if BIT 0 set and DISC EXEC error +DC5C ROR ;occurs +DC5D BCS &DC5D ;hang up machine!!!! + +DC5F JSR OSNEWL ;else print two newlines +DC62 JSR OSNEWL ; +DC65 JMP &DBB8 ;and set tape speed before entering current + ;language + +; ACIA IRQ, RxRDY but both Serial and Printer buffers empty +; --------------------------------------------------------- +DC68 SEC +DC69 ROR &024F ; Set b7 of RS423 busy flag +DC6C BIT &0250 ;check bit 7 of current ACIA control register +DC6F BPL &DC78 ;if interrupts NOT enabled DC78 +DC71 JSR &E741 ;else E741 to check if serial buffer full +DC74 LDX #&00 ; X=&00 to set RTS low +DC76 BCS &DC7A ;if carry set goto DC7A to transfer data + +DC78 LDX #&40 ; X=&40 to set RTS high +DC7A JMP &E17A ; Jump to set ACIA control register + +; Serial IRQ and RxRDY - Get byte and store in serial buffer +; ---------------------------------------------------------- +DC7D LDY &FE09 ; Read data from ACIA +DC80 AND #&3A ; Check PE:RO:FE:DCD +DC82 BNE &DCB8 ; If any set, jump to generate Serial Error Event + +; Serial IRQ and RxRDY, no errors +; ------------------------------- +DC84 LDX &025C ; Read RS423 input suppression flag +DC87 BNE &DC92 ; If not 0, jump to ignore +DC89 INX ; X=1, serial input buffer +DC8A JSR &E4F3 ; Put byte in buffer +DC8D JSR &E741 ; Check if serial buffer almost full +DC90 BCC &DC78 ; If almost full, jump to set RTS high +DC92 RTS ; Return + + +************************************************************************* +* * +* Main IRQ Handling routines, default IRQ1V destination * +* * +************************************************************************* + +DC93 CLD ; Clear decimal flag +DC94 LDA &FC ; Get original value of A +DC96 PHA ; Save it +DC97 TXA ; Save X +DC98 PHA ; +DC99 TYA ; and Y +DC9A PHA ; +DC9B LDA #&DE ; Stack return address to &DE82 +DC9D PHA +DC9E LDA #&81 +DCA0 PHA +DCA1 CLV ; Clear V flag +DCA2 LDA &FE08 ; Read ACIA status register +DCA5 BVS &DCA9 ; b6 set, jump with serial parity error +DCA7 BPL &DD06 ; b7=0, no ACIA interrupt, jump to check VIAs + +; ACIA Interrupt or ACIA Parity Error +; ----------------------------------- +DCA9 LDX &EA ; Get RS423 timeout counter +DCAB DEX ; Decrement it +DCAC BMI &DCDE ; If 0 or <0, RS423 owns 6850, jump to DCDE +DCAE BVS &DCDD ; If &41..&80, nobody owns 6850, jump to exit +DCB0 JMP &F588 ; CFS owns 6850, jump to read ACIA in CFS routines + +; ACIA Data Carrier Detect +; ------------------------ +DCB3 LDY &FE09 ; Read ACIA data +DCB6 ROL A ; +DCB7 ASL A ; Rotate ACIA Status back +DCB8 TAX ; X=ACIA Status +DCB9 TYA ; A=ACIA Data +DCBA LDY #&07 ; Y=07 for RS423 Error Event +DCBC JMP &E494 ; Jump to issue event + +; ACIA IRQ, TxRDY - Send a byte +; ----------------------------- +DCBF LDX #&02 +DCC1 JSR &E460 ; Read from Serial output buffer +DCC4 BCC &DCD6 ; Buffer is not empty, jump to send byte +DCC6 LDA &0285 ; Read printer destination +DCC9 CMP #&02 ; Is it serial printer?? +DCCB BNE &DC68 ; Serial buffer empty, not Serial printer, jump to ... DC68 +DCCD INX ; X=3 for Printer buffer +DCCE JSR &E460 ; Read from Printer buffer +DCD1 ROR &02D2 ; Copy Byte Fetched/Not fetched into Printer Buffer full flag +DCD4 BMI &DC68 ; Printer buffer was empty, so jump to ... DC68 + +DCD6 STA &FE09 ; Send byte to ACIA +DCD9 LDA #&E7 ; Set timeout counter to &E7 +DCDB STA &EA ; Serial owns 6850 for 103 more calls +DCDD RTS ; Exit IRQ + +; RS423 owns 6850, PE or RxRDY interupt occured +; --------------------------------------------- +; On entry, A contains ACIA status +; +DCDE AND &0278 ; AND with ACIA IRQ mask (normally &FF) +DCE1 LSR A ; Move RxRDY into Carry +DCE2 BCC &DCEB ; If no RxData, jump to check DCD and TxRDY +; +; Data in RxData, check for errors +; +DCE4 BVS &DCEB ; If IRQ=1 (now in b6) RxIRQ must have occured, so jump to DCEB +; +; RxData but no RxIRQ, check that IRQs are actually disabled +; +DCE6 LDY &0250 ; Get ACIA control setting +DCE9 BMI &DC7D ; If bit 7=1, IRQs enabled so jump to read byte and insert into buffer +; +; DCE9 -> RxData, no RxIRQ, IRQs disabled +; DCE4 -> RxData and RxIRQ +; DCE2 -> No RxData +; +; Check TxRDY and DCD, if neither set, send a Serial Error Event +; -------------------------------------------------------------- +DCEB LSR A ; Move TxRDY into Carry +DCEC ROR A ; Rotate TxRDY into b7 and DCD into Carry +DCED BCS &DCB3 ; If Data Carrier Detected, jump to DCB3 +DCEF BMI &DCBF ; If TxRDY (now in b7) jump to to DCBF to send a byte +DCF1 BVS &DCDD ; b6 should always be zero by now, but if set, then jump to exit + +; Issue Unknown Interupt service call +; =================================== +DCF3 LDX #&05 +DCF5 JSR &F168 ; Issue service call 5, 'Unknown Interrupt' +DCF8 BEQ &DCDD ; If claimed, then jump to exit +DCFA PLA ; Otherwise drop return address from stack +DCFB PLA ; +DCFC PLA ; And restore registers +DCFD TAY ; +DCFE PLA ; +DCFF TAX ; +DD00 PLA ; +DD01 STA &FC ; Store A in IRQA +DD03 JMP (&0206) ; And pass the IRQ in to IRQ2V + + +************************************************************************* +* * +* VIA INTERUPTS ROUTINES * +* * +************************************************************************* + +DD06 LDA &FE4D ; Read System VIA interrupt flag register +DD09 BPL &DD47 ; No System VIA interrupt, jump to check User VIA + +; System VIA interupt +; +DD0B AND &0279 ; Mask with System VIA bit mask +DD0E AND &FE4E ; and interrupt enable register +DD11 ROR ; Rotate to check for CA1 interupt (frame sync) +DD12 ROR ; +DD13 BCC &DD69 ; No CA1 (frame sync), jump to check speech + +; System VIA CA1 interupt (Frame Sync) +; +DD15 DEC &0240 ;decrement vertical sync counter +DD18 LDA &EA ;A=RS423 Timeout counter +DD1A BPL &DD1E ;if +ve then DD1E +DD1C INC &EA ;else increment it +DD1E LDA &0251 ;load flash counter +DD21 BEQ &DD3D ;if 0 then system is not in use, ignore it +DD23 DEC &0251 ;else decrement counter +DD26 BNE &DD3D ;and if not 0 go on past reset routine + +DD28 LDX &0252 ;else get mark period count in X +DD2B LDA &0248 ;current VIDEO ULA control setting in A +DD2E LSR ;shift bit 0 into C to check if first colour +DD2F BCC &DD34 ;is effective if so C=0 jump to DD34 + +DD31 LDX &0253 ;else get space period count in X +DD34 ROL ;restore bit +DD35 EOR #&01 ;and invert it +DD37 JSR &EA00 ;then change colour + +DD3A STX &0251 ;&0251=X resetting the counter + +DD3D LDY #&04 ;Y=4 and call E494 to check and implement vertical +DD3F JSR &E494 ;sync event (4) if necessary +DD42 LDA #&02 ;A=2 +DD44 JMP &DE6E ;clear interrupt 1 and exit + + +************************************************************************* +* * +* PRINTER INTERRUPT USER VIA 1 * +* * +************************************************************************* + +DD47 LDA &FE6D ; Read User VIA interrupt flag register +DD4A BPL &DCF3 ; No User VIA interrupt, jump to pass to ROMs + +; User VIA interupt +; +DD4C AND &0277 ;else check for USER IRQ 1 +DD4F AND &FE6E ; +DD52 ROR ; +DD53 ROR ; +DD54 BCC &DCF3 ;if bit 1=0 the no interrupt 1 so DCF3 +DD56 LDY &0285 ;else get printer type +DD59 DEY ;decrement +DD5A BNE &DCF3 ;if not parallel then DCF3 +DD5C LDA #&02 ;reset interrupt 1 flag +DD5E STA &FE6D ; +DD61 STA &FE6E ;disable interrupt 1 +DD64 LDX #&03 ;and output data to parallel printer +DD66 JMP &E13A ; + + +************************************************************************* +* * +* SYSTEM INTERRUPT 5 Speech * +* * +************************************************************************* + +DD69 ROL ; Rotate bit 5 into bit 7 +DD6A ROL ; +DD6B ROL ; +DD6C ROL ; +DD6D BPL &DDCA ; Not a Timer 2 interrupt, jump to check timers + +; System VIA Timer 2 interupt - Speech interupt +; +DD6F LDA #&20 ; Prepare to clear VIA interupt +DD71 LDX #&00 +DD73 STA &FE4D ; Clear VIA interupt +DD76 STX &FE49 ; Zero high byte of T2 Timer +DD79 LDX #&08 ; X=8 for Speech buffer +DD7B STX &FB ; Prepare to loop up to four times for Speak from RAM + +DD7D JSR &E45B ; Examine Speech buffer +DD80 ROR &02D7 ; Shift carry into bit 7 +DD83 BMI &DDC9 ; Buffer empty, so exit +DD85 TAY ; Buffer not empty, A=first byte waiting +DD86 BEQ &DD8D ; Waiting byte=&00 (Speak, no reset), skip past +DD88 JSR &EE6D ;control speech chip +DD8B BMI &DDC9 ;if negative exit + +DD8D JSR &E460 ; Fetch Speech command byte from buffer +DD90 STA &F5 ; Store it +DD92 JSR &E460 ; Fetch Speech word high byte from buffer +DD95 STA &F7 ; Store it +DD97 JSR &E460 ; Fetch Speech word low byte from buffer +DD9A STA &F6 ; Store it, giving &F6/7=address to be accessed +DD9C LDY &F5 ; Y=Speech command byte +DD9E BEQ &DDBB ; SOUND &FF00 - Speak from RAM, no reset +DDA0 BPL &DDB8 ; SOUND &FF01-&FF7F - Speak from RAM, with reset +DDA2 BIT &F5 ; Check bit 6 of Speech command +DDA4 BVS &DDAB ; SOUND &FFC0-&FFFF - Speak word number + +; SOUND &FF80-&FFBF - Speak from absolute address +; &F5=command &80-&BF (b0-b3=PHROM number), &F6/7=address +; +DDA6 JSR &EEBB ; Write address to speech processor +DDA9 BVC &DDB2 ; Skip forward to speak from selected address + +; SOUND &FFC0-&FFFF - Speak word number +; &F5=command &C0-&FF (b0-b3=PHROM number), &F6/7=word number +; +DDAB ASL &F6 ; Multiply address by 2 to index into word table +DDAD ROL &F7 ; +DDAF JSR &EE3B ; Read address from specified PHROM + +; Speak from PHROM address +; By now, the address in the PHROM specified in Command b0-b3 has been set +; to the start of the speech data to be voiced. +; +DDB2 LDY &0261 ; Fetch command code, usually &50=Speak or &00=Nop +DDB5 JMP &EE7F ; Jump to send command to speak from current address + +; SOUND &FF01-&FF7F - Speak from RAM with reset +; Y=Speech command byte, &F6/7=Speech data +; Use SOUND &FF60 to send Speak External command +; +DDB8 JSR &EE7F ; Send command byte to Speech processor + +; SOUND &FF00 - Speak from RAM without reset +; &6/7=Speech data +; +DDBB LDY &F6 +DDBD JSR &EE7F ; Send Speech data low byte +DDC0 LDY &F7 +DDC2 JSR &EE7F ; Send Speech data high byte +DDC5 LSR &FB ; Shift loop counter +DDC7 BNE &DD7D ; Loop to send up to four byte-pairs +DDC9 RTS + +*********************************************************************** +* * +* SYSTEM INTERRUPT 6 10mS Clock * +* * +************************************************************************* + +DDCA BCC &DE47 ;bit 6 is in carry so if clear there is no 6 int + ;so go on to DE47 +DDCC LDA #&40 ;Clear interrupt 6 +DDCE STA &FE4D ; + +;UPDATE timers routine, There are 2 timer stores &292-6 and &297-B +;these are updated by adding 1 to the current timer and storing the +;result in the other, the direction of transfer being changed each +;time of update. This ensures that at least 1 timer is valid at any call +;as the current timer is only read. Other methods would cause inaccuracies +;if a timer was read whilst being updated. + +DDD1 LDA &0283 ;get current system clock store pointer (5,or 10) +DDD4 TAX ;put A in X +DDD5 EOR #&0F ;and invert lo nybble (5 becomes 10 and vv) +DDD7 PHA ;store A +DDD8 TAY ;put A in Y + + ;Carry is always set at this point +DDD9 LDA &0291,X ;get timer value +DDDC ADC #&00 ;update it +DDDE STA &0291,Y ;store result in alternate +DDE1 DEX ;decrement X +DDE2 BEQ &DDE7 ;if 0 exit +DDE4 DEY ;else decrement Y +DDE5 BNE &DDD9 ;and go back and do next byte + +DDE7 PLA ;get back A +DDE8 STA &0283 ;and store back in clock pointer (i.e. inverse previous + ;contents) +DDEB LDX #&05 ;set loop pointer for countdown timer +DDED INC &029B,X ;increment byte and if +DDF0 BNE &DDFA ;not 0 then DDFA +DDF2 DEX ;else decrement pointer +DDF3 BNE &DDED ;and if not 0 do it again +DDF5 LDY #&05 ;process EVENT 5 interval timer +DDF7 JSR &E494 ; + +DDFA LDA &02B1 ;get byte of inkey countdown timer +DDFD BNE &DE07 ;if not 0 then DE07 +DDFF LDA &02B2 ;else get next byte +DE02 BEQ &DE0A ;if 0 DE0A +DE04 DEC &02B2 ;decrement 2B2 +DE07 DEC &02B1 ;and 2B1 + +DE0A BIT &02CE ;read bit 7 of envelope processing byte +DE0D BPL &DE1A ;if 0 then DE1A +DE0F INC &02CE ;else increment to 0 +DE12 CLI ;allow interrupts +DE13 JSR &EB47 ;and do routine sound processes +DE16 SEI ;bar interrupts +DE17 DEC &02CE ;DEC envelope processing byte back to 0 + +DE1A BIT &02D7 ;read speech buffer busy flag +DE1D BMI &DE2B ;if set speech buffer is empty, skip routine +DE1F JSR &EE6D ;update speech system variables +DE22 EOR #&A0 ; +DE24 CMP #&60 ; +DE26 BCC &DE2B ;if result >=&60 DE2B +DE28 JSR &DD79 ;else more speech work + +DE2B BIT &D9B7 ;set V and C +DE2E JSR &DCA2 ;check if ACIA needs attention +DE31 LDA &EC ;check if key has been pressed +DE33 ORA &ED ; +DE35 AND &0242 ;(this is 0 if keyboard is to be ignored, else &FF) +DE38 BEQ &DE3E ;if 0 ignore keyboard +DE3A SEC ;else set carry +DE3B JSR &F065 ;and call keyboard +DE3E JSR &E19B ;check for data in user defined printer channel +DE41 BIT &FEC0 ;if ADC bit 6 is set ADC is not busy +DE44 BVS &DE4A ;so DE4A +DE46 RTS ;else return + + +************************************************************************* +* * +* SYSTEM INTERRUPT 4 ADC end of conversion * +* * +************************************************************************* + +DE47 ROL ;put original bit 4 from FE4D into bit 7 of A +DE48 BPL &DE72 ;if not set DE72 + +DE4A LDX &024C ;else get current ADC channel +DE4D BEQ &DE6C ;if 0 DE6C +DE4F LDA &FEC2 ;read low data byte +DE52 STA &02B5,X ;store it in &2B6,7,8 or 9 +DE55 LDA &FEC1 ;get high data byte +DE58 STA &02B9,X ;and store it in hi byte +DE5B STX &02BE ;store in Analogue system flag marking last channel +DE5E LDY #&03 ;handle event 3 conversion complete +DE60 JSR &E494 ; + +DE63 DEX ;decrement X +DE64 BNE &DE69 ;if X=0 +DE66 LDX &024D ;get highest ADC channel preseny +DE69 JSR &DE8F ;and start new conversion +DE6C LDA #&10 ;reset interrupt 4 +DE6E STA &FE4D ; +DE71 RTS ;and return + + +************************************************************************* +* * +* SYSTEM INTERRUPT 0 Keyboard * +* * +************************************************************************* + +DE72 ROL ;get original bit 0 in bit 7 position +DE73 ROL ; +DE74 ROL ; +DE75 ROL ; +DE76 BPL &DE7F ;if bit 7 clear not a keyboard interrupt +DE78 JSR &F065 ;else scan keyboard +DE7B LDA #&01 ;A=1 +DE7D BNE &DE6E ;and off to reset interrupt and exit + +DE7F JMP &DCF3 ; + +************** exit routine ********************************************* + +DE82 PLA ;restore registers +DE83 TAY ; +DE84 PLA ; +DE85 TAX ; +DE86 PLA ; +DE87 STA &FC ;store A + + +************************************************************************* +* * +* IRQ2V default entry * +* * +************************************************************************* + +DE89 LDA &FC ;get back original value of A +DE8B RTI ;and return to calling routine + + +************************************************************************* +* * +* OSBYTE 17 Start conversion * +* * +************************************************************************* + +DE8C STY &02BE ;set last channel to finish conversion +DE8F CPX #&05 ;if X<4 then +DE91 BCC &DE95 ;DE95 +DE93 LDX #&04 ;else X=4 + +DE95 STX &024C ;store it as current ADC channel +DE98 LDY &024E ;get conversion type +DE9B DEY ;decrement +DE9C TYA ;A=Y +DE9D AND #&08 ;and it with 08 +DE9F CLC ;clear carry +DEA0 ADC &024C ;add to current ADC +DEA3 SBC #&00 ;-1 +DEA5 STA &FEC0 ;store to the A/D control panel +DEA8 RTS ;and return + +DEA9 LDA #&C3 ;point to start of string @&C300 +DEAB STA &FE ;store it +DEAD LDA #&00 ;point to lo byte +DEAF STA &FD ;store it and start loop@ + +DEB1 INY ;print character in string +DEB2 LDA (&FD),Y ;pointed to by &FD/E +DEB4 JSR OSASCI ;print it expanding Carriage returns +DEB7 TAX ;store A in X +DEB8 BNE &DEB1 ;and loop again if not =0 +DEBA RTS ;else exit + +*********** OSBYTE 129 TIMED ROUTINE ****************************** +;ON ENTRY TIME IS IN X,Y + +DEBB STX &02B1 ;store time in INKEY countdown timer +DEBE STY &02B2 ;which is decremented every 10ms +DEC1 LDA #&FF ;A=&FF to flag timed wait +DEC3 BNE &DEC7 ;goto DEC7 + + +************************************************************************** +************************************************************************** +** ** +** OSRDCH Default entry point ** +** ** +** RDCHV entry point read a character ** +** ** +************************************************************************** +************************************************************************** + +DEC5 LDA #&00 ;A=0 to flag wait forever + +DEC7 STA &E6 ;store entry value of A +DEC9 TXA ;save X and Y +DECA PHA ; +DECB TYA ; +DECC PHA ; +DECD LDY &0256 ;get *EXEC file handle +DED0 BEQ &DEE6 ;if 0 (not open) then DEE6 +DED2 SEC ;set carry +DED3 ROR &EB ;set bit 7 of CFS active flag to prevent clashes +DED5 JSR OSBGET ;get a byte from the file +DED8 PHP ;push processor flags to preserve carry +DED9 LSR &EB ;restore &EB +DEDB PLP ;get back flags +DEDC BCC &DF03 ;and if carry clear, character found so exit via DF03 +DEDE LDA #&00 ;else A=00 as EXEC file empty +DEE0 STA &0256 ;store it in exec file handle +DEE3 JSR OSFIND ;and close file via OSFIND + +DEE6 BIT &FF ;check ESCAPE flag, if bit 7 set Escape pressed +DEE8 BMI &DF00 ;so off to DF00 +DEEA LDX &0241 ;else get current input buffer number +DEED JSR &E577 ;get a byte from input buffer +DEF0 BCC &DF03 ;and exit if character returned + +DEF2 BIT &E6 ;(E6=0 or FF) +DEF4 BVC &DEE6 ;if entry was OSRDCH not timed keypress, so go back and + ;do it again i.e. perform GET function +DEF6 LDA &02B1 ;else check timers +DEF9 ORA &02B2 ; +DEFC BNE &DEE6 ;and if not zero go round again +DEFE BCS &DF05 ;else exit + +DEF0 BCC &DF03 +DEF2 BIT &E6 +DEF4 BVC &DEE6 +DEF6 LDA &02B1 +DEF9 ORA &02B2 +DEFC BNE &DEE6 +DEFE BCS &DF05 +DF00 SEC +DF01 LDA #&1B +DF03 STA &E6 +DF05 PLA +DF06 TAY +DF07 PLA +DF08 TAX +DF09 LDA &E6 +DF0B RTS + +**** STRINGS **** + +DF0C DB ')C(',0 ; Copyright string match + +**** COMMMANDS **** +; Command Address Call goes to +DF10 DB '.',E0,31,05 ; *. &E031, A=5 FSCV, XY=>String +DF14 DB 'FX',E3,42,FF ; *FX &E342, A=&FF Number parameters +DF19 DB 'BASIC',E0,18,00 ; *BASIC &E018, A=0 XY=>String +DF21 DB 'CAT',E0,31,05 ; *CAT &E031, A=5 FSCV, XY=>String +DF27 DB 'CODE',E3,48,88 ; *CODE &E348, A=&88 OSBYTE &88 +DF2E DB 'EXEC',F6,8D,00 ; *EXEC &F68D, A=0 XY=>String +DF35 DB 'HELP',F0,B9,FF ; *HELP &F0B9, A=&FF F2/3=>String +DF3C DB 'KEY',E3,27,FF ; *KEY &E327, A=&FF F2/3=>String +DF42 DB 'LOAD',E2,3C,00 ; *LOAD &E23C, A=0 XY=>String +DF49 DB 'LINE',E6,59,01 ; *LINE &E659, A=1 USERV, XY=>String +DF50 DB 'MOTOR',E3,48,89 ; *MOTOR &E348, A=&89 OSBYTE +DF58 DB 'OPT',E3,48,8B ; *OPT &E348, A=&8B OSBYTE +DF5E DB 'RUN',E0,31,04 ; *RUN &E031, A=4 FSCV, XY=>String +DF64 DB 'ROM',E3,48,8D ; *ROM &E348, A=&8D OSBYTE +DF6A DB 'SAVE',E2,3E,00 ; *SAVE &E23E, A=0 XY=>String +DF70 DB 'SPOOL',E2,81,00 ; *SPOOL &E281, A=0 XY=>String +DF79 DB 'TAPE',E3,48,8C ; *TAPE &E348, A=&8C OSBYTE +DF80 DB 'TV',E3,48,90 ; *TV &E348, A=&90 OSBYTE +DF85 DB '',E0,31,03 ; Unmatched &E031, A=3 FSCV, XY=>String +DF88 DB 00 ; Table end marker + +; Command routines are entered with XY=>command tail, A=table parameter, +; &F2/3,&E6=>start of command string +; If table parameter if <&80, F2/3,Y converted to XY before entering + + +************************************************************************* +* CLI - COMMAND LINE INTERPRETER * +* * +* ENTRY: XY=>Command line * +* EXIT: All registers corrupted * +* [ A=13 - unterminated string ] * +************************************************************************* +; +DF89 STX &F2 ; Store XY in &F2/3 +DF8B STY &F3 +DF8D LDA #&08 +DF8F JSR &E031 ; Inform filing system CLI being processed +DF92 LDY #&00 ; Check the line is correctly terminated +DF94 LDA (&F2),Y +DF96 CMP #&0D ; Loop until CR is found +DF98 BEQ &DF9E +DF9A INY ; Move to next character +DF9B BNE &DF94 ; Loop back if less than 256 bytes long +DF9D RTS ; Exit if string > 255 characters + +; String is terminated - skip prepended spaces and '*'s +DF9E LDY #&FF +DFA0 JSR &E039 ; Skip any spaces +DFA3 BEQ &E017 ; Exit if at CR +DFA5 CMP #&2A ; Is this character '*'? +DFA7 BEQ &DFA0 ; Loop back to skip it, and check for spaces again + +DFA9 JSR &E03A ; Skip any more spaces +DFAC BEQ &E017 ; Exit if at CR +DFAE CMP #&7C ; Is it '|' - a comment +DFB0 BEQ &E017 ; Exit if so +DFB2 CMP #&2F ; Is it '/' - pass straight to filing system +DFB4 BNE &DFBE ; Jump forward if not +DFB6 INY ; Move past the '/' +DFB7 JSR &E009 ; Convert &F2/3,Y->XY, ignore returned A +DFBA LDA #&02 ; 2=RunSlashCommand +DFBC BNE &E031 ; Jump to pass to FSCV +; +; Look command up in command table +DFBE STY &E6 ; Store offset to start of command +DFC0 LDX #&00 +DFC2 BEQ &DFD7 +; +DFC4 EOR &DF10,X +DFC7 AND #&DF +DFC9 BNE &DFE2 +DFCB INY +DFCC CLC +; +DFCD BCS &DFF4 +DFCF INX +DFD0 LDA (&F2),Y +DFD2 JSR &E4E3 +DFD5 BCC &DFC4 +; +DFD7 LDA &DF10,X +DFDA BMI &DFF2 +DFDC LDA (&F2),Y +DFDE CMP #&2E +DFE0 BEQ &DFE6 +DFE2 CLC +DFE3 LDY &E6 +DFE5 DEY +DFE6 INY +DFE7 INX +DFE8 INX +DFE9 LDA &DF0E,X +DFEC BEQ &E021 +DFEE BPL &DFE8 +DFF0 BMI &DFCD +; +DFF2 INX +DFF3 INX +; +DFF4 DEX +DFF5 DEX +DFF6 PHA +DFF7 LDA &DF11,X +DFFA PHA +DFFB JSR &E03A +DFFE CLC +DFFF PHP +E000 JSR &E004 +E003 RTI ; Jump to routine + +E004 LDA &DF12,X ; Get table parameter +E007 BMI &E017 ; If >=&80, number follow +; ; else string follows + +E009 TYA ; Pass Y line offset to A for later +E00A LDY &DF12,X ; Get looked-up parameter from table + +; Convert &F2/3,A to XY, put Y in A +E00D CLC +E00E ADC &F2 +E010 TAX +E011 TYA ; Pass supplied Y into A +E012 LDY &F3 +E014 BCC &E017 +E016 INY +; +E017 RTS + + +; *BASIC +; ====== +E018 LDX &024B ; Get BASIC ROM number +E01B BMI &E021 ; If none set, jump to pass command on +E01D SEC ; Set Carry = not entering from RESET +E01E JMP &DBE7 ; Enter language rom in X + +; Pass command on to other ROMs and to filing system +E021 LDY &E6 ; Restore pointer to start of command +E023 LDX #&04 ; 4=UnknownCommand +E025 JSR &F168 ; Pass to sideways ROMs +E028 BEQ &E017 ; If claimed, exit +E02A LDA &E6 ; Restore pointer to start of command +E02C JSR &E00D ; Convert &F2/3,A to XY, ignore returned A +E02F LDA #&03 ; 3=PassCommandToFilingSystem + +; Pass to current filing system +E031 JMP (&021E) + +E034 ASL A +E035 AND #&01 +E037 BPL &E031 + +; Skip spaces +E039 INY +E03A LDA (&F2),Y +E03C CMP #&20 +E03E BEQ &E039 +E040 CMP #&0D +E042 RTS + +E043 BCC &E03A +E045 JSR &E03A +E048 CMP #&2C +E04A BNE &E040 +E04C INY +E04D RTS + +E04E JSR &E03A +E051 JSR &E07D +E054 BCC &E08D +E056 STA &E6 +E058 JSR &E07C +E05B BCC &E076 +E05D TAX +E05E LDA &E6 +E060 ASL A +E061 BCS &E08D +E063 ASL A +E064 BCS &E08D +E066 ADC &E6 +E068 BCS &E08D +E06A ASL A +E06B BCS &E08D +E06D STA &E6 +E06F TXA +E070 ADC &E6 +E072 BCS &E08D +E074 BCC &E056 +E076 LDX &E6 +E078 CMP #&0D +E07A SEC +E07B RTS + +E07C INY +E07D LDA (&F2),Y +E07F CMP #&3A +E081 BCS &E08D +E083 CMP #&30 +E085 BCC &E08D +E087 AND #&0F +E089 RTS + +E08A JSR &E045 +E08D CLC +E08E RTS + +E08F JSR &E07D +E092 BCS &E0A2 +E094 AND #&DF +E096 CMP #&47 +E098 BCS &E08A +E09A CMP #&41 +E09C BCC &E08A +E09E PHP +E09F SBC #&37 +E0A1 PLP +E0A2 INY +E0A3 RTS + +; WRCH control routine +; ==================== +E0A4 PHA ; Save all registers +E0A5 TXA +E0A6 PHA +E0A7 TYA +E0A8 PHA +E0A9 TSX +E0AA LDA &0103,X ; Get A back from stack +E0AD PHA ; Save A +E0AE BIT &0260 ; Check OSWRCH interception flag +E0B1 BPL &E0BB ; Not set, skip interception call +E0B3 TAY ; Pass character to Y +E0B4 LDA #&04 ; A=4 for OSWRCH call +E0B6 JSR &E57E ; Call interception code +E0B9 BCS &E10D ; If claimed, jump past to exit + +E0BB CLC ; Prepare to not send this to printer +E0BC LDA #&02 ; Check output destination +E0BE BIT &027C ; Is VDU driver disabled? +E0C1 BNE &E0C8 ; Yes, skip past VDU driver +E0C3 PLA ; Get character back +E0C4 PHA ; Resave character +E0C5 JSR &C4C0 ; Call VDU driver + ; On exit, C=1 if character to be sent to printer + +E0C8 LDA #&08 ; Check output destination +E0CA BIT &027C ; Is printer seperately enabled? +E0CD BNE &E0D1 ; Yes, jump to call printer driver +E0CF BCC &E0D6 ; Carry clear, don't sent to printer +E0D1 PLA ; Get character back +E0D2 PHA ; Resave character +E0D3 JSR &E114 ; Call printer driver + +E0D6 LDA &027C ; Check output destination +E0D9 ROR A ; Is serial output enabled? +E0DA BCC &E0F7 ; No, skip past serial output +E0DC LDY &EA ; Get serial timout counter +E0DE DEY ; Decrease counter +E0DF BPL &E0F7 ; Timed out, skip past serial code +E0E1 PLA ; Get character back +E0E2 PHA ; Resave character +E0E3 PHP ; Save IRQs +E0E4 SEI ; Disable IRQs +E0E5 LDX #&02 ; X=2 for serial output buffer +E0E7 PHA ; Save character +E0E8 JSR &E45B ; Examine serial output buffer +E0EB BCC &E0F0 ; Buffer not full, jump to send character +E0ED JSR &E170 ; Wait for buffer to empty a bit +E0F0 PLA ; Get character back +E0F1 LDX #&02 ; X=2 for serial output buffer +E0F3 JSR &E1F8 ; Send character to serial output buffer +E0F6 PLP ; Restore IRQs + +E0F7 LDA #&10 ; Check output destination +E0F9 BIT &027C ; Is SPOOL output disabled? +E0FC BNE &E10D ; Yes, skip past SPOOL output +E0FE LDY &0257 ; Get SPOOL handle +E101 BEQ &E10D ; If not open, skip past SPOOL output +E103 PLA ; Get character back +E104 PHA ; Resave character +E105 SEC +E106 ROR &EB ; Set RFS/CFS's 'spooling' flag +E108 JSR &FFD4 ; Write character to SPOOL channel +E10B LSR &EB ; Reset RFS/CFS's 'spooling' flag + +E10D PLA ; Restore all registers +E10E PLA +E10F TAY +E110 PLA +E111 TAX +E112 PLA +E113 RTS ; Exit + + +************************************************************************* +* * +* PRINTER DRIVER * +* * +************************************************************************* + +;A=character to print + +E114 BIT &027C ;if bit 6 of VDU byte =1 printer is disabled +E117 BVS &E139 ;so E139 + +E119 CMP &0286 ;compare with printer ignore character +E11C BEQ &E139 ;if the same E139 + +E11E PHP ;else save flags +E11F SEI ;bar interrupts +E120 TAX ;X=A +E121 LDA #&04 ;A=4 +E123 BIT &027C ;read bit 2 'disable printer driver' +E126 BNE &E138 ;if set printer is disabled so exit E138 +E128 TXA ;else A=X +E129 LDX #&03 ;X=3 +E12B JSR &E1F8 ;and put character in printer buffer +E12E BCS &E138 ;if carry set on return exit, buffer not full (empty?) + +E130 BIT &02D2 ;else check buffer busy flag if 0 +E133 BPL &E138 ;then E138 to exit +E135 JSR &E13A ;else E13A to open printer cahnnel + +E138 PLP ;get back flags +E139 RTS ;and exit + +E13A LDA &0285 ;check printer destination +E13D BEQ &E1AD ;if 0 then E1AD clear printer buffer and exit +E13F CMP #&01 ;if parallel printer not selected +E141 BNE &E164 ;E164 +E143 JSR &E460 ;else read a byte from the printer buffer +E146 ROR &02D2 ;if carry is set then 2d2 is -ve +E149 BMI &E190 ;so return via E190 +E14B LDY #&82 ;else enable interrupt 1 of the external VIA +E14D STY &FE6E ; +E150 STA &FE61 ;pass code to centronics port +E153 LDA &FE6C ;pulse CA2 line to generate STROBE signal +E156 AND #&F1 ;to advise printer that +E158 ORA #&0C ;valid data is +E15A STA &FE6C ;waiting +E15D ORA #&0E ; +E15F STA &FE6C ; +E162 BNE &E190 ;then exit + +*********:serial printer ********************************************* + +E164 CMP #&02 ;is it Serial printer?? +E166 BNE &E191 ;if not E191 +E168 LDY &EA ;else is RS423 in use by cassette?? +E16A DEY ; +E16B BPL &E1AD ;if so E1AD to flush buffer + +E16D LSR &02D2 ;else clear buffer busy flag +E170 LSR &024F ;and RS423 busy flag +E173 JSR &E741 ;count buffer if C is clear on return +E176 BCC &E190 ;no room in buffer so exit +E178 LDX #&20 ;else +E17A LDY #&9F ; + + +************************************************************************* +* * +* OSBYTE 156 update ACIA setting and RAM copy * +* * +************************************************************************* +;on entry + +E17C PHP ;push flags +E17D SEI ;bar interrupts +E17E TYA ;A=Y +E17F STX &FA ;&FA=X +E181 AND &0250 ;A=old value AND Y EOR X +E184 EOR &FA ; +E186 LDX &0250 ;get old value in X +E189 STA &0250 ;put new value in +E18C STA &FE08 ;and store to ACIA control register +E18F PLP ;get back flags +E190 RTS ;and exit + +************ printer is neither serial or parallel so its user type ***** + +E191 CLC ;clear carry +E192 LDA #&01 ;A=1 +E194 JSR &E1A2 ; + + +************************************************************************* +* * +* OSBYTE 123 Warn printer driver going dormant * +* * +************************************************************************* + +E197 ROR &02D2 ;mark printer buffer empty for osbyte +E19A RTS ;and exit + +E19B BIT &02D2 ;if bit 7 is set buffer is empty +E19E BMI &E19A ;so exit + +E1A0 LDA #&00 ;else A=0 + +E1A2 LDX #&03 ;X=3 +E1A4 LDY &0285 ;Y=printer destination +E1A7 JSR &E57E ;to JMP (NETV) +E1AA JMP (&0222) ;jump to PRINT VECTOR for special routines + +*************** Buffer handling ***************************************** + ;X=buffer number + ;Buffer number Address Flag Out pointer In pointer + ;0=Keyboard 3E0-3FF 2CF 2D8 2E1 + ;1=RS423 Input A00-AFF 2D0 2D9 2E2 + ;2=RS423 output 900-9BF 2D1 2DA 2E3 + ;3=printer 880-8BF 2D2 2DB 2E4 + ;4=sound0 840-84F 2D3 2DC 2E5 + ;5=sound1 850-85F 2D4 2DD 2E6 + ;6=sound2 860-86F 2D5 2DE 2E7 + ;7=sound3 870-87F 2D6 2DF 2E8 + ;8=speech 8C0-8FF 2D7 2E0 2E9 + +E1AD CLC ;clear carry +E1AE PHA ;save A +E1AF PHP ;save flags +E1B0 SEI ;set interrupts +E1B1 BCS &E1BB ;if carry set on entry then E1BB +E1B3 LDA &E9AD,X ;else get byte from baud rate/sound data table +E1B6 BPL &E1BB ;if +ve the E1BB +E1B8 JSR &ECA2 ;else clear sound data + +E1BB SEC ;set carry +E1BC ROR &02CF,X ;rotate buffer flag to show buffer empty +E1BF CPX #&02 ;if X>1 then its not an input buffer +E1C1 BCS &E1CB ;so E1CB + +E1C3 LDA #&00 ;else Input buffer so A=0 +E1C5 STA &0268 ;store as length of key string +E1C8 STA &026A ;and length of VDU queque +E1CB JSR &E73B ;then enter via count purge vector any user routines +E1CE PLP ;restore flags +E1CF PLA ;restore A +E1D0 RTS ;and exit + + +************************************************************************* +* * +* COUNT PURGE VECTOR DEFAULT ENTRY * +* * +************************************************************************* +;on entry if V set clear buffer +; if C set get space left +; else get bytes used + +E1D1 BVC &E1DA ;if bit 6 is set then E1DA +E1D3 LDA &02D8,X ;else start of buffer=end of buffer +E1D6 STA &02E1,X ; +E1D9 RTS ;and exit + +E1DA PHP ;push flags +E1DB SEI ;bar interrupts +E1DC PHP ;push flags +E1DD SEC ;set carry +E1DE LDA &02E1,X ;get end of buffer +E1E1 SBC &02D8,X ;subtract start of buffer +E1E4 BCS &E1EA ;if carry caused E1EA +E1E6 SEC ;set carry +E1E7 SBC &E447,X ;subtract buffer start offset (i.e. add buffer length) +E1EA PLP ;pull flags +E1EB BCC &E1F3 ;if carry clear E1F3 to exit +E1ED CLC ;clear carry +E1EE ADC &E447,X ;adc to get bytes used +E1F1 EOR #&FF ;and invert to get space left +E1F3 LDY #&00 ;Y=0 +E1F5 TAX ;X=A +E1F6 PLP ;get back flags +E1F7 RTS ;and exit + +********** enter byte in buffer, wait and flash lights if full ********** + +E1F8 SEI ;prevent interrupts +E1F9 JSR &E4B0 ;enter a byte in buffer X +E1FC BCC &E20D ;if successful exit +E1FE JSR &E9EA ;else switch on both keyboard lights +E201 PHP ;push p +E202 PHA ;push A +E203 JSR &EEEB ;switch off unselected LEDs +E206 PLA ;get back A +E207 PLP ;and flags +E208 BMI &E20D ;if return is -ve Escape pressed so exit +E20A CLI ;else allow interrupts +E20B BCS &E1F8 ;if byte didn't enter buffer go and try it again +E20D RTS ;then return + +OS SERIES VI +GEOFF COX + +************************************************************************* +* * +* *SAVE/*LOAD SETUP * +* * +************************************************************************* + +**************: clear osfile control block workspace ******************** + +E20E PHA ;push A +E20F LDA #&00 ;A=0 +E211 STA &02EE,X ;clear osfile control block workspace +E214 STA &02EF,X ; +E217 STA &02F0,X ; +E21A STA &02F1,X ; +E21D PLA ;get back A +E21E RTS ;and exit + +*********** shift through osfile control block ************************** + +E21F STY &E6 ;&E6=Y +E221 ROL ;A=A*2 +E222 ROL ;*4 +E223 ROL ;*8 +E224 ROL ;*16 +E225 LDY #&04 ;Y=4 +E227 ROL ;A=A*32 +E228 ROL &02EE,X ;shift bit 7 of A into shift register +E22B ROL &02EF,X ;and +E22E ROL &02F0,X ;shift +E231 ROL &02F1,X ;along +E234 BCS &E267 ;if carry set on exit then register has overflowed + ;so bad address error +E236 DEY ;decrement Y +E237 BNE &E227 ;and if Y>0 then do another shift +E239 LDY &E6 ;get back original Y +E23B RTS ;and exit + + +************************************************************************* +* * +* *LOAD ENTRY * +* * +************************************************************************* + +E23C LDA #&FF ;signal that load is being performed + + +************************************************************************* +* * +* *SAVE ENTRY * +* * +************************************************************************* +;on entry A=0 for save &ff for load + +E23E STX &F2 ;store address of rest of command line +E240 STY &F3 ; +E242 STX &02EE ;x and Y are stored in OSfile control block +E245 STY &02EF ; +E248 PHA ;Push A +E249 LDX #&02 ;X=2 +E24B JSR &E20E ;clear the shift register +E24E LDY #&FF ;Y=255 +E250 STY &02F4 ;store im 2F4 +E253 INY ;increment Y +E254 JSR &EA1D ;and call GSINIT to prepare for reading text line +E257 JSR &EA2F ;read a code from text line if OK read next +E25A BCC &E257 ;until end of line reached +E25C PLA ;get back A without stack changes +E25D PHA ; +E25E BEQ &E2C2 ;IF A=0 (SAVE) E2C2 +E260 JSR &E2AD ;set up file block +E263 BCS &E2A0 ;if carry set do OSFILE +E265 BEQ &E2A5 ;else if A=0 goto OSFILE + +E267 BRK ; +E268 DB &FC ; +E269 DB 'Bad Address' ;error +E274 BRK ; + + +************************************************************************* +* * +* OSBYTE 119 ENTRY * +* CLOSE SPOOL/ EXEC FILES * +* * +************************************************************************* + +E275 LDX #&10 ;X=10 issue *SPOOL/EXEC files warning +E277 JSR &F168 ;and issue call +E27A BEQ &E29F ;if a rom accepts and issues a 0 then E29F to return +E27C JSR &F68B ;else close the current exec file +E27F LDA #&00 ;A=0 + + +************************************************************************** +* * +* *SPOOL * +* * +************************************************************************** + +E281 PHP ;if A=0 file is closed so +E282 STY &E6 ;Store Y +E284 LDY &0257 ;get file handle +E287 STA &0257 ;store A as file handle +E28A BEQ &E28F ;if Y<>0 then E28F +E28C JSR OSFIND ;else close file via osfind +E28F LDY &E6 ;get back original Y +E291 PLP ;pull flags +E292 BEQ &E29F ;if A=0 on entry then exit +E294 LDA #&80 ;else A=&80 +E296 JSR OSFIND ;to open file Y for output +E299 TAY ;Y=A +E29A BEQ &E310 ;and if this is =0 then E310 BAD COMMAND ERROR +E29C STA &0257 ;store file handle +E29F RTS ;and exit + +E2A0 BNE &E310 ;if NE then BAD COMMAND error +E2A2 INC &02F4 ;increment 2F4 to 00 +E2A5 LDX #&EE ;X=&EE +E2A7 LDY #&02 ;Y=&02 +E2A9 PLA ;get back A +E2AA JMP OSFILE ;and JUMP to OSFILE + +**** check for hex digit ************************************************ + +E2AD JSR &E03A ;look for NEWline +E2B0 JSR &E08F ;carry is set if it finds hex digit +E2B3 BCC &E2C1 ;so E2C1 exit +E2B5 JSR &E20E ;clear shift register + +************** shift byte into control block *************************** + +E2B8 JSR &E21F ;shift lower nybble of A into shift register +E2BB JSR &E08F ;then check for Hex digit +E2BE BCS &E2B8 ;if found then do it again +E2C0 SEC ;else set carry +E2C1 RTS ;and exit + +**************; set up OSfile control block **************************** + +E2C2 LDX #&0A ;X=0A +E2C4 JSR &E2AD ; +E2C7 BCC &E310 ;if no hex digit found EXIT via BAD Command error +E2C9 CLV ;clear bit 6 + +******************READ file length from text line************************ + +E2CA LDA (&F2),Y ;read next byte from text line +E2CC CMP #&2B ;is it '+' +E2CE BNE &E2D4 ;if not assume its a last byte address so e2d4 +E2D0 BIT &D9B7 ;else set V and M flags +E2D3 INY ;increment Y to point to hex group + +E2D4 LDX #&0E ;X=E +E2D6 JSR &E2AD ; +E2D9 BCC &E310 ;if carry clear no hex digit so exit via error +E2DB PHP ;save flags +E2DC BVC &E2ED ;if V set them E2ED explicit end address found +E2DE LDX #&FC ;else X=&FC +E2E0 CLC ;clear carry +E2E1 LDA &01FC,X ;and add length data to start address +E2E4 ADC &0200,X ; +E2E7 STA &0200,X ; +E2EA INX ; +E2EB BNE &E2E1 ;repeat until X=0 + +E2ED LDX #&03 ;X=3 +E2EF LDA &02F8,X ;copy start adddress to load and execution addresses +E2F2 STA &02F4,X ; +E2F5 STA &02F0,X ; +E2F8 DEX ; +E2F9 BPL &E2EF ; +E2FB PLP ;get back flag +E2FC BEQ &E2A5 ;if end of command line reached then E2A5 + ; to do osfile +E2FE LDX #&06 ;else set up execution address +E300 JSR &E2AD ; +E303 BCC &E310 ;if error BAD COMMAND +E305 BEQ &E2A5 ;and if end of line reached do OSFILE + +E307 LDX #&02 ;else set up load address +E309 JSR &E2AD ; +E30C BCC &E310 ;if error BAD command +E30E BEQ &E2A5 ;else on end of line do OSFILE + ;anything else is an error!!!! + +******** Bad command error ************************************ + +E310 BRK ; +E311 DB &FE ;error number +E312 DB 'Bad Command' ; +E31D BRK +E31E DB &FB ; +E31F DB 'Bad Key' ; +E326 BRK + + +************************************************************************* +* * +* *KEY ENTRY * +* * +************************************************************************* + +E327 JSR &E04E ;set up key number in A +E32A BCC &E31D ;if not valid number give error +E32C CPX #&10 ;if key number greater than 15 +E32E BCS &E31D ;if greater then give error +E330 JSR &E045 ;otherwise skip commas, and check for CR +E333 PHP ;save flags for later +E334 LDX &0B10 ;get pointer to top of existing key strings +E337 TYA ;save Y +E338 PHA ;to preserve text pointer +E339 JSR &E3D1 ;set up soft key definition +E33C PLA ;get back Y +E33D TAY ; +E33E PLP ;and flags +E33F BNE &E377 ;if CR found return else E377 to set up new string +E341 RTS ;else return to set null string + + +************************************************************************* +* * +* *FX OSBYTE * +* * +************************************************************************* + A=number + +E342 JSR &E04E ;convert the number to binary +E345 BCC &E310 ;if bad number call bad command +E347 TXA ;save X + + +************************************************************************* +* * +* *CODE *MOTOR *OPT *ROM *TAPE *TV * +* * +************************************************************************* + ;enter codes *CODE &88 + *MOTOR &89 + *OPT &8B + *TAPE &8C + *ROM &8D + *TV &90 + +E348 PHA ;save A +E349 LDA #&00 ;clear &E4/E5 +E34B STA &E5 ; +E34D STA &E4 ; +E34F JSR &E043 ;skip commas and check for newline (CR) +E352 BEQ &E36C ;if CR found E36C +E354 JSR &E04E ;convert character to binary +E357 BCC &E310 ;if bad character bad command error +E359 STX &E5 ;else save it +E35B JSR &E045 ;skip comma and check CR +E35E BEQ &E36C ;if CR then E36C +E360 JSR &E04E ;get another parameter +E363 BCC &E310 ;if bad error +E365 STX &E4 ;else store in E4 +E367 JSR &E03A ;now we must have a newline +E36A BNE &E310 ;if none then output an error + +E36C LDY &E4 ;Y=third osbyte parameter +E36E LDX &E5 ;X=2nd +E370 PLA ;A=first +E371 JSR OSBYTE ;call osbyte +E374 BVS &E310 ;if V set on return then error +E376 RTS ;else RETURN + +********* *KEY CONTINUED ************************************************ + ;X points to last byte of current key definitions +E377 SEC ; +E378 JSR &EA1E ;look for '"' on return bit 6 E4=1 bit 7=1 if '"'found + ;this is a GSINIT call without initial CLC +E37B JSR &EA2F ;call GSREAD carry is set if end of line found +E37E BCS &E388 ;E388 to deal with end of line +E380 INX ;point to first byte of new key definition +E381 BEQ &E31D ;if X=0 buffer WILL overflow so exit with BAD KEY error +E383 STA &0B00,X ;store character +E386 BCC &E37B ;and loop to get next byte if end of line not found +E388 BNE &E31D ;if Z clear then no matching '"' found or for some + ;other reason line doesn't terminate properly +E38A PHP ;else if all OK save flags +E38B SEI ;bar interrupts +E38C JSR &E3D1 ;and move string + +E38F LDX #&10 ;set loop counter + +E391 CPX &E6 ;if key being defined is found +E393 BEQ &E3A3 ;then skip rest of loop +E395 LDA &0B00,X ;else get start of string X +E398 CMP &0B00,Y ;compare with start of string Y +E39B BNE &E3A3 ;if not the same then skip rest of loop +E39D LDA &0B10 ;else store top of string definition +E3A0 STA &0B00,X ;in designated key pointer +E3A3 DEX ;decrement loop pointer X +E3A4 BPL &E391 ;and do it all again +E3A6 PLP ;get back flags +E3A7 RTS ;and exit + +***********: set string lengths ***************************************** + +E3A8 PHP ;push flags +E3A9 SEI ;bar interrupts +E3AA LDA &0B10 ;get top of currently defined strings +E3AD SEC ; +E3AE SBC &0B00,Y ;subtract to get the number of bytes in strings + ;above end of string Y +E3B1 STA &FB ;store this +E3B3 TXA ;save X +E3B4 PHA ; +E3B5 LDX #&10 ;and X=16 + +E3B7 LDA &0B00,X ;get start offset (from B00) of key string X +E3BA SEC ; +E3BB SBC &0B00,Y ;subtract offset of string we are working on +E3BE BCC &E3C8 ;if carry clear (B00+Y>B00+X) or +E3C0 BEQ &E3C8 ;result (in A)=0 +E3C2 CMP &FB ;or greater or equal to number of bytes above + ;string we are working on +E3C4 BCS &E3C8 ;then E3C8 +E3C6 STA &FB ;else store A in &FB + +E3C8 DEX ;point to next lower key offset +E3C9 BPL &E3B7 ;and if 0 or +ve go back and do it again +E3CB PLA ;else get back value of X +E3CC TAX ; +E3CD LDA &FB ;get back latest value of A +E3CF PLP ;pull flags +E3D0 RTS ;and return + +***********: set up soft key definition ********************************* + +E3D1 PHP ;push P +E3D2 SEI ;bar interrupts +E3D3 TXA ;save X +E3D4 PHA ;push A +E3D5 LDY &E6 ;get key number + +E3D7 JSR &E3A8 ;and set up &FB +E3DA LDA &0B00,Y ;get start of string +E3DD TAY ;put it in Y +E3DE CLC ;clear carry +E3DF ADC &FB ;add number of bytes above string +E3E1 TAX ;put this in X +E3E2 STA &FA ;and store it +E3E4 LDA &0268 ;check number of bytes left to remove from key buffer + ;if not 0 key is being used (definition expanded so + ;error. This stops *KEY 1 "*key1 FRED" etc. +E3E7 BEQ &E3F6 ;if not in use continue + +E3E9 BRK ; +E3EA DB &FA ;error number +E3EB DB 'Key in use' ; +E3F5 BRK ; + +E3F6 DEC &0284 ;decrement consistence flag to &FF to warn that key + ;definitions are being changed +E3F9 PLA ;pull A +E3FA SEC ; +E3FB SBC &FA ;subtract &FA +E3FD STA &FA ;and re store it +E3FF BEQ &E40D ;if 0 then E40D + +E401 LDA &0B01,X ;else move string +E404 STA &0B01,Y ;from X to Y +E407 INY ; +E408 INX ; +E409 DEC &FA ;for length of string +E40B BNE &E401 ; + +E40D TYA ;store end of moved string(s) +E40E PHA ; +E40F LDY &E6 ;get back key number +E411 LDX #&10 ;point at top of last string + +E413 LDA &0B00,X ;get this value +E416 CMP &0B00,Y ;compare it with start of new or re defined key +E419 BCC &E422 ;if less then E422 +E41B BEQ &E422 ;if = then E422 +E41D SBC &FB ;shift key definitions accordingly +E41F STA &0B00,X ; +E422 DEX ;point to next lowest string def +E423 BPL &E413 ;and if =>0 then loop and do it again +E425 LDA &0B10 ;else make top of key definitions +E428 STA &0B00,Y ;the start of our key def +E42B PLA ;get new end of strings +E42C STA &0B10 ;and store it +E42F TAX ;put A in X +E430 INC &0284 ;reset consistency flag +E433 PLP ;restore flags +E434 RTS ;and exit + +**************** BUFFER ADDRESS HI LOOK UP TABLE ************************ +E435 DB &03 ;keyboard +E436 DB &0A ;rs423 input +E437 DB &08 ;rs423 output +E438 DB &07 ;printer +E439 DB &07 ;sound 0 +E43A DB &07 ;sound 1 +E43B DB &07 ;sound 2 +E43C DB &07 ;sound 3 +E43D DB &09 ;speech + +**************** BUFFER ADDRESS LO LOOK UP TABLE ************************ +E43E DB &00 +E43F DB &00 +E440 DB &C0 +E441 DB &C0 +E442 DB &50 +E443 DB &60 +E444 DB &70 +E445 DB &80 +E446 DB &00 + +**************** BUFFER START ADDRESS OFFSET **************************** +E447 DB &E0 +E448 DB &00 +E449 DB &40 +E44A DB &C0 +E44B DB &F0 +E44C DB &F0 +E44D DB &F0 +E44E DB &F0 +E44F DB &C0 + +*******: get nominal buffer addresses in &FA/B ************************** + + ; ON ENTRY X=buffer number + ;Buffer number Address Flag Out pointer In pointer + ;0=Keyboard 3E0-3FF 2CF 2D8 2E1 + ;1=RS423 Input A00-AFF 2D0 2D9 2E2 + ;2=RS423 output 900-9BF 2D1 2DA 2E3 + ;3=printer 880-8BF 2D2 2DB 2E4 + ;4=sound0 840-84F 2D3 2DC 2E5 + ;5=sound1 850-85F 2D4 2DD 2E6 + ;6=sound2 860-86F 2D5 2DE 2E7 + ;7=sound3 870-87F 2D6 2DF 2E8 + ;8=speech 8C0-8FF 2D7 2E0 2E9 + +E450 LDA &E43E,X ;get buffer base address lo +E453 STA &FA ;store it +E455 LDA &E435,X ;get buffer base address hi +E458 STA &FB ;store it +E45A RTS ;exit + + +************************************************************************* +* * +* OSBYTE 152 Examine Buffer status * +* * +************************************************************************* +;on entry X = buffer number +;on exit FA/B points to buffer start Y is offset to next character +;if buffer is empty C=1, Y is preserved else C=0 + +E45B BIT &D9B7 ;set V and +E45E BVS &E461 ;jump to E461 + + +************************************************************************* +* * +* OSBYTE 145 Get byte from Buffer * +* * +************************************************************************* +;on entry X = buffer number +; ON EXIT Y is character extracted +;if buffer is empty C=1, else C=0 + +E460 CLV ;clear V + +E461 JMP (&022C) ;Jump via REMV + + +************************************************************************* +* * +* REMV buffer remove vector default entry point * +* * +************************************************************************* +;on entry X = buffer number +;on exit if buffer is empty C=1, Y is preserved else C=0 + +E464 PHP ;push flags +E465 SEI ;bar interrupts +E466 LDA &02D8,X ;get output pointer for buffer X +E469 CMP &02E1,X ;compare to input pointer +E46C BEQ &E4E0 ;if equal buffer is empty so E4E0 to exit +E46E TAY ;else A=Y +E46F JSR &E450 ;and get buffer pointer into FA/B +E472 LDA (&FA),Y ;read byte from buffer +E474 BVS &E491 ;if V is set (on input) exit with CARRY clear + ;Osbyte 152 has been done +E476 PHA ;else must be osbyte 145 so save byte +E477 INY ;increment Y +E478 TYA ;A=Y +E479 BNE &E47E ;if end of buffer not reached <>0 E47E + +E47B LDA &E447,X ;get pointer start from offset table + +E47E STA &02D8,X ;set buffer output pointer +E481 CPX #&02 ;if buffer is input (0 or 1) +E483 BCC &E48F ;then E48F + +E485 CMP &02E1,X ;else for output buffers compare with buffer start +E488 BNE &E48F ;if not the same buffer is not empty so E48F + +E48A LDY #&00 ;buffer is empty so Y=0 +E48C JSR &E494 ;and enter EVENT routine to signal EVENT 0 buffer + ;becoming empty + +E48F PLA ;get back byte from buffer +E490 TAY ;put it in Y +E491 PLP ;get back flags +E492 CLC ;clear carry to indicate success +E493 RTS ;and exit + + +************************************************************************** +************************************************************************** +** ** +** CAUSE AN EVENT ** +** ** +************************************************************************** +************************************************************************** +;on entry Y=event number +;A and X may be significant Y=A, A=event no. when event generated @E4A1 +;on exit carry clear indicates action has been taken else carry set + +E494 PHP ;push flags +E495 SEI ;bar interrupts +E496 PHA ;push A +E497 STA &FA ;&FA=A +E499 LDA &02BF,Y ;get enable event flag +E49C BEQ &E4DF ;if 0 event is not enabled so exit +E49E TYA ;else A=Y +E49F LDY &FA ;Y=A +E4A1 JSR &F0A5 ;vector through &220 +E4A4 PLA ;get back A +E4A5 PLP ;get back flags +E4A6 CLC ;clear carry for success +E4A7 RTS ;and exit + +********* check event 2 character entering buffer *********************** + +E4A8 TYA ;A=Y +E4A9 LDY #&02 ;Y=2 +E4AB JSR &E494 ;check event +E4AE TAY ;Y=A + + +************************************************************************* +* * +* OSBYTE 138 Put byte into Buffer * +* * +************************************************************************* +;on entry X is buffer number, Y is character to be written + +E4AF TYA ;A=Y + +E4B0 JMP (&022A) ;jump to INSBV + + +************************************************************************* +* * +* INSBV insert character in buffer vector default entry point * +* * +************************************************************************* +;on entry X is buffer number, A is character to be written + +E4B3 PHP ;save flags +E4B4 SEI ;bar interrupts +E4B5 PHA ;save A +E4B6 LDY &02E1,X ;get buffer input pointer +E4B9 INY ;increment Y +E4BA BNE &E4BF ;if Y=0 then buffer is full else E4BF +E4BC LDY &E447,X ;get default buffer start + +E4BF TYA ;put it in A +E4C0 CMP &02D8,X ;compare it with input pointer +E4C3 BEQ &E4D4 ;if equal buffer is full so E4D4 +E4C5 LDY &02E1,X ;else get buffer end in Y +E4C8 STA &02E1,X ;and set it from A +E4CB JSR &E450 ;and point &FA/B at it +E4CE PLA ;get back byte +E4CF STA (&FA),Y ;store it in buffer +E4D1 PLP ;pull flags +E4D2 CLC ;clear carry for success +E4D3 RTS ;and exit + +E4D4 PLA ;get back byte +E4D5 CPX #&02 ;if we are working on input buffer +E4D7 BCS &E4E0 ;then E4E0 + +E4D9 LDY #&01 ;else Y=1 +E4DB JSR &E494 ;to service input buffer full event +E4DE PHA ;push A + +***** return with carry set ********************************************* + +E4DF PLA ;restore A + +E4E0 PLP ;restore flags +E4E1 SEC ;set carry +E4E2 RTS ;and exit + + +***************** CODE MODIFIER ROUTINE ********************************* +* CHECK FOR ALPHA CHARACTER * +************************************************************************* + ;ENTRY character in A + ;exit with carry set if non-Alpha character +E4E3 PHA ;Save A +E4E4 AND #&DF ;convert lower to upper case +E4E6 CMP #&41 ;is it 'A' or greater ?? +E4E8 BCC &E4EE ;if not exit routine with carry set +E4EA CMP #&5B ;is it less than 'Z' +E4EC BCC &E4EF ;if so exit with carry clear +E4EE SEC ;else clear carry +E4EF PLA ;get back original value of A +E4F0 RTS ;and Return + +*******: INSERT byte in Keyboard buffer ********************************* + +E4F1 LDX #&00 ;X=0 to indicate keyboard buffer + +************************************************************************* +* * +* OSBYTE 153 Put byte in input Buffer checking for ESCAPE * +* * +************************************************************************* +;on entry X = buffer number (either 0 or 1) +;X=1 is RS423 input +;X=0 is Keyboard +;Y is character to be written + +E4F3 TXA ;A=buffer number +E4F4 AND &0245 ;and with RS423 mode (0 treat as keyboard + ;1 ignore Escapes no events no soft keys) +E4F7 BNE &E4AF ;so if RS423 buffer AND RS423 in normal mode (1) E4AF + +E4F9 TYA ;else Y=A character to write +E4FA EOR &026C ;compare with current escape ASCII code (0=match) +E4FD ORA &0275 ;or with current ESCAPE status (0=ESC, 1=ASCII) +E500 BNE &E4A8 ;if ASCII or no match E4A8 to enter byte in buffer +E502 LDA &0258 ;else get ESCAPE/BREAK action byte +E505 ROR ;Rotate to get ESCAPE bit into carry +E506 TYA ;get character back in A +E507 BCS &E513 ;and if escape disabled exit with carry clear +E509 LDY #&06 ;else signal EVENT 6 Escape pressed +E50B JSR &E494 ; +E50E BCC &E513 ;if event handles ESCAPE then exit with carry clear +E510 JSR &E674 ;else set ESCAPE flag +E513 CLC ;clear carry +E514 RTS ;and exit + +******** get a byte from keyboard buffer and interpret as necessary ***** +;on entry A=cursor editing status 1=return &87-&8B, +;2= use cursor keys as soft keys 11-15 +;this area not reached if cursor editing is normal + +E515 ROR ;get bit 1 into carry +E516 PLA ;get back A +E517 BCS &E592 ;if carry is set return + ;else cursor keys are 'soft' +E519 TYA ;A=Y get back original key code (&80-&FF) +E51A PHA ;PUSH A +E51B LSR ;get high nybble into lo +E51C LSR ; +E51D LSR ; +E51E LSR ;A=8-&F +E51F EOR #&04 ;and invert bit 2 + ;&8 becomes &C + ;&9 becomes &D + ;&A becomes &E + ;&B becomes &F + ;&C becomes &8 + ;&D becomes &9 + ;&E becomes &A + ;&F becomes &B + +E521 TAY ;Y=A = 8-F +E522 LDA &0265,Y ;read 026D to 0274 code interpretation status + ;0=ignore key, 1=expand as 'soft' key + ;2-&FF add this to base for ASCII code + ;note that provision is made for keypad operation + ;as codes &C0-&FF cannot be generated from keyboard + ;but are recognised by OS + ; +E525 CMP #&01 ;is it 01 +E527 BEQ &E594 ;if so expand as 'soft' key via E594 +E529 PLA ;else get back original byte +E52A BCC &E539 ;if above CMP generated Carry then code 0 must have + ;been returned so E539 to ignore +E52C AND #&0F ;else add ASCII to BASE key number so clear hi nybble +E52E CLC ;clear carry +E52F ADC &0265,Y ;add ASCII base +E532 CLC ;clear carry +E533 RTS ;and exit + ; +*********** ERROR MADE IN USING EDIT FACILITY *************************** + +E534 JSR &E86F ;produce bell +E537 PLA ;get back A, buffer number +E538 TAX ;X=buffer number + +********get byte from buffer ******************************************** + +E539 JSR &E460 ;get byte from buffer X +E53C BCS &E593 ;if buffer empty E593 to exit +E53E PHA ;else Push byte +E53F CPX #&01 ;and if RS423 input buffer is not the one +E541 BNE &E549 ;then E549 + +E543 JSR &E173 ;else oswrch +E546 LDX #&01 ;X=1 (RS423 input buffer) +E548 SEC ;set carry + +E549 PLA ;get back original byte +E54A BCC &E551 ;if carry clear (I.E not RS423 input) E551 +E54C LDY &0245 ;else Y=RS423 mode (0 treat as keyboard ) +E54F BNE &E592 ;if not 0 ignore escapes etc. goto E592 + +E551 TAY ;Y=A +E552 BPL &E592 ;if code is less that &80 its simple so E592 +E554 AND #&0F ;else clear high nybble +E556 CMP #&0B ;if less than 11 then treat as special code +E558 BCC &E519 ;or function key and goto E519 +E55A ADC #&7B ;else add &7C (&7B +C) to convert codes B-F to 7-B +E55C PHA ;Push A +E55D LDA &027D ;get cursor editing status +E560 BNE &E515 ;if not 0 (normal) E515 +E562 LDA &027C ;else get character destination status + +;Bit 0 enables RS423 driver +;BIT 1 disables VDU driver +;Bit 2 disables printer driver +;BIT 3 enables printer independent of CTRL B or CTRL C +;Bit 4 disables spooled output +;BIT 5 not used +;Bit 6 disables printer driver unless VDU 1 precedes character +;BIT 7 not used + +E565 ROR ;get bit 1 into carry +E566 ROR ; +E567 PLA ; +E568 BCS &E539 ;if carry is set E539 screen disabled +E56A CMP #&87 ;else is it COPY key +E56C BEQ &E5A6 ;if so E5A6 + +E56E TAY ;else Y=A +E56F TXA ;A=X +E570 PHA ;Push X +E571 TYA ;get back Y +E572 JSR &D8CE ;execute edit action + +E575 PLA ;restore X +E576 TAX ; +E577 BIT &025F ;check econet RDCH flag +E57A BPL &E581 ;if not set goto E581 +E57C LDA #&06 ;else Econet function 6 +E57E JMP (&0224) ;to the Econet vector + +********* get byte from key string ************************************** +;on entry 0268 contains key length +;and 02C9 key string pointer to next byte + +E581 LDA &0268 ;get length of keystring +E584 BEQ &E539 ;if 0 E539 get a character from the buffer +E586 LDY &02C9 ;get soft key expansion pointer +E589 LDA &0B01,Y ;get character from string +E58C INC &02C9 ;increment pointer +E58F DEC &0268 ;decrement length + +************** exit with carry clear ************************************ + +E592 CLC ; +E593 RTS ;exit + ; +*** expand soft key strings ********************************************* +Y=pointer to sring number + +E594 PLA ;restore original code +E595 AND #&0F ;blank hi nybble to get key string number +E597 TAY ;Y=A +E598 JSR &E3A8 ;get string length in A +E59B STA &0268 ;and store it +E59E LDA &0B00,Y ;get start point +E5A1 STA &02C9 ;and store it +E5A4 BNE &E577 ;if not 0 then get byte via E577 and exit + +*********** deal with COPY key ****************************************** + +E5A6 TXA ;A=X +E5A7 PHA ;Push A +E5A8 JSR &D905 ;read a character from the screen +E5AB TAY ;Y=A +E5AC BEQ &E534 ;if not valid A=0 so BEEP +E5AE PLA ;else restore X +E5AF TAX ; +E5B0 TYA ;and Y +E5B1 CLC ;clear carry +E5B2 RTS ;and exit + +************************************************************************* +* * +* OSBYTE LOOK UP TABLE * +* * +************************************************************************* + +E5B3 DB &21,&E8 ;OSBYTE 0 (&E821) +E5B5 DB &88,&E9 ;OSBYTE 1 (&E988) +E5B7 DB &D3,&E6 ;OSBYTE 2 (&E6D3) +E5B9 DB &97,&E9 ;OSBYTE 3 (&E997) +E5BB DB &97,&E9 ;OSBYTE 4 (&E997) +E5BD DB &76,&E9 ;OSBYTE 5 (&E976) +E5BF DB &88,&E9 ;OSBYTE 6 (&E988) +E5C1 DB &8B,&E6 ;OSBYTE 7 (&E68B) +E5C3 DB &89,&E6 ;OSBYTE 8 (&E689) +E5C5 DB &B0,&E6 ;OSBYTE 9 (&E6B0) +E5C7 DB &B2,&E6 ;OSBYTE 10 (&E6B2) +E5C9 DB &95,&E9 ;OSBYTE 11 (&E995) +E5CB DB &8C,&E9 ;OSBYTE 12 (&E98C) +E5CD DB &F9,&E6 ;OSBYTE 13 (&E6F9) +E5CF DB &FA,&E6 ;OSBYTE 14 (&E6FA) +E5D1 DB &A8,&F0 ;OSBYTE 15 (&F0A8) +E5D3 DB &06,&E7 ;OSBYTE 16 (&E706) +E5D5 DB &8C,&DE ;OSBYTE 17 (&DE8C) +E5D7 DB &C8,&E9 ;OSBYTE 18 (&E9C8) +E5D9 DB &B6,&E9 ;OSBYTE 19 (&E9B6) +E5DB DB &07,&CD ;OSBYTE 20 (&CD07) +E5DD DB &B4,&F0 ;OSBYTE 21 (&F0B4) +E5DF DB &6C,&E8 ;OSBYTE 117 (&E86C) +E5E1 DB &D9,&E9 ;OSBYTE 118 (&E9D9) +E5E3 DB &75,&E2 ;OSBYTE 119 (&E275) +E5E5 DB &45,&F0 ;OSBYTE 120 (&F045) +E5E7 DB &CF,&F0 ;OSBYTE 121 (&F0CF) +E5E9 DB &CD,&F0 ;OSBYTE 122 (&F0CD) +E5EB DB &97,&E1 ;OSBYTE 123 (&E197) +E5ED DB &73,&E6 ;OSBYTE 124 (&E673) +E5EF DB &74,&E6 ;OSBYTE 125 (&E674) +E5F1 DB &5C,&E6 ;OSBYTE 126 (&E65C) +E5F3 DB &35,&E0 ;OSBYTE 127 (&E035) +E5F5 DB &4F,&E7 ;OSBYTE 128 (&E74F) +E5F7 DB &13,&E7 ;OSBYTE 129 (&E713) +E5F9 DB &29,&E7 ;OSBYTE 130 (&E729) +E5FB DB &85,&F0 ;OSBYTE 131 (&F085) +E5FD DB &23,&D9 ;OSBYTE 132 (&D923) +E5FF DB &26,&D9 ;OSBYTE 133 (&D926) +E601 DB &47,&D6 ;OSBYTE 134 (&D647) +E603 DB &C2,&D7 ;OSBYTE 135 (&D7C2) +E605 DB &57,&E6 ;OSBYTE 136 (&E657) +E607 DB &7F,&E6 ;OSBYTE 137 (&E67F) +E609 DB &AF,&E4 ;OSBYTE 138 (&E4AF) +E60B DB &34,&E0 ;OSBYTE 139 (&E034) +E60D DB &35,&F1 ;OSBYTE 140 (&F135) +E60F DB &35,&F1 ;OSBYTE 141 (&F135) +E611 DB &E7,&DB ;OSBYTE 142 (&DBE7) +E613 DB &68,&F1 ;OSBYTE 143 (&F168) +E615 DB &E3,&EA ;OSBYTE 144 (&EAE3) +E617 DB &60,&E4 ;OSBYTE 145 (&E460) +E619 DB &AA,&FF ;OSBYTE 146 (&FFAA) +E61B DB &F4,&EA ;OSBYTE 147 (&EAF4) +E61D DB &AE,&FF ;OSBYTE 148 (&FFAE) +E61F DB &F9,&EA ;OSBYTE 149 (&EAF9) +E621 DB &B2,&FF ;OSBYTE 150 (&FFB2) +E623 DB &FE,&EA ;OSBYTE 151 (&EAFE) +E625 DB &5B,&E4 ;OSBYTE 152 (&E45B) +E627 DB &F3,&E4 ;OSBYTE 153 (&E4F3) +E629 DB &FF,&E9 ;OSBYTE 154 (&E9FF) +E62B DB &10,&EA ;OSBYTE 155 (&EA10) +E62D DB &7C,&E1 ;OSBYTE 156 (&E17C) +E62F DB &A7,&FF ;OSBYTE 157 (&FFA7) +E631 DB &6D,&EE ;OSBYTE 158 (&EE6D) +E633 DB &7F,&EE ;OSBYTE 159 (&EE7F) +E635 DB &C0,&E9 ;OSBYTE 160 (&E9C0) +E637 DB &9C,&E9 ;OSBYTE 166+ +E639 DB &59,&E6 ;OSWORD &E0+ + + +************************************************************************* +* * +* OSWORD LOOK UP TABLE * +* * +************************************************************************* + +E63B DB &02,&E9 ;OSWORD 0 (&E902) +E63D DB &D5,&E8 ;OSWORD 1 (&E8D5) +E63F DB &E8,&E8 ;OSWORD 2 (&E8E8) +E641 DB &D1,&E8 ;OSWORD 3 (&E8D1) +E643 DB &E4,&E8 ;OSWORD 4 (&E8E4) +E645 DB &03,&E8 ;OSWORD 5 (&E803) +E647 DB &0B,&E8 ;OSWORD 6 (&E80B) +E649 DB &2D,&E8 ;OSWORD 7 (&E82D) +E64B DB &AE,&E8 ;OSWORD 8 (&E8AE) +E64D DB &35,&C7 ;OSWORD 9 (&C735) +E64F DB &F3,&CB ;OSWORD 10 (&CBF3) +E651 DB &48,&C7 ;OSWORD 11 (&C748) +E653 DB &E0,&C8 ;OSWORD 12 (&C8E0) +E655 DB &CE,&D5 ;OSWORD 13 (&D5CE) + + +************************************************************************* +* * +* OSBYTE 136 Execute Code via User Vector * +* * +* *CODE effectively * +* * +************************************************************************* + +E658 LDA #00 ;A=0 + + +************************************************************************* +* * +* *LINE entry * +* * +************************************************************************* + +E659 JMP (&0200) ;Jump via USERV + + +************************************************************************* +* * +* OSBYTE 126 Acknowledge detection of ESCAPE condition * +* * +************************************************************************* + +E65C LDX #&00 ;X=0 +E65E BIT &FF ;if bit 7 not set there is no ESCAPE condition +E660 BPL &E673 ;so E673 +E662 LDA &0276 ;else get ESCAPE Action, if this is 0 + ;Clear ESCAPE + ;close EXEC files + ;purge all buffers + ;reset VDU paging counter +E665 BNE &E671 ;else do none of the above +E667 CLI ;allow interrupts +E668 STA &0269 ;number of lines printed since last halt in paged + ;mode = 0 +E66B JSR &F68D ;close any open EXEC files +E66E JSR &F0AA ;clear all buffers +E671 LDX #&FF ;X=&FF to indicate ESCAPE acknowledged + + +************************************************************************* +* * +* OSBYTE 124 Clear ESCAPE condition * +* * +************************************************************************* + +E673 CLC ;clear carry + + +************************************************************************* +* * +* OSBYTE 125 Set ESCAPE flag * +* * +************************************************************************* + +E674 ROR &FF ;clear bit 7 of ESCAPE flag +E676 BIT &027A ;read bit 7 of Tube flag +E679 BMI &E67C ;if set TUBE exists so E67C +E67B RTS ;else RETURN + ; +E67C JMP &0403 ;Jump to Tube entry point + + +************************************************************************* +* * +* OSBYTE 137 Turn on Tape motor * +* * +************************************************************************* + +E67F LDA &0282 ;get serial ULA control setting +E682 TAY ;Y=A +E683 ROL ;rotate left to get bit 7 into carry +E684 CPX #&01 ;if X=1 then user wants motor on so CARRY set else + ;carry is cleared +E686 ROR ;put carry back in control RAM copy +E687 BVC &E6A7 ;if bit 6 is clear then cassette is selected + ;so write to control register and RAM copy + +E689 LDA #&38 ;A=ASCII 8 + + +************************************************************************* +* * +* OSBYTE 08/07 set serial baud rates * +* * +************************************************************************* + on entry X=baud rate + A=8 transmit + A=7 receive + +E68B EOR #&3F ;converts ASCII 8 to 7 binary and ASCII 7 to 8 binary +E68D STA &FA ;store result +E68F LDY &0282 ;get serial ULA control register setting +E692 CPX #&09 ;is it 9 or more? +E694 BCS &E6AD ;if so exit +E696 AND &E9AD,X ;and with byte from look up table +E699 STA &FB ;store it +E69B TYA ;put Y in A +E69C ORA &FA ;and or with Accumulator +E69E EOR &FA ;zero the three bits set true +E6A0 ORA &FB ;set up data read from look up table + bit 6 +E6A2 ORA #&40 ; +E6A4 EOR &025D ;write cassette/RS423 flag + +E6A7 STA &0282 ;store serial ULA flag +E6AA STA &FE10 ;and write to control register +E6AD TYA ;put Y in A to save old contents +E6AE TAX ;write new setting to X +E6AF RTS ;and return + +OS SERIES VII +GEOFF COX + +************************************************************************* +* * +* OSBYTE 9 Duration of first colour * +* * +************************************************************************* +;on entry Y=0, X=new value + +E6B0 INY ;Y is incremented to 1 +E6B1 CLC ;clear carry + + +************************************************************************* +* * +* OSBYTE 10 Duration of second colour * +* * +************************************************************************* + +;on entry Y=0 or 1 if from FX 9 call, X=new value + +E6B2 LDA &0252,Y ;get mark period count +E6B5 PHA ;push it +E6B6 TXA ;get new count +E6B7 STA &0252,Y ;store it +E6BA PLA ;get back original value +E6BB TAY ;put it in Y +E6BC LDA &0251 ;get value of flash counter +E6BF BNE &E6D1 ;if not zero E6D1 + +E6C1 STX &0251 ;else restore old value +E6C4 LDA &0248 ;get current video ULA control register setting +E6C7 PHP ;push flags +E6C8 ROR ;rotate bit 0 into carry, carry into bit 7 +E6C9 PLP ;get back flags +E6CA ROL ;rotate back carry into bit 0 +E6CB STA &0248 ;store it in RAM copy +E6CE STA &FE20 ;and ULA control register + +E6D1 BVC &E6AD ;then exit via OSBYTE 7/8 + + +************************************************************************* +* * +* OSBYTE 2 select input stream * +* * +************************************************************************* + +;on input X contains stream number + +E6D3 TXA ;A=X +E6D4 AND #&01 ;blank out bits 1 - 7 +E6D6 PHA ;push A +E6D7 LDA &0250 ;and get current ACIA control setting +E6DA ROL ;Bit 7 into carry +E6DB CPX #&01 ;if X>=1 then +E6DD ROR ;bit 7 of A=1 +E6DE CMP &0250 ;compare this with ACIA control setting +E6E1 PHP ;push processor +E6E2 STA &0250 ;put A into ACIA control setting +E6E5 STA &FE08 ;and write to control register +E6E8 JSR &E173 ;set up RS423 buffer +E6EB PLP ;get back P +E6EC BEQ &E6F1 ;if new setting different from old E6F1 else +E6EE BIT &FE09 ;set bit 6 and 7 + +E6F1 LDX &0241 ;get current input buffer number +E6F4 PLA ;get back A +E6F5 STA &0241 ;store it +E6F8 RTS ;and return + + +************************************************************************* +* * +* OSBYTE 13 disable events * +* * +************************************************************************* + + ;X contains event number 0-9 + +E6F9 TYA ;Y=0 A=0 + + +************************************************************************* +* * +* OSBYTE 14 enable events * +* * +************************************************************************* +;X contains event number 0-9 + +E6FA CPX #&0A ;if X>9 +E6FC BCS &E6AE ;goto E6AE for exit +E6FE LDY &02BF,X ;else get event enable flag +E701 STA &02BF,X ;store new value in flag +E704 BVC &E6AD ;and exit via E6AD + + +************************************************************************* +* * +* OSBYTE 16 Select A/D channel * +* * +************************************************************************* +;X contains channel number or 0 if disable conversion + +E706 BEQ &E70B ;if X=0 then E70B +E708 JSR &DE8C ;start conversion + +E70B LDA &024D ;get current maximum ADC channel number +E70E STX &024D ;store new value +E711 TAX ;put old value in X +E712 RTS ;and exit + + +************************************************************************* +* * +* OSBYTE 129 Read key within time limit * +* * +************************************************************************* +;X and Y contains either time limit in centi seconds Y=&7F max +; or Y=&FF and X=-ve INKEY value + +E713 TYA ;A=Y +E714 BMI &E721 ;if Y=&FF the E721 +E716 CLI ;else allow interrupts +E717 JSR &DEBB ;and go to timed routine +E71A BCS &E71F ;if carry set then E71F +E71C TAX ;then X=A +E71D LDA #&00 ;A=0 + +E71F TAY ;Y=A +E720 RTS ;and return + ; + ;scan keyboard +E721 TXA ;A=X +E722 EOR #&7F ;convert to keyboard input +E724 TAX ;X=A +E725 JSR &F068 ;then scan keyboard +E728 ROL ;put bit 7 into carry +E729 LDX #&FF ;X=&FF +E72B LDY #&FF ;Y=&FF +E72D BCS &E731 ;if bit 7 of A was set goto E731 (RTS) +E72F INX ;else X=0 +E730 INY ;and Y=0 +E731 RTS ;and exit + +********** check occupancy of input or free space of output buffer ******* + ;X=buffer number + ;Buffer number Address Flag Out pointer In pointer + ;0=Keyboard 3E0-3FF 2CF 2D8 2E1 + ;1=RS423 Input A00-AFF 2D0 2D9 2E2 + ;2=RS423 output 900-9BF 2D1 2DA 2E3 + ;3=printer 880-8BF 2D2 2DB 2E4 + ;4=sound0 840-84F 2D3 2DC 2E5 + ;5=sound1 850-85F 2D4 2DD 2E6 + ;6=sound2 860-86F 2D5 2DE 2E7 + ;7=sound3 870-87F 2D6 2DF 2E8 + ;8=speech 8C0-8FF 2D7 2E0 2E9 + +E732 TXA ;buffer number in A +E733 EOR #&FF ;invert it +E735 TAX ;X=A +E736 CPX #&02 ;is X>1 +E738 CLV ;clear V flag +E739 BVC &E73E ;and goto E73E count buffer + +E73B BIT &D9B7 ;set V +E73E JMP (&022E) ;CNPV defaults to E1D1 + +************* check RS423 input buffer ************************************ + +E741 SEC +E742 LDX #&01 ;X=1 to point to buffer +E744 JSR &E738 ;and count it +E747 CPY #&01 ;if the hi byte of the answer is 1 or more +E749 BCS &E74E ;then Return +E74B CPX &025B ;else compare with minimum buffer space +E74E RTS ;and exit + + +************************************************************************* +* * +* OSBYTE 128 READ ADC CHANNEL * +* * +************************************************************************* + +;ON Entry: X=0 Exit Y contains number of last channel converted +; X=channel number X,Y contain 16 bit value read from channe +; X<0 Y=&FF X returns information about various buffers +; X=&FF (keyboard ) X=number of characters in buffer +; X=&FE (RS423 Input) X=number of characters in buffer +; X=&FD (RS423 output) X=number of empty spaces in buffer +; X=&FC (Printer) X=number of empty spaces in buffer +; X=&FB (sound 0) X=number of empty spaces in buffer +; X=&FA (sound 1) X=number of empty spaces in buffer +; X=&F9 (sound 2) X=number of empty spaces in buffer +; X=&F8 (sound 3) X=number of empty spaces in buffer +; X=&F7 (Speech ) X=number of empty spaces in buffer + +E74F BMI &E732 ;if X is -ve then E732 count spaces +E751 BEQ &E75F ;if X=0 then E75F +E753 CPX #&05 ;else check for Valid channel +E755 BCS &E729 ;if not E729 set X & Y to 0 and exit +E757 LDY &02B9,X ;get conversion values for channel of interest Hi & +E75A LDA &02B5,X ;lo byte +E75D TAX ;X=lo byte +E75E RTS ;and exit + +E75F LDA &FE40 ;read system VIA port B +E762 ROR ;move high nybble to low +E763 ROR ; +E764 ROR ; +E765 ROR ; +E766 EOR #&FF ;and invert it +E768 AND #&03 ;isolate the FIRE buttons +E76A LDY &02BE ;get analogue system flag byte +E76D STX &02BE ;store X here +E770 TAX ;A=X bits 0 and 1 indicate fire buttons +E771 RTS ;and return + + +************************************************************************** +************************************************************************** +** ** +** OSBYTE DEFAULT ENTRY POINT ** +** ** +** pointed to by default BYTEV ** +** ** +************************************************************************** +************************************************************************** + +E772 PHA ;save A +E773 PHP ;save Processor flags +E774 SEI ;disable interrupts +E775 STA &EF ;store A,X,Y in zero page +E777 STX &F0 ; +E779 STY &F1 ; +E77B LDX #&07 ;X=7 to signal osbyte is being attempted +E77D CMP #&75 ;if A=0-116 +E77F BCC &E7C2 ;then E7C2 +E781 CMP #&A1 ;if A<161 +E783 BCC &E78E ;then E78E +E785 CMP #&A6 ;if A=161-165 +E787 BCC &E7C8 ;then EC78 +E789 CLC ;clear carry + +E78A LDA #&A1 ;A=&A1 +E78C ADC #&00 ; + +********* process osbyte calls 117 - 160 ***************************** + +E78E SEC ;set carry +E78F SBC #&5F ;convert to &16 to &41 (22-65) + +E791 ASL ;double it (44-130) +E792 SEC ;set carry + +E793 STY &F1 ;store Y +E795 TAY ;Y=A +E796 BIT &025E ;read econet intercept flag +E799 BPL &E7A2 ;if no econet intercept required E7A2 + +E79B TXA ;else A=X +E79C CLV ;V=0 +E79D JSR &E57E ; to JMP via ECONET vector +E7A0 BVS &E7BC ;if return with V set E7BC + +E7A2 LDA &E5B4,Y ;get address from table +E7A5 STA &FB ;store it as hi byte +E7A7 LDA &E5B3,Y ;repeat for lo byte +E7AA STA &FA ; +E7AC LDA &EF ;restore A +E7AE LDY &F1 ;Y +E7B0 BCS &E7B6 ;if carry is set E7B6 + +E7B2 LDY #&00 ;else +E7B4 LDA (&F0),Y ;get value from address pointed to by &F0/1 (Y,X) + +E7B6 SEC ;set carry +E7B7 LDX &F0 ;restore X +E7B9 JSR &F058 ;call &FA/B + +E7BC ROR ;C=bit 0 +E7BD PLP ;get back flags +E7BE ROL ;bit 0=Carry +E7BF PLA ;get back A +E7C0 CLV ;clear V +E7C1 RTS ;and exit + +*************** Process OSBYTE CALLS BELOW &75 ************************** + +E7C2 LDY #&00 ;Y=0 +E7C4 CMP #&16 ;if A<&16 +E7C6 BCC &E791 ;goto E791 + +E7C8 PHP ;push flags +E7C9 PHP ;push flags + +E7CA PLA ;pull flags +E7CB PLA ;pull flags +E7CC JSR &F168 ;offer paged ROMS service 7/8 unrecognised osbyte/word +E7CF BNE &E7D6 ;if roms don't recognise it then E7D6 +E7D1 LDX &F0 ;else restore X +E7D3 JMP &E7BC ;and exit + +E7D6 PLP ;else pull flags +E7D7 PLA ;and A +E7D8 BIT &D9B7 ;set V and C +E7DB RTS ;and return + +E7DC LDA &EB ;read cassette critical flag bit 7 = busy +E7DE BMI &E812 ;if busy then EB12 + +E7E0 LDA #&08 ;else A=8 to check current Catalogue status +E7E2 AND &E2 ;by anding with CFS status flag +E7E4 BNE &E7EA ;if not set (not in use) then E7EA RTS +E7E6 LDA #&88 ;A=%10001000 +E7E8 AND &BB ;AND with FS options (short msg bits) +E7EA RTS ;RETURN + + +************************************************************************** +************************************************************************** +** ** +** OSWORD DEFAULT ENTRY POINT ** +** ** +** pointed to by default WORDV ** +** ** +************************************************************************** +************************************************************************** + +E7EB PHA ;Push A +E7EC PHP ;Push flags +E7ED SEI ;disable interrupts +E7EE STA &EF ;store A,X,Y +E7F0 STX &F0 ; +E7F2 STY &F1 ; +E7F4 LDX #&08 ;X=8 +E7F6 CMP #&E0 ;if A=>224 +E7F8 BCS &E78A ;then E78A with carry set + +E7FA CMP #&0E ;else if A=>14 +E7FC BCS &E7C8 ;else E7C8 with carry set pass to ROMS & exit + +E7FE ADC #&44 ;add to form pointer to table +E800 ASL ;double it +E801 BCC &E793 ;goto E793 ALWAYS!! (carry clear E7F8) + ;this reads bytes from table and enters routine + + +************************************************************************* +* * +* OSWORD 05 ENTRY POINT * +* * +* read a byte from I/O memory * +* * +************************************************************************* +;block of 4 bytes set at address pointed to by 00F0/1 (Y,X) +;XY +0 ADDRESS of byte +; +4 on exit byte read + +E803 JSR &E815 ;set up address of data block +E806 LDA (&F9,X) ;get byte +E808 STA (&F0),Y ;store it +E80A RTS ;exit + + +************************************************************************* +* * +* OSWORD 06 ENTRY POINT * +* * +* write a byte to I/O memory * +* * +************************************************************************* +;block of 5 bytes set at address pointed to by 00F0/1 (Y,X) +;XY +0 ADDRESS of byte +; +4 byte to be written + +E80B JSR &E815 ;set up address +E80E LDA (&F0),Y ;get byte +E810 STA (&F9,X) ;store it +E812 LDA #&00 ;a=0 +E814 RTS ;exit + +********************: set up data block ********************************* + +E815 STA &FA ;&FA=A +E817 INY ;Y=1 +E818 LDA (&F0),Y ;get byte from block +E81A STA &FB ;store it +E81C LDY #&04 ;Y=4 +E81E LDX #&01 ;X=1 +E820 RTS ;and exit + + +************************************************************************* +* * +* OSBYTE 00 ENTRY POINT * +* * +* read OS version number * +* * +************************************************************************* + +E821 BNE &E81E ;if A <> 0 then exit else print error +E823 BRK ; +E824 DB &F7 ;error number +E825 DB 'OS 1.20' ;error message +E82C BRK + +************************************************************************* +************************************************************************* +** ** +** SOUND SYSTEM ** +** ** +************************************************************************* +************************************************************************* + +------------------------------------------------------------------------- +| | +| OSWORD 07 - Make a sound | +| | +------------------------------------------------------------------------- +; On entry, control block pointed to by &F0/1 +; Y=0 on entry +; XY +0 Channel - &hsfc for Hold, Sync, Flush, Channel +; 2 Amplitude/Envelope +; 4 Pitch +; 6 Duration + +E82D INY +E82E LDA (&F0),Y ; Get channel high byte byte +E830 CMP #&FF +E832 BEQ &E88D ; Channel &FFxx, speech command +E834 CMP #&20 ; Is channel>=&20 ? +E836 LDX #&08 ; Prepare X=8 for unrecognised OSWORD call +E838 BCS &E7CA ; Pass to sideways ROMs for channel &2000+ +E83A DEY ; Point back to channel low byte +E83B JSR &E8C9 ; Get Channel 0-3, and Cy if >=&10 for Flush +E83E ORA #&04 ; Convert to buffer number 4-7 +E840 TAX +E841 BCC &E848 ; If not Flush, skip past +E843 JSR &E1AE ; Flush buffer +E846 LDY #&01 ; Point back to channel high byte + +E848 JSR &E8C9 ; Get Sync 0-3, and Cy if >=&10 for Hold +E84B STA &FA ; Save Sync in &FA +E84D PHP ; Stack flags +E84E LDY #&06 +E850 LDA (&F0),Y ; Get Duration byte +E852 PHA ; and stack it +E853 LDY #&04 +E855 LDA (&F0),Y ; Get pitch byte +E857 PHA ; and stack it +E858 LDY #&02 ; +E85A LDA (&F0),Y ; Get amplitude/envelope byte +E85C ROL ; Move Hold into bit 0 +E85D SEC ;set carry +E85E SBC #&02 ;subract 2 +E860 ASL ;multiply by 4 +E861 ASL ; +E862 ORA &FA ;add S byte (0-3) + + ; At this point, + ; b7, 0=envelope, 1=volume + ; b6-3, envelope-1 or volume+15 + ; b2, Hold + ; b1-0, Sync + +E864 JSR &E1F8 ; Insert into buffer +E867 BCC &E887 ; Buffer not full, jump to insert the rest +E869 PLA ; Drop stacked pitch +E86A PLA ; Drop stacked duration +E86B PLP ; Restore flags + ; And exit + +------------------------------------------------------------------------- +| | +| OSBYTE 117 - Read VDU status | +| | +------------------------------------------------------------------------- + +E86C LDX &D0 ;get VDU status byte in X +E86E RTS ;and return + +************* set up sound data for Bell ******************************** + +E86F PHP ;push P +E870 SEI ;bar interrupts +E871 LDA &0263 ;get bell channel number in A +E874 AND #&07 ; (bits 0-3 only set) +E876 ORA #&04 ;set bit 2 +E878 TAX ;X=A = bell channel number +4=buffer number +E879 LDA &0264 ;get bell amplitude/envelope number +E87C JSR &E4B0 ;store it in buffer pointed to by X +E87F LDA &0266 ;get bell duration +E882 PHA ;save it +E883 LDA &0265 ;get bell frequency +E886 PHA ;save it + +; Insert sound pitch and duration into sound buffer +; +E887 SEC ; Set carry +E888 ROR &0800,X ; Set bit 7 of channel flags to indicate it's active +E88B BMI &E8A4 ; Jump forward to insert pitch and duration + +------------------------------------------------------------------------- +| | +| SOUND &FFxx - Speech System | +| | +------------------------------------------------------------------------- +; On entry, control block pointed to by &F0/1 +; Y=1 on entry +; XY +0 Channel - &FFxx - xx=Speech command +; 2 Word number/Address +; 4 Ignored +; 6 Ignored + +E88D PHP ; Save flags +E88E INY ; Y=2 +E88F LDA (&F0),Y ; Get word number low byte +E891 PHA ; and stack it +E892 INY ; Y=3 +E893 LDA (&F0),Y ; Get word number high byte +E895 PHA ; and stack it +E896 LDY #&00 ; Y=0 +E898 LDA (&F0),Y ; Get speech command +E89A LDX #&08 ; X=8 for Speech buffer +E89C JSR &E1F8 ; Insert speech command into speech buffer +E89F BCS &E869 ; Buffer full, drop stack and abandon +E8A1 ROR &02D7 ; Clear bit 7 of speech buffer busy flag + +; Insert two bytes into buffer +; +E8A4 PLA ; Get word number high byte or pitch back +E8A5 JSR &E4B0 ; Insert into speech buffer +E8A8 PLA ; Get word number low byte or duration back +E8A9 JSR &E4B0 ; Insert into speech buffer +E8AC PLP ; Restore flags +E8AD RTS ; and return + + +************************************************************************* +* * +* OSWORD 08 - Define Envelope * +* * +************************************************************************* +; On entry, control block pointed to by &F0/1 +; Y=0 on entry +; A=envelope number from (&F0),0 +;XY +0 Envelope number, also in A +; 1 bits 0-6 length of each step in centi-secsonds bit 7=0 auto repeat +; 2 change of Pitch per step (-128-+127) in section 1 +; 3 change of Pitch per step (-128-+127) in section 2 +; 4 change of Pitch per step (-128-+127) in section 3 +; 5 number of steps in section 1 (0-255) +; 6 number of steps in section 2 (0-255) +; 7 number of steps in section 3 (0-255) +; 8 change of amplitude per step during attack phase (-127 to +127) +; 9 change of amplitude per step during decay phase (-127 to +127) +; 10 change of amplitude per step during sustain phase (-127 to +127) +; 11 change of amplitude per step during release phase (-127 to +127) +; 12 target level at end of attack phase (0-126) +; 13 target level at end of decay phase (0-126) + +E8AE SBC #&01 ;set up appropriate displacement to storage area +E8B0 ASL ;A=(A-1)*16 or 15 +E8B1 ASL ; +E8B2 ASL ; +E8B3 ASL ; +E8B4 ORA #&0F ; +E8B6 TAX ;X=A +E8B7 LDA #&00 ;A=0 + +E8B9 LDY #&10 ;Y=&10 + +E8BB CPY #&0E ;is Y>=14?? +E8BD BCS &E8C1 ;yes then E8C1 +E8BF LDA (&F0),Y ;else get byte from parameter block +E8C1 STA &08C0,X ;and store it in appropriate area +E8C4 DEX ;decrement X +E8C5 DEY ;Decrement Y +E8C6 BNE &E8BB ;if not 0 then do it again +E8C8 RTS ;else exit + ;note that envelope number is NOT transferred +; +E8C9 LDA (&F0),Y ;get byte +E8CB CMP #&10 ;is it greater than 15, if so set carry +E8CD AND #&03 ;and 3 to clear bits 2-7 +E8CF INY ;increment Y +E8D0 RTS ;and exit + + +************************************************************************* +* * +* OSWORD 03 ENTRY POINT * +* * +* read interval timer * +* * +************************************************************************* +;F0/1 points to block to store data + +E8D1 LDX #&0F ;X=&F displacement from clock to timer +E8D3 BNE &E8D8 ;jump to E8D8 + + +************************************************************************* +* * +* OSWORD 01 ENTRY POINT * +* * +* read system clock * +* * +************************************************************************* +;F0/1 points to block to store data + +E8D5 LDX &0283 ;X=current system clock store pointer + +E8D8 LDY #&04 ;Y=4 +E8DA LDA &028D,X ;read byte +E8DD STA (&F0),Y ;store it in parameter block +E8DF INX ;X=x+1 +E8E0 DEY ;Y=Y-1 +E8E1 BPL &E8DA ;if Y>0 then do it again +E8E3 RTS ;else exit + + +************************************************************************* +* * +* OSWORD 04 ENTRY POINT * +* * +* write interval timer * +* * +************************************************************************* +F0/1 points to block to store data + +E8E4 LDA #&0F ;offset between clock and timer +E8E6 BNE &E8EE ;jump to E8EE ALWAYS!! + + +************************************************************************* +* * +* OSWORD 02 ENTRY POINT * +* * +* write system clock * +* * +************************************************************************* +F0/1 points to block to store data + +E8E8 LDA &0283 ;get current clock store pointer +E8EB EOR #&0F ;and invert to get inactive timer +E8ED CLC ;clear carry + +E8EE PHA ;store A +E8EF TAX ;X=A +E8F0 LDY #&04 ;Y=4 +E8F2 LDA (&F0),Y ;and transfer all 5 bytes +E8F4 STA &028D,X ;to the clock or timer +E8F7 INX ; +E8F8 DEY ; +E8F9 BPL &E8F2 ;if Y>0 then E8F2 +E8FB PLA ;get back stack +E8FC BCS &E8E3 ;if set (write to timer) E8E3 exit +E8FE STA &0283 ;write back current clock store +E901 RTS ;and exit + + +************************************************************************* +* * +* OSWORD 00 ENTRY POINT * +* * +* read line from current input to memory * +* * +************************************************************************* +;F0/1 points to parameter block +; +0/1 Buffer address for input +; +2 Maximum line length +; +3 minimum acceptable ASCII value +; +4 maximum acceptable ASCII value + +E902 LDY #&04 ;Y=4 + +E904 LDA (&F0),Y ;transfer bytes 4,3,2 to 2B3-2B5 +E906 STA &02B1,Y ; +E909 DEY ;decrement Y +E90A CPY #&02 ;until Y=1 +E90C BCS &E904 ; + +E90E LDA (&F0),Y ;get address of input buffer +E910 STA &E9 ;store it in &E9 as temporary buffer +E912 DEY ;decrement Y +E913 STY &0269 ;Y=0 store in print line counter for paged mode +E916 LDA (&F0),Y ;get lo byte of address +E918 STA &E8 ;and store in &E8 +E91A CLI ;allow interrupts +E91B BCC &E924 ;Jump to E924 + +E91D LDA #&07 ;A=7 +E91F DEY ;decrement Y +E920 INY ;increment Y +E921 JSR OSWRCH ;and call OSWRCH + +E924 JSR OSRDCH ;else read character from input stream +E927 BCS &E972 ;if carry set then illegal character or other error + ;exit via E972 +E929 TAX ;X=A +E92A LDA &027C ;A=&27C get character destination status +E92D ROR ;put VDU driver bit in carry +E92E ROR ;if this is 1 VDU driver is disabled +E92F TXA ;X=A +E930 BCS &E937 ;if Carry set E937 +E932 LDX &026A ;get number of items in VDU queque +E935 BNE &E921 ;if not 0 output character and loop round again + +E937 CMP #&7F ;if character is not delete +E939 BNE &E942 ;goto E942 +E93B CPY #&00 ;else is Y=0 +E93D BEQ &E924 ;and goto E924 +E93F DEY ;decrement Y +E940 BCS &E921 ;and if carry set E921 to output it +E942 CMP #&15 ;is it delete line &21 +E944 BNE &E953 ;if not E953 +E946 TYA ;else Y=A, if its 0 we are still reading first + ;character +E947 BEQ &E924 ;so E924 +E949 LDA #&7F ;else output DELETES + +E94B JSR OSWRCH ;until Y=0 +E94E DEY ; +E94F BNE &E94B ; + +E951 BEQ &E924 ;then read character again + +E953 STA (&E8),Y ;store character in designated buffer +E955 CMP #&0D ;is it CR? +E957 BEQ &E96C ;if so E96C +E959 CPY &02B3 ;else check the line length +E95C BCS &E91D ;if = or greater loop to ring bell +E95E CMP &02B4 ;check minimum character +E961 BCC &E91F ;if less than minimum backspace +E963 CMP &02B5 ;check maximum character +E966 BEQ &E920 ;if equal E920 +E968 BCC &E920 ;or less E920 +E96A BCS &E91F ;then JUMP E91F + +E96C JSR OSNEWL ;output CR/LF +E96F JSR &E57E ;call Econet vector + +E972 LDA &FF ;A=ESCAPE FLAG +E974 ROL ;put bit 7 into carry +E975 RTS ;and exit routine + + +************************************************************************* +* * +* OSBYTE 05 ENTRY POINT * +* * +* SELECT PRINTER TYPE * +* * +************************************************************************* + +E976 CLI ;allow interrupts briefly +E977 SEI ;bar interrupts +E978 BIT &FF ;check if ESCAPE is pending +E97A BMI &E9AC ;if it is E9AC +E97C BIT &02D2 ;else check bit 7 buffer 3 (printer) +E97F BPL &E976 ;if not empty bit 7=0 E976 + +E981 JSR &E1A4 ;check for user defined routine +E984 LDY #&00 ;Y=0 +E986 STY &F1 ;F1=0 + + +************************************************************************* +* * +* OSBYTE 01 ENTRY POINT * +* * +* READ/WRITE USER FLAG (&281) * +* * +* AND * +* * +* OSBYTE 06 ENTRY POINT * +* * +* SET PRINTER IGNORE CHARACTER * +* * +************************************************************************* +; A contains osbyte number + +E988 ORA #&F0 ;A=osbyte +&F0 +E98A BNE &E99A ;JUMP to E99A + + +************************************************************************* +* * +* OSBYTE 0C ENTRY POINT * +* * +* SET KEYBOARD AUTOREPEAT RATE * +* * +************************************************************************* + +E98C BNE &E995 ;if &F0<>0 goto E995 +E98E LDX #&32 ;if X=0 in original call then X=32 +E990 STX &0254 ;to set keyboard autorepeat delay ram copy +E993 LDX #&08 ;X=8 + + +************************************************************************* +* * +* OSBYTE 0B ENTRY POINT * +* * +* SET KEYBOARD AUTOREPEAT DELAY * +* * +************************************************************************* + +E995 ADC #&CF ;A=A+&D0 (carry set) + + +************************************************************************* +* * +* OSBYTE 03 ENTRY POINT * +* * +* SELECT OUTPUT STREAM * +* * +* AND * +* * +* * +* OSBYTE 04 ENTRY POINT * +* * +* ENABLE/DISABLE CURSOR EDITING * +* * +************************************************************************* + +E997 CLC ;c,ear carry +E998 ADC #&E9 ;A=A+&E9 + +E99A STX &F0 ;store X + + +************************************************************************* +* * +* OSBYTE A6-FF ENTRY POINT * +* * +* READ/ WRITE SYSTEM VARIABLE OSBYTE NO. +&190 * +* * +************************************************************************* + +E99C TAY ;Y=A +E99D LDA &0190,Y ;i.e. A=&190 +osbyte call! +E9A0 TAX ;preserve this +E9A1 AND &F1 ;new value = OLD value AND Y EOR X! +E9A3 EOR &F0 ; +E9A5 STA &0190,Y ;store it +E9A8 LDA &0191,Y ;get value of next byte into A +E9AB TAY ;Y=A +E9AC RTS ;and exit + +******* SERIAL BAUD RATE LOOK UP TABLE ************************************ + +E9AD DB &64 ; % 01100100 75 +E9AE DB &7F ; % 01111111 150 +E9AF DB &5B ; % 01011011 300 +E9B0 DB &6D ; % 01101101 1200 +E9B1 DB &C9 ; % 11001001 2400 +E9B2 DB &F6 ; % 11110110 4800 +E9B3 DB &D2 ; % 11010010 9600 +E9B4 DB &E4 ; % 11100100 19200 +E9B5 DB &40 ; % 01000000 + +************************************************************************* +* * +* OSBYTE &13 ENTRY POINT * +* * +* Wait for VSync * +* * +************************************************************************* + +E9B6 LDA &0240 ;read vertical sync counter +E9B9 CLI ;allow interrupts briefly +E9BA SEI ;bar interrupts +E9BB CMP &0240 ;has it changed? +E9BE BEQ &E9B9 ;no then E9B9 +; falls through and reads VDU variable X + +************************************************************************* +* * +* OSBYTE 160 ENTRY POINT * +* * +* READ VDU VARIABLE * +* * +************************************************************************* +;X contains the variable number +;0 =lefthand column in pixels current graphics window +;2 =Bottom row in pixels current graphics window +;4 =Right hand column in pixels current graphics window +;6 =Top row in pixels current graphics window +;8 =lefthand column in absolute characters current text window +;9 =Bottom row in absolute characters current text window +;10 =Right hand column in absolute characters current text window +;11 =Top row in absolute characters current text window +;12-15 current graphics origin in external coordinates +;16-19 current graphics cursor in external coordina4es +;20-23 old graphics cursor in internal coordinates +;24 current text cursor in X and Y + +E9C0 LDY &0301,X ;get VDU variable hi +E9C3 LDA &0300,X ;low +E9C6 TAX ;X=low byte +E9C7 RTS ;and exit + + +************************************************************************* +* * +* OSBYTE 18 ENTRY POINT * +* * +* RESET SOFT KEYS * +* * +************************************************************************* + +E9C8 LDA #&10 ;set consistency flag +E9CA STA &0284 ; + +E9CD LDX #&00 ;X=0 + +E9CF STA &0B00,X ;and wipe clean +E9D2 INX ;soft key buffer +E9D3 BNE &E9CF ;until X=0 again + +E9D5 STX &0284 ;zero consistency flag +E9D8 RTS ;and exit + + +************************************************************************* +* * +* OSBYTE &76 (118) SET LEDs to Keyboard Status * +* * +************************************************************************* + ;osbyte entry with carry set + ;called from &CB0E, &CAE3, &DB8B + +E9D9 PHP ;PUSH P +E9DA SEI ;DISABLE INTERUPTS +E9DB LDA #&40 ;switch on CAPS and SHIFT lock lights +E9DD JSR &E9EA ;via subroutine +E9E0 BMI &E9E7 ;if ESCAPE exists (M set) E9E7 +E9E2 CLC ;else clear V and C +E9E3 CLV ;before calling main keyboard routine to +E9E4 JSR &F068 ;switch on lights as required +E9E7 PLP ;get back flags +E9E8 ROL ;and rotate carry into bit 0 +E9E9 RTS ;Return to calling routine + ; +***************** Turn on keyboard lights and Test Escape flag ************ + ;called from &E1FE, &E9DD + ; +E9EA BCC &E9F5 ;if carry clear +E9EC LDY #&07 ;switch on shift lock light +E9EE STY &FE40 ; +E9F1 DEY ;Y=6 +E9F2 STY &FE40 ;switch on Caps lock light +E9F5 BIT &FF ;set minus flag if bit 7 of &00FF is set indicating +E9F7 RTS ;that ESCAPE condition exists, then return + ; +****************** Write A to SYSTEM VIA register B ************************* + ;called from &CB6D, &CB73 +E9F8 PHP ;push flags +E9F9 SEI ;disable interupts +E9FA STA &FE40 ;write register B from Accumulator +E9FD PLP ;get back flags +E9FE RTS ;and exit + + +************************************************************************* +* * +* OSBYTE 154 (&9A) SET VIDEO ULA * +* * +************************************************************************* + +E9FF TXA ;osbyte entry! X transferred to A thence to + +*******Set Video ULA control register **entry from VDU routines ************** + ;called from &CBA6, &DD37 + +EA00 PHP ;save flags +EA01 SEI ;disable interupts +EA02 STA &0248 ;save RAM copy of new parameter +EA05 STA &FE20 ;write to control register +EA08 LDA &0253 ;read space count +EA0B STA &0251 ;set flash counter to this value +EA0E PLP ;get back status +EA0F RTS ;and return + + +************************************************************************* +* * +* OSBYTE &9B (155) write to palette register * +* * +************************************************************************* +;entry X contains value to write +EA10 TXA ;A=X +EA11 EOR #&07 ;convert to palette format +EA13 PHP ; +EA14 SEI ;prevent interrupts +EA15 STA &0249 ;store as current palette setting +EA18 STA &FE21 ;store actual colour in register +EA1B PLP ;get back flags +EA1C RTS ;and exit + + +************************************************************************* +* GSINIT string initialisation * +* F2/3 points to string offset by Y * +* * +* ON EXIT * +* Z flag set indicates null string, * +* Y points to first non blank character * +* A contains first non blank character * +************************************************************************* + +EA1D CLC ;clear carry + +EA1E ROR &E4 ;Rotate moves carry to &E4 +EA20 JSR &E03A ;get character from text +EA23 INY ;increment Y to point at next character +EA24 CMP #&22 ;check to see if its '"' +EA26 BEQ &EA2A ;if so EA2A (carry set) +EA28 DEY ;decrement Y +EA29 CLC ;clear carry +EA2A ROR &E4 ;move bit 7 to bit 6 and put carry in bit 7 +EA2C CMP #&0D ;check to see if its CR to set Z +EA2E RTS ;and return + + +************************************************************************* +* GSREAD string read routine * +* F2/3 points to string offset by Y * +* * +************************************************************************* + ; +EA2F LDA #&00 ;A=0 +EA31 STA &E5 ;store A +EA33 LDA (&F2),Y ;read first character +EA35 CMP #&0D ;is it CR +EA37 BNE &EA3F ;if not goto EA3F +EA39 BIT &E4 ;if bit 7=1 no 2nd '"' found +EA3B BMI &EA8F ;goto EA8F +EA3D BPL &EA5A ;if not EA5A + +EA3F CMP #&20 ;is less than a space? +EA41 BCC &EA8F ;goto EA8F +EA43 BNE &EA4B ;if its not a space EA4B +EA45 BIT &E4 ;is bit 7 of &E4 =1 +EA47 BMI &EA89 ;if so goto EA89 +EA49 BVC &EA5A ;if bit 6 = 0 EA5A +EA4B CMP #&22 ;is it '"' +EA4D BNE &EA5F ;if not EA5F +EA4F BIT &E4 ;if so and Bit 7 of &E4 =0 (no previous ") +EA51 BPL &EA89 ;then EA89 +EA53 INY ;else point at next character +EA54 LDA (&F2),Y ;get it +EA56 CMP #&22 ;is it '"' +EA58 BEQ &EA89 ;if so then EA89 + +EA5A JSR &E03A ;read a byte from text +EA5D SEC ;and return with +EA5E RTS ;carry set + ; +EA5F CMP #&7C ;is it '|' +EA61 BNE &EA89 ;if not EA89 +EA63 INY ;if so increase Y to point to next character +EA64 LDA (&F2),Y ;get it +EA66 CMP #&7C ;and compare it with '|' again +EA68 BEQ &EA89 ;if its '|' then EA89 +EA6A CMP #&22 ;else is it '"' +EA6C BEQ &EA89 ;if so then EA89 +EA6E CMP #&21 ;is it ! +EA70 BNE &EA77 ;if not then EA77 +EA72 INY ;increment Y again +EA73 LDA #&80 ;set bit 7 +EA75 BNE &EA31 ;loop back to EA31 to set bit 7 in next CHR +EA77 CMP #&20 ;is it a space +EA79 BCC &EA8F ;if less than EA8F Bad String Error +EA7B CMP #&3F ;is it '?' +EA7D BEQ &EA87 ;if so EA87 +EA7F JSR &EABF ;else modify code as if CTRL had been pressed +EA82 BIT &D9B7 ;if bit 6 set +EA85 BVS &EA8A ;then EA8A +EA87 LDA #&7F ;else set bits 0 to 6 in A + +EA89 CLV ;clear V +EA8A INY ;increment Y +EA8B ORA &E5 ; +EA8D CLC ;clear carry +EA8E RTS ;Return + ; +EA8F BRK ; +EA90 DB &FD ;error number +EA93 DB 'Bad String' ; message +EA9B BRK ; + +************ Modify code as if SHIFT pressed ***************************** + +EA9C CMP #&30 ;if A='0' skip routine +EA9E BEQ &EABE ; +EAA0 CMP #&40 ;if A='@' skip routine +EAA2 BEQ &EABE ; +EAA4 BCC &EAB8 ;if A<'@' then EAB8 +EAA6 CMP #&7F ;else is it DELETE + +EAA8 BEQ &EABE ;if so skip routine +EAAA BCS &EABC ;if greater than &7F then toggle bit 4 +EAAC EOR #&30 ;reverse bits 4 and 5 +EAAE CMP #&6F ;is it &6F (previously ' _' (&5F)) +EAB0 BEQ &EAB6 ;goto EAB6 +EAB2 CMP #&50 ;is it &50 (previously '`' (&60)) +EAB4 BNE &EAB8 ;if not EAB8 +EAB6 EOR #&1F ;else continue to convert ` _ +EAB8 CMP #&21 ;compare &21 '!' +EABA BCC &EABE ;if less than return +EABC EOR #&10 ;else finish conversion by toggling bit 4 +EABE RTS ;exit + ; + ;ASCII codes &00 &20 no change + ;21-3F have bit 4 reverses (31-3F) + ;41-5E A-Z have bit 5 reversed a-z + ;5F & 60 are reversed + ;61-7E bit 5 reversed a-z becomes A-Z + ;DELETE unchanged + ;&80+ has bit 4 changed + +************** Implement CTRL codes ************************************* + +EABF CMP #&7F ;is it DEL +EAC1 BEQ &EAD1 ;if so ignore routine +EAC3 BCS &EAAC ;if greater than &7F go to EAAC +EAC5 CMP #&60 ;if A<>'`' +EAC7 BNE &EACB ;goto EACB +EAC9 LDA #&5F ;if A=&60, A=&5F + +EACB CMP #&40 ;if A<&40 +EACD BCC &EAD1 ;goto EAD1 and return unchanged +EACF AND #&1F ;else zero bits 5 to 7 +EAD1 RTS ;return + ; +EAD2 DB '/!BOOT',&0D + +OS SERIES 8 +GEOFF COX + +************************************************************************* +* * +* OSBYTE &F7 (247) INTERCEPT BREAK * +* * +************************************************************************* + +EAD9 LDA &0287 ;get BREAK vector code +EADC EOR #&4C ;produces 0 if JMP not in &287 +EADE BNE &EAF3 ;if not goto EAF3 +EAE0 JMP &0287 ;else jump to user BREAK code + + +************************************************************************* +* * +* OSBYTE &90 (144) *TV * +* * +************************************************************************* + + ;X=display delay + ;Y=interlace flag + +EAE3 LDA &0290 ;VDU vertical adjustment +EAE6 STX &0290 ;store new value +EAE9 TAX ;put old value in X +EAEA TYA ;put interlace flag in A +EAEB AND #&01 ;maximum value =1 +EAED LDY &0291 ;get old value into Y +EAF0 STA &0291 ;put new value into A +EAF3 RTS ;and Exit + + +************************************************************************* +* * +* OSBYTE &93 (147) WRITE TO FRED * +* * +************************************************************************* + ;X is offset within page + ;Y is byte to write +EAF4 TYA ; +EAF5 STA &FC00,X ; +EAF8 RTS ; + + +************************************************************************* +* * +* OSBYTE &95 (149) WRITE TO JIM * +* * +************************************************************************* + ;X is offset within page + ;Y is byte to write + ; +EAF9 TYA ; +EAFA STA &FD00,X ; +EAFD RTS ; + + +************************************************************************* +* * +* OSBYTE &97 (151) WRITE TO SHEILA * +* * +************************************************************************* + ;X is offset within page + ;Y is byte to write + ; +EAFE TYA ; +EAFF STA &FE00,X ; +EB02 RTS ; + +****************** Silence a sound channel ******************************* + ;X=channel number + +EB03 LDA #&04 ;mark end of release phase +EB05 STA &0808,X ;to channel X +EB08 LDA #&C0 ;load code for zero volume + +****** if sound not disabled set sound generator volume ****************** + +EB0A STA &0804,X ;store A to give basic sound level of Zero +EB0D LDY &0262 ;get sound output/enable flag +EB10 BEQ &EB14 ;if sound enabled goto EB14 +EB12 LDA #&C0 ;else load zero sound code +EB14 SEC ;set carry +EB15 SBC #&40 ;subtract &40 +EB17 LSR ;divide by 8 +EB18 LSR ;to get into bits 0 - 3 +EB19 LSR ; +EB1A EOR #&0F ;invert bits 0-3 +EB1C ORA &EB3C,X ;get channel number into top nybble +EB1F ORA #&10 ; + +EB21 PHP ; + +EB22 SEI ;disable interrupts +EB23 LDY #&FF ;System VIA port A all outputs +EB25 STY &FE43 ;set +EB28 STA &FE4F ;output A on port A +EB2B INY ;Y=0 +EB2C STY &FE40 ;enable sound chip +EB2F LDY #&02 ;set and +EB31 DEY ;execute short delay +EB32 BNE &EB31 ; +EB34 LDY #&08 ;then disable sound chip again +EB36 STY &FE40 ; +EB39 LDY #&04 ;set delay +EB3B DEY ;and loop delay +EB3C BNE &EB3B ; +EB3E PLP ;get back flags +EB3F RTS ;and exit + +*******: Sound parameters look up table ********************************** + +EB40 DB &E0,&C0,&A0,&80 + +EB44 JMP &EC59 ;just to allow relative branches in early part + ;of sound interrupt routine + + +************************************************************************* +* * +* PROCESS SOUND INTERRUPT * +* * +************************************************************************* + +EB47 LDA #&00 ; +EB49 STA &083B ;zero number of channels on hold for sync +EB4C LDA &0838 ;get number of channels required for sync +EB4F BNE &EB57 ;if this <>0 then EB57 +EB51 INC &083B ;else number of chanels on hold for sync =1 +EB54 DEC &0838 ;number of channels required for sync =255 + +EB57 LDX #&08 ;set loop counter +EB59 DEX ;loop +EB5A LDA &0800,X ;get value of &800 +offset (sound queue occupancy) +EB5D BEQ &EB44 ;if 0 goto EC59 no sound this channel +EB5F LDA &02CF,X ;else get buffer busy flag +EB62 BMI &EB69 ;if negative (buffer empty) goto EB69 +EB64 LDA &0818,X ;else if duration count not zer0 +EB67 BNE &EB6C ;goto EB6C +EB69 JSR &EC6B ;check and pick up new sound if required +EB6C LDA &0818,X ;if duration count 0 +EB6F BEQ &EB84 ;goto EB84 +EB71 CMP #&FF ;else if it is &FF (infinite duration) +EB73 BEQ &EB87 ;go onto EB87 +EB75 DEC &081C,X ;decrement 10 mS count +EB78 BNE &EB87 ;and if 0 +EB7A LDA #&05 ;reset to 5 +EB7C STA &081C,X ;to give 50 mSec delay +EB7F DEC &0818,X ;and decrement main counter +EB82 BNE &EB87 ;if not zero then EB87 +EB84 JSR &EC6B ;else check and get nw sound +EB87 LDA &0824,X ;if step progress counter is 0 no envelope involved +EB8A BEQ &EB91 ;so jump to EB91 +EB8C DEC &0824,X ;else decrement it +EB8F BNE &EB44 ;and if not zero go on to EC59 +EB91 LDY &0820,X ;get envelope data offset from (8C0) +EB94 CPY #&FF ;if 255 no envelope set so +EB96 BEQ &EB44 ;goto EC59 +EB98 LDA &08C0,Y ;else get get step length +EB9B AND #&7F ;zero repeat bit +EB9D STA &0824,X ;and store it +EBA0 LDA &0808,X ;get phase counter +EBA3 CMP #&04 ;if release phase completed +EBA5 BEQ &EC07 ;goto EC07 +EBA7 LDA &0808,X ;else start new step by getting phase +EBAA CLC ; +EBAB ADC &0820,X ;add it to interval multiplier +EBAE TAY ;transfer to Y +EBAF LDA &08CB,Y ;and get target value base for envelope +EBB2 SEC ; +EBB3 SBC #&3F ; +EBB5 STA &083A ;store modified number as current target amplitude +EBB8 LDA &08C7,Y ;get byte from envelope store +EBBB STA &0839 ;store as current amplitude step +EBBE LDA &0804,X ;get base volumelevel +EBC1 PHA ;save it +EBC2 CLC ;clear carry +EBC3 ADC &0839 ;add to current amplitude step +EBC6 BVC &EBCF ;if no overflow +EBC8 ROL ;double it Carry = bit 7 +EBC9 LDA #&3F ;if bit =1 A=&3F +EBCB BCS &EBCF ;into &EBCF +EBCD EOR #&FF ;else toggle bits (A=&C0) + + ;at this point the BASIC volume commands are converted + ; &C0 (0) to &38 (-15) 3 times, In fact last 3 bits + ;are ignored so &3F represents -15 + +EBCF STA &0804,X ;store in current volume +EBD2 ROL ;multiply by 2 +EBD3 EOR &0804,X ;if bits 6 and 7 are equal +EBD6 BPL &EBE1 ;goto &EBE1 +EBD8 LDA #&3F ;if carry clear A=&3F (maximum) +EBDA BCC &EBDE ;or +EBDC EOR #&FF ;&C0 minimum + +EBDE STA &0804,X ;and this is stored in current volume + +EBE1 DEC &0839 ;decrement amplitude change per step +EBE4 LDA &0804,X ;get volume again +EBE7 SEC ;set carry +EBE8 SBC &083A ;subtract target value +EBEB EOR &0839 ;negative value undicates correct trend +EBEE BMI &EBF9 ;so jump to next part +EBF0 LDA &083A ;else enter new phase +EBF3 STA &0804,X ; +EBF6 INC &0808,X ; + +EBF9 PLA ;get the old volume level +EBFA EOR &0804,X ;and compare with the old +EBFD AND #&F8 ; +EBFF BEQ &EC07 ;if they are the same goto EC07 +EC01 LDA &0804,X ;else set new level +EC04 JSR &EB0A ;via EB0A +EC07 LDA &0810,X ;get absolute pitch value +EC0A CMP #&03 ;if it =3 +EC0C BEQ &EC59 ;skip rest of loop as all sections are finished +EC0E LDA &0814,X ;else if 814,X is not 0 current section is not + ;complete +EC11 BNE &EC3D ;so EC3D +EC13 INC &0810,X ;else implement a section change +EC16 LDA &0810,X ;check if its complete +EC19 CMP #&03 ;if not +EC1B BNE &EC2D ;goto EC2D +EC1D LDY &0820,X ;else set A from +EC20 LDA &08C0,Y ;&820 and &8C0 (first envelope byte) +EC23 BMI &EC59 ;if negative there is no repeat +EC25 LDA #&00 ;else restart section sequence +EC27 STA &0830,X ; +EC2A STA &0810,X ; + +EC2D LDA &0810,X ;get number of steps in new section +EC30 CLC ; +EC31 ADC &0820,X ; +EC34 TAY ; +EC35 LDA &08C4,Y ; +EC38 STA &0814,X ;set in 814+X +EC3B BEQ &EC59 ;and if 0 then EC59 + +EC3D DEC &0814,X ;decrement +EC40 LDA &0820,X ;and pick up rate of pitch change +EC43 CLC ; +EC44 ADC &0810,X ; +EC47 TAY ; +EC48 LDA &08C1,Y ; +EC4B CLC ; +EC4C ADC &0830,X ;add to rate of differential pitch change +EC4F STA &0830,X ;and save it +EC52 CLC ; +EC53 ADC &080C,X ;ad to base pitch +EC56 JSR &ED01 ;and set new pitch + +EC59 CPX #&04 ;if X=4 (last channel) +EC5B BEQ &EC6A ;goto EC6A (RTS) +EC5D JMP &EB59 ;else do loop again + +EC60 LDX #&08 ;X=7 again +EC62 DEX ;loop +EC63 JSR &ECA2 ;clear channel +EC66 CPX #&04 ;if not 4 +EC68 BNE &EC62 ;do it again +EC6A RTS ;and return + ; +EC6B LDA &0808,X ;check for last channel +EC6E CMP #&04 ;is it 4 (release complete) +EC70 BEQ &EC77 ;if so EC77 +EC72 LDA #&03 ;else mark release in progress +EC74 STA &0808,X ;and store it +EC77 LDA &02CF,X ;is buffer not empty +EC7A BEQ &EC90 ;if so EC90 +EC7C LDA #&00 ;else mark buffer not empty +EC7E STA &02CF,X ;an store it + +EC81 LDY #&04 ;loop counter +EC83 STA &082B,Y ;zero sync bytes +EC86 DEY ; +EC87 BNE &EC83 ;until Y=0 + +EC89 STA &0818,X ;zero duration count +EC8C DEY ;and set sync count to +EC8D STY &0838 ;&FF +EC90 LDA &0828,X ;get synchronising flag +EC93 BEQ &ECDB ;if its 0 then ECDB +EC95 LDA &083B ;else get number of channels on hold +EC98 BEQ &ECD0 ;if 0 then ECD0 +EC9A LDA #&00 ;else +EC9C STA &0828,X ;zero note length interval +EC9F JMP &ED98 ;and goto ED98 + +ECA2 JSR &EB03 ;silence the channel +ECA5 TYA ;Y=0 A=Y +ECA6 STA &0818,X ;zero main count +ECA9 STA &02CF,X ;mark buffer not empty +ECAC STA &0800,X ;mark channel dormant +ECAF LDY #&03 ;loop counter +ECB1 STA &082C,Y ;zero sync flags +ECB4 DEY ; +ECB5 BPL &ECB1 ; + +ECB7 STY &0838 ;number of channels to &FF +ECBA BMI &ED06 ;jump to ED06 ALWAYS + +ECBC PHP ;save flags +ECBD SEI ;and disable interrupts +ECBE LDA &0808,X ;check for end of release +ECC1 CMP #&04 ; +ECC3 BNE &ECCF ;and if not found ECCF +ECC5 JSR &E45B ;elseexamine buffer +ECC8 BCC &ECCF ;if not empty ECCF +ECCA LDA #&00 ;else mark channel dormant +ECCC STA &0800,X ; +ECCF PLP ;get back flags + +ECD0 LDY &0820,X ;if no envelope 820=&FF +ECD3 CPY #&FF ; +ECD5 BNE &ECDA ;then terminate sound +ECD7 JSR &EB03 ;via EB03 +ECDA RTS ;else return + +************ Synchronise sound routines ********************************** + +ECDB JSR &E45B ;examine buffer if empty carry set +ECDE BCS &ECBC ; +ECE0 AND #&03 ;else examine next word if>3 or 0 +ECE2 BEQ &EC9F ;goto ED98 (via EC9F) +ECE4 LDA &0838 ;else get synchronising count +ECE7 BEQ &ECFE ;in 0 (complete) goto ECFE +ECE9 INC &0828,X ;else set sync flag +ECEC BIT &0838 ;if 0838 is +ve S has already been set so +ECEF BPL &ECFB ;jump to ECFB +ECF1 JSR &E45B ;else get first byte +ECF4 AND #&03 ;mask bits 0,1 +ECF6 STA &0838 ;and store result +ECF9 BPL &ECFE ;Jump to ECFE (ALWAYS!!) + +ECFB DEC &0838 ;decrement 0838 +ECFE JMP &ECD0 ;and silence the channel if envelope not in use + +************ Pitch setting *********************************************** + +ED01 CMP &082C,X ;If A=&82C,X then pitch is unchanged +ED04 BEQ &ECDA ;then exit via ECDA +ED06 STA &082C,X ;store new pitch +ED09 CPX #&04 ;if X<>4 then not noise so +ED0B BNE &ED16 ;jump to ED16 + +*********** Noise setting ************************************************ + +ED0D AND #&0F ;convert to chip format +ED0F ORA &EB3C,X ; +ED12 PHP ;save flags +ED13 JMP &ED95 ;and pass to chip control routine at EB22 via ED95 + +ED16 PHA ; +ED17 AND #&03 ; +ED19 STA &083C ;lose eigth tone surplus +ED1C LDA #&00 ; +ED1E STA &083D ; +ED21 PLA ;get back A +ED22 LSR ;divide by 12 +ED23 LSR ; +ED24 CMP #&0C ; +ED26 BCC &ED2F ; +ED28 INC &083D ;store result +ED2B SBC #&0C ;with remainder in A +ED2D BNE &ED24 ; + ;at this point 83D defines the Octave + ;A the semitone within the octave +ED2F TAY ;Y=A +ED30 LDA &083D ;get octave number into A +ED33 PHA ;push it +ED34 LDA &EDFB,Y ;get byte from look up table +ED37 STA &083D ;store it +ED3A LDA &EE07,Y ;get byte from second table +ED3D PHA ;push it +ED3E AND #&03 ;keep two LS bits only +ED40 STA &083E ;save them +ED43 PLA ;pull second table byte +ED44 LSR ;push hi nybble into lo nybble +ED45 LSR ; +ED46 LSR ; +ED47 LSR ; +ED48 STA &083F ;store it +ED4B LDA &083D ;get back octave number +ED4E LDY &083C ;adjust for surplus eighth tones +ED51 BEQ &ED5F ; +ED53 SEC ; +ED54 SBC &083F ; +ED57 BCS &ED5C ; +ED59 DEC &083E ; +ED5C DEY ; +ED5D BNE &ED53 ; +ED5F STA &083D ; +ED62 PLA ; +ED63 TAY ; +ED64 BEQ &ED6F ; +ED66 LSR &083E ; +ED69 ROR &083D ; +ED6C DEY ; +ED6D BNE &ED66 ; +ED6F LDA &083D ; +ED72 CLC ; +ED73 ADC &C43D,X ; +ED76 STA &083D ; +ED79 BCC &ED7E ; +ED7B INC &083E ; +ED7E AND #&0F ; +ED80 ORA &EB3C,X ; +ED83 PHP ;push P +ED84 SEI ;bar interrupts +ED85 JSR &EB21 ;set up chip access 1 +ED88 LDA &083D ; +ED8B LSR &083E ; +ED8E ROR ; +ED8F LSR &083E ; +ED92 ROR ; +ED93 LSR ; +ED94 LSR ; +ED95 JMP &EB22 ;set up chip access 2 and return + +**************** Pick up and interpret sound buffer data ***************** + +ED98 PHP ;push flags +ED99 SEI ;disable interrupts +ED9A JSR &E460 ;read a byte from buffer +ED9D PHA ;push A +ED9E AND #&04 ;isolate H bit +EDA0 BEQ &EDB7 ;if 0 then EDB7 +EDA2 PLA ;get back A +EDA3 LDY &0820,X ;if &820,X=&FF +EDA6 CPY #&FF ;envelope is not in use +EDA8 BNE &EDAD ; +EDAA JSR &EB03 ;so call EB03 to silence channel + +EDAD JSR &E460 ;clear buffer of redundant data +EDB0 JSR &E460 ;and again +EDB3 PLP ;get back flags +EDB4 JMP &EDF7 ;set main duration count using last byte from buffer + +EDB7 PLA ;get back A +EDB8 AND #&F8 ;zero bits 0-2 +EDBA ASL ;put bit 7 into carry +EDBB BCC &EDC8 ;if zero (envelope) jump to EDC8 +EDBD EOR #&FF ;invert A +EDBF LSR ;shift right +EDC0 SEC ; +EDC1 SBC #&40 ;subtract &40 +EDC3 JSR &EB0A ;and set volume +EDC6 LDA #&FF ;A=&FF + +EDC8 STA &0820,X ;get envelope no.-1 *16 into A +EDCB LDA #&05 ;set duration sub-counter +EDCD STA &081C,X ; +EDD0 LDA #&01 ;set phase counter +EDD2 STA &0824,X ; +EDD5 LDA #&00 ;set step counter +EDD7 STA &0814,X ; +EDDA STA &0808,X ;and envelope phase +EDDD STA &0830,X ;and pitch differential +EDE0 LDA #&FF ; +EDE2 STA &0810,X ;set step count +EDE5 JSR &E460 ;read pitch +EDE8 STA &080C,X ;set it +EDEB JSR &E460 ;read buffer +EDEE PLP ; +EDEF PHA ;save duration +EDF0 LDA &080C,X ;get back pitch value +EDF3 JSR &ED01 ;and set it +EDF6 PLA ;get back duration +EDF7 STA &0818,X ;set it +EDFA RTS ;and return + +********************* Pitch look up table 1***************************** +EDFB DB &F0 +EDFC DB &B7 +EDFD DB &82 +EDFE DB &4F +EDFF DB &20 +EE00 DB &F3 +EE01 DB &C8 +EE02 DB &A0 +EE03 DB &7B +EE04 DB &57 +EE05 DB &35 +EE06 DB &16 + +********************* Pitch look up table 2 ***************************** + +EE07 DB &E7 +EE08 DB &D7 +EE09 DB &CB +EE0A DB &C3 +EE0B DB &B7 +EE0C DB &AA +EE0D DB &A2 +EE0E DB &9A +EE0F DB &92 +EE10 DB &8A +EE11 DB &82 +EE12 DB &7A + +*********: set current filing system ROM/PHROM ************************** +EE13 LDA #&EF ;get ROM +EE15 STA &F5 ;store it +EE17 RTS ;return + +********** Get byte from data ROM *************************************** + +EE18 LDX #&0D ;X=13 +EE1A INC &F5 ; +EE1C LDY &F5 ;get Rom +EE1E BPL &EE59 ;if +ve it's a sideways ROM else it's a PHROM +EE20 LDX #&00 ;PHROM +EE22 STX &F7 ;set address pointer in PHROM +EE24 INX ; +EE25 STX &F6 ;to 0001 +EE27 JSR &EEBB ;pass info to speech processor +EE2A LDX #&03 ;X=3 + +EE2C JSR &EE62 ;check for speech processor and output until + ;it reports, read byte from ROM +EE2F CMP &DF0C,X ;if A<> DF0C+X then EE18 (DF0C = (C)) +EE32 BNE &EE18 ; +EE34 DEX ;else decrement X +EE35 BPL &EE2C ;and do it again +EE37 LDA #&3E ; +EE39 STA &F6 ;get noe lo byte address +EE3B JSR &EEBB ;pass info to speech processor +EE3E LDX #&FF ; +EE40 JSR &EE62 ;check for speech proc. etc. +EE43 LDY #&08 ; +EE45 ASL ; +EE46 ROR &F7,X ; +EE48 DEY ; +EE49 BNE &EE45 ; +EE4B INX ; +EE4C BEQ &EE40 ; +EE4E CLC ; +EE4F BCC &EEBB ; + +************ ROM SERVICE ************************************************ + +EE51 LDX #&0E ; +EE53 LDY &F5 ;if Y is negative (PHROM) +EE55 BMI &EE62 ;GOTO EE62 +EE57 LDY #&FF ;else Y=255 +EE59 PHP ;push flags +EE5A JSR &F168 ;offer paged rom service +EE5D PLP ;pull processor flags +EE5E CMP #&01 ;if A>0 set carry +EE60 TYA ;A=Y +EE61 RTS ;return + +********* PHROM SERVICE ************************************************* + ; +EE62 PHP ;push processor flags +EE63 SEI ;disable interrupts +EE64 LDY #&10 ;Y=16 +EE66 JSR &EE7F ;call EE7F (osbyte 159 write to speech processor +EE69 LDY #&00 ;Y=0 +EE6B BEQ &EE84 ;Jump to EE84 (ALWAYS!!) + + +************************************************************************* +* * +* OSBYTE 158 read from speech processor * +* * +************************************************************************* + +EE6D LDY #&00 ;Y=0 to set speech proc to read +EE6F BEQ &EE82 ;jump to EE82 always + + ;write A to speech processor as two nybbles + +EE71 PHA ;push A +EE72 JSR &EE7A ;to write to speech processor +EE75 PLA ;get back A +EE76 ROR ;bring upper nybble to lower nybble +EE77 ROR ;by rotate right +EE78 ROR ;4 times +EE79 ROR ; + +EE7A AND #&0F ;Y=lo nybble A +&40 +EE7C ORA #&40 ; +EE7E TAY ;forming command for speech processor + + +************************************************************************* +* * +* OSBYTE 159 Write to speech processor * +* * +************************************************************************* +; on entry data or command in Y + +EE7F TYA ;transfer command to A +EE80 LDY #&01 ;to set speech proc to write + + ;if Y=0 read speech processor + ;if Y=1 write speech processor + +EE82 PHP ;push flags +EE83 SEI ;disable interrupts +EE84 BIT &027B ;test for prescence of speech processor +EE87 BPL &EEAA ;if not there goto EEAA +EE89 PHA ;else push A +EE8A LDA &F075,Y ; +EE8D STA &FE43 ;set DDRA of system VIA to give 8 bit input (Y=0) + ;or 8 bit output (Y=1) +EE90 PLA ;get back A +EE91 STA &FE4F ;and send to speech chip +EE94 LDA &F077,Y ;output Prt B of system VIA +EE97 STA &FE40 ;to select read or write (dependent on Y) +EE9A BIT &FE40 ;loop until +EE9D BMI &EE9A ;speech proceessor reports ready (bit 7 Prt B=0) +EE9F LDA &FE4F ;read speech processor data if input selected +EEA2 PHA ;push A +EEA3 LDA &F079,Y ;reset speech +EEA6 STA &FE40 ;processor +EEA9 PLA ;get back A + +EEAA PLP ;get back flags +EEAB TAY ;transfer A to Y +EEAC RTS ;and exit routine + ; +EEAD LDA &03CB ;set rom displacement pointer +EEB0 STA &F6 ;in &F6 +EEB2 LDA &03CC ; +EEB5 STA &F7 ;And &F7 +EEB7 LDA &F5 ;if F5 is +ve ROM is selected so +EEB9 BPL &EED9 ;goto EED9 + +EEBB PHP ;else push processor +EEBC SEI ;disable interrupts +EEBD LDA &F6 ;get lo displacement +EEBF JSR &EE71 ;pass two nyblles to speech proc. +EEC2 LDA &F5 ;&FA=&F5 +EEC4 STA &FA ; +EEC6 LDA &F7 ;get hi displacement value +EEC8 ROL ;replace two most significant bits of A +EEC9 ROL ;by 2 LSBs of &FA +EECA LSR &FA ; +EECC ROR ; +EECD LSR &FA ; +EECF ROR ; +EED0 JSR &EE71 ;pass two nybbles to speech processor +EED3 LDA &FA ;FA has now been divided by 4 so pass +EED5 JSR &EE7A ;lower nybble to speech proc. +EED8 PLP ;get back flags +EED9 RTS ;and Return + +************ Keyboard Input and housekeeping ************************ + ;entered from &F00C + +EEDA LDX #&FF ; +EEDC LDA &EC ;get value of most recently pressed key +EEDE ORA &ED ;Or it with previous key to check for presses +EEE0 BNE &EEE8 ;if A=0 no keys pressed so off you go +EEE2 LDA #&81 ;else enable keybd interupt only by writing bit 7 +EEE4 STA &FE4E ;and bit 0 of system VIA interupt register +EEE7 INX ;set X=0 +EEE8 STX &0242 ;reset keyboard semaphore + +**********: Turn on Keyboard indicators ******************************* +EEEB PHP ;save flags +EEEC LDA &025A ;read keyboard status; + ;Bit 7 =1 shift enabled + ;Bit 6 =1 control pressed + ;bit 5 =0 shift lock + ;Bit 4 =0 Caps lock + ;Bit 3 =1 shift pressed +EEEF LSR ;shift Caps bit into bit 3 +EEF0 AND #&18 ;mask out all but 4 and 3 +EEF2 ORA #&06 ;returns 6 if caps lock OFF &E if on +EEF4 STA &FE40 ;turn on or off caps light if required +EEF7 LSR ;bring shift bit into bit 3 +EEF8 ORA #&07 ; +EEFA STA &FE40 ;turn on or off shift lock light +EEFD JSR &F12E ;set keyboard counter +EF00 PLA ;get back flags +EF01 RTS ;return + + +************************************************************************* +* * +* MAIN KEYBOARD HANDLING ROUTINE ENTRY FROM KEYV * +* ========================================================== * +* * +* ENTRY CONDITIONS * +* ================ * +* C=0, V=0 Test Shift and CTRL keys.. exit with N set if CTRL pressed * +* ........with V set if Shift pressed * +* * +* C=1, V=0 Scan Keyboard as OSBYTE &79 * +* * +* C=0, V=1 Key pressed interrupt entry * +* * +* C=1, V=1 Timer interrupt entry * +* * +************************************************************************* + +EF02 BVC &EF0E ;if V is clear then leave interrupt routine +EF04 LDA #&01 ;disable keyboard interrupts +EF06 STA &FE4E ;by writing to VIA interrupt vector +EF09 BCS &EF13 ;if timer interrupt then EF13 +EF0B JMP &F00F ;else to F00F + +EF0E BCC &EF16 ;if test SHFT & CTRL goto EF16 +EF10 JMP &F0D1 ;else to F0D1 + ;to scan keyboard +************************************************************************* +* Timer interrupt entry * +************************************************************************* + +EF13 INC &0242 ;increment keyboard semaphore (to 0) + + +************************************************************************* +* Test Shift and Control Keys entry * +************************************************************************* + +EF16 LDA &025A ;read keyboard status; + ;Bit 7 =1 shift enabled + ;Bit 6 =1 control pressed + ;bit 5 =0 shift lock + ;Bit 4 =0 Caps lock + ;Bit 3 =1 shift pressed +EF19 AND #&B7 ;zero bits 3 and 6 +EF1B LDX #&00 ;zero X to test for shift key press +EF1D JSR &F02A ;interrogate keyboard X=&80 if key determined by + ;X on entry is pressed +EF20 STX &FA ;save X +EF22 CLV ;clear V +EF23 BPL &EF2A ;if no key press (X=0) then EF2A else +EF25 BIT &D9B7 ;set M and V +EF28 ORA #&08 ;set bit 3 to indicate Shift was pressed +EF2A INX ;check the control key +EF2B JSR &F02A ;via keyboard interrogate +EF2E BCC &EEEB ;if carry clear (entry via EF16) then off to EEEB + ;to turn on keyboard lights as required +EF30 BPL &EF34 ;if key not pressed goto EF30 +EF32 ORA #&40 ;or set CTRL pressed bit in keyboard status byte in A +EF34 STA &025A ;save status byte +EF37 LDX &EC ;if no key previously pressed +EF39 BEQ &EF4D ;then EF4D +EF3B JSR &F02A ;else check to see if key still pressed +EF3E BMI &EF50 ;if so enter repeat routine at EF50 +EF40 CPX &EC ;else compare X with last key pressed (set flags) +EF42 STX &EC ;store X in last key pressed +EF44 BNE &EF4D ;if different from previous (Z clear) then EF4D +EF46 LDX #&00 ;else zero +EF48 STX &EC ;last key pressed +EF4A JSR &F01F ;and reset repeat system +EF4D JMP &EFE9 ; + +********** REPEAT ACTION ************************************************* + +EF50 CPX &EC ;if X<>than last key pressed +EF52 BNE &EF42 ;then back to EF42 +EF54 LDA &E7 ;else get value of AUTO REPEAT COUNTDOWN TIMER +EF56 BEQ &EF7B ;if 0 goto EF7B +EF58 DEC &E7 ;else decrement +EF5A BNE &EF7B ;and if not 0 goto EF7B + ;this means that either the repeat system is dormant + ;or it is not at the end of its count +EF5C LDA &02CA ;next value for countdown timer +EF5F STA &E7 ;store it +EF61 LDA &0255 ;get auto repeat rate from 0255 +EF64 STA &02CA ;store it as next value for Countdown timer +EF67 LDA &025A ;get keyboard status +EF6A LDX &EC ;get last key pressed +EF6C CPX #&D0 ;if not SHIFT LOCK key (&D0) goto +EF6E BNE &EF7E ;EF7E +EF70 ORA #&90 ;sets shift enabled, & no caps lock all else preserved +EF72 EOR #&A0 ;reverses shift lock disables Caps lock and Shift enab +EF74 STA &025A ;reset keyboard status +EF77 LDA #&00 ;and set timer +EF79 STA &E7 ;to 0 +EF7B JMP &EFE9 ; + +EF7E CPX #&C0 ;if not CAPS LOCK +EF80 BNE &EF91 ;goto EF91 +EF82 ORA #&A0 ;sets shift enabled and disables SHIFT LOCK +EF84 BIT &FA ;if bit 7 not set by (EF20) shift NOT pressed +EF86 BPL &EF8C ;goto EF8C +EF88 ORA #&10 ;else set CAPS LOCK not enabled +EF8A EOR #&80 ;reverse SHIFT enabled + +EF8C EOR #&90 ;reverse both SHIFT enabled and CAPs Lock +EF8E JMP &EF74 ;reset keyboard status and set timer + +*********** get ASCII code ********************************************* + ;on entry X=key pressed internal number + +EF91 LDA &EFAB,X ;get code from look up table +EF94 BNE &EF99 ;if not zero goto EF99 else TAB pressed +EF96 LDA &026B ;get TAB character + +EF99 LDX &025A ;get keyboard status +EF9C STX &FA ;store it in &FA +EF9E ROL &FA ;rotate to get CTRL pressed into bit 7 +EFA0 BPL &EFA9 ;if CTRL NOT pressed EFA9 + +EFA2 LDX &ED ;get no. of previously pressed key +EFA4 BNE &EF4A ;if not 0 goto EF4A to reset repeat system etc. +EFA6 JSR &EABF ;else perform code changes for CTRL + +EFA9 ROL &FA ;move shift lock into bit 7 +EFAB BMI &EFB5 ;if not effective goto EFB5 else +EFAD JSR &EA9C ;make code changes for SHIFT + +EFB0 ROL &FA ;move CAPS LOCK into bit 7 +EFB2 JMP &EFC1 ;and Jump to EFC1 + +EFB5 ROL &FA ;move CAPS LOCK into bit 7 +EFB7 BMI &EFC6 ;if not effective goto EFC6 +EFB9 JSR &E4E3 ;else make changes for CAPS LOCK on, return with + ;C clear for Alphabetic codes +EFBC BCS &EFC6 ;if carry set goto EFC6 else make changes for +EFBE JSR &EA9C ;SHIFT as above + +EFC1 LDX &025A ;if shift enabled bit is clear +EFC4 BPL &EFD1 ;goto EFD1 +EFC6 ROL &FA ;else get shift bit into 7 +EFC8 BPL &EFD1 ;if not set goto EFD1 +EFC8 BPL &EFD1 ;if not set goto EFD1 +EFCA LDX &ED ;get previous key press +EFCC BNE &EFA4 ;if not 0 reset repeat system etc. via EFA4 +EFCE JSR &EA9C ;else make code changes for SHIFT +EFD1 CMP &026C ;if A<> ESCAPE code +EFD4 BNE &EFDD ;goto EFDD +EFD6 LDX &0275 ;get Escape key status +EFD9 BNE &EFDD ;if ESCAPE returns ASCII code goto EFDD +EFDB STX &E7 ;store in Auto repeat countdown timer + +EFDD TAY ; +EFDE JSR &F129 ;disable keyboard +EFE1 LDA &0259 ;read Keyboard disable flag used by Econet +EFE4 BNE &EFE9 ;if keyboard locked goto EFE9 +EFE6 JSR &E4F1 ;put character in input buffer +EFE9 LDX &ED ;get previous keypress +EFEB BEQ &EFF8 ;if none EFF8 +EFED JSR &F02A ;examine to see if key still pressed +EFF0 STX &ED ;store result +EFF2 BMI &EFF8 ;if pressed goto EFF8 +EFF4 LDX #&00 ;else zero X +EFF6 STX &ED ;and &ED + +EFF8 LDX &ED ;get &ED +EFFA BNE &F012 ;if not 0 goto F012 +EFFC LDY #&EC ;get first keypress into Y +EFFE JSR &F0CC ;scan keyboard from &10 (osbyte 122) + +F001 BMI &F00C ;if exit is negative goto F00C +F003 LDA &EC ;else make last key the +F005 STA &ED ;first key pressed i.e. rollover + +F007 STX &EC ;save X into &EC +F009 JSR &F01F ;set keyboard repeat delay +F00C JMP &EEDA ;go back to EEDA + + +************************************************************************* +* Key pressed interrupt entry point * +************************************************************************* + ;enters with X=key +F00F JSR &F02A ;check if key pressed + +F012 LDA &EC ;get previous key press +F014 BNE &F00C ;if none back to housekeeping routine +F016 LDY #&ED ;get last keypress into Y +F018 JSR &F0CC ;and scan keyboard +F01B BMI &F00C ;if negative on exit back to housekeeping +F01D BPL &F007 ;else back to store X and reset keyboard delay etc. + +**************** Set Autorepeat countdown timer ************************** + +F01F LDX #&01 ;set timer to 1 +F021 STX &E7 ; +F023 LDX &0254 ;get next timer value +F026 STX &02CA ;and store it +F029 RTS ; + +*************** Interrogate Keyboard routine *********************** + ; +F02A LDY #&03 ;stop Auto scan +F02C STY &FE40 ;by writing to system VIA +F02F LDY #&7F ;set bits 0 to 6 of port A to input on bit 7 + ;output on bits 0 to 6 +F031 STY &FE43 ; +F034 STX &FE4F ;write X to Port A system VIA +F037 LDX &FE4F ;read back &80 if key pressed (M set) +F03A RTS ;and return + + +************************************************************************* +* * +* KEY TRANSLATION TABLES * +* * +* 7 BLOCKS interspersed with unrelated code * +************************************************************************* + +key data block 1 + +F03B DB 71,33,34,35,84,38,87,2D,5E,8C + ; q ,3 ,4 ,5 ,f4,8 ,f7,- ,^ ,rt + + +************************************************************************* +* * +* OSBYTE 120 Write KEY pressed Data * +* * +************************************************************************* + +F045 STY &EC ;store Y as latest key pressed +F047 STX &ED ;store X as previous key pressed +F049 RTS ;and exit + +key data block 2 + +F04A DB 80,77,65,74,37,69,39,30,5F,8E + ; f0,w ,e ,t ,7 ,i ,9 ,0 ,_ ,lft + +F055 JMP (&FDFE) ;Jim paged entry vector +F058 JMP (&FA) ; + +key data block 3 + +F05A DB 31,32,64,72,36,75,6F,70,5B,8F + ; 1 ,2 ,d ,r ,6 ,u ,o ,p ,[ ,dn + + +************************************************************************* +* * +* Main entry to keyboard routines * +* * +************************************************************************* + +F065 BIT &D9B7 ;set V and M +F068 JMP (&0228) ;i.e. KEYV + +key data block 4 + +F06B DB 01,61,78,66,79,6A,6B,40,3A,0D + ; CL,a ,x ,f ,y ,j ,k ,@ ,: ,RETN N.B CL=CAPS LOCK + +speech routine data +F075 DB 00,FF,01,02,09,0A + +key data block 5 + +F07B DB 02,73,63,67,68,6E,6C,3B,5D,7F + ; SL,s ,c ,g ,h ,n ,l ,; ,] ,DEL N.B. SL=SHIFT LOCK + + +************************************************************************* +* * +* OSBYTE 131 READ OSHWM (PAGE in BASIC) * +* * +************************************************************************* + +F085 LDY &0244 ;read current OSHWM +F088 LDX #&00 ; +F08A RTS ; + +key data block 6 + +F08B DB 00 ,7A,20 ,76,62,6D,2C,2E,2F,8B + ; TAB,Z ,SPACE,V ,b ,m ,, ,. ,/ ,copy + +***** set input buffer number and flush it ***************************** + +F095 LDX &0241 ;get current input buffer +F098 JMP &E1AD ;flush it + +key data block 7 + +F09B DB 1B,81,82,83,85,86,88,89,5C,8D + ; ESC,f1,f2,f3,f5,f6,f8,f9,\ , + +F0A5 JMP (&0220) ;goto eventV handling routine + + +************************************************************************* +* * +* OSBYTE 15 FLUSH SELECTED BUFFER CLASS * +* * +************************************************************************* + + ;flush selected buffer + ;X=0 flush all buffers + ;X>1 flush input buffer + +F0A8 BNE &F095 ;if X<>1 flush input buffer only +F0AA LDX #&08 ;else load highest buffer number (8) +F0AC CLI ;allow interrupts +F0AD SEI ;briefly! +F0AE JSR &F0B4 ;flush buffer +F0B1 DEX ;decrement X to point at next buffer +F0B2 BPL &F0AC ;if X>=0 flush next buffer + ;at this point X=255 + + +************************************************************************* +* * +* OSBYTE 21 FLUSH SPECIFIC BUFFER * +* * +************************************************************************* +;on entry X=buffer number + +F0B4 CPX #&09 ;is X<9? +F0B6 BCC &F098 ;if so flush buffer or else +F0B8 RTS ;exit + +************************************************************************* +* * +* Issue *HELP to ROMS * +* * +************************************************************************* +F0B9 LDX #&09 ; +F0BB JSR &F168 ; +F0BE JSR &FA4A ;print following message routine return after BRK +F0C1 DB &0D ;carriage return +F0C2 DS 'OS 1.20' ;help message +F0C9 DB &0D ;carriage return +F0CA BRK ; +F0CB RTS ; + +************************************************************************* +* * +* OSBYTE 122 KEYBOARD SCAN FROM &10 (16) * +* * +************************************************************************* + +F0CC CLC ;clear carry +F0CD LDX #&10 ;set X to 10 + + +************************************************************************* +* * +* OSBYTE 121 KEYBOARD SCAN FROM VALUE IN X * +* * +************************************************************************* + +F0CF BCS &F068 ;if carry set (by osbyte 121) F068 + ;Jmps via KEYV and hence back to; + + +************************************************************************* +* Scan Keyboard C=1, V=0 entry via KEYV * +************************************************************************* + +F0D1 TXA ;if X is +ve goto F0D9 +F0D2 BPL &F0D9 ; +F0D4 JSR &F02A ;else interrogate keyboard +F0D7 BCS &F12E ;if carry set F12E to set Auto scan else +F0D9 PHP ;push flags +F0DA BCC &F0DE ;if carry clear goto FODE else +F0DC LDY #&EE ;set Y so next operation saves to 2cd +F0DE STA &01DF,Y ;can be 2cb,2cc or 2cd +F0E1 LDX #&09 ;set X to 9 +F0E3 JSR &F129 ;select auto scan +F0E6 LDA #&7F ;set port A for input on bit 7 others outputs +F0E8 STA &FE43 ; +F0EB LDA #&03 ;stop auto scan +F0ED STA &FE40 ; +F0F0 LDA #&0F ;select non-existent keyboard column F (0-9 only!) +F0F2 STA &FE4F ; +F0F5 LDA #&01 ;cancel keyboard interrupt +F0F7 STA &FE4D ; +F0FA STX &FE4F ;select column X (9 max) +F0FD BIT &FE4D ;if bit 1 =0 there is no keyboard interrupt so +F100 BEQ &F123 ;goto F123 +F102 TXA ;else put column address in A + +F103 CMP &01DF,Y ;compare with 1DF+Y +F106 BCC &F11E ;if less then F11E +F108 STA &FE4F ;else select column again +F10B BIT &FE4F ;and if bit 7 is 0 +F10E BPL &F11E ;then F11E +F110 PLP ;else push and pull flags +F111 PHP ; +F112 BCS &F127 ;and if carry set goto F127 +F114 PHA ;else Push A +F115 EOR &0000,Y ;EOR with EC,ED, or EE depending on Y value +F118 ASL ;shift left +F119 CMP #&01 ;set carry if = or greater than number holds EC,ED,EE +F11B PLA ;get back A +F11C BCS &F127 ;if carry set F127 +F11E CLC ;else clear carry +F11F ADC #&10 ;add 16 +F121 BPL &F103 ;and do it again if 0==3 C set X=3 Z set +F13D JMP &F14B ; + +******** set cassette options ******************************************* + ;called after BREAK etc + ;lower nybble sets sequential access + ;upper sets load and save options + + ;0000 Ignore errors, no messages + ;0001 Abort if error, no messages + ;0010 Retry after error, no messages + ;1000 Ignore error short messages + ;1001 Abort if error short messages + ;1010 Retry after error short messages + ;1100 Ignore error long messages + ;1101 Abort if error long messages + ;1110 Retry after error long messages + +F140 PHP ;save flags +F141 LDA #&A1 ;set sequential access abort if error, no messages +F143 STA &E3 ;set load/save retry if error, short messages +F145 LDA #&19 ;set interblock gap +F147 STA &03D1 ;and store it +F14A PLP ;get back flags + +F14B PHP ;push flags +F14C LDA #&06 ;get close files command to FSCV +F14E JSR &E031 ;and gosub OSFSC +F151 LDX #&06 ; +F153 PLP ;get back flags +F154 BEQ &F157 ;if Z set earlier +F156 DEX ;do not decrement X +F157 STX &C6 ;set current baud rate X=5 300 baud X=6 1200 baud + +********* reset FILEV,ARGSV,BGETV,BPUTV,GBPBV,FINDV,FSCV ****************** +********** to F27D, F18E, F4C9, F529, FFA6, F3CA, F1B1 ****************** + +F159 LDX #&0E ;RESET VECTORS FOR FILE RELATED OPERATIONS +F15B LDA &D951,X ; +F15E STA &0211,X ; +F161 DEX ; +F162 BNE &F15B ; + +F164 STX &C2 ;&C2=0 PROGRESS FLAG +F166 LDX #&0F ;set X to make Rom service call &F claim vectors! + + +************************************************************************* +* * +* OSBYTE 143 * +* Pass service commands to sideways ROMs * +* * +************************************************************************* + ; On entry X=service call number + ; Y=any additional parameter + ; On entry X=0 if claimed, or preserved if unclaimed + ; Y=any returned parameter + ; When called internally, EQ set if call claimed + +F168 LDA &F4 ; Get current ROM number +F16A PHA ; Save it +F16B TXA ; Pass service call number to A +F16C LDX #&0F ; Start at ROM 15 + + ; Issue service call loop +F16E INC &02A1,X ; Read bit 7 on ROM type table (no ROM has type 254 &FE) +F171 DEC &02A1,X ; +F174 BPL &F183 ; If not set (+ve result), step to next ROM down +F176 STX &F4 ; Otherwise, select this ROM, &F4 RAM copy +F178 STX &FE30 ; Page in selected ROM +F17B JSR &8003 ; Call the ROM's service entry + ; X and P do not need to be preserved by the ROM +F17E TAX ; On exit pass A to X to chech if claimed +F17F BEQ &F186 ; If 0, service call claimed, reselect ROM and exit +F181 LDX &F4 ; Otherwise, get current ROM back +F183 DEX ; Step to next ROM down +F184 BPL &F16E ; Loop until done ROM 0 + +F186 PLA ; Get back original ROM number +F187 STA &F4 ; Set ROM number RAM copy +F189 STA &FE30 ; Page in the original ROM +F18C TXA ; Pass X back to A to set zero flag +F18D RTS ; And return + + +************************************************************************* +* * +* CFS OSARGS entry point * +* +************************************************************************* + +F18E ORA #&00 ;is A=00 +F190 BNE &F1A2 ;if not return +F192 CPY #&00 ;is Y=0 +F194 BNE &F1A2 ;if not return +F196 LDA &C6 ;else get current baud rate and zero bit 2 +F198 AND #&FB ;C6=5 becomes 1, 6 becomes 2 +F19A ORA &0247 ;if cassette selected A=0 else A=2 +F19D ASL ;multiply by 2 +F19E ORA &0247 ;Or it again +F1A1 LSR ;divide by 2 +F1A2 RTS ;return cassette =0 + +************************************************************************* +* * +* FSC VECTOR TABLE * +* * +************************************************************************* + +F1A3 DB 4C,F5 ; *OPT (F54C) +F1A5 DB 1D,F6 ; check EOF (F61D) +F1A7 DB 04,F3 ; */ (F304) +F1A9 DB 0F,E3 ; unknown command (E30F) +F1AB DB 04,F3 ; *RUN (F304) +F1AD DB 2A,F3 ; *CAT (F32A) +F1AF DB 74,E2 ; osbyte 77 (E274) + + +************************************************************************* +* Filing System control entry OSFSC * +* Entry via 021E FSCV * +* A= index 0 to 7 * +************************************************************************* + ;on entry A is reason code + ;A=0 A *OPT command has been used X & Y are the 2 parameters + ;A=1 EOF is being checked, on entry X=File handle + on Exit X=FF = EOF exists else 00 + ;A=2 A */ command has been used *RUN the file + ;A=3 An unrecognised OS command has ben used X,Y point at command + ;A=4 A *RUN command has been used X,Y point at filename + ;A=5 A *CAT cammand has been issued X,Y point to rest of command + ;A=6 New filing system about to take over, close SPOOL & EXEC files + ;A=7 Return in X and Y lowest and highest file handle used + ;A=8 OS about to process *command + +F1B1 CMP #&07 ;if A>6 +F1B3 BCS &F1A2 ;goto F1A2 (RTS) +F1B5 STX &BC ;else save X +F1B7 ASL ;A=A*2 +F1B8 TAX ;X=A to get offset +F1B9 LDA &F1A4,X ;get hi byte of address +F1BC PHA ;push it +F1BD LDA &F1A3,X ;get lo byte of address +F1C0 PHA ;push it +F1C1 LDX &BC ;get back X +F1C3 RTS ;this now jumps to the address got from the table +1 + ;the next RTS takes us back to CLI + + +************************************************************************* +* * +* LOAD FILE * +* * +************************************************************************* + +F1C4 PHP ;save flags on stack +F1C5 PHA ;save A on stack +F1C6 JSR &FB27 ;Set cassette optionsinto (BB),set C7=6 + ;claim serial system for cassette +F1C9 LDA &03C2 ;execution address LO +F1CC PHA ;save A on stack +F1CD JSR &F631 ;search for file +F1D0 PLA ;get back A +F1D1 BEQ &F1ED ;if A=0 F1ED +F1D3 LDX #&03 ;else X=3 +F1D5 LDA #&FF ;A=&FF +F1D7 PHA ;save A on stack +F1D8 LDA &03BE,X ;get load address +F1DB STA &B0,X ;store it as current load address +F1DD PLA ;get back A +F1DE AND &B0,X ; +F1E0 DEX ;X=X-1 +F1E1 BPL &F1D7 ;until all 4 bytes copied + +F1E3 CMP #&FF ;if all bytes contain don't contain &FF +F1E5 BNE &F1ED ;continue +F1E7 JSR &FAE8 ;else sound bell, reset ACIA & motor off +F1EA JMP &E267 ;'Bad Address' error + +F1ED LDA &03CA ;block flag +F1F0 LSR ;set carry from bit 0 +F1F1 PLA ;get back A +F1F2 BEQ &F202 ;if A=0 F202 +F1F4 BCC &F209 ;if carry clear F209 + +*************** LOCKED FILE ROUTINE ************************************* + +F1F6 JSR &FAF2 ;enable second processor and reset serial system + +F1F9 BRK ; +F1FA DB &E5 ;error number +F1FC 'Locked' ; +F201 BRK ; + +F202 BCC &F209 ;if carry clear F209 +F204 LDA #&03 ;else A=3 +F206 STA &0258 ;store to cause ESCAPE disable and memory + ;clear on break + +F209 LDA #&30 ; +F20B AND &BB ;current OPTions +F20D BEQ &F213 ;if options and #&30 =0 ignore error condition is set +F20F LDA &C1 ;else get checksum result +F211 BNE &F21D ;and if not 0 F21D + +F213 TYA ;A=Y +F214 PHA ;save A on stack +F215 JSR &FBBB ;read from second processor if present +F218 PLA ;get back A +F219 TAY ;Y=A +F21A JSR &F7D5 ;reset flags and check block length +F21D JSR &F9B4 ;load file from tape +F220 BNE &F255 ;if not found return to search +F222 JSR &FB69 ;increment current block number +F225 BIT &03CA ;block flag +F228 BMI &F232 ;if bit 7=1 then this is last block so F232 +F22A JSR &F96A ;else increment current load address +F22D JSR &F77B ;read block header +F230 BNE &F209 ;and goto F209 + +******** store data in OSFILE parameter block *************************** + +F232 LDY #&0A ;Y=&0A +F234 LDA &CC ;file length counter lo +F236 STA (&C8),Y ;OSFILE parameter block +F238 INY ;Y=Y+1 +F239 LDA &CD ;file length counter hi +F23B STA (&C8),Y ;OSFILE parameter block +F23D LDA #&00 ;A=0 +F23F INY ;Y=Y+1 +F240 STA (&C8),Y ;OSFILE parameter block +F242 INY ;Y=Y+1 +F243 STA (&C8),Y ;OSFILE parameter block +F245 PLP ;get back flags +F246 JSR &FAE8 ;bell, reset ACIA & motor +F249 BIT &BA ;current block flag +F24B BMI &F254 ;return +F24D PHP ;save flags on stack +F24E JSR &FA46 ; print message following call (in this case NEWLINE!) +F251 DB &0D,&00 ;message +F254 RTS ;return + ; +************RETRY AFTER A FAILURE ROUTINE ******************************* + +F255 JSR &F637 ;search for a specified block +F258 BNE &F209 ;goto F209 + +*********** Read Filename using Command Line Interpreter **************** + +;filename pointed to by X and Y + +F25A STX &F2 ;OS filename/command line pointer lo +F25C STY &F3 ;OS filename/command line pointer +F25E LDY #&00 ;Y=0 +F260 JSR &EA1D ;initialise string +F263 LDX #&00 ;X=0 +F265 JSR &EA2F ;GSREAD call +F268 BCS &F277 ;if end of character string F277 +F26A BEQ &F274 ;if 0 found F274 +F26C STA &03D2,X ;else store character in CFS filename area +F26F INX ;X=X+1 +F270 CPX #&0B ;if X<>11 +F272 BNE &F265 ;then read next +F274 JMP &EA8F ;else Bad String error + +************* terminate Filename **************************************** + +F277 LDA #&00 ;terminate filename with 0 +F279 STA &03D2,X ; +F27C RTS ;return + + +************************************************************************* +* * +* OSFILE ENTRY * +* * +* on entry A determines action * +* A=0 save block of memory as a file * +* A=1 write catalogue info for existing file * +* A=2 write load address only for existing file * +* A=3 write execution address only for existing file * +* A=4 write attributes only for existing file * +* A=5 Read catalogue info, return file type in A * +* A=6 Delete named file * +* A=&FF load the named file if lo byte of Exec address=0 use * +* address in parameter block else files own load address * +* X,Y point to parameter block * +* bytes 0,1 filename address, 2-5 load,6-9 exec,A-D length or * +* start of data for save, 0E End address /attributes * +************************************************************************* + +;parameter block located by XY +;0/1 Address of Filename terminated by &0D +;2/4 Load Address of File +;6/9 Execution Address of File +;A/D Start address of data for write operations or length of file +; for read operations +;E/11 End address of Data; i.e. byte AFTER last byte to be written +; or file attributes +; +;On Entry action is determined by value in A +; +;A=0 Save section of memory as named file, write catalogue information +;A=1 Write catalogue information for named file +;A=2 Write the LOAD address (only) for the named File +;A=3 Write the EXECUTION address (only) for the named File +;A=4 Write the ATTRIBUTES for the named File +;A=5 Read the named files catalogue information Place file type in A +;A=6 Delete the named file +;A=&FF Load the named file and read its catalogue information + +F27D PHA ;save A on stack +F27E STX &C8 ;osfile block pointer lo +F280 STY &C9 ;osfile block pointer hi +F282 LDY #&00 ;Y=0 +F284 LDA (&C8),Y ;OSFILE parameter block +F286 TAX ;X=A +F287 INY ;Y=Y+1 +F288 LDA (&C8),Y ;OSFILE parameter block +F28A TAY ;Y=A +F28B JSR &F25A ;get filename from BUFFER +F28E LDY #&02 ;Y=2 + +F290 LDA (&C8),Y ;copy parameters to Cassette block at 3BE/C5 +F292 STA &03BC,Y ;from LOAD and EXEC address +F295 STA &00AE,Y ;make second copy at B0-B8 +F298 INY ;Y=Y+1 +F299 CPY #&0A ;until Y=10 +F29B BNE &F290 ; + +F29D PLA ;get back A +F29E BEQ &F2A7 ;if A=0 F2A7 +F2A0 CMP #&FF ;else if A<>&FF +F2A2 BNE &F254 ;RETURN as cassette has no other options +F2A4 JMP &F1C4 ;load file + +************** Save a file ********************************************** + +F2A7 STA &03C6 ;zero block number +F2AA STA &03C7 ;zero block number hi + +F2AD LDA (&C8),Y ;OSFILE parameter block +F2AF STA &00A6,Y ;store to Zero page copy (&B0 to &B7) +F2B2 INY ;data start and data end address +F2B3 CPY #&12 ;until Y=18 +F2B5 BNE &F2AD ; +F2B7 TXA ;A=X +F2B8 BEQ &F274 ;if X=0 no filename found so B274 else BAD STRING error + +F2BA JSR &FB27 ;Set cassette option sinto (BB),set C7=6 + ;claim serial system for cassette +F2BD JSR &F934 ;prompt to start recording + +F2C0 LDA #&00 ;A=0 +F2C2 JSR &FBBD ;enable 2nd proc. if present and set up osfile block +F2C5 JSR &FBE2 ;set up CFS for write operation +F2C8 SEC ;set carry flag +F2C9 LDX #&FD ;X=&FD + +F2CB LDA &FFB7,X ;set 03C8/A block length and block flag +F2CE SBC &FFB3,X ;to B4/6-B0/2 the number of pages (blocks) to be + ;saved +F2D1 STA &02CB,X ; +F2D4 INX ;X=X+1 +F2D5 BNE &F2CB ; + +F2D7 TAY ;Y=A +F2D8 BNE &F2E8 ;if last byte is non zero F2E8 else +F2DA CPX &03C8 ;compare X with block length +F2DD LDA #&01 ;A=1 +F2DF SBC &03C9 ;subtract block length hi +F2E2 BCC &F2E8 ;if carry clear F2E8 + +F2E4 LDX #&80 ;X=&80 +F2E6 BNE &F2F0 ;jump F2F0 + +F2E8 LDA #&01 ;A=1 +F2EA STA &03C9 ;block length hi +F2ED STX &03C8 ;block length +F2F0 STX &03CA ;block flag +F2F3 JSR &F7EC ;write block to Tape +F2F6 BMI &F341 ;return if negative +F2F8 JSR &F96A ;increment current load address +F2FB INC &03C6 ;block number +F2FE BNE &F2C8 ;if not 0 loop back again else +F300 INC &03C7 ;block number hi +F303 BNE &F2C8 ;and loop back again + + +************************************************************************* +* * +* *RUN ENTRY * +* * +************************************************************************* + +F305 JSR &F25A ;get filename from BUFFER +F308 LDX #&FF ;X=&FF +F30A STX &03C2 ;execution address +F30D JSR &F1C4 ;load file +F310 BIT &027A ;&FF if tube present +F313 BPL &F31F ;so if not present F31F else +F315 LDA &03C4 ;execution address extend +F318 AND &03C5 ;execution address extend +F31B CMP #&FF ;if they are NOT both &FF i.e.for base processor +F31D BNE &F322 ;F322 else +F31F JMP (&03C2) ; RUN file + +F322 LDX #&C2 ;point to execution address +F324 LDY #&03 ;(&03C2) +F326 LDA #&04 ;Tube call 4 +F328 JMP &FBC7 ;and issue to Tube to run file + + +************************************************************************* +* * +* *CAT ENTRY * +* * +************************************************************************* + + ;CASSETTE OPTIONS in &E2 + + ;bit 0 input file open + ;bit 1 output file open + ;bit 2,4,5 not used + ;bit 3 current CATalogue status + ;bit 6 EOF reached + ;bit 7 EOF warning given + +F32B LDA #&08 ;A=8 +F32D JSR &F344 ;set status bits from A +F330 JSR &FB27 ;Set cassette options into (BB),set C7=6 + ;claim serial system for cassette +F333 LDA #&00 ;A=0 +F335 JSR &F348 ;read data from CFS/RFS +F338 JSR &FAFC ;perform read +F33B LDA #&F7 ;A=&F7 +F33D AND &E2 ;clear bit 3 of CFS status bit +F33F STA &E2 ; +F341 RTS ;return + +F342 LDA #&40 ;set bit 6 of E2 cassette options +F344 ORA &E2 ; +F346 BNE &F33F ;and Jump F33F + +********** search routine *********************************************** + +F348 PHA ;save A on stack +F349 LDA &0247 ;filing system flag 0=CFS 2=RFS +F34C BEQ &F359 ;if CFS F359 else +F34E JSR &EE13 ;set current Filing System ROM/PHROM +F351 JSR &EE18 ;get byte from data Romcheck type +F354 BCC &F359 ;if carry clear F359 else +F356 CLV ;clear overflow flag +F357 BVC &F39A ;JUMP F39A + +*********** cassette routine******************************************** + +F359 JSR &F77B ;read block header +F35C LDA &03C6 ;block number +F35F STA &B4 ;current block no. lo +F361 LDA &03C7 ;block number hi +F364 STA &B5 ;current block no. hi +F366 LDX #&FF ;X=&FF +F368 STX &03DF ;copy of last read block flag +F36B INX ;X=X+1 +F36C STX &BA ;current block flag +F36E BEQ &F376 ;if 0 F376 + +F370 JSR &FB69 ;inc. current block no. +F373 JSR &F77B ;read block header +F376 LDA &0247 ;get filing system flag 0=CFS 2=RFS +F379 BEQ &F37D ;if CFS F37D +F37B BVC &F39A ;if V clear F39A +F37D PLA ;get back A +F37E PHA ;save A on stack +F37F BEQ &F3AE ;if A=0 F3AE +F381 JSR &FA72 ;else check filename header block matches searched Fn +F384 BNE &F39C ;if so F39C +F386 LDA #&30 ;else A=30 to clear all but bits 4/5 of current OPTions + +F388 AND &BB ;current OPTions +F38A BEQ &F39A ;if 0 F39A else + +F38C LDA &03C6 ;block number +F38F CMP &B6 ;next block no. lo +F391 BNE &F39C ; +F393 LDA &03C7 ;block number hi +F396 CMP &B7 ;next block no. hi +F398 BNE &F39C ; +F39A PLA ;get back A +F39B RTS ;return + ; +F39C LDA &0247 ;filing system flag 0=CFS 2=RFS +F39F BEQ &F3AE ;if tape F3AE +F3A1 JSR &EEAD ;else set ROM displacement address + +F3A4 LDA #&FF ;A=&FF +F3A6 STA &03C6 ;block number +F3A9 STA &03C7 ;block number hi +F3AC BNE &F370 ;jump F370 + +F3AE BVC &F3B5 ;if carry clear F3B5 +F3B0 LDA #&FF ;A=&FF +F3B2 JSR &F7D7 ;set flags +F3B5 LDX #&00 ;X=0 +F3B7 JSR &F9D9 ;report 'DATA?' +F3BA LDA &0247 ;filing system flag 0=CFS 2=RFS +F3BD BEQ &F3C3 ; +F3BF BIT &BB ;current OPTions +F3C1 BVC &F3A1 ;long messages not required if BIT 6 =0 +F3C3 BIT &03CA ;block flag +F3C6 BMI &F3A4 ;if -ve F3A4 +F3C8 BPL &F370 ;else loop back and do it again + +************************************************************************* +* * +* OSFIND ENTRY * +* file handling * +* * +************************************************************************* +;on entry A determines Action Y may contain file handle or +;X/Y point to filename terminated by &0D in memory +;A=0 closes file in channel Y if Y=0 closes all files +;A=&40 open a file for input (reading) X/Y points to filename +;A=&80 open a file for output (writing) X/Y points to filename +;A=&C0 open a file for input and output (random access) +;ON EXIT Y=0 if no file found else Y=channel number in use for file + + ;save A X and Y +F3CA STA &BC ;file status or temporary store +F3CC TXA ;A=X +F3CD PHA ;save X on stack +F3CE TYA ;A=Y +F3CF PHA ;save Y on stack +F3D0 LDA &BC ;file status or temporary store +F3D2 BNE &F3F2 ;if A is non zero open a file via F3F2 + +************ close a file *********************************************** + +F3D4 TYA ;A=Y +F3D5 BNE &F3E3 ;if A<> 0 close specified file else close them all +F3D7 JSR &E275 ;close spool/exec files via OSBYTE 77 +F3DA JSR &F478 ;tidy up +F3DD LSR &E2 ;CFS status byte is shifted left and right to zero +F3DF ASL &E2 ;bit 0 +F3E1 BCC &F3EF ;and if carry clear no input file was open so F3EF + +F3E3 LSR ;A contains file handle so shift bit 0 into carry +F3E4 BCS &F3DD ;if carry set close input file +F3E6 LSR ;else shift bit 1 into carry +F3E7 BCS &F3EC ;if carry set close output file +F3E9 JMP &FBB1 ;else report 'Channel Error' as CFS can only support + ;1 input and 1 output file + +F3EC JSR &F478 ;tidy up +F3EF JMP &F471 ;and exit + +************ OPEN A FILE ************************************************ + +F3F2 JSR &F25A ;get filename from BUFFER +F3F5 BIT &BC ;file status or temporary store +F3F7 BVC &F436 ;check A at input if bit 6 not set its an output file + +********* Input files +************************************************** + +F3F9 LDA #&00 ;else its an input file +F3FB STA &039E ;BGET buffer offset for next byte +F3FE STA &03DD ;Expected BGET file block number lo +F401 STA &03DE ;expected BGET file block number hi +F404 LDA #&3E ;A=&3E +F406 JSR &F33D ;CFS status =CFS status AND A +F409 JSR &FB1A ;claim serial system and set OPTions +F40C PHP ;save flags on stack +F40D JSR &F631 ;search for file +F410 JSR &F6B4 ;check protection bit of block status and respond +F413 PLP ;get back flags +F414 LDX #&FF ;X=&FF increment to 0 on next instruction + +F416 INX ;X=X+1 +F417 LDA &03B2,X ;get file name and +F41A STA &03A7,X ;store as BGET filename +F41D BNE &F416 ;until end of filename + +F41F LDA #&01 ;A=1 to show file open +F421 JSR &F344 ;set status bits from A +F424 LDA &02EA ;CFS currently resident file block length lo +F427 ORA &02EB ;CFS currently resident file block length hi +F42A BNE &F42F ;if block length is 0 +F42C JSR &F342 ;set CFS status bit 3 (EOF reached) + ;else +F42F LDA #&01 ;A=1 +F431 ORA &0247 ;filing system flag 0=CFS 2=RFS +F434 BNE &F46F ;and exit after restoring registers + +******************* open an output file*********************************** + +F436 TXA ;A=X + +F437 BNE &F43C ;if X=0 then zero length filename so +F439 JMP &EA8F ;Bad String error + +F43C LDX #&FF ;X=&FF +F43E INX ;X=X+1 + ;copy sought filename to header block +F43F LDA &03D2,X ;sought filename +F442 STA &0380,X ;BPUT file header block +F445 BNE &F43E ;until A=0 end of filename +F447 LDA #&FF ;A=&FF +F449 LDX #&08 ;X=8 + +F44B STA &038B,X ;set 38C/93 to &FF +F44E DEX ;X=X-1 +F44F BNE &F44B ; + +F451 TXA ;A=X=0 +F452 LDX #&14 ;X=14 +F454 STA &0380,X ;BPUT file header block +F457 INX ;X=X+1 +F458 CPX #&1E ;this zeros 394/D +F45A BNE &F454 ; + +F45C ROL &0397 ; +F45F JSR &FB27 ;Set cassette optionsinto (BB),set C7=6 + ;claim serial system for cassette +F462 JSR &F934 ;prompt to start recording +F465 JSR &FAF2 ;enable second processor and reset serial system +F468 LDA #&02 ;A=2 +F46A JSR &F344 ;set status bits from A +F46D LDA #&02 ;A=2 +F46F STA &BC ;file status or temporary store +F471 PLA ;get back A +F472 TAY ;Y=A +F473 PLA ;get back A +F474 TAX ;X=A +F475 LDA &BC ;file status or temporary store +F477 RTS ;return + ; + +F478 LDA #&02 ;A=2 clearing all but bit 1 of status byte +F47A AND &E2 ;CFS status byte, with output file open +F47C BEQ &F477 ;if file not open then exit +F47E LDA #&00 ;else A=0 +F480 STA &0397 ;setting block length to current value of BPUT offset +F483 LDA #&80 ;A=&80 +F485 LDX &039D ;get BPUT buffer ofset +F488 STX &0396 ;setting block length to current value of BPUT offset +F48B STA &0398 ;mark current block as last +F48E JSR &F496 ;save block to tape +F491 LDA #&FD ;A=&FD +F493 JMP &F33D ;CFS status =CFS status AND A + +*********** SAVE BLOCK TO TAPE ******************************************** + +F496 JSR &FB1A ;claim serial system and set OPTions + +F499 LDX #&11 ;X=11 +F49B LDA &038C,X ;copy header block from 38C-39D +F49E STA &03BE,X ;to 3BE/DF +F4A1 DEX ;X=X-1 +F4A2 BPL &F49B ; + ;X=&FF +F4A4 STX &B2 ;current load address high word +F4A6 STX &B3 ;current load address high word +F4A8 INX ;X=X+1, (X=0) +F4A9 STX &B0 ;current load address lo byte set to &00 +F4AB LDA #&09 ;A=9 to set current load address at &900 +F4AD STA &B1 ;current load address +F4AF LDX #&7F ;X=&7F +F4B1 JSR &FB81 ;copy from 301/C+X to 3D2/C sought filename +F4B4 STA &03DF ;copy of last read block flag +F4B7 JSR &FB8E ;switch Motor On +F4BA JSR &FBE2 ;set up CFS for write operation +F4BD JSR &F7EC ;write block to Tape +F4C0 INC &0394 ;block number lo +F4C3 BNE &F4C8 ; +F4C5 INC &0395 ;block number hi +F4C8 RTS ;return + + +************************************************************************* +* * +* * +* OSBGET get a byte from a file * +* * +* * +************************************************************************* + ;on ENTRY Y contains channel number + ;on EXIT X and Y are preserved C=0 indicates valid character + ; A contains character (or error) A=&FE End Of File + + ;push X and Y +F4C9 TXA ;A=X +F4CA PHA ;save A on stack +F4CB TYA ;A=Y +F4CC PHA ;save A on stack +F4CD LDA #&01 ;A=1 +F4CF JSR &FB9C ;check conditions for OSBGET are OK +F4D2 LDA &E2 ;CFS status byte +F4D4 ASL ;shift bit 7 into carry (EOF warning given) +F4D5 BCS &F523 ;if carry set F523 +F4D7 ASL ;shift bit 6 into carry +F4D8 BCC &F4E3 ;if clear EOF not reached F4E3 +F4DA LDA #&80 ;else A=&80 setting bit 7 of status byte EOF warning +F4DC JSR &F344 ;set status bits from A +F4DF LDA #&FE ;A=&FE +F4E1 BCS &F51B ;if carry set F51B + +F4E3 LDX &039E ;BGET buffer offset for next byte +F4E6 INX ;X=X+1 +F4E7 CPX &02EA ;CFS currently resident file block length lo +F4EA BNE &F516 ;read a byte + ;else +F4EC BIT &02EC ;block flag of currently resident block +F4EF BMI &F513 ;if bit 7=1 this is the last block so F513 else +F4F1 LDA &02ED ;last character of currently resident block +F4F4 PHA ;save A on stack +F4F5 JSR &FB1A ;claim serial system and set OPTions +F4F8 PHP ;save flags on stack +F4F9 JSR &F6AC ;read in a new block +F4FC PLP ;get back flags +F4FD PLA ;get back A +F4FE STA &BC ;file status or temporary store +F500 CLC ;clear carry flag +F501 BIT &02EC ;block flag of currently resident block +F504 BPL &F51D ;if not last block (bit 7=0) +F506 LDA &02EA ;CFS currently resident file block length lo +F509 ORA &02EB ;CFS currently resident file block length hi +F50C BNE &F51D ;if block size not 0 F51D else +F50E JSR &F342 ;set CFS status bit 6 (EOF reached) +F511 BNE &F51D ;goto F51D + +F513 JSR &F342 ;set CFS status bit 6 (EOF reached) +F516 DEX ;X=X-1 +F517 CLC ;clear carry flag +F518 LDA &0A00,X ;read byte from cassette buffer + +F51B STA &BC ;file status or temporary store +F51D INC &039E ;BGET buffer offset for next byte +F520 JMP &F471 ;exit via F471 + +F523 BRK ; +F524 DB &DF ;error number +F525 DB 'EOF' ; +F528 BRK ; + + +************************************************************************* +* * +* * +* OSBPUT WRITE A BYTE TO FILE * +* * +* * +************************************************************************* +;ON ENTRY Y contains channel number A contains byte to be written + +F529 STA &C4 ;store A in temorary store +F52B TXA ;and stack X and Y +F52C PHA ;save on stack +F52D TYA ;A=Y +F52E PHA ;save on stack + +F52F LDA #&02 ;A=2 +F531 JSR &FB9C ;check conditions necessary for OSBPUT are OK +F534 LDX &039D ;BPUT buffer offset for next byte +F537 LDA &C4 ;get back original value of A +F539 STA &0900,X ;Cassette buffer +F53C INX ;X=X+1 +F53D BNE &F545 ;if not 0 F545, otherwise buffer is full so +F53F JSR &F496 ;save block to tape +F542 JSR &FAF2 ;enable second processor and reset serial system +F545 INC &039D ;BPUT buffer offset for next byte +F548 LDA &C4 ;get back A +F54A JMP &F46F ;and exit + + +************************************************************************* +* * +* * +* OSBYTE 139 Select file options * +* * +* * +************************************************************************* +;ON ENTRY Y contains option value X contains option No. see *OPT X,Y +;this applies largely to CFS LOAD SAVE CAT and RUN +;X=1 is message switch +; Y=0 no messages +; Y=1 short messages +; Y=2 gives detailed information on load and execution addresses + +;X=2 is error handling +; Y=0 ignore errors +; Y=1 prompt for a retry +; Y=2 abort operation + +;X=3 is interblock gap for BPUT# and PRINT# +; Y=0-127 set gap in 1/10ths Second +; Y > 127 use default values + +F54D TXA ;A=X +F54E BEQ &F57E ;if A=0 F57E +F550 CPX #&03 ;if X=3 +F552 BEQ &F573 ;F573 to set interblock gap +F554 CPY #&03 ;else if Y>2 then BAD COMMAND error +F556 BCS &F55E ; +F558 DEX ;X=X-1 +F559 BEQ &F561 ;i.e. if X=1 F561 message control +F55B DEX ;X=X-1 +F55C BEQ &F568 ;i.e. if X=2 F568 error response +F55E JMP &E310 ;else E310 to issue Bad Command error + +*********** message control ********************************************* + +F561 LDA #&33 ;to set lower two bits of each nybble as mask +F563 INY ;Y=Y+1 +F564 INY ;Y=Y+1 +F565 INY ;Y=Y+1 +F566 BNE &F56A ;goto F56A + +*********** error response ********************************************* + +F568 LDA #&CC ;setting top two bits of each nybble as mask +F56A INY ;Y=Y+1 +F56B AND &E3 ;clear lower two bits of each nybble +F56D ORA &F581,Y ;or with table value +F570 STA &E3 ;store it in &E3 +F572 RTS ;return + + ;setting of &E3 + ; + ;lower nybble sets LOAD options + ;upper sets SAVE options + + ;0000 Ignore errors, no messages + ;0001 Abort if error, no messages + ;0010 Retry after error, no messages + ;1000 Ignore error short messages + ;1001 Abort if error short messages + ;1010 Retry after error short messages + ;1100 Ignore error long messages + ;1101 Abort if error long messages + ;1110 Retry after error long messages + +***********set interblock gap ******************************************* + +F573 TYA ;A=Y +F574 BMI &F578 ;if Y>127 use default values +F576 BNE &F57A ;if Y<>0 skip next instruction +F578 LDA #&19 ;else A=&19 + +F57A STA &03D1 ;sequential block gap +F57D RTS ;return + ; +F57E TAY ;Y=A +F57F BEQ &F56D ;jump to F56D + +*********** DEFAULT OPT VALUES TABLE ************************************ + +F581 DB &A1 ;%1010 0001 +F582 DB &00 ;%0000 0000 +F583 DB &22 ;%0010 0010 +F584 DB &11 ;%0001 0001 +F585 DB &00 ;%0000 0000 +F586 DB &88 ;%1000 1000 +F587 DB &CC ;%1100 1100 + +F588 DEC &C0 ;filing system buffer flag +F58A LDA &0247 ;filing system flag 0=CFS 2=RFS +F58D BEQ &F596 ;if CFS F596 + +F58F JSR &EE51 ;read RFS data rom or Phrom +F592 TAY ;Y=A +F593 CLC ;clear carry flag +F594 BCC &F5B0 ;jump to F5B0 + +F596 LDA &FE08 ;ACIA status register +F599 PHA ;save A on stack +F59A AND #&02 ;clear all but bits 0,1 A=(0-3) +F59C BEQ &F5A9 ;if 0 F5A9 transmit data register full or RDR empty +F59E LDY &CA ; +F5A0 BEQ &F5A9 ; +F5A2 PLA ;get back A +F5A3 LDA &BD ;character temporary storage +F5A5 STA &FE09 ;ACIA transmit data register +F5A8 RTS ;return + ; +F5A9 LDY &FE09 ;read ACIA recieve data register +F5AC PLA ;get back A +F5AD LSR ;bit 2 to carry (data carrier detect) +F5AE LSR ; +F5AF LSR ; + +F5B0 LDX &C2 ;progress flag +F5B2 BEQ &F61D ;if &C2=0 exit +F5B4 DEX ;X=X-1 +F5B5 BNE &F5BD ;if &C2>1 then F5BD +F5B7 BCC &F61D ;else if carrier tone from cassette detected exit + +F5B9 LDY #&02 ;Y=2 + +F5BB BNE &F61B ; +F5BD DEX ;X=X-1 +F5BE BNE &F5D3 ;if &C2>2 +F5C0 BCS &F61D ;if carrier tone from cassette not detected exit +F5C2 TYA ;A=Y +F5C3 JSR &FB78 ;set (BE/C0) to 0 +F5C6 LDY #&03 ;Y=3 +F5C8 CMP #&2A ;is A= to synchronising byte &2A? +F5CA BEQ &F61B ;if so F61B +F5CC JSR &FB50 ;control cassette system +F5CF LDY #&01 ;Y=1 +F5D1 BNE &F61B ;goto F61B +F5D3 DEX ;X=X-1 +F5D4 BNE &F5E2 ;if &C2>3 +F5D6 BCS &F5DC ; +F5D8 STY &BD ;get character read into Y +F5DA BEQ &F61D ;if 0 exit via F61D +F5DC LDA #&80 ;else A=&80 +F5DE STA &C0 ;filing system buffer flag +F5E0 BNE &F61D ;and exit + +F5E2 DEX ;X=X-1 +F5E3 BNE &F60E ;if &C2>4 F60E +F5E5 BCS &F616 ;if carry set F616 +F5E7 TYA ;A=Y +F5E8 JSR &F7B0 ;perform CRC +F5EB LDY &BC ;file status or temporary store +F5ED INC &BC ;file status or temporary store +F5EF BIT &BD ;if bit 7 set this is the last byte read +F5F1 BMI &F600 ;so F600 +F5F3 JSR &FBD3 ;check if second processor file test tube prescence +F5F6 BEQ &F5FD ;if return with A=0 F5FD +F5F8 STX &FEE5 ;Tube FIFO3 +F5FB BNE &F600 ; + +F5FD TXA ;A=X restore value +F5FE STA (&B0),Y ;store to current load address +F600 INY ;Y=Y+1 +F601 CPY &03C8 ;block length +F604 BNE &F61D ;exit +F606 LDA #&01 ;A=1 +F608 STA &BC ;file status or temporary store +F60A LDY #&05 ;Y=5 +F60C BNE &F61B ;exit + +F60E TYA ;A=Y +F60F JSR &F7B0 ;perform CRC +F612 DEC &BC ;file status or temporary store +F614 BPL &F61D ;exit + +F616 JSR &FB46 ;reset ACIA +F619 LDY #&00 ;Y=0 +F61B STY &C2 ;progress flag +F61D RTS ;return + + +************************************************************************* +* * +* FSCV &01 - check for end of file * +* * +************************************************************************* + ; +F61E PHA ;save A on stack +F61F TYA ;A=Y +F620 PHA ;save Y on stack +F621 TXA ;A=X to put X into Y +F622 TAY ;Y=A +F623 LDA #&03 ;A=3 +F625 JSR &FB9C ;confirm file is open +F628 LDA &E2 ;CFS status byte +F62A AND #&40 ; +F62C TAX ;X=A +F62D PLA ;get back A +F62E TAY ;Y=A +F62F PLA ;get back A +F630 RTS ;return + ; +F631 LDA #&00 ;A=0 +F633 STA &B4 ;current block no. lo +F635 STA &B5 ;current block no. hi +F637 LDA &B4 ;current block no. lo +F639 PHA ;save A on stack +F63A STA &B6 ;next block no. lo +F63C LDA &B5 ;current block no. hi +F63E PHA ;save A on stack +F63F STA &B7 ;next block no. hi +F641 JSR &FA46 ;print message following call + +F644 DB 'Searching'; +F64C DB &0D ;newline +F64E BRK ; + +F64F LDA #&FF ;A=&FF +F651 JSR &F348 ;read data from CFS/RFS +F654 PLA ;get back A +F655 STA &B5 ;current block no. hi +F657 PLA ;get back A +F658 STA &B4 ;current block no. lo +F65A LDA &B6 ;next block no. lo +F65C ORA &B7 ;next block no. hi +F65E BNE &F66D ; +F660 STA &B4 ;current block no. lo +F662 STA &B5 ;current block no. hi +F664 LDA &C1 ;checksum result +F666 BNE &F66D ; +F668 LDX #&B1 ;current load address +F66A JSR &FB81 ;copy from 301/C+X to 3D2/C sought filename +F66D LDA &0247 ;filing system flag 0=CFS 2=RFS +F670 BEQ &F685 ;if cassette F685 +F672 BVS &F685 ; + +F674 BRK ; +F675 DB &D6 ;Error number +F676 DB 'File Not found' +F684 BRK ; + +F685 LDY #&FF ;Y=&FF +F687 STY &03DF ;copy of last read block flag +F68A RTS ;return + +******** CLOSE EXEC FILE ********************************************** + +F68B LDA #&00 ;A=0 + +************************************************************************* +* * +* *EXEC * +* * +************************************************************************* + +F68D PHP ;save flags on stack +F68E STY &E6 ;&E6=Y +F690 LDY &0256 ;EXEC file handle +F693 STA &0256 ;EXEC file handle +F696 BEQ &F69B ;if not 0 close file via OSFIND +F698 JSR OSFIND ; +F69B LDY &E6 ;else Y= original Y +F69D PLP ;get back flags +F69E BEQ &F6AB ;if A=0 on entry exit else +F6A0 LDA #&40 ;A=&40 +F6A2 JSR OSFIND ;to open an input file +F6A5 TAY ;Y=A +F6A6 BEQ &F674 ;If Y=0 'File not found' else store +F6A8 STA &0256 ;EXEC file handle +F6AB RTS ;return + +******* read a block ************************************************* + +F6AC LDX #&A6 ;X=&A6 +F6AE JSR &FB81 ;copy from 301/C+X to 3D2/C sought filename +F6B1 JSR &F77B ;read block header +F6B4 LDA &03CA ;block flag +F6B7 LSR ;A=A/2 bit 0 into carry to check for locked file +F6B8 BCC &F6BD ;if not set then skip next instruction +F6BA JMP &F1F6 ;'locked' file routine + +F6BD LDA &03DD ;Expected BGET file block number lo +F6C0 STA &B4 ; current block no. lo +F6C2 LDA &03DE ;expected BGET file block number hi +F6C5 STA &B5 ;current block no. hi +F6C7 LDA #&00 ;A=0 +F6C9 STA &B0 ;current load address +F6CB LDA #&0A ;A=&A setting current load address to the CFS/RFS +F6CD STA &B1 ;current load address buffer at &A00 +F6CF LDA #&FF ;A=&FF to set other 2 bytes +F6D1 STA &B2 ;current load address high word +F6D3 STA &B3 ;current load address high word +F6D5 JSR &F7D5 ;reset flags +F6D8 JSR &F9B4 ;load file from tape +F6DB BNE &F702 ;if return non zero F702 else +F6DD LDA &0AFF ;get last character from input buffer +F6E0 STA &02ED ;last character currently resident block +F6E3 JSR &FB69 ;inc. current block no. +F6E6 STX &03DD ;expected BGET file block number lo +F6E9 STY &03DE ;expected BGET file block number hi +F6EC LDX #&02 ;X=2 +F6EE LDA &03C8,X ;read bytes from block flag/block length +F6F1 STA &02EA,X ;store into current values of above +F6F4 DEX ;X=X-1 +F6F5 BPL &F6EE ;until X=-1 (&FF) + +F6F7 BIT &02EC ;block flag of currently resident block +F6FA BPL &F6FF ; +F6FC JSR &F249 ;print newline if needed +F6FF JMP &FAF2 ;enable second processor and reset serial system +F702 JSR &F637 ;search for a specified block +F705 BNE &F6B4 ;if NE check for locked condition else +F707 CMP #&2A ;is it Synchronising byte &2A? +F709 BEQ &F742 ;if so F742 +F70B CMP #&23 ;else is it &23 (header substitute in ROM files) +F70D BNE &F71E ;if not BAD ROM error + +F70F INC &03C6 ;block number +F712 BNE &F717 ; +F714 INC &03C7 ;block number hi +F717 LDX #&FF ;X=&FF +F719 BIT &D9B7 ;to set V & M +F71C BNE &F773 ;and jump (ALWAYS!!) to F773 + +F71E LDA #&F7 ;clear bit 3 of RFS status (current CAT status) +F720 JSR &F33D ;RFS status =RFS status AND A + +F723 BRK ;and cause error +F724 DB &D7 ;error number +F725 DB 'Bad Rom' +F72C BRK ; + +**********: pick up a header ******************************************** + +F72D LDY &FF ;get ESCAPE flag +F72F JSR &FB90 ;switch Motor on +F732 LDA #&01 ;A=1 +F734 STA &C2 ;progress flag +F736 JSR &FB50 ;control serial system +F739 JSR &F995 ;confirm ESC not set and CFS not executing +F73C LDA #&03 ;A=3 +F73E CMP &C2 ;progress flag +F740 BNE &F739 ;back until &C2=3 + +F742 LDY #&00 ;Y=0 +F744 JSR &FB7C ;zero checksum bytes +F747 JSR &F797 ;get character from file and do CRC +F74A BVC &F766 ;if V clear on exit F766 +F74C STA &03B2,Y ;else store +F74F BEQ &F757 ;or if A=0 F757 +F751 INY ;Y=Y+1 +F752 CPY #&0B ;if Y<>&B +F754 BNE &F747 ;go back for next character +F756 DEY ;Y=Y-1 + +F757 LDX #&0C ;X=12 +F759 JSR &F797 ;get character from file and do CRC +F75C BVC &F766 ;if V clear on exit F766 +F75E STA &03B2,X ;else store byte +F761 INX ;X=X+1 +F762 CPX #&1F ;if X<>31 +F764 BNE &F759 ;goto F759 + +F766 TYA ;A=Y +F767 TAX ;X=A +F768 LDA #&00 ;A=0 +F76A STA &03B2,Y ;store it +F76D LDA &BE ;CRC workspace +F76F ORA &BF ;CRC workspace +F771 STA &C1 ;Checksum result +F773 JSR &FB78 ;set (BE/C0) to 0 +F776 STY &C2 ;progress flag +F778 TXA ;A=X +F779 BNE &F7D4 ; +F77B LDA &0247 ;filing system flag 0=CFS 2=RFS +F77E BEQ &F72D ;if cassette F72D +F780 JSR &EE51 ;read RFS data rom or Phrom +F783 CMP #&2B ;is it ROM file terminator? +F785 BNE &F707 ;if not F707 + +********* terminator found ********************************************** + +F787 LDA #&08 ;A=8 isolating bit 3 CAT status +F789 AND &E2 ;CFS status byte +F78B BEQ &F790 ;if clera skip next instruction +F78D JSR &F24D ;print CR if CFS not operational +F790 JSR &EE18 ;get byte from data Rom +F793 BCC &F780 ;if carry set F780 +F795 CLV ;clear overflow flag +F796 RTS ;return + +**************** get character from file and do CRC ******************* + ; +F797 LDA &0247 ;filing system flag 0=CFS 2=RFS +F79A BEQ &F7AD ;if cassette F7AD +F79C TXA ;A=X to save X and Y +F79D PHA ;save X on stack +F79E TYA ;A=Y +F79F PHA ;save Y on stack +F7A0 JSR &EE51 ;read RFS data rom or Phrom +F7A3 STA &BD ;put it in temporary storage +F7A5 LDA #&FF ;A=&FF +F7A7 STA &C0 ;filing system buffer flag +F7A9 PLA ;get back Y +F7AA TAY ;Y=A +F7AB PLA ;get back X +F7AC TAX ;X=A +F7AD JSR &F884 ;check for Escape and loop till bit 7 of FS buffer + ;flag=1 + +************************** perform CRC ********************************** + +F7B0 PHP ;save flags on stack +F7B1 PHA ;save A on stack +F7B2 SEC ;set carry flag +F7B3 ROR &CB ;CRC Bit counter +F7B5 EOR &BF ;CRC workspace +F7B7 STA &BF ;CRC workspace +F7B9 LDA &BF ;CRC workspace +F7BB ROL ;A=A*2 C=bit 7 +F7BC BCC &F7CA ; +F7BE ROR ;A=A/2 +F7BF EOR #&08 ; +F7C1 STA &BF ;CRC workspace +F7C3 LDA &BE ;CRC workspace +F7C5 EOR #&10 ; +F7C7 STA &BE ;CRC workspace +F7C9 SEC ;set carry flag + +F7CA ROL &BE ;CRC workspace +F7CC ROL &BF ;CRC workspace +F7CE LSR &CB ;CRC Bit counter +F7D0 BNE &F7B9 ; +F7D2 PLA ;get back A +F7D3 PLP ;get back flags +F7D4 RTS ;return + +F7D5 LDA #&00 ;A=0 +F7D7 STA &BD ;&BD=character temporary storage buffer=0 +F7D9 LDX #&00 ;X=0 +F7DB STX &BC ;file status or temporary store +F7DD BVC &F7E9 ; +F7DF LDA &03C8 ;block length +F7E2 ORA &03C9 ;block length hi +F7E5 BEQ &F7E9 ;if 0 F7E9 + +F7E7 LDX #&04 ;else X=4 +F7E9 STX &C2 ;filename length/progress flag +F7EB RTS ;return + +*************** SAVE A BLOCK ******************************************** + +F7EC PHP ;save flags on stack +F7ED LDX #&03 ;X=3 +F7EF LDA #&00 ;A=0 +F7F1 STA &03CB,X ;clear 03CB/E (RFS EOF+1?) +F7F4 DEX ;X=X-1 +F7F5 BPL &F7F1 ; + +F7F7 LDA &03C6 ;block number +F7FA ORA &03C7 ;block number hi +F7FD BNE &F804 ;if block =0 F804 else +F7FF JSR &F892 ;generate a 5 second delay +F802 BEQ &F807 ;goto F807 + + +F804 JSR &F896 ;generate delay set by interblock gap +F807 LDA #&2A ;A=&2A +F809 STA &BD ;store it in temporary file +F80B JSR &FB78 ;set (BE/C0) to 0 +F80E JSR &FB4A ;set ACIA control register +F811 JSR &F884 ;check for Escape and loop till bit 7 of FS buffer + ;flag=1 +F814 DEY ;Y=Y-1 +F815 INY ;Y=Y+1 +F816 LDA &03D2,Y ;move sought filename +F819 STA &03B2,Y ;into filename block +F81C JSR &F875 ;transfer byte to CFS and do CRC +F81F BNE &F815 ;if filename not complet then do it again + +******: deal with rest of header **************************************** + +F821 LDX #&0C ;X=12 +F823 LDA &03B2,X ;get filename byte +F826 JSR &F875 ;transfer byte to CFS and do CRC +F829 INX ;X=X+1 +F82A CPX #&1D ;until X=29 +F82C BNE &F823 ; + +F82E JSR &F87B ;save checksum to TAPE reset buffer flag +F831 LDA &03C8 ;block length +F834 ORA &03C9 ;block length hi +F837 BEQ &F855 ;if 0 F855 + +F839 LDY #&00 ;else Y=0 +F83B JSR &FB7C ;zero checksum bytes +F83E LDA (&B0),Y ;get a data byte +F840 JSR &FBD3 ;check if second processor file test tube prescence +F843 BEQ &F848 ;if not F848 else + +F845 LDX &FEE5 ;Tube FIFO3 + +F848 TXA ;A=X +F849 JSR &F875 ;transfer byte to CFS and do CRC +F84C INY ;Y=Y+1 +F84D CPY &03C8 ;block length +F850 BNE &F83E ; +F852 JSR &F87B ;save checksum to TAPE reset buffer flag +F855 JSR &F884 ;check for Escape and loop till bit 7 of FS buffer + ;flag=1 +F858 JSR &F884 ;check for Escape and loop till bit 7 of FS buffer + ;flag=1 +F85B JSR &FB46 ;reset ACIA + +F85E LDA #&01 ;A=1 +F860 JSR &F898 ;generate 0.1 * A second delay +F863 PLP ;get back flags +F864 JSR &F8B9 ;update block flag, PRINT filename (& address if reqd) +F867 BIT &03CA ;block flag +F86A BPL &F874 ;is this last block (bit 7 set)? +F86C PHP ;save flags on stack +F86D JSR &F892 ;generate a 5 second delay +F870 JSR &F246 ;sound bell and abort +F873 PLP ;get back flags +F874 RTS ;return + +****************** transfer byte to CFS and do CRC ********************** + ; +F875 JSR &F882 ;save byte to buffer, transfer to CFS & reset flag +F878 JMP &F7B0 ;perform CRC + +***************** save checksum to TAPE reset buffer flag **************** + +F87B LDA &BF ;CRC workspace +F87D JSR &F882 ;save byte to buffer, transfer to CFS & reset flag +F880 LDA &BE ;CRC workspace + +************** save byte to buffer, transfer to CFS & reset flag ******** + +F882 STA &BD ;store A in temporary buffer + +***** check for Escape and loop untill bit 7 of FS buffer flag=1 *********** + +F884 JSR &F995 ;confirm ESC not set and CFS not executing +F887 BIT &C0 ;filing system buffer flag +F889 BPL &F884 ;loop until bit 7 of &C0 is set + +F88B LDA #&00 ;A=0 +F88D STA &C0 ;filing system buffer flag +F88F LDA &BD ;get temporary store byte +F891 RTS ;return + +****************** generate a 5 second delay *************************** + +F892 LDA #&32 ;A=50 +F894 BNE &F898 ;generate delay 100ms *A (5 seconds) + +*************** generate delay set by interblock gap ******************** + +F896 LDA &C7 ;get current interblock flag + +*************** generate delay ****************************************** + +F898 LDX #&05 ;X=5 +F89A STA &0240 ;CFS timeout counter +F89D JSR &F995 ;confirm ESC not set and CFS not executing +F8A0 BIT &0240 ;CFS timeout counter (decremented each 20ms) +F8A3 BPL &F89D ;if +ve F89D +F8A5 DEX ;X=X-1 +F8A6 BNE &F89A ; +F8A8 RTS ;return + +************: generate screen reports *********************************** + +F8A9 LDA &03C6 ;block number +F8AC ORA &03C7 ;block number hi +F8AF BEQ &F8B6 ;if 0 F8B6 +F8B1 BIT &03DF ;copy of last read block flag +F8B4 BPL &F8B9 ;update block flag, PRINT filename (& address if reqd) +F8B6 JSR &F249 ;print newline if needed + +************** update block flag, PRINT filename (& address if reqd) **** + +F8B9 LDY #&00 ;Y=0 +F8BB STY &BA ;current block flag +F8BD LDA &03CA ;block flag +F8C0 STA &03DF ;copy of last read block flag +F8C3 JSR &E7DC ;check if free to print message +F8C6 BEQ &F933 ;if A=0 on return Cassette system is busy +F8C8 LDA #&0D ;else A=&0D :carriage return +F8CA JSR OSWRCH ;print it (note no linefeed as it's via OSWRCH) +F8CD LDA &03B2,Y ;get byte from filename +F8D0 BEQ &F8E2 ;if 0 filename is ended +F8D2 CMP #&20 ;if ? +F988 CMP #&3A ;if A< ASC(':') +F98A BCC &F98E ;goto F98E +F98C ADC #&06 ;else add 7 to convert : ; < = > ? to A B C D E F + +F98E JMP OSWRCH ;print character and return + +******************** print a space ************************************* + +F991 LDA #&20 ;A=' ' +F993 BNE &F98E ;goto F98E to print it + +******************** confirm CFS not operating, nor ESCAPE flag set ***** + +F995 PHP ;save flags on stack +F996 BIT &EB ;CFS Active flag +F998 BMI &F99E ; +F99A BIT &FF ;if ESCAPE condition +F99C BMI &F9A0 ;goto F9A0 +F99E PLP ;get back flags +F99F RTS ;return + +F9A0 JSR &F33B ;close input file +F9A3 JSR &FAF2 ;enable second processor and reset serial system +F9A6 LDA #&7E ;A=&7E (126) Acknowledge ESCAPE +F9A8 JSR OSBYTE ;OSBYTE Call + +F9AB BRK ; +F9AC DB &11 ;error 17 +F9AD DB 'Escape' ; +F9B3 BRK ; + +OS SERIES 10 +LAST PART +GEOFF COX +****************************** LOAD ************************************* + +F9B4 TYA ;A=Y +F9B5 BEQ &F9C4 ; +F9B7 JSR &FA46 ; print message following call + +F9BA DB &0D ; +F9BB DB 'Loading'; +F9C2 DB &0D ; +F9C3 BRK ; + +F9C5 STA &BA ;current block flag +F9C6 LDX #&FF ;X=&FF +F9C8 LDA &C1 ;Checksum result +F9CA BNE &F9D9 ;if not 0 F9D9 +F9CC JSR &FA72 ;else check filename header block matches searched + ;filename if this returns NE then no match +F9CF PHP ;save flags on stack +F9D0 LDX #&FF ;X=&FF +F9D2 LDY #&99 ;Y=&99 +F9D4 LDA #&FA ;A=&FA this set Y/A to point to 'File?' FA99 +F9D6 PLP ;get back flags +F9D7 BNE &F9F5 ;report a query unexpected file name + +F9D9 LDY #&8E ;making Y/A point to 'Data' FA8E for CRC error +F9DB LDA &C1 ;Checksum result +F9DD BEQ &F9E3 ;if 0 F9E3 +F9DF LDA #&FA ;A=&FA +F9E1 BNE &F9F5 ;jump to F9F5 + +F9E3 LDA &03C6 ;block number +F9E6 CMP &B4 ;current block no. lo +F9E8 BNE &F9F1 ;if not eual F9F1 +F9EA LDA &03C7 ;block number hi +F9ED CMP &B5 ;current block no. hi +F9EF BEQ &FA04 ;if equal FA04 + +F9F1 LDY #&A4 ;Y=&A4 +F9F3 LDA #&FA ;A=&FA point to 'Block?' error unexpected block no. + + ;at this point an error HAS occurred + +F9F5 PHA ;save A on stack +F9F6 TYA ;A=Y +F9F7 PHA ;save Y on stack +F9F8 TXA ;A=X +F9F9 PHA ;save X on stack +F9FA JSR &F8B6 ;print CR if indicated by current block flag +F9FD PLA ;get back A +F9FE TAX ;X=A +F9FF PLA ;get back A +FA00 TAY ;Y=A +FA01 PLA ;get back A +FA02 BNE &FA18 ;jump to FA18 + +FA04 TXA ;A=X +FA05 PHA ;save A on stack +FA06 JSR &F8A9 ;report +FA09 JSR &FAD6 ;check loading progress, read another byte +FA0C PLA ;get back A +FA0D TAX ;X=A +FA0E LDA &BE ;CRC workspace +FA10 ORA &BF ;CRC workspace +FA12 BEQ &FA8D ; +FA14 LDY #&8E ;Y=&8E +FA16 LDA #&FA ;A=&FA FA8E points to 'Data?' +FA18 DEC &BA ;current block flag +FA1A PHA ;save A on stack +FA1B BIT &EB ;CFS Active flag +FA1D BMI &FA2C ;if active FA2C +FA1F TXA ;A=X +FA20 AND &0247 ;filing system flag 0=CFS 2=RFS +FA23 BNE &FA2C ; +FA25 TXA ;A=X +FA26 AND #&11 ; +FA28 AND &BB ;current OPTions +FA2A BEQ &FA3C ;ignore errors +FA2C PLA ;get back A +FA2D STA &B9 ;store A on &B9 +FA2F STY &B8 ;store Y on &B8 +FA31 JSR &F68B ;do *EXEC 0 to tidy up +FA34 LSR &EB ;halve CFS Active flag to clear bit 7 + +FA36 JSR &FAE8 ;bell, reset ACIA & motor +FA39 JMP (&00B8) ;display selected error report + +FA3C PLA ;get back A +FA3D INY ;Y=Y+1 +FA3E BNE &FA43 ; +FA40 CLC ;clear carry flag +FA41 ADC #&01 ;Add 1 +FA43 PHA ;save A on stack +FA44 TYA ;A=Y +FA45 PHA ;save Y on stack +FA46 JSR &E7DC ;check if free to print message +FA49 TAY ;Y=A +FA4A PLA ;get back A +FA4B STA &B8 ;&B8=8 +FA4D PLA ;get back A +FA4E STA &B9 ;&B9=A +FA50 TYA ;A=Y +FA51 PHP ;save flags on stack +FA52 INC &B8 ; +FA54 BNE &FA58 ; +FA56 INC &B9 ; +FA58 LDY #&00 ;Y=0 +FA5A LDA (&B8),Y ;get byte +FA5C BEQ &FA68 ;if 0 Fa68 +FA5E PLP ;get back flags +FA5F PHP ;save flags on stack +FA60 BEQ &FA52 ;if 0 FA52 to get next character +FA62 JSR OSASCI ;else print +FA65 JMP &FA52 ;and do it again + +FA68 PLP ;get back flags +FA69 INC &B8 ;increment pointers +FA6B BNE &FA6F ; +FA6D INC &B9 ; +FA6F JMP (&00B8) ;and print error message so no error condition + ;occcurs + +************ compare filenames ****************************************** + +FA72 LDX #&FF ;X=&FF inx will mean X=0 + +FA74 INX ;X=X+1 +FA75 LDA &03D2,X ;sought filename byte +FA78 BNE &FA81 ;if not 0 FA81 +FA7A TXA ;else A=X +FA7B BEQ &FA80 ;if X=0 A=0 exit +FA7D LDA &03B2,X ;else A=filename byte +FA80 RTS ;return + ; +FA81 JSR &E4E3 ;set carry if byte in A is not upper case Alpha +FA84 EOR &03B2,X ;compare with filename +FA87 BCS &FA8B ;if carry set FA8B +FA89 AND #&DF ;else convert to upper case +FA8B BEQ &FA74 ;and if A=0 filename characters match so do it again +FA8D RTS ;return + ; +FA8E BRK ; +FA8F DB &D8 ;error number +FA90 DB 'Data' ; +FA96 BRK ; + +FA97 BNE &FAAE ; + +FA99 BRK ; +FA9A DB &DB ;error number +FA9B DB 'File?' ; +FAA1 BRK ; + +FAA2 BNE &FAAE ; + +FAA4 BRK ; +FAA5 DB &DA ;error number +FAA6 DB 'Block?' +FAAD BRK ; + +FAAE LDA &BA ;current block flag +FAB0 BEQ &FAD3 ;if 0 FAD3 else +FAB2 TXA ;A=X +FAB3 BEQ &FAD3 ;If X=0 FAD3 +FAB5 LDA #&22 ;A=&22 +FAB7 BIT &BB ;current OPTions checking bits 1 and 5 +FAB9 BEQ &FAD3 ;if neither set no retry so FAD3 else +FABB JSR &FB46 ;reset ACIA +FABE TAY ;Y=A +FABF JSR &FA4A ;print following message + +FAC2 DB &0D ;Carriage RETURN +FAC3 DB &07 ;BEEP +FAC4 DB 'Rewind Tape' ; +FACF DW &0D0D ;two more newlines +FAD1 BRK ; + +FAD2 RTS ;return + +FAD3 JSR &F24D ;print CR if CFS not operational +FAD6 LDA &C2 ;filename length/progress flag +FAD8 BEQ &FAD2 ;if 0 return else +FADA JSR &F995 ;confirm ESC not set and CFS not executing +FADD LDA &0247 ;filing system flag 0=CFS 2=RFS +FAE0 BEQ &FAD6 ;if CFS FAD6 +FAE2 JSR &F588 ;else set up ACIA etc +FAE5 JMP &FAD6 ;and loop back again + +********** sound bell, reset ACIA, motor off **************************** + +FAE8 JSR &E7DC ;check if free to print message +FAEB BEQ &FAF2 ;enable second processor and reset serial system +FAED LDA #&07 ;beep +FAEF JSR OSWRCH ; +FAF2 LDA #&80 ; +FAF4 JSR &FBBD ;enable 2nd proc. if present and set up osfile block +FAF7 LDX #&00 ; +FAF9 JSR &FB95 ;switch on motor +FAFC PHP ;save flags on stack +FAFD SEI ;prevent IRQ interrupts +FAFE LDA &0282 ;get serial ULA control register setting +FB01 STA &FE10 ;write to serial ULA control register setting +FB04 LDA #&00 ;A=0 +FB06 STA &EA ;store A RS423 timeout counter +FB08 BEQ &FB0B ;jump FB0B + +FB0A PHP ;save flags on stacksave flags +FB0B JSR &FB46 ;release ACIA (by &FE08=3) +FB0E LDA &0250 ;get last setting of ACIA +FB11 JMP &E189 ;set ACIA and &250 from A before exit + +FB14 PLP ;get back flags +FB15 BIT &FF ;if bit 7of ESCAPE flag not set +FB17 BPL &FB31 ;then FB31 +FB19 RTS ;else return as unserviced ESCAPE is pending + + +************************************************************************* +* * +* Claim serial system for sequential Access * +* * +************************************************************************* + +FB1A LDA &E3 ;get cassette filing system options byte + ;high nybble used for LOAD & SAVE operations + ;low nybble used for sequential access + + ;0000 Ignore errors, no messages + ;0001 Abort if error, no messages + ;0010 Retry after error, no messages + ;1000 Ignore error short messages + ;1001 Abort if error short messages + ;1010 Retry after error short messages + ;1100 Ignore error long messages + ;1101 Abort if error long messages + ;1110 Retry after error long messages + +FB1C ASL ;move low nybble into high nybble +FB1D ASL ; +FB1E ASL ; +FB1F ASL ; +FB20 STA &BB ;current OPTions save into &BB +FB22 LDA &03D1 ;get sequential block gap +FB25 BNE &FB2F ;goto to &FB2F + + +************************************************************************* +* * +* claim serial system for cassette etc. * +* * +************************************************************************* + +FB27 LDA &E3 ;get cassette filing system options byte + ;high nybble used for LOAD & SAVE operations + ;low nybble used for sequential access + + ;0000 Ignore errors, no messages + ;0001 Abort if error, no messages + ;0010 Retry after error, no messages + ;1000 Ignore error short messages + ;1001 Abort if error short messages + ;1010 Retry after error short messages + ;1100 Ignore error long messages + ;1101 Abort if error long messages + ;1110 Retry after error long messages + +FB29 AND #&F0 ;clear low nybble +FB2B STA &BB ;as current OPTions +FB2D LDA #&06 ;set current interblock gap +FB2F STA &C7 ;to 6 + +FB31 CLI ;allow interrupts +FB32 PHP ;save flags on stack +FB33 SEI ;prevent interrupts +FB34 BIT &024F ;check if RS423 is busy +FB37 BPL &FB14 ;if not FB14 +FB39 LDA &EA ;see if RS423 has timed out +FB3B BMI &FB14 ;if not FB14 + +FB3D LDA #&01 ;else load RS423 timeout counter with +FB3F STA &EA ;1 to indicate that cassette has 6850 +FB41 JSR &FB46 ;reset ACIA with &FE80=3 +FB44 PLP ;get back flags +FB45 RTS ;return + +FB46 LDA #&03 ;A=3 +FB48 BNE &FB65 ;and exit after resetting ACIA + + +********************** set ACIA control register ********************** + +FB4A LDA #&30 ;set current ACIA control register +FB4C STA &CA ;to &30 +FB4E BNE &FB63 ;and goto FB63 + ;if bit 7=0 motor off 1=motor on + +***************** control cassette system ******************************* + +FB50 LDA #&05 ;set &FE10 to 5 +FB52 STA &FE10 ;setting a transmit baud rate of 300,motor off + +FB55 LDX #&FF ; +FB57 DEX ;delay loop +FB58 BNE &FB57 ; + +FB5A STX &CA ;&CA=0 +FB5C LDA #&85 ;Turn motor on and keep baud rate at 300 recieve +FB5E STA &FE10 ;19200 transmit +FB61 LDA #&D0 ;A=&D0 + +FB63 ORA &C6 ; +FB65 STA &FE08 ;set up ACIA control register +FB68 RTS ;returnand return + +FB69 LDX &03C6 ;block number +FB6C LDY &03C7 ;block number hi +FB6F INX ;X=X+1 +FB70 STX &B4 ;current block no. lo +FB72 BNE &FB75 ; +FB74 INY ;Y=Y+1 +FB75 STY &B5 ;current block no. hi +FB77 RTS ;return + ; +FB78 LDY #&00 ; +FB7A STY &C0 ;filing system buffer flag + +*****************set (zero) checksum bytes ****************************** + +FB7C STY &BE ;CRC workspace +FB7E STY &BF ;CRC workspace +FB80 RTS ;return + +*********** copy sought filename routine ******************************** + +FB81 LDY #&FF ;Y=&FF +FB83 INY ;Y=Y+1 +FB84 INX ;X=X+1 +FB85 LDA &0300,X ; +FB88 STA &03D2,Y ;sought filename +FB8B BNE &FB83 ;until end of filename (0) +FB8D RTS ;return + ; +FB8E LDY #&00 ;Y=0 + +********************** switch Motor on ********************************** + +FB90 CLI ;allow IRQ interrupts +FB91 LDX #&01 ;X=1 +FB93 STY &C3 ;store Y as current file handle + +********************: control motor ************************************ + +FB95 LDA #&89 ;do osbyte 137 +FB97 LDY &C3 ;get back file handle (preserved thru osbyte) +FB99 JMP OSBYTE ;turn on motor + +****************** confirm file is open ******************************** + +FB9C STA &BC ;file status or temporary store +FB9E TYA ;A=Y +FB9F EOR &0247 ;filing system flag 0=CFS 2=RFS +FBA2 TAY ;Y=A +FBA3 LDA &E2 ;CFS status byte +FBA5 AND &BC ;file status or temporary store +FBA7 LSR ;A=A/2 +FBA8 DEY ;Y=Y-1 +FBA9 BEQ &FBAF ; +FBAB LSR ;A=A/2 +FBAC DEY ;Y=Y-1 +FBAD BNE &FBB1 ; +FBAF BCS &FBFE ; + +FBB1 BRK ; +FBB2 DB &DE ;error number +FBB3 DB 'Channel' ; +FBBA BRK ; + +************* read from second processor ******************************** + +FBBB LDA #&01 ;A=1 +FBBD JSR &FBD3 ;check if second processor file test tube prescence +FBC0 BEQ &FBFE ;if not exit +FBC2 TXA ;A=X +FBC3 LDX #&B0 ;current load address +FBC5 LDY #&00 ;Y=00 +FBC7 PHA ;save A on stack +FBC8 LDA #&C0 ;filing system buffer flag +FBCA JSR &0406 ;and out to TUBE +FBCD BCC &FBCA ; +FBCF PLA ;get back A +FBD0 JMP &0406 ; + +*************** check if second processor file test tube prescence ****** + +FBD3 TAX ;X=A +FBD4 LDA &B2 ;current load address high word +FBD6 AND &B3 ;current load address high word +FBD8 CMP #&FF ; +FBDA BEQ &FBE1 ;if &FF then its for base processor +FBDC LDA &027A ;&FF if tube present +FBDF AND #&80 ;to set bit 7 alone +FBE1 RTS ;return + +******** control ACIA and Motor ***************************************** + +FBE2 LDA #&85 ;A=&85 +FBE4 STA &FE10 ;write to serial ULA control register setting +FBE7 JSR &FB46 ;reset ACIA +FBEA LDA #&10 ;A=16 +FBEC JSR &FB63 ;set ACIA to CFS baud rate +FBEF JSR &F995 ;confirm ESC not set and CFS not executing +FBF2 LDA &FE08 ;read ACIA status register +FBF5 AND #&02 ;clear all but bit 1 +FBF7 BEQ &FBEF ;if clear FBEF +FBF9 LDA #&AA ;else A=&AA +FBFB STA &FE09 ;transmit data register +FBFE RTS ;return + +FBFF BRK ; +************** FRED 1MHz Bus memory-mapped I/O ************************** + +FC00 ;test hardware +FC10-13 ;teletext +FC14-1F ;Prestel +FC20-27 ;IEEE interface +FC30 ; +FC40-47 ;winchester disc interface +FC50 ; +FC60 ; +FC70 ; +FC80 ; +FC90 ; +FCA0 ; +FCB0 ; +FCC0 ; +FCD0 ; +FCE0 ; +FCF0 ; +FCFF ;paging register for JIM expansion memory + +************** JIM 1MHz Bus memory-expansion page *********************** + +FD00-FF ; +FDFE ;Ecosoak Vector + +************** SHEILA MOS memory-mapped I/O *************************** + + ;DEVICE WRITE READ +FE00 ;6845 CRTC address register +FE01 ;6845 CRTC data register +FE02 ;Border colour border colour +FE03 ; +FE04 ; +FE05 ; +FE06 ; +FE07 ; +FE08 ;6850 ACIA control register status register +FE09 ;6850 ACIA transmit data recieve data +FE0A ; +FE0B ; +FE0C ; +FE0D ; +FE0E ; +FE0F ; +FE10 ;SERIAL ULA control register +FE11 ; +FE12 ; +FE13 ; +FE14 ; +FE15 ; +FE16 ; +FE17 ; +FE18 ;68B54 ADLC Disable interrupts Econet station ID +FE19 ; +FE1A ; +FE1B ; +FE1C ; +FE1D ; +FE1E ; +FE1F ; +FE20 ;Video ULA control register +FE21 ;Video ULA palette register palette register +FE22 ; +FE23 ; +FE24 ; +FE25 ; +FE26 ; +FE27 ; +FE28 ; +FE29 ; +FE2A ; +FE2B ; +FE2C ; +FE2D ; +FE2E ; +FE2F ; +FE30 ;ROM latch paged ROM ID write only +FE31 ;ALTAIR RAM protect +FE32 ; +FE33 ; +FE34 ;Shadow RAM B+ only note different OS +FE35 ; +FE36 ; +FE37 ; +FE38 ; +FE39 ; +FE3A ; +FE3B ; +FE3C ; +FE3D ; +FE3E ; +FE3F ; +FE40 ;MOS 6522 VIA Output Register B Input Register B +FE41 ;MOS 6522 VIA Output Register A Input Register A +FE42 ;MOS 6522 VIA data direction register B +FE43 ;MOS 6522 VIA data direction register A +FE44 ;MOS 6522 VIA T1C-L latches T1 low Order counter +FE45 ;MOS 6522 VIA T1C-H counter +FE46 ;MOS 6522 VIA T1L-L low order latches +FE47 ;MOS 6522 VIA T1L-H high order latches +FE48 ;MOS 6522 VIA T2C-L latches T2C-L lo order counter +FE49 ;MOS 6522 VIA T2C-H T2 high order counter +FE4A ;MOS 6522 VIA shift register +FE4B ;MOS 6522 VIA auxilliary control register ACR +FE4C ;MOS 6522 VIA Peripheral control register PCR +FE4D ;MOS 6522 VIA Interrupt flag register IFR +FE4E ;MOS 6522 VIA Interrupt enable register IER +FE4F ;MOS 6522 VIA ORB/IRB but no handshake +FE50 ; +FE51 ; +FE52 ; +FE53 ; +FE54 ; +FE55 ; +FE56 ; +FE57 ; +FE58 ; +FE59 ; +FE5A ; +FE5B ; +FE5C ; +FE5D ; +FE5E ; +FE5F ; +FE60 ;USER 6522 VIA Output Register B Input Register B +FE61 ;USER 6522 VIA Output Register A Input Register A +FE62 ;USER 6522 VIA data direction register B +FE63 ;USER 6522 VIA data direction register A +FE64 ;USER 6522 VIA T1C-L latches T1 low Order counter +FE65 ;USER 6522 VIA T1C-H counter +FE66 ;USER 6522 VIA T1L-L low order latches +FE67 ;USER 6522 VIA T1L-H high order latches +FE68 ;USER 6522 VIA T2C-L latches T2C-L lo order counter +FE69 ;USER 6522 VIA T2C-H T2 high order counter +FE6A ;USER 6522 VIA shift register +FE6B ;USER 6522 VIA auxilliary control register ACR +FE6C ;USER 6522 VIA Peripheral control register PCR +FE6D ;USER 6522 VIA Interrupt flag register IFR +FE6E ;USER 6522 VIA Interrupt enable register IER +FE6F ;USER 6522 VIA ORB/IRB but no handshake +FE70 ; +FE71 ; +FE72 ; +FE73 ; +FE74 ; +FE75 ; +FE76 ; +FE77 ; +FE78 ; +FE79 ; +FE7A ; +FE7B ; +FE7C ; +FE7D ; +FE7E ; +FE7F ; +FE80 ;8271 FDC command register status register +FE81 ;8271 FDC parameter register result register +FE82 ;8271 FDC reset register +FE83 ;8271 FDC illegal illegal +FE84 ;8271 FDC data data +FE85 ; +FE86 ; +FE87 ; +FE88 ; +FE89 ; +FE8A ; +FE8B ; +FE8C ; +FE8D ; +FE8E ; +FE8F ; +FE90 ; +FE91 ; +FE92 ; +FE93 ; +FE94 ; +FE95 ; +FE96 ; +FE97 ; +FE98 ; +FE99 ; +FE9A ; +FE9B ; +FE9C ; +FE9D ; +FE9E ; +FE9F ; +FEA0 ;68B54 ADLC control register 1 status register 1 +FEA1 ;68B54 ADLC control register 2/3 status register 2/3 +FEA2 ;68B54 ADLC Tx FIFO (frame continue) Rx FIFO +FEA3 ;68B54 ADLC Tx FIFO (frame terminate) Rx FIFO +FEA4 ; +FEA5 ; +FEA6 ; +FEA7 ; +FEA8 ; +FEA9 ; +FEAA ; +FEAB ; +FEAC ; +FEAD ; +FEAE ; +FEAF ; +FEB0 ; +FEB1 ; +FEB2 ; +FEB3 ; +FEB4 ; +FEB5 ; +FEB6 ; +FEB7 ; +FEB8 ; +FEB9 ; +FEBA ; +FEBB ; +FEBC ; +FEBD ; +FEBE ; +FEBF ; +FEC0 ;7002 ADC data latch A/D start status +FEC1 ;7002 ADC hi data byte +FEC2 ;7002 ADC lo data byte +FEC3 ; +FEC4 ; +FEC5 ; +FEC6 ; +FEC7 ; +FEC8 ; +FEC9 ; +FECA ; +FECB ; +FECC ; +FECD ; +FECE ; +FECF ; +FED0 ; +FED1 ; +FED2 ; +FED3 ; +FED4 ; +FED5 ; +FED6 ; +FED7 ; +FED8 ; +FED9 ; +FEDA ; +FEDB ; +FEDC ; +FEDD ; +FEDE ; +FEDF ; +FEE0 ;TUBE FIFO1 status register +FEE1 ;TUBE FIFO1 +FEE2 ;TUBE FIFO2 status register +FEE3 ;TUBE FIFO2 +FEE4 ;TUBE FIFO3 status register +FEE5 ;TUBE FIFO3 +FEE6 ;TUBE FIFO4 status register +FEE7 ;TUBE FIFO4 +FEE8 ; +FEE9 ; +FEEA ; +FEEB ; +FEEC ; +FEED ; +FEEE ; +FEEF ; +FEF0 ; +FEF1 ; +FEF2 ; +FEF3 ; +FEF4 ; +FEF5 ; +FEF6 ; +FEF7 ; +FEF8 ; +FEF9 ; +FEFA ; +FEFB ; +FEFC ; +FEFD ; +FEFE ; +FEFF ; + + +********** EXTENDED VECTOR ENTRY POINTS********************************** +;vectors are pointed to &F000 +vector No. vectors may then be directed thru +;a three byte vector table whose XY address is given by osbyte A8, X=0, Y=&FF +;this is set up as lo-hi byte in ROM and ROM number + +FF00 JSR &FF51 ;XUSERV +FF03 JSR &FF51 ;XBRKV +FF06 JSR &FF51 ;XIRQ1V +FF09 JSR &FF51 ;XIRQ2V +FF0C JSR &FF51 ;XCLIV +FF0F JSR &FF51 ;XBYTEV +FF12 JSR &FF51 ;XWORDV +FF15 JSR &FF51 ;XWRCHV +FF18 JSR &FF51 ;XRDCHV +FF1B JSR &FF51 ;XFILEV +FF1E JSR &FF51 ;XARGSV +FF21 JSR &FF51 ;XBGETV +FF24 JSR &FF51 ;XBPUTV +FF27 JSR &FF51 ;XGBPBV +FF2A JSR &FF51 ;XFINDV +FF2D JSR &FF51 ;XFSCV +FF30 JSR &FF51 ;XEVENTV +FF33 JSR &FF51 ;XUPTV +FF36 JSR &FF51 ;XNETV +FF39 JSR &FF51 ;XVDUV +FF3C JSR &FF51 ;XKEYV +FF3F JSR &FF51 ;XINSV +FF42 JSR &FF51 ;XREMV +FF45 JSR &FF51 ;XCNPV +FF48 JSR &FF51 ;XIND1V +FF4B JSR &FF51 ;XIND2V +FF4E JSR &FF51 ;XIND3V + +;at this point the stack will hold 4 bytes (at least) +;S 0,1 extended vector address +;S 2,3 address of calling routine +;A,X,Y,P will be as at entry + +FF51 PHA ;save A on stack +FF52 PHA ;save A on stack +FF53 PHA ;save A on stack +FF54 PHA ;save A on stack +FF55 PHA ;save A on stack +FF56 PHP ;save flags on stack +FF57 PHA ;save A on stack +FF58 TXA ;A=X +FF59 PHA ;save X on stack +FF5A TYA ;A=Y +FF5B PHA ;save Y on stack +FF5C TSX ;get stack pointer into X (&F2 or less) +FF5D LDA #&FF ;A=&FF +FF5F STA &0108,X ;A +FF62 LDA #&88 ; +FF64 STA &0107,X ; +FF67 LDY &010A,X ;this is VECTOR number*3+2!! +FF6A LDA &0D9D,Y ;lo byte of action address +FF6D STA &0105,X ;store it on stack +FF70 LDA &0D9E,Y ;get hi byte +FF73 STA &0106,X ;store it on stack + ;at this point stack has YXAP and action address + ;followed by return address and 5 more bytes +FF76 LDA &F4 ; +FF78 STA &0109,X ;store original ROM number below this +FF7B LDA &0D9F,Y ;get new ROM number +FF7E STA &F4 ;store it as ram copy +FF80 STA &FE30 ;and switch to that ROM +FF83 PLA ;get back A +FF84 TAY ;Y=A +FF85 PLA ;get back A +FF86 TAX ;X=A +FF87 PLA ;get back A +FF88 RTI ;get back flags and jump to ROM vectored entry + ;leaving return address and 5 more bytes on stack + +************ return address from ROM indirection ************************ + +;at this point stack comprises original ROM number,return from JSR &FF51, +;return from original call the return from FF51 is garbage so; + +FF89 PHP ;save flags on stack +FF8A PHA ;save A on stack +FF8B TXA ;A=X +FF8C PHA ;save X on stack +FF8D TSX ; (&F7 or less) +FF8E LDA &0102,X ;STORE A AND P OVER +FF91 STA &0105,X ;return address from (JSR &FF51) +FF94 LDA &0103,X ;hiding garbage by duplicating A and X just saved +FF97 STA &0106,X ; + ;now we have + ;flags, + ;A, + ;X, + ;ROM number, + ;A, + ;flags, + ;and original return address on stack + ;so +FF9A PLA ;get back X +FF9B TAX ;X=A +FF9C PLA ;get back A lose next two bytes +FF9D PLA ;get back A lose +FF9E PLA ;get back A ROM number +FF9F STA &F4 ;store it +FFA1 STA &FE30 ;and set it +FFA4 PLA ;get back A +FFA5 PLP ;get back flags +FFA6 RTS ;return and exit pulling original return address + ;from stack +;FFA6 is also default input for CFS OSBPGB, VDUV, IND1V,IND2V,IND3V +;as these functions are not implemented by the OS but may be used +;by software or other filing systems or ROMs + + +************************************************************************* +* * +* OSBYTE &9D FAST BPUT * +* * +************************************************************************* +FFA7 TXA ;A=X +FFA8 BCS &FFD4 ;carry always set, jump to BPUT + + +************************************************************************* +* * +* OSBYTE &92 READ A BYTE FROM FRED * +* * +************************************************************************* ; + +FFAA LDY &FC00,X ;read a byte from FRED area +FFAD RTS ;return + + +************************************************************************* +* * +* OSBYTE &94 READ A BYTE FROM JIM * +* * +************************************************************************* ; + ; +FFAE LDY &FD00,X ;read a byte from JIM area +FFB1 RTS ;return + + +************************************************************************* +* * +* OSBYTE &96 READ A BYTE FROM SHEILA * +* * +************************************************************************* ; + ; +FFB2 LDY &FE00,X ;read a byte from SHEILA memory mapped I/O area +FFB5 RTS ;return + + +*********** DEFAULT VECTOR TABLE **************************************** + +FFB6 DB 36 ;length of look up table in bytes +FFB7 DB 40 ;low byte of address of this table +FFB8 DB D9 ;high byte of address of this table + + +************************************************************************** +************************************************************************** +** ** +** OPERATING SYSTEM FUNCTION CALLS ** +** ** +************************************************************************** +************************************************************************** + +FFB9 JMP &DC0B ;OSRDRM get a byte from sideways ROM +FFBC JMP &C4C0 ;VDUCHR VDU character output +FFBF JMP &E494 ;OSEVEN generate an EVENT +FFC2 JMP &EA1E ;GSINIT initialise OS string +FFC5 JMP &EA2F ;GSREAD read character from input stream +FFC8 JMP &DEC5 ;NVRDCH non vectored OSRDCH +FFCB JMP &E0A4 ;NVWRCH non vectored OSWRCH +FFCE JMP (&021C) ;OSFIND open or close a file +FFD1 JMP (&021A) ;OSGBPB transfer block to or from a file +FFD4 JMP (&0218) ;OSBPUT save a byte to file +FFD7 JMP (&0216) ;OSBGET get a byte from file +FFDA JMP (&0214) ;OSARGS read or write file arguments +FFDD JMP (&0212) ;OSFILE read or write a file +FFE0 JMP (&0210) ;OSRDCH get a byte from current input stream +FFE3 CMP #&0D ;OSASCI output a byte to VDU stream expanding +FFE5 BNE &FFEE ; carriage returns (&0D) to LF/CR (&0A,&0D) +FFE7 LDA #&0A ;OSNEWL output a CR/LF to VDU stream +FFE9 JSR OSWRCH ;Outputs A followed by CR to VDU stream +FFEC LDA #&0D ;OSWRCR output a CR to VDU stream +FFEE JMP (&020E) ;OSWRCH output a character to the VDU stream +FFF1 JMP (&020C) ;OSWORD perform operation using parameter table +FFF4 JMP (&020A) ;OSBYTE perform operation with single bytes +FFF7 JMP (&0208) ;OSCLI pass string to command line interpreter + + +************************************************************************* +* * +* 6502 Vectors * +* * +************************************************************************* + +FFFA DW &0D00 ;NMI address +FFFC DW &D9CD ;RESET address +FFFE DW &DC1C ;IRQ address + +That's it the end of the series and the end of Micronet. + +See you on the new system or in the paper mags. + +Geoff + diff --git a/BASIC/Advanced_BASIC_ROM_User_Guide.pdf b/BASIC/Advanced_BASIC_ROM_User_Guide.pdf new file mode 100755 index 0000000..cec9757 Binary files /dev/null and b/BASIC/Advanced_BASIC_ROM_User_Guide.pdf differ diff --git a/BASIC/BASIC ROM.pdf b/BASIC/BASIC ROM.pdf new file mode 100755 index 0000000..872605d Binary files /dev/null and b/BASIC/BASIC ROM.pdf differ diff --git a/FS/Acorn_1770DiscIFUpgradeKit.pdf b/FS/Acorn_1770DiscIFUpgradeKit.pdf new file mode 100644 index 0000000..bdd12db Binary files /dev/null and b/FS/Acorn_1770DiscIFUpgradeKit.pdf differ diff --git a/FS/Acorn_ADFSUG.pdf b/FS/Acorn_ADFSUG.pdf new file mode 100644 index 0000000..50ab7b6 Binary files /dev/null and b/FS/Acorn_ADFSUG.pdf differ diff --git a/FS/Opus_DDOS.pdf b/FS/Opus_DDOS.pdf new file mode 100755 index 0000000..3790214 Binary files /dev/null and b/FS/Opus_DDOS.pdf differ diff --git a/ICs/146818 RTC/MC146818A_RTC_1984.pdf b/ICs/146818 RTC/MC146818A_RTC_1984.pdf new file mode 100755 index 0000000..fdcb5d0 Binary files /dev/null and b/ICs/146818 RTC/MC146818A_RTC_1984.pdf differ diff --git a/ICs/1770 FDC/WD1772-JLG.pdf b/ICs/1770 FDC/WD1772-JLG.pdf new file mode 100755 index 0000000..849fb0f Binary files /dev/null and b/ICs/1770 FDC/WD1772-JLG.pdf differ diff --git a/ICs/1770 FDC/WD1772.pdf b/ICs/1770 FDC/WD1772.pdf new file mode 100755 index 0000000..011f7e5 Binary files /dev/null and b/ICs/1770 FDC/WD1772.pdf differ diff --git a/ICs/23128 EPROM/UPD23128-NEC.pdf b/ICs/23128 EPROM/UPD23128-NEC.pdf new file mode 100755 index 0000000..e85e536 Binary files /dev/null and b/ICs/23128 EPROM/UPD23128-NEC.pdf differ diff --git a/ICs/6502 CPU/6502-NMOS.extra.opcodes.txt b/ICs/6502 CPU/6502-NMOS.extra.opcodes.txt new file mode 100755 index 0000000..33cfe25 --- /dev/null +++ b/ICs/6502 CPU/6502-NMOS.extra.opcodes.txt @@ -0,0 +1,642 @@ + + "Extra Instructions Of The 65XX Series CPU" + + By: Adam Vardy (abe0084@infonet.st-johns.nf.ca) + + +[File created: 22, Aug. 1995... 27, Sept. 1996] + +The following is a list of 65XX/85XX extra opcodes. The operation codes +for the 6502 CPU fit in a single byte; out of 256 possible combinations, +only 151 are "legal." This text describes the other 256-151= 105 operation +codes. These opcodes are not generally recognized as part of the 6502 +instruction set. They are also referred to as undefined opcodes or +undocumented opcodes or non-standard opcodes or unofficial opcodes. In +"The Commodore 64 Programmer's Reference Guide" their hexadecimal values +are simply marked as future expansion. This list of opcodes was compiled +with help from "The Complete Inner Space Anthology" by Karl J. H. Hildon. + +I have marked off the beginning of the description of each opcode with a +few asterisks. At times, I also included an alternate name in parenthesis. +All opcode values are given in hexadecimal. These hexadecimal values are +listed immediately to the right of any sample code. The lowercase letters +found in these examples represent the hex digits that you must provide as +the instruction's immediate byte value or as the instruction's destination +or source address. Thus immediate values and zero page addresses are +referred to as 'ab'. For absolute addressing mode the two bytes of an +absolute address are referred to as 'cd' and 'ab'. + +Execution times for all opcodes are given alongside to the very right of +any sample code. A number of the opcodes described here combine the +operation of two regular 6502 instructions. You can refer to a book on the +6502 instruction set for more information, such as which flags a particular +instruction affects. + + +ASO *** (SLO) +This opcode ASLs the contents of a memory location and then ORs the result +with the accumulator. + +Supported modes: + +ASO abcd ;0F cd ab ;No. Cycles= 6 +ASO abcd,X ;1F cd ab ; 7 +ASO abcd,Y ;1B cd ab ; 7 +ASO ab ;07 ab ; 5 +ASO ab,X ;17 ab ; 6 +ASO (ab,X) ;03 ab ; 8 +ASO (ab),Y ;13 ab ; 8 + +(Sub-instructions: ORA, ASL) + +Here is an example of how you might use this opcode: + +ASO $C010 ;0F 10 C0 + +Here is the same code using equivalent instructions. + +ASL $C010 +ORA $C010 + +RLA *** +RLA ROLs the contents of a memory location and then ANDs the result with +the accumulator. + +Supported modes: + +RLA abcd ;2F cd ab ;No. Cycles= 6 +RLA abcd,X ;3F cd ab ; 7 +RLA abcd,Y ;3B cd ab ; 7 +RLA ab ;27 ab ; 5 +RLA ab,X ;37 ab ; 6 +RLA (ab,X) ;23 ab ; 8 +RLA (ab),Y ;33 ab ; 8 + +(Sub-instructions: AND, ROL) + +Here's an example of how you might write it in a program. + +RLA $FC,X ;37 FC + +Here's the same code using equivalent instructions. + +ROL $FC,X +AND $FC,X + +LSE *** (SRE) +LSE LSRs the contents of a memory location and then EORs the result with +the accumulator. + +Supported modes: + +LSE abcd ;4F cd ab ;No. Cycles= 6 +LSE abcd,X ;5F cd ab ; 7 +LSE abcd,Y ;5B cd ab ; 7 +LSE ab ;47 ab ; 5 +LSE ab,X ;57 ab ; 6 +LSE (ab,X) ;43 ab ; 8 +LSE (ab),Y ;53 ab ; 8 + +(Sub-instructions: EOR, LSR) + +Example: + +LSE $C100,X ;5F 00 C1 + +Here's the same code using equivalent instructions. + +LSR $C100,X +EOR $C100,X + +RRA *** +RRA RORs the contents of a memory location and then ADCs the result with +the accumulator. + +Supported modes: + +RRA abcd ;6F cd ab ;No. Cycles= 6 +RRA abcd,X ;7F cd ab ; 7 +RRA abcd,Y ;7B cd ab ; 7 +RRA ab ;67 ab ; 5 +RRA ab,X ;77 ab ; 6 +RRA (ab,X) ;63 ab ; 8 +RRA (ab),Y ;73 ab ; 8 + +(Sub-instructions: ADC, ROR) + +Example: + +RRA $030C ;6F 0C 03 + +Equivalent instructions: + +ROR $030C +ADC $030C + +AXS *** (SAX) +AXS ANDs the contents of the A and X registers (without changing the +contents of either register) and stores the result in memory. +AXS does not affect any flags in the processor status register. + +Supported modes: + +AXS abcd ;8F cd ab ;No. Cycles= 4 +AXS ab ;87 ab ; 3 +AXS ab,Y ;97 ab ; 4 +AXS (ab,X) ;83 ab ; 6 + +(Sub-instructions: STA, STX) + +Example: + +AXS $FE ;87 FE + +Here's the same code using equivalent instructions. + +STX $FE +PHA +AND $FE +STA $FE +PLA + +LAX *** +This opcode loads both the accumulator and the X register with the contents +of a memory location. + +Supported modes: + +LAX abcd ;AF cd ab ;No. Cycles= 4 +LAX abcd,Y ;BF cd ab ; 4* +LAX ab ;A7 ab ;*=add 1 3 +LAX ab,Y ;B7 ab ;if page 4 +LAX (ab,X) ;A3 ab ;boundary 6 +LAX (ab),Y ;B3 ab ;is crossed 5* + +(Sub-instructions: LDA, LDX) + +Example: + +LAX $8400,Y ;BF 00 84 + +Equivalent instructions: + +LDA $8400,Y +LDX $8400,Y + +DCM *** (DCP) +This opcode DECs the contents of a memory location and then CMPs the result +with the A register. + +Supported modes: + +DCM abcd ;CF cd ab ;No. Cycles= 6 +DCM abcd,X ;DF cd ab ; 7 +DCM abcd,Y ;DB cd ab ; 7 +DCM ab ;C7 ab ; 5 +DCM ab,X ;D7 ab ; 6 +DCM (ab,X) ;C3 ab ; 8 +DCM (ab),Y ;D3 ab ; 8 + +(Sub-instructions: CMP, DEC) + +Example: + +DCM $FF ;C7 FF + +Equivalent instructions: + +DEC $FF +CMP $FF + +INS *** (ISC) +This opcode INCs the contents of a memory location and then SBCs the result +from the A register. + +Supported modes: + +INS abcd ;EF cd ab ;No. Cycles= 6 +INS abcd,X ;FF cd ab ; 7 +INS abcd,Y ;FB cd ab ; 7 +INS ab ;E7 ab ; 5 +INS ab,X ;F7 ab ; 6 +INS (ab,X) ;E3 ab ; 8 +INS (ab),Y ;F3 ab ; 8 + +(Sub-instructions: SBC, INC) + +Example: + +INS $FF ;E7 FF + +Equivalent instructions: + +INC $FF +SBC $FF + +ALR *** +This opcode ANDs the contents of the A register with an immediate value and +then LSRs the result. + +One supported mode: + +ALR #ab ;4B ab ;No. Cycles= 2 + +Example: + +ALR #$FE ;4B FE + +Equivalent instructions: + +AND #$FE +LSR A + +ARR *** +This opcode ANDs the contents of the A register with an immediate value and +then RORs the result. + +One supported mode: + +ARR #ab ;6B ab ;No. Cycles= 2 + +Here's an example of how you might write it in a program. + +ARR #$7F ;6B 7F + +Here's the same code using equivalent instructions. + +AND #$7F +ROR A + +XAA *** +XAA transfers the contents of the X register to the A register and then +ANDs the A register with an immediate value. + +One supported mode: + +XAA #ab ;8B ab ;No. Cycles= 2 + +Example: + +XAA #$44 ;8B 44 + +Equivalent instructions: + +TXA +AND #$44 + +OAL *** +This opcode ORs the A register with #$EE, ANDs the result with an immediate +value, and then stores the result in both A and X. + +One supported mode: + +OAL #ab ;AB ab ;No. Cycles= 2 + +Here's an example of how you might use this opcode: + +OAL #$AA ;AB AA + +Here's the same code using equivalent instructions: + +ORA #$EE +AND #$AA +TAX + +SAX *** +SAX ANDs the contents of the A and X registers (leaving the contents of A +intact), subtracts an immediate value, and then stores the result in X. +... A few points might be made about the action of subtracting an immediate +value. It actually works just like the CMP instruction, except that CMP +does not store the result of the subtraction it performs in any register. +This subtract operation is not affected by the state of the Carry flag, +though it does affect the Carry flag. It does not affect the Overflow +flag. + +One supported mode: + +SAX #ab ;CB ab ;No. Cycles= 2 + +Example: + +SAX #$5A ;CB 5A + +Equivalent instructions: + +STA $02 +TXA +AND $02 +SEC +SBC #$5A +TAX +LDA $02 + +Note: Memory location $02 would not be altered by the SAX opcode. + +NOP *** +NOP performs no operation. Opcodes: 1A, 3A, 5A, 7A, DA, FA. +Takes 2 cycles to execute. + +SKB *** +SKB stands for skip next byte. +Opcodes: 80, 82, C2, E2, 04, 14, 34, 44, 54, 64, 74, D4, F4. +Takes 2, 3, or 4 cycles to execute. + +SKW *** +SKW skips next word (two bytes). +Opcodes: 0C, 1C, 3C, 5C, 7C, DC, FC. +Takes 4 cycles to execute. + +To be dizzyingly precise, SKW actually performs a read operation. It's +just that the value read is not stored in any register. Further, opcode 0C +uses the absolute addressing mode. The two bytes which follow it form the +absolute address. All the other SKW opcodes use the absolute indexed X +addressing mode. If a page boundary is crossed, the execution time of one +of these SKW opcodes is upped to 5 clock cycles. +-------------------------------------------------------------------------- + +The following opcodes were discovered and named exclusively by the author. +(Or so it was thought before.) + +HLT *** +HLT crashes the microprocessor. When this opcode is executed, program +execution ceases. No hardware interrupts will execute either. The author +has characterized this instruction as a halt instruction since this is the +most straightforward explanation for this opcode's behaviour. Only a reset +will restart execution. This opcode leaves no trace of any operation +performed! No registers affected. + +Opcodes: 02, 12, 22, 32, 42, 52, 62, 72, 92, B2, D2, F2. + +TAS *** +This opcode ANDs the contents of the A and X registers (without changing +the contents of either register) and transfers the result to the stack +pointer. It then ANDs that result with the contents of the high byte of +the target address of the operand +1 and stores that final result in +memory. + +One supported mode: + +TAS abcd,Y ;9B cd ab ;No. Cycles= 5 + +(Sub-instructions: STA, TXS) + +Here is an example of how you might use this opcode: + +TAS $7700,Y ;9B 00 77 + +Here is the same code using equivalent instructions. + +STX $02 +PHA +AND $02 +TAX +TXS +AND #$78 +STA $7700,Y +PLA +LDX $02 + +Note: Memory location $02 would not be altered by the TAS opcode. + +Above I used the phrase 'the high byte of the target address of the operand ++1'. By the words target address, I mean the unindexed address, the one +specified explicitly in the operand. The high byte is then the second byte +after the opcode (ab). So we'll shorten that phrase to AB+1. + +SAY *** +This opcode ANDs the contents of the Y register with and stores the +result in memory. + +One supported mode: + +SAY abcd,X ;9C cd ab ;No. Cycles= 5 + +Example: + +SAY $7700,X ;9C 00 77 + +Equivalent instructions: + +PHA +TYA +AND #$78 +STA $7700,X +PLA + +XAS *** +This opcode ANDs the contents of the X register with and stores the +result in memory. + +One supported mode: + +XAS abcd,Y ;9E cd ab ;No. Cycles= 5 + +Example: + +XAS $6430,Y ;9E 30 64 + +Equivalent instructions: + +PHA +TXA +AND #$65 +STA $6430,Y +PLA + +AXA *** +This opcode stores the result of A AND X AND the high byte of the target +address of the operand +1 in memory. + +Supported modes: + +AXA abcd,Y ;9F cd ab ;No. Cycles= 5 +AXA (ab),Y ;93 ab ; 6 + +Example: + +AXA $7133,Y ;9F 33 71 + +Equivalent instructions: + +STX $02 +PHA +AND $02 +AND #$72 +STA $7133,Y +PLA +LDX $02 + +Note: Memory location $02 would not be altered by the AXA opcode. + + +The following notes apply to the above four opcodes: TAS, SAY, XAS, AXA. + +None of these opcodes affect the accumulator, the X register, the Y +register, or the processor status register! + The author has no explanation for the complexity of these +instructions. It is hard to comprehend how the microprocessor could handle +the convoluted sequence of events which appears to occur while executing +one of these opcodes. A partial explanation for what is going on is that +these instructions appear to be corruptions of other instructions. For +example, the opcode SAY would have been one of the addressing modes of the +standard instruction STY (absolute indexed X) were it not for the fact that +the normal operation of this instruction is impaired in this particular +instance. + +One irregularity uncovered is that sometimes the actual value is stored in +memory, and the AND with part drops off (ex. SAY becomes true STY). +This happens very infrequently. The behaviour appears to be connected with +the video display. For example, it never seems to occur if either the +screen is blanked or C128 2MHz mode is enabled. + +--- Imported example --- +Here is a demo program to illustrate the above effect. SYS 8200 to try it. +There is no exit, so you'll have to hit Stop-Restore to quit. And you may +want to clear the screen before running it. For contrast, there is a +second routine which runs during idle state display. Use SYS 8211 for it. +After trying the second routine, check it out again using POKE 53269,255 to +enable sprites. + +begin 640 say->sty +D"""B`*`@G``%Z$P,("P1T##[+!'0$/NB`*`@G``%Z-#Z3!,@ +` +end + +--- Text import end --- + +WARNING: If the target address crosses a page boundary because of indexing, +the instruction may not store at the intended address. It may end up +storing in zero page, or another address altogether (page=value stored). +Apparently certain internal 65XX registers are being overridden. The whole +scheme behind this erratic behaviour is very complex and strange. + + +And continuing with the list... + +ANC *** +ANC ANDs the contents of the A register with an immediate value and then +moves bit 7 of A into the Carry flag. This opcode works basically +identically to AND #immed. except that the Carry flag is set to the same +state that the Negative flag is set to. + +One supported mode: + +ANC #ab ;2B ab ;No. Cycles= 2 +ANC #ab ;0B ab + +(Sub-instructions: AND, ROL) + +OPCODE 89 +Opcode 89 is another SKB instruction. It requires 2 cycles to execute. + +LAS *** +This opcode ANDs the contents of a memory location with the contents of the +stack pointer register and stores the result in the accumulator, the X +register, and the stack pointer. Affected flags: N Z. + +One supported mode: + +LAS abcd,Y ;BB cd ab ;No. Cycles= 4* + +OPCODE EB +Opcode EB seems to work exactly like SBC #immediate. Takes 2 cycles. + +That is the end of the list. + +This list is a full and complete list of all undocumented opcodes, every +last hex value. It provides complete and thorough information and it also +corrects some incorrect information found elsewhere. The opcodes MKA and +MKX (also known as TSTA and TSTX) as described in "The Complete Commodore +Inner Space Anthology" do not exist. Also, it is erroneously indicated +there that the instructions ASO, RLA, LSE, RRA have an immediate addressing +mode. (RLA #ab would be ANC #ab.) + +[Recent additions to this text file] + +Here are some other more scrutinizing observations. + +The opcode ARR operates more complexily than actually described in the list +above. Here is a brief rundown on this. The following assumes the decimal +flag is clear. You see, the sub-instruction for ARR ($6B) is in fact ADC +($69), not AND. While ADC is not performed, some of the ADC mechanics are +evident. Like ADC, ARR affects the overflow flag. The following effects +occur after ANDing but before RORing. The V flag is set to the result of +exclusive ORing bit 7 with bit 6. Unlike ROR, bit 0 does not go into the +carry flag. The state of bit 7 is exchanged with the carry flag. Bit 0 is +lost. All of this may appear strange, but it makes sense if you consider +the probable internal operations of ADC itself. + +SKB opcodes 82, C2, E2 may be HLTs. Since only one source claims this, and +no other sources corroborate this, it must be true on very few machines. +On all others, these opcodes always perform no operation. + +LAS is suspect. This opcode is possibly unreliable. + +OPCODE BIT-PATTERN: 10x0 1011 +Now it is time to discuss XAA ($8B) and OAL ($AB). A fair bit of +controversy has surrounded these two opcodes. There are two good reasons +for this. 1 - They are rather weird in operation. 2 - They do operate +differently on different machines. Highly variable. + +Here is the basic operation. +OAL +This opcode ORs the A register with #xx, ANDs the result with an immediate +value, and then stores the result in both A and X. + +On my 128, xx may be EE,EF,FE, OR FF. These possibilities appear to depend +on three factors: the X register, PC, and the previous instruction +executed. Bit 0 is ORed from x, and also from PCH. As for XAA, on my 128 +this opcode appears to work exactly as described in the list. + +On my 64, OAL produces all sorts of values for xx: 00,04,06,80, etc... A +rough scenario I worked out to explain this is here. The constant value EE +disappears entirely. Instead of ORing with EE, the accumulator is ORed +with certain bits of X and also ORed with certain bits of another +"register" (nature unknown, whether it be the data bus, or something else). +However, if OAL is preceded by certain other instructions like NOP, the +constant value EE reappears and the foregoing does not take place. + +On my 64, XAA works like this. While X is transfered to A, bit 0 and bit 4 +are not. Instead, these bits are ANDed with those bits from A, and the +result is stored in A. + +There may be many variations in the behaviour of both opcodes. XAA #$00 or +OAL #$00 are likely quite reliable in any case. It seems clear that the +video chip (i.e., VIC-II) bears responsibility for some small part of the +anomalousness, at least. Beyond that, the issue is unclear. + +One idea I'll just throw up in the air about why the two opcodes behave as +they do is this observation. While other opcodes like 4B and 6B perform +AND as their first step, 8B and AB do not. Perhaps this difference leads +to some internal conflict in the microprocessor. Besides being subject to +"noise", the actual base operations do not vary. + +All of the opcodes in this list (at least up to the dividing line) use the +naming convention from the CCISA Anthology book. There is another naming +convention used, for example in the first issue of C=Hacking. The only +assembler I know of that supports undocumented opcodes is Power Assembler. +And it uses the same naming conventions as used here. + +One note on a different topic. A small error has been pointed out in the +64 Programmers Reference Guide with the instruction set listing. In the +last row, in the last column of the two instructions AND and ORA there +should be an asterisk, just as there is with ADC. That is the indirect,Y +addressing mode. In another table several pages later correct information +is given. + +(A correction: There was one error in this document originally. One +addressing mode for LAX was given as LAX ab,X. This should have been +LAX ab,Y (B7). Also note that Power Assembler apparently has this same +error, likely because both it and this document derive first from the same +source as regards these opcodes. Coding LAX $00,X is accepted and +produces the output B7 00.) + +References + +o Joel Shepherd. "Extra Instructions" COMPUTE!, October 1983. + +o Jim Butterfield. "Strange Opcodes" COMPUTE, March 1993. + +o Raymond Quirling. "6510 Opcodes" The Transactor, March 1986. + +o John West, Marko Mäkelä. '64doc' file, 1994/06/03. diff --git a/ICs/6502 CPU/6502.org Tutorials - Investigating Interrupts.pdf b/ICs/6502 CPU/6502.org Tutorials - Investigating Interrupts.pdf new file mode 100755 index 0000000..84f1c0f Binary files /dev/null and b/ICs/6502 CPU/6502.org Tutorials - Investigating Interrupts.pdf differ diff --git a/ICs/6502 CPU/MCS6500 Microcomputer Family Hardware Manual (1976).pdf b/ICs/6502 CPU/MCS6500 Microcomputer Family Hardware Manual (1976).pdf new file mode 100755 index 0000000..87869ed Binary files /dev/null and b/ICs/6502 CPU/MCS6500 Microcomputer Family Hardware Manual (1976).pdf differ diff --git a/ICs/6502 CPU/cmd_g65scxxx_mpu_family.pdf b/ICs/6502 CPU/cmd_g65scxxx_mpu_family.pdf new file mode 100755 index 0000000..f990abc Binary files /dev/null and b/ICs/6502 CPU/cmd_g65scxxx_mpu_family.pdf differ diff --git a/ICs/6502 CPU/synertek_hardware_manual.pdf b/ICs/6502 CPU/synertek_hardware_manual.pdf new file mode 100755 index 0000000..2ce3b79 Binary files /dev/null and b/ICs/6502 CPU/synertek_hardware_manual.pdf differ diff --git a/ICs/6502 CPU/synertek_programming_manual.pdf b/ICs/6502 CPU/synertek_programming_manual.pdf new file mode 100755 index 0000000..8964cd0 Binary files /dev/null and b/ICs/6502 CPU/synertek_programming_manual.pdf differ diff --git a/ICs/6502 CPU/w65c02s.pdf b/ICs/6502 CPU/w65c02s.pdf new file mode 100755 index 0000000..32e8c5a Binary files /dev/null and b/ICs/6502 CPU/w65c02s.pdf differ diff --git a/ICs/6522 VIA/6522-VIA.txt b/ICs/6522 VIA/6522-VIA.txt new file mode 100755 index 0000000..66c20c8 --- /dev/null +++ b/ICs/6522 VIA/6522-VIA.txt @@ -0,0 +1,1315 @@ +This document covers all programming information about Rockwell R6522 +Versatile Interface Adapter (VIA) chip used in many Commodore devices. +Figures and tables in this file were drawn with +, -, | characters. +For clear description, some of the figures are bit wider than 80 characters. + +This file was created from scannings by Frank Kontros +Many thanks for corrections to Wolfgang Lorenz + +If you have any questions, comments or suggestions concerning this file or +6522 chip, please contact me (Frank). + + +------------------------------------------------------------------------------ + R6522 + VERSATILE INTERFACE + ADAPTER +------------------------------------------------------------------------------ + + +DESCRIPTION + +The R6522 Versatile Interface Adapter (VIA) is a very flexible I/O control +device. In addition, this device contains a pair of very powerful 16-bit +interval timers, a serial-to-parallel/parallel-to-serial shift register and +input data latching on the peripheral ports. Expanded handshaking capability +allows control of bidirectional data transfers between VIA's in multiple +processor systems. + +Control of peripheral devices is handled primarily through two 8-bit +bidirectional ports. Each line can be programmed as either an input or an +output. Several peripheral I/O lines can be controlled directly from the +interval timers for generating programmable frequency square waves or for +counting externally generated pulses. To facilitate control of the many +powerful features of this chip, an interrupt flag register, an interrupt +enable register and a pair of function control registers are provided. + + +FEATURES + +o Two 8-bit bidirectional I/O ports +o Two 16-bit programmable timer/counters +o Serial data port +o TTL compatible +o CMOS compatible peripheral control lines +o Expanded "handshake" capability allows positive control + data transfers between processor and peripheral devices +o Latched output and input registers +o 1 MHz and 2 Mhz operation +o Single +5V power supply + + + ORDERING INFORMATION +---------------+ + Vss =| 1 40 |= CA1 + PA0 =| 2 39 |= CA2 + Part Number: PA1 =| 3 38 |= RS0 + R6522 _ _ _ PA2 =| 4 37 |= RS1 + | | | PA3 =| 5 36 |= RS2 + | | | PA4 =| 6 35 |= RS3 + | | | PA5 =| 7 34 |= RES + | | | PA6 =| 8 33 |= D0 + | | | PA7 =| 9 32 |= D1 + | | +------ Temperature Range PB0 =| 10 31 |= D2 + | | Blank = 40øC to +70øC PB1 =| 11 30 |= D3 + | | E = 40øC to +85øC PB2 =| 12 29 |= D4 + | | PB3 =| 13 28 |= D5 + | | PB4 =| 14 27 |= D6 + | +-------- Package PB5 =| 15 26 |= D7 + | C = Ceramic PB6 =| 16 25 |= 02 + | P = Plastic PB7 =| 17 24 |= CS1 + | CB1 =| 18 23 |= CS2 + | CB2 =| 19 22 |= R/W + +---------- Frequency Vcc =| 20 21 |= IRQ + No Letter = 1 MHz +---------------+ + A = 2 MHz R6522 Pin Configuration + + +INTERFACE SIGNALS + + +---------------+ + / | | \ + | /-------\ | | /-------\ | + M B | D0-D7 < 8 >| |< (8) > PA0-PA7 | + I U | \-------/ | | \-------/ | + C S | | | | P I + R | 02 ---------->| |<---------- CA1 | E N + R O I | _ | | | R T + 6 P N | R/W ---------->| R6522 |<---------> CA2 | I E + 5 R T < ___ 2 | VIA | > P R + 0 O E | CS1,CS2 -----/---->| |<---------> CB1 | H F + 0 C R | 4 | | | E A + E F | RS0-RS3 -----/---->| |<---------> CB2 | R C + S A | ___ | | | A E + S C | RES ---------->| | /-------\ | L + O E | ___ | |< (8) > PB0-PB7 | + R | IRQ ---------->| | \-------/ | + \ | | / + +---------------+ + + Figure 1. R6522 VIA interface Signals + + ___ +RESET (RES) + ___ +A low reset (RES) input clears all R6522 internal registers to logic 0 +(except T1 and T2 latches and counters and the Shift Register). This +places all peripheral interface lines in the input state, disables the +timers, shift register, etc. and disables interrupting from the chip. + +INPUT CLOCK (PHASE 2) + +The input clock is the system 02 clock and triggers all data transfers +between processor bus and the R6522. + _ +READ/WRITE (R/W) + +The direction of the data transfers between the R6522 and the system processor +is controlled by the R/W line in conjunction with the CS1 and CS2 inputs. When +R/W is low (write operation), and the R6522 is selected, data is transferred +from the processor bus into the selected R6522 register. When R/W is high +(read operation), and the R6522 is selected, data is transferred from the +selected R6522 register to the processor bus. + +DATA BUS (D0-D7) + +The eight bidirectional data bus lines transfer data between the R6522 and +the system processor bus. During read cycles, the contents of the selected +R6522 register are placed on the data bus lines. During write cycles, these +lines are high-impedance inputs and data is transferred from the processor +bus into the selected register. When the R6522 is not selected, the data +bus lines are high impedance. + ___ +CHIP SELECTS (CS1, CS2) + +The two chip select inputs are normally connected to processor address lines +either directly or through decoding. The selected R6522 register is accessed +when CS1 is high and CS2 is low. + +REGISTER SELECTS (RS0-RS3) + +The coding of the four Register Select inputs select one of the 16 internal +registers of the R6522, as shown in Table 1. + + + Table 1. R6522 Register Addressing + ++----+---------------+---------+---------------------------------------------+ +|Reg.| RS Coding |Register | Register/Description | +| # +---+---+---+---+ Desig. +----------------------+----------------------+ +| |RS3|RS2|RS1|RS0| | Write (R/W = L) | Read (R/W = H) | ++----+---+---+---+---+---------+----------------------+----------------------+ +| 0 | 0 | 0 | 0 | 0 | ORB/IRB | Output Register B | Input Register B | ++----+---+---+---+---+---------+----------------------+----------------------+ +| 1 | 0 | 0 | 0 | 1 | ORA/IRA | Output Register A | Input Register A | ++----+---+---+---+---+---------+----------------------+----------------------+ +| 2 | 0 | 0 | 1 | 0 | DDRB | Data Direction Register B | ++----+---+---+---+---+---------+---------------------------------------------+ +| 3 | 0 | 0 | 1 | 1 | DDRA | Data Direction Register A | ++----+---+---+---+---+---------+----------------------+----------------------+ +| 4 | 0 | 1 | 0 | 0 | T1C-L | T1 Low-Order Latches | T1 Low-Order Counter | ++----+---+---+---+---+---------+----------------------+----------------------+ +| 5 | 0 | 1 | 0 | 1 | T1C-H | T1 High-Order Counter| T1 High-Order Counter| ++----+---+---+---+---+---------+---------------------------------------------+ +| 6 | 0 | 1 | 1 | 0 | T1L-L | T1 Low-Order Latches | ++----+---+---+---+---+---------+---------------------------------------------+ +| 7 | 0 | 1 | 1 | 1 | T1L-H | T1 High-Order Latches | ++----+---+---+---+---+---------+----------------------+----------------------+ +| 8 | 1 | 0 | 0 | 0 | T2C-L | T2 Low-Order Latches | T2 Low-Order Counter | ++----+---+---+---+---+---------+----------------------+----------------------+ +| 9 | 1 | 0 | 0 | 1 | T2C-H | T2 High-Order Counter | ++----+---+---+---+---+---------+---------------------------------------------+ +| 10 | 1 | 0 | 1 | 0 | SR | Shift Register | ++----+---+---+---+---+---------+---------------------------------------------+ +| 11 | 1 | 0 | 1 | 1 | ACR | Auxiliary Control Register | ++----+---+---+---+---+---------+---------------------------------------------+ +| 12 | 1 | 1 | 0 | 0 | PCR | Peripheral Control Register | ++----+---+---+---+---+---------+---------------------------------------------+ +| 13 | 1 | 1 | 0 | 1 | IFR | Interrupt Flag Register | ++----+---+---+---+---+---------+---------------------------------------------+ +| 14 | 1 | 1 | 1 | 0 | IER | Interrupt Enable Register | ++----+---+---+---+---+---------+----------------------+----------------------+ +| 15 | 1 | 1 | 1 | 1 | ORA/IRA | Output Register A* | Input Register A* | ++----+---+---+---+---+---------+----------------------+----------------------+ +| NOTE: * Same as Register 1 except no handshake. | ++----------------------------------------------------------------------------+ + + ___ +INTERRUPT REQUEST (IRQ) + +The Interrupt Request output goes low whenever an internal interrupt flag is +set and the corresponding interrupt enable bit is a logic 1. This output is +open-drain to allow the interrupt request signal to be wire-OR'ed with other +equivalent signals in the system. + +PERIPHERAL PORT A (PA0-PA7) + +Port A consists of eight lines which can be individually programmed to act +as inputs or outputs under control of a Data Direction Register A. The +polarity of output pins is controlled by an Output Register and input data +may be latched into an internal register under control of the CA1 line. All +of these modes of operation are controlled by the system processor through +the internal control registers. These lines represents one standard TTL +load in the input mode and will drive one standard TTL load in the output +mode. Figure 2 illustrates the output circuit. + + + +5V + o + | + > + < + > + < + | + *-----*---> PA0-PA7, + | | CA2 + +-----+ +--+ | + I/O CONTROL ----+ | || | + | NOR |o----+| | + OUTPUT DATA ----+ | || | + +-----+ +--+ | + __|__ | + --- | + ~ | + INPUT DATA <-------------------------+ + + Figure 2. Port A Output Circuit + + +PORT A CONTROL LINES (CA1,CA2) + +The two Port A control lines act as interrupt inputs or as handshake +outputs. Each line controls an internal interrupt flag with a corresponding +interrupt enable bit. In addition, CA1 controls the latching of data on +Port A input lines. CA1 is a high-impedance input only while CA2 represents +one standard TTL load in the input mode. CA2 will drive one standard TTL +load in the output mode. + +PORT B (PB0-PB7) + +Peripheral Port B consists of eight bi-directional lines which are +controlled by an output register and a data direction register in much the +same manner as the Port A. In addition, the polarity of the PB7 output +signal can be controlled by one of the interval timers while the second +timer can be programmed to count pulses on the PB6 pin. Port B lines +represent one standard TTL load in the input mode and will drive one +standard TTL load in the output mode. In addition, they are capable of +sourcing 1.0 mA at 1.5 Vdc in the output mode to allow the outputs to +directly drive Darlington transistor circuits. Figure 3 is the circuit +schematic. + + +5V + o + | + *------+ + | | + INPUT +-----+ +--+ > + OUTPUT -------------*---+ | || < + CONTROL |\ | | NOR |o----+| > + +--o| >---+---+ | || < + | |/ | +-----+ +--+ | + | | | | + | | *------*---> PB0-PB7, + | | | | CB1,CB2 + | | +-----+ +--+ | + | +---+ | || | + OUTPUT | | NOR |o----+| | + DATA ---*-------------+ | || | + +-----+ +--+ | + __|__ | + --- | + ~ | + INPUT DATA <---------------------------------------+ + + Figure 3. Port B Output Circuit + + +PORT B CONTROL LINES (CB1,CB2) + +The Port B control lines act as interrupt inputs or as handshake outputs. +As with CA1 and CA2, each line controls an interrupt flag with a +corresponding interrupt enable bit. In addition, these lines act as a +serial port under control of the Shift Register. These lines represent one +standard TTL load in the input mode and will drive one standard TTL load in +the output mode. CB2 can also drive a Darlington transistor circuit; +however, CB1 cannot. + + +FUNCTIONAL DESCRIPTION + +The internal organization of the R6522 VIA is illustrated in Figure 4. + + + INTERRUPT ___ + CONTROL +----------------------------------> IRQ + +------------+ | +-----------+ +-------+ + | FLAGS | | |INPUT LATCH| | | + | (IFR) | | | (IRA) | | | P + +--\+------------+ | +-----------+ | | O + | +/| ENABLE +-+ +--\| OUTPUT |/--\|BUFFERS|/--\ R + +-------+ | | | (IER) | | +/| (ORA) |\--/| (PA) |\--/ T + | | | | +------------+ | | +-----------+ | | +DATA /--\| DATA +-+ +-------------------+ | | DATA DIR | | | A +BUS \--/| BUS +-+ +-------------------+ | | (DDRA) | | | + |BUFFERS| | | +------------+ | | +-----------+ +-------+ + | | | | | PERIPHERAL | | |PORT A REGISTER + +-------+ | | | (PCR) | | | + | +\+------------+ | | +-----------+<--------------- CA1 + | +/| AUXILIARY | | +\| PORT A |<--------------> CA2 + | | | (ACR) | | +/+-----------+ + | | +------------+ | | | PORT B |<--------+ + | | FUNCTION | | +-----------+<------+ | + | | CONTROL | | HANDSHAKE | | + | | +-------+-------+ | | CONTROL | | +___ +-------+ | | | LATCH | LATCH | | | +-----------+ | | +RES ---->| | | | |(T1L-H)|(T1L-L)| | +\| SHIFT REG |<------+-*-----> CB1 + _ | | | +\+-------+-------+ | +/| (SR) |<------*-------> CB2 +R/W ---->| | | +/|COUNTER|COUNTER| | | +-----------+ +02 ---->| | | | |(T1C-H)|(T1C-L)| | | +___ | CHIP | | | +-------+-------+ | |PORT B REGISTER +CS2 ---->| ACCESS| | | TIMER 1 | | +-----------+ +-------+ +CS1 ---->|CONTROL| | | +-------+ | | |INPUT LATCH| | | + | | | | | LATCH | | | | (IRB) | | | P +RS0 ---->| | | | |(T2L-L)| | | +-----------+ | | O +RS1 ---->| | | | +-------+-------+ | +\| OUTPUT |/--\|BUFFERS|/--\ R +RS2 ---->| | | +\|COUNTER|COUNTER| +--/| (ORB) |\--/| (PB) |\--/ T +RS3 ---->| | +--/|(T2C-H)|(T2C-L)| +-----------+ | | + +-------+ +-------+-------+ | DATA DIR | | | B + TIMER 2 | (DDRB) | | | + +-----------+ +-------+ + + Figure 4. R6522 VIA Block Diagram + + +PORT A AND PORT B OPERATION + +The R6522 VIA has two 8-bit bidirectional I/O ports (Port A and Port B) +and each port has two associated control lines. + +Each 8-bit peripheral port has a Data Direction Register (DDRA, DDRB) for +specifying whether the peripheral pins are to act as inputs or outputs. A 0 +in a bit of the Data Direction Register causes the corresponding peripheral +pin to act as an input. A 1 causes the pin to act as an output. + +Each peripheral pin is also controlled by a bit in the Output Register +(ORA, ORB) and the Input Register (IRA, IRB). When the pin is programmed as +an output, the voltage on the pin is controlled by the corresponding bit of +the Output Register. A 1 in the Output Register causes the output to go +high, and a 0 causes the output to go low. Data may be written into Output +Register bits corresponding to pins which are programmed as inputs. In this +case, however, the output signal is unaffected. + +Reading a peripheral port causes the contents of the Input Register (IRA, +IRB) to be transferred onto the Data Bus. With input latching disabled, IRA +will always reflect the levels on the PA pins. With input latching enabled, +IRA will reflect the levels on the PA pins at time the latching occurred +(via CA1). + +The IRB register operates similar to the IRA register. However, for pins +programmed as outputs there is a difference. When reading IRA, the level on +the pin determines whether a 0 or a 1 is sensed. When reading IRB, however, +the bit stored in the output register, ORB, is the bit sensed. Thus, for +outputs which have large loading effects and which pull an output "1" down +or which pull an output "0" up, reading IRA may result in reading a "0" +when a "1" was actually programmed, and reading a "1" when a "0" was +programmed. Reading IRB, on the other hand, will read the "1" or "0" level +actually programmed, no matter what the loading on the pin. + +Figures 5 through 8 illustrate the formats of the port registers. In +addition, the input latching modes are selected by the Auxiliary Control +Register (Figure 12). + + + REG 0 -- ORB/IRB + +---+---+---+---+---+---+---+---+ + | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ -+ + | | | | | | | +----- PB0 | + | | | | | | | | + | | | | | | +--------- PB1 | + | | | | | | | + | | | | | +------------- PB2 | OUTPUT REGISTER + | | | | | | "B" (ORB) + | | | | +----------------- PB3 | + | | | | +- OR + | | | +--------------------- PB4 | + | | | | INPUT REGISTER + | | +------------------------- PB5 | "B" (IRB) + | | | + | +----------------------------- PB6 | + | | + +--------------------------------- PB7 | + -+ + ++-----------------------+-----------------------+---------------------------+ +| PIN | | | +| DATA DIRECTION | WRITE | READ | +| SELECTION | | | ++-----------------------+-----------------------+---------------------------+ +|DDRB = 1 OUTPUT |MPU WRITES OUTPUT LEVEL|MPU READS OUTPUT REGISTER | +| |ORB |BIT, ORB PIN LEVEL HAS NO | +| | |AFFECT | ++-----------------------+-----------------------+---------------------------+ +|DDRB = 0 INPUT |MPU WRITES INTO ORB BUT|MPU READS INPUT LEVEL ON PB| +|INPUT LATCHING DISABLED|NO AFFECT ON PIN LEVEL |PIN | +| |UNTIL DDRB CHANGED | | ++-----------------------+ +---------------------------+ +|DDRB = 0 INPUT | |MPU READS IRB BIT WHICH IS | +|INPUT LATCHING ENABLED | |THE LEVEL OF THE PB PIN AT | +| | |THE TIME OF THE LAST CB1 | +| | |ACTIVE TRANSITION | ++-----------------------+-----------------------+---------------------------+ + + Figure 5. Output Register B (ORB), Input Register B (IRB) + + + REG 1 -- ORA/IRA + +---+---+---+---+---+---+---+---+ + | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ -+ + | | | | | | | +----- PA0 | + | | | | | | | | + | | | | | | +--------- PA1 | + | | | | | | | + | | | | | +------------- PA2 | OUTPUT REGISTER + | | | | | | "A" (ORA) + | | | | +----------------- PA3 | + | | | | +- OR + | | | +--------------------- PA4 | + | | | | INPUT REGISTER + | | +------------------------- PA5 | "A" (IRA) + | | | + | +----------------------------- PA6 | + | | + +--------------------------------- PA7 | + -+ ++-----------------------+-----------------------+---------------------------+ +| PIN | | | +| DATA DIRECTION | WRITE | READ | +| SELECTION | | | ++-----------------------+-----------------------+---------------------------+ +|DDRA = 1 OUTPUT |MPU WRITES OUTPUT LEVEL|MPU READS LEVEL ON PA PIN | +|INPUT LATCHING DISABLED|ORA | | ++-----------------------+ +---------------------------+ +|DDRA = 1 INPUT | |MPU READS IRA BIT WHICH IS | +|INPUT LATCHING ENABLED | |THE LEVEL OF THE PA PIN AT | +| | |THE TIME OF THE LAST CA1 | +| | |ACTIVE TRANSITION | ++-----------------------+-----------------------+---------------------------+ +|DDRA = 0 INPUT |MPU WRITES INTO ORA BUT|MPU READS LEVEL ON PA PIN | +|INPUT LATCHING DISABLED|NO AFFECT ON PIN LEVEL | | +| |UNTIL DDRA CHANGED | | ++-----------------------+ +---------------------------+ +|DDRA = 0 INPUT | |MPU READS IRA BIT WHICH IS | +|INPUT LATCHING ENABLED | |THE LEVEL OF THE PA PIN AT | +| | |THE TIME OF THE LAST CA1 | +| | |ACTIVE TRANSITION | ++-----------------------+-----------------------+---------------------------+ + + Figure 6. Output Register A (ORA), Input Register A (IRA) + + + REG 2 -- DDRB REG 3 -- DDRA + +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ + |7|6|5|4|3|2|1|0| |7|6|5|4|3|2|1|0| + +-+-+-+-+-+-+-+-+ -+ +-+-+-+-+-+-+-+-+ -+ + | | | | | | | +--- PB0 | | | | | | | | +--- PA0 | + | | | | | | +----- PB1 | | | | | | | +----- PA1 | + | | | | | +------- PB2 | DATA | | | | | +------- PA2 | DATA + | | | | +--------- PB3 |_ DIRECTION | | | | +--------- PA3 |_ DIRECTION + | | | +----------- PB4 | REGISTER | | | +----------- PA4 | REGISTER + | | +------------- PB5 | "B" (DDRB) | | +------------- PA5 | "A" (DDRA) + | +--------------- PB6 | | +--------------- PA6 | + +----------------- PB7 | +----------------- PA7 | + -+ -+ + + "0" ASSOCIATED PB PIN IS AN INPUT "0" ASSOCIATED PA PIN IS AN INPUT + (HIGH IMPEDANCE) (HIGH IMPEDANCE) + "1" ASSOCIATED PB PIN IS AN OUTPUT "1" ASSOCIATED PA PIN IS AN OUTPUT + WHOSE LEVEL IS DETERMINED BY WHOSE LEVEL IS DETERMINED BY + ORB REGISTER BIT ORA REGISTER BIT + + Figure 7. Data Direction Register B Figure 8. Data Direction Register A + (DDRB) (DDRA) + + + +HANDSHAKE CONTROL OF DATA TRANSFERS + +The R6522 allows positive control of data transfers between the system +processor and peripheral devices through the operation of "handshake" lines. +Port A lines (CA1, CA2) handshake data on both a read and a write operation +while the Port B lines (CB1, CB2) handshake on a write operation only. + +READ HANDSHAKE + +Positive control of data transfers from peripheral devices into the system +processor can be accomplished very effectively using Read Handshaking. In +this case, the peripheral device must generate the equivalent of a "Data +Ready" signal to the processor signifying that valid data is present on the +peripheral port. This signal normally interrupts the processor, which then +reads the data, causing generation of a "Data Taken" signal. The peripheral +device responds by making new data available. This process continues until +the data transfer is complete. + +In the R6522, automatic "Read Handshaking" is possible on the Peripheral A +Port only. The CA1 interrupt input pin accepts the "Data Ready" signal and +CA2 generates the "Data Taken" signal. The "Data Ready" signal will set an +internal flag which may interrupt the processor or which may be polled +under program control. The "Data Taken" signal can either be a pulse or a +level which is set low by the system processor and is cleared by the "Data +Ready" signal. These options are shown in Figure 9 which illustrates the +normal Read Handshake sequence. + + + +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ + 02 --+ +-+ +-+ +-+ +-#-+ +-+ +-+ +-+ +-+ +-#-+ +-+ +-+ +- + | | + "DATA READY" ---------+ +----#-------+-------------#------+ + CA1) +---+----#-------+ | | +------ + ___ | | | | + IRQ OUTPUT ---------+ +---------#------+ + +--------#-----------+ | +------ + READ IRA +---+ | | + OPERATION ------------------#-------+ +---------#------------- + | | | + "DATA TAKEN" ------------------------------+ | +------ + HANDSHAKE MODE +---------#------+ + (CA2) | | + | | + "DATA TAKEN" ------------------#-----------+ +-----#------------- + PULSE MODE +---+ + (CA2) + + Figure 9. Read Handshake Timing (Port A, Only) + + +WRITE HANDSHAKE + +The sequence of operations which allows handshaking data from the system +processor to a peripheral device is very similar to that described for Read +Handshaking. However, for Write Handshaking, the R6522 generates the "Data +Ready" signal and the peripheral device must respond with the "Data Taken" +signal. This can be accomplished on both the PA port and the PB port on the +R6522. CA2 or CB2 act as a "Data Ready" output in either the handshake mode +or pulse mode and CA1 or CB1 accept the "Data Taken" signal from the +peripheral device, setting the interrupt flag and cleaning the "Data Ready" +output. This sequence is shown in Figure 10. + + + +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ + 02 --+ +-+ +-+ +-+ +-#-+ +-+ +-+ +-+ +-+ +-#-+ +-+ +-+ +- + | | | | + +---+ +---+ + WRITE ORA,ORB ----+ +---------#---------------------#---+ +----- + OPERATION | + | + "DATA READY" ----------+ +----------------------+ + HANDSHAKE MODE +-------#--------+ | +--- + (CA2,CB2) | | | + | | | + "DATA READY" ----------+ +---#---------------------#---------+ + PULSE MODE +---+ | | +--- + (CA2,CB2) | | | + | | | + "DATA TAKEN" ---------------------------+ +--------#---+--------- + (CA1,CB1) +---+--------#---+ | + ___ | | + IRQ OUTPUT ------------------#--------+ +--- + +------------#---------+ + + Figure 10. Write Handshake Timing + + +Selection of operating modes for CA1, CA2, CB1 and CB2 is accomplished by +the Peripheral Control Register (Figure 11). + + + REG 12 -- PERIPHERAL CONTROL REGISTER + +---+---+---+---+---+---+---+---+ + | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | + +---+---+---+---+---+---+---+---+ + | | | | | | + +----+----+ | +----+----+ | + | | | | + CB2 CONTROL -----+ | | +- CA1 INTERRUPT CONTROL ++-+-+-+------------------------+ | | +--------------------------+ +|7|6|5| OPERATION | | | | 0 = NEGATIVE ACTIVE EDGE | ++-+-+-+------------------------+ | | | 1 = POSITIVE ACTIVE EDGE | +|0|0|0| INPUT NEG. ACTIVE EDGE | | | +--------------------------+ ++-+-+-+------------------------+ | +---- CA2 INTERRUPT CONTROL +|0|0|1| INDEPENDENT INTERRUPT | | +-+-+-+------------------------+ +| | | | INPUT NEGATIVE EDGE | | |3|2|1| OPERATION | ++-+-+-+------------------------+ | +-+-+-+------------------------+ +|0|1|0| INPUT POS. ACTIVE EDGE | | |0|0|0| INPUT NEG. ACTIVE EDGE | ++-+-+-+------------------------+ | +-+-+-+------------------------+ +|0|1|1| INDEPENDENT INTERRUPT | | |0|0|1| INDEPENDENT INTERRUPT | +| | | | INPUT POSITIVE EDGE | | | | | | INPUT NEGATIVE EDGE | ++-+-+-+------------------------+ | +-+-+-+------------------------+ +|1|0|0| HANDSHAKE OUTPUT | | |0|1|0| INPUT POS. ACTIVE EDGE | ++-+-+-+------------------------+ | +-+-+-+------------------------+ +|1|0|1| PULSE OUTPUT | | |0|1|1| INDEPENDENT INTERRUPT | ++-+-+-+------------------------+ | | | | | INPUT POSITIVE EDGE | +|1|1|0| LOW OUTPUT | | +-+-+-+------------------------+ ++-+-+-+------------------------+ | |1|0|0| HANDSHAKE OUTPUT | +|1|1|1| HIGH OUTPUT | | +-+-+-+------------------------+ ++-+-+-+------------------------+ | |1|0|1| PULSE OUTPUT | + CB1 INTERRUPT CONTROL --------+ +-+-+-+------------------------+ ++--------------------------+ |1|1|0| LOW OUTPUT | +| 0 = NEGATIVE ACTIVE EDGE | +-+-+-+------------------------+ +| 1 = POSITIVE ACTIVE EDGE | |1|1|1| HIGH OUTPUT | ++--------------------------+ +-+-+-+------------------------+ + + Figure 11. Peripheral Control Register (PCR) + + +COUNTERS/TIMERS + +There are two independent 16-bit-counter/timers (called Timer 1 and Timer +2) in the R6522. Each timer is controlled by writing bits into the Auxiliary +Control Register (ACR) to select this mode of operation (Figure 12). + + + REG 11 -- AUXILIARY CONTROL REGISTER + +---+---+---+---+---+---+---+---+ + | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | + +---+---+---+---+---+---+---+---+ + | | | | | | | + +--+--+ | +----+----+ | +------ PA + | | | | + T1 TIMER CONTROL ---+ | | +---------- PB ++-+-+----------------+-------+ | | +|7|6|OPERATION | PB7 | | | LATCHING ENABLE/DISABLE ++-+-+----------------+-------+ | | +---------------------+ +|0|0|TIMED INTERRUPT | | | | | 0 = DISABLE LATCHING| +| | |EACH TIME T1 IS | | | | | 1 = ENABLE LATCHING | +| | |LOADED |DISABLE| | | +---------------------+ ++-+-+----------------+ | | | +|0|1|CONTINUOUS | | | | +| | |INTERRUPTS | | | +---- SHIFT REGISTER CONTROL ++-+-+----------------+-------+ | +-+-+-+-----------------------------------+ +|1|0|TIMED INTERRUPT |ONE- | | |4|3|2| OPERATION | +| | |EACH TIME T1 IS |SHOT | | +-+-+-+-----------------------------------+ +| | |LOADED |OUTPUT | | |0|0|0| DISABLED | ++-+-+----------------+-------+ | +-+-+-+-----------------------------------+ +|1|1|CONTINUOUS |SQUARE | | |0|0|1| SHIFT IN UNDER COMTROL OF T2 | +| | |INTERRUPTS |WAVE | | +-+-+-+-----------------------------------+ +| | | |OUTPUT | | |0|1|0| SHIFT IN UNDER CONTROL OF 02 | ++-+-+----------------+-------+ | +-+-+-+-----------------------------------+ + | |0|1|1| SHIFT IN UNDER CONTROL OF EXT.CLK | + T2 TIMER CONTROL ------------+ +-+-+-+-----------------------------------+ ++-+-----------------+ |1|0|0| SHIFT OUT FREE-RUNNING AT T2 RATE | +|5| OPERATION | +-+-+-+-----------------------------------+ ++-+-----------------+ |1|0|1| SHIFT OUT UNDER CONTROL OF T2 | +|0| TIMED INTERRUPT | +-+-+-+-----------------------------------+ ++-+-----------------+ |1|1|0| SHIFT OUT UNDER CONTROL OF 02 | +|1| COUNT DOWN WITH | +-+-+-+-----------------------------------+ +| | PULSES ON PB6 | |1|1|1| SHIFT OUT UNDER CONTROL OF EXT.CLK| ++-+-----------------+ +-+-+-+-----------------------------------+ + + Figure 12. Auxiliary Control Register (ACR) + + +Timer 1 Operation + +Interval Timer T1 consists of two 8-bit latches (Figure 13) and a 16-bit +counter (Figure 14). The latches store data which is to be loaded into the +counter. After loading, the counter decrements at 02 clock rate. Upon +reaching zero, an interrupt flag is set, and IRQ goes low if the T1 +interrupt is enabled. Timer 1 then disables any further interrupts or +automatically transfers the contents of the latches into the counter and +continues to decrement. In addition, the timer may be programmed to invert +the output signal on a peripheral pin (PB7) each time it "times-out". Each +of these modes is discussed separately below. + +Note that the processor does not write directly into the low-order counter +(T1C-L). Instead, this half of the counter is loaded automatically from the +low order latch (T1L-L) when the processor writes into the high order +counter (T1C-H). In fact, it may not be necessary to write to the low order +counter in some applications since the timing operation is triggered by +writing to the high order latch. + + + REG 6 -- T1 LOW-ORDER LATCH REG 7 -- T1 HIGH-ORDER LATCH + +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ + |7|6|5|4|3|2|1|0| |7|6|5|4|3|2|1|0| + +-+-+-+-+-+-+-+-+ -+ +-+-+-+-+-+-+-+-+ -+ + | | | | | | | +--- 1 | | | | | | | | +--- 256 | + | | | | | | +----- 2 | | | | | | | +----- 512 | + | | | | | +------- 4 | | | | | | +------- 1024 | + | | | | +--------- 8 |_ COUNT | | | | +--------- 2048 |_ COUNT + | | | +----------- 16 | VALUE | | | +----------- 4096 | VALUE + | | +------------- 32 | | | +------------- 8192 | + | +--------------- 64 | | +--------------- 16384 | + +----------------- 128 | +----------------- 32768 | + -+ -+ + + WRITE - 8 BITS LOADED INTO T1 WRITE - 8 BITS LOADED INTO T1 HIGH- + LOW-ORDER LATCHES. THIS ORDER LATCHES. UNLIKE REG 4 + OPERATION IS NO DIFFERENT OPERATION NO LATCH TO + THAN A WRITE INTO REG 4 COUNTER TRANSFERS TAKE PLACE + + READ - 8 BITS FROM T1 LOW ORDER- READ - 8 BITS FROM T1 HIGH-ORDER + LATCHES TRANSFERRED TO MPU. LATCHES TRANSFERRED TO MPU + UNLIKE REG 4 OPERATION, + THIS DOES NOT CAUSE RESET + OF T1 INTERRUPT FLAG + + Figure 13. Timer 1 (T1) Latch Registers + + + REG 4 -- T1 LOW-ORDER COUNTER REG 5 -- T1 HIGH-ORDER COUNTER + +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ + |7|6|5|4|3|2|1|0| |7|6|5|4|3|2|1|0| + +-+-+-+-+-+-+-+-+ -+ +-+-+-+-+-+-+-+-+ -+ + | | | | | | | +--- 1 | | | | | | | | +--- 256 | + | | | | | | +----- 2 | | | | | | | +----- 512 | + | | | | | +------- 4 | | | | | | +------- 1024 | + | | | | +--------- 8 |_ COUNT | | | | +--------- 2048 |_ COUNT + | | | +----------- 16 | VALUE | | | +----------- 4096 | VALUE + | | +------------- 32 | | | +------------- 8192 | + | +--------------- 64 | | +--------------- 16384 | + +----------------- 128 | +----------------- 32768 | + -+ -+ + + WRITE - 8 BITS LOADED INTO T1 WRITE - 8 BITS LOADED INTO T1 + LOW-ORDER LATCHES. LATCH HIGH-ORDER LATCHES. ALSO + CONTENTS ARE TRANSFERRED AT THIS TIME BOTH HIGH- AND + INTO LOW-ORDER COUNTER AT LOW-ORDER LATCHES TRANSFERRED + THE TIME THE HIGH-ORDER INTO T1 COUNTER. T1 INTERRUPT + COUNTER IS LOADED (REG 5) FLAG ALSO IS RESET + + READ - 8 BITS FROM T1 LOW-ORDER READ - 8 BITS FROM T1 HIGH-ORDER + COUNTER TRANSFERRED TO MPU. COUNTER TRANSFERRED TO MPU + IN ADDITION T1 INTERRUPT FLAG + IS RESET (BIT 6 IN INTERRUPT + FLAG REGISTER) + + Figure 14. Timer 1 (T1) Counter Registers + + +Timer 1 One-Shot Mode + +The Timer 1 one-shot mode generates a single interrupt for each timer load +operation. As with any interval timer, the delay between the "write T1C-H" +operation and generation of the processor interrupt is a direct function of +the data loaded into the timing counter. In addition to generating a single +interrupt, Timer 1 can be programmed to produce a single negative pulse on +the PB7 peripheral pin. With the output enabled (ACR7=1) a "write T1C-H" +operation will cause PB7 to go low. PB7 will return high when Timer 1 times +out. The result is a single programmable width pulse. + ___ +T1 interrupt flag will be set, the IRQ pin will go low (interrupt +enabled), and the signal on PB7 will go high. At this time the counter will +continue to decrement at system clock rate. This allows the system +processor to read the contents of the counter to determine the time since +interrupt. However, the T1 interrupt flag cannot be set again unless it has +been cleared as described in this specification. + +Timing for the R6522 interval timer one-shot mode is shown in Figure 15. + + + +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ + 02 --+ +-+ +-+ +-+ +-+ +-+ +-#-+ +-+ +-+ +-+ +-+ +-+ +- + | | | + +---+ | + WRITE T1C-H ----+ +-----------------#------------------------- + ___ | | + IRQ OUTPUT --------------------------#---------+ + | +--------------- + | | + PB7 OUTPUT --------+ +--------------- + +-----------------#---------+ + | N |N-1|N-2|N-3| | 0 |N| |N-1|N-2|N-3| + | | + |<---- N + 1.5 CYCLES ----->| + + Figure 15. Timer 1 One-Shot Mode Timing + + +In the one-shot mode, writing into the T1L-H has no effect on the +operation of Timer 1. However, it will be necessary to assure that the low +order latch contains the proper data before initiating the count-down with +a "write T1C-H" operation. When the processor writes into the high order +counter (T1C-H), the T1 interrupt flag will be cleared, the contents of the +low order latch will be transferred into the low order counter, and the +timer will begin to decrement at system clock rate. If the PB7 output is +enabled, this signal will go low on the 02 following the write operation. +When the counter reaches zero, the T1 interrupt flag will be set, the IRQ +pin will go low (interrupt enabled), and the signal on PB7 will go high. At +this time the counter will continue to decrement at system clock rate. This +allows the system processor to read the contents of the counter to +determine the time since interrupt. However, the T1 interrupt flag cannot +be set again unless it has been cleared as described in this specification. + +Timer 1 Free-Run Mode + +The most important advantage associated with the latches in T1 is the +ability to produce a continuous series of evenly spaced interrupts and the +ability to produce a square wave on PB7 whose frequency is not affected by +variations in the processor interrupt response time. This is accomplished +in the "free-running" mode. + +In the free-running mode, the interrupt flag is set and the signal on PB7 +is inverted each time the counter reaches zero. However, instead of +continuing to decrement from zero after a time-out, the timer automatically +transfers the contents of the latch into the counter (16 bits) and +continues to decrement from there. The interrupt flag can be cleared by +writing T1C-H, by reading T1C-L or by writing directly into the flag as +described later. However, it is not necessary to rewrite the timer to +enable setting the interrupt flag on the next time-out. + +All interval timers in the R6522 are "re-triggerable". Rewriting the +counter will always re-initialize the time-out period. In fact, the +time-out can be prevented completely if the processor continues to rewrite +the timer before it reaches zero. Timer 1 will operate in this manner if +the processor writes into the high order counter (T1C-H). However, by +loading the latches only, the processor can access the timer during each +down-counting operation without affecting the time-out in process. Instead, +the data loaded into the latches will determine the length of the next +time-out period. This capability is particularly valuable in the +free-running mode with the output enabled. In this mode, the signal on PB7 +is inverted and the interrupt flag is set with each time-out. By responding +to the interrupts with new data for the latches, the processor can +determine the period of the next half cycle during each half cycle of the +output signal on PB7. In this manner, very complex waveforms can be +generated. + +A precaution to take in the use of PB7 as the timer output concerns the +Data Direction Register contents for PB7. Both DDRB bit 7 and ACR bit 7 +must be 1 for PB7 to function as the timer output. If one is 1 and the +other is 0, then PB7 functions as a normal output pin, controlled by ORB +bit 7. + + +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ + 02 --+ +-+ +-+ +-#-+ +-+ +-+ +-+ +-+ +-#-+ +-+ +-+ +-+ +- + | | | + WRITE T1C-H +---+ | | + OPERATION ----+ +-----#---------------------#----------------- + ___ | | | + IRQ OUTPUT --------------#---------+ #---------+ + | +-----------# +------- + | | | + PB7 OUTPUT --------+ +-----------#---------+ + +-----#---------+ +------- + | | | + |< N+1.5 CYCLES>|<---- N+2 CYCLES --->| + + Figure 16. Timer 1 Free-Run Mode Timing + + +Timer 2 Operation + +Timer 2 operates as an interval timer (in the "one-shot" mode only), or as +a counter for counting negative pulses on the PB6 peripheral pin. A single +control bit in the Auxiliary Control Register selects between these two +modes. This timer is comprised of a "write-only" low-order latch (T2L-L), a +"read-only" low-order counter (T2C-L) and a read/write high order counter +(T2C-H). The counter registers act as a 16-bit counter which decrements at +02 rate. Figure 17 illustrates the T2 Latch/Counter Registers. + + + REG 8 - T2 LOW-ORDER LATCH/COUNTER REG 9 - T2 HIGH-ORDER COUNTER + +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ + |7|6|5|4|3|2|1|0| |7|6|5|4|3|2|1|0| + +-+-+-+-+-+-+-+-+ -+ +-+-+-+-+-+-+-+-+ -+ + | | | | | | | +--- 1 | | | | | | | | +--- 256 | + | | | | | | +----- 2 | | | | | | | +----- 512 | + | | | | | +------- 4 | | | | | | +------- 1024 | + | | | | +--------- 8 |_ COUNT | | | | +--------- 2048 |_ COUNT + | | | +----------- 16 | VALUE | | | +----------- 4096 | VALUE + | | +------------- 32 | | | +------------- 8192 | + | +--------------- 64 | | +--------------- 16384 | + +----------------- 128 | +----------------- 32768 | + -+ -+ + + + WRITE - 8 BITS LOADED INTO T2 WRITE - 8 BITS LOADED INTO T2 + LOW-ORDER LATCH HIGH-ORDER COUNTER. ALSO, + LOW-ORDER LATCH TRANSFERRED + READ - 8 BITS FROM T2 LOW-ORDER TO LOW-ORDER COUNTER. IN + COUNTER TRANSFERRED TO MPU. ADDITION T2 INTERRUPT FLAG + T2 INTERRUPT FLAG IS RESET IS RESET + + READ - 8 BITS FROM T2 HIGH-ORDER + COUNTER TRANSFERRED TO MPU + + Figure 17. Timer 2 (T2) Latch/Counter Registers + + +Timer 2 One-Shot Mode + +As an interval timer, T2 operates in the "one-shot" mode similar to Timer 1. +In this mode, T2 provides a single interrupt for each "write T2C-H" +operation. After timing out, the counter will continue to decrement. +However, setting of the interrupt flag is disabled after initial time-out +so that it will not be set by the counter decrementing again through zero. +The processor must rewrite T2C-H to enable setting of the interrupt flag. +The interrupt flag is cleared by reading T2C-L or by writing T2C-H. Timing +for this operation is shown in Figure 18. + + + +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ + 02 --+ +-+ +-+ +-+ +-+ +-+ +-#-+ +-+ +-+ +-+ +-+ +-+ +- + | | | + +---+ | + WRITE T2C-H ----+ +-----------------#------------------------- + ___ | | + IRQ OUTPUT --------------------------#---------+ + | +--------------- + | | + | N |N-1|N-2|N-3| | 0 |N| |N-1|N-2|N-3| + |<------ N+1.5 CYCLES ----->| + + Figure 18. Timer 2 One-Shot Mode Timing + + +Timer 2 Pulse Counting Mode + +In the pulse counting mode, T2 counts a predetermined number of +negative-going pulses on PB6. This is accomplished by first loading a +number into Timer 2. Writing into T2C-H clears the interrupt flag and +allows the counter to decrement each time a pulse is applied to PB6. The +interrupt flag is set when T2 counts down past zero. The counter will then +continue to decrement with each pulse on PB6. However, it is necessary to +rewrite T2C-H to allow the interrupt flag to set on a subsequent time-out. +Timing for this mode is shown in Figure 19. The pulse must be low on the +leading edge of 02. + + + WRITE T2C-H +---+ + OPERATION ----+ +------------------------------------------------ + ------------------+ +-----+ +-----#-----+ +-----+ +------ + PB6 INPUT +-+ +-+ +-+ +-+ + ___ ------------------------------------------------+ + IRQ OUTPUT | | | +-------- + N | N-1 | N-2 1 | 0 | -1 + + Figure 19. Timer 2 Pulse Counting Mode + + +SHIFT REGISTER OPERATION + +The Shift Register (SR) performs serial data transfers into and out of the +CB2 pin under control of an internal modulo-8 counter. Shift pulses can be +applied to the CB1 pin from an external source or, with the proper mode +selection, shift pulses generated internally will appear on the CB1 pin for +controlling external devices. + +The control bits which select the various shift register operating modes +are located in the Auxiliary Control Register. Figure 20 illustrates the +configuration of the SR data bits and Figure 21 shows the SR control bits +of the ACR. + + + REG 10 -- SHIFT REGISTER REG 11 -- AUXILIARY CONTROL REGISTER + +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ + |7|6|5|4|3|2|1|0| |7|6|5|4|3|2|1|0| + +-+-+-+-+-+-+-+-+ -+ +-+-+-+-+-+-+-+-+ + | | | | | | | +---- | | | + | | | | | | +------ | +-+-+ + | | | | | +-------- | SHIFT | + | | | | +---------- |_ REGISTER | SHIFT REGISTER + | | | +------------ | BITS +- MODE CONTROL + | | +-------------- | +-+-+-+---------------------------------+ + | +---------------- | |4|3|2|OPERATION | + +------------------ | +-+-+-+---------------------------------+ + -+ |0|0|0|DISABLED | + |0|0|1|SHIFT IN UNDER CONTROL OF T2 | + NOTES |0|1|0|SHIFT IN UNDER CONTROL OF 02 | + 1 WHEN SHIFTING OUT BIT 7 IS THE |0|1|1|SHIFT IN UNDER CONT. OF EXT.CLK | + FIRST BIT OUT AND SIMULTANEOUSLY |1|0|0|SHIFT OUT FREE RUNNING AT T2 RATE| + IS ROTATED BACK INTO BIT 0 |1|0|1|SHIFT OUT UNDER CONTROL OF T2 | + 2 WHEN SHIFTING IN BITS INITIALLY |1|1|0|SHIFT OUT UNDER CONTROL OF 02 | + ENTER BIT 0 AND ARE SHIFTED |1|1|1|SHIFT OUT UNDER CONT. OF EXT.CLK | + TOWARDS BIT 7 +-+-+-+---------------------------------+ + + Figure 20. Shift registers Figure 21. Shift Register Modes + + +SR Mode 0 -- Disabled + +Mode 0 disables the Shift Register. In this mode the microprocessor can +write or read the SR and the SR will shift on each CB1 positive edge +shifting in the value on CB2. In this mode the SR Interrupt Flag is +disabled (held to a logic 0). + + +SR Mode 1 -- Shift in Under Control of T2 + +In mode 1, the shifting rate is controlled by the low order 8 bits of T2 +(Figure 22). Shift pulses are generated on the CB1 pin to control shifting +in external devices. The time between transitions of this output clock is a +function of the system clock period and the contents of the low order T2 +latch (N). + + + 02 +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ + -+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +- +WRITE OR READ +---+ | | | | | +SHIFT REG ---+ +------------------------------------------------------#---------------------- + N+2 CYCLES |<--------->|<--------->| N+2 CYCLES | +CB1 OUTPUT -----------------+ 1 +-----------+ 2 +--------#--+ 8 +------- +SHIFT CLOCK +-----------+ +-----------+ +-----------+ | + | + CB2 INPUT -----------------------\/---1---\/-------------\/---2---\/----#--------\/---8---\/--- + DATA -----------------------/\-------/\-------------/\-------/\----#--------/\-------/\--- + | + ___ +-----------------------------------------------------------------------------+ + IRQ ---+ +--- + + Figure 22. SR Mode 1 -- Shift In Under T2 Control + + +The shifting operation is triggered by the read or write of the SR if the +SR flag is set in the IFR. Otherwise the first shift will occur at the next +time-out of T2 after a read or write of the SR. Data is shifted first into +the low order bit of SR and is then shifted into the next higher order bit +of the shift register on the negative-going edge of each clock pulse. The +input data should change before the positive-going edge of the CB1 clock +pulse. This data is shifted into shift register during the 02 clock cycle +following the positive-going edge of the CB1 clock pulse. After 8 CB1 clock +pulses, the shift register interrupt flag will set and IRQ will go low. + + +SR Mode 2 -- Shift in Under 02 Control + +In mode 2, the shift rate is a direct function of the system clock +frequency (Figure 23). CB1 becomes an output which generates shift pulses +for controlling external devices. Timer 2 operates as an independent +interval timer and has no effect on SR. The shifting operation is triggered +by reading or writing the Shift Register. Data is shifted, first into bit 0 +and is then shifted into the next higher order bit of the shift register on +the trailing edge of each 02 clock pulse. After 8 clock pulses, the shift +register interrupt flag will be set, and the output clock pulses on CB1 +will stop. + + + +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ + 02 -+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +- + +---+ | | | | + READ SR ---+ +----------------------------------------------------------------------------- + | | | | +CB1 OUTPUT -----------------+ +---+ +---+ +---+ +---+ +---+ +---+ +---+ +------- +SHIFT CLOCK +---+ +---+ +---+ +---+ +---+ +---+ +---+ +---+ | + | + CB2 INPUT -----------------\/---1--\/---2--\/---3--\/---4--\/---5--\/---6--\/---7--\/---8--\/-- + DATA -----------------/\------/\------/\------/\------/\------/\------/\------/\------/\-- + | + ___ ---------------------------------------------------------------------------------+ + IRQ +--- + + Figure 23. SR Mode 2 -- Shift In Under 02 Control + + +SR Mode 3 -- Shift in Under CB1 Control + +In mode 3, external pin CB1 becomes an input (Figure 24). This allows an +external device to load the shift register at its own pace. The shift +register counter will interrupt the processor each time 8 bits have been +shifted in. However, the shift register counter does not stop the shifting +operation; it acts simply as a pulse counter. Reading or writing the Shift +Register resets the Interrupt Flag and initializes the SR counter to count +another 8 pulses. + + + +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ + 02 -+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +- + | +CB1 OUTPUT ---+ 1 +---------+ 2 +--------#----+ 8 +------- +SHIFT CLOCK +---------+ +---------+ +---------+ + | + CB2 INPUT -------\/----1---\/--------\/----2---\/---#--------\/----8---\/-- + DATA -------/\--------/\--------/\--------/\---#--------/\--------/\-- + ___ | + IRQ -------------------------------------------------------------+ + +--- + + Figure 24. SR Mode 3 -- Shift In Under CB1 Control + + +Note that the data is shifted during the first system clock cycle +following the positive-going edge of the CB1 shift pulse. For this reason, +data must be held stable during the first full cycle following CB1 going +high. + + +SR Mode 4 -- Shift Out Under T2 Control (Free-Run) + +Mode 4 is very similar to mode 5 in which the shifting rate is set by T2. +However, in mode 4 the SR Counter does not stop the shifting operation +(Figure 25). Since the Shift Register bit 7 (SR7) is recirculated back into +bit 0, the 8 bits loaded into the Shift Register will be clocked onto CB2 +repetitively. In this mode the Shift Register Counter is disabled. + + + 02 +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ + -+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +- + +---+ | | | | | | +WRITE SR ---+ +---------------------------------------------------#--------------------------------------------- + N+2 CYCLES |<--------->|<--------->| N+2 CYCLES| | | +CB1 OUTPUT -----------------+ 1 +-----------+ 2 +-----#-----+ 8 +-----------+ 9 +--- +SHIFT CLOCK +-----------+ +-----------+ +-----------+ +-----------+ + +CB2 OUTPUT -------------------\/-----------1----------\/-------2------#-------\/-----------8----------\/-----1------ +DATA -------------------/\----------------------/\--------------#-------/\----------------------/\------------ + + Figure 25. SR Mode 4 -- Shift Out Under T2 Control (Free-Run) + + +SR Mode 5 -- Shift Out Under T2 Control + +In mode 5, the shift rate is controlled by T2 (as in mode 4). The shifting +operation is triggered by the read or write of the SR if the SR flag is set +in the IFR (Figure 26). Otherwise the first shift will occur at the next +time-out of T2 after a read or write of the SR. However, with each read or +write of the shift register the SR Counter is reset and 8 bits are shifted +onto CB2. At the same time, 8 shift pulses are generated on CB1 to control +shifting in external devices. After the 8 shift pulses, the shifting is +disabled, the SR Interrupt Flag is set and CB2 remains at the last data +level. + + + +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ + 02 + +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-#-+ +-+ +-+ +-+ +-+ + + +---+ | | | | | | + WRITE SR --+ +---------------------------------------------------------- + N+2 CYCLES |<----->|<----->| N+2 CYCLES | | + CB1 OUTPUT ----------------+ 1 +-------+ 2 +---#-----+ 8 +------ + SHIFT CLOCK +-------+ +-------+ +-------+ + | + CB2 OUTPUT --------------------\/------1------\/---2---#--------\/-----8---- + DATA --------------------/\-------------/\-------#--------/\---------- + ___ | + IRQ ----------------------------------------------------------+ + +------ + + Figure 26. SR Mode 5 -- Shift Out Under T2 Control + + +SR Mode 6 -- Shift Out Under 02 Control + +In mode 6, the shift rate is controlled by the 02 system clock (Figure 27). + + + +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-#-+ +-+ +-+ +-+ +-+ +-+ + 02 + +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ + + +---+ | | | | | | | | | | | | + WRITE SR --+ +---------------------------------------------------------- + | | | | | | | | | | | | + CB1 OUTPUT ------------+ 1 +---+ 2 +---+ 3 +---+ 4 +--#--+ 7 +---+ 8 +------ + SHIFT CLOCK +---+ +---+ +---+ +---+ +---+ +---+ + | | + CB2 OUTPUT -------------\/---1--\/---2--\/---3--\/--4-#---\/---7--\/---8---- + DATA -------------/\------/\------/\------/\----#---/\------/\-------- + ___ | + IRQ ----------------------------------------------------------+ + +------ + + Figure 27. SR Mode 6 -- Shift Out Under 02 Control + + +SR Mode 7 -- Shift Out Under CB1 Control + +In mode 7, shifting is controlled by pulses applied to the CB1 pin by an +external device (Figure 28). The SR counter sets the SR Interrupt Flag each +time it counts 8 pulses but it does not disable the shifting function. Each +time the microprocessor, writes or reads the shift register, the SR +Interrupt Flag is reset and the SR counter is initialized to begin counting +the next 8 shift pulses on pin CB1. After 8 shift pulses, the Interrupt +Flag is set. The microprocessor can then load the shift register with the +next byte of data. + + + +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-#-+ +-+ +-+ +-+ + 02 + +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ + + +---+ | + WRITE SR --+ +---------------------------------------------------------- + | + CB1 INPUT --------------+ 1 +---------------+ 2 +---#----+ | 8 + + SHIFT CLOCK +-------+ +-------+ +--------+ + | + CB2 OUTPUT --------------\/-----------1----------\/-----2----#----\/---8---- + DATA --------------/\----------------------/\----------#----/\-------- + ___ | + IRQ ----------------------------------------------------------+ + +------ + + Figure 28. SR Mode 7 -- Shift Out Under CB1 Control + + + +INTERRUPT OPERATION + +Controlling interrupts within the R6522 involves three principal +operations. These are flagging the interrupts, enabling interrupts and +signaling to the processor that an active interrupt exists within the chip. +Interrupt flags are set in the Interrupt Flag Register (IFR) by conditions +detected within the R6522 or on inputs to the R6522. These flags normally +remain set until the interrupt has been serviced. To determine the source +of an interrupt, the microprocessor must examine these flags in order, from +highest to lowest priority. + +Associated with each interrupt flag is an interrupt enable bit in the +Interrupt Enable Register (IER). This can be set or cleared by the +processor to enable interrupting the processor from the corresponding +interrupt flag. If an interrupt flag is set to a logic 1 by an interrupting +condition, and the corresponding interrupt enable bit is set to a 1, the +Interrupt Request (IRQ) output will go low. IRQ is an "open-collector" +output which can be "wire-OR'ed" with other devices in the system to +interrupt the processor. + + +Interrupt Flag Register (IFR) + +In the R6522, all the interrupt flags are contained in one register, i.e., +the IFR (Figure 29). In addition, bit 7 of this register will be read as a +logic 1 when an interrupt exists within the chip. This allows very +convenient polling of several devices within a system to locate the source +of an interrupt. + + + REG 13 -- INTERRUPT FLAG REGISTER ++-+-+-+-+-+-+-+-+ +|7|6|5|4|3|2|1|0| SET BY CLEARED BY ++-+-+-+-+-+-+-+-+ +-----------------------+------------------------------+ + | | | | | | | +--CA2| CA2 ACTIVE EDGE | READ OR WRITE REG 1 (ORA)* | + | | | | | | | +-----------------------+------------------------------+ + | | | | | | +--CA1--| CA1 ACTIVE EDGE | READ OR WRITE REG 1 (ORA) | + | | | | | | +-----------------------+------------------------------+ + | | | | | +SHIFT REG| COMPLETE 8 SHIFTS | READ OR WRITE SHIFT REG | + | | | | | +-----------------------+------------------------------+ + | | | | +-CB2-------| CB2 ACTIVE EDGE | READ OR WRITE ORB* | + | | | | +-----------------------+------------------------------+ + | | | +-CB1---------| CB1 ACTIVE EDGE | READ OR WRITE ORB | + | | | +-----------------------+------------------------------+ + | | +-TIMER 2-------| TIME-OUT OF T2 | READ T2 LOW OR WRITE T2 HIGH | + | | +-----------------------+------------------------------+ + | +-TIMER 1---------| TIME-OUT OF T1 | READ T1 LOW OR WRITE T1 HIGH | + | +-----------------------+------------------------------+ + +-IRQ---------------| ANY ENABLED INTERRUPT | CLEAR ALL INTERRUPTS | + +-----------------------+------------------------------+ + + * IF THE CA2/CB2 CONTROL IN THE PCR IS SELECTED AS "INDEPENDENT" + INTERRUPT INPUT, THEN READING OR WRITING THE OUTPUT REGISTER + ORA/ORB WILL NOT CLEAR THE FLAG BIT. INSTEAD, THE BIT MUST BE + CLEARED BY WRITING INTO THE IFR, AS DESCRIBED PREVIOUSLY. + + Figure 29. Interrupt Flag Register (IFR) + + +The Interrupt Flag Register (IFR) may be read directly by the processor. +In addition, individual flag bits may be cleared by writing a "1" into the +appropriate bit of the IFR. When the proper chip select and register +signals are applied to the chip, the contents of this register are placed +on the data bus. Bit 7 indicates the status of the IRQ output. This bit +corresponds to the logic function: IRQ = IFR6xIER6 + IFR5xIER5 + IFR4xIER4 + ++ IFR3xIER3 + IFR2xIER2 + IFR1xIER1 + IFR0xIER0 + + Note: + + x = logic AND, + = logic OR + +The IFR bit 7 is not a flag. Therefore, this bit is not directly cleared +by writing a logic 1 into it. It can only be cleared by clearing all the +flags in the register or by disabling all the active interrupts as +discussed in next section. + + +Interrupt Enable Register (IER) + +For each interrupt flag in IFR, there is a corresponding bit in the +Interrupt Enable Register (IER) (Figure 30). Individual bits in the IER can +be set or cleared to facilitate controlling individual interrupts without +affecting others. This is accomplished by writing to the IER after bit 7 +set or cleared to, in turn, set or clear selected enable bits. If bit 7 of +the data placed on the system data bus during this write operation is a 0, +each 1 in bits 6 through 0 clears the corresponding bit in the IER. For +each zero in bits 6 through 0, the corresponding bit is unaffected. + + + REG 14 -- INTERRUPT ENABLE REGISTER + +-+-+-+-+-+-+-+-+ + |7|6|5|4|3|2|1|0| + +-+-+-+-+-+-+-+-+ -+ + | | | | | | | +--- CA2 | + | | | | | | +----- CA1 | 0 = INTERRUPT + | | | | | +------- SHIFT REG | DISABLED + | | | | +--------- CB2 |_ + | | | +----------- CB1 | + | | +------------- TIMER 2 | 1 = INTERRUPT + | +--------------- TIMER 1 | ENABLED + +----------------- SET/CLEAR | + -+ + + NOTES: + 1 IF BIT 7 IS A "0", THEN EACH "1" IN BITS 0-6 DISABLES THE + CORRESPONDING INTERRUPT. + 2 IF BIT 7 IS A "1", THEN EACH "1" IN BITS 0-6 ENABLES THE + CORRESPONDING INTERRUPT. + 3 IF A READ OF THIS REGISTER IS DONE, BIT 7 WILL BE "1" AND + ALL OTHER BITS WILL REFLECT THEIR ENABLE/DISABLE STATE. + + Figure 30. Interrupt Enable Register (IER) + + +Selected bits in the IER can be set by writing to the IER with bit 7 in +the data word set to a logic 1. In this case, each 1 in bits 6 through 0 +will set the corresponding bit. For each zero, the corresponding bit will +be unaffected. This individual control of the setting and clearing +operations allows very convenient control of the interrupts during system +operation. + +In addition to setting and clearing IER bits, the contents of this +register can be read at any time. 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100755 index 0000000..839be89 Binary files /dev/null and b/Master128/Master_Ref_Man2_HQ.pdf differ diff --git a/NuLA/VideoNuLA.manual.pdf b/NuLA/VideoNuLA.manual.pdf new file mode 100755 index 0000000..4f12e3b Binary files /dev/null and b/NuLA/VideoNuLA.manual.pdf differ diff --git a/README.md b/README.md new file mode 100644 index 0000000..308930a --- /dev/null +++ b/README.md @@ -0,0 +1,49 @@ +Miscellanous grab bag of publicly available BBC Micro-related +documents: data sheets, reference manuals, user guides, disassemblies, +etc. + +Predominantly old stuff, with the odd remastered item. + +# TOC + +./AppNotes/ - Acorn app notes + +./AUG/ - Advanced User Guide, New Advanced User Guide + +./B/ - model B + +./B+/ - model B+ + +./BASIC/ - stuff relating to BASIC + +./FS/ - stuff relating to filing systems + +./ICs/ - data sheets + +./Master128/ - Master 128 + +./NuLA/ - Video NuLA + +./Tube/ - Tube info + +# Sources (where known) + +./AUG/AUG.pdf - https://stardot.org.uk/forums/viewtopic.php?f=42&t=17242 + +./AUG/NAUG.pdf - https://stardot.org.uk/forums/viewtopic.php?f=42&t=17243 + +./BASIC/Advanced_BASIC_ROM_User_Guide.pdf - https://stardot.org.uk/forums/viewtopic.php?t=13860 + +./tube/CoProClient.txt - http://mdfs.net/Software/Tube/6502/ + +./tube/tube_121.txt - http://www.zeridajh.org/articles/various/assembly_sources/index.htm + +./tube/TubeClient.txt - http://mdfs.net/Software/Tube/6502/ + +./B/BBC-circuit-diagram.png - https://stardot.org.uk/forums/viewtopic.php?f=3&t=17583 + +# Other links + +BBC MOS source: https://tobylobster.github.io/mos/ + +List of 7400-series integrated circuits: https://en.wikipedia.org/wiki/List_of_7400-series_integrated_circuits diff --git a/Tube/004 -Tube Application Note.pdf b/Tube/004 -Tube Application Note.pdf new file mode 100755 index 0000000..2c24bd4 Binary files /dev/null and b/Tube/004 -Tube Application Note.pdf differ diff --git a/Tube/Acorn_65022ndprocSM.pdf b/Tube/Acorn_65022ndprocSM.pdf new file mode 100755 index 0000000..f67b5bb Binary files /dev/null and b/Tube/Acorn_65022ndprocSM.pdf differ diff --git a/Tube/Acorn_65022ndprocUG.pdf b/Tube/Acorn_65022ndprocUG.pdf new file mode 100755 index 0000000..2b1fdd9 Binary files /dev/null and b/Tube/Acorn_65022ndprocUG.pdf differ diff --git a/Tube/Acorn_65C102CoProUG.pdf b/Tube/Acorn_65C102CoProUG.pdf new file mode 100755 index 0000000..8b61906 Binary files /dev/null and b/Tube/Acorn_65C102CoProUG.pdf differ diff --git a/Tube/CoProClient.txt b/Tube/CoProClient.txt new file mode 100755 index 0000000..8957820 --- /dev/null +++ b/Tube/CoProClient.txt @@ -0,0 +1,944 @@ +10REM >Client/src +20REM Source for 6502 Tube Client +30REM As supplied with Internal 6502 CoPro +40REM +50REM There are only three differences from the +60REM 6502 external second processor client ROM +70REM +80REM Code copyright Acorn Computer +90REM Commentary copyright J.G.Harston +100: +110IF PAGE>&8000:LOADATN "OS_GetEnv"TOA$:IFLEFT$(A$,5)<>"B6502":OSCLI"B6502"+MID$(A$,INSTR(A$," ")) +120: +130load%=&F800:DIM mcode% &900 +140: +150USERV=&200: BRKV=&202:IRQ1V=&204:IRQ2V=&206 +160 CLIV=&208:BYTEV=&20A:WORDV=&20C:WRCHV=&20E +170RDCHV=&210:FILEV=&212:ARGSV=&214:BGetV=&216 +180BPutV=&218:GBPBV=&21A:FINDV=&21C: FSCV=&21E +190EVNTV=&220: UPTV=&222: NETV=&224: VduV=&226 +200 KEYV=&228: INSV=&22A: RemV=&22C: CNPV=&22E +210IND1V=&230:IND2V=&232:IND3V=&234 +220: +230ERRBUF=&236:INPBUF=&236 +240: +250: +260REM Memory addresses: +270REM &EE/F = PROG - Current program +280REM &F0/1 = NUM - hex accumulator +290REM &F2/3 = MEMTOP - top of memory +300REM &F4/5 = address of byte transfer address, NMIAddr or ADDR +310REM &F6/7 = ADDR - Data transfer address +320REM &F8/9 = String pointer, OSWORD control block +330REM &FA/B = CTRL - OSFILE, OSGBPB control block, PrText string pointer +340REM &FC = IRQ A store +350REM &FD/E => last error +360REM &FF = Escape flag +370: +380FOR P=0TO1 +390P%=load%:O%=mcode% +400[OPT P*3+4 +410.RESET +420LDX #&00 +430.LF802 +440LDA &FF00,X:STA &FF00,X :\ Copy entry block to RAM +450DEX:BNE LF802 +460LDX #&36 +470.LF80D +480LDA LFF80,X:STA USERV,X :\ Set up default vectors +490DEX:BPL LF80D +500TXS:LDX #&F0 :\ Clear stack +510.LF819 +520LDA &FDFF,X:STA &FDFF,X :\ Copy &FE00-&FEEF to RAM, avoiding +530DEX:BNE LF819 :\ Tube registers at &FEFx +540LDY #RESET AND 255:STY &F8 :\ Point to start of ROM +550LDA #RESET DIV 256:STA &F9 +560.LF82A :\ Copy rest of ROM to RAM +570LDA (&F8),Y:STA (&F8),Y :\ Copy a page to RAM +580INY:BNE LF82A :\ Loop for 256 bytes +590INC &F9:LDA &F9 :\ Inc. address high byte +600CMP #&FE:BNE LF82A :\ Loop from &F800 to &FDFF +610LDX #&10 +620.LF83B +630LDA LF859,X:STA &0100,X :\ Copy jump code to &100 +640DEX:BPL LF83B +650LDA &EE:STA &F6 :\ Copy &EE/F to &F6/7 +660LDA &EF:STA &F7 +670LDA #&00:STA &FF :\ Clear Escape flag +680STA &F2:LDA #&F8:STA &F3 :\ Set memtop to start of ROM at &F800 +690JMP &0100 :\ Jump via low memory to page ROM out +700 +710\ Executed in low memory to page ROM out +720\ -------------------------------------- +730.LF859 +740LDA TubeS1:CLI :\ Check Tube R1 status to page ROM out +750.LF85D +760JMP LF860 :\ Jump to initilise I/O with banner +770 +780.LF860 +790JSR PrText :\ Display startup banner +800EQUB 10:EQUS "Acorn TUBE 65C102 Co-Processor" :\ ** Different from 6502 TUBE +810EQUB 10:EQUB 10:EQUB 13:EQUB 0 +820NOP +830LDA #CmdOSLoop AND 255 :\ Next time RESET is soft entered, +840STA LF85D+1 :\ banner not printed +850LDA #CmdOSLoop DIV 256 +860STA LF85D+2 +870JSR WaitByte :\ Wait for Acknowledge +880CMP #&80:BEQ EnterCode :\ If &80, jump to enter code +890 :\ Otherwise, enter command prompt loop +900 +910\ Minimal Command prompt +920\ ====================== +930.CmdOSLoop +940LDA #ASC"*":JSR OSWRCH :\ Print '*' prompt +950LDX #LF95D AND 255 +960LDY #LF95D DIV 256 +970LDA #&00:JSR OSWORD :\ Read line to INPBUF +980BCS CmdOSEscape +990LDX #INPBUF AND 255 +1000LDY #INPBUF DIV 256 :\ Execute command +1010JSR OS_CLI:JMP CmdOSLoop :\ and loop back for another +1020.CmdOSEscape +1030LDA #&7E:JSR OSBYTE :\ Acknowledge Escape state +1040BRK:EQUB 17:EQUS "Escape":BRK +1050 +1060 +1070\ Enter Code pointer to by &F6/7 +1080\ ============================== +1090\ Checks to see if code has a ROM header, and verifies +1100\ it if it has +1110.EnterCode +1120LDA &F6:STA &EE:STA &F2 :\ Set current program and memtop +1130LDA &F7:STA &EF:STA &F3 :\ to address beng entered +1140LDY #&07:LDA (&EE),Y :\ Get copyright offset +1150CLD:CLC:ADC &EE:STA &FD +1160LDA #&00:ADC &EF:STA &FE :\ &FD/E=>copyright message +1170\ +1180\ Now check for &00,"(C)" +1190LDY #&00:LDA (&FD),Y:BNE LF8FA :\ Jump if no initial &00 +1200INY:LDA (&FD),Y:CMP #&28:BNE LF8FA :\ Jump if no '(' +1210INY:LDA (&FD),Y:CMP #&43:BNE LF8FA :\ Jump if no 'C' +1220INY:LDA (&FD),Y:CMP #&29:BNE LF8FA :\ Jump if no ')' +1230\ +1240\ &00,"(C)" exists +1250LDY #&06:LDA (&EE),Y :\ Get ROM type +1260AND #&4F:CMP #&40:BCC NotLanguage :\ b6=0, not a language +1270AND #&0D:BNE Not6502Code :\ type<>0 and <>2, not 6502 code +1280.LF8FA +1290LDA #&01:JMP (&00F2) :\ Enter code with A=1 +1300\ +1310\ Any existing error handler will probably have been overwritten +1320\ Set up new error handler before generating an error +1330.NotLanguage +1340LDA #ErrorHandler AND 255:STA BRKV+0 :\ Claim error handler +1350LDA #ErrorHandler DIV 256:STA BRKV+1 +1360BRK:EQUB 0:EQUS "This is not a language":EQUB 0 +1370 +1380.Not6502Code +1390LDA #ErrorHandler AND 255:STA BRKV+0 :\ Claim error handler +1400LDA #ErrorHandler DIV 256:STA BRKV+1 +1410BRK:EQUB 0:EQUS "I cannot run this code":EQUB 0 +1420 +1430.ErrorHandler +1440LDX #&FF:TXS :\ Clear stack +1450JSR OSNEWL:LDY #&01 +1460.LF94D +1470LDA (&FD),Y:BEQ LF957 :\ Print error string +1480JSR OSWRCH:INY:BNE LF94D +1490.LF957 +1500JSR OSNEWL:JMP CmdOSLoop :\ Jump to command prompt +1510 +1520\ Control block for command prompt input +1530\ -------------------------------------- +1540.LF95D +1550EQUW INPBUF :\ Input text to INPBUF at &236 +1560EQUB &CA :\ Up to &CA characters +1570EQUB &20:EQUB &FF :\ Min=&20, Max=&FF +1580 +1590 +1600\ MOS INTERFACE +1610\ ============= +1620\ +1630\ +1640\ OSWRCH - Send character to output stream +1650\ ======================================== +1660\ On entry, A =character +1670\ On exit, A =preserved +1680\ +1690\ Tube data character -- +1700\ +1710.osWRCH +1720BIT TubeS1 :\ Read Tube R1 status +1730NOP:BVC osWRCH :\ Loop until b6 set +1740STA TubeR1:RTS :\ Send character to Tube R1 +1750 +1760 +1770\ OSRDCH - Wait for character from input stream +1780\ ============================================= +1790\ On exit, A =char, Cy=Escape flag +1800\ +1810\ Tube data &00 -- Carry Char +1820\ +1830.osRDCH +1840LDA #&00:JSR SendCommand :\ Send command &00 - OSRDCH +1850.WaitCarryChar :\ Wait for Carry and A +1860JSR WaitByte:ASL A :\ Wait for carry +1870.WaitByte +1880BIT TubeS2:BPL WaitByte :\ Loop until Tube R2 has data +1890LDA TubeR2 :\ Fetch character +1900.NullReturn +1910RTS +1920 +1930 +1940\ Skip Spaces +1950\ =========== +1960.SkipSpaces1 +1970INY +1980.SkipSpaces +1990LDA (&F8),Y:CMP #&20:BEQ SkipSpaces1 +2000RTS +2010 +2020 +2030\ Scan hex +2040\ ======== +2050.ScanHex +2060LDX #&00:STX &F0:STX &F1 :\ Clear hex accumulator +2070.LF98C +2080LDA (&F8),Y :\ Get current character +2090CMP #&30:BCC LF9B1 :\ <'0', exit +2100CMP #&3A:BCC LF9A0 :\ '0'..'9', add to accumulator +2110AND #&DF:SBC #&07:BCC LF9B1:\ Convert letter, if <'A', exit +2120CMP #&40:BCS LF9B1 :\ >'F', exit +2130.LF9A0 +2140ASL A:ASL A:ASL A:ASL A :\ *16 +2150LDX #&03 :\ Prepare to move 3+1 bits +2160.LF9A6 +2170ASL A:ROL &F0:ROL &F1 :\ Move bits into accumulator +2180DEX:BPL LF9A6 :\ Loop for four bits, no overflow check +2190INY:BNE LF98C :\ Move to next character +2200.LF9B1 +2210RTS +2220 +2230 +2240\ Send string to Tube R2 +2250\ ====================== +2260.SendString +2270STX &F8:STY &F9 :\ Set &F8/9=>string +2280.SendStringF8 +2290LDY #&00 +2300.LF9B8 +2310BIT TubeS2:BVC LF9B8 :\ Wait for Tube R2 free +2320LDA (&F8),Y:STA TubeR2 :\ Send character to Tube R2 +2330INY:CMP #&0D:BNE LF9B8 :\ Loop until sent +2340LDY &F9:RTS :\ Restore Y from &F9 and return +2350 +2360 +2370\ OSCLI - Execute command +2380\ ======================= +2390\ On entry, XY=>command string +2400\ On exit, XY= preserved +2410\ +2420.osCLI +2430PHA:STX &F8:STY &F9 :\ Save A, &F8/9=>command string +2440LDY #&00 +2450.LF9D1 +2460JSR SkipSpaces:INY +2470CMP #ASC"*":BEQ LF9D1 :\ Skip spaces and stars +2480AND #&DF:TAX :\ Ignore case, and save in X +2490LDA (&F8),Y :\ Get next character +2500CPX #ASC"G":BEQ CmdGO :\ Jump to check '*GO' +2510CPX #ASC"H":BNE osCLI_IO :\ Not "H---", jump to pass to Tube +2520CMP #ASC".":BEQ CmdHELP :\ "H.", jump to do *DELETEHIMEM +2530AND #&DF :\ Ignore case +2540CMP #ASC"E":BNE osCLI_IO :\ Not "HE---", jump to pass to Tube +2550INY:LDA (&F8),Y :\ Get next character +2560CMP #ASC".":BEQ CmdHELP :\ "HE.", jump to do *DELETEHIMEM +2570AND #&DF :\ Ignore case +2580CMP #ASC"L":BNE osCLI_IO :\ Not "HEL---", jump to pass to Tube +2590INY:LDA (&F8),Y :\ Get next character +2600CMP #ASC".":BEQ CmdHELP :\ "HEL.", jump to do *DELETEHIMEM +2610AND #&DF :\ Ignore case +2620CMP #ASC"P":BNE osCLI_IO :\ Not "HELP---", jump to pass to Tube +2630INY:LDA (&F8),Y :\ Get next character +2640AND #&DF :\ Ignore case +2650CMP #ASC"A":BCC CmdHELP :\ "HELP" terminated by non-letter, do *DELETEHIMEM +2660CMP #ASC"[":BCC osCLI_IO :\ "HELP" followed by letter, pass to Tube +2670 +2680\ *Help - Display help information +2690\ -------------------------------- +2700.CmdHELP +2710JSR PrText :\ Print help message +2720EQUB 10:EQUB 13:EQUS "65C102 TUBE 1.10" :\ ** Different from 6502 TUBE +2730EQUB 10:EQUB 13 +2740NOP :\ Continue to pass '*DELETEHIMEM' command to Tube +2750 +2760 +2770\ OSCLI - Send command line to host +2780\ ================================= +2790\ On entry, &F8/9=>command string +2800\ +2810\ Tube data &02 string &0D -- &7F or &80 +2820\ +2830.osCLI_IO +2840LDA #&02:JSR SendCommand :\ Send command &02 - OSCLI +2850JSR SendStringF8 :\ Send command string at &F8/9 +2860.osCLI_Ack +2870JSR WaitByte :\ Wait for acknowledgement +2880CMP #&80:BEQ LFA5C :\ Jump if code to be entered +2890PLA:RTS :\ Restore A and return +2900 +2910 +2920\ *GO - call machine code +2930\ ----------------------- +2940.CmdGO +2950AND #&DF :\ Ignore case +2960CMP #ASC"O":BNE osCLI_IO :\ Not '*GO', jump to pass to Tube +2970JSR SkipSpaces1 :\ Move past any spaces +2980JSR ScanHex:JSR SkipSpaces :\ Read hex value and move past spaces +2990CMP #&0D:BNE osCLI_IO :\ More parameters, pass to Tube to deal with +3000TXA:BEQ LFA5C :\ If no address given, jump to current program +3010LDA &F0:STA &F6 :\ Set program start to address read +3020LDA &F1:STA &F7 +3030 +3040.LFA5C +3050LDA &EF:PHA:LDA &EE:PHA :\ Save current program +3060JSR EnterCode +3070PLA:STA &EE:STA &F2 :\ Restore current program and +3080PLA:STA &EF:STA &F3 :\ set address top of memory to it +3090PLA:RTS +3100 +3110.CheckAck +3120BEQ osCLI_Ack +3130 +3140 +3150\ OSBYTE - Byte MOS functions +3160\ =========================== +3170\ On entry, A, X, Y=OSBYTE parameters +3180\ On exit, A preserved +3190\ If A<&80, X=returned value +3200\ If A>&7F, X, Y, Carry=returned values +3210\ +3220.osBYTE +3230CMP #&80:BCS ByteHigh :\ Jump for long OSBYTEs +3240\ +3250\ Tube data &04 X A -- X +3260\ +3270PHA:LDA #&04 +3280.LFA7A +3290BIT TubeS2:BVC LFA7A :\ Wait for Tube R2 free +3300STA TubeR2 :\ Send command &04 - OSBYTELO +3310.LFA82 +3320BIT TubeS2:BVC LFA82 :\ Wait for Tube R2 free +3330STX TubeR2:PLA :\ Send single parameter +3340.LFA8B +3350BIT TubeS2:BVC LFA8B :\ Wait for Tube R2 free +3360STA TubeR2 :\ Send function +3370.LFA93 +3380BIT TubeS2:BPL LFA93 :\ Wait for Tube R2 data present +3390LDX TubeR2:RTS :\ Get return value +3400 +3410.ByteHigh +3420CMP #&82:BEQ Byte82 :\ Read memory high word +3430CMP #&83:BEQ Byte83 :\ Read bottom of memory +3440CMP #&84:BEQ Byte84 :\ Read top of memory +3450\ +3460\ Tube data &06 X Y A -- Cy Y X +3470\ +3480PHA:LDA #&06 +3490.LFAAB +3500BIT TubeS2:BVC LFAAB :\ Wait for Tube R2 free +3510STA TubeR2 :\ Send command &06 - OSBYTEHI +3520.LFAB3 +3530BIT TubeS2:BVC LFAB3 :\ Wait for Tube R2 free +3540STX TubeR2 :\ Send parameter 1 +3550.LFABB +3560BIT TubeS2:BVC LFABB :\ Wait for Tube R2 free +3570STY TubeR2 :\ Send parameter 2 +3580PLA +3590.LFAC4 +3600BIT TubeS2:BVC LFAC4 :\ Wait for Tube R2 free +3610STA TubeR2 :\ Send function +3620CMP #&8E:BEQ CheckAck :\ If select language, check to enter code +3630CMP #&9D:BEQ LFAEF :\ Fast return with Fast BPUT +3640PHA :\ Save function +3650.LFAD5 +3660BIT TubeS2:BPL LFAD5 :\ Wait for Tube R2 data present +3670LDA TubeR2:ASL A:PLA :\ Get Carry +3680.LFADF +3690BIT TubeS2:BPL LFADF :\ Wait for Tube R2 data present +3700LDY TubeR2 :\ Get return high byte +3710.LFAE7 +3720BIT TubeS2:BPL LFAE7 :\ Wait for Tube R2 data present +3730LDX TubeR2 :\ Get return low byte +3740.LFAEF +3750RTS +3760 +3770.Byte84:LDX &F2:LDY &F3:RTS :\ Read top of memory from &F2/3 +3780.Byte83:LDX #&00:LDY #&08:RTS :\ Read bottom of memory +3790.Byte82:LDX #&00:LDY #&00:RTS :\ Return &0000 as memory high word +3800 +3810 +3820\ OSWORD - Various functions +3830\ ========================== +3840\ On entry, A =function +3850\ XY=>control block +3860\ +3870.osWORD +3880STX &F8:STY &F9 :\ &F8/9=>control block +3890TAY:BEQ RDLINE :\ OSWORD 0, jump to read line +3900PHA:LDY #&08 +3910.LFB09 +3920BIT TubeS2:BVC LFB09 :\ Loop until Tube R2 free +3930STY TubeR2 :\ Send command &08 - OSWORD +3940.LFB11 +3950BIT TubeS2:BVC LFB11 :\ Loop until Tube R2 free +3960STA TubeR2 :\ Send function +3970TAX:BPL WordSendLow :\ Jump with functions<&80 +3980LDY #&00:LDA (&F8),Y :\ Get send block length from control block +3990TAY:JMP WordSend :\ Jump to send control block +4000 +4010.WordSendLow +4020LDY WordLengthsLo-1,X :\ Get send block length from table +4030CPX #&15:BCC WordSend :\ Use this length for OSWORD 1 to &14 +4040LDY #&10 :\ Send 16 bytes for OSWORD &15 to &7F +4050.WordSend +4060BIT TubeS2:BVC WordSend :\ Wait until Tube R2 free +4070STY TubeR2 :\ Send send block length +4080DEY:BMI LFB45 :\ Zero or &81..&FF length, nothing to send +4090.LFB38 +4100BIT TubeS2:BVC LFB38 :\ Wait for Tube R2 free +4110LDA (&F8),Y:STA TubeR2 :\ Send byte from control block +4120DEY:BPL LFB38 :\ Loop for number to be sent +4130.LFB45 +4140TXA:BPL WordRecvLow :\ Jump with functions<&80 +4150LDY #&01:LDA (&F8),Y :\ Get receive block length from control block +4160TAY:JMP WordRecv :\ Jump to receive control block +4170 +4180.WordRecvLow +4190LDY WordLengthsHi-1,X :\ Get receive length from table +4200CPX #&15:BCC WordRecv :\ Use this length for OSWORD 1 to &14 +4210LDY #&10 :\ Receive 16 bytes for OSWORD &15 to &7F +4220.WordRecv +4230BIT TubeS2:BVC WordRecv :\ Wait for Tube R2 free +4240STY TubeR2 :\ Send receive block length +4250DEY:BMI LFB71 :\ Zero of &81..&FF length, nothing to receive +4260.LFB64 +4270BIT TubeS2:BPL LFB64 :\ Wait for Tube R2 data present +4280LDA TubeR2:STA (&F8),Y :\ Get byte to control block +4290DEY:BPL LFB64 :\ Loop for number to receive +4300.LFB71 +4310LDY &F9:LDX &F8:PLA :\ Restore registers +4320RTS +4330 +4340 +4350\ RDLINE - Read a line of text +4360\ ============================ +4370\ On entry, A =0 +4380\ XY=>control block +4390\ On exit, A =undefined +4400\ Y =length of returned string +4410\ Cy=0 ok, Cy=1 Escape +4420\ +4430\ Tube data &0A block -- &FF or &7F string &0D +4440\ +4450.RDLINE +4460LDA #&0A:JSR SendCommand :\ Send command &0A - RDLINE +4470LDY #&04 +4480.LFB7E +4490BIT TubeS2:BVC LFB7E :\ Wait for Tube R2 free +4500LDA (&F8),Y:STA TubeR2 :\ Send control block +4510DEY:CPY #&01:BNE LFB7E :\ Loop for 4, 3, 2 +4520LDA #&07:JSR SendByte :\ Send &07 as address high byte +4530LDA (&F8),Y:PHA :\ Get text buffer address high byte +4540DEY +4550.LFB96 +4560BIT TubeS2:BVC LFB96 :\ Wait for Tube R2 free +4570STY TubeR2 :\ Send &00 as address low byte +4580LDA (&F8),Y:PHA :\ Get text buffer address low byte +4590LDX #&FF:JSR WaitByte :\ Wait for response +4600CMP #&80:BCS RdLineEscape :\ Jump if Escape returned +4610PLA:STA &F8:PLA:STA &F9 :\ Set &F8/9=>text buffer +4620LDY #&00 +4630.RdLineLp +4640BIT TubeS2:BPL RdLineLp :\ Wait for Tube R2 data present +4650LDA TubeR2:STA (&F8),Y :\ Store returned character +4660INY:CMP #&0D:BNE RdLineLp :\ Loop until +4670LDA #&00:DEY:CLC:INX :\ Return A=0, Y=len, X=00, Cy=0 +4680RTS +4690: +4700.RdLineEscape +4710PLA:PLA:LDA #&00 :\ Return A=0, Y=len, X=FF, Cy=1 +4720RTS +4730 +4740 +4750\ OSARGS - Read info on open file +4760\ =============================== +4770\ On entry, A =function +4780\ X =>data word in zero page +4790\ Y =handle +4800\ On exit, A =returned value +4810\ X preserved +4820\ Y preserved +4830\ +4840\ Tube data &0C handle block function -- result block +4850\ +4860.osARGS +4870PHA:LDA #&0C:JSR SendCommand :\ Send command &0C - OSARGS +4880.LFBD2 +4890BIT TubeS2:BVC LFBD2 :\ Loop until Tube R2 free +4900STY TubeR2 :\ Send handle +4910LDA &03,X:JSR SendByte :\ Send data word +4920LDA &02,X:JSR SendByte +4930LDA &01,X:JSR SendByte +4940LDA &00,X:JSR SendByte +4950PLA:JSR SendByte :\ Send function +4960JSR WaitByte:PHA :\ Get and save result +4970JSR WaitByte:STA &03,X :\ Receive data word +4980JSR WaitByte:STA &02,X +4990JSR WaitByte:STA &01,X +5000JSR WaitByte:STA &00,X +5010PLA:RTS :\ Get result back and return +5020 +5030 +5040\ OSFIND - Open of Close a file +5050\ ============================= +5060\ On entry, A =function +5070\ Y =handle or XY=>filename +5080\ On exit, A =zero or handle +5090\ +5100\ Tube data &12 function string &0D -- handle +5110\ &12 &00 handle -- &7F +5120\ +5130.osFIND +5140PHA:LDA #&12:JSR SendCommand :\ Send command &12 - OSFIND +5150PLA:JSR SendByte :\ Send function +5160CMP #&00:BNE OPEN :\ If <>0, jump to do OPEN +5170PHA:TYA:JSR SendByte :\ Send handle +5180JSR WaitByte:PLA:RTS :\ Wait for acknowledge, restore regs and return +5190.OPEN +5200JSR SendString :\ Send pathname +5210JMP WaitByte :\ Wait for and return handle +5220 +5230 +5240\ OSBGet - Get a byte from open file +5250\ ================================== +5260\ On entry, Y =handle +5270\ On exit, A =byte Read +5280\ Y =preserved +5290\ Cy set if EOF +5300\ +5310\ Tube data &0E handle -- Carry byte +5320\ +5330.osBGET +5340LDA #&0E:JSR SendCommand :\ Send command &0E - OSBGET +5350TYA:JSR SendByte :\ Send handle +5360JMP WaitCarryChar :\ Jump to wait for Carry and byte +5370 +5380 +5390\ OSBPut - Put a byte to an open file +5400\ =================================== +5410\ On entry, A =byte to write +5420\ Y =handle +5430\ On exit, A =preserved +5440\ Y =preserved +5450\ +5460\ Tube data &10 handle byte -- &7F +5470\ +5480.osBPUT +5490PHA:LDA #&10:JSR SendCommand :\ Send command &10 - OSBPUT +5500TYA:JSR SendByte :\ Send handle +5510PLA:JSR SendByte :\ Send byte +5520PHA:JSR WaitByte:PLA:RTS :\ Wait for acknowledge and return +5530 +5540 +5550\ Send a byte to Tube R2 +5560\ ====================== +5570.SendCommand +5580.SendByte +5590BIT TubeS2:BVC SendByte :\ Wait for Tube R2 free +5600STA TubeR2:RTS :\ Send byte to Tube R2 +5610 +5620 +5630\ OSFILE - Operate on whole files +5640\ =============================== +5650\ On entry, A =function +5660\ XY=>control block +5670\ On exit, A =result +5680\ control block updated +5690\ +5700\ Tube data &14 block string function -- result block +5710\ +5720.osFILE +5730STY &FB:STX &FA :\ &FA/B=>control block +5740PHA:LDA #&14:JSR SendCommand :\ Send command &14 - OSFILE +5750LDY #&11 +5760.LFC5F +5770LDA (&FA),Y:JSR SendByte :\ Send control block +5780DEY:CPY #&01:BNE LFC5F :\ Loop for &11..&02 +5790DEY:LDA (&FA),Y:TAX +5800INY:LDA (&FA),Y:TAY :\ Get pathname address to XY +5810JSR SendString :\ Send pathname +5820PLA:JSR SendByte :\ Send function +5830JSR WaitByte:PHA :\ Wait for result +5840LDY #&11 +5850.LFC7E +5860JSR WaitByte:STA (&FA),Y :\ Get control block back +5870DEY:CPY #&01:BNE LFC7E :\ Loop for &11..&02 +5880LDY &FB:LDX &FA :\ Restore registers +5890PLA:RTS :\ Get result and return +5900 +5910 +5920\ OSGBPB - Multiple byte Read and write +5930\ ===================================== +5940\ On entry, A =function +5950\ XY=>control block +5960\ On exit, A =returned value +5970\ control block updated +5980\ +5990\ Tube data &16 block function -- block Carry result +6000\ +6010.osGBPB +6020STY &FB:STX &FA :\ &FA/B=>control block +6030PHA:LDA #&16:JSR SendCommand :\ Send command &16 - OSGBPB +6040LDY #&0C +6050.LFC9A +6060LDA (&FA),Y:JSR SendByte :\ Send control block +6070DEY:BPL LFC9A :\ Loop for &0C..&00 +6080PLA:JSR SendByte :\ Send function +6090LDY #&0C +6100.LFCA8 +6110JSR WaitByte:STA (&FA),Y :\ Get control block back +6120DEY:BPL LFCA8 :\ Loop for &0C..&00 +6130LDY &FB:LDX &FA :\ Restore registers +6140JMP WaitCarryChar :\ Jump to get Carry and result +6150 +6160 +6170.Unsupported +6180BRK:EQUB 255:EQUS "Bad":EQUB 0 +6190 +6200 +6210\ OSWORD control block lengths +6220\ ============================ +6230.WordLengthsLo +6240EQUB &00:EQUB &05:EQUB &00:EQUB &05 +6250EQUB &04:EQUB &05:EQUB &08:EQUB &0E :\ ** Different, 6502 TUBE sends only 2 bytes for =IO +6260EQUB &04:EQUB &01:EQUB &01:EQUB &05 +6270EQUB &00:EQUB &01:EQUB &20:EQUB &10 +6280EQUB &0D:EQUB &00:EQUB &04:EQUB &80 +6290.WordLengthsHi +6300EQUB &05:EQUB &00:EQUB &05:EQUB &00 +6310EQUB &05:EQUB &00:EQUB &00:EQUB &00 +6320EQUB &05:EQUB &09:EQUB &05:EQUB &00 +6330EQUB &08:EQUB &18:EQUB &00:EQUB &01 +6340EQUB &0D:EQUB &80:EQUB &04:EQUB &80 +6350 +6360 +6370\ Interrupt Handler +6380\ ================= +6390.InterruptHandler +6400STA &FC:PLA:PHA :\ Save A, get flags from stack +6410AND #&10:BNE BRKHandler :\ If BRK, jump to BRK handler +6420JMP (IRQ1V) :\ Continue via IRQ1V handler +6430 +6440.IRQ1Handler +6450BIT TubeS4:BMI LFD3F :\ If data in Tube R4, jump to process errors and transferes +6460BIT TubeS1:BMI LFD18 :\ If data in Tube R1, jump to process Escape and Events +6470JMP (IRQ2V) :\ Pass on to IRQ2V +6480 +6490.BRKHandler +6500TXA:PHA :\ Save X +6510TSX:LDA &0103,X :\ Get address from stack +6520CLD:SEC:SBC #&01:STA &FD +6530LDA &0104,X:SBC #&00:STA &FE :\ &FD/E=>after BRK opcode +6540PLA:TAX:LDA &FC :\ Restore X, get saved A +6550CLI:JMP (BRKV) :\ Restore IRQs, jump to Error Handler +6560 +6570 +6580\ Interrupt generated by data in Tube R1 +6590\ -------------------------------------- +6600.LFD18 +6610LDA TubeR1:BMI LFD39 :\ b7=1, jump to set Escape state +6620TYA:PHA:TXA:PHA :\ Save registers +6630JSR LFE80:TAY :\ Get Y parameter from Tube R1 +6640JSR LFE80:TAX :\ Get X parameter from Tube R1 +6650JSR LFE80 :\ Get event number from Tube R1 +6660JSR LFD36:PLA:TAX:PLA:TAY :\ Dispatch event, restore registers +6670LDA &FC:RTI :\ Restore A, return from interrupt +6680.LFD36 +6690JMP (EVNTV) +6700.LFD39 +6710ASL A:STA &FF :\ Set Escape flag from b6 +6720LDA &FC:RTI :\ Restore A, return from interrupt +6730 +6740 +6750\ Interrupt generated by data in Tube R4 +6760\ -------------------------------------- +6770.LFD3F +6780LDA TubeR4:BPL LFD65 :\ b7=0, jump for data transfer +6790CLI +6800.LFD45 +6810BIT TubeS2:BPL LFD45 :\ Wait for data in Tube R2 +6820LDA TubeR2 +6830LDA #&00:STA ERRBUF:TAY :\ Store BRK opcode in error buffer +6840JSR WaitByte:STA ERRBUF+1 :\ Get error number +6850.LFD59 +6860INY:JSR WaitByte :\ Store bytes fetched from Tube R2 +6870STA ERRBUF+1,Y:BNE LFD59 :\ Loop until final zero +6880JMP ERRBUF :\ Jump to error block to generate error +6890 +6900\ Data transfer initiated by IRQ via Tube R4 +6910\ ------------------------------------------ +6920.LFD65 +6930STA NMIV+0:TYA:PHA :\ Save transfer type, save Y +6940LDY NMIV+0 :\ Get transfer type back +6950LDA LFE70,Y:STA NMIV+0 :\ get NMI routine address from table +6960LDA LFE78,Y:STA NMIV+1 :\ and point NMIV to it +6970LDA LFE60,Y:STA &F4 :\ Point &F4/5 to transfer address field +6980LDA LFE68,Y:STA &F5 +6990.LFD83 +7000BIT TubeS4:BPL LFD83 :\ Wait until Tube R4 data present +7010LDA TubeR4 :\ Get called ID from Tube R4 +7020CPY #&05:BEQ LFDE7 :\ If 'TubeRelease', jump to exit +7030TYA:PHA:LDY #&01 :\ Save transfer type +7040.LFD93 +7050BIT TubeS4:BPL LFD93 :\ Wait for Tube R4 data present +7060LDA TubeR4 :\ Fetch and disgard address byte 4 +7070.LFD9B +7080BIT TubeS4:BPL LFD9B :\ Wait for Tube R4 data present +7090LDA TubeR4 :\ Fetch and disgard address byte 3 +7100.LFDA3 +7110BIT TubeS4:BPL LFDA3 :\ Wait for Tube R4 data present +7120LDA TubeR4:STA (&F4),Y:DEY :\ Fetch address byte 2, store in address +7130.LFDAE +7140BIT TubeS4:BPL LFDAE :\ Wait for Tube R4 data present +7150LDA TubeR4:STA (&F4),Y :\ Fetch address byte 1, store in address +7160BIT TubeR3:BIT TubeR3 :\ Read from Tube R3 twice +7170.LFDBE +7180BIT TubeS4:BPL LFDBE :\ Wait for Tube R4 data present +7190LDA TubeR4:PLA :\ Get sync byte from Tube R4 +7200CMP #&06:BCC LFDE7 :\ Exit if not 256-byte transfers +7210BNE LFDEC :\ Jump with 256-byte read +7220 +7230\ Send 256 bytes to Tube via R3 +7240\ ----------------------------- +7250LDY #&00 +7260.LFDCF +7270LDA TubeS3:AND #&80:BPL LFDCF:\ Wait for Tube R3 free +7280.NMI6Addr +7290LDA &FFFF,Y:STA TubeR3 :\ Fetch byte and send to Tube R3 +7300INY:BNE LFDCF :\ Loop for 256 bytes +7310.LFDDF +7320BIT TubeS3:BPL LFDDF :\ Wait for Tube R3 free +7330STA TubeR3 :\ Send final sync byte +7340.LFDE7 +7350PLA:TAY:LDA &FC:RTI :\ Restore registers and return +7360 +7370\ Read 256 bytes from Tube via R3 +7380\ ------------------------------- +7390.LFDEC +7400LDY #&00 +7410.LFDEE +7420LDA TubeS3:AND #&80:BPL LFDEE:\ Wait for Tube R3 data present +7430LDA TubeR3 :\ Fetch byte from Tube R3 +7440.NMI7Addr +7450STA &FFFF,Y:INY:BNE LFDEE :\ Store byte and loop for 256 bytes +7460BEQ LFDE7 :\ Jump to restore registers and return +7470 +7480\ Transfer 0 - Transfer single byte to Tube +7490\ ----------------------------------------- +7500.NMI0 +7510PHA :\ Save A +7520.NMI0Addr +7530LDA &FFFF:STA TubeR3 :\ Get byte and send to Tube R3 +7540INC NMI0Addr+1:BNE LFE0F :\ Increment transfer address +7550INC NMI0Addr+2 +7560.LFE0F +7570PLA:RTI :\ Restore A and return +7580 +7590\ Transfer 1 - Transfer single byte from Tube +7600\ ------------------------------------------- +7610.NMI1 +7620PHA:LDA TubeR3 :\ Save A, get byte from Tube R3 +7630.NMI1Addr +7640STA &FFFF :\ Store byte +7650INC NMI1Addr+1:BNE LFE20 :\ Increment transfer address +7660INC NMI1Addr+2 +7670.LFE20 +7680PLA:RTI :\ Restore A and return +7690 +7700\ Transfer 2 - Transfer two bytes to Tube +7710\ --------------------------------------- +7720.NMI2 +7730PHA:TYA:PHA:LDY #&00 :\ Save registers +7740LDA (&F6),Y:STA TubeR3 :\ Get byte and send to Tube R3 +7750INC &F6:BNE LFE32:INC &F7 :\ Increment transfer address +7760.LFE32 +7770LDA (&F6),Y:STA TubeR3 :\ Get byte and send to Tube R3 +7780INC &F6:BNE LFE3D:INC &F7 :\ Increment transfer address +7790.LFE3D +7800PLA:TAY:PLA:RTI :\ Restore registers and return +7810 +7820\ Transfer 3 - Transfer two bytes from Tube +7830\ ----------------------------------------- +7840.NMI3 +7850PHA:TYA:PHA:LDY #&00 :\ Save registers +7860LDA TubeR3:STA (&F6),Y :\ Get byte from Tube R3 and store +7870INC &F6:BNE LFE51:INC &F7 :\ Increment transfer address +7880.LFE51 +7890LDA TubeR3:STA (&F6),Y :\ Get byte from Tube R3 and store +7900INC &F6:BNE LFE5C:INC &F7 :\ Increment transfer address +7910.LFE5C +7920PLA:TAY:PLA:RTI :\ Restore registers and return +7930 +7940\ Data transfer address pointers +7950\ ------------------------------ +7960.LFE60 +7970EQUB (NMI0Addr+1) AND 255:EQUB (NMI1Addr+1) AND 255 +7980EQUB &00F6 AND 255 :EQUB &00F6 AND 255 +7990EQUB &00F6 AND 255 :EQUB &00F6 AND 255 +8000EQUB (NMI6Addr+1) AND 255:EQUB (NMI7Addr+1) AND 255 +8010.LFE68 +8020EQUB (NMI0Addr+1) DIV 256:EQUB (NMI1Addr+1) DIV 256 +8030EQUB &00F6 DIV 256 :EQUB &00F6 DIV 256 +8040EQUB &00F6 DIV 256 :EQUB &00F6 DIV 256 +8050EQUB (NMI6Addr+1) DIV 256:EQUB (NMI7Addr+1) DIV 256 +8060 +8070\ Data transfer routine addresses +8080\ ------------------------------- +8090.LFE70 +8100EQUB NMI0 AND 255 :EQUB NMI1 AND 255 +8110EQUB NMI2 AND 255 :EQUB NMI3 AND 255 +8120EQUB NMI_Ack AND 255:EQUB NMI_Ack AND 255 +8130EQUB NMI_Ack AND 255:EQUB NMI_Ack AND 255 +8140.LFE78 +8150EQUB NMI0 DIV 256 :EQUB NMI1 DIV 256 +8160EQUB NMI2 DIV 256 :EQUB NMI3 DIV 256 +8170EQUB NMI_Ack DIV 256:EQUB NMI_Ack DIV 256 +8180EQUB NMI_Ack DIV 256:EQUB NMI_Ack DIV 256 +8190 +8200 +8210\ Wait for byte in Tube R1 while allowing requests via Tube R4 +8220\ ============================================================ +8230.LFE80 +8240BIT TubeS1:BMI LFE94 :\ If data in Tube R1, jump to fetch it +8250.LFE85 +8260BIT TubeS4 :\ Check if data present in Tube R4 +8270BPL LFE80 :\ If nothing there, jump back to check Tube R1 +8280LDA &FC :\ Save IRQ's A store in A register +8290PHP:CLI:PLP :\ Allow an IRQ through to process R4 request +8300STA &FC:JMP LFE80 :\ Restore IRQ's A store and jump back to check R1 +8310.LFE94 +8320LDA TubeR1:RTS :\ Fetch byte from Tube R1 and return +8330 +8340 +8350\ Print embedded string +8360\ ===================== +8370.PrText +8380PLA:STA &FA:PLA:STA &FB :\ &FA/B=>embedded string +8390LDY #&00 +8400.LFEA0 +8410INC &FA:BNE LFEA6:INC &FB :\ Increment address +8420.LFEA6 +8430LDA (&FA),Y:BMI LFEB0 :\ Get character, exit if >&7F +8440JSR OSWRCH:JMP LFEA0 :\ Print character and loop back for more +8450.LFEB0 +8460JMP (&00FA) :\ Jump back to code after string +8470 +8480 +8490\ Null NMI code +8500\ ------------- +8510.NMI_Ack +8520STA TubeR3:RTI :\ Store to TubeR3 to acknowlege NMI +8530 +8540 +8550\ Spare space +8560\ =========== +8570EQUS STRING$(&FEF0-P%,CHR$255) +8580 +8590 +8600\ I/O Space +8610\ ========= +8620EQUS STRING$(8,CHR$0) +8630 +8640\ Tube I/O Registers +8650\ ================== +8660.TubeS1 :\ &FEF8 :EQUB 0 +8670.TubeR1 :\ &FEF9 :EQUB 0 +8680.TubeS2 :\ &FEFA :EQUB 0 +8690.TubeR2 :\ &FEFB :EQUB 0 +8700.TubeS3 :\ &FEFC :EQUB 0 +8710.TubeR3 :\ &FEFD :EQUB 0 +8720.TubeS4 :\ &FEFE :EQUB 0 +8730.TubeR4 :\ &FEFF :EQUB 0 +8740 +8750 +8760\ Spare space +8770\ =========== +8780.LFF00 +8790EQUS STRING$(&FF80-P%,CHR$255) +8800 +8810 +8820\ DEFAULT VECTOR TABLE +8830\ ==================== +8840.LFF80 +8850EQUW Unsupported :\ &200 - USERV +8860EQUW ErrorHandler :\ &202 - BRKV +8870EQUW IRQ1Handler :\ &204 - IRQ1V +8880EQUW Unsupported :\ &206 - IRQ2V +8890EQUW osCLI :\ &208 - CLIV +8900EQUW osBYTE :\ &20A - BYTEV +8910EQUW osWORD :\ &20C - WORDV +8920EQUW osWRCH :\ &20E - WRCHV +8930EQUW osRDCH :\ &210 - RDCHV +8940EQUW osFILE :\ &212 - FILEV +8950EQUW osARGS :\ &214 - ARGSV +8960EQUW osBGET :\ &216 - BGetV +8970EQUW osBPUT :\ &218 - BPutV +8980EQUW osGBPB :\ &21A - GBPBV +8990EQUW osFIND :\ &21C - FINDV +9000EQUW Unsupported :\ &21E - FSCV +9010EQUW NullReturn :\ &220 - EVNTV +9020EQUW Unsupported :\ &222 - UPTV +9030EQUW Unsupported :\ &224 - NETV +9040EQUW Unsupported :\ &226 - VduV +9050EQUW Unsupported :\ &228 - KEYV +9060EQUW Unsupported :\ &22A - INSV +9070EQUW Unsupported :\ &22C - RemV +9080EQUW Unsupported :\ &22E - CNPV +9090EQUW NullReturn :\ &230 - IND1V +9100EQUW NullReturn :\ &232 - IND2V +9110EQUW NullReturn :\ &234 - IND3V +9120 +9130.VECDEF :\ &FFB6 :EQUB &36:EQUW LFF80 +9140.OSXXXX :\ &FFB9 :JMP Unsupported +9150.OSXXXX :\ &FFBC :JMP Unsupported +9160.OSXXXX :\ &FFBF :JMP Unsupported +9170.OSXXXX :\ &FFC2 :JMP Unsupported +9180.OSXXXX :\ &FFC5 :JMP Unsupported +9190.NVRDCH :\ &FFC8 :JMP osRDCH +9200.NVWRCH :\ &FFCB :JMP osWRCH +9210 +9220.OSFIND :\ &FFCE :JMP (FINDV) +9230.OSGBPB :\ &FFD1 :JMP (GBPBV) +9240.OSBPUT :\ &FFD4 :JMP (BPutV) +9250.OSBGET :\ &FFD7 :JMP (BGetV) +9260.OSARGS :\ &FFDA :JMP (ARGSV) +9270.OSFILE :\ &FFDD :JMP (FILEV) +9280 +9290.OSRDCH :\ &FFE0 :JMP (RDCHV) +9300.OSASCI :\ &FFE3 :CMP #&0D:BNE OSWRCH +9310.OSNEWL :\ &FFE7 :LDA #&0A:JSR OSWRCH +9320.OSWRCR :\ &FFFC :LDA #&0D +9330.OSWRCH :\ &FFFE :JMP (WRCHV) +9340.OSWORD :\ &FFF1 :JMP (WORDV) +9350.OSBYTE :\ &FFF4 :JMP (BYTEV) +9360.OS_CLI :\ &FFF7 :JMP (CLIV) +9370 +9380.NMIV :\ &FFFA :EQUW NMI0 :\ NMI Vector +9390.RESETV :\ &FFFC :EQUW RESET :\ RESET Vector +9400.IRQV :\ &FFFE :EQUW InterruptHandler :\ IRQ Vector +9410]:NEXT +9420OSCLI"Save Client "+STR$~mcode%+" "+STR$~O%+" "+STR$~load%+" "+STR$~load% +9430ON ERROR ON ERROR OFF:END +9440*Quit diff --git a/Tube/TubeClient.txt b/Tube/TubeClient.txt new file mode 100755 index 0000000..4635190 --- /dev/null +++ b/Tube/TubeClient.txt @@ -0,0 +1,940 @@ +10REM >Client/src +20REM Source for 6502 Tube Client +30REM As supplied with External 6502 Second Processor +40REM Code copyright Acorn Computer +50REM Commentary copyright J.G.Harston +60: +70IF PAGE>&8000:LOADATN "OS_GetEnv"TOA$:IFLEFT$(A$,5)<>"B6502":OSCLI"B6502"+MID$(A$,INSTR(A$," ")) +80: +90load%=&F800:DIM mcode% &900 +100: +110USERV=&200: BRKV=&202:IRQ1V=&204:IRQ2V=&206 +120 CLIV=&208:BYTEV=&20A:WORDV=&20C:WRCHV=&20E +130RDCHV=&210:FILEV=&212:ARGSV=&214:BGetV=&216 +140BPutV=&218:GBPBV=&21A:FINDV=&21C: FSCV=&21E +150EVNTV=&220: UPTV=&222: NETV=&224: VduV=&226 +160 KEYV=&228: INSV=&22A: RemV=&22C: CNPV=&22E +170IND1V=&230:IND2V=&232:IND3V=&234 +180: +190ERRBUF=&236:INPBUF=&236 +200: +210: +220REM Memory addresses: +230REM &EE/F = PROG - Current program +240REM &F0/1 = NUM - hex accumulator +250REM &F2/3 = MEMTOP - top of memory +260REM &F4/5 = address of byte transfer address, NMIAddr or ADDR +270REM &F6/7 = ADDR - Data transfer address +280REM &F8/9 = String pointer, OSWORD control block +290REM &FA/B = CTRL - OSFILE, OSGBPB control block, PrText string pointer +300REM &FC = IRQ A store +310REM &FD/E => last error +320REM &FF = Escape flag +330: +340FOR P=0TO1 +350P%=load%:O%=mcode% +360[OPT P*3+4 +370.RESET +380LDX #&00 +390.LF802 +400LDA &FF00,X:STA &FF00,X :\ Copy entry block to RAM +410DEX:BNE LF802 +420LDX #&36 +430.LF80D +440LDA LFF80,X:STA USERV,X :\ Set up default vectors +450DEX:BPL LF80D +460TXS:LDX #&F0 :\ Clear stack +470.LF819 +480LDA &FDFF,X:STA &FDFF,X :\ Copy &FE00-&FEEF to RAM, avoiding +490DEX:BNE LF819 :\ Tube registers at &FEFx +500LDY #RESET AND 255:STY &F8 :\ Point to start of ROM +510LDA #RESET DIV 256:STA &F9 +520.LF82A :\ Copy rest of ROM to RAM +530LDA (&F8),Y:STA (&F8),Y :\ Copy a page to RAM +540INY:BNE LF82A :\ Loop for 256 bytes +550INC &F9:LDA &F9 :\ Inc. address high byte +560CMP #&FE:BNE LF82A :\ Loop from &F800 to &FDFF +570LDX #&10 +580.LF83B +590LDA LF859,X:STA &0100,X :\ Copy jump code to &100 +600DEX:BPL LF83B +610LDA &EE:STA &F6 :\ Copy &EE/F to &F6/7 +620LDA &EF:STA &F7 +630LDA #&00:STA &FF :\ Clear Escape flag +640STA &F2:LDA #&F8:STA &F3 :\ Set memtop to start of ROM at &F800 +650JMP &0100 :\ Jump via low memory to page ROM out +660 +670\ Executed in low memory to page ROM out +680\ -------------------------------------- +690.LF859 +700LDA TubeS1:CLI :\ Check Tube R1 status to page ROM out +710.LF85D +720JMP LF860 :\ Jump to initilise I/O with banner +730 +740.LF860 +750JSR PrText :\ Display startup banner +760EQUB 10:EQUS "Acorn TUBE 6502 64K" +770EQUB 10:EQUB 10:EQUB 13:EQUB 0 +780NOP +790LDA #CmdOSLoop AND 255 :\ Next time RESET is soft entered, +800STA LF85D+1 :\ banner not printed +810LDA #CmdOSLoop DIV 256 +820STA LF85D+2 +830JSR WaitByte :\ Wait for Acknowledge +840CMP #&80:BEQ EnterCode :\ If &80, jump to enter code +850 :\ Otherwise, enter command prompt loop +860 +870\ Minimal Command prompt +880\ ====================== +890.CmdOSLoop +900LDA #ASC"*":JSR OSWRCH :\ Print '*' prompt +910LDX #LF95D AND 255 +920LDY #LF95D DIV 256 +930LDA #&00:JSR OSWORD :\ Read line to INPBUF +940BCS CmdOSEscape +950LDX #INPBUF AND 255 +960LDY #INPBUF DIV 256 :\ Execute command +970JSR OS_CLI:JMP CmdOSLoop :\ and loop back for another +980.CmdOSEscape +990LDA #&7E:JSR OSBYTE :\ Acknowledge Escape state +1000BRK:EQUB 17:EQUS "Escape":BRK +1010 +1020 +1030\ Enter Code pointer to by &F6/7 +1040\ ============================== +1050\ Checks to see if code has a ROM header, and verifies +1060\ it if it has +1070.EnterCode +1080LDA &F6:STA &EE:STA &F2 :\ Set current program and memtop +1090LDA &F7:STA &EF:STA &F3 :\ to address beng entered +1100LDY #&07:LDA (&EE),Y :\ Get copyright offset +1110CLD:CLC:ADC &EE:STA &FD +1120LDA #&00:ADC &EF:STA &FE :\ &FD/E=>copyright message +1130\ +1140\ Now check for &00,"(C)" +1150LDY #&00:LDA (&FD),Y:BNE LF8FA :\ Jump if no initial &00 +1160INY:LDA (&FD),Y:CMP #&28:BNE LF8FA :\ Jump if no '(' +1170INY:LDA (&FD),Y:CMP #&43:BNE LF8FA :\ Jump if no 'C' +1180INY:LDA (&FD),Y:CMP #&29:BNE LF8FA :\ Jump if no ')' +1190\ +1200\ &00,"(C)" exists +1210LDY #&06:LDA (&EE),Y :\ Get ROM type +1220AND #&4F:CMP #&40:BCC NotLanguage :\ b6=0, not a language +1230AND #&0D:BNE Not6502Code :\ type<>0 and <>2, not 6502 code +1240.LF8FA +1250LDA #&01:JMP (&00F2) :\ Enter code with A=1 +1260\ +1270\ Any existing error handler will probably have been overwritten +1280\ Set up new error handler before generating an error +1290.NotLanguage +1300LDA #ErrorHandler AND 255:STA BRKV+0 :\ Claim error handler +1310LDA #ErrorHandler DIV 256:STA BRKV+1 +1320BRK:EQUB 0:EQUS "This is not a language":EQUB 0 +1330 +1340.Not6502Code +1350LDA #ErrorHandler AND 255:STA BRKV+0 :\ Claim error handler +1360LDA #ErrorHandler DIV 256:STA BRKV+1 +1370BRK:EQUB 0:EQUS "I cannot run this code":EQUB 0 +1380 +1390.ErrorHandler +1400LDX #&FF:TXS :\ Clear stack +1410JSR OSNEWL:LDY #&01 +1420.LF94D +1430LDA (&FD),Y:BEQ LF957 :\ Print error string +1440JSR OSWRCH:INY:BNE LF94D +1450.LF957 +1460JSR OSNEWL:JMP CmdOSLoop :\ Jump to command prompt +1470 +1480\ Control block for command prompt input +1490\ -------------------------------------- +1500.LF95D +1510EQUW INPBUF :\ Input text to INPBUF at &236 +1520EQUB &CA :\ Up to &CA characters +1530EQUB &20:EQUB &FF :\ Min=&20, Max=&FF +1540 +1550 +1560\ MOS INTERFACE +1570\ ============= +1580\ +1590\ +1600\ OSWRCH - Send character to output stream +1610\ ======================================== +1620\ On entry, A =character +1630\ On exit, A =preserved +1640\ +1650\ Tube data character -- +1660\ +1670.osWRCH +1680BIT TubeS1 :\ Read Tube R1 status +1690NOP:BVC osWRCH :\ Loop until b6 set +1700STA TubeR1:RTS :\ Send character to Tube R1 +1710 +1720 +1730\ OSRDCH - Wait for character from input stream +1740\ ============================================= +1750\ On exit, A =char, Cy=Escape flag +1760\ +1770\ Tube data &00 -- Carry Char +1780\ +1790.osRDCH +1800LDA #&00:JSR SendCommand :\ Send command &00 - OSRDCH +1810.WaitCarryChar :\ Wait for Carry and A +1820JSR WaitByte:ASL A :\ Wait for carry +1830.WaitByte +1840BIT TubeS2:BPL WaitByte :\ Loop until Tube R2 has data +1850LDA TubeR2 :\ Fetch character +1860.NullReturn +1870RTS +1880 +1890 +1900\ Skip Spaces +1910\ =========== +1920.SkipSpaces1 +1930INY +1940.SkipSpaces +1950LDA (&F8),Y:CMP #&20:BEQ SkipSpaces1 +1960RTS +1970 +1980 +1990\ Scan hex +2000\ ======== +2010.ScanHex +2020LDX #&00:STX &F0:STX &F1 :\ Clear hex accumulator +2030.LF98C +2040LDA (&F8),Y :\ Get current character +2050CMP #&30:BCC LF9B1 :\ <'0', exit +2060CMP #&3A:BCC LF9A0 :\ '0'..'9', add to accumulator +2070AND #&DF:SBC #&07:BCC LF9B1:\ Convert letter, if <'A', exit +2080CMP #&40:BCS LF9B1 :\ >'F', exit +2090.LF9A0 +2100ASL A:ASL A:ASL A:ASL A :\ *16 +2110LDX #&03 :\ Prepare to move 3+1 bits +2120.LF9A6 +2130ASL A:ROL &F0:ROL &F1 :\ Move bits into accumulator +2140DEX:BPL LF9A6 :\ Loop for four bits, no overflow check +2150INY:BNE LF98C :\ Move to next character +2160.LF9B1 +2170RTS +2180 +2190 +2200\ Send string to Tube R2 +2210\ ====================== +2220.SendString +2230STX &F8:STY &F9 :\ Set &F8/9=>string +2240.SendStringF8 +2250LDY #&00 +2260.LF9B8 +2270BIT TubeS2:BVC LF9B8 :\ Wait for Tube R2 free +2280LDA (&F8),Y:STA TubeR2 :\ Send character to Tube R2 +2290INY:CMP #&0D:BNE LF9B8 :\ Loop until sent +2300LDY &F9:RTS :\ Restore Y from &F9 and return +2310 +2320 +2330\ OSCLI - Execute command +2340\ ======================= +2350\ On entry, XY=>command string +2360\ On exit, XY= preserved +2370\ +2380.osCLI +2390PHA:STX &F8:STY &F9 :\ Save A, &F8/9=>command string +2400LDY #&00 +2410.LF9D1 +2420JSR SkipSpaces:INY +2430CMP #ASC"*":BEQ LF9D1 :\ Skip spaces and stars +2440AND #&DF:TAX :\ Ignore case, and save in X +2450LDA (&F8),Y :\ Get next character +2460CPX #ASC"G":BEQ CmdGO :\ Jump to check '*GO' +2470CPX #ASC"H":BNE osCLI_IO :\ Not "H---", jump to pass to Tube +2480CMP #ASC".":BEQ CmdHELP :\ "H.", jump to do *DELETEHIMEM +2490AND #&DF :\ Ignore case +2500CMP #ASC"E":BNE osCLI_IO :\ Not "HE---", jump to pass to Tube +2510INY:LDA (&F8),Y :\ Get next character +2520CMP #ASC".":BEQ CmdHELP :\ "HE.", jump to do *DELETEHIMEM +2530AND #&DF :\ Ignore case +2540CMP #ASC"L":BNE osCLI_IO :\ Not "HEL---", jump to pass to Tube +2550INY:LDA (&F8),Y :\ Get next character +2560CMP #ASC".":BEQ CmdHELP :\ "HEL.", jump to do *DELETEHIMEM +2570AND #&DF :\ Ignore case +2580CMP #ASC"P":BNE osCLI_IO :\ Not "HELP---", jump to pass to Tube +2590INY:LDA (&F8),Y :\ Get next character +2600AND #&DF :\ Ignore case +2610CMP #ASC"A":BCC CmdHELP :\ "HELP" terminated by non-letter, do *DELETEHIMEM +2620CMP #ASC"[":BCC osCLI_IO :\ "HELP" followed by letter, pass to Tube +2630 +2640\ *Help - Display help information +2650\ -------------------------------- +2660.CmdHELP +2670JSR PrText :\ Print help message +2680EQUB 10:EQUB 13:EQUS "6502 TUBE 1.10" +2690EQUB 10:EQUB 13 +2700NOP :\ Continue to pass '*DELETEHIMEM' command to Tube +2710 +2720 +2730\ OSCLI - Send command line to host +2740\ ================================= +2750\ On entry, &F8/9=>command string +2760\ +2770\ Tube data &02 string &0D -- &7F or &80 +2780\ +2790.osCLI_IO +2800LDA #&02:JSR SendCommand :\ Send command &02 - OSCLI +2810JSR SendStringF8 :\ Send command string at &F8/9 +2820.osCLI_Ack +2830JSR WaitByte :\ Wait for acknowledgement +2840CMP #&80:BEQ LFA5C :\ Jump if code to be entered +2850PLA:RTS :\ Restore A and return +2860 +2870 +2880\ *GO - call machine code +2890\ ----------------------- +2900.CmdGO +2910AND #&DF :\ Ignore case +2920CMP #ASC"O":BNE osCLI_IO :\ Not '*GO', jump to pass to Tube +2930JSR SkipSpaces1 :\ Move past any spaces +2940JSR ScanHex:JSR SkipSpaces :\ Read hex value and move past spaces +2950CMP #&0D:BNE osCLI_IO :\ More parameters, pass to Tube to deal with +2960TXA:BEQ LFA5C :\ If no address given, jump to current program +2970LDA &F0:STA &F6 :\ Set program start to address read +2980LDA &F1:STA &F7 +2990 +3000.LFA5C +3010LDA &EF:PHA:LDA &EE:PHA :\ Save current program +3020JSR EnterCode +3030PLA:STA &EE:STA &F2 :\ Restore current program and +3040PLA:STA &EF:STA &F3 :\ set address top of memory to it +3050PLA:RTS +3060 +3070.CheckAck +3080BEQ osCLI_Ack +3090 +3100 +3110\ OSBYTE - Byte MOS functions +3120\ =========================== +3130\ On entry, A, X, Y=OSBYTE parameters +3140\ On exit, A preserved +3150\ If A<&80, X=returned value +3160\ If A>&7F, X, Y, Carry=returned values +3170\ +3180.osBYTE +3190CMP #&80:BCS ByteHigh :\ Jump for long OSBYTEs +3200\ +3210\ Tube data &04 X A -- X +3220\ +3230PHA:LDA #&04 +3240.LFA7A +3250BIT TubeS2:BVC LFA7A :\ Wait for Tube R2 free +3260STA TubeR2 :\ Send command &04 - OSBYTELO +3270.LFA82 +3280BIT TubeS2:BVC LFA82 :\ Wait for Tube R2 free +3290STX TubeR2:PLA :\ Send single parameter +3300.LFA8B +3310BIT TubeS2:BVC LFA8B :\ Wait for Tube R2 free +3320STA TubeR2 :\ Send function +3330.LFA93 +3340BIT TubeS2:BPL LFA93 :\ Wait for Tube R2 data present +3350LDX TubeR2:RTS :\ Get return value +3360 +3370.ByteHigh +3380CMP #&82:BEQ Byte82 :\ Read memory high word +3390CMP #&83:BEQ Byte83 :\ Read bottom of memory +3400CMP #&84:BEQ Byte84 :\ Read top of memory +3410\ +3420\ Tube data &06 X Y A -- Cy Y X +3430\ +3440PHA:LDA #&06 +3450.LFAAB +3460BIT TubeS2:BVC LFAAB :\ Wait for Tube R2 free +3470STA TubeR2 :\ Send command &06 - OSBYTEHI +3480.LFAB3 +3490BIT TubeS2:BVC LFAB3 :\ Wait for Tube R2 free +3500STX TubeR2 :\ Send parameter 1 +3510.LFABB +3520BIT TubeS2:BVC LFABB :\ Wait for Tube R2 free +3530STY TubeR2 :\ Send parameter 2 +3540PLA +3550.LFAC4 +3560BIT TubeS2:BVC LFAC4 :\ Wait for Tube R2 free +3570STA TubeR2 :\ Send function +3580CMP #&8E:BEQ CheckAck :\ If select language, check to enter code +3590CMP #&9D:BEQ LFAEF :\ Fast return with Fast BPUT +3600PHA :\ Save function +3610.LFAD5 +3620BIT TubeS2:BPL LFAD5 :\ Wait for Tube R2 data present +3630LDA TubeR2:ASL A:PLA :\ Get Carry +3640.LFADF +3650BIT TubeS2:BPL LFADF :\ Wait for Tube R2 data present +3660LDY TubeR2 :\ Get return high byte +3670.LFAE7 +3680BIT TubeS2:BPL LFAE7 :\ Wait for Tube R2 data present +3690LDX TubeR2 :\ Get return low byte +3700.LFAEF +3710RTS +3720 +3730.Byte84:LDX &F2:LDY &F3:RTS :\ Read top of memory from &F2/3 +3740.Byte83:LDX #&00:LDY #&08:RTS :\ Read bottom of memory +3750.Byte82:LDX #&00:LDY #&00:RTS :\ Return &0000 as memory high word +3760 +3770 +3780\ OSWORD - Various functions +3790\ ========================== +3800\ On entry, A =function +3810\ XY=>control block +3820\ +3830.osWORD +3840STX &F8:STY &F9 :\ &F8/9=>control block +3850TAY:BEQ RDLINE :\ OSWORD 0, jump to read line +3860PHA:LDY #&08 +3870.LFB09 +3880BIT TubeS2:BVC LFB09 :\ Loop until Tube R2 free +3890STY TubeR2 :\ Send command &08 - OSWORD +3900.LFB11 +3910BIT TubeS2:BVC LFB11 :\ Loop until Tube R2 free +3920STA TubeR2 :\ Send function +3930TAX:BPL WordSendLow :\ Jump with functions<&80 +3940LDY #&00:LDA (&F8),Y :\ Get send block length from control block +3950TAY:JMP WordSend :\ Jump to send control block +3960 +3970.WordSendLow +3980LDY WordLengthsLo-1,X :\ Get send block length from table +3990CPX #&15:BCC WordSend :\ Use this length for OSWORD 1 to &14 +4000LDY #&10 :\ Send 16 bytes for OSWORD &15 to &7F +4010.WordSend +4020BIT TubeS2:BVC WordSend :\ Wait until Tube R2 free +4030STY TubeR2 :\ Send send block length +4040DEY:BMI LFB45 :\ Zero or &81..&FF length, nothing to send +4050.LFB38 +4060BIT TubeS2:BVC LFB38 :\ Wait for Tube R2 free +4070LDA (&F8),Y:STA TubeR2 :\ Send byte from control block +4080DEY:BPL LFB38 :\ Loop for number to be sent +4090.LFB45 +4100TXA:BPL WordRecvLow :\ Jump with functions<&80 +4110LDY #&01:LDA (&F8),Y :\ Get receive block length from control block +4120TAY:JMP WordRecv :\ Jump to receive control block +4130 +4140.WordRecvLow +4150LDY WordLengthsHi-1,X :\ Get receive length from table +4160CPX #&15:BCC WordRecv :\ Use this length for OSWORD 1 to &14 +4170LDY #&10 :\ Receive 16 bytes for OSWORD &15 to &7F +4180.WordRecv +4190BIT TubeS2:BVC WordRecv :\ Wait for Tube R2 free +4200STY TubeR2 :\ Send receive block length +4210DEY:BMI LFB71 :\ Zero of &81..&FF length, nothing to receive +4220.LFB64 +4230BIT TubeS2:BPL LFB64 :\ Wait for Tube R2 data present +4240LDA TubeR2:STA (&F8),Y :\ Get byte to control block +4250DEY:BPL LFB64 :\ Loop for number to receive +4260.LFB71 +4270LDY &F9:LDX &F8:PLA :\ Restore registers +4280RTS +4290 +4300 +4310\ RDLINE - Read a line of text +4320\ ============================ +4330\ On entry, A =0 +4340\ XY=>control block +4350\ On exit, A =undefined +4360\ Y =length of returned string +4370\ Cy=0 ok, Cy=1 Escape +4380\ +4390\ Tube data &0A block -- &FF or &7F string &0D +4400\ +4410.RDLINE +4420LDA #&0A:JSR SendCommand :\ Send command &0A - RDLINE +4430LDY #&04 +4440.LFB7E +4450BIT TubeS2:BVC LFB7E :\ Wait for Tube R2 free +4460LDA (&F8),Y:STA TubeR2 :\ Send control block +4470DEY:CPY #&01:BNE LFB7E :\ Loop for 4, 3, 2 +4480LDA #&07:JSR SendByte :\ Send &07 as address high byte +4490LDA (&F8),Y:PHA :\ Get text buffer address high byte +4500DEY +4510.LFB96 +4520BIT TubeS2:BVC LFB96 :\ Wait for Tube R2 free +4530STY TubeR2 :\ Send &00 as address low byte +4540LDA (&F8),Y:PHA :\ Get text buffer address low byte +4550LDX #&FF:JSR WaitByte :\ Wait for response +4560CMP #&80:BCS RdLineEscape :\ Jump if Escape returned +4570PLA:STA &F8:PLA:STA &F9 :\ Set &F8/9=>text buffer +4580LDY #&00 +4590.RdLineLp +4600BIT TubeS2:BPL RdLineLp :\ Wait for Tube R2 data present +4610LDA TubeR2:STA (&F8),Y :\ Store returned character +4620INY:CMP #&0D:BNE RdLineLp :\ Loop until +4630LDA #&00:DEY:CLC:INX :\ Return A=0, Y=len, X=00, Cy=0 +4640RTS +4650: +4660.RdLineEscape +4670PLA:PLA:LDA #&00 :\ Return A=0, Y=len, X=FF, Cy=1 +4680RTS +4690 +4700 +4710\ OSARGS - Read info on open file +4720\ =============================== +4730\ On entry, A =function +4740\ X =>data word in zero page +4750\ Y =handle +4760\ On exit, A =returned value +4770\ X preserved +4780\ Y preserved +4790\ +4800\ Tube data &0C handle block function -- result block +4810\ +4820.osARGS +4830PHA:LDA #&0C:JSR SendCommand :\ Send command &0C - OSARGS +4840.LFBD2 +4850BIT TubeS2:BVC LFBD2 :\ Loop until Tube R2 free +4860STY TubeR2 :\ Send handle +4870LDA &03,X:JSR SendByte :\ Send data word +4880LDA &02,X:JSR SendByte +4890LDA &01,X:JSR SendByte +4900LDA &00,X:JSR SendByte +4910PLA:JSR SendByte :\ Send function +4920JSR WaitByte:PHA :\ Get and save result +4930JSR WaitByte:STA &03,X :\ Receive data word +4940JSR WaitByte:STA &02,X +4950JSR WaitByte:STA &01,X +4960JSR WaitByte:STA &00,X +4970PLA:RTS :\ Get result back and return +4980 +4990 +5000\ OSFIND - Open of Close a file +5010\ ============================= +5020\ On entry, A =function +5030\ Y =handle or XY=>filename +5040\ On exit, A =zero or handle +5050\ +5060\ Tube data &12 function string &0D -- handle +5070\ &12 &00 handle -- &7F +5080\ +5090.osFIND +5100PHA:LDA #&12:JSR SendCommand :\ Send command &12 - OSFIND +5110PLA:JSR SendByte :\ Send function +5120CMP #&00:BNE OPEN :\ If <>0, jump to do OPEN +5130PHA:TYA:JSR SendByte :\ Send handle +5140JSR WaitByte:PLA:RTS :\ Wait for acknowledge, restore regs and return +5150.OPEN +5160JSR SendString :\ Send pathname +5170JMP WaitByte :\ Wait for and return handle +5180 +5190 +5200\ OSBGet - Get a byte from open file +5210\ ================================== +5220\ On entry, H =handle +5230\ On exit, A =byte Read +5240\ H =preserved +5250\ Cy set if EOF +5260\ +5270\ Tube data &0E handle -- Carry byte +5280\ +5290.osBGET +5300LDA #&0E:JSR SendCommand :\ Send command &0E - OSBGET +5310TYA:JSR SendByte :\ Send handle +5320JMP WaitCarryChar :\ Jump to wait for Carry and byte +5330 +5340 +5350\ OSBPut - Put a byte to an open file +5360\ =================================== +5370\ On entry, A =byte to write +5380\ Y =handle +5390\ On exit, A =preserved +5400\ Y =preserved +5410\ +5420\ Tube data &10 handle byte -- &7F +5430\ +5440.osBPUT +5450PHA:LDA #&10:JSR SendCommand :\ Send command &10 - OSBPUT +5460TYA:JSR SendByte :\ Send handle +5470PLA:JSR SendByte :\ Send byte +5480PHA:JSR WaitByte:PLA:RTS :\ Wait for acknowledge and return +5490 +5500 +5510\ Send a byte to Tube R2 +5520\ ====================== +5530.SendCommand +5540.SendByte +5550BIT TubeS2:BVC SendByte :\ Wait for Tube R2 free +5560STA TubeR2:RTS :\ Send byte to Tube R2 +5570 +5580 +5590\ OSFILE - Operate on whole files +5600\ =============================== +5610\ On entry, A =function +5620\ XY=>control block +5630\ On exit, A =result +5640\ control block updated +5650\ +5660\ Tube data &14 block string function -- result block +5670\ +5680.osFILE +5690STY &FB:STX &FA :\ &FA/B=>control block +5700PHA:LDA #&14:JSR SendCommand :\ Send command &14 - OSFILE +5710LDY #&11 +5720.LFC5F +5730LDA (&FA),Y:JSR SendByte :\ Send control block +5740DEY:CPY #&01:BNE LFC5F :\ Loop for &11..&02 +5750DEY:LDA (&FA),Y:TAX +5760INY:LDA (&FA),Y:TAY :\ Get pathname address to XY +5770JSR SendString :\ Send pathname +5780PLA:JSR SendByte :\ Send function +5790JSR WaitByte:PHA :\ Wait for result +5800LDY #&11 +5810.LFC7E +5820JSR WaitByte:STA (&FA),Y :\ Get control block back +5830DEY:CPY #&01:BNE LFC7E :\ Loop for &11..&02 +5840LDY &FB:LDX &FA :\ Restore registers +5850PLA:RTS :\ Get result and return +5860 +5870 +5880\ OSGBPB - Multiple byte Read and write +5890\ ===================================== +5900\ On entry, A =function +5910\ XY=>control block +5920\ On exit, A =returned value +5930\ control block updated +5940\ +5950\ Tube data &16 block function -- block Carry result +5960\ +5970.osGBPB +5980STY &FB:STX &FA :\ &FA/B=>control block +5990PHA:LDA #&16:JSR SendCommand :\ Send command &16 - OSGBPB +6000LDY #&0C +6010.LFC9A +6020LDA (&FA),Y:JSR SendByte :\ Send control block +6030DEY:BPL LFC9A :\ Loop for &0C..&00 +6040PLA:JSR SendByte :\ Send function +6050LDY #&0C +6060.LFCA8 +6070JSR WaitByte:STA (&FA),Y :\ Get control block back +6080DEY:BPL LFCA8 :\ Loop for &0C..&00 +6090LDY &FB:LDX &FA :\ Restore registers +6100JMP WaitCarryChar :\ Jump to get Carry and result +6110 +6120 +6130.Unsupported +6140BRK:EQUB 255:EQUS "Bad":EQUB 0 +6150 +6160 +6170\ OSWORD control block lengths +6180\ ============================ +6190.WordLengthsLo +6200EQUB &00:EQUB &05:EQUB &00:EQUB &05 +6210EQUB &02:EQUB &05:EQUB &08:EQUB &0E +6220EQUB &04:EQUB &01:EQUB &01:EQUB &05 +6230EQUB &00:EQUB &01:EQUB &20:EQUB &10 +6240EQUB &0D:EQUB &00:EQUB &04:EQUB &80 +6250.WordLengthsHi +6260EQUB &05:EQUB &00:EQUB &05:EQUB &00 +6270EQUB &05:EQUB &00:EQUB &00:EQUB &00 +6280EQUB &05:EQUB &09:EQUB &05:EQUB &00 +6290EQUB &08:EQUB &18:EQUB &00:EQUB &01 +6300EQUB &0D:EQUB &80:EQUB &04:EQUB &80 +6310 +6320 +6330\ Interrupt Handler +6340\ ================= +6350.InterruptHandler +6360STA &FC:PLA:PHA :\ Save A, get flags from stack +6370AND #&10:BNE BRKHandler :\ If BRK, jump to BRK handler +6380JMP (IRQ1V) :\ Continue via IRQ1V handler +6390 +6400.IRQ1Handler +6410BIT TubeS4:BMI LFD3F :\ If data in Tube R4, jump to process errors and transferes +6420BIT TubeS1:BMI LFD18 :\ If data in Tube R1, jump to process Escape and Events +6430JMP (IRQ2V) :\ Pass on to IRQ2V +6440 +6450.BRKHandler +6460TXA:PHA :\ Save X +6470TSX:LDA &0103,X :\ Get address from stack +6480CLD:SEC:SBC #&01:STA &FD +6490LDA &0104,X:SBC #&00:STA &FE :\ &FD/E=>after BRK opcode +6500PLA:TAX:LDA &FC :\ Restore X, get saved A +6510CLI:JMP (BRKV) :\ Restore IRQs, jump to Error Handler +6520 +6530 +6540\ Interrupt generated by data in Tube R1 +6550\ -------------------------------------- +6560.LFD18 +6570LDA TubeR1:BMI LFD39 :\ b7=1, jump to set Escape state +6580TYA:PHA:TXA:PHA :\ Save registers +6590JSR LFE80:TAY :\ Get Y parameter from Tube R1 +6600JSR LFE80:TAX :\ Get X parameter from Tube R1 +6610JSR LFE80 :\ Get event number from Tube R1 +6620JSR LFD36:PLA:TAX:PLA:TAY :\ Dispatch event, restore registers +6630LDA &FC:RTI :\ Restore A, return from interrupt +6640.LFD36 +6650JMP (EVNTV) +6660.LFD39 +6670ASL A:STA &FF :\ Set Escape flag from b6 +6680LDA &FC:RTI :\ Restore A, return from interrupt +6690 +6700 +6710\ Interrupt generated by data in Tube R4 +6720\ -------------------------------------- +6730.LFD3F +6740LDA TubeR4:BPL LFD65 :\ b7=0, jump for data transfer +6750CLI +6760.LFD45 +6770BIT TubeS2:BPL LFD45 :\ Wait for data in Tube R2 +6780LDA TubeR2 +6790LDA #&00:STA ERRBUF:TAY :\ Store BRK opcode in error buffer +6800JSR WaitByte:STA ERRBUF+1 :\ Get error number +6810.LFD59 +6820INY:JSR WaitByte :\ Store bytes fetched from Tube R2 +6830STA ERRBUF+1,Y:BNE LFD59 :\ Loop until final zero +6840JMP ERRBUF :\ Jump to error block to generate error +6850 +6860\ Data transfer initiated by IRQ via Tube R4 +6870\ ------------------------------------------ +6880.LFD65 +6890STA NMIV+0:TYA:PHA :\ Save transfer type, save Y +6900LDY NMIV+0 :\ Get transfer type back +6910LDA LFE70,Y:STA NMIV+0 :\ get NMI routine address from table +6920LDA LFE78,Y:STA NMIV+1 :\ and point NMIV to it +6930LDA LFE60,Y:STA &F4 :\ Point &F4/5 to transfer address field +6940LDA LFE68,Y:STA &F5 +6950.LFD83 +6960BIT TubeS4:BPL LFD83 :\ Wait until Tube R4 data present +6970LDA TubeR4 :\ Get called ID from Tube R4 +6980CPY #&05:BEQ LFDE7 :\ If 'TubeRelease', jump to exit +6990TYA:PHA:LDY #&01 :\ Save transfer type +7000.LFD93 +7010BIT TubeS4:BPL LFD93 :\ Wait for Tube R4 data present +7020LDA TubeR4 :\ Fetch and disgard address byte 4 +7030.LFD9B +7040BIT TubeS4:BPL LFD9B :\ Wait for Tube R4 data present +7050LDA TubeR4 :\ Fetch and disgard address byte 3 +7060.LFDA3 +7070BIT TubeS4:BPL LFDA3 :\ Wait for Tube R4 data present +7080LDA TubeR4:STA (&F4),Y:DEY :\ Fetch address byte 2, store in address +7090.LFDAE +7100BIT TubeS4:BPL LFDAE :\ Wait for Tube R4 data present +7110LDA TubeR4:STA (&F4),Y :\ Fetch address byte 1, store in address +7120BIT TubeR3:BIT TubeR3 :\ Read from Tube R3 twice +7130.LFDBE +7140BIT TubeS4:BPL LFDBE :\ Wait for Tube R4 data present +7150LDA TubeR4:PLA :\ Get sync byte from Tube R4 +7160CMP #&06:BCC LFDE7 :\ Exit if not 256-byte transfers +7170BNE LFDEC :\ Jump with 256-byte read +7180 +7190\ Send 256 bytes to Tube via R3 +7200\ ----------------------------- +7210LDY #&00 +7220.LFDCF +7230LDA TubeS3:AND #&80:BPL LFDCF:\ Wait for Tube R3 free +7240.NMI6Addr +7250LDA &FFFF,Y:STA TubeR3 :\ Fetch byte and send to Tube R3 +7260INY:BNE LFDCF :\ Loop for 256 bytes +7270.LFDDF +7280BIT TubeS3:BPL LFDDF :\ Wait for Tube R3 free +7290STA TubeR3 :\ Send final sync byte +7300.LFDE7 +7310PLA:TAY:LDA &FC:RTI :\ Restore registers and return +7320 +7330\ Read 256 bytes from Tube via R3 +7340\ ------------------------------- +7350.LFDEC +7360LDY #&00 +7370.LFDEE +7380LDA TubeS3:AND #&80:BPL LFDEE:\ Wait for Tube R3 data present +7390LDA TubeR3 :\ Fetch byte from Tube R3 +7400.NMI7Addr +7410STA &FFFF,Y:INY:BNE LFDEE :\ Store byte and loop for 256 bytes +7420BEQ LFDE7 :\ Jump to restore registers and return +7430 +7440\ Transfer 0 - Transfer single byte to Tube +7450\ ----------------------------------------- +7460.NMI0 +7470PHA :\ Save A +7480.NMI0Addr +7490LDA &FFFF:STA TubeR3 :\ Get byte and send to Tube R3 +7500INC NMI0Addr+1:BNE LFE0F :\ Increment transfer address +7510INC NMI0Addr+2 +7520.LFE0F +7530PLA:RTI :\ Restore A and return +7540 +7550\ Transfer 1 - Transfer single byte from Tube +7560\ ------------------------------------------- +7570.NMI1 +7580PHA:LDA TubeR3 :\ Save A, get byte from Tube R3 +7590.NMI1Addr +7600STA &FFFF :\ Store byte +7610INC NMI1Addr+1:BNE LFE20 :\ Increment transfer address +7620INC NMI1Addr+2 +7630.LFE20 +7640PLA:RTI :\ Restore A and return +7650 +7660\ Transfer 2 - Transfer two bytes to Tube +7670\ --------------------------------------- +7680.NMI2 +7690PHA:TYA:PHA:LDY #&00 :\ Save registers +7700LDA (&F6),Y:STA TubeR3 :\ Get byte and send to Tube R3 +7710INC &F6:BNE LFE32:INC &F7 :\ Increment transfer address +7720.LFE32 +7730LDA (&F6),Y:STA TubeR3 :\ Get byte and send to Tube R3 +7740INC &F6:BNE LFE3D:INC &F7 :\ Increment transfer address +7750.LFE3D +7760PLA:TAY:PLA:RTI :\ Restore registers and return +7770 +7780\ Transfer 3 - Transfer two bytes from Tube +7790\ ----------------------------------------- +7800.NMI3 +7810PHA:TYA:PHA:LDY #&00 :\ Save registers +7820LDA TubeR3:STA (&F6),Y :\ Get byte from Tube R3 and store +7830INC &F6:BNE LFE51:INC &F7 :\ Increment transfer address +7840.LFE51 +7850LDA TubeR3:STA (&F6),Y :\ Get byte from Tube R3 and store +7860INC &F6:BNE LFE5C:INC &F7 :\ Increment transfer address +7870.LFE5C +7880PLA:TAY:PLA:RTI :\ Restore registers and return +7890 +7900\ Data transfer address pointers +7910\ ------------------------------ +7920.LFE60 +7930EQUB (NMI0Addr+1) AND 255:EQUB (NMI1Addr+1) AND 255 +7940EQUB &00F6 AND 255 :EQUB &00F6 AND 255 +7950EQUB &00F6 AND 255 :EQUB &00F6 AND 255 +7960EQUB (NMI6Addr+1) AND 255:EQUB (NMI7Addr+1) AND 255 +7970.LFE68 +7980EQUB (NMI0Addr+1) DIV 256:EQUB (NMI1Addr+1) DIV 256 +7990EQUB &00F6 DIV 256 :EQUB &00F6 DIV 256 +8000EQUB &00F6 DIV 256 :EQUB &00F6 DIV 256 +8010EQUB (NMI6Addr+1) DIV 256:EQUB (NMI7Addr+1) DIV 256 +8020 +8030\ Data transfer routine addresses +8040\ ------------------------------- +8050.LFE70 +8060EQUB NMI0 AND 255 :EQUB NMI1 AND 255 +8070EQUB NMI2 AND 255 :EQUB NMI3 AND 255 +8080EQUB NMI_Ack AND 255:EQUB NMI_Ack AND 255 +8090EQUB NMI_Ack AND 255:EQUB NMI_Ack AND 255 +8100.LFE78 +8110EQUB NMI0 DIV 256 :EQUB NMI1 DIV 256 +8120EQUB NMI2 DIV 256 :EQUB NMI3 DIV 256 +8130EQUB NMI_Ack DIV 256:EQUB NMI_Ack DIV 256 +8140EQUB NMI_Ack DIV 256:EQUB NMI_Ack DIV 256 +8150 +8160 +8170\ Wait for byte in Tube R1 while allowing requests via Tube R4 +8180\ ============================================================ +8190.LFE80 +8200BIT TubeS1:BMI LFE94 :\ If data in Tube R1, jump to fetch it +8210.LFE85 +8220BIT TubeS4 :\ Check if data present in Tube R4 +8230BPL LFE80 :\ If nothing there, jump back to check Tube R1 +8240LDA &FC :\ Save IRQ's A store in A register +8250PHP:CLI:PLP :\ Allow an IRQ through to process R4 request +8260STA &FC:JMP LFE80 :\ Restore IRQ's A store and jump back to check R1 +8270.LFE94 +8280LDA TubeR1:RTS :\ Fetch byte from Tube R1 and return +8290 +8300 +8310\ Print embedded string +8320\ ===================== +8330.PrText +8340PLA:STA &FA:PLA:STA &FB :\ &FA/B=>embedded string +8350LDY #&00 +8360.LFEA0 +8370INC &FA:BNE LFEA6:INC &FB :\ Increment address +8380.LFEA6 +8390LDA (&FA),Y:BMI LFEB0 :\ Get character, exit if >&7F +8400JSR OSWRCH:JMP LFEA0 :\ Print character and loop back for more +8410.LFEB0 +8420JMP (&00FA) :\ Jump back to code after string +8430 +8440 +8450\ Null NMI code +8460\ ------------- +8470.NMI_Ack +8480STA TubeR3:RTI :\ Store to TubeR3 to acknowlege NMI +8490 +8500 +8510\ Spare space +8520\ =========== +8530EQUS STRING$(&FEF0-P%,CHR$255) +8540 +8550 +8560\ I/O Space +8570\ ========= +8580EQUS STRING$(8,CHR$0) +8590 +8600\ Tube I/O Registers +8610\ ================== +8620.TubeS1 :\ &FEF8 :EQUB 0 +8630.TubeR1 :\ &FEF9 :EQUB 0 +8640.TubeS2 :\ &FEFA :EQUB 0 +8650.TubeR2 :\ &FEFB :EQUB 0 +8660.TubeS3 :\ &FEFC :EQUB 0 +8670.TubeR3 :\ &FEFD :EQUB 0 +8680.TubeS4 :\ &FEFE :EQUB 0 +8690.TubeR4 :\ &FEFF :EQUB 0 +8700 +8710 +8720\ Spare space +8730\ =========== +8740.LFF00 +8750EQUS STRING$(&FF80-P%,CHR$255) +8760 +8770 +8780\ DEFAULT VECTOR TABLE +8790\ ==================== +8800.LFF80 +8810EQUW Unsupported :\ &200 - USERV +8820EQUW ErrorHandler :\ &202 - BRKV +8830EQUW IRQ1Handler :\ &204 - IRQ1V +8840EQUW Unsupported :\ &206 - IRQ2V +8850EQUW osCLI :\ &208 - CLIV +8860EQUW osBYTE :\ &20A - BYTEV +8870EQUW osWORD :\ &20C - WORDV +8880EQUW osWRCH :\ &20E - WRCHV +8890EQUW osRDCH :\ &210 - RDCHV +8900EQUW osFILE :\ &212 - FILEV +8910EQUW osARGS :\ &214 - ARGSV +8920EQUW osBGET :\ &216 - BGetV +8930EQUW osBPUT :\ &218 - BPutV +8940EQUW osGBPB :\ &21A - GBPBV +8950EQUW osFIND :\ &21C - FINDV +8960EQUW Unsupported :\ &21E - FSCV +8970EQUW NullReturn :\ &220 - EVNTV +8980EQUW Unsupported :\ &222 - UPTV +8990EQUW Unsupported :\ &224 - NETV +9000EQUW Unsupported :\ &226 - VduV +9010EQUW Unsupported :\ &228 - KEYV +9020EQUW Unsupported :\ &22A - INSV +9030EQUW Unsupported :\ &22C - RemV +9040EQUW Unsupported :\ &22E - CNPV +9050EQUW NullReturn :\ &230 - IND1V +9060EQUW NullReturn :\ &232 - IND2V +9070EQUW NullReturn :\ &234 - IND3V +9080 +9090.VECDEF :\ &FFB6 :EQUB &36:EQUW LFF80 +9100.OSXXXX :\ &FFB9 :JMP Unsupported +9110.OSXXXX :\ &FFBC :JMP Unsupported +9120.OSXXXX :\ &FFBF :JMP Unsupported +9130.OSXXXX :\ &FFC2 :JMP Unsupported +9140.OSXXXX :\ &FFC5 :JMP Unsupported +9150.NVRDCH :\ &FFC8 :JMP osRDCH +9160.NVWRCH :\ &FFCB :JMP osWRCH +9170 +9180.OSFIND :\ &FFCE :JMP (FINDV) +9190.OSGBPB :\ &FFD1 :JMP (GBPBV) +9200.OSBPUT :\ &FFD4 :JMP (BPutV) +9210.OSBGET :\ &FFD7 :JMP (BGetV) +9220.OSARGS :\ &FFDA :JMP (ARGSV) +9230.OSFILE :\ &FFDD :JMP (FILEV) +9240 +9250.OSRDCH :\ &FFE0 :JMP (RDCHV) +9260.OSASCI :\ &FFE3 :CMP #&0D:BNE OSWRCH +9270.OSNEWL :\ &FFE7 :LDA #&0A:JSR OSWRCH +9280.OSWRCR :\ &FFEC :LDA #&0D +9290.OSWRCH :\ &FFEE :JMP (WRCHV) +9300.OSWORD :\ &FFF1 :JMP (WORDV) +9310.OSBYTE :\ &FFF4 :JMP (BYTEV) +9320.OS_CLI :\ &FFF7 :JMP (CLIV) +9330 +9340.NMIV :\ &FFFA :EQUW NMI0 :\ NMI Vector +9350.RESETV :\ &FFFC :EQUW RESET :\ RESET Vector +9360.IRQV :\ &FFFE :EQUW InterruptHandler :\ IRQ Vector +9370]:NEXT +9380OSCLI"Save Client "+STR$~mcode%+" "+STR$~O%+" "+STR$~load%+" "+STR$~load% +9390ON ERROR ON ERROR OFF:END +9400*Quit diff --git a/Tube/tube_121.txt b/Tube/tube_121.txt new file mode 100755 index 0000000..c394410 --- /dev/null +++ b/Tube/tube_121.txt @@ -0,0 +1,1948 @@ +REM >Tube121Src +REM +REM +REM This is Acorn's Tube OS 1.10, plus several improvements : +REM +REM - Implemented most obvious and some less obvious optimisations, primarily by +REM taking advantage of 65C02 specific instructions (which the original code did +REM not do at all). +REM - Hex digits were improperly parsed, e.g. '@' would be interpreted as '9'. +REM - E.g. '*GOA' was mistakenly interpreted as '*GO A' (it is now rejected as an +REM unknown command, as it should have been). +REM - *Help followed by a(ny) keyword caused the 'TUBE' line to be displayed (it +REM should only be displayed if the keyword is recognized or absent). +REM - The carry flag on entering an executable was undefined (it should have been +REM clear for entering due to reset (power on or BREAK), and set otherwise). +REM - OSWORD 5 sends 4 bytes, OSWORD 14 sends 8 (to support reason code 2). +REM - Added the *GOS command, which transfers control to the supervisor prompt. +REM - Moved some reset-time only code to the bottom 2 KB of the ROM, to make more +REM room for the runtime code in the top 2 KB. +REM +REM Base code by Acorn. Improvements by John Kortink, © Zeridajh 2009..2014. +REM +REM Run on 6502 grokking BASIC V, e.g. Basic6502 (google 'Kortink Basic6502') +REM +REM + +`Source_Version$ = "1.21" + +DIM object_code% 64 * 1024 + +PROC`6502code_preassemble + +PRINT '"Assembling ... "; + +FOR `Assembly_Pass% = 1 TO 2 + + `P = %10100 OR (`Assembly_Pass% - 1) << 1 + + P% = rom_boot% + O% = object_code% + rom_boot% + + PROC`6502code_code + +NEXT + +PRINT "Saving ... "; + +SYS "OS_File", 10, "TubeOS121", &FFD,, object_code% + &F000, object_code% + &10000 + +PRINT ;"Done"' + +END + + + +DEFPROC`6502code_preassemble + +REM +REM +REM Miscellaneous +REM +REM + +rom_boot% = &F000 +rom_copy% = &F800 + +FOR A% = object_code% TO A% + &FFFF:?A% = &FF:NEXT + +default_oshwm% = &0800 +default_himem% = &F800 + +mem_ptr_size% = 2 + +REM +REM +REM Register addresses +REM +REM + +tube_1_flag% = &FEF8 +tube_1_data% = &FEF9 +tube_2_flag% = &FEFA +tube_2_data% = &FEFB +tube_3_flag% = &FEFC +tube_3_data% = &FEFD +tube_4_flag% = &FEFE +tube_4_data% = &FEFF + +REM +REM +REM Software vectors +REM +REM + +sw_vectors% = &200 + +osvec_brk% = &202 +osvec_irq1% = &204 +osvec_irq2% = &206 +osvec_cli% = &208 +osvec_byte% = &20A +osvec_word% = &20C +osvec_wrch% = &20E +osvec_rdch% = &210 +osvec_file% = &212 +osvec_args% = &214 +osvec_bget% = &216 +osvec_bput% = &218 +osvec_gbpb% = &21A +osvec_find% = &21C +osvec_evnt% = &220 + +REM +REM +REM Tube call reason codes +REM +REM + +tubrc_osrdch% = &00 +tubrc_oscli% = &02 +tubrc_osbyte_lo% = &04 +tubrc_osbyte_hi% = &06 +tubrc_osword_nn% = &08 +tubrc_osword_00% = &0A +tubrc_osargs% = &0C +tubrc_osbget% = &0E +tubrc_osbput% = &10 +tubrc_osfind% = &12 +tubrc_osfile% = &14 +tubrc_osgbpb% = &16 + +REM +REM +REM Workspace +REM +REM + +tubos_nmiptrad = &EE +tubos_running = &F0 +tubos_himem = &F2 +tubos_transad = &F4 +tubos_genptr1 = &F8 +tubos_genptr2 = &FA +tubos_hexvalue = &FA +tubos_irqa = &FC +tubos_lastbrk = &FD +tubos_escape = &FF + +tubos_strbuf_first = &236 +tubos_strbuf_final = &2FF + +tubos_genva2a = tubos_genptr2 + 0 +tubos_genva2b = tubos_genptr2 + 1 + +ENDPROC + + + +DEFPROC`6502code_code + +[OPT `P + + + +\ +\ +\ Co-pro initialisation +\ +\ + SEI \ Disable interrupts +\ + LDX #&FF \ Initialise processor stack + TXS +\ + JSR copin_copy_os_code \ Copy operating system code +\ + LDA #hwrun_rst MOD 256 \ Change reset vector from 'hard' to 'soft' + STA hwvec_rst+0 + LDA #hwrun_rst DIV 256 + STA hwvec_rst+1 +\ + LDA #swrun_wrch MOD 256 \ Pre-set OSWRCHV (for boot up message) + STA osvec_wrch%+0 + LDA #swrun_wrch DIV 256 + STA osvec_wrch%+1 +\ + LDX #copin_join_end - copin_join - 1 \ Copy 'join' routine +\ +.copin_cpjoi +\ + LDA copin_join,X + STA &100,X +\ + DEX + BPL copin_cpjoi +\ + JMP &100 \ Execute it +\ +\ +\ +.copin_join +\ + LDA tube_1_flag% \ Switch from ROM -> RAM +\ + JSR display_string \ Display boot up message +\ + EQUB &0A + EQUS "Acorn TUBE 65C02 64K" + EQUB &0A:EQUB &0A:EQUB &0D + NOP +\ + JMP (hwvec_rst) \ Continue with reset code +\ +.copin_join_end +\ +\ +\ +.copin_copy_os_code +\ + LDA #rom_copy% DIV 256 \ Copy code (ROM -> RAM) + STA tubos_genptr1+1 +\ + LDY #&00 + STY tubos_genptr1+0 +\ +.copin_cocod_page +\ + LDA tubos_genptr1+1 +\ + LDX #&00 +\ + CMP #&FE + BNE copin_cocod_byte +\ + LDX #&F0 +\ +.copin_cocod_byte +\ + LDA (tubos_genptr1),Y + STA (tubos_genptr1),Y +\ + INY + DEX + BNE copin_cocod_byte +\ + INC tubos_genptr1+1 + BNE copin_cocod_page +\ + RTS + + + +] + +D% = rom_copy% - P%:P% += D%:O% += D% + +[OPT `P + + + +.hwrun_rst +\ + LDX #std_swrun_end - std_swrun - 1 \ Initialise software vectors +\ +.hwrst_swrun +\ + LDA std_swrun,X + STA sw_vectors%,X +\ + DEX + BPL hwrst_swrun +\ + TXS \ Initialise processor stack +\ + STZ tubos_escape \ Initialise global variables +\ + STZ tubos_himem+0 + LDA #default_himem% DIV 256 + STA tubos_himem+1 +\ + LDA tubos_running+0 \ (re-enter previous app by default) + STA tubos_transad+0 + LDA tubos_running+1 + STA tubos_transad+1 +\ + CLI \ Bring on the IRQs +\ +.hwrst_softjmp +\ + BRA supervisor_cli \ On hard reset, continue (but see below) +\ +]:hwrst_softjmp_off% = O%?-1:O%?-1 = 0:[OPT `P +\ + LDA #0 \ Signal 'parasite initialised' + JSR os_wrch% \ (ends Tube main initialisation) +\ + LDA #hwrst_softjmp_off% \ On soft reset, to supervisor (see above) + STA hwrst_softjmp+1 +\ + JSR a_from_fifo_2 \ New or previous app to (re-)enter ? + CMP #&80 + BEQ running_executable_hard \ Yes, do so (otherwise to supervisor) + + + +.supervisor_cli +\ + LDA #ASC"*" \ Display supervisor prompt + JSR os_wrch% +\ + LDX #supervisor_osword_0 MOD 256 \ Receive OSCLI command + LDY #supervisor_osword_0 DIV 256 + LDA #0 + JSR os_word% +\ + JSR escape_if_c +\ + LDX #tubos_strbuf_first MOD 256 \ Execute OSCLI command + LDY #tubos_strbuf_first DIV 256 + JSR os_cli% +\ + BRA supervisor_cli \ Ad infinitum + + + +.running_executable_hard +\ + CLC \ Flag 'entered from reset' +\ + BRA running_executable \ Continue +\ +.running_executable_soft +\ + SEC \ Flag 'not entered from reset' +\ +.running_executable +\ + PHP \ Remember 'entered from' flag +\ + LDA tubos_transad+0 \ Executable becomes new app + STA tubos_running+0 + STA tubos_himem+0 + LDA tubos_transad+1 + STA tubos_running+1 + STA tubos_himem+1 +\ + LDY #7 \ Executable has ROM header ? + LDA (tubos_running),Y + TAY +\ + LDX #3 +\ +.runex_copch +\ + LDA (tubos_running),Y + CMP runex_copyright,X + BNE runex_enter \ (no) +\ + INY + DEX + BPL runex_copch +\ + CLC \ ROM's (c) message is 'last BRK' + LDY #7 + LDA tubos_running+0 + ADC (tubos_running),Y + STA tubos_lastbrk+0 + LDA tubos_running+1 + ADC #0 + STA tubos_lastbrk+1 +\ + DEY \ ROM is 6502 coded language ? + LDA (tubos_running),Y + BIT #1<<6 + BEQ runex_error_notalanguage \ (no, not a language) + BIT #%1101 + BNE runex_error_cannotruncode \ (no, not 6502 coded) +\ +.runex_enter +\ + PLP \ Enter executable + LDA #1 \ (may not return) + JMP (tubos_running) +\ +.runex_error_notalanguage +\ + JSR set_default_brk_handler \ Throw 'not a language' error +\ + BRK + EQUB 0 + EQUS "This is not a language" + EQUB 0 +\ +.runex_error_cannotruncode +\ + JSR set_default_brk_handler \ Throw 'not 6502 coded' error +\ + BRK + EQUB 0 + EQUS "I cannot run this code" + EQUB 0 +\ +\ +\ +.runex_copyright +\ + EQUS ")C(":EQUB 0 + + + +.set_default_brk_handler +\ + LDA #swrun_brk MOD 256 \ Restore default BRK handler + STA osvec_brk%+0 \ (current one may be unusable) + LDA #swrun_brk DIV 256 + STA osvec_brk%+1 +\ + RTS + + + +.display_string +\ + PLA \ Display in-line string + STA tubos_genptr2+0 + PLA + STA tubos_genptr2+1 +\ +.dinls_char +\ + INC tubos_genptr2+0 + BNE `generated_label_1 + INC tubos_genptr2+1 + .`generated_label_1 +\ + LDA (tubos_genptr2) + BMI dinls_done \ (top-bit-set terminated) +\ + JSR os_wrch% +\ + BRA dinls_char +\ +.dinls_done +\ + JMP (tubos_genptr2) + + + +.transmit_string_xy +\ + STX tubos_genptr1+0 \ Transmit string @yyxx to host + STY tubos_genptr1+1 +\ +.transmit_string_ptr1 +\ + LDY #0 \ Transmit string @ptr1 to host +\ +.trstr_char +\ + LDA (tubos_genptr1),Y + FNtube_2_wait_put + STA tube_2_data% +\ + INY +\ + CMP #&0D \ (CR terminated) + BNE trstr_char +\ + LDY tubos_genptr1+1 +\ + RTS + + + +.parse_next_nosp +\ + INY \ Skip current character +\ +.parse_curr_nosp +\ + LDA (tubos_genptr1),Y \ Skip subsequent spaces +\ + CMP #ASC" " + BEQ parse_next_nosp +\ + CMP #&0D \ Flag 'non-space is CR' +\ + RTS + + + +.parse_hex_value +\ + LDX #&00 \ Initialise hex value accumulator + STX tubos_hexvalue+0 \ (and X = 0 means 'no digits' !) + STX tubos_hexvalue+1 +\ +.pahex_char +\ + LDA (tubos_genptr1),Y \ Current character +\ + CMP #ASC"0" \ Verify as hex digit + BCC pahex_done + CMP #ASC"9"+1 + BCC pahex_nibbl + AND #&DF + CMP #ASC"A" + BCC pahex_done + CMP #ASC"F"+1 + BCS pahex_done + SBC #ASC"A"-(ASC"9"+1)-1 +\ +.pahex_nibbl +\ + ASL A \ Update hex value + ASL A + ASL A + ASL A +\ + LDX #3 +\ +.pahex_shift +\ + ASL A + ROL tubos_hexvalue+0 + ROL tubos_hexvalue+1 +\ + DEX + BPL pahex_shift +\ + INY \ Next character + BNE pahex_char +\ +.pahex_done +\ + RTS + + + +.swrun_brk +\ + LDX #&FF \ Initialise processor stack + TXS \ (we won't be returning) +\ + JSR os_newl% \ Display the error message +\ + LDY #1 +\ +.swbrk_char +\ + LDA (tubos_lastbrk),Y + BEQ swbrk_done +\ + JSR os_wrch% +\ + INY + BNE swbrk_char +\ +.swbrk_done +\ + JSR os_newl% +\ + JMP supervisor_cli \ And enter the supervisor + + + +.swrun_wrch +\ + FNtube_1_wait_put \ Perform OSWRCH + STA tube_1_data% +\ + RTS + + + +.swrun_rdch +\ + LDA #tubrc_osrdch% \ Perform OSRDCH + JSR a_to_fifo_2 + + + +.ca_from_fifo_2 +\ + JSR a_from_fifo_2 \ Receive C and A from host + ASL A + + + +.a_from_fifo_2 +\ + FNtube_2_wait_get \ Receive A from host + LDA tube_2_data% +\ + RTS + + + +.a_to_fifo_2 +\ + FNtube_2_wait_put \ Transmit A to host + STA tube_2_data% +\ + RTS + + + +.blk_to_fifo_2_ypl1 \ Transmit block to host (down from Y to 0) +\ + TYA + TAX + INX +\ +.blk_to_fifo_2 \ Transmit block to host (down from Y, X bytes) +\ + LDA (tubos_genptr2),Y + FNtube_2_wait_put + STA tube_2_data% +\ + DEY + DEX + BNE blk_to_fifo_2 +\ + RTS + + + +.blk_from_fifo_2_ypl1 \ Receive block from host (down from Y to 0) +\ + TYA + TAX + INX +\ +.blk_from_fifo_2 \ Receive block from host (down from Y, X bytes) +\ + FNtube_2_wait_get + LDA tube_2_data% + STA (tubos_genptr2),Y +\ + DEY + DEX + BNE blk_from_fifo_2 +\ + RTS + + + +.swrun_cli +\ + STX tubos_genptr1+0 \ Command line to parse + STY tubos_genptr1+1 +\ + LDY #&FF \ Skip leading spaces and '*'s +\ +.swcli_skpld +\ + JSR parse_next_nosp +\ + CMP #ASC"*" + BEQ swcli_skpld +\ + LDX #&FF \ Check for known commands +\ + DEY + STY tubos_genva2a +\ + STZ tubos_genva2b +\ + BRA swcli_cmd_char +\ +.swcli_cmd_next +\ + INX + LDA star_commands,X + BNE swcli_cmd_next +\ + LDY tubos_genva2a +\ + INC tubos_genva2b +\ +.swcli_cmd_char +\ + INX +\ + LDA star_commands,X + BEQ swcli_cmd_match \ (whole command matched) + BPL swcli_pass_on \ (no more table entries) +\ + LSR A \ (C set if '.' allowed) +\ + INY +\ + EOR (tubos_genptr1),Y + AND #&DF + BEQ swcli_cmd_char +\ + BCC swcli_cmd_next +\ + LDA (tubos_genptr1),Y + CMP #ASC"." + BNE swcli_cmd_next +\ + INY +\ + BRA swcli_cmd_ok +\ +.swcli_cmd_match +\ + INY \ (check for end-of-command) +\ + LDA (tubos_genptr1),Y +\ + AND #&DF + CMP #ASC"A" + BCC swcli_cmd_ok + CMP #ASC"Z"+1 + BCC swcli_pass_on +\ +.swcli_cmd_ok +\ + LDA tubos_genva2b \ Dispatch command code + BEQ swcli_x_help + CMP #1 + BEQ swcli_x_gos +\ +\ +\ +.swcli_x_go +\ + JSR parse_curr_nosp \ Parse () +\ + JSR parse_hex_value +\ + JSR parse_curr_nosp \ No more command arguments +\ + BNE swcli_pass_on \ (else pass on command line) +\ + TXA \ Executable address indicated ? + BEQ swcli_does_run \ No, re-enter the current app +\ + LDA tubos_hexvalue+0 \ Enter the indicated executable + STA tubos_transad+0 + LDA tubos_hexvalue+1 + STA tubos_transad+1 +\ +\ +\ +.swcli_does_run +\ + LDA tubos_running+1 \ Remember current app + PHA + LDA tubos_running+0 + PHA +\ + JSR running_executable_soft \ Enter executable (tentatively) +\ + PLA \ Restore previous app if executable returns + STA tubos_running+0 + STA tubos_himem+0 + PLA + STA tubos_running+1 + STA tubos_himem+1 +\ + RTS +\ +\ +\ +.swcli_x_gos +\ + JMP hwrun_rst \ Enter the supervisor +\ +\ +\ +.swcli_x_help +\ + JSR parse_curr_nosp \ No more command arguments +\ + BNE swcli_pass_on \ (else pass on command line) +\ + JSR display_string \ Display our 'help' message +\ + EQUB &0A:EQUB &0D + EQUS "65C02 TUBE " + `Source_Version$ + EQUB &0A:EQUB &0D + NOP +\ +\ +\ +.swcli_pass_on +\ + LDA #tubrc_oscli% \ Pass command line to host + JSR a_to_fifo_2 +\ + JSR transmit_string_ptr1 +\ +\ +\ +.swcli_may_run +\ + JSR a_from_fifo_2 \ Enter executable as a result ? + CMP #&80 + BEQ swcli_does_run \ Yes, do so +\ + RTS + + + +.swrun_byte +\ + CMP #&80 \ Perform OSBYTE + BCC swbyt_low +\ + CMP #&82 \ ('Read machine high order address') + BEQ swbyt_82 + CMP #&83 \ ('Read top of OS RAM address (OSHWM)') + BEQ swbyt_83 + CMP #&84 \ ('Read bottom of display RAM address (HIMEM)') + BEQ swbyt_84 +\ + PHA +\ + LDA #tubrc_osbyte_hi% + FNtube_2_wait_put + STA tube_2_data% +\ + FNtube_2_wait_put + STX tube_2_data% +\ + FNtube_2_wait_put + STY tube_2_data% +\ + PLA +\ + FNtube_2_wait_put + STA tube_2_data% +\ + CMP #&8E \ ('Enter language ROM') + BEQ swcli_may_run + CMP #&9D \ ('Fast Tube BPUT') + BEQ swbyt_done +\ + PHA +\ + FNtube_2_wait_get + LDA tube_2_data% + ASL A +\ + PLA +\ + FNtube_2_wait_get + LDY tube_2_data% +\ + FNtube_2_wait_get + LDX tube_2_data% +\ +.swbyt_done +\ + RTS +\ +.swbyt_82 +\ + LDX #&00 + LDY #&00 +\ + RTS +\ +.swbyt_83 +\ + LDX #default_oshwm% MOD 256 + LDY #default_oshwm% DIV 256 +\ + RTS +\ +.swbyt_84 +\ + LDX tubos_himem+0 + LDY tubos_himem+1 +\ + RTS +\ +.swbyt_low +\ + PHA +\ + LDA #tubrc_osbyte_lo% + FNtube_2_wait_put + STA tube_2_data% +\ + FNtube_2_wait_put + STX tube_2_data% +\ + PLA +\ + FNtube_2_wait_put + STA tube_2_data% +\ + FNtube_2_wait_get + LDX tube_2_data% +\ + RTS + + + +.swrun_word +\ + STX tubos_genptr2+0 \ Perform OSWORD + STY tubos_genptr2+1 +\ + PHA +\ + TAY \ (0 is special) + BEQ swwor_zero +\ + LDY #tubrc_osword_nn% + FNtube_2_wait_put + STY tube_2_data% +\ + FNtube_2_wait_put + STA tube_2_data% +\ + TAX + BPL swwor_o_table +\ + LDY #0 + LDA (tubos_genptr2),Y + TAY +\ + BRA swwor_o_sized +\ +.swwor_o_table +\ + LDY osword_o_rc2size-1,X +\ + CPX #osword_o_rc2size_end - osword_o_rc2size + 1 + BCC swwor_o_sized +\ + LDY #16 +\ +.swwor_o_sized +\ + FNtube_2_wait_put + STY tube_2_data% +\ + PHX +\ + DEY + BMI swwor_o_done +\ + JSR blk_to_fifo_2_ypl1 +\ +.swwor_o_done +\ + PLX + BPL swwor_i_table +\ + LDY #1 + LDA (tubos_genptr2),Y + TAY +\ + BRA swwor_i_sized +\ +.swwor_i_table +\ + LDY osword_i_rc2size-1,X +\ + CPX #osword_i_rc2size_end - osword_i_rc2size + 1 + BCC swwor_i_sized +\ + LDY #16 +\ +.swwor_i_sized +\ + FNtube_2_wait_put + STY tube_2_data% +\ + DEY + BMI swwor_i_done +\ + JSR blk_from_fifo_2_ypl1 +\ +.swwor_i_done +\ + LDX tubos_genptr2+0 + LDY tubos_genptr2+1 +\ + PLA +\ + RTS +\ +.swwor_zero +\ + LDA #tubrc_osword_00% + JSR a_to_fifo_2 +\ + LDX #3 + LDY #4 + JSR blk_to_fifo_2 +\ + LDA #&07 \ (specify their, not our buffer) + JSR a_to_fifo_2 + LDA #&00 + JSR a_to_fifo_2 +\ + JSR a_from_fifo_2 + ASL A + BCS swwor_0_abort +\ + LDA (tubos_genptr2) \ (copy the string to our buffer) + STA tubos_genptr1+0 + LDA (tubos_genptr2),Y + STA tubos_genptr1+1 +\ + LDY #&FF +\ +.swwor_0_ibyte +\ + INY +\ + FNtube_2_wait_get + LDA tube_2_data% + STA (tubos_genptr1),Y +\ + CMP #&0D + BNE swwor_0_ibyte +\ + LDX #0 +\ + PLA +\ + CLC +\ + RTS +\ +.swwor_0_abort +\ + LDX tubos_genptr2+0 +\ + LDY #0 +\ + PLA +\ + RTS + + + +.swrun_args +\ + PHY \ Perform OSARGS + PHA +\ + STX tubos_genptr2+0 + STZ tubos_genptr2+1 +\ + LDA #tubrc_osargs% + JSR a_to_fifo_2 +\ + FNtube_2_wait_put + STY tube_2_data% +\ + LDY #3 + JSR blk_to_fifo_2_ypl1 +\ + PLA +\ + JSR a_to_fifo_2 +\ + JSR a_from_fifo_2 +\ + PHA +\ + LDY #3 + JSR blk_from_fifo_2_ypl1 +\ + LDX tubos_genptr2+0 +\ + PLA + PLY +\ + RTS + + + +.swrun_find +\ + PHA \ Perform OSFIND +\ + LDA #tubrc_osfind% + JSR a_to_fifo_2 +\ + PLA +\ + JSR a_to_fifo_2 +\ + CMP #&00 + BNE swfin_open +\ + PHA +\ + TYA + JSR a_to_fifo_2 +\ + JSR a_from_fifo_2 +\ + PLA +\ + RTS +\ +.swfin_open +\ + JSR transmit_string_xy +\ + JMP a_from_fifo_2 + + + +.swrun_bget +\ + LDA #tubrc_osbget% \ Perform OSBGET + JSR a_to_fifo_2 +\ + TYA + JSR a_to_fifo_2 +\ + JMP ca_from_fifo_2 + + + +.swrun_bput +\ + PHA \ Perform OSBPUT +\ + LDA #tubrc_osbput% + JSR a_to_fifo_2 +\ + TYA + JSR a_to_fifo_2 +\ + PLA +\ + JSR a_to_fifo_2 +\ + PHA +\ + JSR a_from_fifo_2 +\ + PLA +\ + RTS + + + +.swrun_file +\ + STX tubos_genptr2+0 \ Perform OSFILE + STY tubos_genptr2+1 +\ + PHA +\ + LDA #tubrc_osfile% + JSR a_to_fifo_2 +\ + LDX #16 + LDY #17 + JSR blk_to_fifo_2 +\ + LDA (tubos_genptr2) + TAX +\ + LDA (tubos_genptr2),Y + TAY +\ + JSR transmit_string_xy +\ + PLA +\ + JSR a_to_fifo_2 +\ + JSR a_from_fifo_2 +\ + PHA +\ + LDX #16 + LDY #17 + JSR blk_from_fifo_2 +\ + LDX tubos_genptr2+0 + LDY tubos_genptr2+1 +\ + PLA +\ + RTS + + + +.swrun_gbpb +\ + STX tubos_genptr2+0 \ Perform OSGBPB + STY tubos_genptr2+1 +\ + PHA +\ + LDA #tubrc_osgbpb% + JSR a_to_fifo_2 +\ + LDY #12 + JSR blk_to_fifo_2_ypl1 +\ + PLA +\ + JSR a_to_fifo_2 +\ + LDY #12 + JSR blk_from_fifo_2_ypl1 +\ + LDX tubos_genptr2+0 + LDY tubos_genptr2+1 +\ + JMP ca_from_fifo_2 + + + +.hwrun_int +\ + STA tubos_irqa \ Save 'IRQ A' +\ + PLA \ BRK or IRQ ? + PHA + AND #1<<4 + BNE hwint_is_brk \ BRK +\ + JMP (osvec_irq1%) \ IRQ + + + +.swrun_irq1 +\ + BIT tube_4_flag% \ IRQ from 4 ? + BMI hwint_4_active \ Yes, handle +\ + BIT tube_1_flag% \ IRQ from 1 ? + BMI hwint_1_active \ Yes, handle +\ + JMP (osvec_irq2%) \ Relay unknown IRQ + + + +.hwint_is_brk +\ + PHX \ Register 'last BRK' +\ + TSX + CLD + SEC + LDA &0101+1+1,X + SBC #&01 + STA tubos_lastbrk+0 + LDA &0101+1+2,X + SBC #&00 + STA tubos_lastbrk+1 +\ + PLX +\ + LDA tubos_irqa \ Relay to BRK handler +\ + CLI +\ + JMP (osvec_brk%) + + + +.hwint_1_active +\ + LDA tube_1_data% \ Incoming event ? + BMI hwin1_escape \ No, ESCAPE flag +\ + PHX \ Relay to event handler + PHY +\ + JSR next_from_1 + TAY +\ + JSR next_from_1 + TAX +\ + JSR next_from_1 +\ + JSR hwin1_event +\ + PLY + PLX +\ + LDA tubos_irqa +\ + RTI +\ +.hwin1_event +\ + JMP (osvec_evnt%) +\ +.hwin1_escape +\ + ASL A \ Note new ESCAPE flag + STA tubos_escape +\ + LDA tubos_irqa +\ + RTI + + + +.hwint_4_active +\ + LDA tube_4_data% \ Incoming error ? + BPL hwin4_trans \ No, data transfer +\ + CLI \ Copy error to BRK buffer +\ + JSR a_from_fifo_2 +\ + STZ tubos_strbuf_first+0 +\ + LDY #&FF +\ +.hwin4_waich +\ + INY +\ + JSR a_from_fifo_2 + STA tubos_strbuf_first+1,Y +\ + BNE hwin4_waich +\ + TYA + BEQ hwin4_waich \ (zero allowed for erno.) +\ + JMP tubos_strbuf_first \ Execute as BRK type error +\ +.hwin4_trans +\ + PHX \ Save used registers + PHY +\ + TAX \ Transfer type +\ + LDA nmi_codptr_lo,X \ New processor NMI vector + STA hwvec_nmi+0 + LDA nmi_codptr_hi,X + STA hwvec_nmi+1 +\ + LDA nmi_traptr_lo,X \ Target of start address + STA tubos_nmiptrad+0 + LDA nmi_traptr_hi,X + STA tubos_nmiptrad+1 +\ + FNtube_4_wait_get \ Sync (for release) + LDA tube_4_data% +\ + CPX #&05 \ Ready for 'release' + BEQ hwin4_finish +\ + LDY #mem_ptr_size% - 1 \ Initialise transfer address +\ + FNtube_4_wait_get + LDA tube_4_data% +\ + FNtube_4_wait_get + LDA tube_4_data% +\ + FNtube_4_wait_get + LDA tube_4_data% + STA (tubos_nmiptrad),Y +\ + DEY +\ + FNtube_4_wait_get + LDA tube_4_data% + STA (tubos_nmiptrad),Y +\ + BIT tube_3_data% \ Empty H-to-P FIFO + BIT tube_3_data% +\ + FNtube_4_wait_get \ Sync (starts transfer) + LDA tube_4_data% +\ + CPX #&06 \ Done if not polled I/O + BCC hwin4_finish \ (rest, if any, via NMI) +\ + BNE hwin4_7 +\ + LDX #0 \ Perform type 6 transfer +\ +.hwin4_6_byte +\ + BIT tube_3_flag% + BPL hwin4_6_byte +\ +.nmi_6_ptr + LDA &FFFF,X + STA tube_3_data% +\ + INX + BNE hwin4_6_byte +\ + FNtube_3_wait_get + STA tube_3_data% +\ + BRA hwin4_finish +\ +.hwin4_7 +\ + LDX #0 \ Perform type 7 transfer +\ +.hwin4_7_byte +\ + BIT tube_3_flag% + BPL hwin4_7_byte +\ + LDA tube_3_data% +.nmi_7_ptr + STA &FFFF,X +\ + INX + BNE hwin4_7_byte +\ +.hwin4_finish +\ + PLY \ Restore used registers + PLX +\ + LDA tubos_irqa +\ + RTI + + + +.next_from_1 +\ + BIT tube_1_flag% \ Receive next host byte on '1' + BMI nxin1_byte +\ + BIT tube_4_flag% \ (while giving way to IRQs on '4') + BPL next_from_1 +\ + LDA tubos_irqa +\ + PHP + CLI + PLP +\ + STA tubos_irqa +\ + BRA next_from_1 +\ +.nxin1_byte +\ + LDA tube_1_data% +\ +.swrun_inactive +\ + RTS + + + +.hwrun_nmi +\ + STA tube_3_data% \ Attempt to remove NMI cause +\ + RTI + + + +.nmi_0_cod \ total 35 [44] (worst), 30 [31] (best), +4 @ 14 MHz +\ + PHA \ 3 +\ +.nmi_0_ptr + LDA &FFFF \ 4 [5] + STA tube_3_data% \ 4 ; +4 @ 14 MHz +\ + FNinc_mem_ptr(nmi_0_ptr+1) \ 6+2+6[+2+6] (worst), 6+3 (best) +\ + PLA \ 4 +\ + RTI \ 6 + + + +.nmi_1_cod \ total 35 [44] (worst), 30 [31] (best), +4 @ 14 MHz +\ + PHA \ 3 +\ + LDA tube_3_data% \ 4 ; +4 @ 14 MHz +.nmi_1_ptr + STA &FFFF \ 4 [5] +\ + FNinc_mem_ptr(nmi_1_ptr+1) \ 6+2+6[+2+6] (worst), 6+3 (best) +\ + PLA \ 4 +\ + RTI \ 6 + + + +.nmi_2_cod \ total 55 [71] (worst), 51 [60] (best), +8 @ 14 MHz +\ + PHA \ 3 +\ + LDA (tubos_transad) \ 5 [6] + STA tube_3_data% \ 4 ; +4 @ 14 MHz +\ + FNinc_mem_ptr(tubos_transad) \ 5+2+5[+2+5] (worst), 5+3 (best) +\ + LDA (tubos_transad) \ 5 [6] + STA tube_3_data% \ 4 ; +4 @ 14 MHz +\ + FNinc_mem_ptr(tubos_transad) \ 5+2+5[+2+5] (worst), 5+3 (best) +\ + PLA \ 4 +\ + RTI \ 6 + + + +.nmi_3_cod \ total 55 [71] (worst), 51 [60] (best), +8 @ 14 MHz +\ + PHA \ 3 +\ + LDA tube_3_data% \ 4 ; +4 @ 14 MHz + STA (tubos_transad) \ 5 [6] +\ + FNinc_mem_ptr(tubos_transad) \ 5+2+5[+2+5] (worst), 5+3 (best) +\ + LDA tube_3_data% \ 4 ; +4 @ 14 MHz + STA (tubos_transad) \ 5 [6] +\ + FNinc_mem_ptr(tubos_transad) \ 5+2+5[+2+5] (worst), 5+3 (best) +\ + PLA \ 4 +\ + RTI \ 6 + + + +] + +IF P% > &FF00 THEN STOP + +D% = &FF00 - P%:P% += D%:O% += D% + +[OPT `P + + + +.std_swrun +\ + EQUW swrun_illegal ; USR + EQUW swrun_brk ; BRK + EQUW swrun_irq1 ; IRQ1 + EQUW swrun_illegal ; IRQ2 + EQUW swrun_cli ; CLI + EQUW swrun_byte ; BYTE + EQUW swrun_word ; WORD + EQUW swrun_wrch ; WRCH + EQUW swrun_rdch ; RDCH + EQUW swrun_file ; FILE + EQUW swrun_args ; ARGS + EQUW swrun_bget ; BGET + EQUW swrun_bput ; BPUT + EQUW swrun_gbpb ; GBPB + EQUW swrun_find ; FIND + EQUW swrun_illegal ; FSC + EQUW swrun_inactive ; EVNT + EQUW swrun_illegal ; UPT + EQUW swrun_illegal ; NET + EQUW swrun_illegal ; VDU + EQUW swrun_illegal ; KEY + EQUW swrun_illegal ; INS + EQUW swrun_illegal ; REM + EQUW swrun_illegal ; CNP + EQUW swrun_inactive ; IND1 + EQUW swrun_inactive ; IND2 + EQUW swrun_inactive ; IND3 +\ +.std_swrun_end + + + +.star_commands +\ + EQUB ASC"H" << 1 OR 0 + EQUB ASC"E" << 1 OR 1 + EQUB ASC"L" << 1 OR 1 + EQUB ASC"P" << 1 OR 1 + EQUB 0 +\ + EQUB ASC"G" << 1 OR 0 + EQUB ASC"O" << 1 OR 0 + EQUB ASC"S" << 1 OR 0 + EQUB 0 +\ + EQUB ASC"G" << 1 OR 0 + EQUB ASC"O" << 1 OR 0 + EQUB 0 +\ + EQUB 1 + + + +.supervisor_osword_0 +\ + EQUW tubos_strbuf_first +\ + EQUB tubos_strbuf_final + 1 - tubos_strbuf_first +\ + EQUB &20 + EQUB &FF + + + +.osword_o_rc2size +\ + EQUB &00 + EQUB &05 + EQUB &00 + EQUB &05 + EQUB &04 + EQUB &05 + EQUB &08 + EQUB &0E + EQUB &04 + EQUB &01 + EQUB &01 + EQUB &05 + EQUB &00 + EQUB &08 + EQUB &20 + EQUB &10 + EQUB &0D + EQUB &00 + EQUB &04 + EQUB &80 +\ +.osword_o_rc2size_end +\ +.osword_i_rc2size +\ + EQUB &05 + EQUB &00 + EQUB &05 + EQUB &00 + EQUB &05 + EQUB &00 + EQUB &00 + EQUB &00 + EQUB &05 + EQUB &09 + EQUB &05 + EQUB &00 + EQUB &08 + EQUB &18 + EQUB &00 + EQUB &01 + EQUB &0D + EQUB &80 + EQUB &04 + EQUB &80 +\ +.osword_i_rc2size_end + + + +.nmi_traptr_lo +\ + EQUB (nmi_0_ptr+1) MOD 256 + EQUB (nmi_1_ptr+1) MOD 256 + EQUB tubos_transad MOD 256 + EQUB tubos_transad MOD 256 + EQUB tubos_transad MOD 256 + EQUB tubos_transad MOD 256 + EQUB (nmi_6_ptr+1) MOD 256 + EQUB (nmi_7_ptr+1) MOD 256 +\ +.nmi_traptr_hi +\ + EQUB (nmi_0_ptr+1) DIV 256 + EQUB (nmi_1_ptr+1) DIV 256 + EQUB tubos_transad DIV 256 + EQUB tubos_transad DIV 256 + EQUB tubos_transad DIV 256 + EQUB tubos_transad DIV 256 + EQUB (nmi_6_ptr+1) DIV 256 + EQUB (nmi_7_ptr+1) DIV 256 +\ +.nmi_codptr_lo +\ + EQUB nmi_0_cod MOD 256 + EQUB nmi_1_cod MOD 256 + EQUB nmi_2_cod MOD 256 + EQUB nmi_3_cod MOD 256 + EQUB hwrun_nmi MOD 256 + EQUB hwrun_nmi MOD 256 + EQUB hwrun_nmi MOD 256 + EQUB hwrun_nmi MOD 256 +\ +.nmi_codptr_hi +\ + EQUB nmi_0_cod DIV 256 + EQUB nmi_1_cod DIV 256 + EQUB nmi_2_cod DIV 256 + EQUB nmi_3_cod DIV 256 + EQUB hwrun_nmi DIV 256 + EQUB hwrun_nmi DIV 256 + EQUB hwrun_nmi DIV 256 + EQUB hwrun_nmi DIV 256 + + + +.escape_if_c +\ + BCS escape_error \ If ESCAPE detected, handle +\ + RTS +\ +.escape_error +\ + LDA #&7E \ Acknowledge ESCAPE + JSR os_byte% +\ + BRK \ Generate ESCAPE error + EQUB 17 + EQUS "Escape" + EQUB 0 + + + +.swrun_illegal +\ + BRK + EQUB 255 + EQUS "Bad" + EQUB 0 + + + +] + +IF P% > &FFB3 THEN STOP + +D% = &FFB3 - P%:P% += D%:O% += D% + +[OPT `P + + + +.os_wrsc% +\ + JMP swrun_illegal +\ +.os_defv% +\ + EQUB std_swrun_end - std_swrun + EQUW std_swrun +\ +.os_rdsc% +\ + JMP swrun_illegal +\ +.os_rvdu% +\ + JMP swrun_illegal +\ +.os_even% +\ + JMP swrun_illegal +\ +.gs_init% +\ + JMP swrun_illegal +\ +.gs_read% +\ + JMP swrun_illegal +\ +.nv_rdch% +\ + JMP swrun_rdch +\ +.nv_wrch% +\ + JMP swrun_wrch +\ +.os_find% +\ + JMP (osvec_find%) +\ +.os_gbpb% +\ + JMP (osvec_gbpb%) +\ +.os_bput% +\ + JMP (osvec_bput%) +\ +.os_bget% +\ + JMP (osvec_bget%) +\ +.os_args% +\ + JMP (osvec_args%) +\ +.os_file% +\ + JMP (osvec_file%) +\ +.os_rdch% +\ + JMP (osvec_rdch%) +\ +.os_asci% +\ + CMP #&0D + BNE os_wrch% +\ +.os_newl% +\ + LDA #&0A + JSR os_wrch% + LDA #&0D +\ +.os_wrch% +\ + JMP (osvec_wrch%) +\ +.os_word% +\ + JMP (osvec_word%) +\ +.os_byte% +\ + JMP (osvec_byte%) +\ +.os_cli% +\ + JMP (osvec_cli%) + + + +.hwvec_nmi +\ + EQUW hwrun_nmi +\ +.hwvec_rst +\ + EQUW rom_boot% +\ +.hwvec_int +\ + EQUW hwrun_int + + + +] + +IF P% <> &10000 THEN STOP + +ENDPROC + + + +DEFFNtube_1_wait_put + += FNtube_wait_put(tube_1_flag%) + + + +DEFFNtube_2_wait_get + += FNtube_wait_get(tube_2_flag%) + + + +DEFFNtube_2_wait_put + += FNtube_wait_put(tube_2_flag%) + + + +DEFFNtube_3_wait_get + += FNtube_wait_get(tube_3_flag%) + + + +DEFFNtube_4_wait_get + += FNtube_wait_get(tube_4_flag%) + + + +DEFFNtube_wait_get(tube_flag%) + +[OPT `P +\ + BIT tube_flag% + BPL P% - 3 +\ +] + += 0 + + + +DEFFNtube_wait_put(tube_flag%) + +[OPT `P +\ + BIT tube_flag% + BVC P% - 3 +\ +] + += 0 + + + +DEFFNinc_mem_ptr(mem_ptr_addr%) + +LOCAL inc_done% + +inc_done% = P% + +[OPT `P:INC mem_ptr_addr%+0:] + +inc_done% = P% - inc_done% + +inc_done% = P% + (mem_ptr_size% - 1) * (2 + inc_done%) + +FOR B% = 1 TO mem_ptr_size% - 1 + +[OPT `P:BNE inc_done%:INC mem_ptr_addr%+B%:] + +NEXT + += 0 + + +