From 42b6eceae64ff39c288b0a2b5ed79fc9273ff914 Mon Sep 17 00:00:00 2001 From: Andrei Vlad LUTAS Date: Thu, 7 Nov 2024 11:58:23 +0200 Subject: [PATCH 1/3] * Add support for SIMD exceptions reporting in INSTRUX. * Add support for new ISAs: MOVRS, MSR_IMM, AMX-FP8, AMX-TRANSPOSE, AMX-TF32, AMX-AVX512, AMX-MOVRS, EVEX-encoded SM4. Co-authored-by: ianichitei (Rust bindings) --- CHANGELOG.md | 7 + bddisasm/bdx86_decoder.c | 13 +- bddisasm/include/bdx86_instructions.h | 16436 +++++++++++----- bddisasm/include/bdx86_mnemonics.h | 349 +- bddisasm/include/bdx86_table_evex.h | 3696 ++-- bddisasm/include/bdx86_table_root.h | 1568 +- bddisasm/include/bdx86_table_vex.h | 6278 +++--- bddisasm/include/bdx86_table_xop.h | 148 +- bddisasm/include/bdx86_tabledefs.h | 1 + bddisasm_test/conf-x86.json | 28 + bddisasm_test/x86/amx/amx1_64.asm | 28 +- bddisasm_test/x86/amx/amx1_64.result | 430 + bddisasm_test/x86/amx/amx1_64.test | Bin 113 -> 243 bytes bddisasm_test/x86/amx/amx_evex_64.result | 228 + bddisasm_test/x86/amx/amx_evex_64.test | 1 + bddisasm_test/x86/avx/avx_64.result | 448 + bddisasm_test/x86/avx/f16c_64.result | 8 + bddisasm_test/x86/avx/fma4_64.result | 128 + bddisasm_test/x86/avx/fma_64.result | 192 + bddisasm_test/x86/avx10/avx101_64.result | 2 + bddisasm_test/x86/avx10/avx102_64.result | 8583 +++++--- bddisasm_test/x86/avx10/avx102_64.test | 2 +- bddisasm_test/x86/avx512/avx512dq_64.result | 768 + bddisasm_test/x86/avx512/avx512er_64.result | 168 + bddisasm_test/x86/avx512/avx512f_64.result | 4332 ++++ bddisasm_test/x86/avx512/avx512fp16_32.result | 10626 ++++++++++ bddisasm_test/x86/avx512/avx512fp16_64.result | 10626 ++++++++++ bddisasm_test/x86/movrs/movrs_64.asm | 9 + bddisasm_test/x86/movrs/movrs_64.result | 118 + bddisasm_test/x86/movrs/movrs_64.test | Bin 0 -> 31 bytes bddisasm_test/x86/movrs/vmovrs_64.result | 756 + bddisasm_test/x86/movrs/vmovrs_64.test | 1 + bddisasm_test/x86/msr/msr_64.asm | 17 +- bddisasm_test/x86/msr/msr_64.result | 92 +- bddisasm_test/x86/msr/msr_64.test | 2 +- bddisasm_test/x86/simd/mmx_64.result | 8 + bddisasm_test/x86/simd/sse2_64.result | 66 + bddisasm_test/x86/simd/sse3_64.result | 12 + bddisasm_test/x86/simd/sse4_64.result | 12 + bddisasm_test/x86/sm/sm4_evex_64.result | 234 + bddisasm_test/x86/sm/sm4_evex_64.test | 1 + bddisasm_test/x86/sm/sm_64.asm | 4 +- .../x86/special/ignorew_evex_32.result | 4 + .../x86/special/ignorew_evex_64.result | 4 + .../x86/special/regressions_64.result | 1 + bddisasm_test/x86/usermsr/rex2_valid_64.asm | 13 +- .../x86/usermsr/rex2_valid_64.result | 56 +- bddisasm_test/x86/usermsr/rex2_valid_64.test | 2 +- bindings/pybddisasm/setup.py | 2 +- bindings/rsbddisasm/Cargo.toml | 4 +- bindings/rsbddisasm/bddisasm/Cargo.toml | 3 +- bindings/rsbddisasm/bddisasm/README.md | 2 +- .../bddisasm/src/decoded_instruction.rs | 12 +- bindings/rsbddisasm/bddisasm/src/decoder.rs | 4 +- bindings/rsbddisasm/bddisasm/src/fpu_flags.rs | 8 +- bindings/rsbddisasm/bddisasm/src/isa_set.rs | 14 + bindings/rsbddisasm/bddisasm/src/mnemonic.rs | 70 + bindings/rsbddisasm/bddisasm/src/operand.rs | 4 +- disasmtool/disasmtool.c | 30 +- inc/bddisasm_version.h | 2 +- inc/bdx86_constants.h | 42 + inc/bdx86_core.h | 60 +- inc/bdx86_cpuidflags.h | 7 + isagenerator/disasmlib.py | 21 + isagenerator/generate_tables.py | 8 + isagenerator/instructions/cpuid.dat | 12 +- isagenerator/instructions/table_evex_1.dat | 160 +- isagenerator/instructions/table_evex_2.dat | 191 +- isagenerator/instructions/table_evex_3.dat | 83 +- isagenerator/instructions/table_evex_5.dat | 164 +- isagenerator/instructions/table_evex_6.dat | 89 +- isagenerator/instructions/table_evex_7.dat | 6 +- isagenerator/instructions/table_legacy_1.dat | 132 +- isagenerator/instructions/table_legacy_2.dat | 3 + isagenerator/instructions/table_legacy_3.dat | 12 +- isagenerator/instructions/table_vex_1.dat | 118 +- isagenerator/instructions/table_vex_2.dat | 140 +- isagenerator/instructions/table_vex_3.dat | 96 +- isagenerator/instructions/table_vex_5.dat | 14 + isagenerator/instructions/table_vex_7.dat | 2 + isagenerator/isagenerator.vcxproj | 2 +- isagenerator/isagenerator.vcxproj.filters | 6 +- 82 files changed, 53678 insertions(+), 14351 deletions(-) create mode 100644 bddisasm_test/x86/amx/amx_evex_64.result create mode 100644 bddisasm_test/x86/amx/amx_evex_64.test create mode 100644 bddisasm_test/x86/movrs/movrs_64.asm create mode 100644 bddisasm_test/x86/movrs/movrs_64.result create mode 100644 bddisasm_test/x86/movrs/movrs_64.test create mode 100644 bddisasm_test/x86/movrs/vmovrs_64.result create mode 100644 bddisasm_test/x86/movrs/vmovrs_64.test create mode 100644 bddisasm_test/x86/sm/sm4_evex_64.result create mode 100644 bddisasm_test/x86/sm/sm4_evex_64.test create mode 100644 isagenerator/instructions/table_vex_5.dat diff --git a/CHANGELOG.md b/CHANGELOG.md index be29483..48c3091 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -5,6 +5,13 @@ All notable (user-facing) changes to this project will be documented in this fil The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/). +## [2.3.0] - 2024-11-07 + +### Added +- Support for SIMD Exceptions reporting (for instructions that generate SIMD exceptions; this is equivalent to also setting or testing the associated bits in the `MXCSR`). +- Support for the following new x86 ISAs: MOVRS, MSR_IMM, AMX-FP8, AMX-TRANSPOSE, AMX-TF32, AMX-AVX512, AMX-MOVRS and EVEX-encoded SM4 instructions. + + ## [2.2.0] - 2024-09-16 ### Added diff --git a/bddisasm/bdx86_decoder.c b/bddisasm/bdx86_decoder.c index 0cbdaab..c03acc9 100644 --- a/bddisasm/bdx86_decoder.c +++ b/bddisasm/bdx86_decoder.c @@ -4297,7 +4297,8 @@ NdVexExceptionChecks( } // Handle AMX exception class. - if (Instrux->ExceptionType == ND_EXT_AMX_E4) + if (Instrux->ExceptionType == ND_EXT_AMX_E4 || + Instrux->ExceptionType == ND_EXT_AMX_E10) { // #UD if srcdest == src1, srcdest == src2 or src1 == src2. All three operands are tile regs. if (Instrux->Operands[0].Info.Register.Reg == Instrux->Operands[1].Info.Register.Reg || @@ -4374,7 +4375,8 @@ NdCopyInstructionInfo( Instrux->ValidModes.Raw = Idbe->ValidModes; Instrux->ValidPrefixes.Raw = Idbe->ValidPrefixes; Instrux->ValidDecorators.Raw = Idbe->ValidDecorators; - *((ND_UINT8*)&Instrux->FpuFlagsAccess) = Idbe->FpuFlags; + Instrux->FpuFlagsAccess.Raw = Idbe->FpuFlags; + Instrux->SimdExceptions.Raw = Idbe->SimdExc; // Valid for EVEX, VEX and SSE instructions only. A value of 0 means it's not used. Instrux->ExceptionType = Idbe->ExcType; Instrux->TupleType = Idbe->TupleType; @@ -4465,8 +4467,11 @@ NdDecodeWithContext( return ND_STATUS_INVALID_PARAMETER; } - // Initialize with zero. - nd_memzero(Instrux, sizeof(INSTRUX)); + if (0 == (Context->Options & ND_OPTION_SKIP_ZERO_INSTRUX)) + { + // Initialize with zero. + nd_memzero(Instrux, sizeof(INSTRUX)); + } Instrux->DefCode = (ND_UINT8)Context->DefCode; Instrux->DefData = (ND_UINT8)Context->DefData; diff --git a/bddisasm/include/bdx86_instructions.h b/bddisasm/include/bdx86_instructions.h index 8bfcc43..205fb9c 100644 --- a/bddisasm/include/bdx86_instructions.h +++ b/bddisasm/include/bdx86_instructions.h @@ -10,7 +10,7 @@ #ifndef BDX86_INSTRUCTIONS_H #define BDX86_INSTRUCTIONS_H -const ND_IDBE gInstructions[4157] = +const ND_IDBE gInstructions[4206] = { // Pos:0 Instruction:"AAA" Encoding:"0x37"/"" { @@ -26,6 +26,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_AF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF, .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, @@ -54,6 +55,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, @@ -83,6 +85,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_RAOINT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -110,6 +113,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -137,6 +141,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, @@ -166,6 +171,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_RAOINT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -193,6 +199,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -220,6 +227,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_AF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF, .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, @@ -248,6 +256,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -276,6 +285,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -304,6 +314,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -332,6 +343,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -360,6 +372,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -388,6 +401,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -416,6 +430,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -444,6 +459,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -472,6 +488,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -500,6 +517,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -528,6 +546,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -556,6 +575,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -585,6 +605,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -614,6 +635,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -643,6 +665,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -672,6 +695,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -701,6 +725,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -730,6 +755,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -759,6 +785,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -788,6 +815,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -817,6 +845,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -846,6 +875,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -875,6 +905,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -903,6 +934,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -931,6 +963,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -959,6 +992,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -987,6 +1021,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -1015,6 +1050,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -1043,6 +1079,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -1071,6 +1108,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -1099,6 +1137,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -1127,6 +1166,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -1155,6 +1195,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF, .SetFlags = 0, @@ -1183,6 +1224,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF, .SetFlags = 0, @@ -1212,6 +1254,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF, .SetFlags = 0, @@ -1240,6 +1283,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -1268,6 +1312,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -1296,6 +1341,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -1324,6 +1370,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -1352,6 +1399,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -1380,6 +1428,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -1408,6 +1457,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -1436,6 +1486,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -1464,6 +1515,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -1492,6 +1544,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -1520,6 +1573,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -1548,6 +1602,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -1575,6 +1630,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -1602,6 +1658,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -1629,6 +1686,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -1656,6 +1714,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -1683,6 +1742,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -1710,6 +1770,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -1737,6 +1798,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -1764,6 +1826,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -1791,6 +1854,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -1818,6 +1882,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -1845,6 +1910,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -1874,6 +1940,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -1903,6 +1970,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -1932,6 +2000,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -1961,6 +2030,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -1990,6 +2060,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -2019,6 +2090,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -2048,6 +2120,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -2077,6 +2150,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -2106,6 +2180,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -2135,6 +2210,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -2164,6 +2240,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -2192,6 +2269,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -2220,6 +2298,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -2248,6 +2327,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -2276,6 +2356,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -2304,6 +2385,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -2332,6 +2414,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -2360,6 +2443,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -2388,6 +2472,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -2416,6 +2501,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -2444,6 +2530,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -2472,6 +2559,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -2500,6 +2588,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -2528,6 +2617,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -2556,6 +2646,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -2584,6 +2675,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -2612,6 +2704,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -2640,6 +2733,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -2668,6 +2762,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -2696,6 +2791,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -2724,6 +2820,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -2752,6 +2849,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -2779,6 +2877,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -2806,6 +2905,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -2833,6 +2933,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -2860,6 +2961,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -2887,6 +2989,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -2914,6 +3017,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF, .SetFlags = 0, @@ -2942,6 +3046,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF, .SetFlags = 0, @@ -2971,6 +3076,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_OF, .SetFlags = 0, @@ -2999,6 +3105,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -3026,6 +3133,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_ZF, .SetFlags = 0, @@ -3054,6 +3162,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_ZF, .SetFlags = 0, @@ -3082,6 +3191,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -3109,6 +3219,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_ZF, .SetFlags = 0, @@ -3137,6 +3248,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_ZF, .SetFlags = 0, @@ -3165,6 +3277,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -3192,6 +3305,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_ZF, .SetFlags = 0, @@ -3220,6 +3334,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_ZF, .SetFlags = 0, @@ -3248,6 +3363,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -3275,6 +3391,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_ZF, .SetFlags = 0, @@ -3303,6 +3420,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_ZF, .SetFlags = 0, @@ -3331,6 +3449,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -3358,6 +3477,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -3386,6 +3506,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -3414,6 +3535,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -3442,6 +3564,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -3470,6 +3593,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -3498,6 +3622,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -3526,6 +3651,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -3554,6 +3680,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -3582,6 +3709,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -3610,6 +3738,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -3638,6 +3767,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -3666,6 +3796,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -3694,6 +3825,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -3721,6 +3853,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -3748,6 +3881,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -3775,6 +3909,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -3802,6 +3937,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -3829,6 +3965,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -3856,6 +3993,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -3883,6 +4021,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -3910,6 +4049,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -3937,6 +4077,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -3964,6 +4105,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -3991,6 +4133,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -4020,6 +4163,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -4049,6 +4193,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -4078,6 +4223,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -4107,6 +4253,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -4136,6 +4283,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -4165,6 +4313,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -4194,6 +4343,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -4223,6 +4373,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -4252,6 +4403,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -4281,6 +4433,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -4310,6 +4463,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -4338,6 +4492,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -4366,6 +4521,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -4394,6 +4550,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -4422,6 +4579,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -4450,6 +4608,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -4478,6 +4637,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -4506,6 +4666,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -4534,6 +4695,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -4562,6 +4724,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -4590,6 +4753,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -4618,6 +4782,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -4646,6 +4811,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -4674,6 +4840,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -4702,6 +4869,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -4730,6 +4898,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -4758,6 +4927,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -4786,6 +4956,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -4814,6 +4985,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -4842,6 +5014,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -4870,6 +5043,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -4898,6 +5072,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_BMI, .FpuFlags = 0, .EvexMode = ND_EVEXM_VEX, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF, @@ -4927,6 +5102,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_BMI, .FpuFlags = 0, .EvexMode = ND_EVEXM_VEX, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -4955,6 +5131,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_13, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF, @@ -4984,6 +5161,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -5011,6 +5189,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -5038,6 +5217,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -5065,6 +5245,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -5092,6 +5273,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_RAOINT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -5119,6 +5301,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -5146,6 +5329,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_ZF, .SetFlags = 0, @@ -5174,6 +5358,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_RAOINT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -5201,6 +5386,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -5228,6 +5414,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_BMI, .FpuFlags = 0, .EvexMode = ND_EVEXM_VEX, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_ZF, .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF, @@ -5257,6 +5444,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_BMI, .FpuFlags = 0, .EvexMode = ND_EVEXM_VEX, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -5285,6 +5473,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_13, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_ZF, .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF, @@ -5314,6 +5503,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -5342,6 +5532,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -5369,6 +5560,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -5396,6 +5588,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -5423,6 +5616,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -5450,6 +5644,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -5477,6 +5672,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -5505,6 +5701,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -5533,6 +5730,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -5561,6 +5759,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -5589,6 +5788,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -5616,6 +5816,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_BMI, .FpuFlags = 0, .EvexMode = ND_EVEXM_VEX, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF, @@ -5644,6 +5845,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_BMI, .FpuFlags = 0, .EvexMode = ND_EVEXM_VEX, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -5671,6 +5873,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_13, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF, @@ -5699,6 +5902,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -5726,6 +5930,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_BMI, .FpuFlags = 0, .EvexMode = ND_EVEXM_VEX, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF, @@ -5754,6 +5959,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_BMI, .FpuFlags = 0, .EvexMode = ND_EVEXM_VEX, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -5781,6 +5987,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_13, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF, @@ -5809,6 +6016,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_BMI, .FpuFlags = 0, .EvexMode = ND_EVEXM_VEX, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF, @@ -5837,6 +6045,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_BMI, .FpuFlags = 0, .EvexMode = ND_EVEXM_VEX, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -5864,6 +6073,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_13, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF, @@ -5892,6 +6102,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -5919,6 +6130,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -5946,6 +6158,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -5973,6 +6186,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -6000,6 +6214,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -6027,6 +6242,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -6054,6 +6270,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -6081,6 +6298,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -6108,6 +6326,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -6135,6 +6354,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_ZF, .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, @@ -6163,6 +6383,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_ZF, .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, @@ -6191,6 +6412,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -6217,6 +6439,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -6243,6 +6466,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -6269,6 +6493,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -6295,6 +6520,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -6321,6 +6547,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -6347,6 +6574,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -6373,6 +6601,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -6399,6 +6628,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF, .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, @@ -6427,6 +6657,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF, .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, @@ -6455,6 +6686,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF, .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, @@ -6483,6 +6715,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF, .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, @@ -6511,6 +6744,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF, .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, @@ -6539,6 +6773,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF, .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, @@ -6567,6 +6802,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF, .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, @@ -6595,6 +6831,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF, .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, @@ -6623,6 +6860,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_BMI, .FpuFlags = 0, .EvexMode = ND_EVEXM_VEX, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF, @@ -6652,6 +6890,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_BMI, .FpuFlags = 0, .EvexMode = ND_EVEXM_VEX, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -6680,6 +6919,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_13, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF, @@ -6709,6 +6949,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -6738,6 +6979,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -6767,6 +7009,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -6797,6 +7040,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -6827,6 +7071,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -6854,6 +7099,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -6883,6 +7129,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -6912,6 +7159,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -6941,6 +7189,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -6970,6 +7219,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -6999,6 +7249,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -7028,6 +7279,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -7057,6 +7309,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -7086,6 +7339,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -7115,6 +7369,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -7144,6 +7399,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -7173,6 +7429,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0, .SetFlags = 0, @@ -7202,6 +7459,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0, .SetFlags = 0, @@ -7231,6 +7489,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0, .SetFlags = 0, @@ -7260,6 +7519,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0, .SetFlags = 0, @@ -7289,6 +7549,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0, .SetFlags = 0, @@ -7318,6 +7579,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0, .SetFlags = 0, @@ -7347,6 +7609,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0, .SetFlags = 0, @@ -7376,6 +7639,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0, .SetFlags = 0, @@ -7405,6 +7669,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0, .SetFlags = 0, @@ -7434,6 +7699,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0, .SetFlags = 0, @@ -7463,6 +7729,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0, .SetFlags = 0, @@ -7492,6 +7759,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -7521,6 +7789,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -7550,6 +7819,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -7579,6 +7849,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -7608,6 +7879,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -7637,6 +7909,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -7666,6 +7939,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -7695,6 +7969,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -7724,6 +7999,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -7753,6 +8029,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -7782,6 +8059,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -7811,6 +8089,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -7840,6 +8119,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -7869,6 +8149,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -7898,6 +8179,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -7927,6 +8209,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -7956,6 +8239,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -7985,6 +8269,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -8014,6 +8299,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -8043,6 +8329,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -8072,6 +8359,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -8101,6 +8389,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -8130,6 +8419,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -8159,6 +8449,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -8188,6 +8479,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -8217,6 +8509,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -8246,6 +8539,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -8275,6 +8569,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -8304,6 +8599,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -8333,6 +8629,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -8362,6 +8659,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -8391,6 +8689,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -8420,6 +8719,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -8449,6 +8749,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -8478,6 +8779,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -8507,6 +8809,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -8536,6 +8839,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -8565,6 +8869,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -8594,6 +8899,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -8623,6 +8929,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -8652,6 +8959,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -8681,6 +8989,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -8710,6 +9019,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -8739,6 +9049,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -8768,6 +9079,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0, .SetFlags = 0, @@ -8797,6 +9109,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0, .SetFlags = 0, @@ -8826,6 +9139,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0, .SetFlags = 0, @@ -8855,6 +9169,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0, .SetFlags = 0, @@ -8884,6 +9199,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0, .SetFlags = 0, @@ -8913,6 +9229,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0, .SetFlags = 0, @@ -8942,6 +9259,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0, .SetFlags = 0, @@ -8971,6 +9289,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0, .SetFlags = 0, @@ -9000,6 +9319,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0, .SetFlags = 0, @@ -9029,6 +9349,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0, .SetFlags = 0, @@ -9058,6 +9379,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0, .SetFlags = 0, @@ -9087,6 +9409,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -9116,6 +9439,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -9145,6 +9469,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -9174,6 +9499,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -9203,6 +9529,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -9232,6 +9559,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -9261,6 +9589,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -9290,6 +9619,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -9319,6 +9649,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -9348,6 +9679,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -9377,6 +9709,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -9406,6 +9739,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -9435,6 +9769,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -9464,6 +9799,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -9493,6 +9829,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -9522,6 +9859,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -9551,6 +9889,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -9580,6 +9919,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -9609,6 +9949,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -9638,6 +9979,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -9667,6 +10009,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -9696,6 +10039,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -9725,6 +10069,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -9754,6 +10099,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -9783,6 +10129,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -9812,6 +10159,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -9841,6 +10189,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -9870,6 +10219,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -9899,6 +10249,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -9928,6 +10279,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -9957,6 +10309,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -9986,6 +10339,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -10015,6 +10369,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -10044,6 +10399,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF, .ModifiedFlags = 0, .SetFlags = 0, @@ -10073,6 +10429,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF, .ModifiedFlags = 0, .SetFlags = 0, @@ -10102,6 +10459,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF, .ModifiedFlags = 0, .SetFlags = 0, @@ -10131,6 +10489,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF, .ModifiedFlags = 0, .SetFlags = 0, @@ -10160,6 +10519,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF, .ModifiedFlags = 0, .SetFlags = 0, @@ -10189,6 +10549,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF, .ModifiedFlags = 0, .SetFlags = 0, @@ -10218,6 +10579,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF, .ModifiedFlags = 0, .SetFlags = 0, @@ -10247,6 +10609,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF, .ModifiedFlags = 0, .SetFlags = 0, @@ -10276,6 +10639,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF, .ModifiedFlags = 0, .SetFlags = 0, @@ -10305,6 +10669,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF, .ModifiedFlags = 0, .SetFlags = 0, @@ -10334,6 +10699,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF, .ModifiedFlags = 0, .SetFlags = 0, @@ -10363,6 +10729,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -10392,6 +10759,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -10421,6 +10789,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -10450,6 +10819,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -10479,6 +10849,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -10508,6 +10879,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -10537,6 +10909,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -10566,6 +10939,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -10595,6 +10969,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -10624,6 +10999,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -10653,6 +11029,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -10682,6 +11059,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -10711,6 +11089,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -10740,6 +11119,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -10769,6 +11149,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -10798,6 +11179,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -10827,6 +11209,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -10856,6 +11239,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -10885,6 +11269,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -10914,6 +11299,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -10943,6 +11329,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -10972,6 +11359,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -11001,6 +11389,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF, .ModifiedFlags = 0, .SetFlags = 0, @@ -11030,6 +11419,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF, .ModifiedFlags = 0, .SetFlags = 0, @@ -11059,6 +11449,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF, .ModifiedFlags = 0, .SetFlags = 0, @@ -11088,6 +11479,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF, .ModifiedFlags = 0, .SetFlags = 0, @@ -11117,6 +11509,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF, .ModifiedFlags = 0, .SetFlags = 0, @@ -11146,6 +11539,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF, .ModifiedFlags = 0, .SetFlags = 0, @@ -11175,6 +11569,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF, .ModifiedFlags = 0, .SetFlags = 0, @@ -11204,6 +11599,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF, .ModifiedFlags = 0, .SetFlags = 0, @@ -11233,6 +11629,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF, .ModifiedFlags = 0, .SetFlags = 0, @@ -11262,6 +11659,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF, .ModifiedFlags = 0, .SetFlags = 0, @@ -11291,6 +11689,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF, .ModifiedFlags = 0, .SetFlags = 0, @@ -11320,6 +11719,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -11349,6 +11749,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -11378,6 +11779,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -11407,6 +11809,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -11436,6 +11839,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -11465,6 +11869,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -11494,6 +11899,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -11523,6 +11929,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -11552,6 +11959,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -11581,6 +11989,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -11610,6 +12019,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -11639,6 +12049,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -11668,6 +12079,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -11697,6 +12109,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -11726,6 +12139,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -11755,6 +12169,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -11784,6 +12199,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -11813,6 +12229,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -11842,6 +12259,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -11871,6 +12289,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -11900,6 +12319,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -11929,6 +12349,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -11958,6 +12379,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -11985,6 +12407,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -12012,6 +12435,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -12040,6 +12464,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -12068,6 +12493,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -12096,6 +12522,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -12124,6 +12551,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -12152,6 +12580,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -12180,6 +12609,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -12209,6 +12639,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -12238,6 +12669,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0, .SetFlags = 0, @@ -12266,6 +12698,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0, .SetFlags = 0, @@ -12294,6 +12727,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0, .SetFlags = 0, @@ -12322,6 +12756,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0, .SetFlags = 0, @@ -12350,6 +12785,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0, .SetFlags = 0, @@ -12378,6 +12814,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0, .SetFlags = 0, @@ -12406,6 +12843,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0, .SetFlags = 0, @@ -12435,6 +12873,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0, .SetFlags = 0, @@ -12464,6 +12903,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -12492,6 +12932,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -12520,6 +12961,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -12548,6 +12990,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -12576,6 +13019,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -12604,6 +13048,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -12632,6 +13077,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -12661,6 +13107,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -12690,6 +13137,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -12718,6 +13166,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -12746,6 +13195,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -12774,6 +13224,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -12802,6 +13253,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -12830,6 +13282,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -12858,6 +13311,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -12887,6 +13341,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -12916,6 +13371,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -12944,6 +13400,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -12972,6 +13429,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -13000,6 +13458,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -13028,6 +13487,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -13056,6 +13516,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -13084,6 +13545,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -13113,6 +13575,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -13142,6 +13605,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0, .SetFlags = 0, @@ -13170,6 +13634,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0, .SetFlags = 0, @@ -13198,6 +13663,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0, .SetFlags = 0, @@ -13226,6 +13692,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0, .SetFlags = 0, @@ -13254,6 +13721,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0, .SetFlags = 0, @@ -13282,6 +13750,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0, .SetFlags = 0, @@ -13310,6 +13779,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0, .SetFlags = 0, @@ -13339,6 +13809,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0, .SetFlags = 0, @@ -13368,6 +13839,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -13396,6 +13868,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -13424,6 +13897,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -13452,6 +13926,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -13480,6 +13955,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -13508,6 +13984,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -13536,6 +14013,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -13565,6 +14043,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -13594,6 +14073,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -13622,6 +14102,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -13650,6 +14131,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -13678,6 +14160,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -13706,6 +14189,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -13734,6 +14218,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -13762,6 +14247,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -13791,6 +14277,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -13820,6 +14307,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -13848,6 +14336,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -13876,6 +14365,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -13904,6 +14394,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -13932,6 +14423,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -13960,6 +14452,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -13988,6 +14481,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -14017,6 +14511,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -14046,6 +14541,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_PF, .ModifiedFlags = 0, .SetFlags = 0, @@ -14074,6 +14570,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_PF, .ModifiedFlags = 0, .SetFlags = 0, @@ -14102,6 +14599,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_PF, .ModifiedFlags = 0, .SetFlags = 0, @@ -14130,6 +14628,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_PF, .ModifiedFlags = 0, .SetFlags = 0, @@ -14158,6 +14657,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_PF, .ModifiedFlags = 0, .SetFlags = 0, @@ -14186,6 +14686,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_PF, .ModifiedFlags = 0, .SetFlags = 0, @@ -14214,6 +14715,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_PF, .ModifiedFlags = 0, .SetFlags = 0, @@ -14243,6 +14745,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_PF, .ModifiedFlags = 0, .SetFlags = 0, @@ -14272,6 +14775,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF, .ModifiedFlags = 0, .SetFlags = 0, @@ -14300,6 +14804,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF, .ModifiedFlags = 0, .SetFlags = 0, @@ -14328,6 +14833,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF, .ModifiedFlags = 0, .SetFlags = 0, @@ -14356,6 +14862,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF, .ModifiedFlags = 0, .SetFlags = 0, @@ -14384,6 +14891,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF, .ModifiedFlags = 0, .SetFlags = 0, @@ -14412,6 +14920,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF, .ModifiedFlags = 0, .SetFlags = 0, @@ -14440,6 +14949,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF, .ModifiedFlags = 0, .SetFlags = 0, @@ -14469,6 +14979,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF, .ModifiedFlags = 0, .SetFlags = 0, @@ -14498,6 +15009,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -14526,6 +15038,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -14554,6 +15067,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -14582,6 +15096,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -14610,6 +15125,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -14638,6 +15154,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -14666,6 +15183,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -14695,6 +15213,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -14724,6 +15243,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -14752,6 +15272,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -14780,6 +15301,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -14808,6 +15330,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -14836,6 +15359,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -14864,6 +15388,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -14892,6 +15417,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -14921,6 +15447,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -14950,6 +15477,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_PF, .ModifiedFlags = 0, .SetFlags = 0, @@ -14978,6 +15506,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_PF, .ModifiedFlags = 0, .SetFlags = 0, @@ -15006,6 +15535,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_PF, .ModifiedFlags = 0, .SetFlags = 0, @@ -15034,6 +15564,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_PF, .ModifiedFlags = 0, .SetFlags = 0, @@ -15062,6 +15593,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_PF, .ModifiedFlags = 0, .SetFlags = 0, @@ -15090,6 +15622,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_PF, .ModifiedFlags = 0, .SetFlags = 0, @@ -15118,6 +15651,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_PF, .ModifiedFlags = 0, .SetFlags = 0, @@ -15147,6 +15681,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_PF, .ModifiedFlags = 0, .SetFlags = 0, @@ -15176,6 +15711,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF, .ModifiedFlags = 0, .SetFlags = 0, @@ -15204,6 +15740,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF, .ModifiedFlags = 0, .SetFlags = 0, @@ -15232,6 +15769,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF, .ModifiedFlags = 0, .SetFlags = 0, @@ -15260,6 +15798,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF, .ModifiedFlags = 0, .SetFlags = 0, @@ -15288,6 +15827,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF, .ModifiedFlags = 0, .SetFlags = 0, @@ -15316,6 +15856,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF, .ModifiedFlags = 0, .SetFlags = 0, @@ -15344,6 +15885,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF, .ModifiedFlags = 0, .SetFlags = 0, @@ -15373,6 +15915,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF, .ModifiedFlags = 0, .SetFlags = 0, @@ -15402,6 +15945,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -15430,6 +15974,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -15458,6 +16003,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -15486,6 +16032,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -15514,6 +16061,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -15542,6 +16090,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -15570,6 +16119,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -15599,6 +16149,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CFCMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -15628,6 +16179,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -15654,6 +16206,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -15680,6 +16233,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -15706,6 +16260,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -15732,6 +16287,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -15758,6 +16314,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -15784,6 +16341,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -15810,6 +16368,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -15836,6 +16395,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -15862,6 +16422,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -15888,6 +16449,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF, .SetFlags = 0, @@ -15915,6 +16477,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -15941,6 +16504,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -15967,6 +16531,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -15993,6 +16558,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -16019,6 +16585,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF, .SetFlags = 0, @@ -16045,6 +16612,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -16074,6 +16642,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -16103,6 +16672,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -16131,6 +16701,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0, .SetFlags = 0, @@ -16160,6 +16731,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0, .SetFlags = 0, @@ -16189,6 +16761,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0, .SetFlags = 0, @@ -16217,6 +16790,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -16246,6 +16820,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -16275,6 +16850,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -16303,6 +16879,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -16332,6 +16909,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -16361,6 +16939,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -16389,6 +16968,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -16418,6 +16998,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -16447,6 +17028,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -16475,6 +17057,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0, .SetFlags = 0, @@ -16504,6 +17087,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0, .SetFlags = 0, @@ -16533,6 +17117,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0, .SetFlags = 0, @@ -16561,6 +17146,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -16590,6 +17176,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -16619,6 +17206,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -16647,6 +17235,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -16676,6 +17265,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -16705,6 +17295,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -16733,6 +17324,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -16762,6 +17354,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -16791,6 +17384,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -16819,6 +17413,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_PF, .ModifiedFlags = 0, .SetFlags = 0, @@ -16848,6 +17443,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_PF, .ModifiedFlags = 0, .SetFlags = 0, @@ -16877,6 +17473,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_PF, .ModifiedFlags = 0, .SetFlags = 0, @@ -16905,6 +17502,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF, .ModifiedFlags = 0, .SetFlags = 0, @@ -16934,6 +17532,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF, .ModifiedFlags = 0, .SetFlags = 0, @@ -16963,6 +17562,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF, .ModifiedFlags = 0, .SetFlags = 0, @@ -16991,6 +17591,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -17020,6 +17621,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -17049,6 +17651,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -17077,6 +17680,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -17106,6 +17710,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -17135,6 +17740,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -17163,6 +17769,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_PF, .ModifiedFlags = 0, .SetFlags = 0, @@ -17192,6 +17799,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_PF, .ModifiedFlags = 0, .SetFlags = 0, @@ -17221,6 +17829,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_PF, .ModifiedFlags = 0, .SetFlags = 0, @@ -17249,6 +17858,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF, .ModifiedFlags = 0, .SetFlags = 0, @@ -17278,6 +17888,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF, .ModifiedFlags = 0, .SetFlags = 0, @@ -17307,6 +17918,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF, .ModifiedFlags = 0, .SetFlags = 0, @@ -17335,6 +17947,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -17364,6 +17977,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -17393,6 +18007,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -17421,6 +18036,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -17449,6 +18065,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -17477,6 +18094,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -17505,6 +18123,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -17533,6 +18152,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -17561,6 +18181,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -17589,6 +18210,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -17617,6 +18239,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -17645,6 +18268,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -17673,6 +18297,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -17701,6 +18326,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CMPCCXADD, .FpuFlags = 0, .EvexMode = ND_EVEXM_VEX, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -17730,6 +18356,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_14, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -17759,6 +18386,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CMPCCXADD, .FpuFlags = 0, .EvexMode = ND_EVEXM_VEX, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -17788,6 +18416,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_14, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -17817,6 +18446,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CMPCCXADD, .FpuFlags = 0, .EvexMode = ND_EVEXM_VEX, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -17846,6 +18476,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_14, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -17875,6 +18506,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CMPCCXADD, .FpuFlags = 0, .EvexMode = ND_EVEXM_VEX, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -17904,6 +18536,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_14, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -17933,6 +18566,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CMPCCXADD, .FpuFlags = 0, .EvexMode = ND_EVEXM_VEX, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -17962,6 +18596,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_14, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -17991,6 +18626,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CMPCCXADD, .FpuFlags = 0, .EvexMode = ND_EVEXM_VEX, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -18020,6 +18656,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_14, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -18049,6 +18686,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CMPCCXADD, .FpuFlags = 0, .EvexMode = ND_EVEXM_VEX, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -18078,6 +18716,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_14, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -18107,6 +18746,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CMPCCXADD, .FpuFlags = 0, .EvexMode = ND_EVEXM_VEX, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -18136,6 +18776,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_14, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -18165,6 +18806,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CMPCCXADD, .FpuFlags = 0, .EvexMode = ND_EVEXM_VEX, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -18194,6 +18836,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_14, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -18223,6 +18866,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CMPCCXADD, .FpuFlags = 0, .EvexMode = ND_EVEXM_VEX, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -18252,6 +18896,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_14, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -18281,6 +18926,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CMPCCXADD, .FpuFlags = 0, .EvexMode = ND_EVEXM_VEX, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -18310,6 +18956,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_14, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -18339,6 +18986,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CMPCCXADD, .FpuFlags = 0, .EvexMode = ND_EVEXM_VEX, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -18368,6 +19016,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_14, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -18397,6 +19046,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CMPCCXADD, .FpuFlags = 0, .EvexMode = ND_EVEXM_VEX, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -18426,6 +19076,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_14, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -18455,6 +19106,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -18483,6 +19135,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -18511,6 +19164,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CMPCCXADD, .FpuFlags = 0, .EvexMode = ND_EVEXM_VEX, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -18540,6 +19194,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_14, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -18569,6 +19224,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_DF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -18599,6 +19255,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_ZF|NDR_RFLAG_DF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -18630,6 +19287,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_DF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -18660,6 +19318,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_ZF|NDR_RFLAG_DF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -18691,6 +19350,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -18719,6 +19379,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_DF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -18749,6 +19410,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_ZF|NDR_RFLAG_DF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -18780,6 +19442,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -18808,6 +19471,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_DF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -18838,6 +19502,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_ZF|NDR_RFLAG_DF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -18869,6 +19534,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CMPCCXADD, .FpuFlags = 0, .EvexMode = ND_EVEXM_VEX, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -18898,6 +19564,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_14, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -18927,6 +19594,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -18956,6 +19624,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -18985,6 +19654,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_ZF, .SetFlags = 0, @@ -19016,6 +19686,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_ZF, .SetFlags = 0, @@ -19047,6 +19718,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CMPCCXADD, .FpuFlags = 0, .EvexMode = ND_EVEXM_VEX, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -19076,6 +19748,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_14, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -19105,6 +19778,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, .SetFlags = 0, @@ -19133,6 +19807,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, .SetFlags = 0, @@ -19161,6 +19836,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -19190,6 +19866,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -19217,6 +19894,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -19244,6 +19922,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -19271,6 +19950,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -19298,6 +19978,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -19325,6 +20006,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -19352,6 +20034,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -19381,6 +20064,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -19410,6 +20094,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -19439,6 +20124,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -19468,6 +20154,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -19497,6 +20184,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -19526,6 +20214,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -19555,6 +20244,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -19584,6 +20274,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -19613,6 +20304,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0, .SetFlags = 0, @@ -19642,6 +20334,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0, .SetFlags = 0, @@ -19671,6 +20364,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0, .SetFlags = 0, @@ -19700,6 +20394,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0, .SetFlags = 0, @@ -19729,6 +20424,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0, .SetFlags = 0, @@ -19758,6 +20454,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0, .SetFlags = 0, @@ -19787,6 +20484,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0, .SetFlags = 0, @@ -19816,6 +20514,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0, .SetFlags = 0, @@ -19845,6 +20544,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0, .SetFlags = 0, @@ -19874,6 +20574,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -19903,6 +20604,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -19932,6 +20634,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -19961,6 +20664,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -19990,6 +20694,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -20019,6 +20724,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -20048,6 +20754,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -20077,6 +20784,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -20106,6 +20814,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -20135,6 +20844,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -20164,6 +20874,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -20193,6 +20904,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -20222,6 +20934,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -20251,6 +20964,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -20280,6 +20994,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -20309,6 +21024,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -20338,6 +21054,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -20367,6 +21084,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -20396,6 +21114,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -20425,6 +21144,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -20454,6 +21174,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -20483,6 +21204,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -20512,6 +21234,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -20541,6 +21264,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -20570,6 +21294,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -20599,6 +21324,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -20628,6 +21354,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -20657,6 +21384,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -20686,6 +21414,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -20715,6 +21444,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -20744,6 +21474,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -20773,6 +21504,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -20802,6 +21534,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -20831,6 +21564,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -20860,6 +21594,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -20889,6 +21624,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -20918,6 +21654,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0, .SetFlags = 0, @@ -20947,6 +21684,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0, .SetFlags = 0, @@ -20976,6 +21714,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0, .SetFlags = 0, @@ -21005,6 +21744,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0, .SetFlags = 0, @@ -21034,6 +21774,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0, .SetFlags = 0, @@ -21063,6 +21804,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0, .SetFlags = 0, @@ -21092,6 +21834,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0, .SetFlags = 0, @@ -21121,6 +21864,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0, .SetFlags = 0, @@ -21150,6 +21894,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0, .SetFlags = 0, @@ -21179,6 +21924,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -21208,6 +21954,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -21237,6 +21984,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -21266,6 +22014,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -21295,6 +22044,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -21324,6 +22074,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -21353,6 +22104,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -21382,6 +22134,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -21411,6 +22164,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -21440,6 +22194,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -21469,6 +22224,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -21498,6 +22254,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -21527,6 +22284,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -21556,6 +22314,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -21585,6 +22344,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -21614,6 +22374,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -21643,6 +22404,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -21672,6 +22434,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -21701,6 +22464,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -21730,6 +22494,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -21759,6 +22524,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -21788,6 +22554,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -21817,6 +22584,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -21846,6 +22614,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -21875,6 +22644,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -21904,6 +22674,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -21933,6 +22704,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -21962,6 +22734,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF, .ModifiedFlags = 0, .SetFlags = 0, @@ -21991,6 +22764,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF, .ModifiedFlags = 0, .SetFlags = 0, @@ -22020,6 +22794,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF, .ModifiedFlags = 0, .SetFlags = 0, @@ -22049,6 +22824,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF, .ModifiedFlags = 0, .SetFlags = 0, @@ -22078,6 +22854,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF, .ModifiedFlags = 0, .SetFlags = 0, @@ -22107,6 +22884,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF, .ModifiedFlags = 0, .SetFlags = 0, @@ -22136,6 +22914,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF, .ModifiedFlags = 0, .SetFlags = 0, @@ -22165,6 +22944,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF, .ModifiedFlags = 0, .SetFlags = 0, @@ -22194,6 +22974,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF, .ModifiedFlags = 0, .SetFlags = 0, @@ -22223,6 +23004,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -22252,6 +23034,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -22281,6 +23064,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -22310,6 +23094,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -22339,6 +23124,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -22368,6 +23154,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -22397,6 +23184,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -22426,6 +23214,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -22455,6 +23244,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -22484,6 +23274,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -22513,6 +23304,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -22542,6 +23334,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -22571,6 +23364,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -22600,6 +23394,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -22629,6 +23424,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -22658,6 +23454,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -22687,6 +23484,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -22716,6 +23514,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -22745,6 +23544,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF, .ModifiedFlags = 0, .SetFlags = 0, @@ -22774,6 +23574,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF, .ModifiedFlags = 0, .SetFlags = 0, @@ -22803,6 +23604,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF, .ModifiedFlags = 0, .SetFlags = 0, @@ -22832,6 +23634,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF, .ModifiedFlags = 0, .SetFlags = 0, @@ -22861,6 +23664,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF, .ModifiedFlags = 0, .SetFlags = 0, @@ -22890,6 +23694,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF, .ModifiedFlags = 0, .SetFlags = 0, @@ -22919,6 +23724,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF, .ModifiedFlags = 0, .SetFlags = 0, @@ -22948,6 +23754,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF, .ModifiedFlags = 0, .SetFlags = 0, @@ -22977,6 +23784,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF, .ModifiedFlags = 0, .SetFlags = 0, @@ -23006,6 +23814,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -23035,6 +23844,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -23064,6 +23874,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -23093,6 +23904,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -23122,6 +23934,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -23151,6 +23964,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -23180,6 +23994,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -23209,6 +24024,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -23238,6 +24054,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -23267,6 +24084,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -23296,6 +24114,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -23325,6 +24144,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -23354,6 +24174,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -23383,6 +24204,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -23412,6 +24234,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -23441,6 +24264,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -23470,6 +24294,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -23499,6 +24324,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_CCMP, .FpuFlags = 0, .EvexMode = ND_EVEXM_COND, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -23528,6 +24354,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -23555,6 +24382,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -23582,6 +24410,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -23609,6 +24438,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -23636,6 +24466,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -23663,6 +24494,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -23690,6 +24522,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -23717,6 +24550,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -23744,6 +24578,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -23771,6 +24606,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -23798,6 +24634,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -23825,6 +24662,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -23852,6 +24690,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -23879,6 +24718,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -23906,6 +24746,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -23933,6 +24774,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -23960,6 +24802,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -23987,6 +24830,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -24014,6 +24858,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -24041,6 +24886,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -24068,6 +24914,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -24095,6 +24942,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -24122,6 +24970,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -24149,6 +24998,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -24176,6 +25026,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF, .SetFlags = 0|NDR_RFLAG_OF, @@ -24203,6 +25054,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_OF, @@ -24230,6 +25082,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -24257,6 +25110,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -24284,6 +25138,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -24311,6 +25166,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -24337,6 +25193,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -24363,6 +25220,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -24389,6 +25247,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -24417,6 +25276,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -24445,6 +25305,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -24473,6 +25334,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -24500,6 +25362,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -24527,6 +25390,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -24554,6 +25418,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -24581,6 +25446,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -24608,6 +25474,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -24635,6 +25502,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -24662,6 +25530,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -24689,6 +25558,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -24716,6 +25586,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -24743,6 +25614,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -24770,6 +25642,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -24797,6 +25670,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -24824,6 +25698,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -24850,6 +25725,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, @@ -24880,6 +25756,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, @@ -24909,6 +25786,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, @@ -24938,6 +25816,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -24967,6 +25846,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -24995,6 +25875,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -25023,6 +25904,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, @@ -25053,6 +25935,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, @@ -25082,6 +25965,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE|ND_SIMD_EXC_ZE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -25109,6 +25993,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE|ND_SIMD_EXC_ZE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -25136,6 +26021,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE|ND_SIMD_EXC_ZE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -25163,6 +26049,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE|ND_SIMD_EXC_ZE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -25190,6 +26077,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -25218,6 +26106,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -25246,6 +26135,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -25272,6 +26162,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -25301,6 +26192,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -25330,6 +26222,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -25359,6 +26252,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -25390,6 +26284,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -25420,6 +26315,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -25446,6 +26342,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -25472,6 +26369,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_ENQCMD, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_ZF, .SetFlags = 0, @@ -25500,6 +26398,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_ZF, .SetFlags = 0, @@ -25528,6 +26427,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_ENQCMD, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_ZF, .SetFlags = 0, @@ -25556,6 +26456,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_ZF, .SetFlags = 0, @@ -25584,6 +26485,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -25616,6 +26518,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -25646,6 +26549,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -25680,6 +26584,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -25708,6 +26613,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -25736,6 +26642,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -25763,6 +26670,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xfb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -25789,6 +26697,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xf3, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -25815,6 +26724,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xfb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -25843,6 +26753,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xfb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -25871,6 +26782,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xfb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -25899,6 +26811,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xfb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -25927,6 +26840,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xfb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -25955,6 +26869,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xfb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -25983,6 +26898,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xfb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -26011,6 +26927,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xf3, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -26037,6 +26954,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xfb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0, .SetFlags = 0, @@ -26066,6 +26984,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xfb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -26095,6 +27014,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xfb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -26124,6 +27044,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xfb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0, .SetFlags = 0, @@ -26153,6 +27074,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xfb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -26182,6 +27104,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xfb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -26211,6 +27134,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xfb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_PF, .ModifiedFlags = 0, .SetFlags = 0, @@ -26240,6 +27164,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xfb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_PF, .ModifiedFlags = 0, .SetFlags = 0, @@ -26269,6 +27194,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xa2, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -26297,6 +27223,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xa2, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -26325,6 +27252,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xa2, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -26353,6 +27281,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xa2, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -26381,6 +27310,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xa2, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, .SetFlags = 0, @@ -26410,6 +27340,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xa2, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, .SetFlags = 0, @@ -26439,6 +27370,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xa2, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -26467,6 +27399,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xa2, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -26495,6 +27428,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xa2, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -26523,6 +27457,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xa2, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -26551,6 +27486,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xa2, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -26579,6 +27515,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xa2, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -26605,6 +27542,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xeb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -26631,6 +27569,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xf3, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -26657,6 +27596,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xfb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -26685,6 +27625,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xfb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -26713,6 +27654,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xfb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -26741,6 +27683,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xfb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -26769,6 +27712,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xfb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -26797,6 +27741,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xfb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -26825,6 +27770,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xfb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -26853,6 +27799,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xfb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -26881,6 +27828,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xfb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -26909,6 +27857,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xfb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -26937,6 +27886,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -26963,6 +27913,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xff, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -26990,6 +27941,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xff, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -27017,6 +27969,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xfb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -27045,6 +27998,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xfb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -27073,6 +28027,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xaa, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -27101,6 +28056,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xaa, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -27129,6 +28085,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xaa, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -27157,6 +28114,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xaa, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -27185,6 +28143,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xfb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -27213,6 +28172,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xfb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -27241,6 +28201,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xfb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -27269,6 +28230,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xfb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -27297,6 +28259,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xfb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -27325,6 +28288,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xfb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -27353,6 +28317,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xfb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -27381,6 +28346,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xfb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -27409,6 +28375,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xfb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -27437,6 +28404,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xf3, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -27463,6 +28431,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xfb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -27491,6 +28460,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xfb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -27519,6 +28489,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xfb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -27547,6 +28518,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xfb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -27575,6 +28547,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xfb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -27603,6 +28576,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xf3, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -27631,6 +28605,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xf3, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -27659,6 +28634,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xf3, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -27687,6 +28663,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xfb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -27715,6 +28692,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xfb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -27743,6 +28721,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xfb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -27771,6 +28750,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xfb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -27799,6 +28779,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xfb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -27827,6 +28808,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xfb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -27855,6 +28837,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xfb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -27883,6 +28866,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xfb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -27911,6 +28895,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xfb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -27937,6 +28922,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xff, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -27965,6 +28951,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xaa, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -27992,6 +28979,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xfb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -28018,6 +29006,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xfb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -28044,6 +29033,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xfb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -28070,6 +29060,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xfb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -28096,6 +29087,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xfb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -28122,6 +29114,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xfb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -28148,6 +29141,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xfb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -28176,6 +29170,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xfb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -28204,6 +29199,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xfb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -28232,6 +29228,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xfb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -28260,6 +29257,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xfb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -28288,6 +29286,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xff, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -28314,6 +29313,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xff, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -28340,6 +29340,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0x00, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -28368,6 +29369,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xff, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -28394,6 +29396,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xff, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -28420,6 +29423,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xff, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -28446,6 +29450,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0x00, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -28475,6 +29480,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xff, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -28503,6 +29509,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xff, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -28530,6 +29537,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xff, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -28557,6 +29565,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xff, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -28584,6 +29593,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xfb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -28610,6 +29620,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xaa, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -28636,6 +29647,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xaa, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -28662,6 +29674,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xeb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -28688,6 +29701,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xff, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -28714,6 +29728,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xfb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -28740,6 +29755,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xaa, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -28767,6 +29783,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xfb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -28793,6 +29810,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xeb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -28819,6 +29837,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xeb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -28845,6 +29864,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xfb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -28871,6 +29891,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xfb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -28899,6 +29920,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xfb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -28927,6 +29949,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xfb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -28955,6 +29978,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xff, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -28981,6 +30005,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xfb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -29009,6 +30034,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xfb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -29037,6 +30063,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xfb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -29065,6 +30092,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xfb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -29093,6 +30121,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xfb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -29121,6 +30150,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xfb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -29149,6 +30179,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xff, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -29177,6 +30208,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xff, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -29203,6 +30235,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xfb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -29231,6 +30264,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xfb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -29259,6 +30293,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xfb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -29287,6 +30322,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xfb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -29315,6 +30351,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xfb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -29343,6 +30380,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xfb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -29371,6 +30409,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xfb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -29399,6 +30438,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xfb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -29427,6 +30467,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xfb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -29455,6 +30496,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xfb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -29483,6 +30525,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xa2, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -29509,6 +30552,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xaa, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -29537,6 +30581,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xa2, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, .SetFlags = 0, @@ -29566,6 +30611,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xa2, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, .SetFlags = 0, @@ -29595,6 +30641,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xaa, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -29623,6 +30670,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xaa, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -29649,6 +30697,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xaa, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -29675,6 +30724,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xf3, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -29703,6 +30753,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xf3, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -29731,6 +30782,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xf3, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -29759,6 +30811,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -29786,6 +30839,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -29813,6 +30867,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -29840,6 +30895,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -29867,6 +30923,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xfb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -29893,6 +30950,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xfb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -29919,6 +30977,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xfb, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -29945,6 +31004,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -29972,6 +31032,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -30000,6 +31061,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -30028,6 +31090,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -30055,6 +31118,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -30082,6 +31146,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -30109,6 +31174,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -30135,6 +31201,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -30162,6 +31229,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -30189,6 +31257,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -30216,6 +31285,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, @@ -30246,6 +31316,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, @@ -30275,6 +31346,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, @@ -30304,6 +31376,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -30333,6 +31406,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -30361,6 +31435,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -30389,6 +31464,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, @@ -30419,6 +31495,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, @@ -30448,6 +31525,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, @@ -30477,6 +31555,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, @@ -30506,6 +31585,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, @@ -30535,6 +31615,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, @@ -30564,6 +31645,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -30592,6 +31674,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -30620,6 +31703,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -30648,6 +31732,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -30676,6 +31761,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, @@ -30705,6 +31791,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, @@ -30734,6 +31821,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, @@ -30763,6 +31851,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, @@ -30792,6 +31881,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -30820,6 +31910,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -30848,6 +31939,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -30876,6 +31968,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -30904,6 +31997,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, @@ -30932,6 +32026,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, @@ -30960,6 +32055,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, @@ -30989,6 +32085,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, @@ -31018,6 +32115,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, @@ -31047,6 +32145,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -31074,6 +32173,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -31101,6 +32201,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -31129,6 +32230,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -31157,6 +32259,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -31185,6 +32288,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, @@ -31214,6 +32318,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, @@ -31243,6 +32348,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -31271,6 +32377,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -31299,6 +32406,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, @@ -31328,6 +32436,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, @@ -31357,6 +32466,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, @@ -31386,6 +32496,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, @@ -31415,6 +32526,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, @@ -31443,6 +32555,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_IOPL|NDR_RFLAG_VM, .ModifiedFlags = 0, .SetFlags = 0, @@ -31471,6 +32584,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_IOPL|NDR_RFLAG_VM, .ModifiedFlags = 0, .SetFlags = 0, @@ -31499,6 +32613,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_IOPL|NDR_RFLAG_VM, .ModifiedFlags = 0, .SetFlags = 0, @@ -31527,6 +32642,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_IOPL|NDR_RFLAG_VM, .ModifiedFlags = 0, .SetFlags = 0, @@ -31555,6 +32671,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -31582,6 +32699,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -31609,6 +32727,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -31636,6 +32755,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -31662,6 +32782,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -31688,6 +32809,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -31714,6 +32836,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -31742,6 +32865,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -31770,6 +32894,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -31798,6 +32923,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -31825,6 +32951,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -31852,6 +32979,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -31879,6 +33007,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -31906,6 +33035,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -31933,6 +33063,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -31960,6 +33091,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -31987,6 +33119,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -32014,6 +33147,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -32041,6 +33175,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -32068,6 +33203,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -32095,6 +33231,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -32122,6 +33259,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -32149,6 +33287,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -32177,6 +33316,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -32205,6 +33345,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM, .ModifiedFlags = 0, .SetFlags = 0, @@ -32234,6 +33375,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM, .ModifiedFlags = 0, .SetFlags = 0, @@ -32264,6 +33406,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM, .ModifiedFlags = 0, .SetFlags = 0, @@ -32293,6 +33436,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM, .ModifiedFlags = 0, .SetFlags = 0, @@ -32323,6 +33467,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -32351,6 +33496,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -32379,6 +33525,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -32408,6 +33555,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -32435,6 +33583,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM, .ModifiedFlags = 0, .SetFlags = 0, @@ -32464,6 +33613,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM, .ModifiedFlags = 0, .SetFlags = 0, @@ -32494,6 +33644,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_VM, .ModifiedFlags = 0|NDR_RFLAG_VM|NDR_RFLAG_IF|NDR_RFLAG_NT|NDR_RFLAG_AC|NDR_RFLAG_RF|NDR_RFLAG_TF, .SetFlags = 0, @@ -32525,6 +33676,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_VM, .ModifiedFlags = 0|NDR_RFLAG_VM|NDR_RFLAG_IF|NDR_RFLAG_NT|NDR_RFLAG_AC|NDR_RFLAG_RF|NDR_RFLAG_TF, .SetFlags = 0, @@ -32554,6 +33706,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_VM, .ModifiedFlags = 0|NDR_RFLAG_VM|NDR_RFLAG_IF|NDR_RFLAG_NT|NDR_RFLAG_AC|NDR_RFLAG_RF|NDR_RFLAG_TF, .SetFlags = 0, @@ -32584,6 +33737,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_VM, .ModifiedFlags = 0|NDR_RFLAG_VM|NDR_RFLAG_IF|NDR_RFLAG_NT|NDR_RFLAG_AC|NDR_RFLAG_RF|NDR_RFLAG_TF, .SetFlags = 0, @@ -32614,6 +33768,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -32640,6 +33795,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INVEPT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .SetFlags = 0, @@ -32668,6 +33824,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .SetFlags = 0, @@ -32696,6 +33853,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -32722,6 +33880,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -32749,6 +33908,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -32777,6 +33937,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INVPCID, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -32804,6 +33965,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -32831,6 +33993,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INVVPID, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .SetFlags = 0, @@ -32859,6 +34022,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .SetFlags = 0, @@ -32887,6 +34051,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -32917,6 +34082,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -32947,6 +34113,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -32977,6 +34144,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -33005,6 +34173,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -33033,6 +34202,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0, .SetFlags = 0, @@ -33061,6 +34231,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0, .SetFlags = 0, @@ -33089,6 +34260,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -33117,6 +34289,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -33145,6 +34318,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -33173,6 +34347,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -33201,6 +34376,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -33229,6 +34405,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -33257,6 +34434,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -33284,6 +34462,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -33311,6 +34490,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -33338,6 +34518,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -33365,6 +34546,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -33392,6 +34574,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -33419,6 +34602,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -33447,6 +34631,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -33475,6 +34660,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -33503,6 +34689,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -33531,6 +34718,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0, .SetFlags = 0, @@ -33559,6 +34747,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0, .SetFlags = 0, @@ -33587,6 +34776,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -33615,6 +34805,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -33643,6 +34834,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -33671,6 +34863,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -33699,6 +34892,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -33727,6 +34921,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -33755,6 +34950,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_PF, .ModifiedFlags = 0, .SetFlags = 0, @@ -33783,6 +34979,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_PF, .ModifiedFlags = 0, .SetFlags = 0, @@ -33811,6 +35008,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF, .ModifiedFlags = 0, .SetFlags = 0, @@ -33839,6 +35037,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF, .ModifiedFlags = 0, .SetFlags = 0, @@ -33867,6 +35066,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -33895,6 +35095,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -33923,6 +35124,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -33951,6 +35153,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -33979,6 +35182,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_PF, .ModifiedFlags = 0, .SetFlags = 0, @@ -34007,6 +35211,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_PF, .ModifiedFlags = 0, .SetFlags = 0, @@ -34035,6 +35240,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -34063,6 +35269,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF, .ModifiedFlags = 0, .SetFlags = 0, @@ -34091,6 +35298,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF, .ModifiedFlags = 0, .SetFlags = 0, @@ -34119,6 +35327,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -34147,6 +35356,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -34175,6 +35385,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_K20, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -34203,6 +35414,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_K20, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -34231,6 +35443,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_K20, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -34259,6 +35472,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_K20, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -34287,6 +35501,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_K20, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -34315,6 +35530,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_K20, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -34343,6 +35559,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_K20, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -34371,6 +35588,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_K20, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -34399,6 +35617,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_K20, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -34427,6 +35646,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_K20, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -34455,6 +35675,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_K20, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -34483,6 +35704,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_K20, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -34511,6 +35733,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_K20, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -34538,6 +35761,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_K20, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -34565,6 +35789,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_KMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_VEX, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -34592,6 +35817,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_KMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_VEX, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -34619,6 +35845,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_KMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_VEX, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -34646,6 +35873,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_KMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_VEX, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -34673,6 +35901,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_KMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_VEX, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -34700,6 +35929,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_K21, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -34727,6 +35957,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_K20, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -34754,6 +35985,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_K21, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -34781,6 +36013,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_K20, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -34808,6 +36041,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_K20, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -34835,6 +36069,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_KMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_VEX, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -34862,6 +36097,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_KMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_VEX, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -34889,6 +36125,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_KMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_VEX, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -34916,6 +36153,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_KMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_VEX, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -34943,6 +36181,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_KMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_VEX, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -34970,6 +36209,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_K21, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -34997,6 +36237,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_K20, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -35024,6 +36265,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_K21, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -35051,6 +36293,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_K20, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -35078,6 +36321,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_K20, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -35105,6 +36349,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_KMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_VEX, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -35132,6 +36377,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_KMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_VEX, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -35159,6 +36405,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_KMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_VEX, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -35186,6 +36433,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_KMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_VEX, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -35213,6 +36461,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_KMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_VEX, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -35240,6 +36489,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_K21, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -35267,6 +36517,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_K20, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -35294,6 +36545,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_K21, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -35321,6 +36573,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_K20, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -35348,6 +36601,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_K20, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -35375,6 +36629,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_KMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_VEX, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -35402,6 +36657,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_KMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_VEX, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -35429,6 +36685,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_KMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_VEX, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -35456,6 +36713,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_KMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_VEX, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -35483,6 +36741,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_KMOV, .FpuFlags = 0, .EvexMode = ND_EVEXM_VEX, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -35510,6 +36769,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_K21, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -35537,6 +36797,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_K20, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -35564,6 +36825,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_K21, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -35591,6 +36853,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_K20, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -35618,6 +36881,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_K20, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -35645,6 +36909,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_K20, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -35672,6 +36937,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_K20, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -35699,6 +36965,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_K20, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -35726,6 +36993,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_K20, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -35753,6 +37021,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_K20, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -35781,6 +37050,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_K20, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -35809,6 +37079,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_K20, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -35837,6 +37108,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_K20, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .SetFlags = 0, @@ -35865,6 +37137,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_K20, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .SetFlags = 0, @@ -35893,6 +37166,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_K20, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .SetFlags = 0, @@ -35921,6 +37195,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_K20, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .SetFlags = 0, @@ -35949,6 +37224,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_K20, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -35977,6 +37253,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_K20, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -36005,6 +37282,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_K20, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -36033,6 +37311,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_K20, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -36061,6 +37340,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_K20, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -36089,6 +37369,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_K20, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -36117,6 +37398,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_K20, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -36145,6 +37427,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_K20, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -36173,6 +37456,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_K20, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -36201,6 +37485,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_K20, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -36228,6 +37513,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_K20, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -36255,6 +37541,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_K20, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -36282,6 +37569,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_K20, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -36309,6 +37597,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_K20, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -36337,6 +37626,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_K20, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -36365,6 +37655,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_K20, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -36393,6 +37684,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_K20, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -36421,6 +37713,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_K20, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -36449,6 +37742,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_K20, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -36477,6 +37771,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_K20, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -36505,6 +37800,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_K20, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -36533,6 +37829,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_K20, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -36561,6 +37858,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_K20, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -36589,6 +37887,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_K20, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -36617,6 +37916,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .ModifiedFlags = 0, .SetFlags = 0, @@ -36644,6 +37944,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_ZF, .SetFlags = 0, @@ -36672,6 +37973,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_ZF, .SetFlags = 0, @@ -36700,6 +38002,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -36727,6 +38030,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -36754,6 +38058,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -36782,6 +38087,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_AMX_EVEX_E1, .FpuFlags = 0, .EvexMode = ND_EVEXM_VEX, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -36808,6 +38114,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_AMX_E1, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -36834,6 +38141,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -36861,6 +38169,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -36890,6 +38199,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -36918,6 +38228,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -36944,6 +38255,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -36972,6 +38284,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -36999,6 +38312,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -37027,6 +38341,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -37054,6 +38369,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -37081,6 +38397,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -37108,6 +38425,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -37135,6 +38453,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -37161,6 +38480,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -37188,6 +38508,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_ZF, .SetFlags = 0, @@ -37218,6 +38539,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_DF, .ModifiedFlags = 0, .SetFlags = 0, @@ -37247,6 +38569,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_DF, .ModifiedFlags = 0, .SetFlags = 0, @@ -37277,6 +38600,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_DF, .ModifiedFlags = 0, .SetFlags = 0, @@ -37306,6 +38630,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_DF, .ModifiedFlags = 0, .SetFlags = 0, @@ -37336,6 +38661,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_DF, .ModifiedFlags = 0, .SetFlags = 0, @@ -37365,6 +38691,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_DF, .ModifiedFlags = 0, .SetFlags = 0, @@ -37395,6 +38722,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_DF, .ModifiedFlags = 0, .SetFlags = 0, @@ -37424,6 +38752,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_DF, .ModifiedFlags = 0, .SetFlags = 0, @@ -37454,6 +38783,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -37483,6 +38813,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -37512,6 +38843,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -37541,6 +38873,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_ZF, .SetFlags = 0, @@ -37569,6 +38902,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_ZF, .SetFlags = 0, @@ -37597,6 +38931,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -37625,6 +38960,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -37652,6 +38988,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -37680,6 +39017,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -37708,6 +39046,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, @@ -37736,6 +39075,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, @@ -37764,6 +39104,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -37791,6 +39132,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -37818,6 +39160,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, @@ -37846,6 +39189,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -37874,6 +39218,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -37902,6 +39247,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -37929,6 +39275,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -37956,6 +39303,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -37983,6 +39331,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -38010,6 +39359,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF, .SetFlags = 0, @@ -38036,6 +39386,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -38062,6 +39413,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -38089,6 +39441,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -38116,6 +39469,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -38143,6 +39497,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -38170,6 +39525,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -38198,6 +39554,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -38226,6 +39583,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -38253,6 +39611,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -38280,6 +39639,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -38307,6 +39667,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -38334,6 +39695,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -38361,6 +39723,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -38388,6 +39751,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -38415,6 +39779,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -38442,6 +39807,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -38469,6 +39835,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -38496,6 +39863,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -38523,6 +39891,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -38550,6 +39919,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -38577,6 +39947,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -38604,6 +39975,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -38631,6 +40003,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -38658,6 +40031,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -38685,6 +40059,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -38712,6 +40087,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -38739,6 +40115,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -38766,6 +40143,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -38793,6 +40171,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -38820,6 +40199,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -38847,6 +40227,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -38874,6 +40255,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -38901,6 +40283,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -38928,6 +40311,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -38955,6 +40339,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -38982,6 +40367,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -39009,6 +40395,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -39036,6 +40423,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -39063,6 +40451,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -39090,6 +40479,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -39117,6 +40507,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -39144,6 +40535,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -39171,6 +40563,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -39198,6 +40591,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_1, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -39225,6 +40619,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_1, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -39252,6 +40647,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_1, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -39279,6 +40675,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_1, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -39306,6 +40703,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -39333,6 +40731,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -39360,6 +40759,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -39387,6 +40787,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -39414,6 +40815,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -39441,6 +40843,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -39468,6 +40871,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -39495,6 +40899,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -39522,6 +40927,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -39549,6 +40955,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -39576,6 +40983,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -39603,6 +41011,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -39630,6 +41039,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -39657,6 +41067,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -39684,6 +41095,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -39711,6 +41123,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -39738,6 +41151,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -39765,6 +41179,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -39792,6 +41207,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_1, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -39819,6 +41235,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_1, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -39846,6 +41263,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -39873,6 +41291,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -39900,6 +41319,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -39927,6 +41347,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -39954,6 +41375,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -39981,6 +41403,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -40008,6 +41431,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -40035,6 +41459,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_7, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -40062,6 +41487,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -40089,6 +41515,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -40116,6 +41543,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -40143,6 +41571,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_7, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -40170,6 +41599,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_7, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -40197,6 +41627,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_1, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -40224,6 +41655,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_1, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -40251,6 +41683,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -40278,6 +41711,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_1, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -40305,6 +41739,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_1, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -40332,6 +41767,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -40359,6 +41795,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -40386,6 +41823,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -40413,6 +41851,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -40440,6 +41879,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -40467,6 +41907,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -40494,6 +41935,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -40521,6 +41963,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -40548,6 +41991,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -40575,6 +42019,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -40602,6 +42047,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -40629,6 +42075,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -40642,12 +42089,68 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1447 Instruction:"MOVSB Yb,Xb" Encoding:"0xA4"/"" + // Pos:1447 Instruction:"MOVRS Gb,Mb" Encoding:"0x0F 0x38 0x8A /r:mem"/"RM" + { + .Instruction = ND_INS_MOVRS, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_MOVRS, + .Mnemonic = 520, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .SimdExc = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREP|ND_FLAG_MODRM|ND_FLAG_O64, + .CpuidFlag = ND_CFF_MOVRS, + .Operands = + { + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1448 Instruction:"MOVRS Gv,Mv" Encoding:"0x0F 0x38 0x8B /r:mem"/"RM" + { + .Instruction = ND_INS_MOVRS, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_MOVRS, + .Mnemonic = 520, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .SimdExc = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREP|ND_FLAG_MODRM|ND_FLAG_O64, + .CpuidFlag = ND_CFF_MOVRS, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1449 Instruction:"MOVSB Yb,Xb" Encoding:"0xA4"/"" { .Instruction = ND_INS_MOVS, .Category = ND_CAT_STRINGOP, .IsaSet = ND_SET_I86, - .Mnemonic = 520, + .Mnemonic = 521, .ValidPrefixes = ND_PREF_REP, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -40656,6 +42159,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_DF, .ModifiedFlags = 0, .SetFlags = 0, @@ -40672,12 +42176,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1448 Instruction:"MOVSB Yb,Xb" Encoding:"rep 0xA4"/"" + // Pos:1450 Instruction:"MOVSB Yb,Xb" Encoding:"rep 0xA4"/"" { .Instruction = ND_INS_MOVS, .Category = ND_CAT_STRINGOP, .IsaSet = ND_SET_I86, - .Mnemonic = 520, + .Mnemonic = 521, .ValidPrefixes = ND_PREF_REP, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -40686,6 +42190,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_DF, .ModifiedFlags = 0, .SetFlags = 0, @@ -40703,12 +42208,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1449 Instruction:"MOVSD Yv,Xv" Encoding:"ds32 0xA5"/"" + // Pos:1451 Instruction:"MOVSD Yv,Xv" Encoding:"ds32 0xA5"/"" { .Instruction = ND_INS_MOVS, .Category = ND_CAT_STRINGOP, .IsaSet = ND_SET_I86, - .Mnemonic = 521, + .Mnemonic = 522, .ValidPrefixes = ND_PREF_REP, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -40717,6 +42222,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_DF, .ModifiedFlags = 0, .SetFlags = 0, @@ -40733,12 +42239,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1450 Instruction:"MOVSD Yv,Xv" Encoding:"rep ds32 0xA5"/"" + // Pos:1452 Instruction:"MOVSD Yv,Xv" Encoding:"rep ds32 0xA5"/"" { .Instruction = ND_INS_MOVS, .Category = ND_CAT_STRINGOP, .IsaSet = ND_SET_I86, - .Mnemonic = 521, + .Mnemonic = 522, .ValidPrefixes = ND_PREF_REP, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -40747,6 +42253,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_DF, .ModifiedFlags = 0, .SetFlags = 0, @@ -40764,12 +42271,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1451 Instruction:"MOVSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x10 /r"/"RM" + // Pos:1453 Instruction:"MOVSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x10 /r"/"RM" { .Instruction = ND_INS_MOVSD, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_SSE2, - .Mnemonic = 521, + .Mnemonic = 522, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -40778,6 +42285,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -40791,12 +42299,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1452 Instruction:"MOVSD Wsd,Vsd" Encoding:"0xF2 0x0F 0x11 /r"/"MR" + // Pos:1454 Instruction:"MOVSD Wsd,Vsd" Encoding:"0xF2 0x0F 0x11 /r"/"MR" { .Instruction = ND_INS_MOVSD, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_SSE2, - .Mnemonic = 521, + .Mnemonic = 522, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -40805,6 +42313,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -40818,12 +42327,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1453 Instruction:"MOVSHDUP Vx,Wx" Encoding:"0xF3 0x0F 0x16 /r"/"RM" + // Pos:1455 Instruction:"MOVSHDUP Vx,Wx" Encoding:"0xF3 0x0F 0x16 /r"/"RM" { .Instruction = ND_INS_MOVSHDUP, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_SSE3, - .Mnemonic = 522, + .Mnemonic = 523, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -40832,6 +42341,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -40845,12 +42355,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1454 Instruction:"MOVSLDUP Vx,Wx" Encoding:"0xF3 0x0F 0x12 /r"/"RM" + // Pos:1456 Instruction:"MOVSLDUP Vx,Wx" Encoding:"0xF3 0x0F 0x12 /r"/"RM" { .Instruction = ND_INS_MOVSLDUP, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_SSE3, - .Mnemonic = 523, + .Mnemonic = 524, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -40859,6 +42369,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -40872,12 +42383,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1455 Instruction:"MOVSQ Yv,Xv" Encoding:"ds64 0xA5"/"" + // Pos:1457 Instruction:"MOVSQ Yv,Xv" Encoding:"ds64 0xA5"/"" { .Instruction = ND_INS_MOVS, .Category = ND_CAT_STRINGOP, .IsaSet = ND_SET_I86, - .Mnemonic = 524, + .Mnemonic = 525, .ValidPrefixes = ND_PREF_REP, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -40886,6 +42397,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_DF, .ModifiedFlags = 0, .SetFlags = 0, @@ -40902,12 +42414,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1456 Instruction:"MOVSQ Yv,Xv" Encoding:"rep ds64 0xA5"/"" + // Pos:1458 Instruction:"MOVSQ Yv,Xv" Encoding:"rep ds64 0xA5"/"" { .Instruction = ND_INS_MOVS, .Category = ND_CAT_STRINGOP, .IsaSet = ND_SET_I86, - .Mnemonic = 524, + .Mnemonic = 525, .ValidPrefixes = ND_PREF_REP, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -40916,6 +42428,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_DF, .ModifiedFlags = 0, .SetFlags = 0, @@ -40933,12 +42446,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1457 Instruction:"MOVSS Vss,Wss" Encoding:"0xF3 0x0F 0x10 /r"/"RM" + // Pos:1459 Instruction:"MOVSS Vss,Wss" Encoding:"0xF3 0x0F 0x10 /r"/"RM" { .Instruction = ND_INS_MOVSS, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_SSE, - .Mnemonic = 525, + .Mnemonic = 526, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -40947,6 +42460,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -40960,12 +42474,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1458 Instruction:"MOVSS Wss,Vss" Encoding:"0xF3 0x0F 0x11 /r"/"MR" + // Pos:1460 Instruction:"MOVSS Wss,Vss" Encoding:"0xF3 0x0F 0x11 /r"/"MR" { .Instruction = ND_INS_MOVSS, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_SSE, - .Mnemonic = 525, + .Mnemonic = 526, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -40974,6 +42488,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -40987,12 +42502,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1459 Instruction:"MOVSW Yv,Xv" Encoding:"ds16 0xA5"/"" + // Pos:1461 Instruction:"MOVSW Yv,Xv" Encoding:"ds16 0xA5"/"" { .Instruction = ND_INS_MOVS, .Category = ND_CAT_STRINGOP, .IsaSet = ND_SET_I86, - .Mnemonic = 526, + .Mnemonic = 527, .ValidPrefixes = ND_PREF_REP, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -41001,6 +42516,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_DF, .ModifiedFlags = 0, .SetFlags = 0, @@ -41017,12 +42533,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1460 Instruction:"MOVSW Yv,Xv" Encoding:"rep ds16 0xA5"/"" + // Pos:1462 Instruction:"MOVSW Yv,Xv" Encoding:"rep ds16 0xA5"/"" { .Instruction = ND_INS_MOVS, .Category = ND_CAT_STRINGOP, .IsaSet = ND_SET_I86, - .Mnemonic = 526, + .Mnemonic = 527, .ValidPrefixes = ND_PREF_REP, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -41031,6 +42547,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_DF, .ModifiedFlags = 0, .SetFlags = 0, @@ -41048,12 +42565,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1461 Instruction:"MOVSX Gv,Eb" Encoding:"0x0F 0xBE /r"/"RM" + // Pos:1463 Instruction:"MOVSX Gv,Eb" Encoding:"0x0F 0xBE /r"/"RM" { .Instruction = ND_INS_MOVSX, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_I386, - .Mnemonic = 527, + .Mnemonic = 528, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -41062,6 +42579,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -41075,12 +42593,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1462 Instruction:"MOVSX Gv,Ew" Encoding:"0x0F 0xBF /r"/"RM" + // Pos:1464 Instruction:"MOVSX Gv,Ew" Encoding:"0x0F 0xBF /r"/"RM" { .Instruction = ND_INS_MOVSX, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_I386, - .Mnemonic = 527, + .Mnemonic = 528, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -41089,6 +42607,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -41102,12 +42621,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1463 Instruction:"MOVSXD Gv,Ez" Encoding:"mo64 0x63 /r"/"RM" + // Pos:1465 Instruction:"MOVSXD Gv,Ez" Encoding:"mo64 0x63 /r"/"RM" { .Instruction = ND_INS_MOVSXD, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_LONGMODE, - .Mnemonic = 528, + .Mnemonic = 529, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -41116,6 +42635,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -41129,12 +42649,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1464 Instruction:"MOVUPD Vpd,Wpd" Encoding:"0x66 0x0F 0x10 /r"/"RM" + // Pos:1466 Instruction:"MOVUPD Vpd,Wpd" Encoding:"0x66 0x0F 0x10 /r"/"RM" { .Instruction = ND_INS_MOVUPD, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_SSE2, - .Mnemonic = 529, + .Mnemonic = 530, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -41143,6 +42663,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -41156,12 +42677,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1465 Instruction:"MOVUPD Wpd,Vpd" Encoding:"0x66 0x0F 0x11 /r"/"MR" + // Pos:1467 Instruction:"MOVUPD Wpd,Vpd" Encoding:"0x66 0x0F 0x11 /r"/"MR" { .Instruction = ND_INS_MOVUPD, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_SSE2, - .Mnemonic = 529, + .Mnemonic = 530, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -41170,6 +42691,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -41183,12 +42705,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1466 Instruction:"MOVUPS Vps,Wps" Encoding:"NP 0x0F 0x10 /r"/"RM" + // Pos:1468 Instruction:"MOVUPS Vps,Wps" Encoding:"NP 0x0F 0x10 /r"/"RM" { .Instruction = ND_INS_MOVUPS, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_SSE, - .Mnemonic = 530, + .Mnemonic = 531, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -41197,6 +42719,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -41210,12 +42733,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1467 Instruction:"MOVUPS Wps,Vps" Encoding:"NP 0x0F 0x11 /r"/"MR" + // Pos:1469 Instruction:"MOVUPS Wps,Vps" Encoding:"NP 0x0F 0x11 /r"/"MR" { .Instruction = ND_INS_MOVUPS, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_SSE, - .Mnemonic = 530, + .Mnemonic = 531, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -41224,6 +42747,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -41237,12 +42761,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1468 Instruction:"MOVZX Gv,Eb" Encoding:"0x0F 0xB6 /r"/"RM" + // Pos:1470 Instruction:"MOVZX Gv,Eb" Encoding:"0x0F 0xB6 /r"/"RM" { .Instruction = ND_INS_MOVZX, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_I386, - .Mnemonic = 531, + .Mnemonic = 532, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -41251,6 +42775,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -41264,12 +42789,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1469 Instruction:"MOVZX Gv,Ew" Encoding:"0x0F 0xB7 /r"/"RM" + // Pos:1471 Instruction:"MOVZX Gv,Ew" Encoding:"0x0F 0xB7 /r"/"RM" { .Instruction = ND_INS_MOVZX, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_I386, - .Mnemonic = 531, + .Mnemonic = 532, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -41278,6 +42803,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -41291,12 +42817,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1470 Instruction:"MPSADBW Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x42 /r ib"/"RMI" + // Pos:1472 Instruction:"MPSADBW Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x42 /r ib"/"RMI" { .Instruction = ND_INS_MPSADBW, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE4, - .Mnemonic = 532, + .Mnemonic = 533, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -41305,6 +42831,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -41319,12 +42846,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1471 Instruction:"MUL Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF6 /4"/"M" + // Pos:1473 Instruction:"MUL Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF6 /4"/"M" { .Instruction = ND_INS_MUL, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 533, + .Mnemonic = 534, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -41333,6 +42860,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, @@ -41348,12 +42876,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1472 Instruction:"MUL Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF7 /4"/"M" + // Pos:1474 Instruction:"MUL Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF7 /4"/"M" { .Instruction = ND_INS_MUL, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 533, + .Mnemonic = 534, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -41362,6 +42890,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, @@ -41377,12 +42906,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1473 Instruction:"MUL Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xF7 /4"/"M" + // Pos:1475 Instruction:"MUL Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xF7 /4"/"M" { .Instruction = ND_INS_MUL, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 533, + .Mnemonic = 534, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -41391,6 +42920,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, @@ -41406,12 +42936,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1474 Instruction:"MUL Eb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xF6 /4"/"M" + // Pos:1476 Instruction:"MUL Eb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xF6 /4"/"M" { .Instruction = ND_INS_MUL, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 533, + .Mnemonic = 534, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -41420,6 +42950,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -41434,12 +42965,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1475 Instruction:"MUL Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xF7 /4"/"M" + // Pos:1477 Instruction:"MUL Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xF7 /4"/"M" { .Instruction = ND_INS_MUL, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 533, + .Mnemonic = 534, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -41448,6 +42979,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -41462,12 +42994,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1476 Instruction:"MUL Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xF7 /4"/"M" + // Pos:1478 Instruction:"MUL Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xF7 /4"/"M" { .Instruction = ND_INS_MUL, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 533, + .Mnemonic = 534, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -41476,6 +43008,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -41490,12 +43023,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1477 Instruction:"MUL Eb" Encoding:"0xF6 /4"/"M" + // Pos:1479 Instruction:"MUL Eb" Encoding:"0xF6 /4"/"M" { .Instruction = ND_INS_MUL, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_I86, - .Mnemonic = 533, + .Mnemonic = 534, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -41504,6 +43037,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, @@ -41519,12 +43053,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1478 Instruction:"MUL Ev" Encoding:"0xF7 /4"/"M" + // Pos:1480 Instruction:"MUL Ev" Encoding:"0xF7 /4"/"M" { .Instruction = ND_INS_MUL, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_I86, - .Mnemonic = 533, + .Mnemonic = 534, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -41533,6 +43067,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, @@ -41548,12 +43083,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1479 Instruction:"MULPD Vpd,Wpd" Encoding:"0x66 0x0F 0x59 /r"/"RM" + // Pos:1481 Instruction:"MULPD Vpd,Wpd" Encoding:"0x66 0x0F 0x59 /r"/"RM" { .Instruction = ND_INS_MULPD, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE2, - .Mnemonic = 534, + .Mnemonic = 535, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -41562,6 +43097,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -41575,12 +43111,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1480 Instruction:"MULPS Vps,Wps" Encoding:"NP 0x0F 0x59 /r"/"RM" + // Pos:1482 Instruction:"MULPS Vps,Wps" Encoding:"NP 0x0F 0x59 /r"/"RM" { .Instruction = ND_INS_MULPS, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE, - .Mnemonic = 535, + .Mnemonic = 536, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -41589,6 +43125,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -41602,12 +43139,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1481 Instruction:"MULSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x59 /r"/"RM" + // Pos:1483 Instruction:"MULSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x59 /r"/"RM" { .Instruction = ND_INS_MULSD, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE2, - .Mnemonic = 536, + .Mnemonic = 537, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -41616,6 +43153,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -41629,12 +43167,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1482 Instruction:"MULSS Vss,Wss" Encoding:"0xF3 0x0F 0x59 /r"/"RM" + // Pos:1484 Instruction:"MULSS Vss,Wss" Encoding:"0xF3 0x0F 0x59 /r"/"RM" { .Instruction = ND_INS_MULSS, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE, - .Mnemonic = 537, + .Mnemonic = 538, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -41643,6 +43181,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -41656,12 +43195,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1483 Instruction:"MULX Gy,By,Ey" Encoding:"evex m:2 p:3 l:0 nf:0 0xF6 /r"/"RVM" + // Pos:1485 Instruction:"MULX Gy,By,Ey" Encoding:"evex m:2 p:3 l:0 nf:0 0xF6 /r"/"RVM" { .Instruction = ND_INS_MULX, .Category = ND_CAT_BMI2, .IsaSet = ND_SET_APX_F, - .Mnemonic = 538, + .Mnemonic = 539, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -41670,6 +43209,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_BMI, .FpuFlags = 0, .EvexMode = ND_EVEXM_VEX, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -41685,12 +43225,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1484 Instruction:"MULX Gy,By,Ey" Encoding:"vex m:2 p:3 l:0 w:x 0xF6 /r"/"RVM" + // Pos:1486 Instruction:"MULX Gy,By,Ey" Encoding:"vex m:2 p:3 l:0 w:x 0xF6 /r"/"RVM" { .Instruction = ND_INS_MULX, .Category = ND_CAT_BMI2, .IsaSet = ND_SET_BMI2, - .Mnemonic = 538, + .Mnemonic = 539, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -41699,6 +43239,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_13, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -41714,12 +43255,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1485 Instruction:"MWAIT" Encoding:"NP 0x0F 0x01 /0xC9"/"" + // Pos:1487 Instruction:"MWAIT" Encoding:"NP 0x0F 0x01 /0xC9"/"" { .Instruction = ND_INS_MWAIT, .Category = ND_CAT_MISC, .IsaSet = ND_SET_SSE3, - .Mnemonic = 539, + .Mnemonic = 540, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -41728,6 +43269,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -41741,12 +43283,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1486 Instruction:"MWAITX" Encoding:"NP 0x0F 0x01 /0xFB"/"" + // Pos:1488 Instruction:"MWAITX" Encoding:"NP 0x0F 0x01 /0xFB"/"" { .Instruction = ND_INS_MWAITX, .Category = ND_CAT_SYSTEM, .IsaSet = ND_SET_MWAITT, - .Mnemonic = 540, + .Mnemonic = 541, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -41755,6 +43297,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -41769,12 +43312,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1487 Instruction:"NEG Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF6 /3"/"M" + // Pos:1489 Instruction:"NEG Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF6 /3"/"M" { .Instruction = ND_INS_NEG, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 541, + .Mnemonic = 542, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -41783,6 +43326,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -41796,12 +43340,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1488 Instruction:"NEG Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF7 /3"/"M" + // Pos:1490 Instruction:"NEG Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF7 /3"/"M" { .Instruction = ND_INS_NEG, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 541, + .Mnemonic = 542, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -41810,6 +43354,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -41823,12 +43368,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1489 Instruction:"NEG Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xF7 /3"/"M" + // Pos:1491 Instruction:"NEG Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xF7 /3"/"M" { .Instruction = ND_INS_NEG, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 541, + .Mnemonic = 542, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -41837,6 +43382,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -41850,12 +43396,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1490 Instruction:"NEG Eb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xF6 /3"/"M" + // Pos:1492 Instruction:"NEG Eb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xF6 /3"/"M" { .Instruction = ND_INS_NEG, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 541, + .Mnemonic = 542, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -41864,6 +43410,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -41876,12 +43423,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1491 Instruction:"NEG Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xF7 /3"/"M" + // Pos:1493 Instruction:"NEG Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xF7 /3"/"M" { .Instruction = ND_INS_NEG, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 541, + .Mnemonic = 542, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -41890,6 +43437,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -41902,12 +43450,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1492 Instruction:"NEG Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xF7 /3"/"M" + // Pos:1494 Instruction:"NEG Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xF7 /3"/"M" { .Instruction = ND_INS_NEG, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 541, + .Mnemonic = 542, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -41916,6 +43464,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -41928,12 +43477,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1493 Instruction:"NEG Bb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xF6 /3"/"VM" + // Pos:1495 Instruction:"NEG Bb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xF6 /3"/"VM" { .Instruction = ND_INS_NEG, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 541, + .Mnemonic = 542, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -41942,6 +43491,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -41956,12 +43506,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1494 Instruction:"NEG Bv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xF7 /3"/"VM" + // Pos:1496 Instruction:"NEG Bv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xF7 /3"/"VM" { .Instruction = ND_INS_NEG, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 541, + .Mnemonic = 542, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -41970,6 +43520,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -41984,12 +43535,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1495 Instruction:"NEG Bv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xF7 /3"/"VM" + // Pos:1497 Instruction:"NEG Bv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xF7 /3"/"VM" { .Instruction = ND_INS_NEG, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 541, + .Mnemonic = 542, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -41998,6 +43549,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -42012,12 +43564,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1496 Instruction:"NEG Bb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xF6 /3"/"VM" + // Pos:1498 Instruction:"NEG Bb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xF6 /3"/"VM" { .Instruction = ND_INS_NEG, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 541, + .Mnemonic = 542, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -42026,6 +43578,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -42039,12 +43592,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1497 Instruction:"NEG Bv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xF7 /3"/"VM" + // Pos:1499 Instruction:"NEG Bv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xF7 /3"/"VM" { .Instruction = ND_INS_NEG, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 541, + .Mnemonic = 542, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -42053,6 +43606,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -42066,12 +43620,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1498 Instruction:"NEG Bv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xF7 /3"/"VM" + // Pos:1500 Instruction:"NEG Bv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xF7 /3"/"VM" { .Instruction = ND_INS_NEG, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 541, + .Mnemonic = 542, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -42080,6 +43634,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -42093,12 +43648,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1499 Instruction:"NEG Eb" Encoding:"0xF6 /3"/"M" + // Pos:1501 Instruction:"NEG Eb" Encoding:"0xF6 /3"/"M" { .Instruction = ND_INS_NEG, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_I86, - .Mnemonic = 541, + .Mnemonic = 542, .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -42107,6 +43662,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -42120,12 +43676,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1500 Instruction:"NEG Ev" Encoding:"0xF7 /3"/"M" + // Pos:1502 Instruction:"NEG Ev" Encoding:"0xF7 /3"/"M" { .Instruction = ND_INS_NEG, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_I86, - .Mnemonic = 541, + .Mnemonic = 542, .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -42134,6 +43690,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -42147,12 +43704,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1501 Instruction:"NOP" Encoding:"0x90"/"" + // Pos:1503 Instruction:"NOP" Encoding:"0x90"/"" { .Instruction = ND_INS_NOP, .Category = ND_CAT_NOP, .IsaSet = ND_SET_I86, - .Mnemonic = 542, + .Mnemonic = 543, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -42161,6 +43718,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -42173,12 +43731,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1502 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /0:reg"/"MR" + // Pos:1504 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /0:reg"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_NOP, .IsaSet = ND_SET_PPRO, - .Mnemonic = 542, + .Mnemonic = 543, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -42187,6 +43745,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -42200,12 +43759,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1503 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /1:reg"/"MR" + // Pos:1505 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /1:reg"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_NOP, .IsaSet = ND_SET_PPRO, - .Mnemonic = 542, + .Mnemonic = 543, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -42214,6 +43773,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -42227,12 +43787,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1504 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /2:reg"/"MR" + // Pos:1506 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /2:reg"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_NOP, .IsaSet = ND_SET_PPRO, - .Mnemonic = 542, + .Mnemonic = 543, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -42241,6 +43801,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -42254,12 +43815,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1505 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /3:reg"/"MR" + // Pos:1507 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /3:reg"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_NOP, .IsaSet = ND_SET_PPRO, - .Mnemonic = 542, + .Mnemonic = 543, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -42268,6 +43829,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -42281,12 +43843,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1506 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /4:reg"/"MR" + // Pos:1508 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /4:reg"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_NOP, .IsaSet = ND_SET_PPRO, - .Mnemonic = 542, + .Mnemonic = 543, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -42295,6 +43857,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -42308,12 +43871,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1507 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /5:reg"/"MR" + // Pos:1509 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /5:reg"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_NOP, .IsaSet = ND_SET_PPRO, - .Mnemonic = 542, + .Mnemonic = 543, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -42322,6 +43885,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -42335,12 +43899,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1508 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /6:reg"/"MR" + // Pos:1510 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /6:reg"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_NOP, .IsaSet = ND_SET_PPRO, - .Mnemonic = 542, + .Mnemonic = 543, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -42349,6 +43913,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -42362,12 +43927,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1509 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /7:reg"/"MR" + // Pos:1511 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /7:reg"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_NOP, .IsaSet = ND_SET_PPRO, - .Mnemonic = 542, + .Mnemonic = 543, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -42376,6 +43941,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -42389,12 +43955,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1510 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /0:reg"/"M" + // Pos:1512 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /0:reg"/"M" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, .IsaSet = ND_SET_PPRO, - .Mnemonic = 542, + .Mnemonic = 543, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -42403,6 +43969,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -42415,12 +43982,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1511 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /1:reg"/"M" + // Pos:1513 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /1:reg"/"M" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, .IsaSet = ND_SET_PPRO, - .Mnemonic = 542, + .Mnemonic = 543, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -42429,6 +43996,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -42441,12 +44009,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1512 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /2:reg"/"M" + // Pos:1514 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /2:reg"/"M" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, .IsaSet = ND_SET_PPRO, - .Mnemonic = 542, + .Mnemonic = 543, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -42455,6 +44023,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -42467,12 +44036,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1513 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /3:reg"/"M" + // Pos:1515 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /3:reg"/"M" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, .IsaSet = ND_SET_PPRO, - .Mnemonic = 542, + .Mnemonic = 543, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -42481,6 +44050,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -42493,12 +44063,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1514 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /4"/"M" + // Pos:1516 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /4:reg"/"M" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, .IsaSet = ND_SET_PPRO, - .Mnemonic = 542, + .Mnemonic = 543, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -42507,6 +44077,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -42519,12 +44090,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1515 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /5"/"M" + // Pos:1517 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /5"/"M" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, .IsaSet = ND_SET_PPRO, - .Mnemonic = 542, + .Mnemonic = 543, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -42533,6 +44104,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -42545,12 +44117,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1516 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /6"/"M" + // Pos:1518 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /6"/"M" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, .IsaSet = ND_SET_PPRO, - .Mnemonic = 542, + .Mnemonic = 543, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -42559,6 +44131,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -42571,12 +44144,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1517 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /7"/"M" + // Pos:1519 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /7"/"M" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, .IsaSet = ND_SET_PPRO, - .Mnemonic = 542, + .Mnemonic = 543, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -42585,6 +44158,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -42597,12 +44171,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1518 Instruction:"NOP Ev" Encoding:"0x0F 0x19 /r"/"M" + // Pos:1520 Instruction:"NOP Ev" Encoding:"0x0F 0x19 /r"/"M" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, .IsaSet = ND_SET_PPRO, - .Mnemonic = 542, + .Mnemonic = 543, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -42611,6 +44185,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -42623,12 +44198,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1519 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /0:reg"/"M" + // Pos:1521 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /0:reg"/"M" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, .IsaSet = ND_SET_PPRO, - .Mnemonic = 542, + .Mnemonic = 543, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -42637,6 +44212,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -42649,12 +44225,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1520 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /1:reg"/"M" + // Pos:1522 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /1:reg"/"M" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, .IsaSet = ND_SET_PPRO, - .Mnemonic = 542, + .Mnemonic = 543, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -42663,6 +44239,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -42675,12 +44252,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1521 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /2:reg"/"M" + // Pos:1523 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /2:reg"/"M" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, .IsaSet = ND_SET_PPRO, - .Mnemonic = 542, + .Mnemonic = 543, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -42689,6 +44266,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -42701,12 +44279,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1522 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /3:reg"/"M" + // Pos:1524 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /3:reg"/"M" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, .IsaSet = ND_SET_PPRO, - .Mnemonic = 542, + .Mnemonic = 543, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -42715,6 +44293,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -42727,12 +44306,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1523 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /4"/"M" + // Pos:1525 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /4:reg"/"M" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, .IsaSet = ND_SET_PPRO, - .Mnemonic = 542, + .Mnemonic = 543, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -42741,6 +44320,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -42753,12 +44333,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1524 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /5"/"M" + // Pos:1526 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /5"/"M" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, .IsaSet = ND_SET_PPRO, - .Mnemonic = 542, + .Mnemonic = 543, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -42767,6 +44347,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -42779,12 +44360,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1525 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /6:mem"/"M" + // Pos:1527 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /6:mem"/"M" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, .IsaSet = ND_SET_PPRO, - .Mnemonic = 542, + .Mnemonic = 543, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -42793,6 +44374,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -42805,12 +44387,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1526 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /6:reg"/"M" + // Pos:1528 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /6:reg"/"M" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, .IsaSet = ND_SET_PPRO, - .Mnemonic = 542, + .Mnemonic = 543, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -42819,6 +44401,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -42831,12 +44414,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1527 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /7:mem"/"M" + // Pos:1529 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /7:mem"/"M" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, .IsaSet = ND_SET_PPRO, - .Mnemonic = 542, + .Mnemonic = 543, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -42845,6 +44428,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -42857,12 +44441,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1528 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /7:reg"/"M" + // Pos:1530 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /7:reg"/"M" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, .IsaSet = ND_SET_PPRO, - .Mnemonic = 542, + .Mnemonic = 543, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -42871,6 +44455,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -42883,12 +44468,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1529 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1A /r"/"MR" + // Pos:1531 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1A /r"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, .IsaSet = ND_SET_PPRO, - .Mnemonic = 542, + .Mnemonic = 543, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -42897,6 +44482,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -42910,12 +44496,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1530 Instruction:"NOP Gv,Ev" Encoding:"0x0F 0x1B /r"/"RM" + // Pos:1532 Instruction:"NOP Gv,Ev" Encoding:"0x0F 0x1B /r"/"RM" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, .IsaSet = ND_SET_PPRO, - .Mnemonic = 542, + .Mnemonic = 543, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -42924,6 +44510,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -42937,12 +44524,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1531 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1C /r"/"MR" + // Pos:1533 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1C /r"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, .IsaSet = ND_SET_PPRO, - .Mnemonic = 542, + .Mnemonic = 543, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -42951,6 +44538,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -42964,12 +44552,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1532 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1D /r"/"MR" + // Pos:1534 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1D /r"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, .IsaSet = ND_SET_PPRO, - .Mnemonic = 542, + .Mnemonic = 543, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -42978,6 +44566,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -42991,12 +44580,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1533 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1E /r"/"MR" + // Pos:1535 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1E /r"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, .IsaSet = ND_SET_PPRO, - .Mnemonic = 542, + .Mnemonic = 543, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -43005,6 +44594,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -43018,12 +44608,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1534 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1F /r"/"MR" + // Pos:1536 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1F /r"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, .IsaSet = ND_SET_PPRO, - .Mnemonic = 542, + .Mnemonic = 543, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -43032,6 +44622,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -43045,12 +44636,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1535 Instruction:"NOP Gv,Ev" Encoding:"mpx NP 0x0F 0x1A /r:reg"/"RM" + // Pos:1537 Instruction:"NOP Gv,Ev" Encoding:"mpx NP 0x0F 0x1A /r:reg"/"RM" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, .IsaSet = ND_SET_PPRO, - .Mnemonic = 542, + .Mnemonic = 543, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -43059,6 +44650,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -43072,12 +44664,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1536 Instruction:"NOP Gv,Ev" Encoding:"mpx NP 0x0F 0x1B /r:reg"/"RM" + // Pos:1538 Instruction:"NOP Gv,Ev" Encoding:"mpx NP 0x0F 0x1B /r:reg"/"RM" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, .IsaSet = ND_SET_PPRO, - .Mnemonic = 542, + .Mnemonic = 543, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -43086,6 +44678,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -43099,12 +44692,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1537 Instruction:"NOP Gv,Ev" Encoding:"mpx 0xF3 0x0F 0x1B /r:reg"/"RM" + // Pos:1539 Instruction:"NOP Gv,Ev" Encoding:"mpx 0xF3 0x0F 0x1B /r:reg"/"RM" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, .IsaSet = ND_SET_PPRO, - .Mnemonic = 542, + .Mnemonic = 543, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -43113,6 +44706,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -43126,12 +44720,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1538 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x66 0x0F 0x1C /0:mem"/"MR" + // Pos:1540 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x66 0x0F 0x1C /0:mem"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, .IsaSet = ND_SET_PPRO, - .Mnemonic = 542, + .Mnemonic = 543, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -43140,6 +44734,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -43153,12 +44748,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1539 Instruction:"NOP Ev,Gv" Encoding:"cldm 0xF3 0x0F 0x1C /0:mem"/"MR" + // Pos:1541 Instruction:"NOP Ev,Gv" Encoding:"cldm 0xF3 0x0F 0x1C /0:mem"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, .IsaSet = ND_SET_PPRO, - .Mnemonic = 542, + .Mnemonic = 543, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -43167,6 +44762,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -43180,12 +44776,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1540 Instruction:"NOP Ev,Gv" Encoding:"cldm 0xF2 0x0F 0x1C /0:mem"/"MR" + // Pos:1542 Instruction:"NOP Ev,Gv" Encoding:"cldm 0xF2 0x0F 0x1C /0:mem"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, .IsaSet = ND_SET_PPRO, - .Mnemonic = 542, + .Mnemonic = 543, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -43194,6 +44790,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -43207,12 +44804,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1541 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /0:reg"/"MR" + // Pos:1543 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /0:reg"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, .IsaSet = ND_SET_PPRO, - .Mnemonic = 542, + .Mnemonic = 543, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -43221,6 +44818,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -43234,12 +44832,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1542 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /1"/"MR" + // Pos:1544 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /1"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, .IsaSet = ND_SET_PPRO, - .Mnemonic = 542, + .Mnemonic = 543, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -43248,6 +44846,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -43261,12 +44860,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1543 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /2"/"MR" + // Pos:1545 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /2"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, .IsaSet = ND_SET_PPRO, - .Mnemonic = 542, + .Mnemonic = 543, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -43275,6 +44874,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -43288,12 +44888,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1544 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /3"/"MR" + // Pos:1546 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /3"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, .IsaSet = ND_SET_PPRO, - .Mnemonic = 542, + .Mnemonic = 543, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -43302,6 +44902,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -43315,12 +44916,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1545 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /4"/"MR" + // Pos:1547 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /4"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, .IsaSet = ND_SET_PPRO, - .Mnemonic = 542, + .Mnemonic = 543, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -43329,6 +44930,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -43342,12 +44944,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1546 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /5"/"MR" + // Pos:1548 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /5"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, .IsaSet = ND_SET_PPRO, - .Mnemonic = 542, + .Mnemonic = 543, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -43356,6 +44958,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -43369,12 +44972,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1547 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /6"/"MR" + // Pos:1549 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /6"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, .IsaSet = ND_SET_PPRO, - .Mnemonic = 542, + .Mnemonic = 543, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -43383,6 +44986,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -43396,12 +45000,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1548 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /7"/"MR" + // Pos:1550 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /7"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, .IsaSet = ND_SET_PPRO, - .Mnemonic = 542, + .Mnemonic = 543, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -43410,6 +45014,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -43423,12 +45028,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1549 Instruction:"NOP Mv,Gv" Encoding:"cet 0x0F 0x1E /0:mem"/"MR" + // Pos:1551 Instruction:"NOP Mv,Gv" Encoding:"cet 0x0F 0x1E /0:mem"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, .IsaSet = ND_SET_PPRO, - .Mnemonic = 542, + .Mnemonic = 543, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -43437,6 +45042,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -43450,12 +45056,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1550 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0:reg"/"MR" + // Pos:1552 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0:reg"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, .IsaSet = ND_SET_PPRO, - .Mnemonic = 542, + .Mnemonic = 543, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -43464,6 +45070,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -43477,12 +45084,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1551 Instruction:"NOP Mv,Gv" Encoding:"cet 0x0F 0x1E /1:mem"/"MR" + // Pos:1553 Instruction:"NOP Mv,Gv" Encoding:"cet 0x0F 0x1E /1:mem"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, .IsaSet = ND_SET_PPRO, - .Mnemonic = 542, + .Mnemonic = 543, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -43491,6 +45098,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -43504,12 +45112,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1552 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /1:reg"/"MR" + // Pos:1554 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /1:reg"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, .IsaSet = ND_SET_PPRO, - .Mnemonic = 542, + .Mnemonic = 543, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -43518,6 +45126,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -43531,12 +45140,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1553 Instruction:"NOP Mv,Gv" Encoding:"cet 0x0F 0x1E /2:mem"/"MR" + // Pos:1555 Instruction:"NOP Mv,Gv" Encoding:"cet 0x0F 0x1E /2:mem"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, .IsaSet = ND_SET_PPRO, - .Mnemonic = 542, + .Mnemonic = 543, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -43545,6 +45154,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -43558,12 +45168,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1554 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /2:reg"/"MR" + // Pos:1556 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /2:reg"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, .IsaSet = ND_SET_PPRO, - .Mnemonic = 542, + .Mnemonic = 543, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -43572,6 +45182,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -43585,12 +45196,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1555 Instruction:"NOP Mv,Gv" Encoding:"cet 0x0F 0x1E /3:mem"/"MR" + // Pos:1557 Instruction:"NOP Mv,Gv" Encoding:"cet 0x0F 0x1E /3:mem"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, .IsaSet = ND_SET_PPRO, - .Mnemonic = 542, + .Mnemonic = 543, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -43599,6 +45210,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -43612,12 +45224,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1556 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /3:reg"/"MR" + // Pos:1558 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /3:reg"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, .IsaSet = ND_SET_PPRO, - .Mnemonic = 542, + .Mnemonic = 543, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -43626,6 +45238,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -43639,12 +45252,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1557 Instruction:"NOP Mv,Gv" Encoding:"cet 0x0F 0x1E /4:mem"/"MR" + // Pos:1559 Instruction:"NOP Mv,Gv" Encoding:"cet 0x0F 0x1E /4:mem"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, .IsaSet = ND_SET_PPRO, - .Mnemonic = 542, + .Mnemonic = 543, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -43653,6 +45266,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -43666,12 +45280,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1558 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /4:reg"/"MR" + // Pos:1560 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /4:reg"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, .IsaSet = ND_SET_PPRO, - .Mnemonic = 542, + .Mnemonic = 543, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -43680,6 +45294,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -43693,12 +45308,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1559 Instruction:"NOP Mv,Gv" Encoding:"cet 0x0F 0x1E /5:mem"/"MR" + // Pos:1561 Instruction:"NOP Mv,Gv" Encoding:"cet 0x0F 0x1E /5:mem"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, .IsaSet = ND_SET_PPRO, - .Mnemonic = 542, + .Mnemonic = 543, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -43707,6 +45322,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -43720,12 +45336,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1560 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /5:reg"/"MR" + // Pos:1562 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /5:reg"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, .IsaSet = ND_SET_PPRO, - .Mnemonic = 542, + .Mnemonic = 543, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -43734,6 +45350,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -43747,12 +45364,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1561 Instruction:"NOP Mv,Gv" Encoding:"cet 0x0F 0x1E /6:mem"/"MR" + // Pos:1563 Instruction:"NOP Mv,Gv" Encoding:"cet 0x0F 0x1E /6:mem"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, .IsaSet = ND_SET_PPRO, - .Mnemonic = 542, + .Mnemonic = 543, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -43761,6 +45378,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -43774,12 +45392,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1562 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /6:reg"/"MR" + // Pos:1564 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /6:reg"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, .IsaSet = ND_SET_PPRO, - .Mnemonic = 542, + .Mnemonic = 543, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -43788,6 +45406,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -43801,12 +45420,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1563 Instruction:"NOP Mv,Gv" Encoding:"cet 0x0F 0x1E /7:mem"/"MR" + // Pos:1565 Instruction:"NOP Mv,Gv" Encoding:"cet 0x0F 0x1E /7:mem"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, .IsaSet = ND_SET_PPRO, - .Mnemonic = 542, + .Mnemonic = 543, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -43815,6 +45434,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -43828,12 +45448,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1564 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xF8"/"MR" + // Pos:1566 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xF8"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, .IsaSet = ND_SET_PPRO, - .Mnemonic = 542, + .Mnemonic = 543, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -43842,6 +45462,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -43855,12 +45476,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1565 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xF9"/"MR" + // Pos:1567 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xF9"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, .IsaSet = ND_SET_PPRO, - .Mnemonic = 542, + .Mnemonic = 543, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -43869,6 +45490,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -43882,12 +45504,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1566 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFA"/"MR" + // Pos:1568 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFA"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, .IsaSet = ND_SET_PPRO, - .Mnemonic = 542, + .Mnemonic = 543, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -43896,6 +45518,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -43909,12 +45532,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1567 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFB"/"MR" + // Pos:1569 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFB"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, .IsaSet = ND_SET_PPRO, - .Mnemonic = 542, + .Mnemonic = 543, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -43923,6 +45546,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -43936,12 +45560,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1568 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFC"/"MR" + // Pos:1570 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFC"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, .IsaSet = ND_SET_PPRO, - .Mnemonic = 542, + .Mnemonic = 543, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -43950,6 +45574,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -43963,12 +45588,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1569 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFD"/"MR" + // Pos:1571 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFD"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, .IsaSet = ND_SET_PPRO, - .Mnemonic = 542, + .Mnemonic = 543, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -43977,6 +45602,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -43990,12 +45616,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1570 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFE"/"MR" + // Pos:1572 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFE"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, .IsaSet = ND_SET_PPRO, - .Mnemonic = 542, + .Mnemonic = 543, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -44004,6 +45630,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -44017,12 +45644,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1571 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFF"/"MR" + // Pos:1573 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFF"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, .IsaSet = ND_SET_PPRO, - .Mnemonic = 542, + .Mnemonic = 543, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -44031,6 +45658,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -44044,12 +45672,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1572 Instruction:"NOT Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF6 /2"/"M" + // Pos:1574 Instruction:"NOT Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF6 /2"/"M" { .Instruction = ND_INS_NOT, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 543, + .Mnemonic = 544, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -44058,6 +45686,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -44070,12 +45699,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1573 Instruction:"NOT Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF7 /2"/"M" + // Pos:1575 Instruction:"NOT Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF7 /2"/"M" { .Instruction = ND_INS_NOT, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 543, + .Mnemonic = 544, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -44084,6 +45713,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -44096,12 +45726,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1574 Instruction:"NOT Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xF7 /2"/"M" + // Pos:1576 Instruction:"NOT Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xF7 /2"/"M" { .Instruction = ND_INS_NOT, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 543, + .Mnemonic = 544, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -44110,6 +45740,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -44122,12 +45753,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1575 Instruction:"NOT Bb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xF6 /2"/"VM" + // Pos:1577 Instruction:"NOT Bb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xF6 /2"/"VM" { .Instruction = ND_INS_NOT, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 543, + .Mnemonic = 544, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -44136,6 +45767,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -44149,12 +45781,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1576 Instruction:"NOT Bv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xF7 /2"/"VM" + // Pos:1578 Instruction:"NOT Bv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xF7 /2"/"VM" { .Instruction = ND_INS_NOT, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 543, + .Mnemonic = 544, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -44163,6 +45795,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -44176,12 +45809,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1577 Instruction:"NOT Bv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xF7 /2"/"VM" + // Pos:1579 Instruction:"NOT Bv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xF7 /2"/"VM" { .Instruction = ND_INS_NOT, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 543, + .Mnemonic = 544, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -44190,6 +45823,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -44203,12 +45837,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1578 Instruction:"NOT Eb" Encoding:"0xF6 /2"/"M" + // Pos:1580 Instruction:"NOT Eb" Encoding:"0xF6 /2"/"M" { .Instruction = ND_INS_NOT, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_I86, - .Mnemonic = 543, + .Mnemonic = 544, .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -44217,6 +45851,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -44229,12 +45864,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1579 Instruction:"NOT Ev" Encoding:"0xF7 /2"/"M" + // Pos:1581 Instruction:"NOT Ev" Encoding:"0xF7 /2"/"M" { .Instruction = ND_INS_NOT, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_I86, - .Mnemonic = 543, + .Mnemonic = 544, .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -44243,6 +45878,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -44255,12 +45891,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1580 Instruction:"OR Eb,Gb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x08 /r"/"MR" + // Pos:1582 Instruction:"OR Eb,Gb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x08 /r"/"MR" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 544, + .Mnemonic = 545, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -44269,6 +45905,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -44283,12 +45920,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1581 Instruction:"OR Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x09 /r"/"MR" + // Pos:1583 Instruction:"OR Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x09 /r"/"MR" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 544, + .Mnemonic = 545, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -44297,6 +45934,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -44311,12 +45949,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1582 Instruction:"OR Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x09 /r"/"MR" + // Pos:1584 Instruction:"OR Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x09 /r"/"MR" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 544, + .Mnemonic = 545, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -44325,6 +45963,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -44339,12 +45978,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1583 Instruction:"OR Gb,Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x0A /r"/"RM" + // Pos:1585 Instruction:"OR Gb,Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x0A /r"/"RM" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 544, + .Mnemonic = 545, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -44353,6 +45992,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -44367,12 +46007,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1584 Instruction:"OR Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x0B /r"/"RM" + // Pos:1586 Instruction:"OR Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x0B /r"/"RM" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 544, + .Mnemonic = 545, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -44381,6 +46021,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -44395,12 +46036,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1585 Instruction:"OR Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x0B /r"/"RM" + // Pos:1587 Instruction:"OR Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x0B /r"/"RM" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 544, + .Mnemonic = 545, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -44409,6 +46050,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -44423,12 +46065,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1586 Instruction:"OR Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x80 /1 ib"/"MI" + // Pos:1588 Instruction:"OR Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x80 /1 ib"/"MI" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 544, + .Mnemonic = 545, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -44437,6 +46079,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -44451,12 +46094,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1587 Instruction:"OR Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x81 /1 iz"/"MI" + // Pos:1589 Instruction:"OR Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x81 /1 iz"/"MI" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 544, + .Mnemonic = 545, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -44465,6 +46108,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -44479,12 +46123,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1588 Instruction:"OR Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x81 /1 iz"/"MI" + // Pos:1590 Instruction:"OR Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x81 /1 iz"/"MI" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 544, + .Mnemonic = 545, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -44493,6 +46137,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -44507,12 +46152,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1589 Instruction:"OR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x83 /1 ib"/"MI" + // Pos:1591 Instruction:"OR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x83 /1 ib"/"MI" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 544, + .Mnemonic = 545, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -44521,6 +46166,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -44535,12 +46181,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1590 Instruction:"OR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x83 /1 ib"/"MI" + // Pos:1592 Instruction:"OR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x83 /1 ib"/"MI" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 544, + .Mnemonic = 545, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -44549,6 +46195,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -44563,12 +46210,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1591 Instruction:"OR Eb,Gb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x08 /r"/"MR" + // Pos:1593 Instruction:"OR Eb,Gb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x08 /r"/"MR" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 544, + .Mnemonic = 545, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -44577,6 +46224,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -44590,12 +46238,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1592 Instruction:"OR Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x09 /r"/"MR" + // Pos:1594 Instruction:"OR Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x09 /r"/"MR" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 544, + .Mnemonic = 545, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -44604,6 +46252,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -44617,12 +46266,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1593 Instruction:"OR Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x09 /r"/"MR" + // Pos:1595 Instruction:"OR Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x09 /r"/"MR" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 544, + .Mnemonic = 545, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -44631,6 +46280,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -44644,12 +46294,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1594 Instruction:"OR Gb,Eb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x0A /r"/"RM" + // Pos:1596 Instruction:"OR Gb,Eb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x0A /r"/"RM" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 544, + .Mnemonic = 545, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -44658,6 +46308,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -44671,12 +46322,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1595 Instruction:"OR Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x0B /r"/"RM" + // Pos:1597 Instruction:"OR Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x0B /r"/"RM" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 544, + .Mnemonic = 545, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -44685,6 +46336,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -44698,12 +46350,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1596 Instruction:"OR Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x0B /r"/"RM" + // Pos:1598 Instruction:"OR Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x0B /r"/"RM" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 544, + .Mnemonic = 545, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -44712,6 +46364,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -44725,12 +46378,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1597 Instruction:"OR Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x80 /1 ib"/"MI" + // Pos:1599 Instruction:"OR Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x80 /1 ib"/"MI" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 544, + .Mnemonic = 545, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -44739,6 +46392,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -44752,12 +46406,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1598 Instruction:"OR Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x81 /1 iz"/"MI" + // Pos:1600 Instruction:"OR Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x81 /1 iz"/"MI" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 544, + .Mnemonic = 545, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -44766,6 +46420,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -44779,12 +46434,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1599 Instruction:"OR Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x81 /1 iz"/"MI" + // Pos:1601 Instruction:"OR Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x81 /1 iz"/"MI" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 544, + .Mnemonic = 545, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -44793,6 +46448,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -44806,12 +46462,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1600 Instruction:"OR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x83 /1 ib"/"MI" + // Pos:1602 Instruction:"OR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x83 /1 ib"/"MI" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 544, + .Mnemonic = 545, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -44820,6 +46476,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -44833,12 +46490,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1601 Instruction:"OR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x83 /1 ib"/"MI" + // Pos:1603 Instruction:"OR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x83 /1 ib"/"MI" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 544, + .Mnemonic = 545, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -44847,6 +46504,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -44860,12 +46518,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1602 Instruction:"OR Bb,Eb,Gb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x08 /r"/"VMR" + // Pos:1604 Instruction:"OR Bb,Eb,Gb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x08 /r"/"VMR" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 544, + .Mnemonic = 545, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -44874,6 +46532,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -44889,12 +46548,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1603 Instruction:"OR Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x09 /r"/"VMR" + // Pos:1605 Instruction:"OR Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x09 /r"/"VMR" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 544, + .Mnemonic = 545, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -44903,6 +46562,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -44918,12 +46578,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1604 Instruction:"OR Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x09 /r"/"VMR" + // Pos:1606 Instruction:"OR Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x09 /r"/"VMR" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 544, + .Mnemonic = 545, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -44932,6 +46592,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -44947,12 +46608,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1605 Instruction:"OR Bb,Gb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x0A /r"/"VRM" + // Pos:1607 Instruction:"OR Bb,Gb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x0A /r"/"VRM" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 544, + .Mnemonic = 545, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -44961,6 +46622,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -44976,12 +46638,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1606 Instruction:"OR Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x0B /r"/"VRM" + // Pos:1608 Instruction:"OR Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x0B /r"/"VRM" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 544, + .Mnemonic = 545, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -44990,6 +46652,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -45005,12 +46668,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1607 Instruction:"OR Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x0B /r"/"VRM" + // Pos:1609 Instruction:"OR Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x0B /r"/"VRM" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 544, + .Mnemonic = 545, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -45019,6 +46682,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -45034,12 +46698,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1608 Instruction:"OR Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x80 /1 ib"/"VMI" + // Pos:1610 Instruction:"OR Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x80 /1 ib"/"VMI" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 544, + .Mnemonic = 545, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -45048,6 +46712,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -45063,12 +46728,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1609 Instruction:"OR Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x81 /1 iz"/"VMI" + // Pos:1611 Instruction:"OR Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x81 /1 iz"/"VMI" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 544, + .Mnemonic = 545, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -45077,6 +46742,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -45092,12 +46758,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1610 Instruction:"OR Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x81 /1 iz"/"VMI" + // Pos:1612 Instruction:"OR Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x81 /1 iz"/"VMI" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 544, + .Mnemonic = 545, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -45106,6 +46772,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -45121,12 +46788,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1611 Instruction:"OR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x83 /1 ib"/"VMI" + // Pos:1613 Instruction:"OR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x83 /1 ib"/"VMI" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 544, + .Mnemonic = 545, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -45135,6 +46802,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -45150,12 +46818,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1612 Instruction:"OR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x83 /1 ib"/"VMI" + // Pos:1614 Instruction:"OR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x83 /1 ib"/"VMI" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 544, + .Mnemonic = 545, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -45164,6 +46832,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -45179,12 +46848,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1613 Instruction:"OR Bb,Eb,Gb" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x08 /r"/"VMR" + // Pos:1615 Instruction:"OR Bb,Eb,Gb" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x08 /r"/"VMR" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 544, + .Mnemonic = 545, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -45193,6 +46862,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -45207,12 +46877,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1614 Instruction:"OR Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x09 /r"/"VMR" + // Pos:1616 Instruction:"OR Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x09 /r"/"VMR" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 544, + .Mnemonic = 545, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -45221,6 +46891,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -45235,12 +46906,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1615 Instruction:"OR Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x09 /r"/"VMR" + // Pos:1617 Instruction:"OR Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x09 /r"/"VMR" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 544, + .Mnemonic = 545, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -45249,6 +46920,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -45263,12 +46935,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1616 Instruction:"OR Bb,Gb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x0A /r"/"VRM" + // Pos:1618 Instruction:"OR Bb,Gb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x0A /r"/"VRM" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 544, + .Mnemonic = 545, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -45277,6 +46949,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -45291,12 +46964,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1617 Instruction:"OR Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x0B /r"/"VRM" + // Pos:1619 Instruction:"OR Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x0B /r"/"VRM" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 544, + .Mnemonic = 545, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -45305,6 +46978,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -45319,12 +46993,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1618 Instruction:"OR Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x0B /r"/"VRM" + // Pos:1620 Instruction:"OR Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x0B /r"/"VRM" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 544, + .Mnemonic = 545, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -45333,6 +47007,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -45347,12 +47022,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1619 Instruction:"OR Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x80 /1 ib"/"VMI" + // Pos:1621 Instruction:"OR Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x80 /1 ib"/"VMI" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 544, + .Mnemonic = 545, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -45361,6 +47036,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -45375,12 +47051,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1620 Instruction:"OR Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x81 /1 iz"/"VMI" + // Pos:1622 Instruction:"OR Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x81 /1 iz"/"VMI" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 544, + .Mnemonic = 545, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -45389,6 +47065,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -45403,12 +47080,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1621 Instruction:"OR Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x81 /1 iz"/"VMI" + // Pos:1623 Instruction:"OR Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x81 /1 iz"/"VMI" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 544, + .Mnemonic = 545, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -45417,6 +47094,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -45431,12 +47109,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1622 Instruction:"OR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x83 /1 ib"/"VMI" + // Pos:1624 Instruction:"OR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x83 /1 ib"/"VMI" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 544, + .Mnemonic = 545, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -45445,6 +47123,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -45459,12 +47138,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1623 Instruction:"OR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x83 /1 ib"/"VMI" + // Pos:1625 Instruction:"OR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x83 /1 ib"/"VMI" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 544, + .Mnemonic = 545, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -45473,6 +47152,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -45487,12 +47167,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1624 Instruction:"OR Eb,Gb" Encoding:"0x08 /r"/"MR" + // Pos:1626 Instruction:"OR Eb,Gb" Encoding:"0x08 /r"/"MR" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_I86, - .Mnemonic = 544, + .Mnemonic = 545, .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -45501,6 +47181,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -45515,12 +47196,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1625 Instruction:"OR Ev,Gv" Encoding:"0x09 /r"/"MR" + // Pos:1627 Instruction:"OR Ev,Gv" Encoding:"0x09 /r"/"MR" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_I86, - .Mnemonic = 544, + .Mnemonic = 545, .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -45529,6 +47210,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -45543,12 +47225,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1626 Instruction:"OR Gb,Eb" Encoding:"0x0A /r"/"RM" + // Pos:1628 Instruction:"OR Gb,Eb" Encoding:"0x0A /r"/"RM" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_I86, - .Mnemonic = 544, + .Mnemonic = 545, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -45557,6 +47239,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -45571,12 +47254,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1627 Instruction:"OR Gv,Ev" Encoding:"0x0B /r"/"RM" + // Pos:1629 Instruction:"OR Gv,Ev" Encoding:"0x0B /r"/"RM" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_I86, - .Mnemonic = 544, + .Mnemonic = 545, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -45585,6 +47268,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -45599,12 +47283,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1628 Instruction:"OR AL,Ib" Encoding:"0x0C ib"/"I" + // Pos:1630 Instruction:"OR AL,Ib" Encoding:"0x0C ib"/"I" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_I86, - .Mnemonic = 544, + .Mnemonic = 545, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -45613,6 +47297,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -45627,12 +47312,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1629 Instruction:"OR rAX,Iz" Encoding:"0x0D iz"/"I" + // Pos:1631 Instruction:"OR rAX,Iz" Encoding:"0x0D iz"/"I" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_I86, - .Mnemonic = 544, + .Mnemonic = 545, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -45641,6 +47326,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -45655,12 +47341,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1630 Instruction:"OR Eb,Ib" Encoding:"0x80 /1 ib"/"MI" + // Pos:1632 Instruction:"OR Eb,Ib" Encoding:"0x80 /1 ib"/"MI" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_I86, - .Mnemonic = 544, + .Mnemonic = 545, .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -45669,6 +47355,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -45683,12 +47370,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1631 Instruction:"OR Ev,Iz" Encoding:"0x81 /1 iz"/"MI" + // Pos:1633 Instruction:"OR Ev,Iz" Encoding:"0x81 /1 iz"/"MI" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_I86, - .Mnemonic = 544, + .Mnemonic = 545, .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -45697,6 +47384,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -45711,12 +47399,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1632 Instruction:"OR Eb,Ib" Encoding:"0x82 /1 iz"/"MI" + // Pos:1634 Instruction:"OR Eb,Ib" Encoding:"0x82 /1 iz"/"MI" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_I86, - .Mnemonic = 544, + .Mnemonic = 545, .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -45725,6 +47413,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -45739,12 +47428,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1633 Instruction:"OR Ev,Ib" Encoding:"0x83 /1 ib"/"MI" + // Pos:1635 Instruction:"OR Ev,Ib" Encoding:"0x83 /1 ib"/"MI" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_I86, - .Mnemonic = 544, + .Mnemonic = 545, .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -45753,6 +47442,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -45767,12 +47457,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1634 Instruction:"ORPD Vpd,Wpd" Encoding:"0x66 0x0F 0x56 /r"/"RM" + // Pos:1636 Instruction:"ORPD Vpd,Wpd" Encoding:"0x66 0x0F 0x56 /r"/"RM" { .Instruction = ND_INS_ORPD, .Category = ND_CAT_LOGICAL_FP, .IsaSet = ND_SET_SSE2, - .Mnemonic = 545, + .Mnemonic = 546, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -45781,6 +47471,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -45794,12 +47485,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1635 Instruction:"ORPS Vps,Wps" Encoding:"NP 0x0F 0x56 /r"/"RM" + // Pos:1637 Instruction:"ORPS Vps,Wps" Encoding:"NP 0x0F 0x56 /r"/"RM" { .Instruction = ND_INS_ORPS, .Category = ND_CAT_LOGICAL_FP, .IsaSet = ND_SET_SSE, - .Mnemonic = 546, + .Mnemonic = 547, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -45808,6 +47499,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -45821,12 +47513,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1636 Instruction:"OUT Ib,AL" Encoding:"0xE6 ib"/"I" + // Pos:1638 Instruction:"OUT Ib,AL" Encoding:"0xE6 ib"/"I" { .Instruction = ND_INS_OUT, .Category = ND_CAT_IO, .IsaSet = ND_SET_I86, - .Mnemonic = 547, + .Mnemonic = 548, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -45835,6 +47527,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_IOPL|NDR_RFLAG_VM, .ModifiedFlags = 0, .SetFlags = 0, @@ -45849,12 +47542,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1637 Instruction:"OUT Ib,eAX" Encoding:"0xE7 ib"/"I" + // Pos:1639 Instruction:"OUT Ib,eAX" Encoding:"0xE7 ib"/"I" { .Instruction = ND_INS_OUT, .Category = ND_CAT_IO, .IsaSet = ND_SET_I86, - .Mnemonic = 547, + .Mnemonic = 548, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -45863,6 +47556,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_IOPL|NDR_RFLAG_VM, .ModifiedFlags = 0, .SetFlags = 0, @@ -45877,12 +47571,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1638 Instruction:"OUT DX,AL" Encoding:"0xEE"/"" + // Pos:1640 Instruction:"OUT DX,AL" Encoding:"0xEE"/"" { .Instruction = ND_INS_OUT, .Category = ND_CAT_IO, .IsaSet = ND_SET_I86, - .Mnemonic = 547, + .Mnemonic = 548, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -45891,6 +47585,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_IOPL|NDR_RFLAG_VM, .ModifiedFlags = 0, .SetFlags = 0, @@ -45905,12 +47600,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1639 Instruction:"OUT DX,eAX" Encoding:"0xEF"/"" + // Pos:1641 Instruction:"OUT DX,eAX" Encoding:"0xEF"/"" { .Instruction = ND_INS_OUT, .Category = ND_CAT_IO, .IsaSet = ND_SET_I86, - .Mnemonic = 547, + .Mnemonic = 548, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -45919,6 +47614,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_IOPL|NDR_RFLAG_VM, .ModifiedFlags = 0, .SetFlags = 0, @@ -45933,12 +47629,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1640 Instruction:"OUTSB DX,Xb" Encoding:"0x6E"/"" + // Pos:1642 Instruction:"OUTSB DX,Xb" Encoding:"0x6E"/"" { .Instruction = ND_INS_OUTS, .Category = ND_CAT_IOSTRINGOP, .IsaSet = ND_SET_I86, - .Mnemonic = 548, + .Mnemonic = 549, .ValidPrefixes = ND_PREF_REP, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -45947,6 +47643,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM, .ModifiedFlags = 0, .SetFlags = 0, @@ -45962,12 +47659,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1641 Instruction:"OUTSB DX,Xb" Encoding:"rep 0x6E"/"" + // Pos:1643 Instruction:"OUTSB DX,Xb" Encoding:"rep 0x6E"/"" { .Instruction = ND_INS_OUTS, .Category = ND_CAT_IOSTRINGOP, .IsaSet = ND_SET_I86, - .Mnemonic = 548, + .Mnemonic = 549, .ValidPrefixes = ND_PREF_REP, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -45976,6 +47673,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM, .ModifiedFlags = 0, .SetFlags = 0, @@ -45992,12 +47690,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1642 Instruction:"OUTSD DX,Xz" Encoding:"0x6F"/"" + // Pos:1644 Instruction:"OUTSD DX,Xz" Encoding:"0x6F"/"" { .Instruction = ND_INS_OUTS, .Category = ND_CAT_IOSTRINGOP, .IsaSet = ND_SET_I86, - .Mnemonic = 549, + .Mnemonic = 550, .ValidPrefixes = ND_PREF_REP, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -46006,6 +47704,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM, .ModifiedFlags = 0, .SetFlags = 0, @@ -46021,12 +47720,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1643 Instruction:"OUTSD DX,Xz" Encoding:"rep 0x6F"/"" + // Pos:1645 Instruction:"OUTSD DX,Xz" Encoding:"rep 0x6F"/"" { .Instruction = ND_INS_OUTS, .Category = ND_CAT_IOSTRINGOP, .IsaSet = ND_SET_I86, - .Mnemonic = 549, + .Mnemonic = 550, .ValidPrefixes = ND_PREF_REP, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -46035,6 +47734,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM, .ModifiedFlags = 0, .SetFlags = 0, @@ -46051,12 +47751,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1644 Instruction:"OUTSW DX,Xz" Encoding:"ds16 0x6F"/"" + // Pos:1646 Instruction:"OUTSW DX,Xz" Encoding:"ds16 0x6F"/"" { .Instruction = ND_INS_OUTS, .Category = ND_CAT_IOSTRINGOP, .IsaSet = ND_SET_I86, - .Mnemonic = 550, + .Mnemonic = 551, .ValidPrefixes = ND_PREF_REP, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -46065,6 +47765,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM, .ModifiedFlags = 0, .SetFlags = 0, @@ -46080,12 +47781,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1645 Instruction:"OUTSW DX,Xz" Encoding:"rep ds16 0x6F"/"" + // Pos:1647 Instruction:"OUTSW DX,Xz" Encoding:"rep ds16 0x6F"/"" { .Instruction = ND_INS_OUTS, .Category = ND_CAT_IOSTRINGOP, .IsaSet = ND_SET_I86, - .Mnemonic = 550, + .Mnemonic = 551, .ValidPrefixes = ND_PREF_REP, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -46094,6 +47795,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM, .ModifiedFlags = 0, .SetFlags = 0, @@ -46110,12 +47812,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1646 Instruction:"PABSB Pq,Qq" Encoding:"NP 0x0F 0x38 0x1C /r"/"RM" + // Pos:1648 Instruction:"PABSB Pq,Qq" Encoding:"NP 0x0F 0x38 0x1C /r"/"RM" { .Instruction = ND_INS_PABSB, .Category = ND_CAT_MMX, .IsaSet = ND_SET_SSSE3, - .Mnemonic = 551, + .Mnemonic = 552, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -46124,6 +47826,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -46137,12 +47840,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1647 Instruction:"PABSB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x1C /r"/"RM" + // Pos:1649 Instruction:"PABSB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x1C /r"/"RM" { .Instruction = ND_INS_PABSB, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSSE3, - .Mnemonic = 551, + .Mnemonic = 552, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -46151,6 +47854,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -46164,12 +47868,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1648 Instruction:"PABSD Pq,Qq" Encoding:"NP 0x0F 0x38 0x1E /r"/"RM" + // Pos:1650 Instruction:"PABSD Pq,Qq" Encoding:"NP 0x0F 0x38 0x1E /r"/"RM" { .Instruction = ND_INS_PABSD, .Category = ND_CAT_MMX, .IsaSet = ND_SET_SSSE3, - .Mnemonic = 552, + .Mnemonic = 553, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -46178,6 +47882,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -46191,12 +47896,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1649 Instruction:"PABSD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x1E /r"/"RM" + // Pos:1651 Instruction:"PABSD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x1E /r"/"RM" { .Instruction = ND_INS_PABSD, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSSE3, - .Mnemonic = 552, + .Mnemonic = 553, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -46205,6 +47910,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -46218,12 +47924,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1650 Instruction:"PABSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x1D /r"/"RM" + // Pos:1652 Instruction:"PABSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x1D /r"/"RM" { .Instruction = ND_INS_PABSW, .Category = ND_CAT_MMX, .IsaSet = ND_SET_SSSE3, - .Mnemonic = 553, + .Mnemonic = 554, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -46232,6 +47938,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -46245,12 +47952,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1651 Instruction:"PABSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x1D /r"/"RM" + // Pos:1653 Instruction:"PABSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x1D /r"/"RM" { .Instruction = ND_INS_PABSW, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSSE3, - .Mnemonic = 553, + .Mnemonic = 554, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -46259,6 +47966,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -46272,12 +47980,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1652 Instruction:"PACKSSDW Pq,Qq" Encoding:"NP 0x0F 0x6B /r"/"RM" + // Pos:1654 Instruction:"PACKSSDW Pq,Qq" Encoding:"NP 0x0F 0x6B /r"/"RM" { .Instruction = ND_INS_PACKSSDW, .Category = ND_CAT_MMX, .IsaSet = ND_SET_MMX, - .Mnemonic = 554, + .Mnemonic = 555, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -46286,6 +47994,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -46299,12 +48008,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1653 Instruction:"PACKSSDW Vx,Wx" Encoding:"0x66 0x0F 0x6B /r"/"RM" + // Pos:1655 Instruction:"PACKSSDW Vx,Wx" Encoding:"0x66 0x0F 0x6B /r"/"RM" { .Instruction = ND_INS_PACKSSDW, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE2, - .Mnemonic = 554, + .Mnemonic = 555, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -46313,6 +48022,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -46326,12 +48036,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1654 Instruction:"PACKSSWB Pq,Qq" Encoding:"NP 0x0F 0x63 /r"/"RM" + // Pos:1656 Instruction:"PACKSSWB Pq,Qq" Encoding:"NP 0x0F 0x63 /r"/"RM" { .Instruction = ND_INS_PACKSSWB, .Category = ND_CAT_MMX, .IsaSet = ND_SET_MMX, - .Mnemonic = 555, + .Mnemonic = 556, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -46340,6 +48050,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -46353,12 +48064,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1655 Instruction:"PACKSSWB Vx,Wx" Encoding:"0x66 0x0F 0x63 /r"/"RM" + // Pos:1657 Instruction:"PACKSSWB Vx,Wx" Encoding:"0x66 0x0F 0x63 /r"/"RM" { .Instruction = ND_INS_PACKSSWB, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE2, - .Mnemonic = 555, + .Mnemonic = 556, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -46367,6 +48078,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -46380,12 +48092,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1656 Instruction:"PACKUSDW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x2B /r"/"RM" + // Pos:1658 Instruction:"PACKUSDW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x2B /r"/"RM" { .Instruction = ND_INS_PACKUSDW, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE4, - .Mnemonic = 556, + .Mnemonic = 557, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -46394,6 +48106,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -46407,12 +48120,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1657 Instruction:"PACKUSWB Pq,Qq" Encoding:"NP 0x0F 0x67 /r"/"RM" + // Pos:1659 Instruction:"PACKUSWB Pq,Qq" Encoding:"NP 0x0F 0x67 /r"/"RM" { .Instruction = ND_INS_PACKUSWB, .Category = ND_CAT_MMX, .IsaSet = ND_SET_MMX, - .Mnemonic = 557, + .Mnemonic = 558, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -46421,6 +48134,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -46434,12 +48148,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1658 Instruction:"PACKUSWB Vx,Wx" Encoding:"0x66 0x0F 0x67 /r"/"RM" + // Pos:1660 Instruction:"PACKUSWB Vx,Wx" Encoding:"0x66 0x0F 0x67 /r"/"RM" { .Instruction = ND_INS_PACKUSWB, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE2, - .Mnemonic = 557, + .Mnemonic = 558, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -46448,6 +48162,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -46461,12 +48176,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1659 Instruction:"PADDB Pq,Qq" Encoding:"NP 0x0F 0xFC /r"/"RM" + // Pos:1661 Instruction:"PADDB Pq,Qq" Encoding:"NP 0x0F 0xFC /r"/"RM" { .Instruction = ND_INS_PADDB, .Category = ND_CAT_MMX, .IsaSet = ND_SET_MMX, - .Mnemonic = 558, + .Mnemonic = 559, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -46475,6 +48190,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -46488,12 +48204,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1660 Instruction:"PADDB Vx,Wx" Encoding:"0x66 0x0F 0xFC /r"/"RM" + // Pos:1662 Instruction:"PADDB Vx,Wx" Encoding:"0x66 0x0F 0xFC /r"/"RM" { .Instruction = ND_INS_PADDB, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE2, - .Mnemonic = 558, + .Mnemonic = 559, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -46502,6 +48218,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -46515,12 +48232,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1661 Instruction:"PADDD Pq,Qq" Encoding:"NP 0x0F 0xFE /r"/"RM" + // Pos:1663 Instruction:"PADDD Pq,Qq" Encoding:"NP 0x0F 0xFE /r"/"RM" { .Instruction = ND_INS_PADDD, .Category = ND_CAT_MMX, .IsaSet = ND_SET_MMX, - .Mnemonic = 559, + .Mnemonic = 560, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -46529,6 +48246,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -46542,12 +48260,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1662 Instruction:"PADDD Vx,Wx" Encoding:"0x66 0x0F 0xFE /r"/"RM" + // Pos:1664 Instruction:"PADDD Vx,Wx" Encoding:"0x66 0x0F 0xFE /r"/"RM" { .Instruction = ND_INS_PADDD, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE2, - .Mnemonic = 559, + .Mnemonic = 560, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -46556,6 +48274,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -46569,12 +48288,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1663 Instruction:"PADDQ Pq,Qq" Encoding:"NP 0x0F 0xD4 /r"/"RM" + // Pos:1665 Instruction:"PADDQ Pq,Qq" Encoding:"NP 0x0F 0xD4 /r"/"RM" { .Instruction = ND_INS_PADDQ, .Category = ND_CAT_MMX, .IsaSet = ND_SET_SSE2, - .Mnemonic = 560, + .Mnemonic = 561, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -46583,6 +48302,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -46596,12 +48316,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1664 Instruction:"PADDQ Vx,Wx" Encoding:"0x66 0x0F 0xD4 /r"/"RM" + // Pos:1666 Instruction:"PADDQ Vx,Wx" Encoding:"0x66 0x0F 0xD4 /r"/"RM" { .Instruction = ND_INS_PADDQ, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE2, - .Mnemonic = 560, + .Mnemonic = 561, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -46610,6 +48330,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -46623,12 +48344,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1665 Instruction:"PADDSB Pq,Qq" Encoding:"NP 0x0F 0xEC /r"/"RM" + // Pos:1667 Instruction:"PADDSB Pq,Qq" Encoding:"NP 0x0F 0xEC /r"/"RM" { .Instruction = ND_INS_PADDSB, .Category = ND_CAT_MMX, .IsaSet = ND_SET_MMX, - .Mnemonic = 561, + .Mnemonic = 562, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -46637,6 +48358,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -46650,12 +48372,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1666 Instruction:"PADDSB Vx,Wx" Encoding:"0x66 0x0F 0xEC /r"/"RM" + // Pos:1668 Instruction:"PADDSB Vx,Wx" Encoding:"0x66 0x0F 0xEC /r"/"RM" { .Instruction = ND_INS_PADDSB, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE2, - .Mnemonic = 561, + .Mnemonic = 562, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -46664,6 +48386,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -46677,12 +48400,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1667 Instruction:"PADDSW Pq,Qq" Encoding:"NP 0x0F 0xED /r"/"RM" + // Pos:1669 Instruction:"PADDSW Pq,Qq" Encoding:"NP 0x0F 0xED /r"/"RM" { .Instruction = ND_INS_PADDSW, .Category = ND_CAT_MMX, .IsaSet = ND_SET_MMX, - .Mnemonic = 562, + .Mnemonic = 563, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -46691,6 +48414,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -46704,12 +48428,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1668 Instruction:"PADDSW Vx,Wx" Encoding:"0x66 0x0F 0xED /r"/"RM" + // Pos:1670 Instruction:"PADDSW Vx,Wx" Encoding:"0x66 0x0F 0xED /r"/"RM" { .Instruction = ND_INS_PADDSW, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE2, - .Mnemonic = 562, + .Mnemonic = 563, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -46718,6 +48442,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -46731,12 +48456,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1669 Instruction:"PADDUSB Pq,Qq" Encoding:"NP 0x0F 0xDC /r"/"RM" + // Pos:1671 Instruction:"PADDUSB Pq,Qq" Encoding:"NP 0x0F 0xDC /r"/"RM" { .Instruction = ND_INS_PADDUSB, .Category = ND_CAT_MMX, .IsaSet = ND_SET_MMX, - .Mnemonic = 563, + .Mnemonic = 564, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -46745,6 +48470,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -46758,12 +48484,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1670 Instruction:"PADDUSB Vx,Wx" Encoding:"0x66 0x0F 0xDC /r"/"RM" + // Pos:1672 Instruction:"PADDUSB Vx,Wx" Encoding:"0x66 0x0F 0xDC /r"/"RM" { .Instruction = ND_INS_PADDUSB, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE2, - .Mnemonic = 563, + .Mnemonic = 564, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -46772,6 +48498,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -46785,12 +48512,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1671 Instruction:"PADDUSW Pq,Qq" Encoding:"NP 0x0F 0xDD /r"/"RM" + // Pos:1673 Instruction:"PADDUSW Pq,Qq" Encoding:"NP 0x0F 0xDD /r"/"RM" { .Instruction = ND_INS_PADDUSW, .Category = ND_CAT_MMX, .IsaSet = ND_SET_MMX, - .Mnemonic = 564, + .Mnemonic = 565, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -46799,6 +48526,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -46812,12 +48540,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1672 Instruction:"PADDUSW Vx,Wx" Encoding:"0x66 0x0F 0xDD /r"/"RM" + // Pos:1674 Instruction:"PADDUSW Vx,Wx" Encoding:"0x66 0x0F 0xDD /r"/"RM" { .Instruction = ND_INS_PADDUSW, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE2, - .Mnemonic = 564, + .Mnemonic = 565, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -46826,6 +48554,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -46839,12 +48568,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1673 Instruction:"PADDW Pq,Qq" Encoding:"NP 0x0F 0xFD /r"/"RM" + // Pos:1675 Instruction:"PADDW Pq,Qq" Encoding:"NP 0x0F 0xFD /r"/"RM" { .Instruction = ND_INS_PADDW, .Category = ND_CAT_MMX, .IsaSet = ND_SET_MMX, - .Mnemonic = 565, + .Mnemonic = 566, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -46853,6 +48582,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -46866,12 +48596,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1674 Instruction:"PADDW Vx,Wx" Encoding:"0x66 0x0F 0xFD /r"/"RM" + // Pos:1676 Instruction:"PADDW Vx,Wx" Encoding:"0x66 0x0F 0xFD /r"/"RM" { .Instruction = ND_INS_PADDW, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE2, - .Mnemonic = 565, + .Mnemonic = 566, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -46880,6 +48610,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -46893,12 +48624,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1675 Instruction:"PALIGNR Pq,Qq,Ib" Encoding:"NP 0x0F 0x3A 0x0F /r ib"/"RMI" + // Pos:1677 Instruction:"PALIGNR Pq,Qq,Ib" Encoding:"NP 0x0F 0x3A 0x0F /r ib"/"RMI" { .Instruction = ND_INS_PALIGNR, .Category = ND_CAT_MMX, .IsaSet = ND_SET_SSSE3, - .Mnemonic = 566, + .Mnemonic = 567, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -46907,6 +48638,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -46921,12 +48653,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1676 Instruction:"PALIGNR Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x0F /r ib"/"RMI" + // Pos:1678 Instruction:"PALIGNR Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x0F /r ib"/"RMI" { .Instruction = ND_INS_PALIGNR, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSSE3, - .Mnemonic = 566, + .Mnemonic = 567, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -46935,6 +48667,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -46949,12 +48682,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1677 Instruction:"PAND Pq,Qq" Encoding:"NP 0x0F 0xDB /r"/"RM" + // Pos:1679 Instruction:"PAND Pq,Qq" Encoding:"NP 0x0F 0xDB /r"/"RM" { .Instruction = ND_INS_PAND, .Category = ND_CAT_LOGICAL, .IsaSet = ND_SET_MMX, - .Mnemonic = 567, + .Mnemonic = 568, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -46963,6 +48696,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -46976,12 +48710,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1678 Instruction:"PAND Vx,Wx" Encoding:"0x66 0x0F 0xDB /r"/"RM" + // Pos:1680 Instruction:"PAND Vx,Wx" Encoding:"0x66 0x0F 0xDB /r"/"RM" { .Instruction = ND_INS_PAND, .Category = ND_CAT_LOGICAL, .IsaSet = ND_SET_SSE2, - .Mnemonic = 567, + .Mnemonic = 568, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -46990,6 +48724,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -47003,12 +48738,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1679 Instruction:"PANDN Pq,Qq" Encoding:"NP 0x0F 0xDF /r"/"RM" + // Pos:1681 Instruction:"PANDN Pq,Qq" Encoding:"NP 0x0F 0xDF /r"/"RM" { .Instruction = ND_INS_PANDN, .Category = ND_CAT_LOGICAL, .IsaSet = ND_SET_MMX, - .Mnemonic = 568, + .Mnemonic = 569, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -47017,6 +48752,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -47030,12 +48766,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1680 Instruction:"PANDN Vx,Wx" Encoding:"0x66 0x0F 0xDF /r"/"RM" + // Pos:1682 Instruction:"PANDN Vx,Wx" Encoding:"0x66 0x0F 0xDF /r"/"RM" { .Instruction = ND_INS_PANDN, .Category = ND_CAT_LOGICAL, .IsaSet = ND_SET_SSE2, - .Mnemonic = 568, + .Mnemonic = 569, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -47044,6 +48780,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -47057,12 +48794,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1681 Instruction:"PAUSE" Encoding:"repz 0x90"/"" + // Pos:1683 Instruction:"PAUSE" Encoding:"repz 0x90"/"" { .Instruction = ND_INS_PAUSE, .Category = ND_CAT_MISC, .IsaSet = ND_SET_PAUSE, - .Mnemonic = 569, + .Mnemonic = 570, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -47071,6 +48808,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -47083,12 +48821,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1682 Instruction:"PAVGB Pq,Qq" Encoding:"NP 0x0F 0xE0 /r"/"RM" + // Pos:1684 Instruction:"PAVGB Pq,Qq" Encoding:"NP 0x0F 0xE0 /r"/"RM" { .Instruction = ND_INS_PAVGB, .Category = ND_CAT_MMX, .IsaSet = ND_SET_MMX, - .Mnemonic = 570, + .Mnemonic = 571, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -47097,6 +48835,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -47110,12 +48849,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1683 Instruction:"PAVGB Vx,Wx" Encoding:"0x66 0x0F 0xE0 /r"/"RM" + // Pos:1685 Instruction:"PAVGB Vx,Wx" Encoding:"0x66 0x0F 0xE0 /r"/"RM" { .Instruction = ND_INS_PAVGB, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE2, - .Mnemonic = 570, + .Mnemonic = 571, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -47124,6 +48863,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -47137,12 +48877,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1684 Instruction:"PAVGUSB Pq,Qq" Encoding:"0x0F 0x0F /r 0xBF"/"RM" + // Pos:1686 Instruction:"PAVGUSB Pq,Qq" Encoding:"0x0F 0x0F /r 0xBF"/"RM" { .Instruction = ND_INS_PAVGUSB, .Category = ND_CAT_3DNOW, .IsaSet = ND_SET_3DNOW, - .Mnemonic = 571, + .Mnemonic = 572, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -47151,6 +48891,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -47164,12 +48905,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1685 Instruction:"PAVGW Pq,Qq" Encoding:"NP 0x0F 0xE3 /r"/"RM" + // Pos:1687 Instruction:"PAVGW Pq,Qq" Encoding:"NP 0x0F 0xE3 /r"/"RM" { .Instruction = ND_INS_PAVGW, .Category = ND_CAT_MMX, .IsaSet = ND_SET_MMX, - .Mnemonic = 572, + .Mnemonic = 573, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -47178,6 +48919,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -47191,12 +48933,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1686 Instruction:"PAVGW Vx,Wx" Encoding:"0x66 0x0F 0xE3 /r"/"RM" + // Pos:1688 Instruction:"PAVGW Vx,Wx" Encoding:"0x66 0x0F 0xE3 /r"/"RM" { .Instruction = ND_INS_PAVGW, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE2, - .Mnemonic = 572, + .Mnemonic = 573, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -47205,6 +48947,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -47218,12 +48961,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1687 Instruction:"PBLENDVB Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x10 /r"/"RM" + // Pos:1689 Instruction:"PBLENDVB Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x10 /r"/"RM" { .Instruction = ND_INS_PBLENDVB, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE4, - .Mnemonic = 573, + .Mnemonic = 574, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -47232,6 +48975,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -47246,12 +48990,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1688 Instruction:"PBLENDW Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x0E /r ib"/"RMI" + // Pos:1690 Instruction:"PBLENDW Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x0E /r ib"/"RMI" { .Instruction = ND_INS_PBLENDW, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE4, - .Mnemonic = 574, + .Mnemonic = 575, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -47260,6 +49004,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -47274,12 +49019,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1689 Instruction:"PBNDKB" Encoding:"NP 0x0F 0x01 /0xC7"/"" + // Pos:1691 Instruction:"PBNDKB" Encoding:"NP 0x0F 0x01 /0xC7"/"" { .Instruction = ND_INS_PBNDKB, .Category = ND_CAT_SYSTEM, .IsaSet = ND_SET_TSE, - .Mnemonic = 575, + .Mnemonic = 576, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -47288,6 +49033,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_ZF, .SetFlags = 0, @@ -47303,12 +49049,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1690 Instruction:"PCLMULQDQ Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x44 /r ib"/"RMI" + // Pos:1692 Instruction:"PCLMULQDQ Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x44 /r ib"/"RMI" { .Instruction = ND_INS_PCLMULQDQ, .Category = ND_CAT_PCLMULQDQ, .IsaSet = ND_SET_PCLMULQDQ, - .Mnemonic = 576, + .Mnemonic = 577, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -47317,6 +49063,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -47331,12 +49078,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1691 Instruction:"PCMPEQB Pq,Qq" Encoding:"NP 0x0F 0x74 /r"/"RM" + // Pos:1693 Instruction:"PCMPEQB Pq,Qq" Encoding:"NP 0x0F 0x74 /r"/"RM" { .Instruction = ND_INS_PCMPEQB, .Category = ND_CAT_MMX, .IsaSet = ND_SET_MMX, - .Mnemonic = 577, + .Mnemonic = 578, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -47345,6 +49092,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -47358,12 +49106,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1692 Instruction:"PCMPEQB Vx,Wx" Encoding:"0x66 0x0F 0x74 /r"/"RM" + // Pos:1694 Instruction:"PCMPEQB Vx,Wx" Encoding:"0x66 0x0F 0x74 /r"/"RM" { .Instruction = ND_INS_PCMPEQB, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE2, - .Mnemonic = 577, + .Mnemonic = 578, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -47372,6 +49120,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -47385,12 +49134,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1693 Instruction:"PCMPEQD Pq,Qq" Encoding:"NP 0x0F 0x76 /r"/"RM" + // Pos:1695 Instruction:"PCMPEQD Pq,Qq" Encoding:"NP 0x0F 0x76 /r"/"RM" { .Instruction = ND_INS_PCMPEQD, .Category = ND_CAT_MMX, .IsaSet = ND_SET_MMX, - .Mnemonic = 578, + .Mnemonic = 579, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -47399,6 +49148,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -47412,12 +49162,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1694 Instruction:"PCMPEQD Vx,Wx" Encoding:"0x66 0x0F 0x76 /r"/"RM" + // Pos:1696 Instruction:"PCMPEQD Vx,Wx" Encoding:"0x66 0x0F 0x76 /r"/"RM" { .Instruction = ND_INS_PCMPEQD, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE2, - .Mnemonic = 578, + .Mnemonic = 579, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -47426,6 +49176,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -47439,12 +49190,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1695 Instruction:"PCMPEQQ Vx,Wx" Encoding:"0x66 0x0F 0x38 0x29 /r"/"RM" + // Pos:1697 Instruction:"PCMPEQQ Vx,Wx" Encoding:"0x66 0x0F 0x38 0x29 /r"/"RM" { .Instruction = ND_INS_PCMPEQQ, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE4, - .Mnemonic = 579, + .Mnemonic = 580, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -47453,6 +49204,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -47466,12 +49218,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1696 Instruction:"PCMPEQW Pq,Qq" Encoding:"NP 0x0F 0x75 /r"/"RM" + // Pos:1698 Instruction:"PCMPEQW Pq,Qq" Encoding:"NP 0x0F 0x75 /r"/"RM" { .Instruction = ND_INS_PCMPEQW, .Category = ND_CAT_MMX, .IsaSet = ND_SET_MMX, - .Mnemonic = 580, + .Mnemonic = 581, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -47480,6 +49232,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -47493,12 +49246,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1697 Instruction:"PCMPEQW Vx,Wx" Encoding:"0x66 0x0F 0x75 /r"/"RM" + // Pos:1699 Instruction:"PCMPEQW Vx,Wx" Encoding:"0x66 0x0F 0x75 /r"/"RM" { .Instruction = ND_INS_PCMPEQW, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE2, - .Mnemonic = 580, + .Mnemonic = 581, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -47507,6 +49260,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -47520,12 +49274,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1698 Instruction:"PCMPESTRI Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x61 /r ib"/"RMI" + // Pos:1700 Instruction:"PCMPESTRI Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x61 /r ib"/"RMI" { .Instruction = ND_INS_PCMPESTRI, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE42, - .Mnemonic = 581, + .Mnemonic = 582, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -47534,6 +49288,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -47552,12 +49307,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1699 Instruction:"PCMPESTRM Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x60 /r ib"/"RMI" + // Pos:1701 Instruction:"PCMPESTRM Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x60 /r ib"/"RMI" { .Instruction = ND_INS_PCMPESTRM, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE42, - .Mnemonic = 582, + .Mnemonic = 583, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -47566,6 +49321,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -47584,12 +49340,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1700 Instruction:"PCMPGTB Pq,Qq" Encoding:"NP 0x0F 0x64 /r"/"RM" + // Pos:1702 Instruction:"PCMPGTB Pq,Qq" Encoding:"NP 0x0F 0x64 /r"/"RM" { .Instruction = ND_INS_PCMPGTB, .Category = ND_CAT_MMX, .IsaSet = ND_SET_MMX, - .Mnemonic = 583, + .Mnemonic = 584, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -47598,6 +49354,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -47611,12 +49368,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1701 Instruction:"PCMPGTB Vx,Wx" Encoding:"0x66 0x0F 0x64 /r"/"RM" + // Pos:1703 Instruction:"PCMPGTB Vx,Wx" Encoding:"0x66 0x0F 0x64 /r"/"RM" { .Instruction = ND_INS_PCMPGTB, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE2, - .Mnemonic = 583, + .Mnemonic = 584, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -47625,6 +49382,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -47638,12 +49396,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1702 Instruction:"PCMPGTD Pq,Qq" Encoding:"NP 0x0F 0x66 /r"/"RM" + // Pos:1704 Instruction:"PCMPGTD Pq,Qq" Encoding:"NP 0x0F 0x66 /r"/"RM" { .Instruction = ND_INS_PCMPGTD, .Category = ND_CAT_MMX, .IsaSet = ND_SET_MMX, - .Mnemonic = 584, + .Mnemonic = 585, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -47652,6 +49410,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -47665,12 +49424,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1703 Instruction:"PCMPGTD Vx,Wx" Encoding:"0x66 0x0F 0x66 /r"/"RM" + // Pos:1705 Instruction:"PCMPGTD Vx,Wx" Encoding:"0x66 0x0F 0x66 /r"/"RM" { .Instruction = ND_INS_PCMPGTD, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE2, - .Mnemonic = 584, + .Mnemonic = 585, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -47679,6 +49438,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -47692,12 +49452,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1704 Instruction:"PCMPGTQ Vx,Wx" Encoding:"0x66 0x0F 0x38 0x37 /r"/"RM" + // Pos:1706 Instruction:"PCMPGTQ Vx,Wx" Encoding:"0x66 0x0F 0x38 0x37 /r"/"RM" { .Instruction = ND_INS_PCMPGTQ, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE42, - .Mnemonic = 585, + .Mnemonic = 586, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -47706,6 +49466,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -47719,12 +49480,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1705 Instruction:"PCMPGTW Pq,Qq" Encoding:"NP 0x0F 0x65 /r"/"RM" + // Pos:1707 Instruction:"PCMPGTW Pq,Qq" Encoding:"NP 0x0F 0x65 /r"/"RM" { .Instruction = ND_INS_PCMPGTW, .Category = ND_CAT_MMX, .IsaSet = ND_SET_MMX, - .Mnemonic = 586, + .Mnemonic = 587, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -47733,6 +49494,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -47746,12 +49508,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1706 Instruction:"PCMPGTW Vx,Wx" Encoding:"0x66 0x0F 0x65 /r"/"RM" + // Pos:1708 Instruction:"PCMPGTW Vx,Wx" Encoding:"0x66 0x0F 0x65 /r"/"RM" { .Instruction = ND_INS_PCMPGTW, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE2, - .Mnemonic = 586, + .Mnemonic = 587, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -47760,6 +49522,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -47773,12 +49536,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1707 Instruction:"PCMPISTRI Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x63 /r ib"/"RMI" + // Pos:1709 Instruction:"PCMPISTRI Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x63 /r ib"/"RMI" { .Instruction = ND_INS_PCMPISTRI, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE42, - .Mnemonic = 587, + .Mnemonic = 588, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -47787,6 +49550,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -47803,12 +49567,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1708 Instruction:"PCMPISTRM Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x62 /r ib"/"RMI" + // Pos:1710 Instruction:"PCMPISTRM Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x62 /r ib"/"RMI" { .Instruction = ND_INS_PCMPISTRM, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE42, - .Mnemonic = 588, + .Mnemonic = 589, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -47817,6 +49581,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -47833,12 +49598,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1709 Instruction:"PCONFIG" Encoding:"NP 0x0F 0x01 /0xC5"/"" + // Pos:1711 Instruction:"PCONFIG" Encoding:"NP 0x0F 0x01 /0xC5"/"" { .Instruction = ND_INS_PCONFIG, .Category = ND_CAT_PCONFIG, .IsaSet = ND_SET_PCONFIG, - .Mnemonic = 589, + .Mnemonic = 590, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -47847,6 +49612,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_ZF, .SetFlags = 0, @@ -47863,12 +49629,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1710 Instruction:"PDEP Gy,By,Ey" Encoding:"evex m:2 p:3 l:0 nf:0 0xF5 /r"/"RVM" + // Pos:1712 Instruction:"PDEP Gy,By,Ey" Encoding:"evex m:2 p:3 l:0 nf:0 0xF5 /r"/"RVM" { .Instruction = ND_INS_PDEP, .Category = ND_CAT_BMI2, .IsaSet = ND_SET_APX_F, - .Mnemonic = 590, + .Mnemonic = 591, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -47877,6 +49643,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_BMI, .FpuFlags = 0, .EvexMode = ND_EVEXM_VEX, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -47891,12 +49658,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1711 Instruction:"PDEP Gy,By,Ey" Encoding:"vex m:2 p:3 l:0 w:x 0xF5 /r"/"RVM" + // Pos:1713 Instruction:"PDEP Gy,By,Ey" Encoding:"vex m:2 p:3 l:0 w:x 0xF5 /r"/"RVM" { .Instruction = ND_INS_PDEP, .Category = ND_CAT_BMI2, .IsaSet = ND_SET_BMI2, - .Mnemonic = 590, + .Mnemonic = 591, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -47905,6 +49672,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_13, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -47919,12 +49687,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1712 Instruction:"PEXT Gy,By,Ey" Encoding:"evex m:2 p:2 l:0 nf:0 0xF5 /r"/"RVM" + // Pos:1714 Instruction:"PEXT Gy,By,Ey" Encoding:"evex m:2 p:2 l:0 nf:0 0xF5 /r"/"RVM" { .Instruction = ND_INS_PEXT, .Category = ND_CAT_BMI2, .IsaSet = ND_SET_APX_F, - .Mnemonic = 591, + .Mnemonic = 592, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -47933,6 +49701,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_BMI, .FpuFlags = 0, .EvexMode = ND_EVEXM_VEX, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -47947,12 +49716,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1713 Instruction:"PEXT Gy,By,Ey" Encoding:"vex m:2 p:2 l:0 w:x 0xF5 /r"/"RVM" + // Pos:1715 Instruction:"PEXT Gy,By,Ey" Encoding:"vex m:2 p:2 l:0 w:x 0xF5 /r"/"RVM" { .Instruction = ND_INS_PEXT, .Category = ND_CAT_BMI2, .IsaSet = ND_SET_BMI2, - .Mnemonic = 591, + .Mnemonic = 592, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -47961,6 +49730,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_13, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -47975,12 +49745,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1714 Instruction:"PEXTRB Mb,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x14 /r:mem ib"/"MRI" + // Pos:1716 Instruction:"PEXTRB Mb,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x14 /r:mem ib"/"MRI" { .Instruction = ND_INS_PEXTRB, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE4, - .Mnemonic = 592, + .Mnemonic = 593, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -47989,6 +49759,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -48003,12 +49774,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1715 Instruction:"PEXTRB Ry,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x14 /r:reg ib"/"MRI" + // Pos:1717 Instruction:"PEXTRB Ry,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x14 /r:reg ib"/"MRI" { .Instruction = ND_INS_PEXTRB, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE4, - .Mnemonic = 592, + .Mnemonic = 593, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -48017,6 +49788,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -48031,12 +49803,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1716 Instruction:"PEXTRD Md,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x16 /r:mem ib"/"MRI" + // Pos:1718 Instruction:"PEXTRD Md,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x16 /r:mem ib"/"MRI" { .Instruction = ND_INS_PEXTRD, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE4, - .Mnemonic = 593, + .Mnemonic = 594, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -48045,6 +49817,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -48059,12 +49832,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1717 Instruction:"PEXTRD Ry,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x16 /r:reg ib"/"MRI" + // Pos:1719 Instruction:"PEXTRD Ry,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x16 /r:reg ib"/"MRI" { .Instruction = ND_INS_PEXTRD, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE4, - .Mnemonic = 593, + .Mnemonic = 594, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -48073,6 +49846,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -48087,12 +49861,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1718 Instruction:"PEXTRQ Mq,Vdq,Ib" Encoding:"rexw 0x66 0x0F 0x3A 0x16 /r:mem ib"/"MRI" + // Pos:1720 Instruction:"PEXTRQ Mq,Vdq,Ib" Encoding:"rexw 0x66 0x0F 0x3A 0x16 /r:mem ib"/"MRI" { .Instruction = ND_INS_PEXTRQ, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE4, - .Mnemonic = 594, + .Mnemonic = 595, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -48101,6 +49875,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -48115,12 +49890,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1719 Instruction:"PEXTRQ Ry,Vdq,Ib" Encoding:"rexw 0x66 0x0F 0x3A 0x16 /r:reg ib"/"MRI" + // Pos:1721 Instruction:"PEXTRQ Ry,Vdq,Ib" Encoding:"rexw 0x66 0x0F 0x3A 0x16 /r:reg ib"/"MRI" { .Instruction = ND_INS_PEXTRQ, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE4, - .Mnemonic = 594, + .Mnemonic = 595, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -48129,6 +49904,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -48143,12 +49919,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1720 Instruction:"PEXTRW Gy,Nq,Ib" Encoding:"NP 0x0F 0xC5 /r:reg ib"/"RMI" + // Pos:1722 Instruction:"PEXTRW Gy,Nq,Ib" Encoding:"NP 0x0F 0xC5 /r:reg ib"/"RMI" { .Instruction = ND_INS_PEXTRW, .Category = ND_CAT_MMX, .IsaSet = ND_SET_MMX, - .Mnemonic = 595, + .Mnemonic = 596, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -48157,6 +49933,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -48171,12 +49948,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1721 Instruction:"PEXTRW Gy,Udq,Ib" Encoding:"0x66 0x0F 0xC5 /r:reg ib"/"RMI" + // Pos:1723 Instruction:"PEXTRW Gy,Udq,Ib" Encoding:"0x66 0x0F 0xC5 /r:reg ib"/"RMI" { .Instruction = ND_INS_PEXTRW, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE2, - .Mnemonic = 595, + .Mnemonic = 596, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -48185,6 +49962,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -48199,12 +49977,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1722 Instruction:"PEXTRW Mw,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x15 /r:mem ib"/"MRI" + // Pos:1724 Instruction:"PEXTRW Mw,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x15 /r:mem ib"/"MRI" { .Instruction = ND_INS_PEXTRW, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE4, - .Mnemonic = 595, + .Mnemonic = 596, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -48213,6 +49991,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -48227,12 +50006,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1723 Instruction:"PEXTRW Ry,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x15 /r:reg ib"/"MRI" + // Pos:1725 Instruction:"PEXTRW Ry,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x15 /r:reg ib"/"MRI" { .Instruction = ND_INS_PEXTRW, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE4, - .Mnemonic = 595, + .Mnemonic = 596, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -48241,6 +50020,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -48255,12 +50035,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1724 Instruction:"PF2ID Pq,Qq" Encoding:"0x0F 0x0F /r 0x1D"/"RM" + // Pos:1726 Instruction:"PF2ID Pq,Qq" Encoding:"0x0F 0x0F /r 0x1D"/"RM" { .Instruction = ND_INS_PF2ID, .Category = ND_CAT_3DNOW, .IsaSet = ND_SET_3DNOW, - .Mnemonic = 596, + .Mnemonic = 597, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -48269,6 +50049,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -48282,12 +50063,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1725 Instruction:"PF2IW Pq,Qq" Encoding:"0x0F 0x0F /r 0x1C"/"RM" + // Pos:1727 Instruction:"PF2IW Pq,Qq" Encoding:"0x0F 0x0F /r 0x1C"/"RM" { .Instruction = ND_INS_PF2IW, .Category = ND_CAT_3DNOW, .IsaSet = ND_SET_3DNOW, - .Mnemonic = 597, + .Mnemonic = 598, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -48296,6 +50077,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -48309,12 +50091,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1726 Instruction:"PFACC Pq,Qq" Encoding:"0x0F 0x0F /r 0xAE"/"RM" + // Pos:1728 Instruction:"PFACC Pq,Qq" Encoding:"0x0F 0x0F /r 0xAE"/"RM" { .Instruction = ND_INS_PFACC, .Category = ND_CAT_3DNOW, .IsaSet = ND_SET_3DNOW, - .Mnemonic = 598, + .Mnemonic = 599, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -48323,6 +50105,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -48336,12 +50119,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1727 Instruction:"PFADD Pq,Qq" Encoding:"0x0F 0x0F /r 0x9E"/"RM" + // Pos:1729 Instruction:"PFADD Pq,Qq" Encoding:"0x0F 0x0F /r 0x9E"/"RM" { .Instruction = ND_INS_PFADD, .Category = ND_CAT_3DNOW, .IsaSet = ND_SET_3DNOW, - .Mnemonic = 599, + .Mnemonic = 600, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -48350,6 +50133,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -48363,12 +50147,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1728 Instruction:"PFCMPEQ Pq,Qq" Encoding:"0x0F 0x0F /r 0xB0"/"RM" + // Pos:1730 Instruction:"PFCMPEQ Pq,Qq" Encoding:"0x0F 0x0F /r 0xB0"/"RM" { .Instruction = ND_INS_PFCMPEQ, .Category = ND_CAT_3DNOW, .IsaSet = ND_SET_3DNOW, - .Mnemonic = 600, + .Mnemonic = 601, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -48377,6 +50161,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -48390,12 +50175,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1729 Instruction:"PFCMPGE Pq,Qq" Encoding:"0x0F 0x0F /r 0x90"/"RM" + // Pos:1731 Instruction:"PFCMPGE Pq,Qq" Encoding:"0x0F 0x0F /r 0x90"/"RM" { .Instruction = ND_INS_PFCMPGE, .Category = ND_CAT_3DNOW, .IsaSet = ND_SET_3DNOW, - .Mnemonic = 601, + .Mnemonic = 602, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -48404,6 +50189,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -48417,12 +50203,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1730 Instruction:"PFCMPGT Pq,Qq" Encoding:"0x0F 0x0F /r 0xA0"/"RM" + // Pos:1732 Instruction:"PFCMPGT Pq,Qq" Encoding:"0x0F 0x0F /r 0xA0"/"RM" { .Instruction = ND_INS_PFCMPGT, .Category = ND_CAT_3DNOW, .IsaSet = ND_SET_3DNOW, - .Mnemonic = 602, + .Mnemonic = 603, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -48431,6 +50217,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -48444,12 +50231,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1731 Instruction:"PFMAX Pq,Qq" Encoding:"0x0F 0x0F /r 0xA4"/"RM" + // Pos:1733 Instruction:"PFMAX Pq,Qq" Encoding:"0x0F 0x0F /r 0xA4"/"RM" { .Instruction = ND_INS_PFMAX, .Category = ND_CAT_3DNOW, .IsaSet = ND_SET_3DNOW, - .Mnemonic = 603, + .Mnemonic = 604, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -48458,6 +50245,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -48471,12 +50259,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1732 Instruction:"PFMIN Pq,Qq" Encoding:"0x0F 0x0F /r 0x94"/"RM" + // Pos:1734 Instruction:"PFMIN Pq,Qq" Encoding:"0x0F 0x0F /r 0x94"/"RM" { .Instruction = ND_INS_PFMIN, .Category = ND_CAT_3DNOW, .IsaSet = ND_SET_3DNOW, - .Mnemonic = 604, + .Mnemonic = 605, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -48485,6 +50273,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -48498,12 +50287,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1733 Instruction:"PFMUL Pq,Qq" Encoding:"0x0F 0x0F /r 0xB4"/"RM" + // Pos:1735 Instruction:"PFMUL Pq,Qq" Encoding:"0x0F 0x0F /r 0xB4"/"RM" { .Instruction = ND_INS_PFMUL, .Category = ND_CAT_3DNOW, .IsaSet = ND_SET_3DNOW, - .Mnemonic = 605, + .Mnemonic = 606, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -48512,6 +50301,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -48525,12 +50315,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1734 Instruction:"PFNACC Pq,Qq" Encoding:"0x0F 0x0F /r 0x8A"/"RM" + // Pos:1736 Instruction:"PFNACC Pq,Qq" Encoding:"0x0F 0x0F /r 0x8A"/"RM" { .Instruction = ND_INS_PFNACC, .Category = ND_CAT_3DNOW, .IsaSet = ND_SET_3DNOW, - .Mnemonic = 606, + .Mnemonic = 607, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -48539,6 +50329,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -48552,12 +50343,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1735 Instruction:"PFPNACC Pq,Qq" Encoding:"0x0F 0x0F /r 0x8E"/"RM" + // Pos:1737 Instruction:"PFPNACC Pq,Qq" Encoding:"0x0F 0x0F /r 0x8E"/"RM" { .Instruction = ND_INS_PFPNACC, .Category = ND_CAT_3DNOW, .IsaSet = ND_SET_3DNOW, - .Mnemonic = 607, + .Mnemonic = 608, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -48566,6 +50357,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -48579,12 +50371,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1736 Instruction:"PFRCP Pq,Qq" Encoding:"0x0F 0x0F /r 0x96"/"RM" + // Pos:1738 Instruction:"PFRCP Pq,Qq" Encoding:"0x0F 0x0F /r 0x96"/"RM" { .Instruction = ND_INS_PFRCP, .Category = ND_CAT_3DNOW, .IsaSet = ND_SET_3DNOW, - .Mnemonic = 608, + .Mnemonic = 609, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -48593,6 +50385,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -48606,12 +50399,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1737 Instruction:"PFRCPIT1 Pq,Qq" Encoding:"0x0F 0x0F /r 0xA6"/"RM" + // Pos:1739 Instruction:"PFRCPIT1 Pq,Qq" Encoding:"0x0F 0x0F /r 0xA6"/"RM" { .Instruction = ND_INS_PFRCPIT1, .Category = ND_CAT_3DNOW, .IsaSet = ND_SET_3DNOW, - .Mnemonic = 609, + .Mnemonic = 610, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -48620,6 +50413,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -48633,12 +50427,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1738 Instruction:"PFRCPIT2 Pq,Qq" Encoding:"0x0F 0x0F /r 0xB6"/"RM" + // Pos:1740 Instruction:"PFRCPIT2 Pq,Qq" Encoding:"0x0F 0x0F /r 0xB6"/"RM" { .Instruction = ND_INS_PFRCPIT2, .Category = ND_CAT_3DNOW, .IsaSet = ND_SET_3DNOW, - .Mnemonic = 610, + .Mnemonic = 611, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -48647,6 +50441,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -48660,12 +50455,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1739 Instruction:"PFRCPV Pq,Qq" Encoding:"0x0F 0x0F /r 0x86"/"RM" + // Pos:1741 Instruction:"PFRCPV Pq,Qq" Encoding:"0x0F 0x0F /r 0x86"/"RM" { .Instruction = ND_INS_PFRCPV, .Category = ND_CAT_3DNOW, .IsaSet = ND_SET_3DNOW, - .Mnemonic = 611, + .Mnemonic = 612, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -48674,6 +50469,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -48687,12 +50483,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1740 Instruction:"PFRSQIT1 Pq,Qq" Encoding:"0x0F 0x0F /r 0xA7"/"RM" + // Pos:1742 Instruction:"PFRSQIT1 Pq,Qq" Encoding:"0x0F 0x0F /r 0xA7"/"RM" { .Instruction = ND_INS_PFRSQIT1, .Category = ND_CAT_3DNOW, .IsaSet = ND_SET_3DNOW, - .Mnemonic = 612, + .Mnemonic = 613, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -48701,6 +50497,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -48714,12 +50511,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1741 Instruction:"PFRSQRT Pq,Qq" Encoding:"0x0F 0x0F /r 0x97"/"RM" + // Pos:1743 Instruction:"PFRSQRT Pq,Qq" Encoding:"0x0F 0x0F /r 0x97"/"RM" { .Instruction = ND_INS_PFRSQRT, .Category = ND_CAT_3DNOW, .IsaSet = ND_SET_3DNOW, - .Mnemonic = 613, + .Mnemonic = 614, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -48728,6 +50525,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -48741,12 +50539,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1742 Instruction:"PFRSQRTV Pq,Qq" Encoding:"0x0F 0x0F /r 0x87"/"RM" + // Pos:1744 Instruction:"PFRSQRTV Pq,Qq" Encoding:"0x0F 0x0F /r 0x87"/"RM" { .Instruction = ND_INS_PFRSQRTV, .Category = ND_CAT_3DNOW, .IsaSet = ND_SET_3DNOW, - .Mnemonic = 614, + .Mnemonic = 615, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -48755,6 +50553,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -48768,12 +50567,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1743 Instruction:"PFSUB Pq,Qq" Encoding:"0x0F 0x0F /r 0x9A"/"RM" + // Pos:1745 Instruction:"PFSUB Pq,Qq" Encoding:"0x0F 0x0F /r 0x9A"/"RM" { .Instruction = ND_INS_PFSUB, .Category = ND_CAT_3DNOW, .IsaSet = ND_SET_3DNOW, - .Mnemonic = 615, + .Mnemonic = 616, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -48782,6 +50581,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -48795,12 +50595,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1744 Instruction:"PFSUBR Pq,Qq" Encoding:"0x0F 0x0F /r 0xAA"/"RM" + // Pos:1746 Instruction:"PFSUBR Pq,Qq" Encoding:"0x0F 0x0F /r 0xAA"/"RM" { .Instruction = ND_INS_PFSUBR, .Category = ND_CAT_3DNOW, .IsaSet = ND_SET_3DNOW, - .Mnemonic = 616, + .Mnemonic = 617, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -48809,6 +50609,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -48822,12 +50623,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1745 Instruction:"PHADDD Pq,Qq" Encoding:"NP 0x0F 0x38 0x02 /r"/"RM" + // Pos:1747 Instruction:"PHADDD Pq,Qq" Encoding:"NP 0x0F 0x38 0x02 /r"/"RM" { .Instruction = ND_INS_PHADDD, .Category = ND_CAT_MMX, .IsaSet = ND_SET_SSSE3, - .Mnemonic = 617, + .Mnemonic = 618, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -48836,6 +50637,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -48849,12 +50651,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1746 Instruction:"PHADDD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x02 /r"/"RM" + // Pos:1748 Instruction:"PHADDD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x02 /r"/"RM" { .Instruction = ND_INS_PHADDD, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSSE3, - .Mnemonic = 617, + .Mnemonic = 618, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -48863,6 +50665,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -48876,12 +50679,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1747 Instruction:"PHADDSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x03 /r"/"RM" + // Pos:1749 Instruction:"PHADDSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x03 /r"/"RM" { .Instruction = ND_INS_PHADDSW, .Category = ND_CAT_MMX, .IsaSet = ND_SET_SSSE3, - .Mnemonic = 618, + .Mnemonic = 619, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -48890,6 +50693,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -48903,12 +50707,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1748 Instruction:"PHADDSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x03 /r"/"RM" + // Pos:1750 Instruction:"PHADDSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x03 /r"/"RM" { .Instruction = ND_INS_PHADDSW, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSSE3, - .Mnemonic = 618, + .Mnemonic = 619, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -48917,6 +50721,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -48930,12 +50735,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1749 Instruction:"PHADDW Pq,Qq" Encoding:"NP 0x0F 0x38 0x01 /r"/"RM" + // Pos:1751 Instruction:"PHADDW Pq,Qq" Encoding:"NP 0x0F 0x38 0x01 /r"/"RM" { .Instruction = ND_INS_PHADDW, .Category = ND_CAT_MMX, .IsaSet = ND_SET_SSSE3, - .Mnemonic = 619, + .Mnemonic = 620, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -48944,6 +50749,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -48957,12 +50763,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1750 Instruction:"PHADDW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x01 /r"/"RM" + // Pos:1752 Instruction:"PHADDW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x01 /r"/"RM" { .Instruction = ND_INS_PHADDW, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSSE3, - .Mnemonic = 619, + .Mnemonic = 620, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -48971,6 +50777,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -48984,12 +50791,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1751 Instruction:"PHMINPOSUW Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x41 /r"/"RM" + // Pos:1753 Instruction:"PHMINPOSUW Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x41 /r"/"RM" { .Instruction = ND_INS_PHMINPOSUW, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE4, - .Mnemonic = 620, + .Mnemonic = 621, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -48998,6 +50805,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -49011,12 +50819,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1752 Instruction:"PHSUBD Pq,Qq" Encoding:"NP 0x0F 0x38 0x06 /r"/"RM" + // Pos:1754 Instruction:"PHSUBD Pq,Qq" Encoding:"NP 0x0F 0x38 0x06 /r"/"RM" { .Instruction = ND_INS_PHSUBD, .Category = ND_CAT_MMX, .IsaSet = ND_SET_SSSE3, - .Mnemonic = 621, + .Mnemonic = 622, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -49025,6 +50833,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -49038,12 +50847,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1753 Instruction:"PHSUBD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x06 /r"/"RM" + // Pos:1755 Instruction:"PHSUBD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x06 /r"/"RM" { .Instruction = ND_INS_PHSUBD, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSSE3, - .Mnemonic = 621, + .Mnemonic = 622, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -49052,6 +50861,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -49065,12 +50875,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1754 Instruction:"PHSUBSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x07 /r"/"RM" + // Pos:1756 Instruction:"PHSUBSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x07 /r"/"RM" { .Instruction = ND_INS_PHSUBSW, .Category = ND_CAT_MMX, .IsaSet = ND_SET_SSSE3, - .Mnemonic = 622, + .Mnemonic = 623, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -49079,6 +50889,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -49092,12 +50903,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1755 Instruction:"PHSUBSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x07 /r"/"RM" + // Pos:1757 Instruction:"PHSUBSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x07 /r"/"RM" { .Instruction = ND_INS_PHSUBSW, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSSE3, - .Mnemonic = 622, + .Mnemonic = 623, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -49106,6 +50917,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -49119,12 +50931,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1756 Instruction:"PHSUBW Pq,Qq" Encoding:"NP 0x0F 0x38 0x05 /r"/"RM" + // Pos:1758 Instruction:"PHSUBW Pq,Qq" Encoding:"NP 0x0F 0x38 0x05 /r"/"RM" { .Instruction = ND_INS_PHSUBW, .Category = ND_CAT_MMX, .IsaSet = ND_SET_SSSE3, - .Mnemonic = 623, + .Mnemonic = 624, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -49133,6 +50945,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -49146,12 +50959,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1757 Instruction:"PHSUBW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x05 /r"/"RM" + // Pos:1759 Instruction:"PHSUBW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x05 /r"/"RM" { .Instruction = ND_INS_PHSUBW, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSSE3, - .Mnemonic = 623, + .Mnemonic = 624, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -49160,6 +50973,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -49173,12 +50987,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1758 Instruction:"PI2FD Pq,Qq" Encoding:"0x0F 0x0F /r 0x0D"/"RM" + // Pos:1760 Instruction:"PI2FD Pq,Qq" Encoding:"0x0F 0x0F /r 0x0D"/"RM" { .Instruction = ND_INS_PI2FD, .Category = ND_CAT_3DNOW, .IsaSet = ND_SET_3DNOW, - .Mnemonic = 624, + .Mnemonic = 625, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -49187,6 +51001,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -49200,12 +51015,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1759 Instruction:"PI2FW Pq,Qq" Encoding:"0x0F 0x0F /r 0x0C"/"RM" + // Pos:1761 Instruction:"PI2FW Pq,Qq" Encoding:"0x0F 0x0F /r 0x0C"/"RM" { .Instruction = ND_INS_PI2FW, .Category = ND_CAT_3DNOW, .IsaSet = ND_SET_3DNOW, - .Mnemonic = 625, + .Mnemonic = 626, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -49214,6 +51029,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -49227,12 +51043,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1760 Instruction:"PINSRB Vdq,Mb,Ib" Encoding:"0x66 0x0F 0x3A 0x20 /r:mem ib"/"RMI" + // Pos:1762 Instruction:"PINSRB Vdq,Mb,Ib" Encoding:"0x66 0x0F 0x3A 0x20 /r:mem ib"/"RMI" { .Instruction = ND_INS_PINSRB, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE4, - .Mnemonic = 626, + .Mnemonic = 627, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -49241,6 +51057,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -49255,12 +51072,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1761 Instruction:"PINSRB Vdq,Ry,Ib" Encoding:"0x66 0x0F 0x3A 0x20 /r:reg ib"/"RMI" + // Pos:1763 Instruction:"PINSRB Vdq,Ry,Ib" Encoding:"0x66 0x0F 0x3A 0x20 /r:reg ib"/"RMI" { .Instruction = ND_INS_PINSRB, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE4, - .Mnemonic = 626, + .Mnemonic = 627, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -49269,6 +51086,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -49283,12 +51101,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1762 Instruction:"PINSRD Vdq,Ed,Ib" Encoding:"0x66 0x0F 0x3A 0x22 /r ib"/"RMI" + // Pos:1764 Instruction:"PINSRD Vdq,Ed,Ib" Encoding:"0x66 0x0F 0x3A 0x22 /r ib"/"RMI" { .Instruction = ND_INS_PINSRD, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE4, - .Mnemonic = 627, + .Mnemonic = 628, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -49297,6 +51115,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -49311,12 +51130,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1763 Instruction:"PINSRQ Vdq,Eq,Ib" Encoding:"rexw 0x66 0x0F 0x3A 0x22 /r ib"/"RMI" + // Pos:1765 Instruction:"PINSRQ Vdq,Eq,Ib" Encoding:"rexw 0x66 0x0F 0x3A 0x22 /r ib"/"RMI" { .Instruction = ND_INS_PINSRQ, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE4, - .Mnemonic = 628, + .Mnemonic = 629, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -49325,6 +51144,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -49339,12 +51159,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1764 Instruction:"PINSRW Pq,Rd,Ib" Encoding:"NP 0x0F 0xC4 /r:reg ib"/"RMI" + // Pos:1766 Instruction:"PINSRW Pq,Rd,Ib" Encoding:"NP 0x0F 0xC4 /r:reg ib"/"RMI" { .Instruction = ND_INS_PINSRW, .Category = ND_CAT_MMX, .IsaSet = ND_SET_MMX, - .Mnemonic = 629, + .Mnemonic = 630, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -49353,6 +51173,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -49367,12 +51188,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1765 Instruction:"PINSRW Pq,Mw,Ib" Encoding:"NP 0x0F 0xC4 /r:mem ib"/"RMI" + // Pos:1767 Instruction:"PINSRW Pq,Mw,Ib" Encoding:"NP 0x0F 0xC4 /r:mem ib"/"RMI" { .Instruction = ND_INS_PINSRW, .Category = ND_CAT_MMX, .IsaSet = ND_SET_MMX, - .Mnemonic = 629, + .Mnemonic = 630, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -49381,6 +51202,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -49395,12 +51217,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1766 Instruction:"PINSRW Vdq,Rd,Ib" Encoding:"0x66 0x0F 0xC4 /r:reg ib"/"RMI" + // Pos:1768 Instruction:"PINSRW Vdq,Rd,Ib" Encoding:"0x66 0x0F 0xC4 /r:reg ib"/"RMI" { .Instruction = ND_INS_PINSRW, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE2, - .Mnemonic = 629, + .Mnemonic = 630, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -49409,6 +51231,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -49423,12 +51246,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1767 Instruction:"PINSRW Vdq,Mw,Ib" Encoding:"0x66 0x0F 0xC4 /r:mem ib"/"RMI" + // Pos:1769 Instruction:"PINSRW Vdq,Mw,Ib" Encoding:"0x66 0x0F 0xC4 /r:mem ib"/"RMI" { .Instruction = ND_INS_PINSRW, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE2, - .Mnemonic = 629, + .Mnemonic = 630, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -49437,6 +51260,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -49451,12 +51275,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1768 Instruction:"PMADDUBSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x04 /r"/"RM" + // Pos:1770 Instruction:"PMADDUBSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x04 /r"/"RM" { .Instruction = ND_INS_PMADDUBSW, .Category = ND_CAT_MMX, .IsaSet = ND_SET_SSSE3, - .Mnemonic = 630, + .Mnemonic = 631, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -49465,6 +51289,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -49478,12 +51303,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1769 Instruction:"PMADDUBSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x04 /r"/"RM" + // Pos:1771 Instruction:"PMADDUBSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x04 /r"/"RM" { .Instruction = ND_INS_PMADDUBSW, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSSE3, - .Mnemonic = 630, + .Mnemonic = 631, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -49492,6 +51317,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -49505,12 +51331,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1770 Instruction:"PMADDWD Pq,Qq" Encoding:"NP 0x0F 0xF5 /r"/"RM" + // Pos:1772 Instruction:"PMADDWD Pq,Qq" Encoding:"NP 0x0F 0xF5 /r"/"RM" { .Instruction = ND_INS_PMADDWD, .Category = ND_CAT_MMX, .IsaSet = ND_SET_MMX, - .Mnemonic = 631, + .Mnemonic = 632, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -49519,6 +51345,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -49532,12 +51359,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1771 Instruction:"PMADDWD Vx,Wx" Encoding:"0x66 0x0F 0xF5 /r"/"RM" + // Pos:1773 Instruction:"PMADDWD Vx,Wx" Encoding:"0x66 0x0F 0xF5 /r"/"RM" { .Instruction = ND_INS_PMADDWD, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE2, - .Mnemonic = 631, + .Mnemonic = 632, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -49546,6 +51373,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -49559,12 +51387,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1772 Instruction:"PMAXSB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3C /r"/"RM" + // Pos:1774 Instruction:"PMAXSB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3C /r"/"RM" { .Instruction = ND_INS_PMAXSB, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE4, - .Mnemonic = 632, + .Mnemonic = 633, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -49573,6 +51401,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -49586,12 +51415,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1773 Instruction:"PMAXSD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3D /r"/"RM" + // Pos:1775 Instruction:"PMAXSD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3D /r"/"RM" { .Instruction = ND_INS_PMAXSD, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE4, - .Mnemonic = 633, + .Mnemonic = 634, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -49600,6 +51429,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -49613,12 +51443,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1774 Instruction:"PMAXSW Pq,Qq" Encoding:"NP 0x0F 0xEE /r"/"RM" + // Pos:1776 Instruction:"PMAXSW Pq,Qq" Encoding:"NP 0x0F 0xEE /r"/"RM" { .Instruction = ND_INS_PMAXSW, .Category = ND_CAT_MMX, .IsaSet = ND_SET_MMX, - .Mnemonic = 634, + .Mnemonic = 635, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -49627,6 +51457,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -49640,12 +51471,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1775 Instruction:"PMAXSW Vx,Wx" Encoding:"0x66 0x0F 0xEE /r"/"RM" + // Pos:1777 Instruction:"PMAXSW Vx,Wx" Encoding:"0x66 0x0F 0xEE /r"/"RM" { .Instruction = ND_INS_PMAXSW, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE2, - .Mnemonic = 634, + .Mnemonic = 635, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -49654,6 +51485,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -49667,12 +51499,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1776 Instruction:"PMAXUB Pq,Qq" Encoding:"NP 0x0F 0xDE /r"/"RM" + // Pos:1778 Instruction:"PMAXUB Pq,Qq" Encoding:"NP 0x0F 0xDE /r"/"RM" { .Instruction = ND_INS_PMAXUB, .Category = ND_CAT_MMX, .IsaSet = ND_SET_MMX, - .Mnemonic = 635, + .Mnemonic = 636, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -49681,6 +51513,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -49694,12 +51527,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1777 Instruction:"PMAXUB Vx,Wx" Encoding:"0x66 0x0F 0xDE /r"/"RM" + // Pos:1779 Instruction:"PMAXUB Vx,Wx" Encoding:"0x66 0x0F 0xDE /r"/"RM" { .Instruction = ND_INS_PMAXUB, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE2, - .Mnemonic = 635, + .Mnemonic = 636, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -49708,6 +51541,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -49721,12 +51555,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1778 Instruction:"PMAXUD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3F /r"/"RM" + // Pos:1780 Instruction:"PMAXUD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3F /r"/"RM" { .Instruction = ND_INS_PMAXUD, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE4, - .Mnemonic = 636, + .Mnemonic = 637, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -49735,6 +51569,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -49748,12 +51583,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1779 Instruction:"PMAXUW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3E /r"/"RM" + // Pos:1781 Instruction:"PMAXUW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3E /r"/"RM" { .Instruction = ND_INS_PMAXUW, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE4, - .Mnemonic = 637, + .Mnemonic = 638, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -49762,6 +51597,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -49775,12 +51611,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1780 Instruction:"PMINSB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x38 /r"/"RM" + // Pos:1782 Instruction:"PMINSB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x38 /r"/"RM" { .Instruction = ND_INS_PMINSB, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE4, - .Mnemonic = 638, + .Mnemonic = 639, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -49789,6 +51625,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -49802,12 +51639,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1781 Instruction:"PMINSD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x39 /r"/"RM" + // Pos:1783 Instruction:"PMINSD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x39 /r"/"RM" { .Instruction = ND_INS_PMINSD, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE4, - .Mnemonic = 639, + .Mnemonic = 640, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -49816,6 +51653,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -49829,12 +51667,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1782 Instruction:"PMINSW Pq,Qq" Encoding:"NP 0x0F 0xEA /r"/"RM" + // Pos:1784 Instruction:"PMINSW Pq,Qq" Encoding:"NP 0x0F 0xEA /r"/"RM" { .Instruction = ND_INS_PMINSW, .Category = ND_CAT_MMX, .IsaSet = ND_SET_MMX, - .Mnemonic = 640, + .Mnemonic = 641, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -49843,6 +51681,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -49856,12 +51695,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1783 Instruction:"PMINSW Vx,Wx" Encoding:"0x66 0x0F 0xEA /r"/"RM" + // Pos:1785 Instruction:"PMINSW Vx,Wx" Encoding:"0x66 0x0F 0xEA /r"/"RM" { .Instruction = ND_INS_PMINSW, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE2, - .Mnemonic = 640, + .Mnemonic = 641, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -49870,6 +51709,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -49883,12 +51723,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1784 Instruction:"PMINUB Pq,Qq" Encoding:"NP 0x0F 0xDA /r"/"RM" + // Pos:1786 Instruction:"PMINUB Pq,Qq" Encoding:"NP 0x0F 0xDA /r"/"RM" { .Instruction = ND_INS_PMINUB, .Category = ND_CAT_MMX, .IsaSet = ND_SET_MMX, - .Mnemonic = 641, + .Mnemonic = 642, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -49897,6 +51737,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -49910,12 +51751,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1785 Instruction:"PMINUB Vx,Wx" Encoding:"0x66 0x0F 0xDA /r"/"RM" + // Pos:1787 Instruction:"PMINUB Vx,Wx" Encoding:"0x66 0x0F 0xDA /r"/"RM" { .Instruction = ND_INS_PMINUB, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE2, - .Mnemonic = 641, + .Mnemonic = 642, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -49924,6 +51765,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -49937,12 +51779,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1786 Instruction:"PMINUD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3B /r"/"RM" + // Pos:1788 Instruction:"PMINUD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3B /r"/"RM" { .Instruction = ND_INS_PMINUD, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE4, - .Mnemonic = 642, + .Mnemonic = 643, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -49951,6 +51793,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -49964,12 +51807,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1787 Instruction:"PMINUW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3A /r"/"RM" + // Pos:1789 Instruction:"PMINUW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3A /r"/"RM" { .Instruction = ND_INS_PMINUW, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE4, - .Mnemonic = 643, + .Mnemonic = 644, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -49978,6 +51821,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -49991,12 +51835,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1788 Instruction:"PMOVMSKB Gy,Nq" Encoding:"NP 0x0F 0xD7 /r:reg"/"RM" + // Pos:1790 Instruction:"PMOVMSKB Gy,Nq" Encoding:"NP 0x0F 0xD7 /r:reg"/"RM" { .Instruction = ND_INS_PMOVMSKB, .Category = ND_CAT_MMX, .IsaSet = ND_SET_SSE, - .Mnemonic = 644, + .Mnemonic = 645, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -50005,6 +51849,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_7, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -50018,12 +51863,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1789 Instruction:"PMOVMSKB Gy,Ux" Encoding:"0x66 0x0F 0xD7 /r:reg"/"RM" + // Pos:1791 Instruction:"PMOVMSKB Gy,Ux" Encoding:"0x66 0x0F 0xD7 /r:reg"/"RM" { .Instruction = ND_INS_PMOVMSKB, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE2, - .Mnemonic = 644, + .Mnemonic = 645, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -50032,6 +51877,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_7, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -50045,12 +51891,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1790 Instruction:"PMOVSXBD Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x21 /r"/"RM" + // Pos:1792 Instruction:"PMOVSXBD Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x21 /r"/"RM" { .Instruction = ND_INS_PMOVSXBD, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE4, - .Mnemonic = 645, + .Mnemonic = 646, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -50059,6 +51905,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -50072,12 +51919,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1791 Instruction:"PMOVSXBQ Vdq,Ww" Encoding:"0x66 0x0F 0x38 0x22 /r"/"RM" + // Pos:1793 Instruction:"PMOVSXBQ Vdq,Ww" Encoding:"0x66 0x0F 0x38 0x22 /r"/"RM" { .Instruction = ND_INS_PMOVSXBQ, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE4, - .Mnemonic = 646, + .Mnemonic = 647, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -50086,6 +51933,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -50099,12 +51947,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1792 Instruction:"PMOVSXBW Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x20 /r"/"RM" + // Pos:1794 Instruction:"PMOVSXBW Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x20 /r"/"RM" { .Instruction = ND_INS_PMOVSXBW, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE4, - .Mnemonic = 647, + .Mnemonic = 648, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -50113,6 +51961,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -50126,12 +51975,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1793 Instruction:"PMOVSXDQ Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x25 /r"/"RM" + // Pos:1795 Instruction:"PMOVSXDQ Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x25 /r"/"RM" { .Instruction = ND_INS_PMOVSXDQ, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE4, - .Mnemonic = 648, + .Mnemonic = 649, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -50140,6 +51989,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -50153,12 +52003,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1794 Instruction:"PMOVSXWD Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x23 /r"/"RM" + // Pos:1796 Instruction:"PMOVSXWD Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x23 /r"/"RM" { .Instruction = ND_INS_PMOVSXWD, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE4, - .Mnemonic = 649, + .Mnemonic = 650, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -50167,6 +52017,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -50180,12 +52031,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1795 Instruction:"PMOVSXWQ Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x24 /r"/"RM" + // Pos:1797 Instruction:"PMOVSXWQ Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x24 /r"/"RM" { .Instruction = ND_INS_PMOVSXWQ, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE4, - .Mnemonic = 650, + .Mnemonic = 651, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -50194,6 +52045,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -50207,12 +52059,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1796 Instruction:"PMOVZXBD Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x31 /r"/"RM" + // Pos:1798 Instruction:"PMOVZXBD Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x31 /r"/"RM" { .Instruction = ND_INS_PMOVZXBD, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE4, - .Mnemonic = 651, + .Mnemonic = 652, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -50221,6 +52073,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -50234,12 +52087,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1797 Instruction:"PMOVZXBQ Vdq,Ww" Encoding:"0x66 0x0F 0x38 0x32 /r"/"RM" + // Pos:1799 Instruction:"PMOVZXBQ Vdq,Ww" Encoding:"0x66 0x0F 0x38 0x32 /r"/"RM" { .Instruction = ND_INS_PMOVZXBQ, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE4, - .Mnemonic = 652, + .Mnemonic = 653, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -50248,6 +52101,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -50261,12 +52115,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1798 Instruction:"PMOVZXBW Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x30 /r"/"RM" + // Pos:1800 Instruction:"PMOVZXBW Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x30 /r"/"RM" { .Instruction = ND_INS_PMOVZXBW, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE4, - .Mnemonic = 653, + .Mnemonic = 654, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -50275,6 +52129,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -50288,12 +52143,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1799 Instruction:"PMOVZXDQ Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x35 /r"/"RM" + // Pos:1801 Instruction:"PMOVZXDQ Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x35 /r"/"RM" { .Instruction = ND_INS_PMOVZXDQ, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE4, - .Mnemonic = 654, + .Mnemonic = 655, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -50302,6 +52157,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -50315,12 +52171,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1800 Instruction:"PMOVZXWD Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x33 /r"/"RM" + // Pos:1802 Instruction:"PMOVZXWD Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x33 /r"/"RM" { .Instruction = ND_INS_PMOVZXWD, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE4, - .Mnemonic = 655, + .Mnemonic = 656, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -50329,6 +52185,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -50342,12 +52199,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1801 Instruction:"PMOVZXWQ Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x34 /r"/"RM" + // Pos:1803 Instruction:"PMOVZXWQ Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x34 /r"/"RM" { .Instruction = ND_INS_PMOVZXWQ, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE4, - .Mnemonic = 656, + .Mnemonic = 657, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -50356,6 +52213,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -50369,12 +52227,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1802 Instruction:"PMULDQ Vx,Wx" Encoding:"0x66 0x0F 0x38 0x28 /r"/"RM" + // Pos:1804 Instruction:"PMULDQ Vx,Wx" Encoding:"0x66 0x0F 0x38 0x28 /r"/"RM" { .Instruction = ND_INS_PMULDQ, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE4, - .Mnemonic = 657, + .Mnemonic = 658, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -50383,6 +52241,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -50396,12 +52255,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1803 Instruction:"PMULHRSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x0B /r"/"RM" + // Pos:1805 Instruction:"PMULHRSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x0B /r"/"RM" { .Instruction = ND_INS_PMULHRSW, .Category = ND_CAT_MMX, .IsaSet = ND_SET_SSSE3, - .Mnemonic = 658, + .Mnemonic = 659, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -50410,6 +52269,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -50423,12 +52283,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1804 Instruction:"PMULHRSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x0B /r"/"RM" + // Pos:1806 Instruction:"PMULHRSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x0B /r"/"RM" { .Instruction = ND_INS_PMULHRSW, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSSE3, - .Mnemonic = 658, + .Mnemonic = 659, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -50437,6 +52297,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -50450,12 +52311,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1805 Instruction:"PMULHRW Pq,Qq" Encoding:"0x0F 0x0F /r 0xB7"/"RM" + // Pos:1807 Instruction:"PMULHRW Pq,Qq" Encoding:"0x0F 0x0F /r 0xB7"/"RM" { .Instruction = ND_INS_PMULHRW, .Category = ND_CAT_3DNOW, .IsaSet = ND_SET_3DNOW, - .Mnemonic = 659, + .Mnemonic = 660, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -50464,6 +52325,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -50477,12 +52339,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1806 Instruction:"PMULHUW Pq,Qq" Encoding:"NP 0x0F 0xE4 /r"/"RM" + // Pos:1808 Instruction:"PMULHUW Pq,Qq" Encoding:"NP 0x0F 0xE4 /r"/"RM" { .Instruction = ND_INS_PMULHUW, .Category = ND_CAT_MMX, .IsaSet = ND_SET_MMX, - .Mnemonic = 660, + .Mnemonic = 661, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -50491,6 +52353,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -50504,12 +52367,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1807 Instruction:"PMULHUW Vx,Wx" Encoding:"0x66 0x0F 0xE4 /r"/"RM" + // Pos:1809 Instruction:"PMULHUW Vx,Wx" Encoding:"0x66 0x0F 0xE4 /r"/"RM" { .Instruction = ND_INS_PMULHUW, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE2, - .Mnemonic = 660, + .Mnemonic = 661, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -50518,6 +52381,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -50531,12 +52395,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1808 Instruction:"PMULHW Pq,Qq" Encoding:"NP 0x0F 0xE5 /r"/"RM" + // Pos:1810 Instruction:"PMULHW Pq,Qq" Encoding:"NP 0x0F 0xE5 /r"/"RM" { .Instruction = ND_INS_PMULHW, .Category = ND_CAT_MMX, .IsaSet = ND_SET_MMX, - .Mnemonic = 661, + .Mnemonic = 662, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -50545,6 +52409,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -50558,12 +52423,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1809 Instruction:"PMULHW Vx,Wx" Encoding:"0x66 0x0F 0xE5 /r"/"RM" + // Pos:1811 Instruction:"PMULHW Vx,Wx" Encoding:"0x66 0x0F 0xE5 /r"/"RM" { .Instruction = ND_INS_PMULHW, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE2, - .Mnemonic = 661, + .Mnemonic = 662, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -50572,6 +52437,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -50585,12 +52451,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1810 Instruction:"PMULLD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x40 /r"/"RM" + // Pos:1812 Instruction:"PMULLD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x40 /r"/"RM" { .Instruction = ND_INS_PMULLD, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE4, - .Mnemonic = 662, + .Mnemonic = 663, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -50599,6 +52465,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -50612,12 +52479,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1811 Instruction:"PMULLW Pq,Qq" Encoding:"NP 0x0F 0xD5 /r"/"RM" + // Pos:1813 Instruction:"PMULLW Pq,Qq" Encoding:"NP 0x0F 0xD5 /r"/"RM" { .Instruction = ND_INS_PMULLW, .Category = ND_CAT_MMX, .IsaSet = ND_SET_MMX, - .Mnemonic = 663, + .Mnemonic = 664, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -50626,6 +52493,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -50639,12 +52507,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1812 Instruction:"PMULLW Vx,Wx" Encoding:"0x66 0x0F 0xD5 /r"/"RM" + // Pos:1814 Instruction:"PMULLW Vx,Wx" Encoding:"0x66 0x0F 0xD5 /r"/"RM" { .Instruction = ND_INS_PMULLW, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE2, - .Mnemonic = 663, + .Mnemonic = 664, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -50653,6 +52521,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -50666,12 +52535,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1813 Instruction:"PMULUDQ Pq,Qq" Encoding:"NP 0x0F 0xF4 /r"/"RM" + // Pos:1815 Instruction:"PMULUDQ Pq,Qq" Encoding:"NP 0x0F 0xF4 /r"/"RM" { .Instruction = ND_INS_PMULUDQ, .Category = ND_CAT_MMX, .IsaSet = ND_SET_SSE2, - .Mnemonic = 664, + .Mnemonic = 665, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -50680,6 +52549,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -50693,12 +52563,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1814 Instruction:"PMULUDQ Vx,Wx" Encoding:"0x66 0x0F 0xF4 /r"/"RM" + // Pos:1816 Instruction:"PMULUDQ Vx,Wx" Encoding:"0x66 0x0F 0xF4 /r"/"RM" { .Instruction = ND_INS_PMULUDQ, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE2, - .Mnemonic = 664, + .Mnemonic = 665, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -50707,6 +52577,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -50720,12 +52591,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1815 Instruction:"POP ES" Encoding:"0x07"/"" + // Pos:1817 Instruction:"POP ES" Encoding:"0x07"/"" { .Instruction = ND_INS_POP, .Category = ND_CAT_POP, .IsaSet = ND_SET_I86, - .Mnemonic = 665, + .Mnemonic = 666, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -50734,6 +52605,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -50747,12 +52619,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1816 Instruction:"POP SS" Encoding:"0x17"/"" + // Pos:1818 Instruction:"POP SS" Encoding:"0x17"/"" { .Instruction = ND_INS_POP, .Category = ND_CAT_POP, .IsaSet = ND_SET_I86, - .Mnemonic = 665, + .Mnemonic = 666, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -50761,6 +52633,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -50774,12 +52647,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1817 Instruction:"POP DS" Encoding:"0x1F"/"" + // Pos:1819 Instruction:"POP DS" Encoding:"0x1F"/"" { .Instruction = ND_INS_POP, .Category = ND_CAT_POP, .IsaSet = ND_SET_I86, - .Mnemonic = 665, + .Mnemonic = 666, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -50788,6 +52661,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -50801,12 +52675,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1818 Instruction:"POP Zv" Encoding:"0x58"/"O" + // Pos:1820 Instruction:"POP Zv" Encoding:"0x58"/"O" { .Instruction = ND_INS_POP, .Category = ND_CAT_POP, .IsaSet = ND_SET_I86, - .Mnemonic = 665, + .Mnemonic = 666, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -50815,6 +52689,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -50828,12 +52703,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1819 Instruction:"POP Zv" Encoding:"0x59"/"O" + // Pos:1821 Instruction:"POP Zv" Encoding:"0x59"/"O" { .Instruction = ND_INS_POP, .Category = ND_CAT_POP, .IsaSet = ND_SET_I86, - .Mnemonic = 665, + .Mnemonic = 666, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -50842,6 +52717,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -50855,12 +52731,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1820 Instruction:"POP Zv" Encoding:"0x5A"/"O" + // Pos:1822 Instruction:"POP Zv" Encoding:"0x5A"/"O" { .Instruction = ND_INS_POP, .Category = ND_CAT_POP, .IsaSet = ND_SET_I86, - .Mnemonic = 665, + .Mnemonic = 666, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -50869,6 +52745,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -50882,12 +52759,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1821 Instruction:"POP Zv" Encoding:"0x5B"/"O" + // Pos:1823 Instruction:"POP Zv" Encoding:"0x5B"/"O" { .Instruction = ND_INS_POP, .Category = ND_CAT_POP, .IsaSet = ND_SET_I86, - .Mnemonic = 665, + .Mnemonic = 666, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -50896,6 +52773,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -50909,12 +52787,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1822 Instruction:"POP Zv" Encoding:"0x5C"/"O" + // Pos:1824 Instruction:"POP Zv" Encoding:"0x5C"/"O" { .Instruction = ND_INS_POP, .Category = ND_CAT_POP, .IsaSet = ND_SET_I86, - .Mnemonic = 665, + .Mnemonic = 666, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -50923,6 +52801,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -50936,12 +52815,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1823 Instruction:"POP Zv" Encoding:"0x5D"/"O" + // Pos:1825 Instruction:"POP Zv" Encoding:"0x5D"/"O" { .Instruction = ND_INS_POP, .Category = ND_CAT_POP, .IsaSet = ND_SET_I86, - .Mnemonic = 665, + .Mnemonic = 666, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -50950,6 +52829,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -50963,12 +52843,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1824 Instruction:"POP Zv" Encoding:"0x5E"/"O" + // Pos:1826 Instruction:"POP Zv" Encoding:"0x5E"/"O" { .Instruction = ND_INS_POP, .Category = ND_CAT_POP, .IsaSet = ND_SET_I86, - .Mnemonic = 665, + .Mnemonic = 666, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -50977,6 +52857,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -50990,12 +52871,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1825 Instruction:"POP Zv" Encoding:"0x5F"/"O" + // Pos:1827 Instruction:"POP Zv" Encoding:"0x5F"/"O" { .Instruction = ND_INS_POP, .Category = ND_CAT_POP, .IsaSet = ND_SET_I86, - .Mnemonic = 665, + .Mnemonic = 666, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -51004,6 +52885,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -51017,12 +52899,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1826 Instruction:"POP Ev" Encoding:"0x8F /0"/"M" + // Pos:1828 Instruction:"POP Ev" Encoding:"0x8F /0"/"M" { .Instruction = ND_INS_POP, .Category = ND_CAT_POP, .IsaSet = ND_SET_I86, - .Mnemonic = 665, + .Mnemonic = 666, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -51031,6 +52913,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -51044,12 +52927,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1827 Instruction:"POP FS" Encoding:"0x0F 0xA1"/"" + // Pos:1829 Instruction:"POP FS" Encoding:"0x0F 0xA1"/"" { .Instruction = ND_INS_POP, .Category = ND_CAT_POP, .IsaSet = ND_SET_I86, - .Mnemonic = 665, + .Mnemonic = 666, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -51058,6 +52941,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -51071,12 +52955,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1828 Instruction:"POP GS" Encoding:"0x0F 0xA9"/"" + // Pos:1830 Instruction:"POP GS" Encoding:"0x0F 0xA9"/"" { .Instruction = ND_INS_POP, .Category = ND_CAT_POP, .IsaSet = ND_SET_I86, - .Mnemonic = 665, + .Mnemonic = 666, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -51085,6 +52969,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -51098,12 +52983,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1829 Instruction:"POP2 Bv,Rv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 w:0 0x8F /0:reg"/"VM" + // Pos:1831 Instruction:"POP2 Bv,Rv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 w:0 0x8F /0:reg"/"VM" { .Instruction = ND_INS_POP2, .Category = ND_CAT_POP, .IsaSet = ND_SET_APX_F, - .Mnemonic = 666, + .Mnemonic = 667, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -51112,6 +52997,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_PP2, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -51126,12 +53012,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1830 Instruction:"POP2P Bv,Rv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 w:1 0x8F /0:reg"/"VM" + // Pos:1832 Instruction:"POP2P Bv,Rv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 w:1 0x8F /0:reg"/"VM" { .Instruction = ND_INS_POP2P, .Category = ND_CAT_POP, .IsaSet = ND_SET_APX_F, - .Mnemonic = 667, + .Mnemonic = 668, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -51140,6 +53026,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_PP2, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -51154,12 +53041,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1831 Instruction:"POPA" Encoding:"ds16 0x61"/"" + // Pos:1833 Instruction:"POPA" Encoding:"ds16 0x61"/"" { .Instruction = ND_INS_POPA, .Category = ND_CAT_POP, .IsaSet = ND_SET_I386, - .Mnemonic = 668, + .Mnemonic = 669, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -51168,6 +53055,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -51181,12 +53069,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1832 Instruction:"POPAD" Encoding:"ds32 0x61"/"" + // Pos:1834 Instruction:"POPAD" Encoding:"ds32 0x61"/"" { .Instruction = ND_INS_POPAD, .Category = ND_CAT_POP, .IsaSet = ND_SET_I386, - .Mnemonic = 669, + .Mnemonic = 670, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -51195,6 +53083,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -51208,12 +53097,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1833 Instruction:"POPCNT Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x88 /r"/"RM" + // Pos:1835 Instruction:"POPCNT Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x88 /r"/"RM" { .Instruction = ND_INS_POPCNT, .Category = ND_CAT_APX, .IsaSet = ND_SET_APX_F, - .Mnemonic = 670, + .Mnemonic = 671, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -51222,6 +53111,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_ZF, .SetFlags = 0, @@ -51236,12 +53126,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1834 Instruction:"POPCNT Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x88 /r"/"RM" + // Pos:1836 Instruction:"POPCNT Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x88 /r"/"RM" { .Instruction = ND_INS_POPCNT, .Category = ND_CAT_APX, .IsaSet = ND_SET_APX_F, - .Mnemonic = 670, + .Mnemonic = 671, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -51250,6 +53140,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_ZF, .SetFlags = 0, @@ -51264,12 +53155,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1835 Instruction:"POPCNT Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x88 /r"/"RM" + // Pos:1837 Instruction:"POPCNT Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x88 /r"/"RM" { .Instruction = ND_INS_POPCNT, .Category = ND_CAT_APX, .IsaSet = ND_SET_APX_F, - .Mnemonic = 670, + .Mnemonic = 671, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -51278,6 +53169,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -51291,12 +53183,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1836 Instruction:"POPCNT Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x88 /r"/"RM" + // Pos:1838 Instruction:"POPCNT Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x88 /r"/"RM" { .Instruction = ND_INS_POPCNT, .Category = ND_CAT_APX, .IsaSet = ND_SET_APX_F, - .Mnemonic = 670, + .Mnemonic = 671, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -51305,6 +53197,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -51318,12 +53211,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1837 Instruction:"POPCNT Gv,Ev" Encoding:"repz 0x0F 0xB8 /r"/"RM" + // Pos:1839 Instruction:"POPCNT Gv,Ev" Encoding:"repz 0x0F 0xB8 /r"/"RM" { .Instruction = ND_INS_POPCNT, .Category = ND_CAT_SSE, .IsaSet = ND_SET_POPCNT, - .Mnemonic = 670, + .Mnemonic = 671, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -51332,6 +53225,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_ZF, .SetFlags = 0, @@ -51346,12 +53240,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1838 Instruction:"POPFD Fv" Encoding:"ds32 0x9D"/"" + // Pos:1840 Instruction:"POPFD Fv" Encoding:"ds32 0x9D"/"" { .Instruction = ND_INS_POPF, .Category = ND_CAT_POP, .IsaSet = ND_SET_I86, - .Mnemonic = 671, + .Mnemonic = 672, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -51360,6 +53254,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -51373,12 +53268,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1839 Instruction:"POPFQ Fv" Encoding:"dds64 0x9D"/"" + // Pos:1841 Instruction:"POPFQ Fv" Encoding:"dds64 0x9D"/"" { .Instruction = ND_INS_POPF, .Category = ND_CAT_POP, .IsaSet = ND_SET_I86, - .Mnemonic = 672, + .Mnemonic = 673, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -51387,6 +53282,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -51400,12 +53296,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1840 Instruction:"POPFW Fv" Encoding:"ds16 0x9D"/"" + // Pos:1842 Instruction:"POPFW Fv" Encoding:"ds16 0x9D"/"" { .Instruction = ND_INS_POPF, .Category = ND_CAT_POP, .IsaSet = ND_SET_I86, - .Mnemonic = 673, + .Mnemonic = 674, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -51414,6 +53310,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -51427,12 +53324,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1841 Instruction:"POPP Zv" Encoding:"rex2w 0x58"/"O" + // Pos:1843 Instruction:"POPP Zv" Encoding:"rex2w 0x58"/"O" { .Instruction = ND_INS_POPP, .Category = ND_CAT_POP, .IsaSet = ND_SET_APX_F, - .Mnemonic = 674, + .Mnemonic = 675, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -51441,6 +53338,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -51454,12 +53352,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1842 Instruction:"POPP Zv" Encoding:"rex2w 0x59"/"O" + // Pos:1844 Instruction:"POPP Zv" Encoding:"rex2w 0x59"/"O" { .Instruction = ND_INS_POPP, .Category = ND_CAT_POP, .IsaSet = ND_SET_APX_F, - .Mnemonic = 674, + .Mnemonic = 675, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -51468,6 +53366,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -51481,12 +53380,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1843 Instruction:"POPP Zv" Encoding:"rex2w 0x5A"/"O" + // Pos:1845 Instruction:"POPP Zv" Encoding:"rex2w 0x5A"/"O" { .Instruction = ND_INS_POPP, .Category = ND_CAT_POP, .IsaSet = ND_SET_APX_F, - .Mnemonic = 674, + .Mnemonic = 675, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -51495,6 +53394,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -51508,12 +53408,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1844 Instruction:"POPP Zv" Encoding:"rex2w 0x5B"/"O" + // Pos:1846 Instruction:"POPP Zv" Encoding:"rex2w 0x5B"/"O" { .Instruction = ND_INS_POPP, .Category = ND_CAT_POP, .IsaSet = ND_SET_APX_F, - .Mnemonic = 674, + .Mnemonic = 675, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -51522,6 +53422,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -51535,12 +53436,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1845 Instruction:"POPP Zv" Encoding:"rex2w 0x5C"/"O" + // Pos:1847 Instruction:"POPP Zv" Encoding:"rex2w 0x5C"/"O" { .Instruction = ND_INS_POPP, .Category = ND_CAT_POP, .IsaSet = ND_SET_APX_F, - .Mnemonic = 674, + .Mnemonic = 675, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -51549,6 +53450,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -51562,12 +53464,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1846 Instruction:"POPP Zv" Encoding:"rex2w 0x5D"/"O" + // Pos:1848 Instruction:"POPP Zv" Encoding:"rex2w 0x5D"/"O" { .Instruction = ND_INS_POPP, .Category = ND_CAT_POP, .IsaSet = ND_SET_APX_F, - .Mnemonic = 674, + .Mnemonic = 675, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -51576,6 +53478,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -51589,12 +53492,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1847 Instruction:"POPP Zv" Encoding:"rex2w 0x5E"/"O" + // Pos:1849 Instruction:"POPP Zv" Encoding:"rex2w 0x5E"/"O" { .Instruction = ND_INS_POPP, .Category = ND_CAT_POP, .IsaSet = ND_SET_APX_F, - .Mnemonic = 674, + .Mnemonic = 675, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -51603,6 +53506,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -51616,12 +53520,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1848 Instruction:"POPP Zv" Encoding:"rex2w 0x5F"/"O" + // Pos:1850 Instruction:"POPP Zv" Encoding:"rex2w 0x5F"/"O" { .Instruction = ND_INS_POPP, .Category = ND_CAT_POP, .IsaSet = ND_SET_APX_F, - .Mnemonic = 674, + .Mnemonic = 675, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -51630,6 +53534,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -51643,12 +53548,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1849 Instruction:"POR Pq,Qq" Encoding:"NP 0x0F 0xEB /r"/"RM" + // Pos:1851 Instruction:"POR Pq,Qq" Encoding:"NP 0x0F 0xEB /r"/"RM" { .Instruction = ND_INS_POR, .Category = ND_CAT_LOGICAL, .IsaSet = ND_SET_MMX, - .Mnemonic = 675, + .Mnemonic = 676, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -51657,6 +53562,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -51670,12 +53576,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1850 Instruction:"POR Vx,Wx" Encoding:"0x66 0x0F 0xEB /r"/"RM" + // Pos:1852 Instruction:"POR Vx,Wx" Encoding:"0x66 0x0F 0xEB /r"/"RM" { .Instruction = ND_INS_POR, .Category = ND_CAT_LOGICAL, .IsaSet = ND_SET_SSE2, - .Mnemonic = 675, + .Mnemonic = 676, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -51684,6 +53590,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -51697,12 +53604,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1851 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /4:mem"/"M" + // Pos:1853 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /4:mem"/"M" { .Instruction = ND_INS_PREFETCH, .Category = ND_CAT_PREFETCH, .IsaSet = ND_SET_PREFETCH_NOP, - .Mnemonic = 676, + .Mnemonic = 677, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -51711,6 +53618,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -51723,12 +53631,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1852 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /5:mem"/"M" + // Pos:1854 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /5:mem"/"M" { .Instruction = ND_INS_PREFETCH, .Category = ND_CAT_PREFETCH, .IsaSet = ND_SET_PREFETCH_NOP, - .Mnemonic = 676, + .Mnemonic = 677, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -51737,6 +53645,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -51749,12 +53658,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1853 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /6:mem"/"M" + // Pos:1855 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /6:mem"/"M" { .Instruction = ND_INS_PREFETCH, .Category = ND_CAT_PREFETCH, .IsaSet = ND_SET_PREFETCH_NOP, - .Mnemonic = 676, + .Mnemonic = 677, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -51763,6 +53672,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -51775,12 +53685,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1854 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /7:mem"/"M" + // Pos:1856 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /7:mem"/"M" { .Instruction = ND_INS_PREFETCH, .Category = ND_CAT_PREFETCH, .IsaSet = ND_SET_PREFETCH_NOP, - .Mnemonic = 676, + .Mnemonic = 677, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -51789,6 +53699,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -51801,12 +53712,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1855 Instruction:"PREFETCHE Mb" Encoding:"0x0F 0x0D /0:mem"/"M" + // Pos:1857 Instruction:"PREFETCHE Mb" Encoding:"0x0F 0x0D /0:mem"/"M" { .Instruction = ND_INS_PREFETCHE, .Category = ND_CAT_PREFETCH, .IsaSet = ND_SET_PREFETCH_NOP, - .Mnemonic = 677, + .Mnemonic = 678, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -51815,6 +53726,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -51827,12 +53739,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1856 Instruction:"PREFETCHIT0 Mb" Encoding:"piti riprel 0x0F 0x18 /7:mem"/"M" + // Pos:1858 Instruction:"PREFETCHIT0 Mb" Encoding:"piti riprel 0x0F 0x18 /7:mem"/"M" { .Instruction = ND_INS_PREFETCHIT0, .Category = ND_CAT_PREFETCH, .IsaSet = ND_SET_PREFETCHITI, - .Mnemonic = 678, + .Mnemonic = 679, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -51841,6 +53753,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -51853,12 +53766,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1857 Instruction:"PREFETCHIT1 Mb" Encoding:"piti riprel 0x0F 0x18 /6:mem"/"M" + // Pos:1859 Instruction:"PREFETCHIT1 Mb" Encoding:"piti riprel 0x0F 0x18 /6:mem"/"M" { .Instruction = ND_INS_PREFETCHIT1, .Category = ND_CAT_PREFETCH, .IsaSet = ND_SET_PREFETCHITI, - .Mnemonic = 679, + .Mnemonic = 680, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -51867,6 +53780,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -51879,12 +53793,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1858 Instruction:"PREFETCHM Mb" Encoding:"0x0F 0x0D /3:mem"/"M" + // Pos:1860 Instruction:"PREFETCHM Mb" Encoding:"0x0F 0x0D /3:mem"/"M" { .Instruction = ND_INS_PREFETCHM, .Category = ND_CAT_PREFETCH, .IsaSet = ND_SET_PREFETCH_NOP, - .Mnemonic = 680, + .Mnemonic = 681, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -51893,6 +53807,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -51905,12 +53820,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1859 Instruction:"PREFETCHNTA Mb" Encoding:"0x0F 0x18 /0:mem"/"M" + // Pos:1861 Instruction:"PREFETCHNTA Mb" Encoding:"0x0F 0x18 /0:mem"/"M" { .Instruction = ND_INS_PREFETCHNTA, .Category = ND_CAT_PREFETCH, .IsaSet = ND_SET_SSE, - .Mnemonic = 681, + .Mnemonic = 682, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -51919,6 +53834,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -51931,12 +53847,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1860 Instruction:"PREFETCHNTA Mb" Encoding:"piti 0x0F 0x18 /0:mem"/"M" + // Pos:1862 Instruction:"PREFETCHNTA Mb" Encoding:"piti 0x0F 0x18 /0:mem"/"M" { .Instruction = ND_INS_PREFETCHNTA, .Category = ND_CAT_PREFETCH, .IsaSet = ND_SET_SSE, - .Mnemonic = 681, + .Mnemonic = 682, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -51945,6 +53861,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -51957,12 +53874,66 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1861 Instruction:"PREFETCHT0 Mb" Encoding:"0x0F 0x18 /1:mem"/"M" + // Pos:1863 Instruction:"PREFETCHRST2 Mb" Encoding:"0x0F 0x18 /4:mem"/"M" + { + .Instruction = ND_INS_PREFETCHRST2, + .Category = ND_CAT_PREFETCH, + .IsaSet = ND_SET_MOVRS, + .Mnemonic = 683, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .SimdExc = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_MOVRS, + .Operands = + { + OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0), + }, + }, + + // Pos:1864 Instruction:"PREFETCHRST2 Mb" Encoding:"piti 0x0F 0x18 /4:mem"/"M" + { + .Instruction = ND_INS_PREFETCHRST2, + .Category = ND_CAT_PREFETCH, + .IsaSet = ND_SET_MOVRS, + .Mnemonic = 683, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .SimdExc = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_MOVRS, + .Operands = + { + OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0), + }, + }, + + // Pos:1865 Instruction:"PREFETCHT0 Mb" Encoding:"0x0F 0x18 /1:mem"/"M" { .Instruction = ND_INS_PREFETCHT0, .Category = ND_CAT_PREFETCH, .IsaSet = ND_SET_SSE, - .Mnemonic = 682, + .Mnemonic = 684, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -51971,6 +53942,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -51983,12 +53955,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1862 Instruction:"PREFETCHT0 Mb" Encoding:"piti 0x0F 0x18 /1:mem"/"M" + // Pos:1866 Instruction:"PREFETCHT0 Mb" Encoding:"piti 0x0F 0x18 /1:mem"/"M" { .Instruction = ND_INS_PREFETCHT0, .Category = ND_CAT_PREFETCH, .IsaSet = ND_SET_SSE, - .Mnemonic = 682, + .Mnemonic = 684, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -51997,6 +53969,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -52009,12 +53982,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1863 Instruction:"PREFETCHT1 Mb" Encoding:"0x0F 0x18 /2:mem"/"M" + // Pos:1867 Instruction:"PREFETCHT1 Mb" Encoding:"0x0F 0x18 /2:mem"/"M" { .Instruction = ND_INS_PREFETCHT1, .Category = ND_CAT_PREFETCH, .IsaSet = ND_SET_SSE, - .Mnemonic = 683, + .Mnemonic = 685, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -52023,6 +53996,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -52035,12 +54009,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1864 Instruction:"PREFETCHT1 Mb" Encoding:"piti 0x0F 0x18 /2:mem"/"M" + // Pos:1868 Instruction:"PREFETCHT1 Mb" Encoding:"piti 0x0F 0x18 /2:mem"/"M" { .Instruction = ND_INS_PREFETCHT1, .Category = ND_CAT_PREFETCH, .IsaSet = ND_SET_SSE, - .Mnemonic = 683, + .Mnemonic = 685, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -52049,6 +54023,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -52061,12 +54036,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1865 Instruction:"PREFETCHT2 Mb" Encoding:"0x0F 0x18 /3:mem"/"M" + // Pos:1869 Instruction:"PREFETCHT2 Mb" Encoding:"0x0F 0x18 /3:mem"/"M" { .Instruction = ND_INS_PREFETCHT2, .Category = ND_CAT_PREFETCH, .IsaSet = ND_SET_SSE, - .Mnemonic = 684, + .Mnemonic = 686, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -52075,6 +54050,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -52087,12 +54063,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1866 Instruction:"PREFETCHT2 Mb" Encoding:"piti 0x0F 0x18 /3:mem"/"M" + // Pos:1870 Instruction:"PREFETCHT2 Mb" Encoding:"piti 0x0F 0x18 /3:mem"/"M" { .Instruction = ND_INS_PREFETCHT2, .Category = ND_CAT_PREFETCH, .IsaSet = ND_SET_SSE, - .Mnemonic = 684, + .Mnemonic = 686, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -52101,6 +54077,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -52113,12 +54090,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1867 Instruction:"PREFETCHW Mb" Encoding:"0x0F 0x0D /1:mem"/"M" + // Pos:1871 Instruction:"PREFETCHW Mb" Encoding:"0x0F 0x0D /1:mem"/"M" { .Instruction = ND_INS_PREFETCHW, .Category = ND_CAT_PREFETCH, .IsaSet = ND_SET_PREFETCH_NOP, - .Mnemonic = 685, + .Mnemonic = 687, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -52127,6 +54104,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -52139,12 +54117,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1868 Instruction:"PREFETCHWT1 Mb" Encoding:"0x0F 0x0D /2:mem"/"M" + // Pos:1872 Instruction:"PREFETCHWT1 Mb" Encoding:"0x0F 0x0D /2:mem"/"M" { .Instruction = ND_INS_PREFETCHWT1, .Category = ND_CAT_PREFETCH, .IsaSet = ND_SET_PREFETCH_NOP, - .Mnemonic = 686, + .Mnemonic = 688, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -52153,6 +54131,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -52165,12 +54144,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1869 Instruction:"PSADBW Pq,Qq" Encoding:"NP 0x0F 0xF6 /r"/"RM" + // Pos:1873 Instruction:"PSADBW Pq,Qq" Encoding:"NP 0x0F 0xF6 /r"/"RM" { .Instruction = ND_INS_PSADBW, .Category = ND_CAT_MMX, .IsaSet = ND_SET_MMX, - .Mnemonic = 687, + .Mnemonic = 689, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -52179,6 +54158,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -52192,12 +54172,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1870 Instruction:"PSADBW Vx,Wx" Encoding:"0x66 0x0F 0xF6 /r"/"RM" + // Pos:1874 Instruction:"PSADBW Vx,Wx" Encoding:"0x66 0x0F 0xF6 /r"/"RM" { .Instruction = ND_INS_PSADBW, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE2, - .Mnemonic = 687, + .Mnemonic = 689, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -52206,6 +54186,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -52219,12 +54200,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1871 Instruction:"PSHUFB Pq,Qq" Encoding:"NP 0x0F 0x38 0x00 /r"/"RM" + // Pos:1875 Instruction:"PSHUFB Pq,Qq" Encoding:"NP 0x0F 0x38 0x00 /r"/"RM" { .Instruction = ND_INS_PSHUFB, .Category = ND_CAT_MMX, .IsaSet = ND_SET_SSSE3, - .Mnemonic = 688, + .Mnemonic = 690, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -52233,6 +54214,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -52246,12 +54228,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1872 Instruction:"PSHUFB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x00 /r"/"RM" + // Pos:1876 Instruction:"PSHUFB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x00 /r"/"RM" { .Instruction = ND_INS_PSHUFB, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSSE3, - .Mnemonic = 688, + .Mnemonic = 690, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -52260,6 +54242,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -52273,12 +54256,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1873 Instruction:"PSHUFD Vx,Wx,Ib" Encoding:"0x66 0x0F 0x70 /r ib"/"RMI" + // Pos:1877 Instruction:"PSHUFD Vx,Wx,Ib" Encoding:"0x66 0x0F 0x70 /r ib"/"RMI" { .Instruction = ND_INS_PSHUFD, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE2, - .Mnemonic = 689, + .Mnemonic = 691, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -52287,6 +54270,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -52301,12 +54285,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1874 Instruction:"PSHUFHW Vx,Wx,Ib" Encoding:"0xF3 0x0F 0x70 /r ib"/"RMI" + // Pos:1878 Instruction:"PSHUFHW Vx,Wx,Ib" Encoding:"0xF3 0x0F 0x70 /r ib"/"RMI" { .Instruction = ND_INS_PSHUFHW, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE2, - .Mnemonic = 690, + .Mnemonic = 692, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -52315,6 +54299,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -52329,12 +54314,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1875 Instruction:"PSHUFLW Vx,Wx,Ib" Encoding:"0xF2 0x0F 0x70 /r ib"/"RMI" + // Pos:1879 Instruction:"PSHUFLW Vx,Wx,Ib" Encoding:"0xF2 0x0F 0x70 /r ib"/"RMI" { .Instruction = ND_INS_PSHUFLW, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE2, - .Mnemonic = 691, + .Mnemonic = 693, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -52343,6 +54328,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -52357,12 +54343,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1876 Instruction:"PSHUFW Pq,Qq,Ib" Encoding:"NP 0x0F 0x70 /r ib"/"RMI" + // Pos:1880 Instruction:"PSHUFW Pq,Qq,Ib" Encoding:"NP 0x0F 0x70 /r ib"/"RMI" { .Instruction = ND_INS_PSHUFW, .Category = ND_CAT_MMX, .IsaSet = ND_SET_MMX, - .Mnemonic = 692, + .Mnemonic = 694, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -52371,6 +54357,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -52385,12 +54372,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1877 Instruction:"PSIGNB Pq,Qq" Encoding:"NP 0x0F 0x38 0x08 /r"/"RM" + // Pos:1881 Instruction:"PSIGNB Pq,Qq" Encoding:"NP 0x0F 0x38 0x08 /r"/"RM" { .Instruction = ND_INS_PSIGNB, .Category = ND_CAT_MMX, .IsaSet = ND_SET_SSSE3, - .Mnemonic = 693, + .Mnemonic = 695, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -52399,6 +54386,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -52412,12 +54400,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1878 Instruction:"PSIGNB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x08 /r"/"RM" + // Pos:1882 Instruction:"PSIGNB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x08 /r"/"RM" { .Instruction = ND_INS_PSIGNB, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSSE3, - .Mnemonic = 693, + .Mnemonic = 695, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -52426,6 +54414,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -52439,12 +54428,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1879 Instruction:"PSIGND Pq,Qq" Encoding:"NP 0x0F 0x38 0x0A /r"/"RM" + // Pos:1883 Instruction:"PSIGND Pq,Qq" Encoding:"NP 0x0F 0x38 0x0A /r"/"RM" { .Instruction = ND_INS_PSIGND, .Category = ND_CAT_MMX, .IsaSet = ND_SET_SSSE3, - .Mnemonic = 694, + .Mnemonic = 696, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -52453,6 +54442,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -52466,12 +54456,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1880 Instruction:"PSIGND Vx,Wx" Encoding:"0x66 0x0F 0x38 0x0A /r"/"RM" + // Pos:1884 Instruction:"PSIGND Vx,Wx" Encoding:"0x66 0x0F 0x38 0x0A /r"/"RM" { .Instruction = ND_INS_PSIGND, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSSE3, - .Mnemonic = 694, + .Mnemonic = 696, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -52480,6 +54470,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -52493,12 +54484,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1881 Instruction:"PSIGNW Pq,Qq" Encoding:"NP 0x0F 0x38 0x09 /r"/"RM" + // Pos:1885 Instruction:"PSIGNW Pq,Qq" Encoding:"NP 0x0F 0x38 0x09 /r"/"RM" { .Instruction = ND_INS_PSIGNW, .Category = ND_CAT_MMX, .IsaSet = ND_SET_SSSE3, - .Mnemonic = 695, + .Mnemonic = 697, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -52507,6 +54498,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -52520,12 +54512,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1882 Instruction:"PSIGNW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x09 /r"/"RM" + // Pos:1886 Instruction:"PSIGNW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x09 /r"/"RM" { .Instruction = ND_INS_PSIGNW, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSSE3, - .Mnemonic = 695, + .Mnemonic = 697, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -52534,6 +54526,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -52547,12 +54540,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1883 Instruction:"PSLLD Nq,Ib" Encoding:"NP 0x0F 0x72 /6:reg ib"/"MI" + // Pos:1887 Instruction:"PSLLD Nq,Ib" Encoding:"NP 0x0F 0x72 /6:reg ib"/"MI" { .Instruction = ND_INS_PSLLD, .Category = ND_CAT_MMX, .IsaSet = ND_SET_MMX, - .Mnemonic = 696, + .Mnemonic = 698, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -52561,6 +54554,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -52574,12 +54568,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1884 Instruction:"PSLLD Ux,Ib" Encoding:"0x66 0x0F 0x72 /6:reg ib"/"MI" + // Pos:1888 Instruction:"PSLLD Ux,Ib" Encoding:"0x66 0x0F 0x72 /6:reg ib"/"MI" { .Instruction = ND_INS_PSLLD, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE2, - .Mnemonic = 696, + .Mnemonic = 698, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -52588,6 +54582,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -52601,12 +54596,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1885 Instruction:"PSLLD Pq,Qq" Encoding:"NP 0x0F 0xF2 /r"/"RM" + // Pos:1889 Instruction:"PSLLD Pq,Qq" Encoding:"NP 0x0F 0xF2 /r"/"RM" { .Instruction = ND_INS_PSLLD, .Category = ND_CAT_MMX, .IsaSet = ND_SET_MMX, - .Mnemonic = 696, + .Mnemonic = 698, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -52615,6 +54610,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -52628,12 +54624,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1886 Instruction:"PSLLD Vx,Wx" Encoding:"0x66 0x0F 0xF2 /r"/"RM" + // Pos:1890 Instruction:"PSLLD Vx,Wx" Encoding:"0x66 0x0F 0xF2 /r"/"RM" { .Instruction = ND_INS_PSLLD, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE2, - .Mnemonic = 696, + .Mnemonic = 698, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -52642,6 +54638,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -52655,12 +54652,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1887 Instruction:"PSLLDQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /7:reg ib"/"MI" + // Pos:1891 Instruction:"PSLLDQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /7:reg ib"/"MI" { .Instruction = ND_INS_PSLLDQ, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE2, - .Mnemonic = 697, + .Mnemonic = 699, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -52669,6 +54666,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_7, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -52682,12 +54680,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1888 Instruction:"PSLLQ Nq,Ib" Encoding:"NP 0x0F 0x73 /6:reg ib"/"MI" + // Pos:1892 Instruction:"PSLLQ Nq,Ib" Encoding:"NP 0x0F 0x73 /6:reg ib"/"MI" { .Instruction = ND_INS_PSLLQ, .Category = ND_CAT_MMX, .IsaSet = ND_SET_MMX, - .Mnemonic = 698, + .Mnemonic = 700, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -52696,6 +54694,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -52709,12 +54708,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1889 Instruction:"PSLLQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /6:reg ib"/"MI" + // Pos:1893 Instruction:"PSLLQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /6:reg ib"/"MI" { .Instruction = ND_INS_PSLLQ, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE2, - .Mnemonic = 698, + .Mnemonic = 700, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -52723,6 +54722,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -52736,12 +54736,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1890 Instruction:"PSLLQ Pq,Qq" Encoding:"NP 0x0F 0xF3 /r"/"RM" + // Pos:1894 Instruction:"PSLLQ Pq,Qq" Encoding:"NP 0x0F 0xF3 /r"/"RM" { .Instruction = ND_INS_PSLLQ, .Category = ND_CAT_MMX, .IsaSet = ND_SET_MMX, - .Mnemonic = 698, + .Mnemonic = 700, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -52750,6 +54750,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -52763,12 +54764,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1891 Instruction:"PSLLQ Vx,Wx" Encoding:"0x66 0x0F 0xF3 /r"/"RM" + // Pos:1895 Instruction:"PSLLQ Vx,Wx" Encoding:"0x66 0x0F 0xF3 /r"/"RM" { .Instruction = ND_INS_PSLLQ, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE2, - .Mnemonic = 698, + .Mnemonic = 700, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -52777,6 +54778,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -52790,12 +54792,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1892 Instruction:"PSLLW Nq,Ib" Encoding:"NP 0x0F 0x71 /6:reg ib"/"MI" + // Pos:1896 Instruction:"PSLLW Nq,Ib" Encoding:"NP 0x0F 0x71 /6:reg ib"/"MI" { .Instruction = ND_INS_PSLLW, .Category = ND_CAT_MMX, .IsaSet = ND_SET_MMX, - .Mnemonic = 699, + .Mnemonic = 701, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -52804,6 +54806,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -52817,12 +54820,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1893 Instruction:"PSLLW Ux,Ib" Encoding:"0x66 0x0F 0x71 /6:reg ib"/"MI" + // Pos:1897 Instruction:"PSLLW Ux,Ib" Encoding:"0x66 0x0F 0x71 /6:reg ib"/"MI" { .Instruction = ND_INS_PSLLW, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE2, - .Mnemonic = 699, + .Mnemonic = 701, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -52831,6 +54834,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -52844,12 +54848,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1894 Instruction:"PSLLW Pq,Qq" Encoding:"NP 0x0F 0xF1 /r"/"RM" + // Pos:1898 Instruction:"PSLLW Pq,Qq" Encoding:"NP 0x0F 0xF1 /r"/"RM" { .Instruction = ND_INS_PSLLW, .Category = ND_CAT_MMX, .IsaSet = ND_SET_MMX, - .Mnemonic = 699, + .Mnemonic = 701, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -52858,6 +54862,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -52871,12 +54876,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1895 Instruction:"PSLLW Vx,Wx" Encoding:"0x66 0x0F 0xF1 /r"/"RM" + // Pos:1899 Instruction:"PSLLW Vx,Wx" Encoding:"0x66 0x0F 0xF1 /r"/"RM" { .Instruction = ND_INS_PSLLW, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE2, - .Mnemonic = 699, + .Mnemonic = 701, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -52885,6 +54890,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -52898,12 +54904,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1896 Instruction:"PSMASH" Encoding:"0xF3 0x0F 0x01 /0xFF"/"" + // Pos:1900 Instruction:"PSMASH" Encoding:"0xF3 0x0F 0x01 /0xFF"/"" { .Instruction = ND_INS_PSMASH, .Category = ND_CAT_SYSTEM, .IsaSet = ND_SET_SNP, - .Mnemonic = 700, + .Mnemonic = 702, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -52912,6 +54918,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_OF|NDR_RFLAG_ZF|NDR_RFLAG_AF|NDR_RFLAG_PF|NDR_RFLAG_SF, .SetFlags = 0, @@ -52925,12 +54932,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1897 Instruction:"PSRAD Nq,Ib" Encoding:"NP 0x0F 0x72 /4:reg ib"/"MI" + // Pos:1901 Instruction:"PSRAD Nq,Ib" Encoding:"NP 0x0F 0x72 /4:reg ib"/"MI" { .Instruction = ND_INS_PSRAD, .Category = ND_CAT_MMX, .IsaSet = ND_SET_MMX, - .Mnemonic = 701, + .Mnemonic = 703, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -52939,6 +54946,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -52952,12 +54960,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1898 Instruction:"PSRAD Ux,Ib" Encoding:"0x66 0x0F 0x72 /4:reg ib"/"MI" + // Pos:1902 Instruction:"PSRAD Ux,Ib" Encoding:"0x66 0x0F 0x72 /4:reg ib"/"MI" { .Instruction = ND_INS_PSRAD, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE2, - .Mnemonic = 701, + .Mnemonic = 703, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -52966,6 +54974,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -52979,12 +54988,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1899 Instruction:"PSRAD Pq,Qq" Encoding:"NP 0x0F 0xE2 /r"/"RM" + // Pos:1903 Instruction:"PSRAD Pq,Qq" Encoding:"NP 0x0F 0xE2 /r"/"RM" { .Instruction = ND_INS_PSRAD, .Category = ND_CAT_MMX, .IsaSet = ND_SET_MMX, - .Mnemonic = 701, + .Mnemonic = 703, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -52993,6 +55002,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -53006,12 +55016,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1900 Instruction:"PSRAD Vx,Wx" Encoding:"0x66 0x0F 0xE2 /r"/"RM" + // Pos:1904 Instruction:"PSRAD Vx,Wx" Encoding:"0x66 0x0F 0xE2 /r"/"RM" { .Instruction = ND_INS_PSRAD, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE2, - .Mnemonic = 701, + .Mnemonic = 703, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -53020,6 +55030,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -53033,12 +55044,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1901 Instruction:"PSRAW Nq,Ib" Encoding:"NP 0x0F 0x71 /4:reg ib"/"MI" + // Pos:1905 Instruction:"PSRAW Nq,Ib" Encoding:"NP 0x0F 0x71 /4:reg ib"/"MI" { .Instruction = ND_INS_PSRAW, .Category = ND_CAT_MMX, .IsaSet = ND_SET_MMX, - .Mnemonic = 702, + .Mnemonic = 704, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -53047,6 +55058,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -53060,12 +55072,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1902 Instruction:"PSRAW Ux,Ib" Encoding:"0x66 0x0F 0x71 /4:reg ib"/"MI" + // Pos:1906 Instruction:"PSRAW Ux,Ib" Encoding:"0x66 0x0F 0x71 /4:reg ib"/"MI" { .Instruction = ND_INS_PSRAW, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE2, - .Mnemonic = 702, + .Mnemonic = 704, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -53074,6 +55086,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -53087,12 +55100,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1903 Instruction:"PSRAW Pq,Qq" Encoding:"NP 0x0F 0xE1 /r"/"RM" + // Pos:1907 Instruction:"PSRAW Pq,Qq" Encoding:"NP 0x0F 0xE1 /r"/"RM" { .Instruction = ND_INS_PSRAW, .Category = ND_CAT_MMX, .IsaSet = ND_SET_MMX, - .Mnemonic = 702, + .Mnemonic = 704, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -53101,6 +55114,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -53114,12 +55128,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1904 Instruction:"PSRAW Vx,Wx" Encoding:"0x66 0x0F 0xE1 /r"/"RM" + // Pos:1908 Instruction:"PSRAW Vx,Wx" Encoding:"0x66 0x0F 0xE1 /r"/"RM" { .Instruction = ND_INS_PSRAW, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE2, - .Mnemonic = 702, + .Mnemonic = 704, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -53128,6 +55142,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -53141,12 +55156,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1905 Instruction:"PSRLD Nq,Ib" Encoding:"NP 0x0F 0x72 /2:reg ib"/"MI" + // Pos:1909 Instruction:"PSRLD Nq,Ib" Encoding:"NP 0x0F 0x72 /2:reg ib"/"MI" { .Instruction = ND_INS_PSRLD, .Category = ND_CAT_MMX, .IsaSet = ND_SET_MMX, - .Mnemonic = 703, + .Mnemonic = 705, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -53155,6 +55170,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -53168,12 +55184,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1906 Instruction:"PSRLD Ux,Ib" Encoding:"0x66 0x0F 0x72 /2:reg ib"/"MI" + // Pos:1910 Instruction:"PSRLD Ux,Ib" Encoding:"0x66 0x0F 0x72 /2:reg ib"/"MI" { .Instruction = ND_INS_PSRLD, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE2, - .Mnemonic = 703, + .Mnemonic = 705, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -53182,6 +55198,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -53195,12 +55212,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1907 Instruction:"PSRLD Pq,Qq" Encoding:"NP 0x0F 0xD2 /r"/"RM" + // Pos:1911 Instruction:"PSRLD Pq,Qq" Encoding:"NP 0x0F 0xD2 /r"/"RM" { .Instruction = ND_INS_PSRLD, .Category = ND_CAT_MMX, .IsaSet = ND_SET_MMX, - .Mnemonic = 703, + .Mnemonic = 705, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -53209,6 +55226,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -53222,12 +55240,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1908 Instruction:"PSRLD Vx,Wx" Encoding:"0x66 0x0F 0xD2 /r"/"RM" + // Pos:1912 Instruction:"PSRLD Vx,Wx" Encoding:"0x66 0x0F 0xD2 /r"/"RM" { .Instruction = ND_INS_PSRLD, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE2, - .Mnemonic = 703, + .Mnemonic = 705, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -53236,6 +55254,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -53249,12 +55268,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1909 Instruction:"PSRLDQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /3:reg ib"/"MI" + // Pos:1913 Instruction:"PSRLDQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /3:reg ib"/"MI" { .Instruction = ND_INS_PSRLDQ, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE2, - .Mnemonic = 704, + .Mnemonic = 706, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -53263,6 +55282,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_7, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -53276,12 +55296,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1910 Instruction:"PSRLQ Nq,Ib" Encoding:"NP 0x0F 0x73 /2:reg ib"/"MI" + // Pos:1914 Instruction:"PSRLQ Nq,Ib" Encoding:"NP 0x0F 0x73 /2:reg ib"/"MI" { .Instruction = ND_INS_PSRLQ, .Category = ND_CAT_MMX, .IsaSet = ND_SET_MMX, - .Mnemonic = 705, + .Mnemonic = 707, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -53290,6 +55310,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -53303,12 +55324,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1911 Instruction:"PSRLQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /2:reg ib"/"MI" + // Pos:1915 Instruction:"PSRLQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /2:reg ib"/"MI" { .Instruction = ND_INS_PSRLQ, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE2, - .Mnemonic = 705, + .Mnemonic = 707, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -53317,6 +55338,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -53330,12 +55352,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1912 Instruction:"PSRLQ Pq,Qq" Encoding:"NP 0x0F 0xD3 /r"/"RM" + // Pos:1916 Instruction:"PSRLQ Pq,Qq" Encoding:"NP 0x0F 0xD3 /r"/"RM" { .Instruction = ND_INS_PSRLQ, .Category = ND_CAT_MMX, .IsaSet = ND_SET_MMX, - .Mnemonic = 705, + .Mnemonic = 707, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -53344,6 +55366,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -53357,12 +55380,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1913 Instruction:"PSRLQ Vx,Wx" Encoding:"0x66 0x0F 0xD3 /r"/"RM" + // Pos:1917 Instruction:"PSRLQ Vx,Wx" Encoding:"0x66 0x0F 0xD3 /r"/"RM" { .Instruction = ND_INS_PSRLQ, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE2, - .Mnemonic = 705, + .Mnemonic = 707, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -53371,6 +55394,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -53384,12 +55408,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1914 Instruction:"PSRLW Nq,Ib" Encoding:"NP 0x0F 0x71 /2:reg ib"/"MI" + // Pos:1918 Instruction:"PSRLW Nq,Ib" Encoding:"NP 0x0F 0x71 /2:reg ib"/"MI" { .Instruction = ND_INS_PSRLW, .Category = ND_CAT_MMX, .IsaSet = ND_SET_MMX, - .Mnemonic = 706, + .Mnemonic = 708, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -53398,6 +55422,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -53411,12 +55436,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1915 Instruction:"PSRLW Ux,Ib" Encoding:"0x66 0x0F 0x71 /2:reg ib"/"MI" + // Pos:1919 Instruction:"PSRLW Ux,Ib" Encoding:"0x66 0x0F 0x71 /2:reg ib"/"MI" { .Instruction = ND_INS_PSRLW, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE2, - .Mnemonic = 706, + .Mnemonic = 708, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -53425,6 +55450,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -53438,12 +55464,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1916 Instruction:"PSRLW Pq,Qq" Encoding:"NP 0x0F 0xD1 /r"/"RM" + // Pos:1920 Instruction:"PSRLW Pq,Qq" Encoding:"NP 0x0F 0xD1 /r"/"RM" { .Instruction = ND_INS_PSRLW, .Category = ND_CAT_MMX, .IsaSet = ND_SET_MMX, - .Mnemonic = 706, + .Mnemonic = 708, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -53452,6 +55478,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -53465,12 +55492,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1917 Instruction:"PSRLW Vx,Wx" Encoding:"0x66 0x0F 0xD1 /r"/"RM" + // Pos:1921 Instruction:"PSRLW Vx,Wx" Encoding:"0x66 0x0F 0xD1 /r"/"RM" { .Instruction = ND_INS_PSRLW, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE2, - .Mnemonic = 706, + .Mnemonic = 708, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -53479,6 +55506,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -53492,12 +55520,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1918 Instruction:"PSUBB Pq,Qq" Encoding:"NP 0x0F 0xF8 /r"/"RM" + // Pos:1922 Instruction:"PSUBB Pq,Qq" Encoding:"NP 0x0F 0xF8 /r"/"RM" { .Instruction = ND_INS_PSUBB, .Category = ND_CAT_MMX, .IsaSet = ND_SET_MMX, - .Mnemonic = 707, + .Mnemonic = 709, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -53506,6 +55534,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -53519,12 +55548,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1919 Instruction:"PSUBB Vx,Wx" Encoding:"0x66 0x0F 0xF8 /r"/"RM" + // Pos:1923 Instruction:"PSUBB Vx,Wx" Encoding:"0x66 0x0F 0xF8 /r"/"RM" { .Instruction = ND_INS_PSUBB, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE2, - .Mnemonic = 707, + .Mnemonic = 709, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -53533,6 +55562,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -53546,12 +55576,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1920 Instruction:"PSUBD Pq,Qq" Encoding:"NP 0x0F 0xFA /r"/"RM" + // Pos:1924 Instruction:"PSUBD Pq,Qq" Encoding:"NP 0x0F 0xFA /r"/"RM" { .Instruction = ND_INS_PSUBD, .Category = ND_CAT_MMX, .IsaSet = ND_SET_MMX, - .Mnemonic = 708, + .Mnemonic = 710, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -53560,6 +55590,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -53573,12 +55604,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1921 Instruction:"PSUBD Vx,Wx" Encoding:"0x66 0x0F 0xFA /r"/"RM" + // Pos:1925 Instruction:"PSUBD Vx,Wx" Encoding:"0x66 0x0F 0xFA /r"/"RM" { .Instruction = ND_INS_PSUBD, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE2, - .Mnemonic = 708, + .Mnemonic = 710, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -53587,6 +55618,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -53600,12 +55632,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1922 Instruction:"PSUBQ Pq,Qq" Encoding:"NP 0x0F 0xFB /r"/"RM" + // Pos:1926 Instruction:"PSUBQ Pq,Qq" Encoding:"NP 0x0F 0xFB /r"/"RM" { .Instruction = ND_INS_PSUBQ, .Category = ND_CAT_MMX, .IsaSet = ND_SET_MMX, - .Mnemonic = 709, + .Mnemonic = 711, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -53614,6 +55646,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -53627,12 +55660,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1923 Instruction:"PSUBQ Vx,Wx" Encoding:"0x66 0x0F 0xFB /r"/"RM" + // Pos:1927 Instruction:"PSUBQ Vx,Wx" Encoding:"0x66 0x0F 0xFB /r"/"RM" { .Instruction = ND_INS_PSUBQ, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE2, - .Mnemonic = 709, + .Mnemonic = 711, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -53641,6 +55674,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -53654,12 +55688,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1924 Instruction:"PSUBSB Pq,Qq" Encoding:"NP 0x0F 0xE8 /r"/"RM" + // Pos:1928 Instruction:"PSUBSB Pq,Qq" Encoding:"NP 0x0F 0xE8 /r"/"RM" { .Instruction = ND_INS_PSUBSB, .Category = ND_CAT_MMX, .IsaSet = ND_SET_MMX, - .Mnemonic = 710, + .Mnemonic = 712, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -53668,6 +55702,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -53681,12 +55716,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1925 Instruction:"PSUBSB Vx,Wx" Encoding:"0x66 0x0F 0xE8 /r"/"RM" + // Pos:1929 Instruction:"PSUBSB Vx,Wx" Encoding:"0x66 0x0F 0xE8 /r"/"RM" { .Instruction = ND_INS_PSUBSB, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE2, - .Mnemonic = 710, + .Mnemonic = 712, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -53695,6 +55730,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -53708,12 +55744,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1926 Instruction:"PSUBSW Pq,Qq" Encoding:"NP 0x0F 0xE9 /r"/"RM" + // Pos:1930 Instruction:"PSUBSW Pq,Qq" Encoding:"NP 0x0F 0xE9 /r"/"RM" { .Instruction = ND_INS_PSUBSW, .Category = ND_CAT_MMX, .IsaSet = ND_SET_MMX, - .Mnemonic = 711, + .Mnemonic = 713, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -53722,6 +55758,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -53735,12 +55772,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1927 Instruction:"PSUBSW Vx,Wx" Encoding:"0x66 0x0F 0xE9 /r"/"RM" + // Pos:1931 Instruction:"PSUBSW Vx,Wx" Encoding:"0x66 0x0F 0xE9 /r"/"RM" { .Instruction = ND_INS_PSUBSW, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE2, - .Mnemonic = 711, + .Mnemonic = 713, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -53749,6 +55786,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -53762,12 +55800,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1928 Instruction:"PSUBUSB Pq,Qq" Encoding:"NP 0x0F 0xD8 /r"/"RM" + // Pos:1932 Instruction:"PSUBUSB Pq,Qq" Encoding:"NP 0x0F 0xD8 /r"/"RM" { .Instruction = ND_INS_PSUBUSB, .Category = ND_CAT_MMX, .IsaSet = ND_SET_MMX, - .Mnemonic = 712, + .Mnemonic = 714, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -53776,6 +55814,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -53789,12 +55828,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1929 Instruction:"PSUBUSB Vx,Wx" Encoding:"0x66 0x0F 0xD8 /r"/"RM" + // Pos:1933 Instruction:"PSUBUSB Vx,Wx" Encoding:"0x66 0x0F 0xD8 /r"/"RM" { .Instruction = ND_INS_PSUBUSB, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE2, - .Mnemonic = 712, + .Mnemonic = 714, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -53803,6 +55842,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -53816,12 +55856,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1930 Instruction:"PSUBUSW Pq,Qq" Encoding:"NP 0x0F 0xD9 /r"/"RM" + // Pos:1934 Instruction:"PSUBUSW Pq,Qq" Encoding:"NP 0x0F 0xD9 /r"/"RM" { .Instruction = ND_INS_PSUBUSW, .Category = ND_CAT_MMX, .IsaSet = ND_SET_MMX, - .Mnemonic = 713, + .Mnemonic = 715, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -53830,6 +55870,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -53843,12 +55884,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1931 Instruction:"PSUBUSW Vx,Wx" Encoding:"0x66 0x0F 0xD9 /r"/"RM" + // Pos:1935 Instruction:"PSUBUSW Vx,Wx" Encoding:"0x66 0x0F 0xD9 /r"/"RM" { .Instruction = ND_INS_PSUBUSW, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE2, - .Mnemonic = 713, + .Mnemonic = 715, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -53857,6 +55898,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -53870,12 +55912,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1932 Instruction:"PSUBW Pq,Qq" Encoding:"NP 0x0F 0xF9 /r"/"RM" + // Pos:1936 Instruction:"PSUBW Pq,Qq" Encoding:"NP 0x0F 0xF9 /r"/"RM" { .Instruction = ND_INS_PSUBW, .Category = ND_CAT_MMX, .IsaSet = ND_SET_MMX, - .Mnemonic = 714, + .Mnemonic = 716, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -53884,6 +55926,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -53897,12 +55940,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1933 Instruction:"PSUBW Vx,Wx" Encoding:"0x66 0x0F 0xF9 /r"/"RM" + // Pos:1937 Instruction:"PSUBW Vx,Wx" Encoding:"0x66 0x0F 0xF9 /r"/"RM" { .Instruction = ND_INS_PSUBW, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE2, - .Mnemonic = 714, + .Mnemonic = 716, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -53911,6 +55954,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -53924,12 +55968,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1934 Instruction:"PSWAPD Pq,Qq" Encoding:"0x0F 0x0F /r 0xBB"/"RM" + // Pos:1938 Instruction:"PSWAPD Pq,Qq" Encoding:"0x0F 0x0F /r 0xBB"/"RM" { .Instruction = ND_INS_PSWAPD, .Category = ND_CAT_3DNOW, .IsaSet = ND_SET_3DNOW, - .Mnemonic = 715, + .Mnemonic = 717, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -53938,6 +55982,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -53951,12 +55996,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1935 Instruction:"PTEST Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x17 /r"/"RM" + // Pos:1939 Instruction:"PTEST Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x17 /r"/"RM" { .Instruction = ND_INS_PTEST, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE4, - .Mnemonic = 716, + .Mnemonic = 718, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -53965,6 +56010,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .SetFlags = 0, @@ -53979,12 +56025,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1936 Instruction:"PTWRITE Ey" Encoding:"0xF3 0x0F 0xAE /4"/"M" + // Pos:1940 Instruction:"PTWRITE Ey" Encoding:"0xF3 0x0F 0xAE /4"/"M" { .Instruction = ND_INS_PTWRITE, .Category = ND_CAT_PTWRITE, .IsaSet = ND_SET_PTWRITE, - .Mnemonic = 717, + .Mnemonic = 719, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -53993,6 +56039,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -54005,12 +56052,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1937 Instruction:"PUNPCKHBW Pq,Qq" Encoding:"NP 0x0F 0x68 /r"/"RM" + // Pos:1941 Instruction:"PUNPCKHBW Pq,Qq" Encoding:"NP 0x0F 0x68 /r"/"RM" { .Instruction = ND_INS_PUNPCKHBW, .Category = ND_CAT_MMX, .IsaSet = ND_SET_MMX, - .Mnemonic = 718, + .Mnemonic = 720, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -54019,6 +56066,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -54032,12 +56080,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1938 Instruction:"PUNPCKHBW Vx,Wx" Encoding:"0x66 0x0F 0x68 /r"/"RM" + // Pos:1942 Instruction:"PUNPCKHBW Vx,Wx" Encoding:"0x66 0x0F 0x68 /r"/"RM" { .Instruction = ND_INS_PUNPCKHBW, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE2, - .Mnemonic = 718, + .Mnemonic = 720, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -54046,6 +56094,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -54059,12 +56108,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1939 Instruction:"PUNPCKHDQ Pq,Qq" Encoding:"NP 0x0F 0x6A /r"/"RM" + // Pos:1943 Instruction:"PUNPCKHDQ Pq,Qq" Encoding:"NP 0x0F 0x6A /r"/"RM" { .Instruction = ND_INS_PUNPCKHDQ, .Category = ND_CAT_MMX, .IsaSet = ND_SET_MMX, - .Mnemonic = 719, + .Mnemonic = 721, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -54073,6 +56122,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -54086,12 +56136,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1940 Instruction:"PUNPCKHDQ Vx,Wx" Encoding:"0x66 0x0F 0x6A /r"/"RM" + // Pos:1944 Instruction:"PUNPCKHDQ Vx,Wx" Encoding:"0x66 0x0F 0x6A /r"/"RM" { .Instruction = ND_INS_PUNPCKHDQ, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE2, - .Mnemonic = 719, + .Mnemonic = 721, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -54100,6 +56150,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -54113,12 +56164,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1941 Instruction:"PUNPCKHQDQ Vx,Wx" Encoding:"0x66 0x0F 0x6D /r"/"RM" + // Pos:1945 Instruction:"PUNPCKHQDQ Vx,Wx" Encoding:"0x66 0x0F 0x6D /r"/"RM" { .Instruction = ND_INS_PUNPCKHQDQ, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE2, - .Mnemonic = 720, + .Mnemonic = 722, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -54127,6 +56178,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -54140,12 +56192,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1942 Instruction:"PUNPCKHWD Pq,Qq" Encoding:"NP 0x0F 0x69 /r"/"RM" + // Pos:1946 Instruction:"PUNPCKHWD Pq,Qq" Encoding:"NP 0x0F 0x69 /r"/"RM" { .Instruction = ND_INS_PUNPCKHWD, .Category = ND_CAT_MMX, .IsaSet = ND_SET_MMX, - .Mnemonic = 721, + .Mnemonic = 723, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -54154,6 +56206,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -54167,12 +56220,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1943 Instruction:"PUNPCKHWD Vx,Wx" Encoding:"0x66 0x0F 0x69 /r"/"RM" + // Pos:1947 Instruction:"PUNPCKHWD Vx,Wx" Encoding:"0x66 0x0F 0x69 /r"/"RM" { .Instruction = ND_INS_PUNPCKHWD, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE2, - .Mnemonic = 721, + .Mnemonic = 723, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -54181,6 +56234,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -54194,12 +56248,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1944 Instruction:"PUNPCKLBW Pq,Qd" Encoding:"NP 0x0F 0x60 /r"/"RM" + // Pos:1948 Instruction:"PUNPCKLBW Pq,Qd" Encoding:"NP 0x0F 0x60 /r"/"RM" { .Instruction = ND_INS_PUNPCKLBW, .Category = ND_CAT_MMX, .IsaSet = ND_SET_MMX, - .Mnemonic = 722, + .Mnemonic = 724, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -54208,6 +56262,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -54221,12 +56276,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1945 Instruction:"PUNPCKLBW Vx,Wx" Encoding:"0x66 0x0F 0x60 /r"/"RM" + // Pos:1949 Instruction:"PUNPCKLBW Vx,Wx" Encoding:"0x66 0x0F 0x60 /r"/"RM" { .Instruction = ND_INS_PUNPCKLBW, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE2, - .Mnemonic = 722, + .Mnemonic = 724, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -54235,6 +56290,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -54248,12 +56304,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1946 Instruction:"PUNPCKLDQ Pq,Qd" Encoding:"NP 0x0F 0x62 /r"/"RM" + // Pos:1950 Instruction:"PUNPCKLDQ Pq,Qd" Encoding:"NP 0x0F 0x62 /r"/"RM" { .Instruction = ND_INS_PUNPCKLDQ, .Category = ND_CAT_MMX, .IsaSet = ND_SET_MMX, - .Mnemonic = 723, + .Mnemonic = 725, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -54262,6 +56318,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -54275,12 +56332,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1947 Instruction:"PUNPCKLDQ Vx,Wx" Encoding:"0x66 0x0F 0x62 /r"/"RM" + // Pos:1951 Instruction:"PUNPCKLDQ Vx,Wx" Encoding:"0x66 0x0F 0x62 /r"/"RM" { .Instruction = ND_INS_PUNPCKLDQ, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE2, - .Mnemonic = 723, + .Mnemonic = 725, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -54289,6 +56346,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -54302,12 +56360,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1948 Instruction:"PUNPCKLQDQ Vx,Wx" Encoding:"0x66 0x0F 0x6C /r"/"RM" + // Pos:1952 Instruction:"PUNPCKLQDQ Vx,Wx" Encoding:"0x66 0x0F 0x6C /r"/"RM" { .Instruction = ND_INS_PUNPCKLQDQ, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE2, - .Mnemonic = 724, + .Mnemonic = 726, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -54316,6 +56374,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -54329,12 +56388,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1949 Instruction:"PUNPCKLWD Pq,Qd" Encoding:"NP 0x0F 0x61 /r"/"RM" + // Pos:1953 Instruction:"PUNPCKLWD Pq,Qd" Encoding:"NP 0x0F 0x61 /r"/"RM" { .Instruction = ND_INS_PUNPCKLWD, .Category = ND_CAT_MMX, .IsaSet = ND_SET_MMX, - .Mnemonic = 725, + .Mnemonic = 727, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -54343,6 +56402,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -54356,12 +56416,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1950 Instruction:"PUNPCKLWD Vx,Wx" Encoding:"0x66 0x0F 0x61 /r"/"RM" + // Pos:1954 Instruction:"PUNPCKLWD Vx,Wx" Encoding:"0x66 0x0F 0x61 /r"/"RM" { .Instruction = ND_INS_PUNPCKLWD, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE2, - .Mnemonic = 725, + .Mnemonic = 727, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -54370,6 +56430,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -54383,12 +56444,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1951 Instruction:"PUSH ES" Encoding:"0x06"/"" + // Pos:1955 Instruction:"PUSH ES" Encoding:"0x06"/"" { .Instruction = ND_INS_PUSH, .Category = ND_CAT_PUSH, .IsaSet = ND_SET_I86, - .Mnemonic = 726, + .Mnemonic = 728, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -54397,6 +56458,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -54410,12 +56472,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1952 Instruction:"PUSH CS" Encoding:"0x0E"/"" + // Pos:1956 Instruction:"PUSH CS" Encoding:"0x0E"/"" { .Instruction = ND_INS_PUSH, .Category = ND_CAT_PUSH, .IsaSet = ND_SET_I86, - .Mnemonic = 726, + .Mnemonic = 728, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -54424,6 +56486,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -54437,12 +56500,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1953 Instruction:"PUSH SS" Encoding:"0x16"/"" + // Pos:1957 Instruction:"PUSH SS" Encoding:"0x16"/"" { .Instruction = ND_INS_PUSH, .Category = ND_CAT_PUSH, .IsaSet = ND_SET_I86, - .Mnemonic = 726, + .Mnemonic = 728, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -54451,6 +56514,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -54464,12 +56528,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1954 Instruction:"PUSH DS" Encoding:"0x1E"/"" + // Pos:1958 Instruction:"PUSH DS" Encoding:"0x1E"/"" { .Instruction = ND_INS_PUSH, .Category = ND_CAT_PUSH, .IsaSet = ND_SET_I86, - .Mnemonic = 726, + .Mnemonic = 728, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -54478,6 +56542,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -54491,12 +56556,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1955 Instruction:"PUSH Zv" Encoding:"0x50"/"O" + // Pos:1959 Instruction:"PUSH Zv" Encoding:"0x50"/"O" { .Instruction = ND_INS_PUSH, .Category = ND_CAT_PUSH, .IsaSet = ND_SET_I86, - .Mnemonic = 726, + .Mnemonic = 728, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -54505,6 +56570,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -54518,12 +56584,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1956 Instruction:"PUSH Zv" Encoding:"0x51"/"O" + // Pos:1960 Instruction:"PUSH Zv" Encoding:"0x51"/"O" { .Instruction = ND_INS_PUSH, .Category = ND_CAT_PUSH, .IsaSet = ND_SET_I86, - .Mnemonic = 726, + .Mnemonic = 728, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -54532,6 +56598,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -54545,12 +56612,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1957 Instruction:"PUSH Zv" Encoding:"0x52"/"O" + // Pos:1961 Instruction:"PUSH Zv" Encoding:"0x52"/"O" { .Instruction = ND_INS_PUSH, .Category = ND_CAT_PUSH, .IsaSet = ND_SET_I86, - .Mnemonic = 726, + .Mnemonic = 728, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -54559,6 +56626,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -54572,12 +56640,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1958 Instruction:"PUSH Zv" Encoding:"0x53"/"O" + // Pos:1962 Instruction:"PUSH Zv" Encoding:"0x53"/"O" { .Instruction = ND_INS_PUSH, .Category = ND_CAT_PUSH, .IsaSet = ND_SET_I86, - .Mnemonic = 726, + .Mnemonic = 728, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -54586,6 +56654,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -54599,12 +56668,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1959 Instruction:"PUSH Zv" Encoding:"0x54"/"O" + // Pos:1963 Instruction:"PUSH Zv" Encoding:"0x54"/"O" { .Instruction = ND_INS_PUSH, .Category = ND_CAT_PUSH, .IsaSet = ND_SET_I86, - .Mnemonic = 726, + .Mnemonic = 728, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -54613,6 +56682,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -54626,12 +56696,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1960 Instruction:"PUSH Zv" Encoding:"0x55"/"O" + // Pos:1964 Instruction:"PUSH Zv" Encoding:"0x55"/"O" { .Instruction = ND_INS_PUSH, .Category = ND_CAT_PUSH, .IsaSet = ND_SET_I86, - .Mnemonic = 726, + .Mnemonic = 728, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -54640,6 +56710,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -54653,12 +56724,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1961 Instruction:"PUSH Zv" Encoding:"0x56"/"O" + // Pos:1965 Instruction:"PUSH Zv" Encoding:"0x56"/"O" { .Instruction = ND_INS_PUSH, .Category = ND_CAT_PUSH, .IsaSet = ND_SET_I86, - .Mnemonic = 726, + .Mnemonic = 728, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -54667,6 +56738,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -54680,12 +56752,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1962 Instruction:"PUSH Zv" Encoding:"0x57"/"O" + // Pos:1966 Instruction:"PUSH Zv" Encoding:"0x57"/"O" { .Instruction = ND_INS_PUSH, .Category = ND_CAT_PUSH, .IsaSet = ND_SET_I86, - .Mnemonic = 726, + .Mnemonic = 728, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -54694,6 +56766,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -54707,12 +56780,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1963 Instruction:"PUSH Iz" Encoding:"0x68 iz"/"I" + // Pos:1967 Instruction:"PUSH Iz" Encoding:"0x68 iz"/"I" { .Instruction = ND_INS_PUSH, .Category = ND_CAT_PUSH, .IsaSet = ND_SET_I86, - .Mnemonic = 726, + .Mnemonic = 728, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -54721,6 +56794,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -54734,12 +56808,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1964 Instruction:"PUSH Ib" Encoding:"0x6A ib"/"I" + // Pos:1968 Instruction:"PUSH Ib" Encoding:"0x6A ib"/"I" { .Instruction = ND_INS_PUSH, .Category = ND_CAT_PUSH, .IsaSet = ND_SET_I86, - .Mnemonic = 726, + .Mnemonic = 728, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -54748,6 +56822,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -54761,12 +56836,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1965 Instruction:"PUSH Ev" Encoding:"0xFF /6"/"M" + // Pos:1969 Instruction:"PUSH Ev" Encoding:"0xFF /6"/"M" { .Instruction = ND_INS_PUSH, .Category = ND_CAT_PUSH, .IsaSet = ND_SET_I86, - .Mnemonic = 726, + .Mnemonic = 728, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -54775,6 +56850,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -54788,12 +56864,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1966 Instruction:"PUSH FS" Encoding:"0x0F 0xA0"/"" + // Pos:1970 Instruction:"PUSH FS" Encoding:"0x0F 0xA0"/"" { .Instruction = ND_INS_PUSH, .Category = ND_CAT_PUSH, .IsaSet = ND_SET_I86, - .Mnemonic = 726, + .Mnemonic = 728, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -54802,6 +56878,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -54815,12 +56892,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1967 Instruction:"PUSH GS" Encoding:"0x0F 0xA8"/"" + // Pos:1971 Instruction:"PUSH GS" Encoding:"0x0F 0xA8"/"" { .Instruction = ND_INS_PUSH, .Category = ND_CAT_PUSH, .IsaSet = ND_SET_I86, - .Mnemonic = 726, + .Mnemonic = 728, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -54829,6 +56906,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -54842,12 +56920,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1968 Instruction:"PUSH2 Bv,Rv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 w:0 0xFF /6:reg"/"VM" + // Pos:1972 Instruction:"PUSH2 Bv,Rv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 w:0 0xFF /6:reg"/"VM" { .Instruction = ND_INS_PUSH2, .Category = ND_CAT_PUSH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 727, + .Mnemonic = 729, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -54856,6 +56934,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_PP2, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -54870,12 +56949,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1969 Instruction:"PUSH2P Bv,Rv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 w:1 0xFF /6:reg"/"VM" + // Pos:1973 Instruction:"PUSH2P Bv,Rv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 w:1 0xFF /6:reg"/"VM" { .Instruction = ND_INS_PUSH2P, .Category = ND_CAT_PUSH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 728, + .Mnemonic = 730, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -54884,6 +56963,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_PP2, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -54898,12 +56978,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1970 Instruction:"PUSHA" Encoding:"ds16 0x60"/"" + // Pos:1974 Instruction:"PUSHA" Encoding:"ds16 0x60"/"" { .Instruction = ND_INS_PUSHA, .Category = ND_CAT_PUSH, .IsaSet = ND_SET_I386, - .Mnemonic = 729, + .Mnemonic = 731, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -54912,6 +56992,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -54925,12 +57006,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1971 Instruction:"PUSHAD" Encoding:"ds32 0x60"/"" + // Pos:1975 Instruction:"PUSHAD" Encoding:"ds32 0x60"/"" { .Instruction = ND_INS_PUSHAD, .Category = ND_CAT_PUSH, .IsaSet = ND_SET_I386, - .Mnemonic = 730, + .Mnemonic = 732, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -54939,6 +57020,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -54952,12 +57034,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1972 Instruction:"PUSHFD Fv" Encoding:"ds32 0x9C"/"" + // Pos:1976 Instruction:"PUSHFD Fv" Encoding:"ds32 0x9C"/"" { .Instruction = ND_INS_PUSHF, .Category = ND_CAT_PUSH, .IsaSet = ND_SET_I86, - .Mnemonic = 731, + .Mnemonic = 733, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -54966,6 +57048,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -54979,12 +57062,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1973 Instruction:"PUSHFQ Fv" Encoding:"dds64 0x9C"/"" + // Pos:1977 Instruction:"PUSHFQ Fv" Encoding:"dds64 0x9C"/"" { .Instruction = ND_INS_PUSHF, .Category = ND_CAT_PUSH, .IsaSet = ND_SET_I86, - .Mnemonic = 732, + .Mnemonic = 734, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -54993,6 +57076,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -55006,12 +57090,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1974 Instruction:"PUSHFW Fv" Encoding:"ds16 0x9C"/"" + // Pos:1978 Instruction:"PUSHFW Fv" Encoding:"ds16 0x9C"/"" { .Instruction = ND_INS_PUSHF, .Category = ND_CAT_PUSH, .IsaSet = ND_SET_I86, - .Mnemonic = 733, + .Mnemonic = 735, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -55020,6 +57104,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -55033,12 +57118,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1975 Instruction:"PUSHP Zv" Encoding:"rex2w 0x50"/"O" + // Pos:1979 Instruction:"PUSHP Zv" Encoding:"rex2w 0x50"/"O" { .Instruction = ND_INS_PUSHP, .Category = ND_CAT_PUSH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 734, + .Mnemonic = 736, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -55047,6 +57132,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -55060,12 +57146,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1976 Instruction:"PUSHP Zv" Encoding:"rex2w 0x51"/"O" + // Pos:1980 Instruction:"PUSHP Zv" Encoding:"rex2w 0x51"/"O" { .Instruction = ND_INS_PUSHP, .Category = ND_CAT_PUSH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 734, + .Mnemonic = 736, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -55074,6 +57160,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -55087,12 +57174,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1977 Instruction:"PUSHP Zv" Encoding:"rex2w 0x52"/"O" + // Pos:1981 Instruction:"PUSHP Zv" Encoding:"rex2w 0x52"/"O" { .Instruction = ND_INS_PUSHP, .Category = ND_CAT_PUSH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 734, + .Mnemonic = 736, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -55101,6 +57188,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -55114,12 +57202,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1978 Instruction:"PUSHP Zv" Encoding:"rex2w 0x53"/"O" + // Pos:1982 Instruction:"PUSHP Zv" Encoding:"rex2w 0x53"/"O" { .Instruction = ND_INS_PUSHP, .Category = ND_CAT_PUSH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 734, + .Mnemonic = 736, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -55128,6 +57216,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -55141,12 +57230,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1979 Instruction:"PUSHP Zv" Encoding:"rex2w 0x54"/"O" + // Pos:1983 Instruction:"PUSHP Zv" Encoding:"rex2w 0x54"/"O" { .Instruction = ND_INS_PUSHP, .Category = ND_CAT_PUSH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 734, + .Mnemonic = 736, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -55155,6 +57244,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -55168,12 +57258,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1980 Instruction:"PUSHP Zv" Encoding:"rex2w 0x55"/"O" + // Pos:1984 Instruction:"PUSHP Zv" Encoding:"rex2w 0x55"/"O" { .Instruction = ND_INS_PUSHP, .Category = ND_CAT_PUSH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 734, + .Mnemonic = 736, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -55182,6 +57272,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -55195,12 +57286,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1981 Instruction:"PUSHP Zv" Encoding:"rex2w 0x56"/"O" + // Pos:1985 Instruction:"PUSHP Zv" Encoding:"rex2w 0x56"/"O" { .Instruction = ND_INS_PUSHP, .Category = ND_CAT_PUSH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 734, + .Mnemonic = 736, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -55209,6 +57300,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -55222,12 +57314,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1982 Instruction:"PUSHP Zv" Encoding:"rex2w 0x57"/"O" + // Pos:1986 Instruction:"PUSHP Zv" Encoding:"rex2w 0x57"/"O" { .Instruction = ND_INS_PUSHP, .Category = ND_CAT_PUSH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 734, + .Mnemonic = 736, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -55236,6 +57328,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -55249,12 +57342,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1983 Instruction:"PVALIDATE" Encoding:"0xF2 0x0F 0x01 /0xFF"/"" + // Pos:1987 Instruction:"PVALIDATE" Encoding:"0xF2 0x0F 0x01 /0xFF"/"" { .Instruction = ND_INS_PVALIDATE, .Category = ND_CAT_SYSTEM, .IsaSet = ND_SET_SNP, - .Mnemonic = 735, + .Mnemonic = 737, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -55263,6 +57356,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_OF|NDR_RFLAG_ZF|NDR_RFLAG_AF|NDR_RFLAG_PF|NDR_RFLAG_SF|NDR_RFLAG_CF, .SetFlags = 0, @@ -55278,12 +57372,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1984 Instruction:"PXOR Pq,Qq" Encoding:"NP 0x0F 0xEF /r"/"RM" + // Pos:1988 Instruction:"PXOR Pq,Qq" Encoding:"NP 0x0F 0xEF /r"/"RM" { .Instruction = ND_INS_PXOR, .Category = ND_CAT_LOGICAL, .IsaSet = ND_SET_MMX, - .Mnemonic = 736, + .Mnemonic = 738, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -55292,6 +57386,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -55305,12 +57400,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1985 Instruction:"PXOR Vx,Wx" Encoding:"0x66 0x0F 0xEF /r"/"RM" + // Pos:1989 Instruction:"PXOR Vx,Wx" Encoding:"0x66 0x0F 0xEF /r"/"RM" { .Instruction = ND_INS_PXOR, .Category = ND_CAT_LOGICAL, .IsaSet = ND_SET_SSE2, - .Mnemonic = 736, + .Mnemonic = 738, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -55319,6 +57414,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -55332,12 +57428,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1986 Instruction:"RCL Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC0 /2 ib"/"MI" + // Pos:1990 Instruction:"RCL Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC0 /2 ib"/"MI" { .Instruction = ND_INS_RCL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 737, + .Mnemonic = 739, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -55346,6 +57442,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -55360,12 +57457,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1987 Instruction:"RCL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC1 /2 ib"/"MI" + // Pos:1991 Instruction:"RCL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC1 /2 ib"/"MI" { .Instruction = ND_INS_RCL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 737, + .Mnemonic = 739, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -55374,6 +57471,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -55388,12 +57486,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1988 Instruction:"RCL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xC1 /2 ib"/"MI" + // Pos:1992 Instruction:"RCL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xC1 /2 ib"/"MI" { .Instruction = ND_INS_RCL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 737, + .Mnemonic = 739, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -55402,6 +57500,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -55416,12 +57515,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1989 Instruction:"RCL Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD0 /2"/"M1" + // Pos:1993 Instruction:"RCL Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD0 /2"/"M1" { .Instruction = ND_INS_RCL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 737, + .Mnemonic = 739, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -55430,6 +57529,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -55444,12 +57544,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1990 Instruction:"RCL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD1 /2"/"M1" + // Pos:1994 Instruction:"RCL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD1 /2"/"M1" { .Instruction = ND_INS_RCL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 737, + .Mnemonic = 739, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -55458,6 +57558,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -55472,12 +57573,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1991 Instruction:"RCL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD1 /2"/"M1" + // Pos:1995 Instruction:"RCL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD1 /2"/"M1" { .Instruction = ND_INS_RCL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 737, + .Mnemonic = 739, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -55486,6 +57587,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -55500,12 +57602,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1992 Instruction:"RCL Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD2 /2"/"MC" + // Pos:1996 Instruction:"RCL Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD2 /2"/"MC" { .Instruction = ND_INS_RCL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 737, + .Mnemonic = 739, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -55514,6 +57616,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -55528,12 +57631,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1993 Instruction:"RCL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD3 /2"/"MC" + // Pos:1997 Instruction:"RCL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD3 /2"/"MC" { .Instruction = ND_INS_RCL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 737, + .Mnemonic = 739, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -55542,6 +57645,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -55556,12 +57660,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1994 Instruction:"RCL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD3 /2"/"MC" + // Pos:1998 Instruction:"RCL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD3 /2"/"MC" { .Instruction = ND_INS_RCL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 737, + .Mnemonic = 739, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -55570,6 +57674,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -55584,12 +57689,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1995 Instruction:"RCL Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC0 /2 ib"/"MI" + // Pos:1999 Instruction:"RCL Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC0 /2 ib"/"MI" { .Instruction = ND_INS_RCL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 737, + .Mnemonic = 739, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -55598,6 +57703,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -55611,12 +57717,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1996 Instruction:"RCL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC1 /2 ib"/"MI" + // Pos:2000 Instruction:"RCL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC1 /2 ib"/"MI" { .Instruction = ND_INS_RCL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 737, + .Mnemonic = 739, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -55625,6 +57731,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -55638,12 +57745,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1997 Instruction:"RCL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xC1 /2 ib"/"MI" + // Pos:2001 Instruction:"RCL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xC1 /2 ib"/"MI" { .Instruction = ND_INS_RCL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 737, + .Mnemonic = 739, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -55652,6 +57759,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -55665,12 +57773,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1998 Instruction:"RCL Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD0 /2"/"M1" + // Pos:2002 Instruction:"RCL Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD0 /2"/"M1" { .Instruction = ND_INS_RCL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 737, + .Mnemonic = 739, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -55679,6 +57787,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -55692,12 +57801,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:1999 Instruction:"RCL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD1 /2"/"M1" + // Pos:2003 Instruction:"RCL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD1 /2"/"M1" { .Instruction = ND_INS_RCL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 737, + .Mnemonic = 739, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -55706,6 +57815,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -55719,12 +57829,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2000 Instruction:"RCL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD1 /2"/"M1" + // Pos:2004 Instruction:"RCL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD1 /2"/"M1" { .Instruction = ND_INS_RCL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 737, + .Mnemonic = 739, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -55733,6 +57843,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -55746,12 +57857,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2001 Instruction:"RCL Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD2 /2"/"MC" + // Pos:2005 Instruction:"RCL Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD2 /2"/"MC" { .Instruction = ND_INS_RCL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 737, + .Mnemonic = 739, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -55760,6 +57871,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -55773,12 +57885,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2002 Instruction:"RCL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD3 /2"/"MC" + // Pos:2006 Instruction:"RCL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD3 /2"/"MC" { .Instruction = ND_INS_RCL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 737, + .Mnemonic = 739, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -55787,6 +57899,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -55800,12 +57913,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2003 Instruction:"RCL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD3 /2"/"MC" + // Pos:2007 Instruction:"RCL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD3 /2"/"MC" { .Instruction = ND_INS_RCL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 737, + .Mnemonic = 739, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -55814,6 +57927,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -55827,12 +57941,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2004 Instruction:"RCL Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC0 /2 ib"/"VMI" + // Pos:2008 Instruction:"RCL Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC0 /2 ib"/"VMI" { .Instruction = ND_INS_RCL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 737, + .Mnemonic = 739, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -55841,6 +57955,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -55856,12 +57971,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2005 Instruction:"RCL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC1 /2 ib"/"VMI" + // Pos:2009 Instruction:"RCL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC1 /2 ib"/"VMI" { .Instruction = ND_INS_RCL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 737, + .Mnemonic = 739, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -55870,6 +57985,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -55885,12 +58001,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2006 Instruction:"RCL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xC1 /2 ib"/"VMI" + // Pos:2010 Instruction:"RCL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xC1 /2 ib"/"VMI" { .Instruction = ND_INS_RCL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 737, + .Mnemonic = 739, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -55899,6 +58015,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -55914,12 +58031,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2007 Instruction:"RCL Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD0 /2"/"VM1" + // Pos:2011 Instruction:"RCL Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD0 /2"/"VM1" { .Instruction = ND_INS_RCL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 737, + .Mnemonic = 739, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -55928,6 +58045,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -55943,12 +58061,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2008 Instruction:"RCL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD1 /2"/"VM1" + // Pos:2012 Instruction:"RCL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD1 /2"/"VM1" { .Instruction = ND_INS_RCL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 737, + .Mnemonic = 739, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -55957,6 +58075,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -55972,12 +58091,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2009 Instruction:"RCL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD1 /2"/"VM1" + // Pos:2013 Instruction:"RCL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD1 /2"/"VM1" { .Instruction = ND_INS_RCL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 737, + .Mnemonic = 739, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -55986,6 +58105,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -56001,12 +58121,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2010 Instruction:"RCL Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD2 /2"/"VMC" + // Pos:2014 Instruction:"RCL Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD2 /2"/"VMC" { .Instruction = ND_INS_RCL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 737, + .Mnemonic = 739, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -56015,6 +58135,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -56030,12 +58151,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2011 Instruction:"RCL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD3 /2"/"VMC" + // Pos:2015 Instruction:"RCL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD3 /2"/"VMC" { .Instruction = ND_INS_RCL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 737, + .Mnemonic = 739, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -56044,6 +58165,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -56059,12 +58181,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2012 Instruction:"RCL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD3 /2"/"VMC" + // Pos:2016 Instruction:"RCL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD3 /2"/"VMC" { .Instruction = ND_INS_RCL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 737, + .Mnemonic = 739, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -56073,6 +58195,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -56088,12 +58211,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2013 Instruction:"RCL Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC0 /2 ib"/"VMI" + // Pos:2017 Instruction:"RCL Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC0 /2 ib"/"VMI" { .Instruction = ND_INS_RCL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 737, + .Mnemonic = 739, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -56102,6 +58225,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -56116,12 +58240,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2014 Instruction:"RCL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC1 /2 ib"/"VMI" + // Pos:2018 Instruction:"RCL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC1 /2 ib"/"VMI" { .Instruction = ND_INS_RCL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 737, + .Mnemonic = 739, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -56130,6 +58254,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -56144,12 +58269,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2015 Instruction:"RCL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xC1 /2 ib"/"VMI" + // Pos:2019 Instruction:"RCL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xC1 /2 ib"/"VMI" { .Instruction = ND_INS_RCL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 737, + .Mnemonic = 739, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -56158,6 +58283,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -56172,12 +58298,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2016 Instruction:"RCL Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD0 /2"/"VM1" + // Pos:2020 Instruction:"RCL Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD0 /2"/"VM1" { .Instruction = ND_INS_RCL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 737, + .Mnemonic = 739, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -56186,6 +58312,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -56200,12 +58327,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2017 Instruction:"RCL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD1 /2"/"VM1" + // Pos:2021 Instruction:"RCL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD1 /2"/"VM1" { .Instruction = ND_INS_RCL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 737, + .Mnemonic = 739, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -56214,6 +58341,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -56228,12 +58356,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2018 Instruction:"RCL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD1 /2"/"VM1" + // Pos:2022 Instruction:"RCL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD1 /2"/"VM1" { .Instruction = ND_INS_RCL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 737, + .Mnemonic = 739, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -56242,6 +58370,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -56256,12 +58385,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2019 Instruction:"RCL Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD2 /2"/"VMC" + // Pos:2023 Instruction:"RCL Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD2 /2"/"VMC" { .Instruction = ND_INS_RCL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 737, + .Mnemonic = 739, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -56270,6 +58399,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -56284,12 +58414,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2020 Instruction:"RCL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD3 /2"/"VMC" + // Pos:2024 Instruction:"RCL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD3 /2"/"VMC" { .Instruction = ND_INS_RCL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 737, + .Mnemonic = 739, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -56298,6 +58428,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -56312,12 +58443,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2021 Instruction:"RCL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD3 /2"/"VMC" + // Pos:2025 Instruction:"RCL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD3 /2"/"VMC" { .Instruction = ND_INS_RCL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 737, + .Mnemonic = 739, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -56326,6 +58457,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -56340,12 +58472,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2022 Instruction:"RCL Eb,Ib" Encoding:"0xC0 /2 ib"/"MI" + // Pos:2026 Instruction:"RCL Eb,Ib" Encoding:"0xC0 /2 ib"/"MI" { .Instruction = ND_INS_RCL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_I86, - .Mnemonic = 737, + .Mnemonic = 739, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -56354,6 +58486,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -56368,12 +58501,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2023 Instruction:"RCL Ev,Ib" Encoding:"0xC1 /2 ib"/"MI" + // Pos:2027 Instruction:"RCL Ev,Ib" Encoding:"0xC1 /2 ib"/"MI" { .Instruction = ND_INS_RCL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_I86, - .Mnemonic = 737, + .Mnemonic = 739, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -56382,6 +58515,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -56396,12 +58530,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2024 Instruction:"RCL Eb,1" Encoding:"0xD0 /2"/"M1" + // Pos:2028 Instruction:"RCL Eb,1" Encoding:"0xD0 /2"/"M1" { .Instruction = ND_INS_RCL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_I86, - .Mnemonic = 737, + .Mnemonic = 739, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -56410,6 +58544,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -56424,12 +58559,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2025 Instruction:"RCL Ev,1" Encoding:"0xD1 /2"/"M1" + // Pos:2029 Instruction:"RCL Ev,1" Encoding:"0xD1 /2"/"M1" { .Instruction = ND_INS_RCL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_I86, - .Mnemonic = 737, + .Mnemonic = 739, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -56438,6 +58573,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -56452,12 +58588,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2026 Instruction:"RCL Eb,CL" Encoding:"0xD2 /2"/"MC" + // Pos:2030 Instruction:"RCL Eb,CL" Encoding:"0xD2 /2"/"MC" { .Instruction = ND_INS_RCL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_I86, - .Mnemonic = 737, + .Mnemonic = 739, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -56466,6 +58602,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -56480,12 +58617,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2027 Instruction:"RCL Ev,CL" Encoding:"0xD3 /2"/"MC" + // Pos:2031 Instruction:"RCL Ev,CL" Encoding:"0xD3 /2"/"MC" { .Instruction = ND_INS_RCL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_I86, - .Mnemonic = 737, + .Mnemonic = 739, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -56494,6 +58631,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -56508,12 +58646,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2028 Instruction:"RCPPS Vps,Wps" Encoding:"NP 0x0F 0x53 /r"/"RM" + // Pos:2032 Instruction:"RCPPS Vps,Wps" Encoding:"NP 0x0F 0x53 /r"/"RM" { .Instruction = ND_INS_RCPPS, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE, - .Mnemonic = 738, + .Mnemonic = 740, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -56522,6 +58660,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -56535,12 +58674,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2029 Instruction:"RCPSS Vss,Wss" Encoding:"0xF3 0x0F 0x53 /r"/"RM" + // Pos:2033 Instruction:"RCPSS Vss,Wss" Encoding:"0xF3 0x0F 0x53 /r"/"RM" { .Instruction = ND_INS_RCPSS, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE, - .Mnemonic = 739, + .Mnemonic = 741, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -56549,6 +58688,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -56562,12 +58702,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2030 Instruction:"RCR Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC0 /3 ib"/"MI" + // Pos:2034 Instruction:"RCR Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC0 /3 ib"/"MI" { .Instruction = ND_INS_RCR, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 740, + .Mnemonic = 742, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -56576,6 +58716,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -56590,12 +58731,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2031 Instruction:"RCR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC1 /3 ib"/"MI" + // Pos:2035 Instruction:"RCR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC1 /3 ib"/"MI" { .Instruction = ND_INS_RCR, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 740, + .Mnemonic = 742, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -56604,6 +58745,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -56618,12 +58760,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2032 Instruction:"RCR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xC1 /3 ib"/"MI" + // Pos:2036 Instruction:"RCR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xC1 /3 ib"/"MI" { .Instruction = ND_INS_RCR, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 740, + .Mnemonic = 742, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -56632,6 +58774,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -56646,12 +58789,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2033 Instruction:"RCR Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD0 /3"/"M1" + // Pos:2037 Instruction:"RCR Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD0 /3"/"M1" { .Instruction = ND_INS_RCR, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 740, + .Mnemonic = 742, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -56660,6 +58803,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -56674,12 +58818,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2034 Instruction:"RCR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD1 /3"/"M1" + // Pos:2038 Instruction:"RCR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD1 /3"/"M1" { .Instruction = ND_INS_RCR, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 740, + .Mnemonic = 742, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -56688,6 +58832,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -56702,12 +58847,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2035 Instruction:"RCR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD1 /3"/"M1" + // Pos:2039 Instruction:"RCR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD1 /3"/"M1" { .Instruction = ND_INS_RCR, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 740, + .Mnemonic = 742, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -56716,6 +58861,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -56730,12 +58876,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2036 Instruction:"RCR Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD2 /3"/"MC" + // Pos:2040 Instruction:"RCR Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD2 /3"/"MC" { .Instruction = ND_INS_RCR, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 740, + .Mnemonic = 742, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -56744,6 +58890,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -56758,12 +58905,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2037 Instruction:"RCR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD3 /3"/"MC" + // Pos:2041 Instruction:"RCR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD3 /3"/"MC" { .Instruction = ND_INS_RCR, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 740, + .Mnemonic = 742, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -56772,6 +58919,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -56786,12 +58934,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2038 Instruction:"RCR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD3 /3"/"MC" + // Pos:2042 Instruction:"RCR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD3 /3"/"MC" { .Instruction = ND_INS_RCR, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 740, + .Mnemonic = 742, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -56800,6 +58948,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -56814,12 +58963,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2039 Instruction:"RCR Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC0 /3 ib"/"MI" + // Pos:2043 Instruction:"RCR Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC0 /3 ib"/"MI" { .Instruction = ND_INS_RCR, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 740, + .Mnemonic = 742, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -56828,6 +58977,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -56841,12 +58991,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2040 Instruction:"RCR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC1 /3 ib"/"MI" + // Pos:2044 Instruction:"RCR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC1 /3 ib"/"MI" { .Instruction = ND_INS_RCR, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 740, + .Mnemonic = 742, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -56855,6 +59005,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -56868,12 +59019,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2041 Instruction:"RCR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xC1 /3 ib"/"MI" + // Pos:2045 Instruction:"RCR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xC1 /3 ib"/"MI" { .Instruction = ND_INS_RCR, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 740, + .Mnemonic = 742, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -56882,6 +59033,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -56895,12 +59047,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2042 Instruction:"RCR Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD0 /3"/"M1" + // Pos:2046 Instruction:"RCR Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD0 /3"/"M1" { .Instruction = ND_INS_RCR, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 740, + .Mnemonic = 742, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -56909,6 +59061,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -56922,12 +59075,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2043 Instruction:"RCR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD1 /3"/"M1" + // Pos:2047 Instruction:"RCR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD1 /3"/"M1" { .Instruction = ND_INS_RCR, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 740, + .Mnemonic = 742, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -56936,6 +59089,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -56949,12 +59103,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2044 Instruction:"RCR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD1 /3"/"M1" + // Pos:2048 Instruction:"RCR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD1 /3"/"M1" { .Instruction = ND_INS_RCR, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 740, + .Mnemonic = 742, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -56963,6 +59117,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -56976,12 +59131,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2045 Instruction:"RCR Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD2 /3"/"MC" + // Pos:2049 Instruction:"RCR Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD2 /3"/"MC" { .Instruction = ND_INS_RCR, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 740, + .Mnemonic = 742, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -56990,6 +59145,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -57003,12 +59159,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2046 Instruction:"RCR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD3 /3"/"MC" + // Pos:2050 Instruction:"RCR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD3 /3"/"MC" { .Instruction = ND_INS_RCR, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 740, + .Mnemonic = 742, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -57017,6 +59173,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -57030,12 +59187,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2047 Instruction:"RCR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD3 /3"/"MC" + // Pos:2051 Instruction:"RCR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD3 /3"/"MC" { .Instruction = ND_INS_RCR, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 740, + .Mnemonic = 742, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -57044,6 +59201,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -57057,12 +59215,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2048 Instruction:"RCR Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC0 /3 ib"/"VMI" + // Pos:2052 Instruction:"RCR Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC0 /3 ib"/"VMI" { .Instruction = ND_INS_RCR, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 740, + .Mnemonic = 742, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -57071,6 +59229,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -57086,12 +59245,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2049 Instruction:"RCR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC1 /3 ib"/"VMI" + // Pos:2053 Instruction:"RCR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC1 /3 ib"/"VMI" { .Instruction = ND_INS_RCR, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 740, + .Mnemonic = 742, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -57100,6 +59259,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -57115,12 +59275,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2050 Instruction:"RCR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xC1 /3 ib"/"VMI" + // Pos:2054 Instruction:"RCR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xC1 /3 ib"/"VMI" { .Instruction = ND_INS_RCR, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 740, + .Mnemonic = 742, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -57129,6 +59289,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -57144,12 +59305,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2051 Instruction:"RCR Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD0 /3"/"VM1" + // Pos:2055 Instruction:"RCR Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD0 /3"/"VM1" { .Instruction = ND_INS_RCR, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 740, + .Mnemonic = 742, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -57158,6 +59319,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -57173,12 +59335,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2052 Instruction:"RCR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD1 /3"/"VM1" + // Pos:2056 Instruction:"RCR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD1 /3"/"VM1" { .Instruction = ND_INS_RCR, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 740, + .Mnemonic = 742, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -57187,6 +59349,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -57202,12 +59365,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2053 Instruction:"RCR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD1 /3"/"VM1" + // Pos:2057 Instruction:"RCR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD1 /3"/"VM1" { .Instruction = ND_INS_RCR, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 740, + .Mnemonic = 742, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -57216,6 +59379,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -57231,12 +59395,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2054 Instruction:"RCR Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD2 /3"/"VMC" + // Pos:2058 Instruction:"RCR Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD2 /3"/"VMC" { .Instruction = ND_INS_RCR, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 740, + .Mnemonic = 742, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -57245,6 +59409,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -57260,12 +59425,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2055 Instruction:"RCR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD3 /3"/"VMC" + // Pos:2059 Instruction:"RCR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD3 /3"/"VMC" { .Instruction = ND_INS_RCR, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 740, + .Mnemonic = 742, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -57274,6 +59439,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -57289,12 +59455,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2056 Instruction:"RCR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD3 /3"/"VMC" + // Pos:2060 Instruction:"RCR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD3 /3"/"VMC" { .Instruction = ND_INS_RCR, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 740, + .Mnemonic = 742, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -57303,6 +59469,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -57318,12 +59485,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2057 Instruction:"RCR Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC0 /3 ib"/"VMI" + // Pos:2061 Instruction:"RCR Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC0 /3 ib"/"VMI" { .Instruction = ND_INS_RCR, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 740, + .Mnemonic = 742, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -57332,6 +59499,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -57346,12 +59514,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2058 Instruction:"RCR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC1 /3 ib"/"VMI" + // Pos:2062 Instruction:"RCR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC1 /3 ib"/"VMI" { .Instruction = ND_INS_RCR, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 740, + .Mnemonic = 742, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -57360,6 +59528,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -57374,12 +59543,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2059 Instruction:"RCR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xC1 /3 ib"/"VMI" + // Pos:2063 Instruction:"RCR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xC1 /3 ib"/"VMI" { .Instruction = ND_INS_RCR, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 740, + .Mnemonic = 742, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -57388,6 +59557,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -57402,12 +59572,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2060 Instruction:"RCR Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD0 /3"/"VM1" + // Pos:2064 Instruction:"RCR Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD0 /3"/"VM1" { .Instruction = ND_INS_RCR, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 740, + .Mnemonic = 742, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -57416,6 +59586,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -57430,12 +59601,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2061 Instruction:"RCR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD1 /3"/"VM1" + // Pos:2065 Instruction:"RCR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD1 /3"/"VM1" { .Instruction = ND_INS_RCR, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 740, + .Mnemonic = 742, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -57444,6 +59615,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -57458,12 +59630,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2062 Instruction:"RCR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD1 /3"/"VM1" + // Pos:2066 Instruction:"RCR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD1 /3"/"VM1" { .Instruction = ND_INS_RCR, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 740, + .Mnemonic = 742, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -57472,6 +59644,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -57486,12 +59659,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2063 Instruction:"RCR Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD2 /3"/"VMC" + // Pos:2067 Instruction:"RCR Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD2 /3"/"VMC" { .Instruction = ND_INS_RCR, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 740, + .Mnemonic = 742, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -57500,6 +59673,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -57514,12 +59688,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2064 Instruction:"RCR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD3 /3"/"VMC" + // Pos:2068 Instruction:"RCR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD3 /3"/"VMC" { .Instruction = ND_INS_RCR, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 740, + .Mnemonic = 742, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -57528,6 +59702,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -57542,12 +59717,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2065 Instruction:"RCR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD3 /3"/"VMC" + // Pos:2069 Instruction:"RCR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD3 /3"/"VMC" { .Instruction = ND_INS_RCR, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 740, + .Mnemonic = 742, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -57556,6 +59731,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -57570,12 +59746,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2066 Instruction:"RCR Eb,Ib" Encoding:"0xC0 /3 ib"/"MI" + // Pos:2070 Instruction:"RCR Eb,Ib" Encoding:"0xC0 /3 ib"/"MI" { .Instruction = ND_INS_RCR, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_I86, - .Mnemonic = 740, + .Mnemonic = 742, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -57584,6 +59760,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -57598,12 +59775,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2067 Instruction:"RCR Ev,Ib" Encoding:"0xC1 /3 ib"/"MI" + // Pos:2071 Instruction:"RCR Ev,Ib" Encoding:"0xC1 /3 ib"/"MI" { .Instruction = ND_INS_RCR, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_I86, - .Mnemonic = 740, + .Mnemonic = 742, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -57612,6 +59789,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -57626,12 +59804,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2068 Instruction:"RCR Eb,1" Encoding:"0xD0 /3"/"M1" + // Pos:2072 Instruction:"RCR Eb,1" Encoding:"0xD0 /3"/"M1" { .Instruction = ND_INS_RCR, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_I86, - .Mnemonic = 740, + .Mnemonic = 742, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -57640,6 +59818,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -57654,12 +59833,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2069 Instruction:"RCR Ev,1" Encoding:"0xD1 /3"/"M1" + // Pos:2073 Instruction:"RCR Ev,1" Encoding:"0xD1 /3"/"M1" { .Instruction = ND_INS_RCR, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_I86, - .Mnemonic = 740, + .Mnemonic = 742, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -57668,6 +59847,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -57682,12 +59862,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2070 Instruction:"RCR Eb,CL" Encoding:"0xD2 /3"/"MC" + // Pos:2074 Instruction:"RCR Eb,CL" Encoding:"0xD2 /3"/"MC" { .Instruction = ND_INS_RCR, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_I86, - .Mnemonic = 740, + .Mnemonic = 742, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -57696,6 +59876,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -57710,12 +59891,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2071 Instruction:"RCR Ev,CL" Encoding:"0xD3 /3"/"MC" + // Pos:2075 Instruction:"RCR Ev,CL" Encoding:"0xD3 /3"/"MC" { .Instruction = ND_INS_RCR, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_I86, - .Mnemonic = 740, + .Mnemonic = 742, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -57724,6 +59905,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -57738,12 +59920,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2072 Instruction:"RDFSBASE Ry" Encoding:"mo64 0xF3 0x0F 0xAE /0:reg"/"M" + // Pos:2076 Instruction:"RDFSBASE Ry" Encoding:"mo64 0xF3 0x0F 0xAE /0:reg"/"M" { .Instruction = ND_INS_RDFSBASE, .Category = ND_CAT_RDWRFSGS, .IsaSet = ND_SET_RDWRFSGS, - .Mnemonic = 741, + .Mnemonic = 743, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -57752,6 +59934,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -57765,12 +59948,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2073 Instruction:"RDGSBASE Ry" Encoding:"mo64 0xF3 0x0F 0xAE /1:reg"/"M" + // Pos:2077 Instruction:"RDGSBASE Ry" Encoding:"mo64 0xF3 0x0F 0xAE /1:reg"/"M" { .Instruction = ND_INS_RDGSBASE, .Category = ND_CAT_RDWRFSGS, .IsaSet = ND_SET_RDWRFSGS, - .Mnemonic = 742, + .Mnemonic = 744, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -57779,6 +59962,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -57792,12 +59976,41 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2074 Instruction:"RDMSR" Encoding:"0x0F 0x32"/"" + // Pos:2078 Instruction:"RDMSR Rq,Id" Encoding:"evex m:7 nf:0 p:3 l:0 w:0 0xF6 /0:reg id"/"MI" + { + .Instruction = ND_INS_RDMSR, + .Category = ND_CAT_SYSTEM, + .IsaSet = ND_SET_MSR_IMM, + .Mnemonic = 745, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_VEX, + .SimdExc = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP|ND_FLAG_O64, + .CpuidFlag = ND_CFF_MSR_IMM, + .Operands = + { + OP(ND_OPT_R, ND_OPS_q, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_I, ND_OPS_d, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_MSR, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2079 Instruction:"RDMSR" Encoding:"0x0F 0x32"/"" { .Instruction = ND_INS_RDMSR, .Category = ND_CAT_SYSTEM, .IsaSet = ND_SET_PENTIUMREAL, - .Mnemonic = 743, + .Mnemonic = 745, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -57806,6 +60019,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -57821,12 +60035,41 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2075 Instruction:"RDMSRLIST" Encoding:"0xF2 0x0F 0x01 /0xC6"/"" + // Pos:2080 Instruction:"RDMSR Rq,Id" Encoding:"vex m:7 p:3 l:0 w:0 0xF6 /0:reg id"/"MI" + { + .Instruction = ND_INS_RDMSR, + .Category = ND_CAT_SYSTEM, + .IsaSet = ND_SET_MSR_IMM, + .Mnemonic = 745, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .SimdExc = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_O64, + .CpuidFlag = ND_CFF_MSR_IMM, + .Operands = + { + OP(ND_OPT_R, ND_OPS_q, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_I, ND_OPS_d, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_MSR, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2081 Instruction:"RDMSRLIST" Encoding:"0xF2 0x0F 0x01 /0xC6"/"" { .Instruction = ND_INS_RDMSRLIST, .Category = ND_CAT_SYSTEM, .IsaSet = ND_SET_MSRLIST, - .Mnemonic = 744, + .Mnemonic = 746, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -57835,6 +60078,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -57849,12 +60093,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2076 Instruction:"RDPID Ryf" Encoding:"0xF3 0x0F 0xC7 /7:reg"/"M" + // Pos:2082 Instruction:"RDPID Ryf" Encoding:"0xF3 0x0F 0xC7 /7:reg"/"M" { .Instruction = ND_INS_RDPID, .Category = ND_CAT_RDPID, .IsaSet = ND_SET_RDPID, - .Mnemonic = 745, + .Mnemonic = 747, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -57863,6 +60107,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -57876,12 +60121,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2077 Instruction:"RDPKRU" Encoding:"NP 0x0F 0x01 /0xEE"/"" + // Pos:2083 Instruction:"RDPKRU" Encoding:"NP 0x0F 0x01 /0xEE"/"" { .Instruction = ND_INS_RDPKRU, .Category = ND_CAT_MISC, .IsaSet = ND_SET_PKU, - .Mnemonic = 746, + .Mnemonic = 748, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -57890,6 +60135,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -57905,12 +60151,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2078 Instruction:"RDPMC" Encoding:"0x0F 0x33"/"" + // Pos:2084 Instruction:"RDPMC" Encoding:"0x0F 0x33"/"" { .Instruction = ND_INS_RDPMC, .Category = ND_CAT_SYSTEM, .IsaSet = ND_SET_RDPMC, - .Mnemonic = 747, + .Mnemonic = 749, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -57919,6 +60165,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -57934,12 +60181,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2079 Instruction:"RDPRU" Encoding:"NP 0x0F 0x01 /0xFD"/"" + // Pos:2085 Instruction:"RDPRU" Encoding:"NP 0x0F 0x01 /0xFD"/"" { .Instruction = ND_INS_RDPRU, .Category = ND_CAT_MISC, .IsaSet = ND_SET_RDPRU, - .Mnemonic = 748, + .Mnemonic = 750, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -57948,6 +60195,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF, .SetFlags = 0, @@ -57963,12 +60211,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2080 Instruction:"RDRAND Rv" Encoding:"NP 0x0F 0xC7 /6:reg"/"M" + // Pos:2086 Instruction:"RDRAND Rv" Encoding:"NP 0x0F 0xC7 /6:reg"/"M" { .Instruction = ND_INS_RDRAND, .Category = ND_CAT_RDRAND, .IsaSet = ND_SET_RDRAND, - .Mnemonic = 749, + .Mnemonic = 751, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -57977,6 +60225,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF, .SetFlags = 0, @@ -57990,12 +60239,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2081 Instruction:"RDRAND Rv" Encoding:"0x66 0x0F 0xC7 /6:reg"/"M" + // Pos:2087 Instruction:"RDRAND Rv" Encoding:"0x66 0x0F 0xC7 /6:reg"/"M" { .Instruction = ND_INS_RDRAND, .Category = ND_CAT_RDRAND, .IsaSet = ND_SET_RDRAND, - .Mnemonic = 749, + .Mnemonic = 751, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -58004,6 +60253,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF, .SetFlags = 0, @@ -58017,12 +60267,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2082 Instruction:"RDSEED Rv" Encoding:"NP 0x0F 0xC7 /7:reg"/"M" + // Pos:2088 Instruction:"RDSEED Rv" Encoding:"NP 0x0F 0xC7 /7:reg"/"M" { .Instruction = ND_INS_RDSEED, .Category = ND_CAT_RDSEED, .IsaSet = ND_SET_RDSEED, - .Mnemonic = 750, + .Mnemonic = 752, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -58031,6 +60281,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF, .SetFlags = 0, @@ -58044,12 +60295,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2083 Instruction:"RDSEED Rv" Encoding:"0x66 0x0F 0xC7 /7:reg"/"M" + // Pos:2089 Instruction:"RDSEED Rv" Encoding:"0x66 0x0F 0xC7 /7:reg"/"M" { .Instruction = ND_INS_RDSEED, .Category = ND_CAT_RDSEED, .IsaSet = ND_SET_RDSEED, - .Mnemonic = 750, + .Mnemonic = 752, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -58058,6 +60309,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF, .SetFlags = 0, @@ -58071,12 +60323,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2084 Instruction:"RDSSPD Rd" Encoding:"cet repz 0x0F 0x1E /1:reg"/"M" + // Pos:2090 Instruction:"RDSSPD Rd" Encoding:"cet repz 0x0F 0x1E /1:reg"/"M" { .Instruction = ND_INS_RSSSP, .Category = ND_CAT_CET, .IsaSet = ND_SET_CET_SS, - .Mnemonic = 751, + .Mnemonic = 753, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -58085,6 +60337,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -58098,12 +60351,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2085 Instruction:"RDSSPQ Rq" Encoding:"cet repz rexw 0x0F 0x1E /1:reg"/"M" + // Pos:2091 Instruction:"RDSSPQ Rq" Encoding:"cet repz rexw 0x0F 0x1E /1:reg"/"M" { .Instruction = ND_INS_RSSSP, .Category = ND_CAT_CET, .IsaSet = ND_SET_CET_SS, - .Mnemonic = 752, + .Mnemonic = 754, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -58112,6 +60365,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -58125,12 +60379,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2086 Instruction:"RDTSC" Encoding:"0x0F 0x31"/"" + // Pos:2092 Instruction:"RDTSC" Encoding:"0x0F 0x31"/"" { .Instruction = ND_INS_RDTSC, .Category = ND_CAT_SYSTEM, .IsaSet = ND_SET_PENTIUMREAL, - .Mnemonic = 753, + .Mnemonic = 755, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -58139,6 +60393,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -58153,12 +60408,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2087 Instruction:"RDTSCP" Encoding:"0x0F 0x01 /0xF9"/"" + // Pos:2093 Instruction:"RDTSCP" Encoding:"0x0F 0x01 /0xF9"/"" { .Instruction = ND_INS_RDTSCP, .Category = ND_CAT_SYSTEM, .IsaSet = ND_SET_RDTSCP, - .Mnemonic = 754, + .Mnemonic = 756, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -58167,6 +60422,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -58183,12 +60439,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2088 Instruction:"RETF Iw" Encoding:"0xCA iw"/"I" + // Pos:2094 Instruction:"RETF Iw" Encoding:"0xCA iw"/"I" { .Instruction = ND_INS_RETF, .Category = ND_CAT_RET, .IsaSet = ND_SET_I86, - .Mnemonic = 755, + .Mnemonic = 757, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -58197,6 +60453,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -58213,12 +60470,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2089 Instruction:"RETF" Encoding:"0xCB"/"" + // Pos:2095 Instruction:"RETF" Encoding:"0xCB"/"" { .Instruction = ND_INS_RETF, .Category = ND_CAT_RET, .IsaSet = ND_SET_I86, - .Mnemonic = 755, + .Mnemonic = 757, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -58227,6 +60484,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -58242,12 +60500,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2090 Instruction:"RETN Iw" Encoding:"0xC2 iw"/"I" + // Pos:2096 Instruction:"RETN Iw" Encoding:"0xC2 iw"/"I" { .Instruction = ND_INS_RETN, .Category = ND_CAT_RET, .IsaSet = ND_SET_I86, - .Mnemonic = 756, + .Mnemonic = 758, .ValidPrefixes = ND_PREF_BND, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -58256,6 +60514,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -58272,12 +60531,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2091 Instruction:"RETN" Encoding:"0xC3"/"" + // Pos:2097 Instruction:"RETN" Encoding:"0xC3"/"" { .Instruction = ND_INS_RETN, .Category = ND_CAT_RET, .IsaSet = ND_SET_I86, - .Mnemonic = 756, + .Mnemonic = 758, .ValidPrefixes = ND_PREF_BND, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -58286,6 +60545,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -58300,12 +60560,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2092 Instruction:"RMPADJUST" Encoding:"0xF3 0x0F 0x01 /0xFE"/"" + // Pos:2098 Instruction:"RMPADJUST" Encoding:"0xF3 0x0F 0x01 /0xFE"/"" { .Instruction = ND_INS_RMPADJUST, .Category = ND_CAT_SYSTEM, .IsaSet = ND_SET_SNP, - .Mnemonic = 757, + .Mnemonic = 759, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -58314,6 +60574,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_OF|NDR_RFLAG_ZF|NDR_RFLAG_AF|NDR_RFLAG_PF|NDR_RFLAG_SF, .SetFlags = 0, @@ -58330,12 +60591,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2093 Instruction:"RMPQUERY" Encoding:"0xF3 0x0F 0x01 /0xFD"/"" + // Pos:2099 Instruction:"RMPQUERY" Encoding:"0xF3 0x0F 0x01 /0xFD"/"" { .Instruction = ND_INS_RMPQUERY, .Category = ND_CAT_SYSTEM, .IsaSet = ND_SET_SNP, - .Mnemonic = 758, + .Mnemonic = 760, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -58344,6 +60605,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_OF|NDR_RFLAG_ZF|NDR_RFLAG_AF|NDR_RFLAG_PF|NDR_RFLAG_SF, .SetFlags = 0, @@ -58360,12 +60622,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2094 Instruction:"RMPREAD" Encoding:"0xF2 0x0F 0x01 /0xFD"/"" + // Pos:2100 Instruction:"RMPREAD" Encoding:"0xF2 0x0F 0x01 /0xFD"/"" { .Instruction = ND_INS_RMPREAD, .Category = ND_CAT_SYSTEM, .IsaSet = ND_SET_SNP, - .Mnemonic = 759, + .Mnemonic = 761, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -58374,6 +60636,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_OF|NDR_RFLAG_ZF|NDR_RFLAG_AF|NDR_RFLAG_PF|NDR_RFLAG_SF, .SetFlags = 0, @@ -58388,12 +60651,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2095 Instruction:"RMPUPDATE" Encoding:"0xF2 0x0F 0x01 /0xFE"/"" + // Pos:2101 Instruction:"RMPUPDATE" Encoding:"0xF2 0x0F 0x01 /0xFE"/"" { .Instruction = ND_INS_RMPUPDATE, .Category = ND_CAT_SYSTEM, .IsaSet = ND_SET_SNP, - .Mnemonic = 760, + .Mnemonic = 762, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -58402,6 +60665,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_OF|NDR_RFLAG_ZF|NDR_RFLAG_AF|NDR_RFLAG_PF|NDR_RFLAG_SF, .SetFlags = 0, @@ -58416,12 +60680,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2096 Instruction:"ROL Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC0 /0 ib"/"MI" + // Pos:2102 Instruction:"ROL Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC0 /0 ib"/"MI" { .Instruction = ND_INS_ROL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 761, + .Mnemonic = 763, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -58430,6 +60694,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -58444,12 +60709,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2097 Instruction:"ROL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC1 /0 ib"/"MI" + // Pos:2103 Instruction:"ROL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC1 /0 ib"/"MI" { .Instruction = ND_INS_ROL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 761, + .Mnemonic = 763, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -58458,6 +60723,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -58472,12 +60738,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2098 Instruction:"ROL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xC1 /0 ib"/"MI" + // Pos:2104 Instruction:"ROL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xC1 /0 ib"/"MI" { .Instruction = ND_INS_ROL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 761, + .Mnemonic = 763, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -58486,6 +60752,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -58500,12 +60767,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2099 Instruction:"ROL Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD0 /0"/"M1" + // Pos:2105 Instruction:"ROL Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD0 /0"/"M1" { .Instruction = ND_INS_ROL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 761, + .Mnemonic = 763, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -58514,6 +60781,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -58528,12 +60796,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2100 Instruction:"ROL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD1 /0"/"M1" + // Pos:2106 Instruction:"ROL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD1 /0"/"M1" { .Instruction = ND_INS_ROL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 761, + .Mnemonic = 763, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -58542,6 +60810,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -58556,12 +60825,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2101 Instruction:"ROL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD1 /0"/"M1" + // Pos:2107 Instruction:"ROL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD1 /0"/"M1" { .Instruction = ND_INS_ROL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 761, + .Mnemonic = 763, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -58570,6 +60839,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -58584,12 +60854,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2102 Instruction:"ROL Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD2 /0"/"MC" + // Pos:2108 Instruction:"ROL Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD2 /0"/"MC" { .Instruction = ND_INS_ROL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 761, + .Mnemonic = 763, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -58598,6 +60868,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -58612,12 +60883,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2103 Instruction:"ROL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD3 /0"/"MC" + // Pos:2109 Instruction:"ROL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD3 /0"/"MC" { .Instruction = ND_INS_ROL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 761, + .Mnemonic = 763, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -58626,6 +60897,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -58640,12 +60912,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2104 Instruction:"ROL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD3 /0"/"MC" + // Pos:2110 Instruction:"ROL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD3 /0"/"MC" { .Instruction = ND_INS_ROL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 761, + .Mnemonic = 763, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -58654,6 +60926,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -58668,12 +60941,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2105 Instruction:"ROL Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC0 /0 ib"/"MI" + // Pos:2111 Instruction:"ROL Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC0 /0 ib"/"MI" { .Instruction = ND_INS_ROL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 761, + .Mnemonic = 763, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -58682,6 +60955,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -58695,12 +60969,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2106 Instruction:"ROL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC1 /0 ib"/"MI" + // Pos:2112 Instruction:"ROL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC1 /0 ib"/"MI" { .Instruction = ND_INS_ROL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 761, + .Mnemonic = 763, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -58709,6 +60983,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -58722,12 +60997,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2107 Instruction:"ROL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xC1 /0 ib"/"MI" + // Pos:2113 Instruction:"ROL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xC1 /0 ib"/"MI" { .Instruction = ND_INS_ROL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 761, + .Mnemonic = 763, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -58736,6 +61011,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -58749,12 +61025,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2108 Instruction:"ROL Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD0 /0"/"M1" + // Pos:2114 Instruction:"ROL Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD0 /0"/"M1" { .Instruction = ND_INS_ROL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 761, + .Mnemonic = 763, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -58763,6 +61039,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -58776,12 +61053,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2109 Instruction:"ROL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD1 /0"/"M1" + // Pos:2115 Instruction:"ROL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD1 /0"/"M1" { .Instruction = ND_INS_ROL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 761, + .Mnemonic = 763, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -58790,6 +61067,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -58803,12 +61081,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2110 Instruction:"ROL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD1 /0"/"M1" + // Pos:2116 Instruction:"ROL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD1 /0"/"M1" { .Instruction = ND_INS_ROL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 761, + .Mnemonic = 763, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -58817,6 +61095,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -58830,12 +61109,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2111 Instruction:"ROL Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD2 /0"/"MC" + // Pos:2117 Instruction:"ROL Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD2 /0"/"MC" { .Instruction = ND_INS_ROL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 761, + .Mnemonic = 763, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -58844,6 +61123,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -58857,12 +61137,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2112 Instruction:"ROL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD3 /0"/"MC" + // Pos:2118 Instruction:"ROL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD3 /0"/"MC" { .Instruction = ND_INS_ROL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 761, + .Mnemonic = 763, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -58871,6 +61151,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -58884,12 +61165,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2113 Instruction:"ROL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD3 /0"/"MC" + // Pos:2119 Instruction:"ROL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD3 /0"/"MC" { .Instruction = ND_INS_ROL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 761, + .Mnemonic = 763, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -58898,6 +61179,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -58911,12 +61193,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2114 Instruction:"ROL Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC0 /0 ib"/"VMI" + // Pos:2120 Instruction:"ROL Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC0 /0 ib"/"VMI" { .Instruction = ND_INS_ROL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 761, + .Mnemonic = 763, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -58925,6 +61207,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -58940,12 +61223,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2115 Instruction:"ROL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC1 /0 ib"/"VMI" + // Pos:2121 Instruction:"ROL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC1 /0 ib"/"VMI" { .Instruction = ND_INS_ROL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 761, + .Mnemonic = 763, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -58954,6 +61237,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -58969,12 +61253,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2116 Instruction:"ROL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xC1 /0 ib"/"VMI" + // Pos:2122 Instruction:"ROL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xC1 /0 ib"/"VMI" { .Instruction = ND_INS_ROL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 761, + .Mnemonic = 763, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -58983,6 +61267,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -58998,12 +61283,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2117 Instruction:"ROL Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD0 /0"/"VM1" + // Pos:2123 Instruction:"ROL Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD0 /0"/"VM1" { .Instruction = ND_INS_ROL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 761, + .Mnemonic = 763, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -59012,6 +61297,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -59027,12 +61313,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2118 Instruction:"ROL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD1 /0"/"VM1" + // Pos:2124 Instruction:"ROL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD1 /0"/"VM1" { .Instruction = ND_INS_ROL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 761, + .Mnemonic = 763, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -59041,6 +61327,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -59056,12 +61343,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2119 Instruction:"ROL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD1 /0"/"VM1" + // Pos:2125 Instruction:"ROL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD1 /0"/"VM1" { .Instruction = ND_INS_ROL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 761, + .Mnemonic = 763, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -59070,6 +61357,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -59085,12 +61373,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2120 Instruction:"ROL Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD2 /0"/"VMC" + // Pos:2126 Instruction:"ROL Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD2 /0"/"VMC" { .Instruction = ND_INS_ROL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 761, + .Mnemonic = 763, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -59099,6 +61387,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -59114,12 +61403,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2121 Instruction:"ROL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD3 /0"/"VMC" + // Pos:2127 Instruction:"ROL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD3 /0"/"VMC" { .Instruction = ND_INS_ROL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 761, + .Mnemonic = 763, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -59128,6 +61417,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -59143,12 +61433,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2122 Instruction:"ROL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD3 /0"/"VMC" + // Pos:2128 Instruction:"ROL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD3 /0"/"VMC" { .Instruction = ND_INS_ROL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 761, + .Mnemonic = 763, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -59157,6 +61447,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -59172,12 +61463,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2123 Instruction:"ROL Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC0 /0 ib"/"VMI" + // Pos:2129 Instruction:"ROL Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC0 /0 ib"/"VMI" { .Instruction = ND_INS_ROL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 761, + .Mnemonic = 763, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -59186,6 +61477,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -59200,12 +61492,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2124 Instruction:"ROL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC1 /0 ib"/"VMI" + // Pos:2130 Instruction:"ROL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC1 /0 ib"/"VMI" { .Instruction = ND_INS_ROL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 761, + .Mnemonic = 763, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -59214,6 +61506,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -59228,12 +61521,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2125 Instruction:"ROL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xC1 /0 ib"/"VMI" + // Pos:2131 Instruction:"ROL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xC1 /0 ib"/"VMI" { .Instruction = ND_INS_ROL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 761, + .Mnemonic = 763, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -59242,6 +61535,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -59256,12 +61550,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2126 Instruction:"ROL Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD0 /0"/"VM1" + // Pos:2132 Instruction:"ROL Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD0 /0"/"VM1" { .Instruction = ND_INS_ROL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 761, + .Mnemonic = 763, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -59270,6 +61564,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -59284,12 +61579,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2127 Instruction:"ROL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD1 /0"/"VM1" + // Pos:2133 Instruction:"ROL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD1 /0"/"VM1" { .Instruction = ND_INS_ROL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 761, + .Mnemonic = 763, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -59298,6 +61593,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -59312,12 +61608,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2128 Instruction:"ROL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD1 /0"/"VM1" + // Pos:2134 Instruction:"ROL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD1 /0"/"VM1" { .Instruction = ND_INS_ROL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 761, + .Mnemonic = 763, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -59326,6 +61622,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -59340,12 +61637,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2129 Instruction:"ROL Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD2 /0"/"VMC" + // Pos:2135 Instruction:"ROL Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD2 /0"/"VMC" { .Instruction = ND_INS_ROL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 761, + .Mnemonic = 763, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -59354,6 +61651,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -59368,12 +61666,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2130 Instruction:"ROL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD3 /0"/"VMC" + // Pos:2136 Instruction:"ROL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD3 /0"/"VMC" { .Instruction = ND_INS_ROL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 761, + .Mnemonic = 763, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -59382,6 +61680,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -59396,12 +61695,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2131 Instruction:"ROL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD3 /0"/"VMC" + // Pos:2137 Instruction:"ROL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD3 /0"/"VMC" { .Instruction = ND_INS_ROL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 761, + .Mnemonic = 763, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -59410,6 +61709,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -59424,12 +61724,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2132 Instruction:"ROL Eb,Ib" Encoding:"0xC0 /0 ib"/"MI" + // Pos:2138 Instruction:"ROL Eb,Ib" Encoding:"0xC0 /0 ib"/"MI" { .Instruction = ND_INS_ROL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_I86, - .Mnemonic = 761, + .Mnemonic = 763, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -59438,6 +61738,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -59452,12 +61753,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2133 Instruction:"ROL Ev,Ib" Encoding:"0xC1 /0 ib"/"MI" + // Pos:2139 Instruction:"ROL Ev,Ib" Encoding:"0xC1 /0 ib"/"MI" { .Instruction = ND_INS_ROL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_I86, - .Mnemonic = 761, + .Mnemonic = 763, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -59466,6 +61767,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -59480,12 +61782,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2134 Instruction:"ROL Eb,1" Encoding:"0xD0 /0"/"M1" + // Pos:2140 Instruction:"ROL Eb,1" Encoding:"0xD0 /0"/"M1" { .Instruction = ND_INS_ROL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_I86, - .Mnemonic = 761, + .Mnemonic = 763, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -59494,6 +61796,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -59508,12 +61811,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2135 Instruction:"ROL Ev,1" Encoding:"0xD1 /0"/"M1" + // Pos:2141 Instruction:"ROL Ev,1" Encoding:"0xD1 /0"/"M1" { .Instruction = ND_INS_ROL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_I86, - .Mnemonic = 761, + .Mnemonic = 763, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -59522,6 +61825,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -59536,12 +61840,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2136 Instruction:"ROL Eb,CL" Encoding:"0xD2 /0"/"MC" + // Pos:2142 Instruction:"ROL Eb,CL" Encoding:"0xD2 /0"/"MC" { .Instruction = ND_INS_ROL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_I86, - .Mnemonic = 761, + .Mnemonic = 763, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -59550,6 +61854,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -59564,12 +61869,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2137 Instruction:"ROL Ev,CL" Encoding:"0xD3 /0"/"MC" + // Pos:2143 Instruction:"ROL Ev,CL" Encoding:"0xD3 /0"/"MC" { .Instruction = ND_INS_ROL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_I86, - .Mnemonic = 761, + .Mnemonic = 763, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -59578,6 +61883,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -59592,12 +61898,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2138 Instruction:"ROR Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC0 /1 ib"/"MI" + // Pos:2144 Instruction:"ROR Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC0 /1 ib"/"MI" { .Instruction = ND_INS_ROR, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 762, + .Mnemonic = 764, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -59606,6 +61912,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -59620,12 +61927,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2139 Instruction:"ROR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC1 /1 ib"/"MI" + // Pos:2145 Instruction:"ROR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC1 /1 ib"/"MI" { .Instruction = ND_INS_ROR, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 762, + .Mnemonic = 764, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -59634,6 +61941,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -59648,12 +61956,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2140 Instruction:"ROR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xC1 /1 ib"/"MI" + // Pos:2146 Instruction:"ROR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xC1 /1 ib"/"MI" { .Instruction = ND_INS_ROR, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 762, + .Mnemonic = 764, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -59662,6 +61970,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -59676,12 +61985,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2141 Instruction:"ROR Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD0 /1"/"M1" + // Pos:2147 Instruction:"ROR Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD0 /1"/"M1" { .Instruction = ND_INS_ROR, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 762, + .Mnemonic = 764, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -59690,6 +61999,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -59704,12 +62014,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2142 Instruction:"ROR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD1 /1"/"M1" + // Pos:2148 Instruction:"ROR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD1 /1"/"M1" { .Instruction = ND_INS_ROR, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 762, + .Mnemonic = 764, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -59718,6 +62028,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -59732,12 +62043,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2143 Instruction:"ROR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD1 /1"/"M1" + // Pos:2149 Instruction:"ROR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD1 /1"/"M1" { .Instruction = ND_INS_ROR, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 762, + .Mnemonic = 764, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -59746,6 +62057,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -59760,12 +62072,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2144 Instruction:"ROR Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD2 /1"/"MC" + // Pos:2150 Instruction:"ROR Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD2 /1"/"MC" { .Instruction = ND_INS_ROR, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 762, + .Mnemonic = 764, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -59774,6 +62086,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -59788,12 +62101,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2145 Instruction:"ROR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD3 /1"/"MC" + // Pos:2151 Instruction:"ROR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD3 /1"/"MC" { .Instruction = ND_INS_ROR, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 762, + .Mnemonic = 764, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -59802,6 +62115,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -59816,12 +62130,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2146 Instruction:"ROR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD3 /1"/"MC" + // Pos:2152 Instruction:"ROR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD3 /1"/"MC" { .Instruction = ND_INS_ROR, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 762, + .Mnemonic = 764, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -59830,6 +62144,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -59844,12 +62159,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2147 Instruction:"ROR Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC0 /1 ib"/"MI" + // Pos:2153 Instruction:"ROR Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC0 /1 ib"/"MI" { .Instruction = ND_INS_ROR, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 762, + .Mnemonic = 764, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -59858,6 +62173,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -59871,12 +62187,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2148 Instruction:"ROR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC1 /1 ib"/"MI" + // Pos:2154 Instruction:"ROR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC1 /1 ib"/"MI" { .Instruction = ND_INS_ROR, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 762, + .Mnemonic = 764, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -59885,6 +62201,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -59898,12 +62215,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2149 Instruction:"ROR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xC1 /1 ib"/"MI" + // Pos:2155 Instruction:"ROR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xC1 /1 ib"/"MI" { .Instruction = ND_INS_ROR, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 762, + .Mnemonic = 764, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -59912,6 +62229,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -59925,12 +62243,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2150 Instruction:"ROR Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD0 /1"/"M1" + // Pos:2156 Instruction:"ROR Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD0 /1"/"M1" { .Instruction = ND_INS_ROR, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 762, + .Mnemonic = 764, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -59939,6 +62257,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -59952,12 +62271,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2151 Instruction:"ROR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD1 /1"/"M1" + // Pos:2157 Instruction:"ROR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD1 /1"/"M1" { .Instruction = ND_INS_ROR, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 762, + .Mnemonic = 764, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -59966,6 +62285,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -59979,12 +62299,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2152 Instruction:"ROR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD1 /1"/"M1" + // Pos:2158 Instruction:"ROR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD1 /1"/"M1" { .Instruction = ND_INS_ROR, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 762, + .Mnemonic = 764, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -59993,6 +62313,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -60006,12 +62327,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2153 Instruction:"ROR Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD2 /1"/"MC" + // Pos:2159 Instruction:"ROR Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD2 /1"/"MC" { .Instruction = ND_INS_ROR, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 762, + .Mnemonic = 764, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -60020,6 +62341,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -60033,12 +62355,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2154 Instruction:"ROR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD3 /1"/"MC" + // Pos:2160 Instruction:"ROR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD3 /1"/"MC" { .Instruction = ND_INS_ROR, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 762, + .Mnemonic = 764, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -60047,6 +62369,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -60060,12 +62383,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2155 Instruction:"ROR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD3 /1"/"MC" + // Pos:2161 Instruction:"ROR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD3 /1"/"MC" { .Instruction = ND_INS_ROR, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 762, + .Mnemonic = 764, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -60074,6 +62397,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -60087,12 +62411,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2156 Instruction:"ROR Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC0 /1 ib"/"VMI" + // Pos:2162 Instruction:"ROR Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC0 /1 ib"/"VMI" { .Instruction = ND_INS_ROR, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 762, + .Mnemonic = 764, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -60101,6 +62425,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -60116,12 +62441,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2157 Instruction:"ROR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC1 /1 ib"/"VMI" + // Pos:2163 Instruction:"ROR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC1 /1 ib"/"VMI" { .Instruction = ND_INS_ROR, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 762, + .Mnemonic = 764, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -60130,6 +62455,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -60145,12 +62471,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2158 Instruction:"ROR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xC1 /1 ib"/"VMI" + // Pos:2164 Instruction:"ROR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xC1 /1 ib"/"VMI" { .Instruction = ND_INS_ROR, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 762, + .Mnemonic = 764, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -60159,6 +62485,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -60174,12 +62501,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2159 Instruction:"ROR Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD0 /1"/"VM1" + // Pos:2165 Instruction:"ROR Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD0 /1"/"VM1" { .Instruction = ND_INS_ROR, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 762, + .Mnemonic = 764, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -60188,6 +62515,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -60203,12 +62531,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2160 Instruction:"ROR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD1 /1"/"VM1" + // Pos:2166 Instruction:"ROR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD1 /1"/"VM1" { .Instruction = ND_INS_ROR, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 762, + .Mnemonic = 764, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -60217,6 +62545,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -60232,12 +62561,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2161 Instruction:"ROR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD1 /1"/"VM1" + // Pos:2167 Instruction:"ROR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD1 /1"/"VM1" { .Instruction = ND_INS_ROR, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 762, + .Mnemonic = 764, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -60246,6 +62575,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -60261,12 +62591,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2162 Instruction:"ROR Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD2 /1"/"VMC" + // Pos:2168 Instruction:"ROR Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD2 /1"/"VMC" { .Instruction = ND_INS_ROR, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 762, + .Mnemonic = 764, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -60275,6 +62605,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -60290,12 +62621,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2163 Instruction:"ROR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD3 /1"/"VMC" + // Pos:2169 Instruction:"ROR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD3 /1"/"VMC" { .Instruction = ND_INS_ROR, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 762, + .Mnemonic = 764, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -60304,6 +62635,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -60319,12 +62651,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2164 Instruction:"ROR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD3 /1"/"VMC" + // Pos:2170 Instruction:"ROR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD3 /1"/"VMC" { .Instruction = ND_INS_ROR, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 762, + .Mnemonic = 764, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -60333,6 +62665,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -60348,12 +62681,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2165 Instruction:"ROR Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC0 /1 ib"/"VMI" + // Pos:2171 Instruction:"ROR Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC0 /1 ib"/"VMI" { .Instruction = ND_INS_ROR, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 762, + .Mnemonic = 764, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -60362,6 +62695,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -60376,12 +62710,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2166 Instruction:"ROR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC1 /1 ib"/"VMI" + // Pos:2172 Instruction:"ROR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC1 /1 ib"/"VMI" { .Instruction = ND_INS_ROR, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 762, + .Mnemonic = 764, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -60390,6 +62724,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -60404,12 +62739,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2167 Instruction:"ROR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xC1 /1 ib"/"VMI" + // Pos:2173 Instruction:"ROR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xC1 /1 ib"/"VMI" { .Instruction = ND_INS_ROR, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 762, + .Mnemonic = 764, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -60418,6 +62753,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -60432,12 +62768,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2168 Instruction:"ROR Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD0 /1"/"VM1" + // Pos:2174 Instruction:"ROR Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD0 /1"/"VM1" { .Instruction = ND_INS_ROR, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 762, + .Mnemonic = 764, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -60446,6 +62782,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -60460,12 +62797,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2169 Instruction:"ROR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD1 /1"/"VM1" + // Pos:2175 Instruction:"ROR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD1 /1"/"VM1" { .Instruction = ND_INS_ROR, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 762, + .Mnemonic = 764, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -60474,6 +62811,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -60488,12 +62826,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2170 Instruction:"ROR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD1 /1"/"VM1" + // Pos:2176 Instruction:"ROR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD1 /1"/"VM1" { .Instruction = ND_INS_ROR, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 762, + .Mnemonic = 764, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -60502,6 +62840,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -60516,12 +62855,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2171 Instruction:"ROR Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD2 /1"/"VMC" + // Pos:2177 Instruction:"ROR Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD2 /1"/"VMC" { .Instruction = ND_INS_ROR, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 762, + .Mnemonic = 764, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -60530,6 +62869,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -60544,12 +62884,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2172 Instruction:"ROR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD3 /1"/"VMC" + // Pos:2178 Instruction:"ROR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD3 /1"/"VMC" { .Instruction = ND_INS_ROR, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 762, + .Mnemonic = 764, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -60558,6 +62898,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -60572,12 +62913,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2173 Instruction:"ROR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD3 /1"/"VMC" + // Pos:2179 Instruction:"ROR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD3 /1"/"VMC" { .Instruction = ND_INS_ROR, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 762, + .Mnemonic = 764, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -60586,6 +62927,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -60600,12 +62942,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2174 Instruction:"ROR Eb,Ib" Encoding:"0xC0 /1 ib"/"MI" + // Pos:2180 Instruction:"ROR Eb,Ib" Encoding:"0xC0 /1 ib"/"MI" { .Instruction = ND_INS_ROR, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_I86, - .Mnemonic = 762, + .Mnemonic = 764, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -60614,6 +62956,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -60628,12 +62971,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2175 Instruction:"ROR Ev,Ib" Encoding:"0xC1 /1 ib"/"MI" + // Pos:2181 Instruction:"ROR Ev,Ib" Encoding:"0xC1 /1 ib"/"MI" { .Instruction = ND_INS_ROR, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_I86, - .Mnemonic = 762, + .Mnemonic = 764, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -60642,6 +62985,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -60656,12 +63000,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2176 Instruction:"ROR Eb,1" Encoding:"0xD0 /1"/"M1" + // Pos:2182 Instruction:"ROR Eb,1" Encoding:"0xD0 /1"/"M1" { .Instruction = ND_INS_ROR, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_I86, - .Mnemonic = 762, + .Mnemonic = 764, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -60670,6 +63014,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -60684,12 +63029,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2177 Instruction:"ROR Ev,1" Encoding:"0xD1 /1"/"M1" + // Pos:2183 Instruction:"ROR Ev,1" Encoding:"0xD1 /1"/"M1" { .Instruction = ND_INS_ROR, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_I86, - .Mnemonic = 762, + .Mnemonic = 764, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -60698,6 +63043,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -60712,12 +63058,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2178 Instruction:"ROR Eb,CL" Encoding:"0xD2 /1"/"MC" + // Pos:2184 Instruction:"ROR Eb,CL" Encoding:"0xD2 /1"/"MC" { .Instruction = ND_INS_ROR, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_I86, - .Mnemonic = 762, + .Mnemonic = 764, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -60726,6 +63072,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -60740,12 +63087,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2179 Instruction:"ROR Ev,CL" Encoding:"0xD3 /1"/"MC" + // Pos:2185 Instruction:"ROR Ev,CL" Encoding:"0xD3 /1"/"MC" { .Instruction = ND_INS_ROR, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_I86, - .Mnemonic = 762, + .Mnemonic = 764, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -60754,6 +63101,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, .SetFlags = 0, @@ -60768,12 +63116,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2180 Instruction:"RORX Gy,Ey,Ib" Encoding:"evex m:3 p:3 l:0 nd:0 nf:0 0xF0 /r ib"/"RMI" + // Pos:2186 Instruction:"RORX Gy,Ey,Ib" Encoding:"evex m:3 p:3 l:0 nd:0 nf:0 0xF0 /r ib"/"RMI" { .Instruction = ND_INS_RORX, .Category = ND_CAT_BMI2, .IsaSet = ND_SET_APX_F, - .Mnemonic = 763, + .Mnemonic = 765, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -60782,6 +63130,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_BMI, .FpuFlags = 0, .EvexMode = ND_EVEXM_VEX, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -60796,12 +63145,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2181 Instruction:"RORX Gy,Ey,Ib" Encoding:"vex m:3 p:3 l:0 w:x 0xF0 /r ib"/"RMI" + // Pos:2187 Instruction:"RORX Gy,Ey,Ib" Encoding:"vex m:3 p:3 l:0 w:x 0xF0 /r ib"/"RMI" { .Instruction = ND_INS_RORX, .Category = ND_CAT_BMI2, .IsaSet = ND_SET_BMI2, - .Mnemonic = 763, + .Mnemonic = 765, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -60810,6 +63159,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_13, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -60824,12 +63174,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2182 Instruction:"ROUNDPD Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x09 /r ib"/"RMI" + // Pos:2188 Instruction:"ROUNDPD Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x09 /r ib"/"RMI" { .Instruction = ND_INS_ROUNDPD, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE4, - .Mnemonic = 764, + .Mnemonic = 766, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -60838,6 +63188,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -60852,12 +63203,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2183 Instruction:"ROUNDPS Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x08 /r ib"/"RMI" + // Pos:2189 Instruction:"ROUNDPS Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x08 /r ib"/"RMI" { .Instruction = ND_INS_ROUNDPS, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE4, - .Mnemonic = 765, + .Mnemonic = 767, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -60866,6 +63217,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -60880,12 +63232,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2184 Instruction:"ROUNDSD Vsd,Wsd,Ib" Encoding:"0x66 0x0F 0x3A 0x0B /r ib"/"RMI" + // Pos:2190 Instruction:"ROUNDSD Vsd,Wsd,Ib" Encoding:"0x66 0x0F 0x3A 0x0B /r ib"/"RMI" { .Instruction = ND_INS_ROUNDSD, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE4, - .Mnemonic = 766, + .Mnemonic = 768, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -60894,6 +63246,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -60908,12 +63261,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2185 Instruction:"ROUNDSS Vss,Wss,Ib" Encoding:"0x66 0x0F 0x3A 0x0A /r ib"/"RMI" + // Pos:2191 Instruction:"ROUNDSS Vss,Wss,Ib" Encoding:"0x66 0x0F 0x3A 0x0A /r ib"/"RMI" { .Instruction = ND_INS_ROUNDSS, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE4, - .Mnemonic = 767, + .Mnemonic = 769, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -60922,6 +63275,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -60936,12 +63290,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2186 Instruction:"RSM" Encoding:"0x0F 0xAA"/"" + // Pos:2192 Instruction:"RSM" Encoding:"0x0F 0xAA"/"" { .Instruction = ND_INS_RSM, .Category = ND_CAT_SYSRET, .IsaSet = ND_SET_I486, - .Mnemonic = 768, + .Mnemonic = 770, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -60950,6 +63304,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -60964,12 +63319,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2187 Instruction:"RSQRTPS Vps,Wps" Encoding:"NP 0x0F 0x52 /r"/"RM" + // Pos:2193 Instruction:"RSQRTPS Vps,Wps" Encoding:"NP 0x0F 0x52 /r"/"RM" { .Instruction = ND_INS_RSQRTPS, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE, - .Mnemonic = 769, + .Mnemonic = 771, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -60978,6 +63333,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -60991,12 +63347,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2188 Instruction:"RSQRTSS Vss,Wss" Encoding:"0xF3 0x0F 0x52 /r"/"RM" + // Pos:2194 Instruction:"RSQRTSS Vss,Wss" Encoding:"0xF3 0x0F 0x52 /r"/"RM" { .Instruction = ND_INS_RSQRTSS, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE, - .Mnemonic = 770, + .Mnemonic = 772, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -61005,6 +63361,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -61018,12 +63375,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2189 Instruction:"RSTORSSP Mq" Encoding:"0xF3 0x0F 0x01 /5:mem"/"M" + // Pos:2195 Instruction:"RSTORSSP Mq" Encoding:"0xF3 0x0F 0x01 /5:mem"/"M" { .Instruction = ND_INS_RSTORSSP, .Category = ND_CAT_CET, .IsaSet = ND_SET_CET_SS, - .Mnemonic = 771, + .Mnemonic = 773, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -61032,6 +63389,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF, .SetFlags = 0, @@ -61045,12 +63403,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2190 Instruction:"SAHF" Encoding:"0x9E"/"" + // Pos:2196 Instruction:"SAHF" Encoding:"0x9E"/"" { .Instruction = ND_INS_SAHF, .Category = ND_CAT_FLAGOP, .IsaSet = ND_SET_I86, - .Mnemonic = 772, + .Mnemonic = 774, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -61059,6 +63417,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0, @@ -61072,12 +63431,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2191 Instruction:"SAL Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC0 /6 ib"/"MI" + // Pos:2197 Instruction:"SAL Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC0 /6 ib"/"MI" { .Instruction = ND_INS_SAL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 773, + .Mnemonic = 775, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -61086,6 +63445,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -61100,12 +63460,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2192 Instruction:"SAL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC1 /6 ib"/"MI" + // Pos:2198 Instruction:"SAL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC1 /6 ib"/"MI" { .Instruction = ND_INS_SAL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 773, + .Mnemonic = 775, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -61114,6 +63474,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -61128,12 +63489,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2193 Instruction:"SAL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xC1 /6 ib"/"MI" + // Pos:2199 Instruction:"SAL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xC1 /6 ib"/"MI" { .Instruction = ND_INS_SAL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 773, + .Mnemonic = 775, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -61142,6 +63503,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -61156,12 +63518,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2194 Instruction:"SAL Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD0 /6"/"M1" + // Pos:2200 Instruction:"SAL Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD0 /6"/"M1" { .Instruction = ND_INS_SAL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 773, + .Mnemonic = 775, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -61170,6 +63532,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -61184,12 +63547,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2195 Instruction:"SAL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD1 /6"/"M1" + // Pos:2201 Instruction:"SAL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD1 /6"/"M1" { .Instruction = ND_INS_SAL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 773, + .Mnemonic = 775, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -61198,6 +63561,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -61212,12 +63576,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2196 Instruction:"SAL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD1 /6"/"M1" + // Pos:2202 Instruction:"SAL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD1 /6"/"M1" { .Instruction = ND_INS_SAL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 773, + .Mnemonic = 775, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -61226,6 +63590,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -61240,12 +63605,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2197 Instruction:"SAL Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD2 /6"/"MC" + // Pos:2203 Instruction:"SAL Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD2 /6"/"MC" { .Instruction = ND_INS_SAL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 773, + .Mnemonic = 775, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -61254,6 +63619,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -61268,12 +63634,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2198 Instruction:"SAL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD3 /6"/"MC" + // Pos:2204 Instruction:"SAL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD3 /6"/"MC" { .Instruction = ND_INS_SAL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 773, + .Mnemonic = 775, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -61282,6 +63648,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -61296,12 +63663,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2199 Instruction:"SAL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD3 /6"/"MC" + // Pos:2205 Instruction:"SAL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD3 /6"/"MC" { .Instruction = ND_INS_SAL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 773, + .Mnemonic = 775, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -61310,6 +63677,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -61324,12 +63692,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2200 Instruction:"SAL Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC0 /6 ib"/"MI" + // Pos:2206 Instruction:"SAL Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC0 /6 ib"/"MI" { .Instruction = ND_INS_SAL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 773, + .Mnemonic = 775, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -61338,6 +63706,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -61351,12 +63720,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2201 Instruction:"SAL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC1 /6 ib"/"MI" + // Pos:2207 Instruction:"SAL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC1 /6 ib"/"MI" { .Instruction = ND_INS_SAL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 773, + .Mnemonic = 775, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -61365,6 +63734,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -61378,12 +63748,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2202 Instruction:"SAL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xC1 /6 ib"/"MI" + // Pos:2208 Instruction:"SAL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xC1 /6 ib"/"MI" { .Instruction = ND_INS_SAL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 773, + .Mnemonic = 775, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -61392,6 +63762,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -61405,12 +63776,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2203 Instruction:"SAL Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD0 /6"/"M1" + // Pos:2209 Instruction:"SAL Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD0 /6"/"M1" { .Instruction = ND_INS_SAL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 773, + .Mnemonic = 775, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -61419,6 +63790,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -61432,12 +63804,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2204 Instruction:"SAL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD1 /6"/"M1" + // Pos:2210 Instruction:"SAL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD1 /6"/"M1" { .Instruction = ND_INS_SAL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 773, + .Mnemonic = 775, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -61446,6 +63818,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -61459,12 +63832,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2205 Instruction:"SAL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD1 /6"/"M1" + // Pos:2211 Instruction:"SAL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD1 /6"/"M1" { .Instruction = ND_INS_SAL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 773, + .Mnemonic = 775, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -61473,6 +63846,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -61486,12 +63860,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2206 Instruction:"SAL Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD2 /6"/"MC" + // Pos:2212 Instruction:"SAL Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD2 /6"/"MC" { .Instruction = ND_INS_SAL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 773, + .Mnemonic = 775, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -61500,6 +63874,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -61513,12 +63888,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2207 Instruction:"SAL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD3 /6"/"MC" + // Pos:2213 Instruction:"SAL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD3 /6"/"MC" { .Instruction = ND_INS_SAL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 773, + .Mnemonic = 775, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -61527,6 +63902,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -61540,12 +63916,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2208 Instruction:"SAL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD3 /6"/"MC" + // Pos:2214 Instruction:"SAL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD3 /6"/"MC" { .Instruction = ND_INS_SAL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 773, + .Mnemonic = 775, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -61554,6 +63930,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -61567,12 +63944,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2209 Instruction:"SAL Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC0 /6 ib"/"VMI" + // Pos:2215 Instruction:"SAL Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC0 /6 ib"/"VMI" { .Instruction = ND_INS_SAL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 773, + .Mnemonic = 775, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -61581,6 +63958,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -61596,12 +63974,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2210 Instruction:"SAL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC1 /6 ib"/"VMI" + // Pos:2216 Instruction:"SAL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC1 /6 ib"/"VMI" { .Instruction = ND_INS_SAL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 773, + .Mnemonic = 775, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -61610,6 +63988,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -61625,12 +64004,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2211 Instruction:"SAL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xC1 /6 ib"/"VMI" + // Pos:2217 Instruction:"SAL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xC1 /6 ib"/"VMI" { .Instruction = ND_INS_SAL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 773, + .Mnemonic = 775, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -61639,6 +64018,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -61654,12 +64034,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2212 Instruction:"SAL Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD0 /6"/"VM1" + // Pos:2218 Instruction:"SAL Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD0 /6"/"VM1" { .Instruction = ND_INS_SAL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 773, + .Mnemonic = 775, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -61668,6 +64048,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -61683,12 +64064,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2213 Instruction:"SAL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD1 /6"/"VM1" + // Pos:2219 Instruction:"SAL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD1 /6"/"VM1" { .Instruction = ND_INS_SAL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 773, + .Mnemonic = 775, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -61697,6 +64078,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -61712,12 +64094,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2214 Instruction:"SAL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD1 /6"/"VM1" + // Pos:2220 Instruction:"SAL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD1 /6"/"VM1" { .Instruction = ND_INS_SAL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 773, + .Mnemonic = 775, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -61726,6 +64108,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -61741,12 +64124,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2215 Instruction:"SAL Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD2 /6"/"VMC" + // Pos:2221 Instruction:"SAL Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD2 /6"/"VMC" { .Instruction = ND_INS_SAL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 773, + .Mnemonic = 775, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -61755,6 +64138,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -61770,12 +64154,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2216 Instruction:"SAL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD3 /6"/"VMC" + // Pos:2222 Instruction:"SAL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD3 /6"/"VMC" { .Instruction = ND_INS_SAL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 773, + .Mnemonic = 775, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -61784,6 +64168,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -61799,12 +64184,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2217 Instruction:"SAL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD3 /6"/"VMC" + // Pos:2223 Instruction:"SAL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD3 /6"/"VMC" { .Instruction = ND_INS_SAL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 773, + .Mnemonic = 775, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -61813,6 +64198,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -61828,12 +64214,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2218 Instruction:"SAL Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC0 /6 ib"/"VMI" + // Pos:2224 Instruction:"SAL Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC0 /6 ib"/"VMI" { .Instruction = ND_INS_SAL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 773, + .Mnemonic = 775, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -61842,6 +64228,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -61856,12 +64243,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2219 Instruction:"SAL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC1 /6 ib"/"VMI" + // Pos:2225 Instruction:"SAL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC1 /6 ib"/"VMI" { .Instruction = ND_INS_SAL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 773, + .Mnemonic = 775, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -61870,6 +64257,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -61884,12 +64272,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2220 Instruction:"SAL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xC1 /6 ib"/"VMI" + // Pos:2226 Instruction:"SAL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xC1 /6 ib"/"VMI" { .Instruction = ND_INS_SAL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 773, + .Mnemonic = 775, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -61898,6 +64286,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -61912,12 +64301,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2221 Instruction:"SAL Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD0 /6"/"VM1" + // Pos:2227 Instruction:"SAL Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD0 /6"/"VM1" { .Instruction = ND_INS_SAL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 773, + .Mnemonic = 775, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -61926,6 +64315,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -61940,12 +64330,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2222 Instruction:"SAL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD1 /6"/"VM1" + // Pos:2228 Instruction:"SAL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD1 /6"/"VM1" { .Instruction = ND_INS_SAL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 773, + .Mnemonic = 775, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -61954,6 +64344,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -61968,12 +64359,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2223 Instruction:"SAL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD1 /6"/"VM1" + // Pos:2229 Instruction:"SAL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD1 /6"/"VM1" { .Instruction = ND_INS_SAL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 773, + .Mnemonic = 775, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -61982,6 +64373,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -61996,12 +64388,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2224 Instruction:"SAL Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD2 /6"/"VMC" + // Pos:2230 Instruction:"SAL Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD2 /6"/"VMC" { .Instruction = ND_INS_SAL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 773, + .Mnemonic = 775, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -62010,6 +64402,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -62024,12 +64417,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2225 Instruction:"SAL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD3 /6"/"VMC" + // Pos:2231 Instruction:"SAL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD3 /6"/"VMC" { .Instruction = ND_INS_SAL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 773, + .Mnemonic = 775, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -62038,6 +64431,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -62052,12 +64446,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2226 Instruction:"SAL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD3 /6"/"VMC" + // Pos:2232 Instruction:"SAL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD3 /6"/"VMC" { .Instruction = ND_INS_SAL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 773, + .Mnemonic = 775, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -62066,6 +64460,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -62080,12 +64475,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2227 Instruction:"SAL Eb,Ib" Encoding:"0xC0 /6 ib"/"MI" + // Pos:2233 Instruction:"SAL Eb,Ib" Encoding:"0xC0 /6 ib"/"MI" { .Instruction = ND_INS_SAL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_I86, - .Mnemonic = 773, + .Mnemonic = 775, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -62094,6 +64489,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -62108,12 +64504,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2228 Instruction:"SAL Ev,Ib" Encoding:"0xC1 /6 ib"/"MI" + // Pos:2234 Instruction:"SAL Ev,Ib" Encoding:"0xC1 /6 ib"/"MI" { .Instruction = ND_INS_SAL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_I86, - .Mnemonic = 773, + .Mnemonic = 775, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -62122,6 +64518,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -62136,12 +64533,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2229 Instruction:"SAL Eb,1" Encoding:"0xD0 /6"/"M1" + // Pos:2235 Instruction:"SAL Eb,1" Encoding:"0xD0 /6"/"M1" { .Instruction = ND_INS_SAL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_I86, - .Mnemonic = 773, + .Mnemonic = 775, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -62150,6 +64547,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -62164,12 +64562,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2230 Instruction:"SAL Ev,1" Encoding:"0xD1 /6"/"M1" + // Pos:2236 Instruction:"SAL Ev,1" Encoding:"0xD1 /6"/"M1" { .Instruction = ND_INS_SAL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_I86, - .Mnemonic = 773, + .Mnemonic = 775, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -62178,6 +64576,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -62192,12 +64591,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2231 Instruction:"SAL Eb,CL" Encoding:"0xD2 /6"/"MC" + // Pos:2237 Instruction:"SAL Eb,CL" Encoding:"0xD2 /6"/"MC" { .Instruction = ND_INS_SAL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_I86, - .Mnemonic = 773, + .Mnemonic = 775, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -62206,6 +64605,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -62220,12 +64620,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2232 Instruction:"SAL Ev,CL" Encoding:"0xD3 /6"/"MC" + // Pos:2238 Instruction:"SAL Ev,CL" Encoding:"0xD3 /6"/"MC" { .Instruction = ND_INS_SAL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_I86, - .Mnemonic = 773, + .Mnemonic = 775, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -62234,6 +64634,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -62248,12 +64649,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2233 Instruction:"SALC" Encoding:"0xD6"/"" + // Pos:2239 Instruction:"SALC" Encoding:"0xD6"/"" { .Instruction = ND_INS_SALC, .Category = ND_CAT_FLAGOP, .IsaSet = ND_SET_I86, - .Mnemonic = 774, + .Mnemonic = 776, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -62262,6 +64663,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0, .SetFlags = 0, @@ -62275,12 +64677,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2234 Instruction:"SAR Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC0 /7 ib"/"MI" + // Pos:2240 Instruction:"SAR Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC0 /7 ib"/"MI" { .Instruction = ND_INS_SAR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 775, + .Mnemonic = 777, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -62289,6 +64691,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -62303,12 +64706,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2235 Instruction:"SAR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC1 /7 ib"/"MI" + // Pos:2241 Instruction:"SAR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC1 /7 ib"/"MI" { .Instruction = ND_INS_SAR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 775, + .Mnemonic = 777, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -62317,6 +64720,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -62331,12 +64735,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2236 Instruction:"SAR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xC1 /7 ib"/"MI" + // Pos:2242 Instruction:"SAR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xC1 /7 ib"/"MI" { .Instruction = ND_INS_SAR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 775, + .Mnemonic = 777, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -62345,6 +64749,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -62359,12 +64764,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2237 Instruction:"SAR Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD0 /7"/"M1" + // Pos:2243 Instruction:"SAR Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD0 /7"/"M1" { .Instruction = ND_INS_SAR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 775, + .Mnemonic = 777, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -62373,6 +64778,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -62387,12 +64793,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2238 Instruction:"SAR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD1 /7"/"M1" + // Pos:2244 Instruction:"SAR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD1 /7"/"M1" { .Instruction = ND_INS_SAR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 775, + .Mnemonic = 777, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -62401,6 +64807,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -62415,12 +64822,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2239 Instruction:"SAR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD1 /7"/"M1" + // Pos:2245 Instruction:"SAR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD1 /7"/"M1" { .Instruction = ND_INS_SAR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 775, + .Mnemonic = 777, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -62429,6 +64836,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -62443,12 +64851,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2240 Instruction:"SAR Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD2 /7"/"MC" + // Pos:2246 Instruction:"SAR Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD2 /7"/"MC" { .Instruction = ND_INS_SAR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 775, + .Mnemonic = 777, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -62457,6 +64865,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -62471,12 +64880,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2241 Instruction:"SAR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD3 /7"/"MC" + // Pos:2247 Instruction:"SAR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD3 /7"/"MC" { .Instruction = ND_INS_SAR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 775, + .Mnemonic = 777, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -62485,6 +64894,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -62499,12 +64909,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2242 Instruction:"SAR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD3 /7"/"MC" + // Pos:2248 Instruction:"SAR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD3 /7"/"MC" { .Instruction = ND_INS_SAR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 775, + .Mnemonic = 777, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -62513,6 +64923,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -62527,12 +64938,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2243 Instruction:"SAR Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC0 /7 ib"/"MI" + // Pos:2249 Instruction:"SAR Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC0 /7 ib"/"MI" { .Instruction = ND_INS_SAR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 775, + .Mnemonic = 777, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -62541,6 +64952,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -62554,12 +64966,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2244 Instruction:"SAR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC1 /7 ib"/"MI" + // Pos:2250 Instruction:"SAR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC1 /7 ib"/"MI" { .Instruction = ND_INS_SAR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 775, + .Mnemonic = 777, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -62568,6 +64980,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -62581,12 +64994,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2245 Instruction:"SAR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xC1 /7 ib"/"MI" + // Pos:2251 Instruction:"SAR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xC1 /7 ib"/"MI" { .Instruction = ND_INS_SAR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 775, + .Mnemonic = 777, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -62595,6 +65008,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -62608,12 +65022,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2246 Instruction:"SAR Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD0 /7"/"M1" + // Pos:2252 Instruction:"SAR Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD0 /7"/"M1" { .Instruction = ND_INS_SAR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 775, + .Mnemonic = 777, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -62622,6 +65036,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -62635,12 +65050,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2247 Instruction:"SAR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD1 /7"/"M1" + // Pos:2253 Instruction:"SAR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD1 /7"/"M1" { .Instruction = ND_INS_SAR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 775, + .Mnemonic = 777, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -62649,6 +65064,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -62662,12 +65078,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2248 Instruction:"SAR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD1 /7"/"M1" + // Pos:2254 Instruction:"SAR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD1 /7"/"M1" { .Instruction = ND_INS_SAR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 775, + .Mnemonic = 777, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -62676,6 +65092,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -62689,12 +65106,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2249 Instruction:"SAR Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD2 /7"/"MC" + // Pos:2255 Instruction:"SAR Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD2 /7"/"MC" { .Instruction = ND_INS_SAR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 775, + .Mnemonic = 777, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -62703,6 +65120,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -62716,12 +65134,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2250 Instruction:"SAR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD3 /7"/"MC" + // Pos:2256 Instruction:"SAR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD3 /7"/"MC" { .Instruction = ND_INS_SAR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 775, + .Mnemonic = 777, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -62730,6 +65148,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -62743,12 +65162,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2251 Instruction:"SAR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD3 /7"/"MC" + // Pos:2257 Instruction:"SAR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD3 /7"/"MC" { .Instruction = ND_INS_SAR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 775, + .Mnemonic = 777, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -62757,6 +65176,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -62770,12 +65190,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2252 Instruction:"SAR Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC0 /7 ib"/"VMI" + // Pos:2258 Instruction:"SAR Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC0 /7 ib"/"VMI" { .Instruction = ND_INS_SAR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 775, + .Mnemonic = 777, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -62784,6 +65204,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -62799,12 +65220,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2253 Instruction:"SAR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC1 /7 ib"/"VMI" + // Pos:2259 Instruction:"SAR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC1 /7 ib"/"VMI" { .Instruction = ND_INS_SAR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 775, + .Mnemonic = 777, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -62813,6 +65234,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -62828,12 +65250,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2254 Instruction:"SAR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xC1 /7 ib"/"VMI" + // Pos:2260 Instruction:"SAR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xC1 /7 ib"/"VMI" { .Instruction = ND_INS_SAR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 775, + .Mnemonic = 777, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -62842,6 +65264,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -62857,12 +65280,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2255 Instruction:"SAR Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD0 /7"/"VM1" + // Pos:2261 Instruction:"SAR Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD0 /7"/"VM1" { .Instruction = ND_INS_SAR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 775, + .Mnemonic = 777, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -62871,6 +65294,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -62886,12 +65310,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2256 Instruction:"SAR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD1 /7"/"VM1" + // Pos:2262 Instruction:"SAR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD1 /7"/"VM1" { .Instruction = ND_INS_SAR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 775, + .Mnemonic = 777, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -62900,6 +65324,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -62915,12 +65340,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2257 Instruction:"SAR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD1 /7"/"VM1" + // Pos:2263 Instruction:"SAR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD1 /7"/"VM1" { .Instruction = ND_INS_SAR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 775, + .Mnemonic = 777, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -62929,6 +65354,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -62944,12 +65370,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2258 Instruction:"SAR Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD2 /7"/"VMC" + // Pos:2264 Instruction:"SAR Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD2 /7"/"VMC" { .Instruction = ND_INS_SAR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 775, + .Mnemonic = 777, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -62958,6 +65384,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -62973,12 +65400,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2259 Instruction:"SAR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD3 /7"/"VMC" + // Pos:2265 Instruction:"SAR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD3 /7"/"VMC" { .Instruction = ND_INS_SAR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 775, + .Mnemonic = 777, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -62987,6 +65414,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -63002,12 +65430,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2260 Instruction:"SAR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD3 /7"/"VMC" + // Pos:2266 Instruction:"SAR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD3 /7"/"VMC" { .Instruction = ND_INS_SAR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 775, + .Mnemonic = 777, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -63016,6 +65444,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -63031,12 +65460,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2261 Instruction:"SAR Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC0 /7 ib"/"VMI" + // Pos:2267 Instruction:"SAR Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC0 /7 ib"/"VMI" { .Instruction = ND_INS_SAR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 775, + .Mnemonic = 777, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -63045,6 +65474,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -63059,12 +65489,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2262 Instruction:"SAR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC1 /7 ib"/"VMI" + // Pos:2268 Instruction:"SAR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC1 /7 ib"/"VMI" { .Instruction = ND_INS_SAR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 775, + .Mnemonic = 777, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -63073,6 +65503,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -63087,12 +65518,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2263 Instruction:"SAR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xC1 /7 ib"/"VMI" + // Pos:2269 Instruction:"SAR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xC1 /7 ib"/"VMI" { .Instruction = ND_INS_SAR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 775, + .Mnemonic = 777, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -63101,6 +65532,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -63115,12 +65547,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2264 Instruction:"SAR Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD0 /7"/"VM1" + // Pos:2270 Instruction:"SAR Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD0 /7"/"VM1" { .Instruction = ND_INS_SAR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 775, + .Mnemonic = 777, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -63129,6 +65561,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -63143,12 +65576,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2265 Instruction:"SAR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD1 /7"/"VM1" + // Pos:2271 Instruction:"SAR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD1 /7"/"VM1" { .Instruction = ND_INS_SAR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 775, + .Mnemonic = 777, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -63157,6 +65590,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -63171,12 +65605,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2266 Instruction:"SAR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD1 /7"/"VM1" + // Pos:2272 Instruction:"SAR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD1 /7"/"VM1" { .Instruction = ND_INS_SAR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 775, + .Mnemonic = 777, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -63185,6 +65619,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -63199,12 +65634,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2267 Instruction:"SAR Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD2 /7"/"VMC" + // Pos:2273 Instruction:"SAR Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD2 /7"/"VMC" { .Instruction = ND_INS_SAR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 775, + .Mnemonic = 777, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -63213,6 +65648,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -63227,12 +65663,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2268 Instruction:"SAR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD3 /7"/"VMC" + // Pos:2274 Instruction:"SAR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD3 /7"/"VMC" { .Instruction = ND_INS_SAR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 775, + .Mnemonic = 777, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -63241,6 +65677,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -63255,12 +65692,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2269 Instruction:"SAR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD3 /7"/"VMC" + // Pos:2275 Instruction:"SAR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD3 /7"/"VMC" { .Instruction = ND_INS_SAR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 775, + .Mnemonic = 777, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -63269,6 +65706,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -63283,12 +65721,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2270 Instruction:"SAR Eb,Ib" Encoding:"0xC0 /7 ib"/"MI" + // Pos:2276 Instruction:"SAR Eb,Ib" Encoding:"0xC0 /7 ib"/"MI" { .Instruction = ND_INS_SAR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_I86, - .Mnemonic = 775, + .Mnemonic = 777, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -63297,6 +65735,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -63311,12 +65750,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2271 Instruction:"SAR Ev,Ib" Encoding:"0xC1 /7 ib"/"MI" + // Pos:2277 Instruction:"SAR Ev,Ib" Encoding:"0xC1 /7 ib"/"MI" { .Instruction = ND_INS_SAR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_I86, - .Mnemonic = 775, + .Mnemonic = 777, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -63325,6 +65764,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -63339,12 +65779,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2272 Instruction:"SAR Eb,1" Encoding:"0xD0 /7"/"M1" + // Pos:2278 Instruction:"SAR Eb,1" Encoding:"0xD0 /7"/"M1" { .Instruction = ND_INS_SAR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_I86, - .Mnemonic = 775, + .Mnemonic = 777, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -63353,6 +65793,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -63367,12 +65808,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2273 Instruction:"SAR Ev,1" Encoding:"0xD1 /7"/"M1" + // Pos:2279 Instruction:"SAR Ev,1" Encoding:"0xD1 /7"/"M1" { .Instruction = ND_INS_SAR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_I86, - .Mnemonic = 775, + .Mnemonic = 777, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -63381,6 +65822,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -63395,12 +65837,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2274 Instruction:"SAR Eb,CL" Encoding:"0xD2 /7"/"MC" + // Pos:2280 Instruction:"SAR Eb,CL" Encoding:"0xD2 /7"/"MC" { .Instruction = ND_INS_SAR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_I86, - .Mnemonic = 775, + .Mnemonic = 777, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -63409,6 +65851,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -63423,12 +65866,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2275 Instruction:"SAR Ev,CL" Encoding:"0xD3 /7"/"MC" + // Pos:2281 Instruction:"SAR Ev,CL" Encoding:"0xD3 /7"/"MC" { .Instruction = ND_INS_SAR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_I86, - .Mnemonic = 775, + .Mnemonic = 777, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -63437,6 +65880,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -63451,12 +65895,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2276 Instruction:"SARX Gy,Ey,By" Encoding:"evex m:2 p:2 l:0 nf:0 0xF7 /r"/"RMV" + // Pos:2282 Instruction:"SARX Gy,Ey,By" Encoding:"evex m:2 p:2 l:0 nf:0 0xF7 /r"/"RMV" { .Instruction = ND_INS_SARX, .Category = ND_CAT_BMI2, .IsaSet = ND_SET_APX_F, - .Mnemonic = 776, + .Mnemonic = 778, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -63465,6 +65909,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_BMI, .FpuFlags = 0, .EvexMode = ND_EVEXM_VEX, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -63479,12 +65924,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2277 Instruction:"SARX Gy,Ey,By" Encoding:"vex m:2 p:2 l:0 w:x 0xF7 /r"/"RMV" + // Pos:2283 Instruction:"SARX Gy,Ey,By" Encoding:"vex m:2 p:2 l:0 w:x 0xF7 /r"/"RMV" { .Instruction = ND_INS_SARX, .Category = ND_CAT_BMI2, .IsaSet = ND_SET_BMI2, - .Mnemonic = 776, + .Mnemonic = 778, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -63493,6 +65938,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_13, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -63507,12 +65953,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2278 Instruction:"SAVEPREVSSP" Encoding:"0xF3 0x0F 0x01 /0xEA"/"" + // Pos:2284 Instruction:"SAVEPREVSSP" Encoding:"0xF3 0x0F 0x01 /0xEA"/"" { .Instruction = ND_INS_SAVEPREVSSP, .Category = ND_CAT_CET, .IsaSet = ND_SET_CET_SS, - .Mnemonic = 777, + .Mnemonic = 779, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -63521,6 +65967,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0, .SetFlags = 0, @@ -63534,12 +65981,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2279 Instruction:"SBB Eb,Gb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x18 /r"/"MR" + // Pos:2285 Instruction:"SBB Eb,Gb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x18 /r"/"MR" { .Instruction = ND_INS_SBB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 778, + .Mnemonic = 780, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -63548,6 +65995,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -63562,12 +66010,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2280 Instruction:"SBB Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x19 /r"/"MR" + // Pos:2286 Instruction:"SBB Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x19 /r"/"MR" { .Instruction = ND_INS_SBB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 778, + .Mnemonic = 780, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -63576,6 +66024,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -63590,12 +66039,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2281 Instruction:"SBB Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x19 /r"/"MR" + // Pos:2287 Instruction:"SBB Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x19 /r"/"MR" { .Instruction = ND_INS_SBB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 778, + .Mnemonic = 780, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -63604,6 +66053,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -63618,12 +66068,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2282 Instruction:"SBB Gb,Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x1A /r"/"RM" + // Pos:2288 Instruction:"SBB Gb,Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x1A /r"/"RM" { .Instruction = ND_INS_SBB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 778, + .Mnemonic = 780, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -63632,6 +66082,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -63646,12 +66097,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2283 Instruction:"SBB Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x1B /r"/"RM" + // Pos:2289 Instruction:"SBB Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x1B /r"/"RM" { .Instruction = ND_INS_SBB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 778, + .Mnemonic = 780, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -63660,6 +66111,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -63674,12 +66126,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2284 Instruction:"SBB Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x1B /r"/"RM" + // Pos:2290 Instruction:"SBB Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x1B /r"/"RM" { .Instruction = ND_INS_SBB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 778, + .Mnemonic = 780, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -63688,6 +66140,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -63702,12 +66155,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2285 Instruction:"SBB Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x80 /3 ib"/"MI" + // Pos:2291 Instruction:"SBB Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x80 /3 ib"/"MI" { .Instruction = ND_INS_SBB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 778, + .Mnemonic = 780, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -63716,6 +66169,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -63730,12 +66184,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2286 Instruction:"SBB Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x81 /3 iz"/"MI" + // Pos:2292 Instruction:"SBB Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x81 /3 iz"/"MI" { .Instruction = ND_INS_SBB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 778, + .Mnemonic = 780, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -63744,6 +66198,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -63758,12 +66213,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2287 Instruction:"SBB Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x81 /3 iz"/"MI" + // Pos:2293 Instruction:"SBB Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x81 /3 iz"/"MI" { .Instruction = ND_INS_SBB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 778, + .Mnemonic = 780, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -63772,6 +66227,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -63786,12 +66242,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2288 Instruction:"SBB Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x83 /3 ib"/"MI" + // Pos:2294 Instruction:"SBB Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x83 /3 ib"/"MI" { .Instruction = ND_INS_SBB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 778, + .Mnemonic = 780, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -63800,6 +66256,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -63814,12 +66271,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2289 Instruction:"SBB Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x83 /3 ib"/"MI" + // Pos:2295 Instruction:"SBB Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x83 /3 ib"/"MI" { .Instruction = ND_INS_SBB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 778, + .Mnemonic = 780, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -63828,6 +66285,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -63842,12 +66300,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2290 Instruction:"SBB Bb,Eb,Gb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x18 /r"/"VMR" + // Pos:2296 Instruction:"SBB Bb,Eb,Gb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x18 /r"/"VMR" { .Instruction = ND_INS_SBB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 778, + .Mnemonic = 780, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -63856,6 +66314,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -63871,12 +66330,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2291 Instruction:"SBB Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x19 /r"/"VMR" + // Pos:2297 Instruction:"SBB Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x19 /r"/"VMR" { .Instruction = ND_INS_SBB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 778, + .Mnemonic = 780, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -63885,6 +66344,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -63900,12 +66360,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2292 Instruction:"SBB Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x19 /r"/"VMR" + // Pos:2298 Instruction:"SBB Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x19 /r"/"VMR" { .Instruction = ND_INS_SBB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 778, + .Mnemonic = 780, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -63914,6 +66374,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -63929,12 +66390,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2293 Instruction:"SBB Bb,Gb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x1A /r"/"VRM" + // Pos:2299 Instruction:"SBB Bb,Gb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x1A /r"/"VRM" { .Instruction = ND_INS_SBB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 778, + .Mnemonic = 780, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -63943,6 +66404,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -63958,12 +66420,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2294 Instruction:"SBB Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x1B /r"/"VRM" + // Pos:2300 Instruction:"SBB Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x1B /r"/"VRM" { .Instruction = ND_INS_SBB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 778, + .Mnemonic = 780, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -63972,6 +66434,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -63987,12 +66450,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2295 Instruction:"SBB Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x1B /r"/"VRM" + // Pos:2301 Instruction:"SBB Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x1B /r"/"VRM" { .Instruction = ND_INS_SBB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 778, + .Mnemonic = 780, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -64001,6 +66464,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -64016,12 +66480,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2296 Instruction:"SBB Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x80 /3 ib"/"VMI" + // Pos:2302 Instruction:"SBB Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x80 /3 ib"/"VMI" { .Instruction = ND_INS_SBB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 778, + .Mnemonic = 780, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -64030,6 +66494,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -64045,12 +66510,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2297 Instruction:"SBB Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x81 /3 iz"/"VMI" + // Pos:2303 Instruction:"SBB Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x81 /3 iz"/"VMI" { .Instruction = ND_INS_SBB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 778, + .Mnemonic = 780, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -64059,6 +66524,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -64074,12 +66540,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2298 Instruction:"SBB Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x81 /3 iz"/"VMI" + // Pos:2304 Instruction:"SBB Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x81 /3 iz"/"VMI" { .Instruction = ND_INS_SBB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 778, + .Mnemonic = 780, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -64088,6 +66554,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -64103,12 +66570,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2299 Instruction:"SBB Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x83 /3 ib"/"VMI" + // Pos:2305 Instruction:"SBB Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x83 /3 ib"/"VMI" { .Instruction = ND_INS_SBB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 778, + .Mnemonic = 780, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -64117,6 +66584,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -64132,12 +66600,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2300 Instruction:"SBB Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x83 /3 ib"/"VMI" + // Pos:2306 Instruction:"SBB Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x83 /3 ib"/"VMI" { .Instruction = ND_INS_SBB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 778, + .Mnemonic = 780, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -64146,6 +66614,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -64161,12 +66630,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2301 Instruction:"SBB Eb,Gb" Encoding:"0x18 /r"/"MR" + // Pos:2307 Instruction:"SBB Eb,Gb" Encoding:"0x18 /r"/"MR" { .Instruction = ND_INS_SBB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_I86, - .Mnemonic = 778, + .Mnemonic = 780, .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -64175,6 +66644,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -64189,12 +66659,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2302 Instruction:"SBB Ev,Gv" Encoding:"0x19 /r"/"MR" + // Pos:2308 Instruction:"SBB Ev,Gv" Encoding:"0x19 /r"/"MR" { .Instruction = ND_INS_SBB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_I86, - .Mnemonic = 778, + .Mnemonic = 780, .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -64203,6 +66673,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -64217,12 +66688,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2303 Instruction:"SBB Gb,Eb" Encoding:"0x1A /r"/"RM" + // Pos:2309 Instruction:"SBB Gb,Eb" Encoding:"0x1A /r"/"RM" { .Instruction = ND_INS_SBB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_I86, - .Mnemonic = 778, + .Mnemonic = 780, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -64231,6 +66702,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -64245,12 +66717,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2304 Instruction:"SBB Gv,Ev" Encoding:"0x1B /r"/"RM" + // Pos:2310 Instruction:"SBB Gv,Ev" Encoding:"0x1B /r"/"RM" { .Instruction = ND_INS_SBB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_I86, - .Mnemonic = 778, + .Mnemonic = 780, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -64259,6 +66731,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -64273,12 +66746,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2305 Instruction:"SBB AL,Ib" Encoding:"0x1C ib"/"I" + // Pos:2311 Instruction:"SBB AL,Ib" Encoding:"0x1C ib"/"I" { .Instruction = ND_INS_SBB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_I86, - .Mnemonic = 778, + .Mnemonic = 780, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -64287,6 +66760,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -64301,12 +66775,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2306 Instruction:"SBB rAX,Iz" Encoding:"0x1D iz"/"I" + // Pos:2312 Instruction:"SBB rAX,Iz" Encoding:"0x1D iz"/"I" { .Instruction = ND_INS_SBB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_I86, - .Mnemonic = 778, + .Mnemonic = 780, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -64315,6 +66789,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -64329,12 +66804,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2307 Instruction:"SBB Eb,Ib" Encoding:"0x80 /3 ib"/"MI" + // Pos:2313 Instruction:"SBB Eb,Ib" Encoding:"0x80 /3 ib"/"MI" { .Instruction = ND_INS_SBB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_I86, - .Mnemonic = 778, + .Mnemonic = 780, .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -64343,6 +66818,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -64357,12 +66833,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2308 Instruction:"SBB Ev,Iz" Encoding:"0x81 /3 iz"/"MI" + // Pos:2314 Instruction:"SBB Ev,Iz" Encoding:"0x81 /3 iz"/"MI" { .Instruction = ND_INS_SBB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_I86, - .Mnemonic = 778, + .Mnemonic = 780, .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -64371,6 +66847,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -64385,12 +66862,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2309 Instruction:"SBB Eb,Ib" Encoding:"0x82 /3 iz"/"MI" + // Pos:2315 Instruction:"SBB Eb,Ib" Encoding:"0x82 /3 iz"/"MI" { .Instruction = ND_INS_SBB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_I86, - .Mnemonic = 778, + .Mnemonic = 780, .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -64399,6 +66876,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -64413,12 +66891,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2310 Instruction:"SBB Ev,Ib" Encoding:"0x83 /3 ib"/"MI" + // Pos:2316 Instruction:"SBB Ev,Ib" Encoding:"0x83 /3 ib"/"MI" { .Instruction = ND_INS_SBB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_I86, - .Mnemonic = 778, + .Mnemonic = 780, .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -64427,6 +66905,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -64441,12 +66920,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2311 Instruction:"SCASB AL,Yb" Encoding:"0xAE"/"" + // Pos:2317 Instruction:"SCASB AL,Yb" Encoding:"0xAE"/"" { .Instruction = ND_INS_SCAS, .Category = ND_CAT_STRINGOP, .IsaSet = ND_SET_I86, - .Mnemonic = 779, + .Mnemonic = 781, .ValidPrefixes = ND_PREF_REPC, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -64455,6 +66934,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_DF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -64470,12 +66950,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2312 Instruction:"SCASB AL,Yb" Encoding:"rep 0xAE"/"" + // Pos:2318 Instruction:"SCASB AL,Yb" Encoding:"rep 0xAE"/"" { .Instruction = ND_INS_SCAS, .Category = ND_CAT_STRINGOP, .IsaSet = ND_SET_I86, - .Mnemonic = 779, + .Mnemonic = 781, .ValidPrefixes = ND_PREF_REPC, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -64484,6 +66964,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_ZF|NDR_RFLAG_DF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -64500,12 +66981,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2313 Instruction:"SCASD EAX,Yv" Encoding:"ds32 0xAF"/"" + // Pos:2319 Instruction:"SCASD EAX,Yv" Encoding:"ds32 0xAF"/"" { .Instruction = ND_INS_SCAS, .Category = ND_CAT_STRINGOP, .IsaSet = ND_SET_I86, - .Mnemonic = 780, + .Mnemonic = 782, .ValidPrefixes = ND_PREF_REPC, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -64514,6 +66995,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_DF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -64529,12 +67011,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2314 Instruction:"SCASD EAX,Yv" Encoding:"rep ds32 0xAF"/"" + // Pos:2320 Instruction:"SCASD EAX,Yv" Encoding:"rep ds32 0xAF"/"" { .Instruction = ND_INS_SCAS, .Category = ND_CAT_STRINGOP, .IsaSet = ND_SET_I86, - .Mnemonic = 780, + .Mnemonic = 782, .ValidPrefixes = ND_PREF_REPC, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -64543,6 +67025,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_ZF|NDR_RFLAG_DF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -64559,12 +67042,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2315 Instruction:"SCASQ RAX,Yv" Encoding:"ds64 0xAF"/"" + // Pos:2321 Instruction:"SCASQ RAX,Yv" Encoding:"ds64 0xAF"/"" { .Instruction = ND_INS_SCAS, .Category = ND_CAT_STRINGOP, .IsaSet = ND_SET_I86, - .Mnemonic = 781, + .Mnemonic = 783, .ValidPrefixes = ND_PREF_REPC, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -64573,6 +67056,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_DF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -64588,12 +67072,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2316 Instruction:"SCASQ RAX,Yv" Encoding:"rep ds64 0xAF"/"" + // Pos:2322 Instruction:"SCASQ RAX,Yv" Encoding:"rep ds64 0xAF"/"" { .Instruction = ND_INS_SCAS, .Category = ND_CAT_STRINGOP, .IsaSet = ND_SET_I86, - .Mnemonic = 781, + .Mnemonic = 783, .ValidPrefixes = ND_PREF_REPC, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -64602,6 +67086,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_ZF|NDR_RFLAG_DF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -64618,12 +67103,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2317 Instruction:"SCASW AX,Yv" Encoding:"ds16 0xAF"/"" + // Pos:2323 Instruction:"SCASW AX,Yv" Encoding:"ds16 0xAF"/"" { .Instruction = ND_INS_SCAS, .Category = ND_CAT_STRINGOP, .IsaSet = ND_SET_I86, - .Mnemonic = 782, + .Mnemonic = 784, .ValidPrefixes = ND_PREF_REPC, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -64632,6 +67117,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_DF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -64647,12 +67133,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2318 Instruction:"SCASW AX,Yv" Encoding:"rep ds16 0xAF"/"" + // Pos:2324 Instruction:"SCASW AX,Yv" Encoding:"rep ds16 0xAF"/"" { .Instruction = ND_INS_SCAS, .Category = ND_CAT_STRINGOP, .IsaSet = ND_SET_I86, - .Mnemonic = 782, + .Mnemonic = 784, .ValidPrefixes = ND_PREF_REPC, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -64661,6 +67147,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_ZF|NDR_RFLAG_DF, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -64677,12 +67164,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2319 Instruction:"SEAMCALL" Encoding:"0x66 0x0F 0x01 /0xCF"/"" + // Pos:2325 Instruction:"SEAMCALL" Encoding:"0x66 0x0F 0x01 /0xCF"/"" { .Instruction = ND_INS_SEAMCALL, .Category = ND_CAT_TDX, .IsaSet = ND_SET_TDX, - .Mnemonic = 783, + .Mnemonic = 785, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXN_SEAM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -64691,6 +67178,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .SetFlags = 0, @@ -64703,12 +67191,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2320 Instruction:"SEAMOPS" Encoding:"0x66 0x0F 0x01 /0xCE"/"" + // Pos:2326 Instruction:"SEAMOPS" Encoding:"0x66 0x0F 0x01 /0xCE"/"" { .Instruction = ND_INS_SEAMOPS, .Category = ND_CAT_TDX, .IsaSet = ND_SET_TDX, - .Mnemonic = 784, + .Mnemonic = 786, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -64717,6 +67205,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -64733,12 +67222,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2321 Instruction:"SEAMRET" Encoding:"0x66 0x0F 0x01 /0xCD"/"" + // Pos:2327 Instruction:"SEAMRET" Encoding:"0x66 0x0F 0x01 /0xCD"/"" { .Instruction = ND_INS_SEAMRET, .Category = ND_CAT_TDX, .IsaSet = ND_SET_TDX, - .Mnemonic = 785, + .Mnemonic = 787, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -64747,6 +67236,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .SetFlags = 0, @@ -64759,12 +67249,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2322 Instruction:"SENDUIPI Rq" Encoding:"0xF3 0x0F 0xC7 /6:reg"/"M" + // Pos:2328 Instruction:"SENDUIPI Rq" Encoding:"0xF3 0x0F 0xC7 /6:reg"/"M" { .Instruction = ND_INS_SENDUIPI, .Category = ND_CAT_UINTR, .IsaSet = ND_SET_UINTR, - .Mnemonic = 786, + .Mnemonic = 788, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -64773,6 +67263,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -64785,12 +67276,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2323 Instruction:"SERIALIZE" Encoding:"NP 0x0F 0x01 /0xE8"/"" + // Pos:2329 Instruction:"SERIALIZE" Encoding:"NP 0x0F 0x01 /0xE8"/"" { .Instruction = ND_INS_SERIALIZE, .Category = ND_CAT_MISC, .IsaSet = ND_SET_SERIALIZE, - .Mnemonic = 787, + .Mnemonic = 789, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -64799,6 +67290,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -64811,12 +67303,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2324 Instruction:"SETBE Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x46 /r"/"M" + // Pos:2330 Instruction:"SETBE Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x46 /r"/"M" { .Instruction = ND_INS_SETcc, .Category = ND_CAT_BITBYTE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 788, + .Mnemonic = 790, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ZU, @@ -64825,6 +67317,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -64838,12 +67331,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2325 Instruction:"SETBE Eb" Encoding:"0x0F 0x96 /r"/"M" + // Pos:2331 Instruction:"SETBE Eb" Encoding:"0x0F 0x96 /r"/"M" { .Instruction = ND_INS_SETcc, .Category = ND_CAT_BITBYTE, .IsaSet = ND_SET_I386, - .Mnemonic = 788, + .Mnemonic = 790, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -64852,6 +67345,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -64865,12 +67359,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2326 Instruction:"SETC Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x42 /r"/"M" + // Pos:2332 Instruction:"SETC Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x42 /r"/"M" { .Instruction = ND_INS_SETcc, .Category = ND_CAT_BITBYTE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 789, + .Mnemonic = 791, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ZU, @@ -64879,6 +67373,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0, .SetFlags = 0, @@ -64892,12 +67387,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2327 Instruction:"SETC Eb" Encoding:"0x0F 0x92 /r"/"M" + // Pos:2333 Instruction:"SETC Eb" Encoding:"0x0F 0x92 /r"/"M" { .Instruction = ND_INS_SETcc, .Category = ND_CAT_BITBYTE, .IsaSet = ND_SET_I386, - .Mnemonic = 789, + .Mnemonic = 791, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -64906,6 +67401,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0, .SetFlags = 0, @@ -64919,12 +67415,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2328 Instruction:"SETL Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x4C /r"/"M" + // Pos:2334 Instruction:"SETL Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x4C /r"/"M" { .Instruction = ND_INS_SETcc, .Category = ND_CAT_BITBYTE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 790, + .Mnemonic = 792, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ZU, @@ -64933,6 +67429,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -64946,12 +67443,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2329 Instruction:"SETL Eb" Encoding:"0x0F 0x9C /r"/"M" + // Pos:2335 Instruction:"SETL Eb" Encoding:"0x0F 0x9C /r"/"M" { .Instruction = ND_INS_SETcc, .Category = ND_CAT_BITBYTE, .IsaSet = ND_SET_I386, - .Mnemonic = 790, + .Mnemonic = 792, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -64960,6 +67457,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -64973,12 +67471,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2330 Instruction:"SETLE Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x4E /r"/"M" + // Pos:2336 Instruction:"SETLE Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x4E /r"/"M" { .Instruction = ND_INS_SETcc, .Category = ND_CAT_BITBYTE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 791, + .Mnemonic = 793, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ZU, @@ -64987,6 +67485,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -65000,12 +67499,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2331 Instruction:"SETLE Eb" Encoding:"0x0F 0x9E /r"/"M" + // Pos:2337 Instruction:"SETLE Eb" Encoding:"0x0F 0x9E /r"/"M" { .Instruction = ND_INS_SETcc, .Category = ND_CAT_BITBYTE, .IsaSet = ND_SET_I386, - .Mnemonic = 791, + .Mnemonic = 793, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -65014,6 +67513,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -65027,12 +67527,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2332 Instruction:"SETNBE Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x47 /r"/"M" + // Pos:2338 Instruction:"SETNBE Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x47 /r"/"M" { .Instruction = ND_INS_SETcc, .Category = ND_CAT_BITBYTE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 792, + .Mnemonic = 794, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ZU, @@ -65041,6 +67541,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -65054,12 +67555,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2333 Instruction:"SETNBE Eb" Encoding:"0x0F 0x97 /r"/"M" + // Pos:2339 Instruction:"SETNBE Eb" Encoding:"0x0F 0x97 /r"/"M" { .Instruction = ND_INS_SETcc, .Category = ND_CAT_BITBYTE, .IsaSet = ND_SET_I386, - .Mnemonic = 792, + .Mnemonic = 794, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -65068,6 +67569,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -65081,12 +67583,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2334 Instruction:"SETNC Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x43 /r"/"M" + // Pos:2340 Instruction:"SETNC Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x43 /r"/"M" { .Instruction = ND_INS_SETcc, .Category = ND_CAT_BITBYTE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 793, + .Mnemonic = 795, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ZU, @@ -65095,6 +67597,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0, .SetFlags = 0, @@ -65108,12 +67611,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2335 Instruction:"SETNC Eb" Encoding:"0x0F 0x93 /r"/"M" + // Pos:2341 Instruction:"SETNC Eb" Encoding:"0x0F 0x93 /r"/"M" { .Instruction = ND_INS_SETcc, .Category = ND_CAT_BITBYTE, .IsaSet = ND_SET_I386, - .Mnemonic = 793, + .Mnemonic = 795, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -65122,6 +67625,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0, .SetFlags = 0, @@ -65135,12 +67639,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2336 Instruction:"SETNL Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x4D /r"/"M" + // Pos:2342 Instruction:"SETNL Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x4D /r"/"M" { .Instruction = ND_INS_SETcc, .Category = ND_CAT_BITBYTE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 794, + .Mnemonic = 796, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ZU, @@ -65149,6 +67653,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -65162,12 +67667,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2337 Instruction:"SETNL Eb" Encoding:"0x0F 0x9D /r"/"M" + // Pos:2343 Instruction:"SETNL Eb" Encoding:"0x0F 0x9D /r"/"M" { .Instruction = ND_INS_SETcc, .Category = ND_CAT_BITBYTE, .IsaSet = ND_SET_I386, - .Mnemonic = 794, + .Mnemonic = 796, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -65176,6 +67681,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -65189,12 +67695,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2338 Instruction:"SETNLE Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x4F /r"/"M" + // Pos:2344 Instruction:"SETNLE Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x4F /r"/"M" { .Instruction = ND_INS_SETcc, .Category = ND_CAT_BITBYTE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 795, + .Mnemonic = 797, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ZU, @@ -65203,6 +67709,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -65216,12 +67723,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2339 Instruction:"SETNLE Eb" Encoding:"0x0F 0x9F /r"/"M" + // Pos:2345 Instruction:"SETNLE Eb" Encoding:"0x0F 0x9F /r"/"M" { .Instruction = ND_INS_SETcc, .Category = ND_CAT_BITBYTE, .IsaSet = ND_SET_I386, - .Mnemonic = 795, + .Mnemonic = 797, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -65230,6 +67737,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -65243,12 +67751,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2340 Instruction:"SETNO Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x41 /r"/"M" + // Pos:2346 Instruction:"SETNO Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x41 /r"/"M" { .Instruction = ND_INS_SETcc, .Category = ND_CAT_BITBYTE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 796, + .Mnemonic = 798, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ZU, @@ -65257,6 +67765,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -65270,12 +67779,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2341 Instruction:"SETNO Eb" Encoding:"0x0F 0x91 /r"/"M" + // Pos:2347 Instruction:"SETNO Eb" Encoding:"0x0F 0x91 /r"/"M" { .Instruction = ND_INS_SETcc, .Category = ND_CAT_BITBYTE, .IsaSet = ND_SET_I386, - .Mnemonic = 796, + .Mnemonic = 798, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -65284,6 +67793,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -65297,12 +67807,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2342 Instruction:"SETNP Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x4B /r"/"M" + // Pos:2348 Instruction:"SETNP Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x4B /r"/"M" { .Instruction = ND_INS_SETcc, .Category = ND_CAT_BITBYTE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 797, + .Mnemonic = 799, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ZU, @@ -65311,6 +67821,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_PF, .ModifiedFlags = 0, .SetFlags = 0, @@ -65324,12 +67835,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2343 Instruction:"SETNP Eb" Encoding:"0x0F 0x9B /r"/"M" + // Pos:2349 Instruction:"SETNP Eb" Encoding:"0x0F 0x9B /r"/"M" { .Instruction = ND_INS_SETcc, .Category = ND_CAT_BITBYTE, .IsaSet = ND_SET_I386, - .Mnemonic = 797, + .Mnemonic = 799, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -65338,6 +67849,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_PF, .ModifiedFlags = 0, .SetFlags = 0, @@ -65351,12 +67863,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2344 Instruction:"SETNS Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x49 /r"/"M" + // Pos:2350 Instruction:"SETNS Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x49 /r"/"M" { .Instruction = ND_INS_SETcc, .Category = ND_CAT_BITBYTE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 798, + .Mnemonic = 800, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ZU, @@ -65365,6 +67877,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF, .ModifiedFlags = 0, .SetFlags = 0, @@ -65378,12 +67891,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2345 Instruction:"SETNS Eb" Encoding:"0x0F 0x99 /r"/"M" + // Pos:2351 Instruction:"SETNS Eb" Encoding:"0x0F 0x99 /r"/"M" { .Instruction = ND_INS_SETcc, .Category = ND_CAT_BITBYTE, .IsaSet = ND_SET_I386, - .Mnemonic = 798, + .Mnemonic = 800, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -65392,6 +67905,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF, .ModifiedFlags = 0, .SetFlags = 0, @@ -65405,12 +67919,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2346 Instruction:"SETNZ Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x45 /r"/"M" + // Pos:2352 Instruction:"SETNZ Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x45 /r"/"M" { .Instruction = ND_INS_SETcc, .Category = ND_CAT_BITBYTE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 799, + .Mnemonic = 801, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ZU, @@ -65419,6 +67933,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -65432,12 +67947,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2347 Instruction:"SETNZ Eb" Encoding:"0x0F 0x95 /r"/"M" + // Pos:2353 Instruction:"SETNZ Eb" Encoding:"0x0F 0x95 /r"/"M" { .Instruction = ND_INS_SETcc, .Category = ND_CAT_BITBYTE, .IsaSet = ND_SET_I386, - .Mnemonic = 799, + .Mnemonic = 801, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -65446,6 +67961,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -65459,12 +67975,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2348 Instruction:"SETO Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x40 /r"/"M" + // Pos:2354 Instruction:"SETO Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x40 /r"/"M" { .Instruction = ND_INS_SETcc, .Category = ND_CAT_BITBYTE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 800, + .Mnemonic = 802, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ZU, @@ -65473,6 +67989,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -65486,12 +68003,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2349 Instruction:"SETO Eb" Encoding:"0x0F 0x90 /r"/"M" + // Pos:2355 Instruction:"SETO Eb" Encoding:"0x0F 0x90 /r"/"M" { .Instruction = ND_INS_SETcc, .Category = ND_CAT_BITBYTE, .IsaSet = ND_SET_I386, - .Mnemonic = 800, + .Mnemonic = 802, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -65500,6 +68017,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -65513,12 +68031,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2350 Instruction:"SETP Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x4A /r"/"M" + // Pos:2356 Instruction:"SETP Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x4A /r"/"M" { .Instruction = ND_INS_SETcc, .Category = ND_CAT_BITBYTE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 801, + .Mnemonic = 803, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ZU, @@ -65527,6 +68045,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_PF, .ModifiedFlags = 0, .SetFlags = 0, @@ -65540,12 +68059,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2351 Instruction:"SETP Eb" Encoding:"0x0F 0x9A /r"/"M" + // Pos:2357 Instruction:"SETP Eb" Encoding:"0x0F 0x9A /r"/"M" { .Instruction = ND_INS_SETcc, .Category = ND_CAT_BITBYTE, .IsaSet = ND_SET_I386, - .Mnemonic = 801, + .Mnemonic = 803, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -65554,6 +68073,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_PF, .ModifiedFlags = 0, .SetFlags = 0, @@ -65567,12 +68087,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2352 Instruction:"SETS Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x48 /r"/"M" + // Pos:2358 Instruction:"SETS Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x48 /r"/"M" { .Instruction = ND_INS_SETcc, .Category = ND_CAT_BITBYTE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 802, + .Mnemonic = 804, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ZU, @@ -65581,6 +68101,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF, .ModifiedFlags = 0, .SetFlags = 0, @@ -65594,12 +68115,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2353 Instruction:"SETS Eb" Encoding:"0x0F 0x98 /r"/"M" + // Pos:2359 Instruction:"SETS Eb" Encoding:"0x0F 0x98 /r"/"M" { .Instruction = ND_INS_SETcc, .Category = ND_CAT_BITBYTE, .IsaSet = ND_SET_I386, - .Mnemonic = 802, + .Mnemonic = 804, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -65608,6 +68129,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_SF, .ModifiedFlags = 0, .SetFlags = 0, @@ -65621,12 +68143,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2354 Instruction:"SETSSBSY" Encoding:"0xF3 0x0F 0x01 /0xE8"/"" + // Pos:2360 Instruction:"SETSSBSY" Encoding:"0xF3 0x0F 0x01 /0xE8"/"" { .Instruction = ND_INS_SETSSBSY, .Category = ND_CAT_CET, .IsaSet = ND_SET_CET_SS, - .Mnemonic = 803, + .Mnemonic = 805, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -65635,6 +68157,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -65648,12 +68171,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2355 Instruction:"SETZ Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x44 /r"/"M" + // Pos:2361 Instruction:"SETZ Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x44 /r"/"M" { .Instruction = ND_INS_SETcc, .Category = ND_CAT_BITBYTE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 804, + .Mnemonic = 806, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ZU, @@ -65662,6 +68185,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -65675,12 +68199,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2356 Instruction:"SETZ Eb" Encoding:"0x0F 0x94 /r"/"M" + // Pos:2362 Instruction:"SETZ Eb" Encoding:"0x0F 0x94 /r"/"M" { .Instruction = ND_INS_SETcc, .Category = ND_CAT_BITBYTE, .IsaSet = ND_SET_I386, - .Mnemonic = 804, + .Mnemonic = 806, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -65689,6 +68213,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -65702,12 +68227,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2357 Instruction:"SFENCE" Encoding:"NP 0x0F 0xAE /7:reg"/"" + // Pos:2363 Instruction:"SFENCE" Encoding:"NP 0x0F 0xAE /7:reg"/"" { .Instruction = ND_INS_SFENCE, .Category = ND_CAT_MISC, .IsaSet = ND_SET_SSE2, - .Mnemonic = 805, + .Mnemonic = 807, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -65716,6 +68241,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -65728,12 +68254,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2358 Instruction:"SGDT Ms" Encoding:"0x0F 0x01 /0:mem"/"M" + // Pos:2364 Instruction:"SGDT Ms" Encoding:"0x0F 0x01 /0:mem"/"M" { .Instruction = ND_INS_SGDT, .Category = ND_CAT_SYSTEM, .IsaSet = ND_SET_I286REAL, - .Mnemonic = 806, + .Mnemonic = 808, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -65742,6 +68268,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -65755,12 +68282,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2359 Instruction:"SHA1MSG1 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xC9 /r"/"RM" + // Pos:2365 Instruction:"SHA1MSG1 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xC9 /r"/"RM" { .Instruction = ND_INS_SHA1MSG1, .Category = ND_CAT_SHA, .IsaSet = ND_SET_SHA, - .Mnemonic = 807, + .Mnemonic = 809, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -65769,6 +68296,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -65782,12 +68310,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2360 Instruction:"SHA1MSG2 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCA /r"/"RM" + // Pos:2366 Instruction:"SHA1MSG2 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCA /r"/"RM" { .Instruction = ND_INS_SHA1MSG2, .Category = ND_CAT_SHA, .IsaSet = ND_SET_SHA, - .Mnemonic = 808, + .Mnemonic = 810, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -65796,6 +68324,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -65809,12 +68338,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2361 Instruction:"SHA1NEXTE Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xC8 /r"/"RM" + // Pos:2367 Instruction:"SHA1NEXTE Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xC8 /r"/"RM" { .Instruction = ND_INS_SHA1NEXTE, .Category = ND_CAT_SHA, .IsaSet = ND_SET_SHA, - .Mnemonic = 809, + .Mnemonic = 811, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -65823,6 +68352,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -65836,12 +68366,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2362 Instruction:"SHA1RNDS4 Vdq,Wdq,Ib" Encoding:"NP 0x0F 0x3A 0xCC /r ib"/"RMI" + // Pos:2368 Instruction:"SHA1RNDS4 Vdq,Wdq,Ib" Encoding:"NP 0x0F 0x3A 0xCC /r ib"/"RMI" { .Instruction = ND_INS_SHA1RNDS4, .Category = ND_CAT_SHA, .IsaSet = ND_SET_SHA, - .Mnemonic = 810, + .Mnemonic = 812, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -65850,6 +68380,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -65864,12 +68395,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2363 Instruction:"SHA256MSG1 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCC /r"/"RM" + // Pos:2369 Instruction:"SHA256MSG1 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCC /r"/"RM" { .Instruction = ND_INS_SHA256MSG1, .Category = ND_CAT_SHA, .IsaSet = ND_SET_SHA, - .Mnemonic = 811, + .Mnemonic = 813, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -65878,6 +68409,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -65891,12 +68423,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2364 Instruction:"SHA256MSG2 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCD /r"/"RM" + // Pos:2370 Instruction:"SHA256MSG2 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCD /r"/"RM" { .Instruction = ND_INS_SHA256MSG2, .Category = ND_CAT_SHA, .IsaSet = ND_SET_SHA, - .Mnemonic = 812, + .Mnemonic = 814, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -65905,6 +68437,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -65918,12 +68451,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2365 Instruction:"SHA256RNDS2 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCB /r"/"RM" + // Pos:2371 Instruction:"SHA256RNDS2 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCB /r"/"RM" { .Instruction = ND_INS_SHA256RNDS2, .Category = ND_CAT_SHA, .IsaSet = ND_SET_SHA, - .Mnemonic = 813, + .Mnemonic = 815, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -65932,6 +68465,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -65946,12 +68480,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2366 Instruction:"SHL Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC0 /4 ib"/"MI" + // Pos:2372 Instruction:"SHL Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC0 /4 ib"/"MI" { .Instruction = ND_INS_SHL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 814, + .Mnemonic = 816, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -65960,6 +68494,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -65974,12 +68509,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2367 Instruction:"SHL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC1 /4 ib"/"MI" + // Pos:2373 Instruction:"SHL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC1 /4 ib"/"MI" { .Instruction = ND_INS_SHL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 814, + .Mnemonic = 816, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -65988,6 +68523,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -66002,12 +68538,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2368 Instruction:"SHL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xC1 /4 ib"/"MI" + // Pos:2374 Instruction:"SHL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xC1 /4 ib"/"MI" { .Instruction = ND_INS_SHL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 814, + .Mnemonic = 816, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -66016,6 +68552,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -66030,12 +68567,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2369 Instruction:"SHL Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD0 /4"/"M1" + // Pos:2375 Instruction:"SHL Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD0 /4"/"M1" { .Instruction = ND_INS_SHL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 814, + .Mnemonic = 816, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -66044,6 +68581,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -66058,12 +68596,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2370 Instruction:"SHL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD1 /4"/"M1" + // Pos:2376 Instruction:"SHL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD1 /4"/"M1" { .Instruction = ND_INS_SHL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 814, + .Mnemonic = 816, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -66072,6 +68610,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -66086,12 +68625,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2371 Instruction:"SHL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD1 /4"/"M1" + // Pos:2377 Instruction:"SHL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD1 /4"/"M1" { .Instruction = ND_INS_SHL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 814, + .Mnemonic = 816, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -66100,6 +68639,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -66114,12 +68654,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2372 Instruction:"SHL Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD2 /4"/"MC" + // Pos:2378 Instruction:"SHL Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD2 /4"/"MC" { .Instruction = ND_INS_SHL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 814, + .Mnemonic = 816, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -66128,6 +68668,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -66142,12 +68683,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2373 Instruction:"SHL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD3 /4"/"MC" + // Pos:2379 Instruction:"SHL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD3 /4"/"MC" { .Instruction = ND_INS_SHL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 814, + .Mnemonic = 816, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -66156,6 +68697,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -66170,12 +68712,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2374 Instruction:"SHL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD3 /4"/"MC" + // Pos:2380 Instruction:"SHL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD3 /4"/"MC" { .Instruction = ND_INS_SHL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 814, + .Mnemonic = 816, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -66184,6 +68726,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -66198,12 +68741,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2375 Instruction:"SHL Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC0 /4 ib"/"MI" + // Pos:2381 Instruction:"SHL Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC0 /4 ib"/"MI" { .Instruction = ND_INS_SHL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 814, + .Mnemonic = 816, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -66212,6 +68755,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -66225,12 +68769,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2376 Instruction:"SHL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC1 /4 ib"/"MI" + // Pos:2382 Instruction:"SHL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC1 /4 ib"/"MI" { .Instruction = ND_INS_SHL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 814, + .Mnemonic = 816, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -66239,6 +68783,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -66252,12 +68797,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2377 Instruction:"SHL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xC1 /4 ib"/"MI" + // Pos:2383 Instruction:"SHL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xC1 /4 ib"/"MI" { .Instruction = ND_INS_SHL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 814, + .Mnemonic = 816, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -66266,6 +68811,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -66279,12 +68825,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2378 Instruction:"SHL Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD0 /4"/"M1" + // Pos:2384 Instruction:"SHL Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD0 /4"/"M1" { .Instruction = ND_INS_SHL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 814, + .Mnemonic = 816, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -66293,6 +68839,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -66306,12 +68853,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2379 Instruction:"SHL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD1 /4"/"M1" + // Pos:2385 Instruction:"SHL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD1 /4"/"M1" { .Instruction = ND_INS_SHL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 814, + .Mnemonic = 816, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -66320,6 +68867,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -66333,12 +68881,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2380 Instruction:"SHL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD1 /4"/"M1" + // Pos:2386 Instruction:"SHL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD1 /4"/"M1" { .Instruction = ND_INS_SHL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 814, + .Mnemonic = 816, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -66347,6 +68895,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -66360,12 +68909,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2381 Instruction:"SHL Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD2 /4"/"MC" + // Pos:2387 Instruction:"SHL Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD2 /4"/"MC" { .Instruction = ND_INS_SHL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 814, + .Mnemonic = 816, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -66374,6 +68923,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -66387,12 +68937,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2382 Instruction:"SHL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD3 /4"/"MC" + // Pos:2388 Instruction:"SHL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD3 /4"/"MC" { .Instruction = ND_INS_SHL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 814, + .Mnemonic = 816, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -66401,6 +68951,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -66414,12 +68965,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2383 Instruction:"SHL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD3 /4"/"MC" + // Pos:2389 Instruction:"SHL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD3 /4"/"MC" { .Instruction = ND_INS_SHL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 814, + .Mnemonic = 816, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -66428,6 +68979,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -66441,12 +68993,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2384 Instruction:"SHL Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC0 /4 ib"/"VMI" + // Pos:2390 Instruction:"SHL Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC0 /4 ib"/"VMI" { .Instruction = ND_INS_SHL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 814, + .Mnemonic = 816, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -66455,6 +69007,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -66470,12 +69023,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2385 Instruction:"SHL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC1 /4 ib"/"VMI" + // Pos:2391 Instruction:"SHL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC1 /4 ib"/"VMI" { .Instruction = ND_INS_SHL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 814, + .Mnemonic = 816, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -66484,6 +69037,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -66499,12 +69053,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2386 Instruction:"SHL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xC1 /4 ib"/"VMI" + // Pos:2392 Instruction:"SHL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xC1 /4 ib"/"VMI" { .Instruction = ND_INS_SHL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 814, + .Mnemonic = 816, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -66513,6 +69067,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -66528,12 +69083,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2387 Instruction:"SHL Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD0 /4"/"VM1" + // Pos:2393 Instruction:"SHL Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD0 /4"/"VM1" { .Instruction = ND_INS_SHL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 814, + .Mnemonic = 816, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -66542,6 +69097,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -66557,12 +69113,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2388 Instruction:"SHL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD1 /4"/"VM1" + // Pos:2394 Instruction:"SHL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD1 /4"/"VM1" { .Instruction = ND_INS_SHL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 814, + .Mnemonic = 816, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -66571,6 +69127,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -66586,12 +69143,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2389 Instruction:"SHL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD1 /4"/"VM1" + // Pos:2395 Instruction:"SHL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD1 /4"/"VM1" { .Instruction = ND_INS_SHL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 814, + .Mnemonic = 816, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -66600,6 +69157,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -66615,12 +69173,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2390 Instruction:"SHL Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD2 /4"/"VMC" + // Pos:2396 Instruction:"SHL Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD2 /4"/"VMC" { .Instruction = ND_INS_SHL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 814, + .Mnemonic = 816, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -66629,6 +69187,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -66644,12 +69203,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2391 Instruction:"SHL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD3 /4"/"VMC" + // Pos:2397 Instruction:"SHL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD3 /4"/"VMC" { .Instruction = ND_INS_SHL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 814, + .Mnemonic = 816, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -66658,6 +69217,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -66673,12 +69233,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2392 Instruction:"SHL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD3 /4"/"VMC" + // Pos:2398 Instruction:"SHL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD3 /4"/"VMC" { .Instruction = ND_INS_SHL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 814, + .Mnemonic = 816, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -66687,6 +69247,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -66702,12 +69263,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2393 Instruction:"SHL Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC0 /4 ib"/"VMI" + // Pos:2399 Instruction:"SHL Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC0 /4 ib"/"VMI" { .Instruction = ND_INS_SHL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 814, + .Mnemonic = 816, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -66716,6 +69277,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -66730,12 +69292,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2394 Instruction:"SHL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC1 /4 ib"/"VMI" + // Pos:2400 Instruction:"SHL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC1 /4 ib"/"VMI" { .Instruction = ND_INS_SHL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 814, + .Mnemonic = 816, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -66744,6 +69306,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -66758,12 +69321,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2395 Instruction:"SHL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xC1 /4 ib"/"VMI" + // Pos:2401 Instruction:"SHL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xC1 /4 ib"/"VMI" { .Instruction = ND_INS_SHL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 814, + .Mnemonic = 816, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -66772,6 +69335,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -66786,12 +69350,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2396 Instruction:"SHL Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD0 /4"/"VM1" + // Pos:2402 Instruction:"SHL Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD0 /4"/"VM1" { .Instruction = ND_INS_SHL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 814, + .Mnemonic = 816, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -66800,6 +69364,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -66814,12 +69379,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2397 Instruction:"SHL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD1 /4"/"VM1" + // Pos:2403 Instruction:"SHL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD1 /4"/"VM1" { .Instruction = ND_INS_SHL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 814, + .Mnemonic = 816, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -66828,6 +69393,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -66842,12 +69408,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2398 Instruction:"SHL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD1 /4"/"VM1" + // Pos:2404 Instruction:"SHL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD1 /4"/"VM1" { .Instruction = ND_INS_SHL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 814, + .Mnemonic = 816, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -66856,6 +69422,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -66870,12 +69437,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2399 Instruction:"SHL Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD2 /4"/"VMC" + // Pos:2405 Instruction:"SHL Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD2 /4"/"VMC" { .Instruction = ND_INS_SHL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 814, + .Mnemonic = 816, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -66884,6 +69451,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -66898,12 +69466,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2400 Instruction:"SHL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD3 /4"/"VMC" + // Pos:2406 Instruction:"SHL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD3 /4"/"VMC" { .Instruction = ND_INS_SHL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 814, + .Mnemonic = 816, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -66912,6 +69480,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -66926,12 +69495,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2401 Instruction:"SHL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD3 /4"/"VMC" + // Pos:2407 Instruction:"SHL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD3 /4"/"VMC" { .Instruction = ND_INS_SHL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 814, + .Mnemonic = 816, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -66940,6 +69509,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -66954,12 +69524,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2402 Instruction:"SHL Eb,Ib" Encoding:"0xC0 /4 ib"/"MI" + // Pos:2408 Instruction:"SHL Eb,Ib" Encoding:"0xC0 /4 ib"/"MI" { .Instruction = ND_INS_SHL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_I86, - .Mnemonic = 814, + .Mnemonic = 816, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -66968,6 +69538,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -66982,12 +69553,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2403 Instruction:"SHL Ev,Ib" Encoding:"0xC1 /4 ib"/"MI" + // Pos:2409 Instruction:"SHL Ev,Ib" Encoding:"0xC1 /4 ib"/"MI" { .Instruction = ND_INS_SHL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_I86, - .Mnemonic = 814, + .Mnemonic = 816, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -66996,6 +69567,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -67010,12 +69582,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2404 Instruction:"SHL Eb,1" Encoding:"0xD0 /4"/"M1" + // Pos:2410 Instruction:"SHL Eb,1" Encoding:"0xD0 /4"/"M1" { .Instruction = ND_INS_SHL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_I86, - .Mnemonic = 814, + .Mnemonic = 816, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -67024,6 +69596,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -67038,12 +69611,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2405 Instruction:"SHL Ev,1" Encoding:"0xD1 /4"/"M1" + // Pos:2411 Instruction:"SHL Ev,1" Encoding:"0xD1 /4"/"M1" { .Instruction = ND_INS_SHL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_I86, - .Mnemonic = 814, + .Mnemonic = 816, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -67052,6 +69625,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -67066,12 +69640,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2406 Instruction:"SHL Eb,CL" Encoding:"0xD2 /4"/"MC" + // Pos:2412 Instruction:"SHL Eb,CL" Encoding:"0xD2 /4"/"MC" { .Instruction = ND_INS_SHL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_I86, - .Mnemonic = 814, + .Mnemonic = 816, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -67080,6 +69654,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -67094,12 +69669,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2407 Instruction:"SHL Ev,CL" Encoding:"0xD3 /4"/"MC" + // Pos:2413 Instruction:"SHL Ev,CL" Encoding:"0xD3 /4"/"MC" { .Instruction = ND_INS_SHL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_I86, - .Mnemonic = 814, + .Mnemonic = 816, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -67108,6 +69683,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -67122,12 +69698,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2408 Instruction:"SHLD Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x24 /r ib"/"MRI" + // Pos:2414 Instruction:"SHLD Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x24 /r ib"/"MRI" { .Instruction = ND_INS_SHLD, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 815, + .Mnemonic = 817, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -67136,6 +69712,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, @@ -67151,12 +69728,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2409 Instruction:"SHLD Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xA5 /r"/"MRC" + // Pos:2415 Instruction:"SHLD Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xA5 /r"/"MRC" { .Instruction = ND_INS_SHLD, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 815, + .Mnemonic = 817, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -67165,6 +69742,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, @@ -67180,12 +69758,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2410 Instruction:"SHLD Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x24 /r ib"/"MRI" + // Pos:2416 Instruction:"SHLD Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x24 /r ib"/"MRI" { .Instruction = ND_INS_SHLD, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 815, + .Mnemonic = 817, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -67194,6 +69772,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, @@ -67209,12 +69788,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2411 Instruction:"SHLD Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xA5 /r"/"MRC" + // Pos:2417 Instruction:"SHLD Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xA5 /r"/"MRC" { .Instruction = ND_INS_SHLD, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 815, + .Mnemonic = 817, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -67223,6 +69802,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, @@ -67238,12 +69818,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2412 Instruction:"SHLD Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x24 /r ib"/"MRI" + // Pos:2418 Instruction:"SHLD Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x24 /r ib"/"MRI" { .Instruction = ND_INS_SHLD, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 815, + .Mnemonic = 817, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -67252,6 +69832,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -67266,12 +69847,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2413 Instruction:"SHLD Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xA5 /r"/"MRC" + // Pos:2419 Instruction:"SHLD Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xA5 /r"/"MRC" { .Instruction = ND_INS_SHLD, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 815, + .Mnemonic = 817, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -67280,6 +69861,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -67294,12 +69876,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2414 Instruction:"SHLD Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x24 /r ib"/"MRI" + // Pos:2420 Instruction:"SHLD Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x24 /r ib"/"MRI" { .Instruction = ND_INS_SHLD, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 815, + .Mnemonic = 817, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -67308,6 +69890,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -67322,12 +69905,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2415 Instruction:"SHLD Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xA5 /r"/"MRC" + // Pos:2421 Instruction:"SHLD Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xA5 /r"/"MRC" { .Instruction = ND_INS_SHLD, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 815, + .Mnemonic = 817, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -67336,6 +69919,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -67350,12 +69934,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2416 Instruction:"SHLD Bv,Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x24 /r ib"/"VMRI" + // Pos:2422 Instruction:"SHLD Bv,Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x24 /r ib"/"VMRI" { .Instruction = ND_INS_SHLD, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 815, + .Mnemonic = 817, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -67364,6 +69948,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, @@ -67380,12 +69965,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2417 Instruction:"SHLD Bv,Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xA5 /r"/"VMRC" + // Pos:2423 Instruction:"SHLD Bv,Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xA5 /r"/"VMRC" { .Instruction = ND_INS_SHLD, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 815, + .Mnemonic = 817, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -67394,6 +69979,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, @@ -67410,12 +69996,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2418 Instruction:"SHLD Bv,Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x24 /r ib"/"VMRI" + // Pos:2424 Instruction:"SHLD Bv,Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x24 /r ib"/"VMRI" { .Instruction = ND_INS_SHLD, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 815, + .Mnemonic = 817, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -67424,6 +70010,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, @@ -67440,12 +70027,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2419 Instruction:"SHLD Bv,Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xA5 /r"/"VMRC" + // Pos:2425 Instruction:"SHLD Bv,Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xA5 /r"/"VMRC" { .Instruction = ND_INS_SHLD, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 815, + .Mnemonic = 817, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -67454,6 +70041,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, @@ -67470,12 +70058,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2420 Instruction:"SHLD Bv,Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x24 /r ib"/"VMRI" + // Pos:2426 Instruction:"SHLD Bv,Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x24 /r ib"/"VMRI" { .Instruction = ND_INS_SHLD, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 815, + .Mnemonic = 817, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -67484,6 +70072,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -67499,12 +70088,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2421 Instruction:"SHLD Bv,Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xA5 /r"/"VMRC" + // Pos:2427 Instruction:"SHLD Bv,Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xA5 /r"/"VMRC" { .Instruction = ND_INS_SHLD, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 815, + .Mnemonic = 817, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -67513,6 +70102,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -67528,12 +70118,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2422 Instruction:"SHLD Bv,Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x24 /r ib"/"VMRI" + // Pos:2428 Instruction:"SHLD Bv,Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x24 /r ib"/"VMRI" { .Instruction = ND_INS_SHLD, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 815, + .Mnemonic = 817, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -67542,6 +70132,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -67557,12 +70148,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2423 Instruction:"SHLD Bv,Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xA5 /r"/"VMRC" + // Pos:2429 Instruction:"SHLD Bv,Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xA5 /r"/"VMRC" { .Instruction = ND_INS_SHLD, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 815, + .Mnemonic = 817, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -67571,6 +70162,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -67586,12 +70178,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2424 Instruction:"SHLD Ev,Gv,Ib" Encoding:"0x0F 0xA4 /r ib"/"MRI" + // Pos:2430 Instruction:"SHLD Ev,Gv,Ib" Encoding:"0x0F 0xA4 /r ib"/"MRI" { .Instruction = ND_INS_SHLD, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_I386, - .Mnemonic = 815, + .Mnemonic = 817, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -67600,6 +70192,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, @@ -67615,12 +70208,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2425 Instruction:"SHLD Ev,Gv,CL" Encoding:"0x0F 0xA5 /r"/"MRC" + // Pos:2431 Instruction:"SHLD Ev,Gv,CL" Encoding:"0x0F 0xA5 /r"/"MRC" { .Instruction = ND_INS_SHLD, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_I386, - .Mnemonic = 815, + .Mnemonic = 817, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -67629,6 +70222,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, @@ -67644,12 +70238,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2426 Instruction:"SHLX Gy,Ey,By" Encoding:"evex m:2 p:1 l:0 nf:0 0xF7 /r"/"RMV" + // Pos:2432 Instruction:"SHLX Gy,Ey,By" Encoding:"evex m:2 p:1 l:0 nf:0 0xF7 /r"/"RMV" { .Instruction = ND_INS_SHLX, .Category = ND_CAT_BMI2, .IsaSet = ND_SET_APX_F, - .Mnemonic = 816, + .Mnemonic = 818, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -67658,6 +70252,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_BMI, .FpuFlags = 0, .EvexMode = ND_EVEXM_VEX, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -67672,12 +70267,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2427 Instruction:"SHLX Gy,Ey,By" Encoding:"vex m:2 p:1 l:0 w:x 0xF7 /r"/"RMV" + // Pos:2433 Instruction:"SHLX Gy,Ey,By" Encoding:"vex m:2 p:1 l:0 w:x 0xF7 /r"/"RMV" { .Instruction = ND_INS_SHLX, .Category = ND_CAT_BMI2, .IsaSet = ND_SET_BMI2, - .Mnemonic = 816, + .Mnemonic = 818, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -67686,6 +70281,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_13, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -67700,12 +70296,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2428 Instruction:"SHR Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC0 /5 ib"/"MI" + // Pos:2434 Instruction:"SHR Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC0 /5 ib"/"MI" { .Instruction = ND_INS_SHR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 817, + .Mnemonic = 819, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -67714,6 +70310,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -67728,12 +70325,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2429 Instruction:"SHR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC1 /5 ib"/"MI" + // Pos:2435 Instruction:"SHR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC1 /5 ib"/"MI" { .Instruction = ND_INS_SHR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 817, + .Mnemonic = 819, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -67742,6 +70339,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -67756,12 +70354,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2430 Instruction:"SHR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xC1 /5 ib"/"MI" + // Pos:2436 Instruction:"SHR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xC1 /5 ib"/"MI" { .Instruction = ND_INS_SHR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 817, + .Mnemonic = 819, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -67770,6 +70368,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -67784,12 +70383,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2431 Instruction:"SHR Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD0 /5"/"M1" + // Pos:2437 Instruction:"SHR Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD0 /5"/"M1" { .Instruction = ND_INS_SHR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 817, + .Mnemonic = 819, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -67798,6 +70397,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -67812,12 +70412,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2432 Instruction:"SHR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD1 /5"/"M1" + // Pos:2438 Instruction:"SHR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD1 /5"/"M1" { .Instruction = ND_INS_SHR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 817, + .Mnemonic = 819, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -67826,6 +70426,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -67840,12 +70441,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2433 Instruction:"SHR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD1 /5"/"M1" + // Pos:2439 Instruction:"SHR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD1 /5"/"M1" { .Instruction = ND_INS_SHR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 817, + .Mnemonic = 819, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -67854,6 +70455,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -67868,12 +70470,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2434 Instruction:"SHR Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD2 /5"/"MC" + // Pos:2440 Instruction:"SHR Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD2 /5"/"MC" { .Instruction = ND_INS_SHR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 817, + .Mnemonic = 819, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -67882,6 +70484,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -67896,12 +70499,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2435 Instruction:"SHR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD3 /5"/"MC" + // Pos:2441 Instruction:"SHR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD3 /5"/"MC" { .Instruction = ND_INS_SHR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 817, + .Mnemonic = 819, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -67910,6 +70513,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -67924,12 +70528,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2436 Instruction:"SHR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD3 /5"/"MC" + // Pos:2442 Instruction:"SHR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD3 /5"/"MC" { .Instruction = ND_INS_SHR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 817, + .Mnemonic = 819, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -67938,6 +70542,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -67952,12 +70557,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2437 Instruction:"SHR Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC0 /5 ib"/"MI" + // Pos:2443 Instruction:"SHR Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC0 /5 ib"/"MI" { .Instruction = ND_INS_SHR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 817, + .Mnemonic = 819, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -67966,6 +70571,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -67979,12 +70585,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2438 Instruction:"SHR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC1 /5 ib"/"MI" + // Pos:2444 Instruction:"SHR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC1 /5 ib"/"MI" { .Instruction = ND_INS_SHR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 817, + .Mnemonic = 819, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -67993,6 +70599,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -68006,12 +70613,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2439 Instruction:"SHR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xC1 /5 ib"/"MI" + // Pos:2445 Instruction:"SHR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xC1 /5 ib"/"MI" { .Instruction = ND_INS_SHR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 817, + .Mnemonic = 819, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -68020,6 +70627,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -68033,12 +70641,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2440 Instruction:"SHR Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD0 /5"/"M1" + // Pos:2446 Instruction:"SHR Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD0 /5"/"M1" { .Instruction = ND_INS_SHR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 817, + .Mnemonic = 819, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -68047,6 +70655,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -68060,12 +70669,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2441 Instruction:"SHR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD1 /5"/"M1" + // Pos:2447 Instruction:"SHR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD1 /5"/"M1" { .Instruction = ND_INS_SHR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 817, + .Mnemonic = 819, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -68074,6 +70683,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -68087,12 +70697,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2442 Instruction:"SHR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD1 /5"/"M1" + // Pos:2448 Instruction:"SHR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD1 /5"/"M1" { .Instruction = ND_INS_SHR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 817, + .Mnemonic = 819, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -68101,6 +70711,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -68114,12 +70725,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2443 Instruction:"SHR Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD2 /5"/"MC" + // Pos:2449 Instruction:"SHR Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD2 /5"/"MC" { .Instruction = ND_INS_SHR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 817, + .Mnemonic = 819, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -68128,6 +70739,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -68141,12 +70753,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2444 Instruction:"SHR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD3 /5"/"MC" + // Pos:2450 Instruction:"SHR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD3 /5"/"MC" { .Instruction = ND_INS_SHR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 817, + .Mnemonic = 819, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -68155,6 +70767,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -68168,12 +70781,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2445 Instruction:"SHR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD3 /5"/"MC" + // Pos:2451 Instruction:"SHR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD3 /5"/"MC" { .Instruction = ND_INS_SHR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 817, + .Mnemonic = 819, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -68182,6 +70795,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -68195,12 +70809,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2446 Instruction:"SHR Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC0 /5 ib"/"VMI" + // Pos:2452 Instruction:"SHR Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC0 /5 ib"/"VMI" { .Instruction = ND_INS_SHR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 817, + .Mnemonic = 819, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -68209,6 +70823,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -68224,12 +70839,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2447 Instruction:"SHR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC1 /5 ib"/"VMI" + // Pos:2453 Instruction:"SHR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC1 /5 ib"/"VMI" { .Instruction = ND_INS_SHR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 817, + .Mnemonic = 819, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -68238,6 +70853,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -68253,12 +70869,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2448 Instruction:"SHR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xC1 /5 ib"/"VMI" + // Pos:2454 Instruction:"SHR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xC1 /5 ib"/"VMI" { .Instruction = ND_INS_SHR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 817, + .Mnemonic = 819, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -68267,6 +70883,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -68282,12 +70899,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2449 Instruction:"SHR Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD0 /5"/"VM1" + // Pos:2455 Instruction:"SHR Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD0 /5"/"VM1" { .Instruction = ND_INS_SHR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 817, + .Mnemonic = 819, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -68296,6 +70913,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -68311,12 +70929,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2450 Instruction:"SHR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD1 /5"/"VM1" + // Pos:2456 Instruction:"SHR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD1 /5"/"VM1" { .Instruction = ND_INS_SHR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 817, + .Mnemonic = 819, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -68325,6 +70943,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -68340,12 +70959,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2451 Instruction:"SHR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD1 /5"/"VM1" + // Pos:2457 Instruction:"SHR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD1 /5"/"VM1" { .Instruction = ND_INS_SHR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 817, + .Mnemonic = 819, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -68354,6 +70973,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -68369,12 +70989,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2452 Instruction:"SHR Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD2 /5"/"VMC" + // Pos:2458 Instruction:"SHR Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD2 /5"/"VMC" { .Instruction = ND_INS_SHR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 817, + .Mnemonic = 819, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -68383,6 +71003,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -68398,12 +71019,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2453 Instruction:"SHR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD3 /5"/"VMC" + // Pos:2459 Instruction:"SHR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD3 /5"/"VMC" { .Instruction = ND_INS_SHR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 817, + .Mnemonic = 819, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -68412,6 +71033,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -68427,12 +71049,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2454 Instruction:"SHR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD3 /5"/"VMC" + // Pos:2460 Instruction:"SHR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD3 /5"/"VMC" { .Instruction = ND_INS_SHR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 817, + .Mnemonic = 819, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -68441,6 +71063,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -68456,12 +71079,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2455 Instruction:"SHR Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC0 /5 ib"/"VMI" + // Pos:2461 Instruction:"SHR Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC0 /5 ib"/"VMI" { .Instruction = ND_INS_SHR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 817, + .Mnemonic = 819, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -68470,6 +71093,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -68484,12 +71108,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2456 Instruction:"SHR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC1 /5 ib"/"VMI" + // Pos:2462 Instruction:"SHR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC1 /5 ib"/"VMI" { .Instruction = ND_INS_SHR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 817, + .Mnemonic = 819, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -68498,6 +71122,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -68512,12 +71137,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2457 Instruction:"SHR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xC1 /5 ib"/"VMI" + // Pos:2463 Instruction:"SHR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xC1 /5 ib"/"VMI" { .Instruction = ND_INS_SHR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 817, + .Mnemonic = 819, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -68526,6 +71151,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -68540,12 +71166,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2458 Instruction:"SHR Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD0 /5"/"VM1" + // Pos:2464 Instruction:"SHR Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD0 /5"/"VM1" { .Instruction = ND_INS_SHR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 817, + .Mnemonic = 819, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -68554,6 +71180,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -68568,12 +71195,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2459 Instruction:"SHR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD1 /5"/"VM1" + // Pos:2465 Instruction:"SHR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD1 /5"/"VM1" { .Instruction = ND_INS_SHR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 817, + .Mnemonic = 819, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -68582,6 +71209,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -68596,12 +71224,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2460 Instruction:"SHR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD1 /5"/"VM1" + // Pos:2466 Instruction:"SHR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD1 /5"/"VM1" { .Instruction = ND_INS_SHR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 817, + .Mnemonic = 819, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -68610,6 +71238,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -68624,12 +71253,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2461 Instruction:"SHR Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD2 /5"/"VMC" + // Pos:2467 Instruction:"SHR Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD2 /5"/"VMC" { .Instruction = ND_INS_SHR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 817, + .Mnemonic = 819, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -68638,6 +71267,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -68652,12 +71282,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2462 Instruction:"SHR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD3 /5"/"VMC" + // Pos:2468 Instruction:"SHR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD3 /5"/"VMC" { .Instruction = ND_INS_SHR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 817, + .Mnemonic = 819, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -68666,6 +71296,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -68680,12 +71311,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2463 Instruction:"SHR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD3 /5"/"VMC" + // Pos:2469 Instruction:"SHR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD3 /5"/"VMC" { .Instruction = ND_INS_SHR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 817, + .Mnemonic = 819, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -68694,6 +71325,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -68708,12 +71340,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2464 Instruction:"SHR Eb,Ib" Encoding:"0xC0 /5 ib"/"MI" + // Pos:2470 Instruction:"SHR Eb,Ib" Encoding:"0xC0 /5 ib"/"MI" { .Instruction = ND_INS_SHR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_I86, - .Mnemonic = 817, + .Mnemonic = 819, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -68722,6 +71354,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -68736,12 +71369,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2465 Instruction:"SHR Ev,Ib" Encoding:"0xC1 /5 ib"/"MI" + // Pos:2471 Instruction:"SHR Ev,Ib" Encoding:"0xC1 /5 ib"/"MI" { .Instruction = ND_INS_SHR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_I86, - .Mnemonic = 817, + .Mnemonic = 819, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -68750,6 +71383,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -68764,12 +71398,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2466 Instruction:"SHR Eb,1" Encoding:"0xD0 /5"/"M1" + // Pos:2472 Instruction:"SHR Eb,1" Encoding:"0xD0 /5"/"M1" { .Instruction = ND_INS_SHR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_I86, - .Mnemonic = 817, + .Mnemonic = 819, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -68778,6 +71412,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -68792,12 +71427,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2467 Instruction:"SHR Ev,1" Encoding:"0xD1 /5"/"M1" + // Pos:2473 Instruction:"SHR Ev,1" Encoding:"0xD1 /5"/"M1" { .Instruction = ND_INS_SHR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_I86, - .Mnemonic = 817, + .Mnemonic = 819, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -68806,6 +71441,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -68820,12 +71456,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2468 Instruction:"SHR Eb,CL" Encoding:"0xD2 /5"/"MC" + // Pos:2474 Instruction:"SHR Eb,CL" Encoding:"0xD2 /5"/"MC" { .Instruction = ND_INS_SHR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_I86, - .Mnemonic = 817, + .Mnemonic = 819, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -68834,6 +71470,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -68848,12 +71485,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2469 Instruction:"SHR Ev,CL" Encoding:"0xD3 /5"/"MC" + // Pos:2475 Instruction:"SHR Ev,CL" Encoding:"0xD3 /5"/"MC" { .Instruction = ND_INS_SHR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_I86, - .Mnemonic = 817, + .Mnemonic = 819, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -68862,6 +71499,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0|NDR_RFLAG_AF, @@ -68876,12 +71514,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2470 Instruction:"SHRD Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x2C /r ib"/"MRI" + // Pos:2476 Instruction:"SHRD Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x2C /r ib"/"MRI" { .Instruction = ND_INS_SHRD, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 818, + .Mnemonic = 820, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -68890,6 +71528,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, @@ -68905,12 +71544,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2471 Instruction:"SHRD Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xAD /r"/"MRC" + // Pos:2477 Instruction:"SHRD Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xAD /r"/"MRC" { .Instruction = ND_INS_SHRD, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 818, + .Mnemonic = 820, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -68919,6 +71558,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, @@ -68934,12 +71574,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2472 Instruction:"SHRD Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x2C /r ib"/"MRI" + // Pos:2478 Instruction:"SHRD Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x2C /r ib"/"MRI" { .Instruction = ND_INS_SHRD, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 818, + .Mnemonic = 820, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -68948,6 +71588,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, @@ -68963,12 +71604,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2473 Instruction:"SHRD Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xAD /r"/"MRC" + // Pos:2479 Instruction:"SHRD Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xAD /r"/"MRC" { .Instruction = ND_INS_SHRD, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 818, + .Mnemonic = 820, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -68977,6 +71618,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, @@ -68992,12 +71634,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2474 Instruction:"SHRD Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x2C /r ib"/"MRI" + // Pos:2480 Instruction:"SHRD Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x2C /r ib"/"MRI" { .Instruction = ND_INS_SHRD, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 818, + .Mnemonic = 820, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -69006,6 +71648,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -69020,12 +71663,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2475 Instruction:"SHRD Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xAD /r"/"MRC" + // Pos:2481 Instruction:"SHRD Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xAD /r"/"MRC" { .Instruction = ND_INS_SHRD, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 818, + .Mnemonic = 820, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -69034,6 +71677,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -69048,12 +71692,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2476 Instruction:"SHRD Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x2C /r ib"/"MRI" + // Pos:2482 Instruction:"SHRD Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x2C /r ib"/"MRI" { .Instruction = ND_INS_SHRD, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 818, + .Mnemonic = 820, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -69062,6 +71706,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -69076,12 +71721,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2477 Instruction:"SHRD Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xAD /r"/"MRC" + // Pos:2483 Instruction:"SHRD Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xAD /r"/"MRC" { .Instruction = ND_INS_SHRD, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 818, + .Mnemonic = 820, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -69090,6 +71735,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -69104,12 +71750,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2478 Instruction:"SHRD Bv,Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x2C /r ib"/"VMRI" + // Pos:2484 Instruction:"SHRD Bv,Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x2C /r ib"/"VMRI" { .Instruction = ND_INS_SHRD, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 818, + .Mnemonic = 820, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -69118,6 +71764,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, @@ -69134,12 +71781,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2479 Instruction:"SHRD Bv,Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xAD /r"/"VMRC" + // Pos:2485 Instruction:"SHRD Bv,Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xAD /r"/"VMRC" { .Instruction = ND_INS_SHRD, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 818, + .Mnemonic = 820, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -69148,6 +71795,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, @@ -69164,12 +71812,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2480 Instruction:"SHRD Bv,Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x2C /r ib"/"VMRI" + // Pos:2486 Instruction:"SHRD Bv,Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x2C /r ib"/"VMRI" { .Instruction = ND_INS_SHRD, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 818, + .Mnemonic = 820, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -69178,6 +71826,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, @@ -69194,12 +71843,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2481 Instruction:"SHRD Bv,Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xAD /r"/"VMRC" + // Pos:2487 Instruction:"SHRD Bv,Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xAD /r"/"VMRC" { .Instruction = ND_INS_SHRD, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 818, + .Mnemonic = 820, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -69208,6 +71857,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, @@ -69224,12 +71874,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2482 Instruction:"SHRD Bv,Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x2C /r ib"/"VMRI" + // Pos:2488 Instruction:"SHRD Bv,Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x2C /r ib"/"VMRI" { .Instruction = ND_INS_SHRD, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 818, + .Mnemonic = 820, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -69238,6 +71888,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -69253,12 +71904,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2483 Instruction:"SHRD Bv,Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xAD /r"/"VMRC" + // Pos:2489 Instruction:"SHRD Bv,Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xAD /r"/"VMRC" { .Instruction = ND_INS_SHRD, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 818, + .Mnemonic = 820, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -69267,6 +71918,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -69282,12 +71934,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2484 Instruction:"SHRD Bv,Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x2C /r ib"/"VMRI" + // Pos:2490 Instruction:"SHRD Bv,Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x2C /r ib"/"VMRI" { .Instruction = ND_INS_SHRD, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 818, + .Mnemonic = 820, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -69296,6 +71948,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -69311,12 +71964,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2485 Instruction:"SHRD Bv,Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xAD /r"/"VMRC" + // Pos:2491 Instruction:"SHRD Bv,Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xAD /r"/"VMRC" { .Instruction = ND_INS_SHRD, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 818, + .Mnemonic = 820, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -69325,6 +71978,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -69340,12 +71994,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2486 Instruction:"SHRD Ev,Gv,Ib" Encoding:"0x0F 0xAC /r ib"/"MRI" + // Pos:2492 Instruction:"SHRD Ev,Gv,Ib" Encoding:"0x0F 0xAC /r ib"/"MRI" { .Instruction = ND_INS_SHRD, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_I386, - .Mnemonic = 818, + .Mnemonic = 820, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -69354,6 +72008,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, @@ -69369,12 +72024,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2487 Instruction:"SHRD Ev,Gv,CL" Encoding:"0x0F 0xAD /r"/"MRC" + // Pos:2493 Instruction:"SHRD Ev,Gv,CL" Encoding:"0x0F 0xAD /r"/"MRC" { .Instruction = ND_INS_SHRD, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_I386, - .Mnemonic = 818, + .Mnemonic = 820, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -69383,6 +72038,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, @@ -69398,12 +72054,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2488 Instruction:"SHRX Gy,Ey,By" Encoding:"evex m:2 p:3 l:0 nf:0 0xF7 /r"/"RMV" + // Pos:2494 Instruction:"SHRX Gy,Ey,By" Encoding:"evex m:2 p:3 l:0 nf:0 0xF7 /r"/"RMV" { .Instruction = ND_INS_SHRX, .Category = ND_CAT_BMI2, .IsaSet = ND_SET_APX_F, - .Mnemonic = 819, + .Mnemonic = 821, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -69412,6 +72068,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_BMI, .FpuFlags = 0, .EvexMode = ND_EVEXM_VEX, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -69426,12 +72083,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2489 Instruction:"SHRX Gy,Ey,By" Encoding:"vex m:2 p:3 l:0 w:x 0xF7 /r"/"RMV" + // Pos:2495 Instruction:"SHRX Gy,Ey,By" Encoding:"vex m:2 p:3 l:0 w:x 0xF7 /r"/"RMV" { .Instruction = ND_INS_SHRX, .Category = ND_CAT_BMI2, .IsaSet = ND_SET_BMI2, - .Mnemonic = 819, + .Mnemonic = 821, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -69440,6 +72097,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_13, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -69454,12 +72112,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2490 Instruction:"SHUFPD Vpd,Wpd,Ib" Encoding:"0x66 0x0F 0xC6 /r ib"/"RMI" + // Pos:2496 Instruction:"SHUFPD Vpd,Wpd,Ib" Encoding:"0x66 0x0F 0xC6 /r ib"/"RMI" { .Instruction = ND_INS_SHUFPD, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE2, - .Mnemonic = 820, + .Mnemonic = 822, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -69468,6 +72126,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -69482,12 +72141,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2491 Instruction:"SHUFPS Vps,Wps,Ib" Encoding:"NP 0x0F 0xC6 /r ib"/"RMI" + // Pos:2497 Instruction:"SHUFPS Vps,Wps,Ib" Encoding:"NP 0x0F 0xC6 /r ib"/"RMI" { .Instruction = ND_INS_SHUFPS, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE, - .Mnemonic = 821, + .Mnemonic = 823, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -69496,6 +72155,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -69510,12 +72170,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2492 Instruction:"SIDT Ms" Encoding:"0x0F 0x01 /1:mem"/"M" + // Pos:2498 Instruction:"SIDT Ms" Encoding:"0x0F 0x01 /1:mem"/"M" { .Instruction = ND_INS_SIDT, .Category = ND_CAT_SYSTEM, .IsaSet = ND_SET_I286REAL, - .Mnemonic = 822, + .Mnemonic = 824, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -69524,6 +72184,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -69537,12 +72198,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2493 Instruction:"SKINIT" Encoding:"0x0F 0x01 /0xDE"/"" + // Pos:2499 Instruction:"SKINIT" Encoding:"0x0F 0x01 /0xDE"/"" { .Instruction = ND_INS_SKINIT, .Category = ND_CAT_SYSTEM, .IsaSet = ND_SET_SVM, - .Mnemonic = 823, + .Mnemonic = 825, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, .ValidDecorators = 0, @@ -69551,6 +72212,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -69563,12 +72225,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2494 Instruction:"SLDT Mw" Encoding:"0x0F 0x00 /0:mem"/"M" + // Pos:2500 Instruction:"SLDT Mw" Encoding:"0x0F 0x00 /0:mem"/"M" { .Instruction = ND_INS_SLDT, .Category = ND_CAT_SYSTEM, .IsaSet = ND_SET_I286PROT, - .Mnemonic = 824, + .Mnemonic = 826, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -69577,6 +72239,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -69590,12 +72253,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2495 Instruction:"SLDT Rv" Encoding:"0x0F 0x00 /0:reg"/"M" + // Pos:2501 Instruction:"SLDT Rv" Encoding:"0x0F 0x00 /0:reg"/"M" { .Instruction = ND_INS_SLDT, .Category = ND_CAT_SYSTEM, .IsaSet = ND_SET_I286PROT, - .Mnemonic = 824, + .Mnemonic = 826, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -69604,6 +72267,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -69617,12 +72281,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2496 Instruction:"SLWPCB Ry" Encoding:"xop m:9 0x12 /1:reg"/"M" + // Pos:2502 Instruction:"SLWPCB Ry" Encoding:"xop m:9 0x12 /1:reg"/"M" { .Instruction = ND_INS_SLWPCB, .Category = ND_CAT_LWP, .IsaSet = ND_SET_LWP, - .Mnemonic = 825, + .Mnemonic = 827, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -69631,6 +72295,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -69643,12 +72308,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2497 Instruction:"SMSW Mw" Encoding:"0x0F 0x01 /4:mem"/"M" + // Pos:2503 Instruction:"SMSW Mw" Encoding:"0x0F 0x01 /4:mem"/"M" { .Instruction = ND_INS_SMSW, .Category = ND_CAT_SYSTEM, .IsaSet = ND_SET_I286REAL, - .Mnemonic = 826, + .Mnemonic = 828, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -69657,6 +72322,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -69670,12 +72336,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2498 Instruction:"SMSW Rv" Encoding:"0x0F 0x01 /4:reg"/"M" + // Pos:2504 Instruction:"SMSW Rv" Encoding:"0x0F 0x01 /4:reg"/"M" { .Instruction = ND_INS_SMSW, .Category = ND_CAT_SYSTEM, .IsaSet = ND_SET_I286REAL, - .Mnemonic = 826, + .Mnemonic = 828, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -69684,6 +72350,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -69697,12 +72364,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2499 Instruction:"SPFLT Ry" Encoding:"vex m:1 p:3 0xAE /6:reg"/"M" + // Pos:2505 Instruction:"SPFLT Ry" Encoding:"vex m:1 p:3 0xAE /6:reg"/"M" { .Instruction = ND_INS_SPFLT, .Category = ND_CAT_UNKNOWN, .IsaSet = ND_SET_UNKNOWN, - .Mnemonic = 827, + .Mnemonic = 829, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -69711,6 +72378,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -69723,12 +72391,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2500 Instruction:"SQRTPD Vpd,Wpd" Encoding:"0x66 0x0F 0x51 /r"/"RM" + // Pos:2506 Instruction:"SQRTPD Vpd,Wpd" Encoding:"0x66 0x0F 0x51 /r"/"RM" { .Instruction = ND_INS_SQRTPD, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE2, - .Mnemonic = 828, + .Mnemonic = 830, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -69737,6 +72405,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -69750,12 +72419,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2501 Instruction:"SQRTPS Vps,Wps" Encoding:"NP 0x0F 0x51 /r"/"RM" + // Pos:2507 Instruction:"SQRTPS Vps,Wps" Encoding:"NP 0x0F 0x51 /r"/"RM" { .Instruction = ND_INS_SQRTPS, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE, - .Mnemonic = 829, + .Mnemonic = 831, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -69764,6 +72433,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -69777,12 +72447,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2502 Instruction:"SQRTSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x51 /r"/"RM" + // Pos:2508 Instruction:"SQRTSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x51 /r"/"RM" { .Instruction = ND_INS_SQRTSD, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE2, - .Mnemonic = 830, + .Mnemonic = 832, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -69791,6 +72461,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -69804,12 +72475,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2503 Instruction:"SQRTSS Vss,Wss" Encoding:"0xF3 0x0F 0x51 /r"/"RM" + // Pos:2509 Instruction:"SQRTSS Vss,Wss" Encoding:"0xF3 0x0F 0x51 /r"/"RM" { .Instruction = ND_INS_SQRTSS, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE, - .Mnemonic = 831, + .Mnemonic = 833, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -69818,6 +72489,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -69831,12 +72503,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2504 Instruction:"STAC" Encoding:"NP 0x0F 0x01 /0xCB"/"" + // Pos:2510 Instruction:"STAC" Encoding:"NP 0x0F 0x01 /0xCB"/"" { .Instruction = ND_INS_STAC, .Category = ND_CAT_SMAP, .IsaSet = ND_SET_SMAP, - .Mnemonic = 832, + .Mnemonic = 834, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -69845,6 +72517,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0|NDR_RFLAG_AC, @@ -69857,12 +72530,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2505 Instruction:"STC" Encoding:"0xF9"/"" + // Pos:2511 Instruction:"STC" Encoding:"0xF9"/"" { .Instruction = ND_INS_STC, .Category = ND_CAT_FLAGOP, .IsaSet = ND_SET_I86, - .Mnemonic = 833, + .Mnemonic = 835, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -69871,6 +72544,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0|NDR_RFLAG_CF, @@ -69883,12 +72557,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2506 Instruction:"STD" Encoding:"0xFD"/"" + // Pos:2512 Instruction:"STD" Encoding:"0xFD"/"" { .Instruction = ND_INS_STD, .Category = ND_CAT_FLAGOP, .IsaSet = ND_SET_I86, - .Mnemonic = 834, + .Mnemonic = 836, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -69897,6 +72571,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0|NDR_RFLAG_DF, @@ -69909,12 +72584,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2507 Instruction:"STGI" Encoding:"0x0F 0x01 /0xDC"/"" + // Pos:2513 Instruction:"STGI" Encoding:"0x0F 0x01 /0xDC"/"" { .Instruction = ND_INS_STGI, .Category = ND_CAT_SYSTEM, .IsaSet = ND_SET_SVM, - .Mnemonic = 835, + .Mnemonic = 837, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, .ValidDecorators = 0, @@ -69923,6 +72598,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -69935,12 +72611,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2508 Instruction:"STI" Encoding:"0xFB"/"" + // Pos:2514 Instruction:"STI" Encoding:"0xFB"/"" { .Instruction = ND_INS_STI, .Category = ND_CAT_FLAGOP, .IsaSet = ND_SET_I86, - .Mnemonic = 836, + .Mnemonic = 838, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -69949,6 +72625,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0|NDR_RFLAG_IF, @@ -69961,12 +72638,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2509 Instruction:"STMXCSR Md" Encoding:"NP 0x0F 0xAE /3:mem"/"M" + // Pos:2515 Instruction:"STMXCSR Md" Encoding:"NP 0x0F 0xAE /3:mem"/"M" { .Instruction = ND_INS_STMXCSR, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE, - .Mnemonic = 837, + .Mnemonic = 839, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -69975,6 +72652,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -69988,12 +72666,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2510 Instruction:"STOSB Yb,AL" Encoding:"0xAA"/"" + // Pos:2516 Instruction:"STOSB Yb,AL" Encoding:"0xAA"/"" { .Instruction = ND_INS_STOS, .Category = ND_CAT_STRINGOP, .IsaSet = ND_SET_I86, - .Mnemonic = 838, + .Mnemonic = 840, .ValidPrefixes = ND_PREF_REP, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -70002,6 +72680,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_DF, .ModifiedFlags = 0, .SetFlags = 0, @@ -70017,12 +72696,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2511 Instruction:"STOSB Yb,AL" Encoding:"rep 0xAA"/"" + // Pos:2517 Instruction:"STOSB Yb,AL" Encoding:"rep 0xAA"/"" { .Instruction = ND_INS_STOS, .Category = ND_CAT_STRINGOP, .IsaSet = ND_SET_I86, - .Mnemonic = 838, + .Mnemonic = 840, .ValidPrefixes = ND_PREF_REP, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -70031,6 +72710,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_DF, .ModifiedFlags = 0, .SetFlags = 0, @@ -70047,12 +72727,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2512 Instruction:"STOSD Yv,EAX" Encoding:"ds32 0xAB"/"" + // Pos:2518 Instruction:"STOSD Yv,EAX" Encoding:"ds32 0xAB"/"" { .Instruction = ND_INS_STOS, .Category = ND_CAT_STRINGOP, .IsaSet = ND_SET_I86, - .Mnemonic = 839, + .Mnemonic = 841, .ValidPrefixes = ND_PREF_REP, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -70061,6 +72741,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_DF, .ModifiedFlags = 0, .SetFlags = 0, @@ -70076,12 +72757,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2513 Instruction:"STOSD Yv,EAX" Encoding:"rep ds32 0xAB"/"" + // Pos:2519 Instruction:"STOSD Yv,EAX" Encoding:"rep ds32 0xAB"/"" { .Instruction = ND_INS_STOS, .Category = ND_CAT_STRINGOP, .IsaSet = ND_SET_I86, - .Mnemonic = 839, + .Mnemonic = 841, .ValidPrefixes = ND_PREF_REP, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -70090,6 +72771,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_DF, .ModifiedFlags = 0, .SetFlags = 0, @@ -70106,12 +72788,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2514 Instruction:"STOSQ Yv,RAX" Encoding:"ds64 0xAB"/"" + // Pos:2520 Instruction:"STOSQ Yv,RAX" Encoding:"ds64 0xAB"/"" { .Instruction = ND_INS_STOS, .Category = ND_CAT_STRINGOP, .IsaSet = ND_SET_I86, - .Mnemonic = 840, + .Mnemonic = 842, .ValidPrefixes = ND_PREF_REP, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -70120,6 +72802,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_DF, .ModifiedFlags = 0, .SetFlags = 0, @@ -70135,12 +72818,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2515 Instruction:"STOSQ Yv,RAX" Encoding:"rep ds64 0xAB"/"" + // Pos:2521 Instruction:"STOSQ Yv,RAX" Encoding:"rep ds64 0xAB"/"" { .Instruction = ND_INS_STOS, .Category = ND_CAT_STRINGOP, .IsaSet = ND_SET_I86, - .Mnemonic = 840, + .Mnemonic = 842, .ValidPrefixes = ND_PREF_REP, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -70149,6 +72832,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_DF, .ModifiedFlags = 0, .SetFlags = 0, @@ -70165,12 +72849,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2516 Instruction:"STOSW Yv,AX" Encoding:"ds16 0xAB"/"" + // Pos:2522 Instruction:"STOSW Yv,AX" Encoding:"ds16 0xAB"/"" { .Instruction = ND_INS_STOS, .Category = ND_CAT_STRINGOP, .IsaSet = ND_SET_I86, - .Mnemonic = 841, + .Mnemonic = 843, .ValidPrefixes = ND_PREF_REP, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -70179,6 +72863,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_DF, .ModifiedFlags = 0, .SetFlags = 0, @@ -70194,12 +72879,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2517 Instruction:"STOSW Yv,AX" Encoding:"rep ds16 0xAB"/"" + // Pos:2523 Instruction:"STOSW Yv,AX" Encoding:"rep ds16 0xAB"/"" { .Instruction = ND_INS_STOS, .Category = ND_CAT_STRINGOP, .IsaSet = ND_SET_I86, - .Mnemonic = 841, + .Mnemonic = 843, .ValidPrefixes = ND_PREF_REP, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -70208,6 +72893,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0|NDR_RFLAG_DF, .ModifiedFlags = 0, .SetFlags = 0, @@ -70224,12 +72910,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2518 Instruction:"STR Mw" Encoding:"0x0F 0x00 /1:mem"/"M" + // Pos:2524 Instruction:"STR Mw" Encoding:"0x0F 0x00 /1:mem"/"M" { .Instruction = ND_INS_STR, .Category = ND_CAT_SYSTEM, .IsaSet = ND_SET_I286PROT, - .Mnemonic = 842, + .Mnemonic = 844, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -70238,6 +72924,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -70251,12 +72938,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2519 Instruction:"STR Rv" Encoding:"0x0F 0x00 /1:reg"/"M" + // Pos:2525 Instruction:"STR Rv" Encoding:"0x0F 0x00 /1:reg"/"M" { .Instruction = ND_INS_STR, .Category = ND_CAT_SYSTEM, .IsaSet = ND_SET_I286PROT, - .Mnemonic = 842, + .Mnemonic = 844, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -70265,6 +72952,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -70278,12 +72966,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2520 Instruction:"STTILECFG Moq" Encoding:"evex m:2 p:1 l:0 nf:0 w:0 0x49 /0:mem"/"M" + // Pos:2526 Instruction:"STTILECFG Moq" Encoding:"evex m:2 p:1 l:0 nf:0 w:0 0x49 /0:mem"/"M" { .Instruction = ND_INS_STTILECFG, .Category = ND_CAT_AMX, .IsaSet = ND_SET_APX_F, - .Mnemonic = 843, + .Mnemonic = 845, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -70292,6 +72980,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_AMX_EVEX_E2, .FpuFlags = 0, .EvexMode = ND_EVEXM_VEX, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -70304,12 +72993,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2521 Instruction:"STTILECFG Moq" Encoding:"vex m:2 p:1 l:0 w:0 0x49 /0:mem"/"M" + // Pos:2527 Instruction:"STTILECFG Moq" Encoding:"vex m:2 p:1 l:0 w:0 0x49 /0:mem"/"M" { .Instruction = ND_INS_STTILECFG, .Category = ND_CAT_AMX, .IsaSet = ND_SET_AMXTILE, - .Mnemonic = 843, + .Mnemonic = 845, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -70318,6 +73007,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_AMX_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -70330,12 +73020,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2522 Instruction:"STUI" Encoding:"0xF3 0x0F 0x01 /0xEF"/"" + // Pos:2528 Instruction:"STUI" Encoding:"0xF3 0x0F 0x01 /0xEF"/"" { .Instruction = ND_INS_STUI, .Category = ND_CAT_UINTR, .IsaSet = ND_SET_UINTR, - .Mnemonic = 844, + .Mnemonic = 846, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -70344,6 +73034,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -70356,12 +73047,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2523 Instruction:"SUB Eb,Gb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x28 /r"/"MR" + // Pos:2529 Instruction:"SUB Eb,Gb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x28 /r"/"MR" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 845, + .Mnemonic = 847, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -70370,6 +73061,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -70384,12 +73076,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2524 Instruction:"SUB Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x29 /r"/"MR" + // Pos:2530 Instruction:"SUB Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x29 /r"/"MR" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 845, + .Mnemonic = 847, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -70398,6 +73090,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -70412,12 +73105,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2525 Instruction:"SUB Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x29 /r"/"MR" + // Pos:2531 Instruction:"SUB Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x29 /r"/"MR" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 845, + .Mnemonic = 847, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -70426,6 +73119,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -70440,12 +73134,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2526 Instruction:"SUB Gb,Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x2A /r"/"RM" + // Pos:2532 Instruction:"SUB Gb,Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x2A /r"/"RM" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 845, + .Mnemonic = 847, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -70454,6 +73148,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -70468,12 +73163,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2527 Instruction:"SUB Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x2B /r"/"RM" + // Pos:2533 Instruction:"SUB Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x2B /r"/"RM" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 845, + .Mnemonic = 847, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -70482,6 +73177,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -70496,12 +73192,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2528 Instruction:"SUB Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x2B /r"/"RM" + // Pos:2534 Instruction:"SUB Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x2B /r"/"RM" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 845, + .Mnemonic = 847, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -70510,6 +73206,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -70524,12 +73221,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2529 Instruction:"SUB Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x80 /5 ib"/"MI" + // Pos:2535 Instruction:"SUB Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x80 /5 ib"/"MI" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 845, + .Mnemonic = 847, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -70538,6 +73235,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -70552,12 +73250,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2530 Instruction:"SUB Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x81 /5 iz"/"MI" + // Pos:2536 Instruction:"SUB Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x81 /5 iz"/"MI" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 845, + .Mnemonic = 847, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -70566,6 +73264,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -70580,12 +73279,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2531 Instruction:"SUB Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x81 /5 iz"/"MI" + // Pos:2537 Instruction:"SUB Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x81 /5 iz"/"MI" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 845, + .Mnemonic = 847, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -70594,6 +73293,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -70608,12 +73308,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2532 Instruction:"SUB Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x83 /5 ib"/"MI" + // Pos:2538 Instruction:"SUB Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x83 /5 ib"/"MI" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 845, + .Mnemonic = 847, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -70622,6 +73322,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -70636,12 +73337,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2533 Instruction:"SUB Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x83 /5 ib"/"MI" + // Pos:2539 Instruction:"SUB Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x83 /5 ib"/"MI" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 845, + .Mnemonic = 847, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -70650,6 +73351,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -70664,12 +73366,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2534 Instruction:"SUB Eb,Gb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x28 /r"/"MR" + // Pos:2540 Instruction:"SUB Eb,Gb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x28 /r"/"MR" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 845, + .Mnemonic = 847, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -70678,6 +73380,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -70691,12 +73394,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2535 Instruction:"SUB Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x29 /r"/"MR" + // Pos:2541 Instruction:"SUB Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x29 /r"/"MR" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 845, + .Mnemonic = 847, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -70705,6 +73408,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -70718,12 +73422,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2536 Instruction:"SUB Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x29 /r"/"MR" + // Pos:2542 Instruction:"SUB Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x29 /r"/"MR" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 845, + .Mnemonic = 847, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -70732,6 +73436,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -70745,12 +73450,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2537 Instruction:"SUB Gb,Eb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x2A /r"/"RM" + // Pos:2543 Instruction:"SUB Gb,Eb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x2A /r"/"RM" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 845, + .Mnemonic = 847, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -70759,6 +73464,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -70772,12 +73478,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2538 Instruction:"SUB Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x2B /r"/"RM" + // Pos:2544 Instruction:"SUB Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x2B /r"/"RM" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 845, + .Mnemonic = 847, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -70786,6 +73492,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -70799,12 +73506,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2539 Instruction:"SUB Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x2B /r"/"RM" + // Pos:2545 Instruction:"SUB Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x2B /r"/"RM" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 845, + .Mnemonic = 847, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -70813,6 +73520,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -70826,12 +73534,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2540 Instruction:"SUB Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x80 /5 ib"/"MI" + // Pos:2546 Instruction:"SUB Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x80 /5 ib"/"MI" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 845, + .Mnemonic = 847, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -70840,6 +73548,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -70853,12 +73562,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2541 Instruction:"SUB Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x81 /5 iz"/"MI" + // Pos:2547 Instruction:"SUB Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x81 /5 iz"/"MI" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 845, + .Mnemonic = 847, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -70867,6 +73576,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -70880,12 +73590,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2542 Instruction:"SUB Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x81 /5 iz"/"MI" + // Pos:2548 Instruction:"SUB Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x81 /5 iz"/"MI" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 845, + .Mnemonic = 847, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -70894,6 +73604,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -70907,12 +73618,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2543 Instruction:"SUB Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x83 /5 ib"/"MI" + // Pos:2549 Instruction:"SUB Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x83 /5 ib"/"MI" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 845, + .Mnemonic = 847, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -70921,6 +73632,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -70934,12 +73646,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2544 Instruction:"SUB Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x83 /5 ib"/"MI" + // Pos:2550 Instruction:"SUB Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x83 /5 ib"/"MI" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 845, + .Mnemonic = 847, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -70948,6 +73660,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -70961,12 +73674,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2545 Instruction:"SUB Bb,Eb,Gb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x28 /r"/"VMR" + // Pos:2551 Instruction:"SUB Bb,Eb,Gb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x28 /r"/"VMR" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 845, + .Mnemonic = 847, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -70975,6 +73688,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -70990,12 +73704,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2546 Instruction:"SUB Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x29 /r"/"VMR" + // Pos:2552 Instruction:"SUB Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x29 /r"/"VMR" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 845, + .Mnemonic = 847, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -71004,6 +73718,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -71019,12 +73734,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2547 Instruction:"SUB Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x29 /r"/"VMR" + // Pos:2553 Instruction:"SUB Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x29 /r"/"VMR" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 845, + .Mnemonic = 847, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -71033,6 +73748,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -71048,12 +73764,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2548 Instruction:"SUB Bb,Gb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x2A /r"/"VRM" + // Pos:2554 Instruction:"SUB Bb,Gb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x2A /r"/"VRM" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 845, + .Mnemonic = 847, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -71062,6 +73778,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -71077,12 +73794,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2549 Instruction:"SUB Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x2B /r"/"VRM" + // Pos:2555 Instruction:"SUB Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x2B /r"/"VRM" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 845, + .Mnemonic = 847, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -71091,6 +73808,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -71106,12 +73824,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2550 Instruction:"SUB Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x2B /r"/"VRM" + // Pos:2556 Instruction:"SUB Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x2B /r"/"VRM" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 845, + .Mnemonic = 847, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -71120,6 +73838,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -71135,12 +73854,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2551 Instruction:"SUB Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x80 /5 ib"/"VMI" + // Pos:2557 Instruction:"SUB Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x80 /5 ib"/"VMI" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 845, + .Mnemonic = 847, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -71149,6 +73868,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -71164,12 +73884,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2552 Instruction:"SUB Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x81 /5 iz"/"VMI" + // Pos:2558 Instruction:"SUB Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x81 /5 iz"/"VMI" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 845, + .Mnemonic = 847, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -71178,6 +73898,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -71193,12 +73914,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2553 Instruction:"SUB Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x81 /5 iz"/"VMI" + // Pos:2559 Instruction:"SUB Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x81 /5 iz"/"VMI" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 845, + .Mnemonic = 847, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -71207,6 +73928,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -71222,12 +73944,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2554 Instruction:"SUB Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x83 /5 ib"/"VMI" + // Pos:2560 Instruction:"SUB Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x83 /5 ib"/"VMI" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 845, + .Mnemonic = 847, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -71236,6 +73958,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -71251,12 +73974,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2555 Instruction:"SUB Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x83 /5 ib"/"VMI" + // Pos:2561 Instruction:"SUB Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x83 /5 ib"/"VMI" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 845, + .Mnemonic = 847, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -71265,6 +73988,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -71280,12 +74004,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2556 Instruction:"SUB Bb,Eb,Gb" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x28 /r"/"VMR" + // Pos:2562 Instruction:"SUB Bb,Eb,Gb" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x28 /r"/"VMR" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 845, + .Mnemonic = 847, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -71294,6 +74018,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -71308,12 +74033,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2557 Instruction:"SUB Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x29 /r"/"VMR" + // Pos:2563 Instruction:"SUB Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x29 /r"/"VMR" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 845, + .Mnemonic = 847, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -71322,6 +74047,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -71336,12 +74062,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2558 Instruction:"SUB Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x29 /r"/"VMR" + // Pos:2564 Instruction:"SUB Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x29 /r"/"VMR" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 845, + .Mnemonic = 847, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -71350,6 +74076,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -71364,12 +74091,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2559 Instruction:"SUB Bb,Gb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x2A /r"/"VRM" + // Pos:2565 Instruction:"SUB Bb,Gb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x2A /r"/"VRM" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 845, + .Mnemonic = 847, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -71378,6 +74105,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -71392,12 +74120,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2560 Instruction:"SUB Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x2B /r"/"VRM" + // Pos:2566 Instruction:"SUB Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x2B /r"/"VRM" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 845, + .Mnemonic = 847, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -71406,6 +74134,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -71420,12 +74149,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2561 Instruction:"SUB Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x2B /r"/"VRM" + // Pos:2567 Instruction:"SUB Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x2B /r"/"VRM" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 845, + .Mnemonic = 847, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -71434,6 +74163,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -71448,12 +74178,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2562 Instruction:"SUB Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x80 /5 ib"/"VMI" + // Pos:2568 Instruction:"SUB Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x80 /5 ib"/"VMI" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 845, + .Mnemonic = 847, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -71462,6 +74192,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -71476,12 +74207,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2563 Instruction:"SUB Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x81 /5 iz"/"VMI" + // Pos:2569 Instruction:"SUB Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x81 /5 iz"/"VMI" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 845, + .Mnemonic = 847, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -71490,6 +74221,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -71504,12 +74236,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2564 Instruction:"SUB Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x81 /5 iz"/"VMI" + // Pos:2570 Instruction:"SUB Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x81 /5 iz"/"VMI" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 845, + .Mnemonic = 847, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -71518,6 +74250,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -71532,12 +74265,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2565 Instruction:"SUB Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x83 /5 ib"/"VMI" + // Pos:2571 Instruction:"SUB Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x83 /5 ib"/"VMI" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 845, + .Mnemonic = 847, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -71546,6 +74279,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -71560,12 +74294,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2566 Instruction:"SUB Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x83 /5 ib"/"VMI" + // Pos:2572 Instruction:"SUB Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x83 /5 ib"/"VMI" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 845, + .Mnemonic = 847, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -71574,6 +74308,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -71588,12 +74323,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2567 Instruction:"SUB Eb,Gb" Encoding:"0x28 /r"/"MR" + // Pos:2573 Instruction:"SUB Eb,Gb" Encoding:"0x28 /r"/"MR" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_I86, - .Mnemonic = 845, + .Mnemonic = 847, .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -71602,6 +74337,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -71616,12 +74352,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2568 Instruction:"SUB Ev,Gv" Encoding:"0x29 /r"/"MR" + // Pos:2574 Instruction:"SUB Ev,Gv" Encoding:"0x29 /r"/"MR" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_I86, - .Mnemonic = 845, + .Mnemonic = 847, .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -71630,6 +74366,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -71644,12 +74381,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2569 Instruction:"SUB Gb,Eb" Encoding:"0x2A /r"/"RM" + // Pos:2575 Instruction:"SUB Gb,Eb" Encoding:"0x2A /r"/"RM" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_I86, - .Mnemonic = 845, + .Mnemonic = 847, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -71658,6 +74395,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -71672,12 +74410,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2570 Instruction:"SUB Gv,Ev" Encoding:"0x2B /r"/"RM" + // Pos:2576 Instruction:"SUB Gv,Ev" Encoding:"0x2B /r"/"RM" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_I86, - .Mnemonic = 845, + .Mnemonic = 847, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -71686,6 +74424,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -71700,12 +74439,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2571 Instruction:"SUB AL,Ib" Encoding:"0x2C ib"/"I" + // Pos:2577 Instruction:"SUB AL,Ib" Encoding:"0x2C ib"/"I" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_I86, - .Mnemonic = 845, + .Mnemonic = 847, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -71714,6 +74453,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -71728,12 +74468,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2572 Instruction:"SUB rAX,Iz" Encoding:"0x2D iz"/"I" + // Pos:2578 Instruction:"SUB rAX,Iz" Encoding:"0x2D iz"/"I" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_I86, - .Mnemonic = 845, + .Mnemonic = 847, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -71742,6 +74482,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -71756,12 +74497,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2573 Instruction:"SUB Eb,Ib" Encoding:"0x80 /5 ib"/"MI" + // Pos:2579 Instruction:"SUB Eb,Ib" Encoding:"0x80 /5 ib"/"MI" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_I86, - .Mnemonic = 845, + .Mnemonic = 847, .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -71770,6 +74511,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -71784,12 +74526,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2574 Instruction:"SUB Ev,Iz" Encoding:"0x81 /5 iz"/"MI" + // Pos:2580 Instruction:"SUB Ev,Iz" Encoding:"0x81 /5 iz"/"MI" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_I86, - .Mnemonic = 845, + .Mnemonic = 847, .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -71798,6 +74540,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -71812,12 +74555,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2575 Instruction:"SUB Eb,Ib" Encoding:"0x82 /5 iz"/"MI" + // Pos:2581 Instruction:"SUB Eb,Ib" Encoding:"0x82 /5 iz"/"MI" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_I86, - .Mnemonic = 845, + .Mnemonic = 847, .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -71826,6 +74569,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -71840,12 +74584,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2576 Instruction:"SUB Ev,Ib" Encoding:"0x83 /5 ib"/"MI" + // Pos:2582 Instruction:"SUB Ev,Ib" Encoding:"0x83 /5 ib"/"MI" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_I86, - .Mnemonic = 845, + .Mnemonic = 847, .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -71854,6 +74598,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -71868,12 +74613,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2577 Instruction:"SUBPD Vpd,Wpd" Encoding:"0x66 0x0F 0x5C /r"/"RM" + // Pos:2583 Instruction:"SUBPD Vpd,Wpd" Encoding:"0x66 0x0F 0x5C /r"/"RM" { .Instruction = ND_INS_SUBPD, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE2, - .Mnemonic = 846, + .Mnemonic = 848, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -71882,6 +74627,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -71895,12 +74641,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2578 Instruction:"SUBPS Vps,Wps" Encoding:"NP 0x0F 0x5C /r"/"RM" + // Pos:2584 Instruction:"SUBPS Vps,Wps" Encoding:"NP 0x0F 0x5C /r"/"RM" { .Instruction = ND_INS_SUBPS, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE, - .Mnemonic = 847, + .Mnemonic = 849, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -71909,6 +74655,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -71922,12 +74669,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2579 Instruction:"SUBSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x5C /r"/"RM" + // Pos:2585 Instruction:"SUBSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x5C /r"/"RM" { .Instruction = ND_INS_SUBSD, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE2, - .Mnemonic = 848, + .Mnemonic = 850, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -71936,6 +74683,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -71949,12 +74697,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2580 Instruction:"SUBSS Vss,Wss" Encoding:"0xF3 0x0F 0x5C /r"/"RM" + // Pos:2586 Instruction:"SUBSS Vss,Wss" Encoding:"0xF3 0x0F 0x5C /r"/"RM" { .Instruction = ND_INS_SUBSS, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE, - .Mnemonic = 849, + .Mnemonic = 851, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -71963,6 +74711,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -71976,12 +74725,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2581 Instruction:"SWAPGS" Encoding:"0x0F 0x01 /0xF8"/"" + // Pos:2587 Instruction:"SWAPGS" Encoding:"0x0F 0x01 /0xF8"/"" { .Instruction = ND_INS_SWAPGS, .Category = ND_CAT_SYSTEM, .IsaSet = ND_SET_LONGMODE, - .Mnemonic = 850, + .Mnemonic = 852, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -71990,6 +74739,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -72003,12 +74753,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2582 Instruction:"SYSCALL" Encoding:"0x0F 0x05"/"" + // Pos:2588 Instruction:"SYSCALL" Encoding:"0x0F 0x05"/"" { .Instruction = ND_INS_SYSCALL, .Category = ND_CAT_SYSCALL, .IsaSet = ND_SET_AMD, - .Mnemonic = 851, + .Mnemonic = 853, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -72017,6 +74767,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -72038,12 +74789,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2583 Instruction:"SYSENTER" Encoding:"0x0F 0x34"/"" + // Pos:2589 Instruction:"SYSENTER" Encoding:"0x0F 0x34"/"" { .Instruction = ND_INS_SYSENTER, .Category = ND_CAT_SYSCALL, .IsaSet = ND_SET_PPRO, - .Mnemonic = 852, + .Mnemonic = 854, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -72052,6 +74803,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -72072,12 +74824,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2584 Instruction:"SYSEXIT" Encoding:"0x0F 0x35"/"" + // Pos:2590 Instruction:"SYSEXIT" Encoding:"0x0F 0x35"/"" { .Instruction = ND_INS_SYSEXIT, .Category = ND_CAT_SYSRET, .IsaSet = ND_SET_PPRO, - .Mnemonic = 853, + .Mnemonic = 855, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -72086,6 +74838,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -72105,12 +74858,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2585 Instruction:"SYSRET" Encoding:"0x0F 0x07"/"" + // Pos:2591 Instruction:"SYSRET" Encoding:"0x0F 0x07"/"" { .Instruction = ND_INS_SYSRET, .Category = ND_CAT_SYSRET, .IsaSet = ND_SET_AMD, - .Mnemonic = 854, + .Mnemonic = 856, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -72119,6 +74872,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -72138,12 +74892,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2586 Instruction:"T1MSKC By,Ey" Encoding:"xop m:9 0x01 /7"/"VM" + // Pos:2592 Instruction:"T1MSKC By,Ey" Encoding:"xop m:9 0x01 /7"/"VM" { .Instruction = ND_INS_T1MSKC, .Category = ND_CAT_BITBYTE, .IsaSet = ND_SET_TBM, - .Mnemonic = 855, + .Mnemonic = 857, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -72152,6 +74906,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -72165,40 +74920,236 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2587 Instruction:"TCMMIMFP16PS rTt,mTt,vTt" Encoding:"vex m:2 p:1 l:0 w:0 0x6C /r:reg"/"" + // Pos:2593 Instruction:"T2RPNTLVWZ0 rTt+1,Mt" Encoding:"vex m:2 p:0 l:0 w:0 0x6E /r:mem sibmem"/"M" { - .Instruction = ND_INS_TCMMIMFP16PS, + .Instruction = ND_INS_T2RPNTLVWZ0, .Category = ND_CAT_AMX, - .IsaSet = ND_SET_AMXCOMPLEX, - .Mnemonic = 856, + .IsaSet = ND_SET_AMXTRANSPOSE, + .Mnemonic = 858, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(3, 0), + .OpsCount = ND_OPS_CNT(2, 0), .TupleType = 0, - .ExcType = ND_EXT_AMX_E4, + .ExcType = ND_EXT_AMX_E11, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_O64, - .CpuidFlag = ND_CFF_AMXCOMPLEX, + .Attributes = ND_FLAG_MODRM|ND_FLAG_SIBMEM|ND_FLAG_NOV|ND_FLAG_O64, + .CpuidFlag = ND_CFF_AMXTRANSPOSE, .Operands = { - OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_vT, ND_OPS_t, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_W, 0, 2), + OP(ND_OPT_M, ND_OPS_t, 0, ND_OPA_R, 0, 0), }, }, - // Pos:2588 Instruction:"TCMMRLFP16PS rTt,mTt,vTt" Encoding:"vex m:2 p:0 l:0 w:0 0x6C /r:reg"/"" + // Pos:2594 Instruction:"T2RPNTLVWZ0RS rTt+1,Mt" Encoding:"vex m:5 p:0 l:0 w:0 0xF8 /r:mem sibmem"/"M" { - .Instruction = ND_INS_TCMMRLFP16PS, + .Instruction = ND_INS_T2RPNTLVWZ0RS, + .Category = ND_CAT_AMX, + .IsaSet = ND_SET_AMXTRANSPOSE, + .Mnemonic = 859, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_AMX_E11, + .FpuFlags = 0, + .EvexMode = 0, + .SimdExc = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_SIBMEM|ND_FLAG_NOV|ND_FLAG_O64, + .CpuidFlag = ND_CFF_AMXTRANSPOSE, + .Operands = + { + OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_W, 0, 2), + OP(ND_OPT_M, ND_OPS_t, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2595 Instruction:"T2RPNTLVWZ0RST1 rTt+1,Mt" Encoding:"vex m:5 p:0 l:0 w:0 0xF9 /r:mem sibmem"/"M" + { + .Instruction = ND_INS_T2RPNTLVWZ0RST1, + .Category = ND_CAT_AMX, + .IsaSet = ND_SET_AMXTRANSPOSE, + .Mnemonic = 860, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_AMX_E11, + .FpuFlags = 0, + .EvexMode = 0, + .SimdExc = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_SIBMEM|ND_FLAG_NOV|ND_FLAG_O64, + .CpuidFlag = ND_CFF_AMXTRANSPOSE, + .Operands = + { + OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_W, 0, 2), + OP(ND_OPT_M, ND_OPS_t, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2596 Instruction:"T2RPNTLVWZ0T1 rTt+1,Mt" Encoding:"vex m:2 p:0 l:0 w:0 0x6F /r:mem sibmem"/"M" + { + .Instruction = ND_INS_T2RPNTLVWZ0T1, + .Category = ND_CAT_AMX, + .IsaSet = ND_SET_AMXTRANSPOSE, + .Mnemonic = 861, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_AMX_E11, + .FpuFlags = 0, + .EvexMode = 0, + .SimdExc = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_SIBMEM|ND_FLAG_NOV|ND_FLAG_O64, + .CpuidFlag = ND_CFF_AMXTRANSPOSE, + .Operands = + { + OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_W, 0, 2), + OP(ND_OPT_M, ND_OPS_t, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2597 Instruction:"T2RPNTLVWZ1 rTt+1,Mt" Encoding:"vex m:2 p:1 l:0 w:0 0x6E /r:mem sibmem"/"M" + { + .Instruction = ND_INS_T2RPNTLVWZ1, + .Category = ND_CAT_AMX, + .IsaSet = ND_SET_AMXTRANSPOSE, + .Mnemonic = 862, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_AMX_E11, + .FpuFlags = 0, + .EvexMode = 0, + .SimdExc = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_SIBMEM|ND_FLAG_NOV|ND_FLAG_O64, + .CpuidFlag = ND_CFF_AMXTRANSPOSE, + .Operands = + { + OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_W, 0, 2), + OP(ND_OPT_M, ND_OPS_t, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2598 Instruction:"T2RPNTLVWZ1RS rTt+1,Mt" Encoding:"vex m:5 p:1 l:0 w:0 0xF8 /r:mem sibmem"/"M" + { + .Instruction = ND_INS_T2RPNTLVWZ1RS, + .Category = ND_CAT_AMX, + .IsaSet = ND_SET_AMXTRANSPOSE, + .Mnemonic = 863, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_AMX_E11, + .FpuFlags = 0, + .EvexMode = 0, + .SimdExc = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_SIBMEM|ND_FLAG_NOV|ND_FLAG_O64, + .CpuidFlag = ND_CFF_AMXTRANSPOSE, + .Operands = + { + OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_W, 0, 2), + OP(ND_OPT_M, ND_OPS_t, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2599 Instruction:"T2RPNTLVWZ1RST1 rTt+1,Mt" Encoding:"vex m:5 p:1 l:0 w:0 0xF9 /r:mem sibmem"/"M" + { + .Instruction = ND_INS_T2RPNTLVWZ1RST1, + .Category = ND_CAT_AMX, + .IsaSet = ND_SET_AMXTRANSPOSE, + .Mnemonic = 864, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_AMX_E11, + .FpuFlags = 0, + .EvexMode = 0, + .SimdExc = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_SIBMEM|ND_FLAG_NOV|ND_FLAG_O64, + .CpuidFlag = ND_CFF_AMXTRANSPOSE, + .Operands = + { + OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_W, 0, 2), + OP(ND_OPT_M, ND_OPS_t, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2600 Instruction:"T2RPNTLVWZ1T1 rTt+1,Mt" Encoding:"vex m:2 p:1 l:0 w:0 0x6F /r:mem sibmem"/"M" + { + .Instruction = ND_INS_T2RPNTLVWZ1T1, + .Category = ND_CAT_AMX, + .IsaSet = ND_SET_AMXTRANSPOSE, + .Mnemonic = 865, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_AMX_E11, + .FpuFlags = 0, + .EvexMode = 0, + .SimdExc = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_SIBMEM|ND_FLAG_NOV|ND_FLAG_O64, + .CpuidFlag = ND_CFF_AMXTRANSPOSE, + .Operands = + { + OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_W, 0, 2), + OP(ND_OPT_M, ND_OPS_t, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2601 Instruction:"TCMMIMFP16PS rTt,mTt,vTt" Encoding:"vex m:2 p:1 l:0 w:0 0x6C /r:reg"/"" + { + .Instruction = ND_INS_TCMMIMFP16PS, .Category = ND_CAT_AMX, .IsaSet = ND_SET_AMXCOMPLEX, - .Mnemonic = 857, + .Mnemonic = 866, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -72207,6 +75158,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_AMX_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -72221,12 +75173,388 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2589 Instruction:"TDCALL" Encoding:"0x66 0x0F 0x01 /0xCC"/"" + // Pos:2602 Instruction:"TCMMRLFP16PS rTt,mTt,vTt" Encoding:"vex m:2 p:0 l:0 w:0 0x6C /r:reg"/"" + { + .Instruction = ND_INS_TCMMRLFP16PS, + .Category = ND_CAT_AMX, + .IsaSet = ND_SET_AMXCOMPLEX, + .Mnemonic = 867, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_AMX_E4, + .FpuFlags = 0, + .EvexMode = 0, + .SimdExc = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_O64, + .CpuidFlag = ND_CFF_AMXCOMPLEX, + .Operands = + { + OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_vT, ND_OPS_t, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2603 Instruction:"TCONJTCMMIMFP16PS rTt,mTt,vTt" Encoding:"vex m:2 p:0 l:0 w:0 0x6B /r:reg"/"" + { + .Instruction = ND_INS_TCONJTCMMIMFP16PS, + .Category = ND_CAT_AMX, + .IsaSet = ND_SET_AMXTRANSPOSE, + .Mnemonic = 868, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_AMX_E10, + .FpuFlags = 0, + .EvexMode = 0, + .SimdExc = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_O64, + .CpuidFlag = ND_CFF_AMXTRANSPOSE, + .Operands = + { + OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_vT, ND_OPS_t, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2604 Instruction:"TCONJTFP16 rTt,mTt" Encoding:"vex m:2 p:1 l:0 w:0 0x6B /r:reg"/"" + { + .Instruction = ND_INS_TCONJTFP16, + .Category = ND_CAT_AMX, + .IsaSet = ND_SET_AMXTRANSPOSE, + .Mnemonic = 869, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_AMX_E9, + .FpuFlags = 0, + .EvexMode = 0, + .SimdExc = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_O64, + .CpuidFlag = ND_CFF_AMXTRANSPOSE, + .Operands = + { + OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2605 Instruction:"TCVTROWD2PS Voq,mTt,Bd" Encoding:"evex m:2 p:2 l:2 w:0 0x4A /r:reg"/"RV" + { + .Instruction = ND_INS_TCVTROWD2PS, + .Category = ND_CAT_AMX, + .IsaSet = ND_SET_AMXAVX512, + .Mnemonic = 870, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_AMX_EVEX_E8, + .FpuFlags = 0, + .EvexMode = 0, + .SimdExc = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AMXAVX512, + .Operands = + { + OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_B, ND_OPS_d, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2606 Instruction:"TCVTROWD2PS Voq,mTt,Ib" Encoding:"evex m:3 p:2 l:2 w:0 0x07 /r:reg ib"/"RI" + { + .Instruction = ND_INS_TCVTROWD2PS, + .Category = ND_CAT_AMX, + .IsaSet = ND_SET_AMXAVX512, + .Mnemonic = 870, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_AMX_EVEX_E7, + .FpuFlags = 0, + .EvexMode = 0, + .SimdExc = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AMXAVX512, + .Operands = + { + OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2607 Instruction:"TCVTROWPS2PBF16H Voq,mTt,Bd" Encoding:"evex m:2 p:3 l:2 w:0 0x6D /r:reg"/"RV" + { + .Instruction = ND_INS_TCVTROWPS2PBF16H, + .Category = ND_CAT_AMX, + .IsaSet = ND_SET_AMXAVX512, + .Mnemonic = 871, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_AMX_EVEX_E8, + .FpuFlags = 0, + .EvexMode = 0, + .SimdExc = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AMXAVX512, + .Operands = + { + OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_B, ND_OPS_d, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2608 Instruction:"TCVTROWPS2PBF16H Voq,mTt,Ib" Encoding:"evex m:3 p:3 l:2 w:0 0x07 /r:reg ib"/"RI" + { + .Instruction = ND_INS_TCVTROWPS2PBF16H, + .Category = ND_CAT_AMX, + .IsaSet = ND_SET_AMXAVX512, + .Mnemonic = 871, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_AMX_EVEX_E7, + .FpuFlags = 0, + .EvexMode = 0, + .SimdExc = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AMXAVX512, + .Operands = + { + OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2609 Instruction:"TCVTROWPS2PBF16L Voq,mTt,Bd" Encoding:"evex m:2 p:2 l:2 w:0 0x6D /r:reg"/"RV" + { + .Instruction = ND_INS_TCVTROWPS2PBF16L, + .Category = ND_CAT_AMX, + .IsaSet = ND_SET_AMXAVX512, + .Mnemonic = 872, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_AMX_EVEX_E8, + .FpuFlags = 0, + .EvexMode = 0, + .SimdExc = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AMXAVX512, + .Operands = + { + OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_B, ND_OPS_d, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2610 Instruction:"TCVTROWPS2PBF16L Voq,mTt,Ib" Encoding:"evex m:3 p:2 l:2 w:0 0x77 /r:reg ib"/"RI" + { + .Instruction = ND_INS_TCVTROWPS2PBF16L, + .Category = ND_CAT_AMX, + .IsaSet = ND_SET_AMXAVX512, + .Mnemonic = 872, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_AMX_EVEX_E7, + .FpuFlags = 0, + .EvexMode = 0, + .SimdExc = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AMXAVX512, + .Operands = + { + OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2611 Instruction:"TCVTROWPS2PHH Voq,mTt,Bd" Encoding:"evex m:2 p:0 l:2 w:0 0x6D /r:reg"/"RV" + { + .Instruction = ND_INS_TCVTROWPS2PHH, + .Category = ND_CAT_AMX, + .IsaSet = ND_SET_AMXAVX512, + .Mnemonic = 873, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_AMX_EVEX_E8, + .FpuFlags = 0, + .EvexMode = 0, + .SimdExc = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AMXAVX512, + .Operands = + { + OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_B, ND_OPS_d, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2612 Instruction:"TCVTROWPS2PHH Voq,mTt,Ib" Encoding:"evex m:3 p:0 l:2 w:0 0x07 /r:reg ib"/"RI" + { + .Instruction = ND_INS_TCVTROWPS2PHH, + .Category = ND_CAT_AMX, + .IsaSet = ND_SET_AMXAVX512, + .Mnemonic = 873, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_AMX_EVEX_E7, + .FpuFlags = 0, + .EvexMode = 0, + .SimdExc = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AMXAVX512, + .Operands = + { + OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2613 Instruction:"TCVTROWPS2PHL Voq,mTt,Bd" Encoding:"evex m:2 p:1 l:2 w:0 0x6D /r:reg"/"RV" + { + .Instruction = ND_INS_TCVTROWPS2PHL, + .Category = ND_CAT_AMX, + .IsaSet = ND_SET_AMXAVX512, + .Mnemonic = 874, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_AMX_EVEX_E8, + .FpuFlags = 0, + .EvexMode = 0, + .SimdExc = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AMXAVX512, + .Operands = + { + OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_B, ND_OPS_d, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2614 Instruction:"TCVTROWPS2PHL Voq,mTt,Ib" Encoding:"evex m:3 p:3 l:2 w:0 0x77 /r:reg ib"/"RI" + { + .Instruction = ND_INS_TCVTROWPS2PHL, + .Category = ND_CAT_AMX, + .IsaSet = ND_SET_AMXAVX512, + .Mnemonic = 874, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_AMX_EVEX_E7, + .FpuFlags = 0, + .EvexMode = 0, + .SimdExc = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AMXAVX512, + .Operands = + { + OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2615 Instruction:"TDCALL" Encoding:"0x66 0x0F 0x01 /0xCC"/"" { .Instruction = ND_INS_TDCALL, .Category = ND_CAT_TDX, .IsaSet = ND_SET_TDX, - .Mnemonic = 858, + .Mnemonic = 875, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXN|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -72235,6 +75563,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -72247,12 +75576,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2590 Instruction:"TDPBF16PS rTt,mTt,vTt" Encoding:"vex m:2 p:2 l:0 w:0 0x5C /r:reg"/"" + // Pos:2616 Instruction:"TDPBF16PS rTt,mTt,vTt" Encoding:"vex m:2 p:2 l:0 w:0 0x5C /r:reg"/"" { .Instruction = ND_INS_TDPBF16PS, .Category = ND_CAT_AMX, .IsaSet = ND_SET_AMXBF16, - .Mnemonic = 859, + .Mnemonic = 876, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -72261,6 +75590,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_AMX_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -72275,12 +75605,70 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2591 Instruction:"TDPBSSD rTt,mTt,vTt" Encoding:"vex m:2 p:3 l:0 w:0 0x5E /r:reg"/"" + // Pos:2617 Instruction:"TDPBF8PS rTt,mTt,vTt" Encoding:"vex m:5 p:0 l:0 w:0 0xFD /r:reg"/"" + { + .Instruction = ND_INS_TDPBF8PS, + .Category = ND_CAT_AMX, + .IsaSet = ND_SET_AMXFP8, + .Mnemonic = 877, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_AMX_E4, + .FpuFlags = 0, + .EvexMode = 0, + .SimdExc = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_O64, + .CpuidFlag = ND_CFF_AMXFP8, + .Operands = + { + OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_vT, ND_OPS_t, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2618 Instruction:"TDPBHF8PS rTt,mTt,vTt" Encoding:"vex m:5 p:3 l:0 w:0 0xFD /r:reg"/"" + { + .Instruction = ND_INS_TDPBHF8PS, + .Category = ND_CAT_AMX, + .IsaSet = ND_SET_AMXFP8, + .Mnemonic = 878, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_AMX_E4, + .FpuFlags = 0, + .EvexMode = 0, + .SimdExc = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_O64, + .CpuidFlag = ND_CFF_AMXFP8, + .Operands = + { + OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_vT, ND_OPS_t, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2619 Instruction:"TDPBSSD rTt,mTt,vTt" Encoding:"vex m:2 p:3 l:0 w:0 0x5E /r:reg"/"" { .Instruction = ND_INS_TDPBSSD, .Category = ND_CAT_AMX, .IsaSet = ND_SET_AMXINT8, - .Mnemonic = 860, + .Mnemonic = 879, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -72289,6 +75677,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_AMX_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -72303,12 +75692,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2592 Instruction:"TDPBSUD rTt,mTt,vTt" Encoding:"vex m:2 p:2 l:0 w:0 0x5E /r:reg"/"" + // Pos:2620 Instruction:"TDPBSUD rTt,mTt,vTt" Encoding:"vex m:2 p:2 l:0 w:0 0x5E /r:reg"/"" { .Instruction = ND_INS_TDPBSUD, .Category = ND_CAT_AMX, .IsaSet = ND_SET_AMXINT8, - .Mnemonic = 861, + .Mnemonic = 880, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -72317,6 +75706,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_AMX_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -72331,12 +75721,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2593 Instruction:"TDPBUSD rTt,mTt,vTt" Encoding:"vex m:2 p:1 l:0 w:0 0x5E /r:reg"/"" + // Pos:2621 Instruction:"TDPBUSD rTt,mTt,vTt" Encoding:"vex m:2 p:1 l:0 w:0 0x5E /r:reg"/"" { .Instruction = ND_INS_TDPBUSD, .Category = ND_CAT_AMX, .IsaSet = ND_SET_AMXINT8, - .Mnemonic = 862, + .Mnemonic = 881, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -72345,6 +75735,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_AMX_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -72359,12 +75750,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2594 Instruction:"TDPBUUD rTt,mTt,vTt" Encoding:"vex m:2 p:0 l:0 w:0 0x5E /r:reg"/"" + // Pos:2622 Instruction:"TDPBUUD rTt,mTt,vTt" Encoding:"vex m:2 p:0 l:0 w:0 0x5E /r:reg"/"" { .Instruction = ND_INS_TDPBUUD, .Category = ND_CAT_AMX, .IsaSet = ND_SET_AMXINT8, - .Mnemonic = 863, + .Mnemonic = 882, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -72373,6 +75764,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_AMX_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -72387,12 +75779,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2595 Instruction:"TDPFP16PS rTt,mTt,vTt" Encoding:"vex m:2 p:3 l:0 w:0 0x5C /r:reg"/"" + // Pos:2623 Instruction:"TDPFP16PS rTt,mTt,vTt" Encoding:"vex m:2 p:3 l:0 w:0 0x5C /r:reg"/"" { .Instruction = ND_INS_TDPFP16PS, .Category = ND_CAT_AMX, .IsaSet = ND_SET_AMXFP16, - .Mnemonic = 864, + .Mnemonic = 883, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -72401,6 +75793,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_AMX_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -72415,12 +75808,70 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2596 Instruction:"TEST Eb,Gb" Encoding:"0x84 /r"/"MR" + // Pos:2624 Instruction:"TDPHBF8PS rTt,mTt,vTt" Encoding:"vex m:5 p:2 l:0 w:0 0xFD /r:reg"/"" + { + .Instruction = ND_INS_TDPHBF8PS, + .Category = ND_CAT_AMX, + .IsaSet = ND_SET_AMXFP8, + .Mnemonic = 884, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_AMX_E4, + .FpuFlags = 0, + .EvexMode = 0, + .SimdExc = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_O64, + .CpuidFlag = ND_CFF_AMXFP8, + .Operands = + { + OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_vT, ND_OPS_t, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2625 Instruction:"TDPHF8PS rTt,mTt,vTt" Encoding:"vex m:5 p:1 l:0 w:0 0xFD /r:reg"/"" + { + .Instruction = ND_INS_TDPHF8PS, + .Category = ND_CAT_AMX, + .IsaSet = ND_SET_AMXFP8, + .Mnemonic = 885, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_AMX_E4, + .FpuFlags = 0, + .EvexMode = 0, + .SimdExc = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_O64, + .CpuidFlag = ND_CFF_AMXFP8, + .Operands = + { + OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_vT, ND_OPS_t, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2626 Instruction:"TEST Eb,Gb" Encoding:"0x84 /r"/"MR" { .Instruction = ND_INS_TEST, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_I86, - .Mnemonic = 865, + .Mnemonic = 886, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -72429,6 +75880,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -72443,12 +75895,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2597 Instruction:"TEST Ev,Gv" Encoding:"0x85 /r"/"MR" + // Pos:2627 Instruction:"TEST Ev,Gv" Encoding:"0x85 /r"/"MR" { .Instruction = ND_INS_TEST, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_I86, - .Mnemonic = 865, + .Mnemonic = 886, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -72457,6 +75909,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -72471,12 +75924,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2598 Instruction:"TEST AL,Ib" Encoding:"0xA8 ib"/"I" + // Pos:2628 Instruction:"TEST AL,Ib" Encoding:"0xA8 ib"/"I" { .Instruction = ND_INS_TEST, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_I86, - .Mnemonic = 865, + .Mnemonic = 886, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -72485,6 +75938,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -72499,12 +75953,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2599 Instruction:"TEST rAX,Iz" Encoding:"0xA9 iz"/"I" + // Pos:2629 Instruction:"TEST rAX,Iz" Encoding:"0xA9 iz"/"I" { .Instruction = ND_INS_TEST, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_I86, - .Mnemonic = 865, + .Mnemonic = 886, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -72513,6 +75967,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -72527,12 +75982,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2600 Instruction:"TEST Eb,Ib" Encoding:"0xF6 /0 ib"/"MI" + // Pos:2630 Instruction:"TEST Eb,Ib" Encoding:"0xF6 /0 ib"/"MI" { .Instruction = ND_INS_TEST, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_I86, - .Mnemonic = 865, + .Mnemonic = 886, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -72541,6 +75996,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -72555,12 +76011,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2601 Instruction:"TEST Eb,Ib" Encoding:"0xF6 /1 ib"/"MI" + // Pos:2631 Instruction:"TEST Eb,Ib" Encoding:"0xF6 /1 ib"/"MI" { .Instruction = ND_INS_TEST, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_I86, - .Mnemonic = 865, + .Mnemonic = 886, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -72569,6 +76025,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -72583,12 +76040,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2602 Instruction:"TEST Ev,Iz" Encoding:"0xF7 /0 iz"/"MI" + // Pos:2632 Instruction:"TEST Ev,Iz" Encoding:"0xF7 /0 iz"/"MI" { .Instruction = ND_INS_TEST, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_I86, - .Mnemonic = 865, + .Mnemonic = 886, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -72597,6 +76054,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -72611,12 +76069,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2603 Instruction:"TEST Ev,Iz" Encoding:"0xF7 /1 iz"/"MI" + // Pos:2633 Instruction:"TEST Ev,Iz" Encoding:"0xF7 /1 iz"/"MI" { .Instruction = ND_INS_TEST, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_I86, - .Mnemonic = 865, + .Mnemonic = 886, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -72625,6 +76083,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -72639,12 +76098,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2604 Instruction:"TESTUI" Encoding:"0xF3 0x0F 0x01 /0xED"/"" + // Pos:2634 Instruction:"TESTUI" Encoding:"0xF3 0x0F 0x01 /0xED"/"" { .Instruction = ND_INS_TESTUI, .Category = ND_CAT_UINTR, .IsaSet = ND_SET_UINTR, - .Mnemonic = 866, + .Mnemonic = 887, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -72653,6 +76112,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF, .SetFlags = 0, @@ -72666,12 +76126,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2605 Instruction:"TILELOADD rTt,Mt" Encoding:"evex m:2 p:3 l:0 nf:0 w:0 0x4B /r:mem rm:4 sibmem"/"M" + // Pos:2635 Instruction:"TILELOADD rTt,Mt" Encoding:"evex m:2 p:3 l:0 nf:0 w:0 0x4B /r:mem rm:4 sibmem"/"M" { .Instruction = ND_INS_TILELOADD, .Category = ND_CAT_AMX, .IsaSet = ND_SET_APX_F, - .Mnemonic = 867, + .Mnemonic = 888, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -72680,6 +76140,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_AMX_EVEX_E3, .FpuFlags = 0, .EvexMode = ND_EVEXM_VEX, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -72693,12 +76154,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2606 Instruction:"TILELOADD rTt,Mt" Encoding:"vex m:2 p:3 l:0 w:0 0x4B /r:mem sibmem"/"M" + // Pos:2636 Instruction:"TILELOADD rTt,Mt" Encoding:"vex m:2 p:3 l:0 w:0 0x4B /r:mem sibmem"/"M" { .Instruction = ND_INS_TILELOADD, .Category = ND_CAT_AMX, .IsaSet = ND_SET_AMXTILE, - .Mnemonic = 867, + .Mnemonic = 888, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -72707,6 +76168,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_AMX_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -72720,12 +76182,68 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2607 Instruction:"TILELOADDT1 rTt,Mt" Encoding:"evex m:2 p:1 l:0 nf:0 w:0 0x4B /r:mem rm:4 sibmem"/"M" + // Pos:2637 Instruction:"TILELOADDRS rTt,Mt" Encoding:"vex m:2 p:3 l:0 w:0 0x4A /r:mem sibmem"/"M" + { + .Instruction = ND_INS_TILELOADDRS, + .Category = ND_CAT_AMX, + .IsaSet = ND_SET_AMXMOVRS, + .Mnemonic = 889, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_AMX_E3, + .FpuFlags = 0, + .EvexMode = 0, + .SimdExc = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_SIBMEM|ND_FLAG_NOV|ND_FLAG_O64, + .CpuidFlag = ND_CFF_AMXMOVRS, + .Operands = + { + OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_M, ND_OPS_t, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2638 Instruction:"TILELOADDRST1 rTt,Mt" Encoding:"vex m:2 p:1 l:0 w:0 0x4A /r:mem sibmem"/"M" + { + .Instruction = ND_INS_TILELOADDRST1, + .Category = ND_CAT_AMX, + .IsaSet = ND_SET_AMXMOVRS, + .Mnemonic = 890, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_AMX_E3, + .FpuFlags = 0, + .EvexMode = 0, + .SimdExc = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_SIBMEM|ND_FLAG_NOV|ND_FLAG_O64, + .CpuidFlag = ND_CFF_AMXMOVRS, + .Operands = + { + OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_M, ND_OPS_t, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2639 Instruction:"TILELOADDT1 rTt,Mt" Encoding:"evex m:2 p:1 l:0 nf:0 w:0 0x4B /r:mem rm:4 sibmem"/"M" { .Instruction = ND_INS_TILELOADDT1, .Category = ND_CAT_AMX, .IsaSet = ND_SET_APX_F, - .Mnemonic = 868, + .Mnemonic = 891, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -72734,6 +76252,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_AMX_EVEX_E3, .FpuFlags = 0, .EvexMode = ND_EVEXM_VEX, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -72747,12 +76266,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2608 Instruction:"TILELOADDT1 rTt,Mt" Encoding:"vex m:2 p:1 l:0 w:0 0x4B /r:mem sibmem"/"M" + // Pos:2640 Instruction:"TILELOADDT1 rTt,Mt" Encoding:"vex m:2 p:1 l:0 w:0 0x4B /r:mem sibmem"/"M" { .Instruction = ND_INS_TILELOADDT1, .Category = ND_CAT_AMX, .IsaSet = ND_SET_AMXTILE, - .Mnemonic = 868, + .Mnemonic = 891, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -72761,6 +76280,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_AMX_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -72774,12 +76294,70 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2609 Instruction:"TILERELEASE" Encoding:"vex m:2 p:0 l:0 w:0 0x49 /0xC0"/"" + // Pos:2641 Instruction:"TILEMOVROW Voq,mTt,Bd" Encoding:"evex m:2 p:1 l:2 w:0 0x4A /r:reg"/"RV" + { + .Instruction = ND_INS_TILEMOVROW, + .Category = ND_CAT_AMX, + .IsaSet = ND_SET_AMXAVX512, + .Mnemonic = 892, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_AMX_EVEX_E8, + .FpuFlags = 0, + .EvexMode = 0, + .SimdExc = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AMXAVX512, + .Operands = + { + OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_B, ND_OPS_d, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2642 Instruction:"TILEMOVROW Voq,mTt,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x07 /r:reg ib"/"RI" + { + .Instruction = ND_INS_TILEMOVROW, + .Category = ND_CAT_AMX, + .IsaSet = ND_SET_AMXAVX512, + .Mnemonic = 892, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_AMX_EVEX_E7, + .FpuFlags = 0, + .EvexMode = 0, + .SimdExc = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AMXAVX512, + .Operands = + { + OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2643 Instruction:"TILERELEASE" Encoding:"vex m:2 p:0 l:0 w:0 0x49 /0xC0"/"" { .Instruction = ND_INS_TILERELEASE, .Category = ND_CAT_AMX, .IsaSet = ND_SET_AMXTILE, - .Mnemonic = 869, + .Mnemonic = 893, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -72788,6 +76366,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_AMX_E6, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -72800,12 +76379,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2610 Instruction:"TILESTORED Mt,rTt" Encoding:"evex m:2 p:2 l:0 nf:0 w:0 0x4B /r:mem rm:4 sibmem"/"M" + // Pos:2644 Instruction:"TILESTORED Mt,rTt" Encoding:"evex m:2 p:2 l:0 nf:0 w:0 0x4B /r:mem rm:4 sibmem"/"M" { .Instruction = ND_INS_TILESTORED, .Category = ND_CAT_AMX, .IsaSet = ND_SET_APX_F, - .Mnemonic = 870, + .Mnemonic = 894, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -72814,6 +76393,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_AMX_EVEX_E3, .FpuFlags = 0, .EvexMode = ND_EVEXM_VEX, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -72827,12 +76407,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2611 Instruction:"TILESTORED Mt,rTt" Encoding:"vex m:2 p:2 l:0 w:0 0x4B /r:mem sibmem"/"M" + // Pos:2645 Instruction:"TILESTORED Mt,rTt" Encoding:"vex m:2 p:2 l:0 w:0 0x4B /r:mem sibmem"/"M" { .Instruction = ND_INS_TILESTORED, .Category = ND_CAT_AMX, .IsaSet = ND_SET_AMXTILE, - .Mnemonic = 870, + .Mnemonic = 894, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -72841,6 +76421,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_AMX_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -72854,12 +76435,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2612 Instruction:"TILEZERO rTt" Encoding:"vex m:2 p:3 l:0 w:0 0x49 /r:reg rm:0"/"" + // Pos:2646 Instruction:"TILEZERO rTt" Encoding:"vex m:2 p:3 l:0 w:0 0x49 /r:reg rm:0"/"" { .Instruction = ND_INS_TILEZERO, .Category = ND_CAT_AMX, .IsaSet = ND_SET_AMXTILE, - .Mnemonic = 871, + .Mnemonic = 895, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -72868,6 +76449,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_AMX_E5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -72880,12 +76462,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2613 Instruction:"TLBSYNC" Encoding:"NP 0x0F 0x01 /0xFF"/"" + // Pos:2647 Instruction:"TLBSYNC" Encoding:"NP 0x0F 0x01 /0xFF"/"" { .Instruction = ND_INS_TLBSYNC, .Category = ND_CAT_SYSTEM, .IsaSet = ND_SET_INVLPGB, - .Mnemonic = 872, + .Mnemonic = 896, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -72894,6 +76476,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -72906,12 +76489,41 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2614 Instruction:"TPAUSE Ry" Encoding:"0x66 0x0F 0xAE /6:reg"/"M" + // Pos:2648 Instruction:"TMMULTF32PS rTt,mTt,vTt" Encoding:"vex m:2 p:1 l:0 w:0 0x48 /r:reg"/"" + { + .Instruction = ND_INS_TMMULTF32PS, + .Category = ND_CAT_AMX, + .IsaSet = ND_SET_AMXTF32, + .Mnemonic = 897, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_AMX_E4, + .FpuFlags = 0, + .EvexMode = 0, + .SimdExc = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_O64, + .CpuidFlag = ND_CFF_AMXTF32, + .Operands = + { + OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_vT, ND_OPS_t, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2649 Instruction:"TPAUSE Ry" Encoding:"0x66 0x0F 0xAE /6:reg"/"M" { .Instruction = ND_INS_TPAUSE, .Category = ND_CAT_WAITPKG, .IsaSet = ND_SET_WAITPKG, - .Mnemonic = 873, + .Mnemonic = 898, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -72920,6 +76532,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF, .SetFlags = 0, @@ -72935,12 +76548,185 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2615 Instruction:"TZCNT Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF4 /r"/"RM" + // Pos:2650 Instruction:"TTCMMIMFP16PS rTt,mTt,vTt" Encoding:"vex m:2 p:3 l:0 w:0 0x6B /r:reg"/"" + { + .Instruction = ND_INS_TTCMMIMFP16PS, + .Category = ND_CAT_AMX, + .IsaSet = ND_SET_AMXTRANSPOSE, + .Mnemonic = 899, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_AMX_E10, + .FpuFlags = 0, + .EvexMode = 0, + .SimdExc = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_O64, + .CpuidFlag = ND_CFF_AMXTRANSPOSE, + .Operands = + { + OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_vT, ND_OPS_t, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2651 Instruction:"TTCMMRLFP16PS rTt,mTt,vTt" Encoding:"vex m:2 p:2 l:0 w:0 0x6B /r:reg"/"" + { + .Instruction = ND_INS_TTCMMRLFP16PS, + .Category = ND_CAT_AMX, + .IsaSet = ND_SET_AMXTRANSPOSE, + .Mnemonic = 900, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_AMX_E10, + .FpuFlags = 0, + .EvexMode = 0, + .SimdExc = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_O64, + .CpuidFlag = ND_CFF_AMXTRANSPOSE, + .Operands = + { + OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_vT, ND_OPS_t, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2652 Instruction:"TTDPBF16PS rTt,mTt,vTt" Encoding:"vex m:2 p:2 l:0 w:0 0x6C /r:reg"/"" + { + .Instruction = ND_INS_TTDPBF16PS, + .Category = ND_CAT_AMX, + .IsaSet = ND_SET_AMXTRANSPOSE, + .Mnemonic = 901, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_AMX_E10, + .FpuFlags = 0, + .EvexMode = 0, + .SimdExc = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_O64, + .CpuidFlag = ND_CFF_AMXTRANSPOSE, + .Operands = + { + OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_vT, ND_OPS_t, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2653 Instruction:"TTDPFP16PS rTt,mTt,vTt" Encoding:"vex m:2 p:3 l:0 w:0 0x6C /r:reg"/"" + { + .Instruction = ND_INS_TTDPFP16PS, + .Category = ND_CAT_AMX, + .IsaSet = ND_SET_AMXTRANSPOSE, + .Mnemonic = 902, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_AMX_E10, + .FpuFlags = 0, + .EvexMode = 0, + .SimdExc = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_O64, + .CpuidFlag = ND_CFF_AMXTRANSPOSE, + .Operands = + { + OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_vT, ND_OPS_t, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2654 Instruction:"TTMMULTF32PS rTt,mTt,vTt" Encoding:"vex m:2 p:0 l:0 w:0 0x48 /r:reg"/"" + { + .Instruction = ND_INS_TTMMULTF32PS, + .Category = ND_CAT_AMX, + .IsaSet = ND_SET_AMXTRANSPOSE, + .Mnemonic = 903, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_AMX_E10, + .FpuFlags = 0, + .EvexMode = 0, + .SimdExc = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_O64, + .CpuidFlag = ND_CFF_AMXTRANSPOSE, + .Operands = + { + OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_vT, ND_OPS_t, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2655 Instruction:"TTRANSPOSED rTt,mTt" Encoding:"vex m:2 p:2 l:0 w:0 0x5F /r:reg"/"" + { + .Instruction = ND_INS_TTRANSPOSED, + .Category = ND_CAT_AMX, + .IsaSet = ND_SET_AMXTRANSPOSE, + .Mnemonic = 904, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_AMX_E9, + .FpuFlags = 0, + .EvexMode = 0, + .SimdExc = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_O64, + .CpuidFlag = ND_CFF_AMXTRANSPOSE, + .Operands = + { + OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2656 Instruction:"TZCNT Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF4 /r"/"RM" { .Instruction = ND_INS_TZCNT, .Category = ND_CAT_BMI1, .IsaSet = ND_SET_APX_F, - .Mnemonic = 874, + .Mnemonic = 905, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -72949,6 +76735,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, @@ -72963,12 +76750,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2616 Instruction:"TZCNT Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xF4 /r"/"RM" + // Pos:2657 Instruction:"TZCNT Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xF4 /r"/"RM" { .Instruction = ND_INS_TZCNT, .Category = ND_CAT_BMI1, .IsaSet = ND_SET_APX_F, - .Mnemonic = 874, + .Mnemonic = 905, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -72977,6 +76764,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, @@ -72991,12 +76779,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2617 Instruction:"TZCNT Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xF4 /r"/"RM" + // Pos:2658 Instruction:"TZCNT Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xF4 /r"/"RM" { .Instruction = ND_INS_TZCNT, .Category = ND_CAT_BMI1, .IsaSet = ND_SET_APX_F, - .Mnemonic = 874, + .Mnemonic = 905, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -73005,6 +76793,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -73018,12 +76807,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2618 Instruction:"TZCNT Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xF4 /r"/"RM" + // Pos:2659 Instruction:"TZCNT Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xF4 /r"/"RM" { .Instruction = ND_INS_TZCNT, .Category = ND_CAT_BMI1, .IsaSet = ND_SET_APX_F, - .Mnemonic = 874, + .Mnemonic = 905, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -73032,6 +76821,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -73045,12 +76835,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2619 Instruction:"TZCNT Gv,Ev" Encoding:"repz 0x0F 0xBC /r"/"RM" + // Pos:2660 Instruction:"TZCNT Gv,Ev" Encoding:"repz 0x0F 0xBC /r"/"RM" { .Instruction = ND_INS_TZCNT, .Category = ND_CAT_BMI1, .IsaSet = ND_SET_BMI1, - .Mnemonic = 874, + .Mnemonic = 905, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -73059,6 +76849,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, @@ -73073,12 +76864,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2620 Instruction:"TZMSK By,Ey" Encoding:"xop m:9 0x01 /4"/"VM" + // Pos:2661 Instruction:"TZMSK By,Ey" Encoding:"xop m:9 0x01 /4"/"VM" { .Instruction = ND_INS_TZMSK, .Category = ND_CAT_BITBYTE, .IsaSet = ND_SET_TBM, - .Mnemonic = 875, + .Mnemonic = 906, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -73087,6 +76878,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -73100,12 +76892,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2621 Instruction:"UCOMISD Vsd,Wsd" Encoding:"0x66 0x0F 0x2E /r"/"RM" + // Pos:2662 Instruction:"UCOMISD Vsd,Wsd" Encoding:"0x66 0x0F 0x2E /r"/"RM" { .Instruction = ND_INS_UCOMISD, .Category = ND_CAT_SSE2, .IsaSet = ND_SET_SSE2, - .Mnemonic = 876, + .Mnemonic = 907, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -73114,6 +76906,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, .SetFlags = 0, @@ -73128,20 +76921,21 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2622 Instruction:"UCOMISS Vss,Wss" Encoding:"NP 0x0F 0x2E /r"/"RM" + // Pos:2663 Instruction:"UCOMISS Vss,Wss" Encoding:"NP 0x0F 0x2E /r"/"RM" { .Instruction = ND_INS_UCOMISS, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE, - .Mnemonic = 877, + .Mnemonic = 908, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, .OpsCount = ND_OPS_CNT(2, 1), .TupleType = 0, - .ExcType = 0, + .ExcType = ND_EXT_3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, .SetFlags = 0, @@ -73156,12 +76950,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2623 Instruction:"UD0 Gd,Ed" Encoding:"0x0F 0xFF /r"/"RM" + // Pos:2664 Instruction:"UD0 Gd,Ed" Encoding:"0x0F 0xFF /r"/"RM" { .Instruction = ND_INS_UD0, .Category = ND_CAT_UD, .IsaSet = ND_SET_UD, - .Mnemonic = 878, + .Mnemonic = 909, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -73170,6 +76964,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -73183,12 +76978,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2624 Instruction:"UD1 Gd,Ed" Encoding:"0x0F 0xB9 /r"/"RM" + // Pos:2665 Instruction:"UD1 Gd,Ed" Encoding:"0x0F 0xB9 /r"/"RM" { .Instruction = ND_INS_UD1, .Category = ND_CAT_UD, .IsaSet = ND_SET_UD, - .Mnemonic = 879, + .Mnemonic = 910, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -73197,6 +76992,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -73210,12 +77006,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2625 Instruction:"UD2" Encoding:"0x0F 0x0B"/"" + // Pos:2666 Instruction:"UD2" Encoding:"0x0F 0x0B"/"" { .Instruction = ND_INS_UD2, .Category = ND_CAT_MISC, .IsaSet = ND_SET_PPRO, - .Mnemonic = 880, + .Mnemonic = 911, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -73224,6 +77020,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -73236,12 +77033,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2626 Instruction:"UIRET" Encoding:"0xF3 0x0F 0x01 /0xEC"/"" + // Pos:2667 Instruction:"UIRET" Encoding:"0xF3 0x0F 0x01 /0xEC"/"" { .Instruction = ND_INS_UIRET, .Category = ND_CAT_RET, .IsaSet = ND_SET_UINTR, - .Mnemonic = 881, + .Mnemonic = 912, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -73250,6 +77047,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -73267,12 +77065,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2627 Instruction:"UMONITOR mMb" Encoding:"0xF3 0x0F 0xAE /6:reg"/"M" + // Pos:2668 Instruction:"UMONITOR mMb" Encoding:"0xF3 0x0F 0xAE /6:reg"/"M" { .Instruction = ND_INS_UMONITOR, .Category = ND_CAT_WAITPKG, .IsaSet = ND_SET_WAITPKG, - .Mnemonic = 882, + .Mnemonic = 913, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -73281,6 +77079,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF, .SetFlags = 0, @@ -73294,12 +77093,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2628 Instruction:"UMWAIT Ry" Encoding:"0xF2 0x0F 0xAE /6:reg"/"M" + // Pos:2669 Instruction:"UMWAIT Ry" Encoding:"0xF2 0x0F 0xAE /6:reg"/"M" { .Instruction = ND_INS_UMWAIT, .Category = ND_CAT_WAITPKG, .IsaSet = ND_SET_WAITPKG, - .Mnemonic = 883, + .Mnemonic = 914, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -73308,6 +77107,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -73322,12 +77122,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2629 Instruction:"UNPCKHPD Vx,Wx" Encoding:"0x66 0x0F 0x15 /r"/"RM" + // Pos:2670 Instruction:"UNPCKHPD Vx,Wx" Encoding:"0x66 0x0F 0x15 /r"/"RM" { .Instruction = ND_INS_UNPCKHPD, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE2, - .Mnemonic = 884, + .Mnemonic = 915, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -73336,6 +77136,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -73349,12 +77150,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2630 Instruction:"UNPCKHPS Vx,Wx" Encoding:"NP 0x0F 0x15 /r"/"RM" + // Pos:2671 Instruction:"UNPCKHPS Vx,Wx" Encoding:"NP 0x0F 0x15 /r"/"RM" { .Instruction = ND_INS_UNPCKHPS, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE, - .Mnemonic = 885, + .Mnemonic = 916, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -73363,6 +77164,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -73376,12 +77178,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2631 Instruction:"UNPCKLPD Vx,Wx" Encoding:"0x66 0x0F 0x14 /r"/"RM" + // Pos:2672 Instruction:"UNPCKLPD Vx,Wx" Encoding:"0x66 0x0F 0x14 /r"/"RM" { .Instruction = ND_INS_UNPCKLPD, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE2, - .Mnemonic = 886, + .Mnemonic = 917, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -73390,6 +77192,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -73403,12 +77206,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2632 Instruction:"UNPCKLPS Vx,Wx" Encoding:"NP 0x0F 0x14 /r"/"RM" + // Pos:2673 Instruction:"UNPCKLPS Vx,Wx" Encoding:"NP 0x0F 0x14 /r"/"RM" { .Instruction = ND_INS_UNPCKLPS, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE, - .Mnemonic = 887, + .Mnemonic = 918, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -73417,6 +77220,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -73430,12 +77234,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2633 Instruction:"URDMSR Eq,Gq" Encoding:"evex m:4 l:0 nd:0 nf:0 p:3 w:0 0xF8 /r:reg"/"MR" + // Pos:2674 Instruction:"URDMSR Eq,Gq" Encoding:"evex m:4 l:0 nd:0 nf:0 p:3 w:0 0xF8 /r:reg"/"MR" { .Instruction = ND_INS_URDMSR, .Category = ND_CAT_USER_MSR, .IsaSet = ND_SET_APX_F, - .Mnemonic = 888, + .Mnemonic = 919, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -73444,6 +77248,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_USER_MSR, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -73457,12 +77262,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2634 Instruction:"URDMSR Rq,Id" Encoding:"evex m:7 nf:0 p:3 l:0 w:0 0xF8 /0:reg id"/"MI" + // Pos:2675 Instruction:"URDMSR Rq,Id" Encoding:"evex m:7 nf:0 p:3 l:0 w:0 0xF8 /0:reg id"/"MI" { .Instruction = ND_INS_URDMSR, .Category = ND_CAT_USER_MSR, .IsaSet = ND_SET_APX_F, - .Mnemonic = 888, + .Mnemonic = 919, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -73471,6 +77276,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = ND_EVEXM_VEX, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -73485,12 +77291,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2635 Instruction:"URDMSR Rq,Gq" Encoding:"0xF2 0x0F 0x38 0xF8 /r:reg"/"MR" + // Pos:2676 Instruction:"URDMSR Rq,Gq" Encoding:"0xF2 0x0F 0x38 0xF8 /r:reg"/"MR" { .Instruction = ND_INS_URDMSR, .Category = ND_CAT_USER_MSR, .IsaSet = ND_SET_USER_MSR, - .Mnemonic = 888, + .Mnemonic = 919, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -73499,6 +77305,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -73513,12 +77320,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2636 Instruction:"URDMSR Rq,Id" Encoding:"vex m:7 p:3 l:0 w:0 0xF8 /0:reg id"/"MI" + // Pos:2677 Instruction:"URDMSR Rq,Id" Encoding:"vex m:7 p:3 l:0 w:0 0xF8 /0:reg id"/"MI" { .Instruction = ND_INS_URDMSR, .Category = ND_CAT_USER_MSR, .IsaSet = ND_SET_USER_MSR, - .Mnemonic = 888, + .Mnemonic = 919, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -73527,6 +77334,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -73541,12 +77349,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2637 Instruction:"UWRMSR Gq,Eq" Encoding:"evex m:4 l:0 nd:0 nf:0 p:2 w:0 0xF8 /r:reg"/"RM" + // Pos:2678 Instruction:"UWRMSR Gq,Eq" Encoding:"evex m:4 l:0 nd:0 nf:0 p:2 w:0 0xF8 /r:reg"/"RM" { .Instruction = ND_INS_UWRMSR, .Category = ND_CAT_USER_MSR, .IsaSet = ND_SET_APX_F, - .Mnemonic = 889, + .Mnemonic = 920, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -73555,6 +77363,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_USER_MSR, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -73568,12 +77377,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2638 Instruction:"UWRMSR Id,Rq" Encoding:"evex m:7 nf:0 p:2 l:0 w:0 0xF8 /0:reg id"/"IM" + // Pos:2679 Instruction:"UWRMSR Id,Rq" Encoding:"evex m:7 nf:0 p:2 l:0 w:0 0xF8 /0:reg id"/"IM" { .Instruction = ND_INS_UWRMSR, .Category = ND_CAT_USER_MSR, .IsaSet = ND_SET_APX_F, - .Mnemonic = 889, + .Mnemonic = 920, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -73582,6 +77391,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = ND_EVEXM_VEX, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -73596,12 +77406,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2639 Instruction:"UWRMSR Gq,Rq" Encoding:"0xF3 0x0F 0x38 0xF8 /r:reg"/"RM" + // Pos:2680 Instruction:"UWRMSR Gq,Rq" Encoding:"0xF3 0x0F 0x38 0xF8 /r:reg"/"RM" { .Instruction = ND_INS_UWRMSR, .Category = ND_CAT_USER_MSR, .IsaSet = ND_SET_USER_MSR, - .Mnemonic = 889, + .Mnemonic = 920, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -73610,6 +77420,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -73624,12 +77435,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2640 Instruction:"UWRMSR Id,Rq" Encoding:"vex m:7 p:2 l:0 w:0 0xF8 /0:reg id"/"IM" + // Pos:2681 Instruction:"UWRMSR Id,Rq" Encoding:"vex m:7 p:2 l:0 w:0 0xF8 /0:reg id"/"IM" { .Instruction = ND_INS_UWRMSR, .Category = ND_CAT_USER_MSR, .IsaSet = ND_SET_USER_MSR, - .Mnemonic = 889, + .Mnemonic = 920, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -73638,6 +77449,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -73652,12 +77464,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2641 Instruction:"V4FMADDPS Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0x9A /r:mem"/"RAVM" + // Pos:2682 Instruction:"V4FMADDPS Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0x9A /r:mem"/"RAVM" { .Instruction = ND_INS_V4FMADDPS, .Category = ND_CAT_VFMAPS, .IsaSet = ND_SET_AVX5124FMAPS, - .Mnemonic = 890, + .Mnemonic = 921, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -73666,6 +77478,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -73681,12 +77494,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2642 Instruction:"V4FMADDSS Vdq{K}{z},aKq,Hdq+3,Mdq" Encoding:"evex m:2 p:3 l:i w:0 0x9B /r:mem"/"RAVM" + // Pos:2683 Instruction:"V4FMADDSS Vdq{K}{z},aKq,Hdq+3,Mdq" Encoding:"evex m:2 p:3 l:i w:0 0x9B /r:mem"/"RAVM" { .Instruction = ND_INS_V4FMADDSS, .Category = ND_CAT_VFMAPS, .IsaSet = ND_SET_AVX5124FMAPS, - .Mnemonic = 891, + .Mnemonic = 922, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -73695,6 +77508,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -73710,12 +77524,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2643 Instruction:"V4FNMADDPS Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0xAA /r:mem"/"RAVM" + // Pos:2684 Instruction:"V4FNMADDPS Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0xAA /r:mem"/"RAVM" { .Instruction = ND_INS_V4FNMADDPS, .Category = ND_CAT_VFMAPS, .IsaSet = ND_SET_AVX5124FMAPS, - .Mnemonic = 892, + .Mnemonic = 923, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -73724,6 +77538,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -73739,12 +77554,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2644 Instruction:"V4FNMADDSS Vdq{K}{z},aKq,Hdq+3,Mdq" Encoding:"evex m:2 p:3 l:i w:0 0xAB /r:mem"/"RAVM" + // Pos:2685 Instruction:"V4FNMADDSS Vdq{K}{z},aKq,Hdq+3,Mdq" Encoding:"evex m:2 p:3 l:i w:0 0xAB /r:mem"/"RAVM" { .Instruction = ND_INS_V4FNMADDSS, .Category = ND_CAT_VFMAPS, .IsaSet = ND_SET_AVX5124FMAPS, - .Mnemonic = 893, + .Mnemonic = 924, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -73753,6 +77568,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -73768,12 +77584,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2645 Instruction:"VADDNEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:5 p:1 l:x w:0 0x58 /r"/"RAVM" + // Pos:2686 Instruction:"VADDNEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:5 p:1 l:x w:0 0x58 /r"/"RAVM" { .Instruction = ND_INS_VADDNEPBF16, .Category = ND_CAT_AVX10BF16, .IsaSet = ND_SET_AVX102, - .Mnemonic = 894, + .Mnemonic = 925, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -73782,6 +77598,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -73797,12 +77614,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2646 Instruction:"VADDPD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x58 /r"/"RAVM" + // Pos:2687 Instruction:"VADDPD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x58 /r"/"RAVM" { .Instruction = ND_INS_VADDPD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 895, + .Mnemonic = 926, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -73811,6 +77628,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -73826,12 +77644,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2647 Instruction:"VADDPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x58 /r"/"RVM" + // Pos:2688 Instruction:"VADDPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x58 /r"/"RVM" { .Instruction = ND_INS_VADDPD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 895, + .Mnemonic = 926, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -73840,6 +77658,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -73854,12 +77673,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2648 Instruction:"VADDPH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x58 /r"/"RAVM" + // Pos:2689 Instruction:"VADDPH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x58 /r"/"RAVM" { .Instruction = ND_INS_VADDPH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 896, + .Mnemonic = 927, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -73868,6 +77687,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -73883,12 +77703,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2649 Instruction:"VADDPS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x58 /r"/"RAVM" + // Pos:2690 Instruction:"VADDPS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x58 /r"/"RAVM" { .Instruction = ND_INS_VADDPS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 897, + .Mnemonic = 928, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -73897,6 +77717,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -73912,12 +77733,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2650 Instruction:"VADDPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x58 /r"/"RVM" + // Pos:2691 Instruction:"VADDPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x58 /r"/"RVM" { .Instruction = ND_INS_VADDPS, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 897, + .Mnemonic = 928, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -73926,6 +77747,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -73940,12 +77762,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2651 Instruction:"VADDSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x58 /r"/"RAVM" + // Pos:2692 Instruction:"VADDSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x58 /r"/"RAVM" { .Instruction = ND_INS_VADDSD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 898, + .Mnemonic = 929, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -73954,6 +77776,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -73969,12 +77792,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2652 Instruction:"VADDSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x58 /r"/"RVM" + // Pos:2693 Instruction:"VADDSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x58 /r"/"RVM" { .Instruction = ND_INS_VADDSD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 898, + .Mnemonic = 929, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -73983,6 +77806,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -73997,12 +77821,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2653 Instruction:"VADDSH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:0 0x58 /r"/"RAVM" + // Pos:2694 Instruction:"VADDSH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:0 0x58 /r"/"RAVM" { .Instruction = ND_INS_VADDSH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 899, + .Mnemonic = 930, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -74011,6 +77835,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -74026,12 +77851,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2654 Instruction:"VADDSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x58 /r"/"RAVM" + // Pos:2695 Instruction:"VADDSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x58 /r"/"RAVM" { .Instruction = ND_INS_VADDSS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 900, + .Mnemonic = 931, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -74040,6 +77865,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -74055,12 +77881,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2655 Instruction:"VADDSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x58 /r"/"RVM" + // Pos:2696 Instruction:"VADDSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x58 /r"/"RVM" { .Instruction = ND_INS_VADDSS, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 900, + .Mnemonic = 931, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -74069,6 +77895,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -74083,12 +77910,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2656 Instruction:"VADDSUBPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0xD0 /r"/"RVM" + // Pos:2697 Instruction:"VADDSUBPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0xD0 /r"/"RVM" { .Instruction = ND_INS_VADDSUBPD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 901, + .Mnemonic = 932, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -74097,6 +77924,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -74111,12 +77939,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2657 Instruction:"VADDSUBPS Vps,Hps,Wps" Encoding:"vex m:1 p:3 l:x w:i 0xD0 /r"/"RVM" + // Pos:2698 Instruction:"VADDSUBPS Vps,Hps,Wps" Encoding:"vex m:1 p:3 l:x w:i 0xD0 /r"/"RVM" { .Instruction = ND_INS_VADDSUBPS, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 902, + .Mnemonic = 933, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -74125,6 +77953,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -74139,12 +77968,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2658 Instruction:"VAESDEC Vfv,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0xDE /r"/"RVM" + // Pos:2699 Instruction:"VAESDEC Vfv,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0xDE /r"/"RVM" { .Instruction = ND_INS_VAESDEC, .Category = ND_CAT_VAES, .IsaSet = ND_SET_VAES, - .Mnemonic = 903, + .Mnemonic = 934, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -74153,6 +77982,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -74167,12 +77997,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2659 Instruction:"VAESDEC Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDE /r"/"RVM" + // Pos:2700 Instruction:"VAESDEC Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDE /r"/"RVM" { .Instruction = ND_INS_VAESDEC, .Category = ND_CAT_AES, .IsaSet = ND_SET_AES, - .Mnemonic = 903, + .Mnemonic = 934, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -74181,6 +78011,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -74195,12 +78026,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2660 Instruction:"VAESDECLAST Vfv,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0xDF /r"/"RVM" + // Pos:2701 Instruction:"VAESDECLAST Vfv,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0xDF /r"/"RVM" { .Instruction = ND_INS_VAESDECLAST, .Category = ND_CAT_VAES, .IsaSet = ND_SET_VAES, - .Mnemonic = 904, + .Mnemonic = 935, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -74209,6 +78040,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -74223,12 +78055,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2661 Instruction:"VAESDECLAST Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDF /r"/"RVM" + // Pos:2702 Instruction:"VAESDECLAST Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDF /r"/"RVM" { .Instruction = ND_INS_VAESDECLAST, .Category = ND_CAT_AES, .IsaSet = ND_SET_AES, - .Mnemonic = 904, + .Mnemonic = 935, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -74237,6 +78069,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -74251,12 +78084,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2662 Instruction:"VAESENC Vfv,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0xDC /r"/"RVM" + // Pos:2703 Instruction:"VAESENC Vfv,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0xDC /r"/"RVM" { .Instruction = ND_INS_VAESENC, .Category = ND_CAT_VAES, .IsaSet = ND_SET_VAES, - .Mnemonic = 905, + .Mnemonic = 936, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -74265,6 +78098,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -74279,12 +78113,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2663 Instruction:"VAESENC Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDC /r"/"RVM" + // Pos:2704 Instruction:"VAESENC Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDC /r"/"RVM" { .Instruction = ND_INS_VAESENC, .Category = ND_CAT_AES, .IsaSet = ND_SET_AES, - .Mnemonic = 905, + .Mnemonic = 936, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -74293,6 +78127,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -74307,12 +78142,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2664 Instruction:"VAESENCLAST Vfv,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0xDD /r"/"RVM" + // Pos:2705 Instruction:"VAESENCLAST Vfv,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0xDD /r"/"RVM" { .Instruction = ND_INS_VAESENCLAST, .Category = ND_CAT_VAES, .IsaSet = ND_SET_VAES, - .Mnemonic = 906, + .Mnemonic = 937, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -74321,6 +78156,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -74335,12 +78171,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2665 Instruction:"VAESENCLAST Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDD /r"/"RVM" + // Pos:2706 Instruction:"VAESENCLAST Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDD /r"/"RVM" { .Instruction = ND_INS_VAESENCLAST, .Category = ND_CAT_AES, .IsaSet = ND_SET_AES, - .Mnemonic = 906, + .Mnemonic = 937, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -74349,6 +78185,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -74363,12 +78200,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2666 Instruction:"VAESIMC Vdq,Wdq" Encoding:"vex m:2 p:1 l:0 w:i 0xDB /r"/"RM" + // Pos:2707 Instruction:"VAESIMC Vdq,Wdq" Encoding:"vex m:2 p:1 l:0 w:i 0xDB /r"/"RM" { .Instruction = ND_INS_VAESIMC, .Category = ND_CAT_AES, .IsaSet = ND_SET_AES, - .Mnemonic = 907, + .Mnemonic = 938, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -74377,6 +78214,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -74390,12 +78228,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2667 Instruction:"VAESKEYGENASSIST Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0xDF /r ib"/"RMI" + // Pos:2708 Instruction:"VAESKEYGENASSIST Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0xDF /r ib"/"RMI" { .Instruction = ND_INS_VAESKEYGENASSIST, .Category = ND_CAT_AES, .IsaSet = ND_SET_AES, - .Mnemonic = 908, + .Mnemonic = 939, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -74404,6 +78242,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -74418,12 +78257,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2668 Instruction:"VALIGND Vfv{K}{z},aKq,Hfv,Wfv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x03 /r ib"/"RAVMI" + // Pos:2709 Instruction:"VALIGND Vfv{K}{z},aKq,Hfv,Wfv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x03 /r ib"/"RAVMI" { .Instruction = ND_INS_VALIGND, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 909, + .Mnemonic = 940, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -74432,6 +78271,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -74448,12 +78288,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2669 Instruction:"VALIGNQ Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x03 /r ib"/"RAVMI" + // Pos:2710 Instruction:"VALIGNQ Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x03 /r ib"/"RAVMI" { .Instruction = ND_INS_VALIGNQ, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 910, + .Mnemonic = 941, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -74462,6 +78302,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -74478,12 +78319,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2670 Instruction:"VANDNPD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0x55 /r"/"RAVM" + // Pos:2711 Instruction:"VANDNPD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0x55 /r"/"RAVM" { .Instruction = ND_INS_VANDNPD, .Category = ND_CAT_LOGICAL_FP, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 911, + .Mnemonic = 942, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -74492,6 +78333,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -74507,12 +78349,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2671 Instruction:"VANDNPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x55 /r"/"RVM" + // Pos:2712 Instruction:"VANDNPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x55 /r"/"RVM" { .Instruction = ND_INS_VANDNPD, .Category = ND_CAT_LOGICAL_FP, .IsaSet = ND_SET_AVX, - .Mnemonic = 911, + .Mnemonic = 942, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -74521,6 +78363,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -74535,12 +78378,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2672 Instruction:"VANDNPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:0 l:x w:0 0x55 /r"/"RAVM" + // Pos:2713 Instruction:"VANDNPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:0 l:x w:0 0x55 /r"/"RAVM" { .Instruction = ND_INS_VANDNPS, .Category = ND_CAT_LOGICAL_FP, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 912, + .Mnemonic = 943, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -74549,6 +78392,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -74564,12 +78408,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2673 Instruction:"VANDNPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x55 /r"/"RVM" + // Pos:2714 Instruction:"VANDNPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x55 /r"/"RVM" { .Instruction = ND_INS_VANDNPS, .Category = ND_CAT_LOGICAL_FP, .IsaSet = ND_SET_AVX, - .Mnemonic = 912, + .Mnemonic = 943, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -74578,6 +78422,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -74592,12 +78437,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2674 Instruction:"VANDPD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0x54 /r"/"RAVM" + // Pos:2715 Instruction:"VANDPD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0x54 /r"/"RAVM" { .Instruction = ND_INS_VANDPD, .Category = ND_CAT_LOGICAL_FP, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 913, + .Mnemonic = 944, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -74606,6 +78451,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -74621,12 +78467,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2675 Instruction:"VANDPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x54 /r"/"RVM" + // Pos:2716 Instruction:"VANDPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x54 /r"/"RVM" { .Instruction = ND_INS_VANDPD, .Category = ND_CAT_LOGICAL_FP, .IsaSet = ND_SET_AVX, - .Mnemonic = 913, + .Mnemonic = 944, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -74635,6 +78481,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -74649,12 +78496,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2676 Instruction:"VANDPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:0 l:x w:0 0x54 /r"/"RAVM" + // Pos:2717 Instruction:"VANDPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:0 l:x w:0 0x54 /r"/"RAVM" { .Instruction = ND_INS_VANDPS, .Category = ND_CAT_LOGICAL_FP, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 914, + .Mnemonic = 945, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -74663,6 +78510,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -74678,12 +78526,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2677 Instruction:"VANDPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x54 /r"/"RVM" + // Pos:2718 Instruction:"VANDPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x54 /r"/"RVM" { .Instruction = ND_INS_VANDPS, .Category = ND_CAT_LOGICAL_FP, .IsaSet = ND_SET_AVX, - .Mnemonic = 914, + .Mnemonic = 945, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -74692,6 +78540,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -74706,12 +78555,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2678 Instruction:"VBCSTNEBF162PS Vx,Mw" Encoding:"vex m:2 p:2 l:x w:0 0xB1 /r:mem"/"RM" + // Pos:2719 Instruction:"VBCSTNEBF162PS Vx,Mw" Encoding:"vex m:2 p:2 l:x w:0 0xB1 /r:mem"/"RM" { .Instruction = ND_INS_VBCSTNEBF162PS, .Category = ND_CAT_AVXNECONVERT, .IsaSet = ND_SET_AVXNECONVERT, - .Mnemonic = 915, + .Mnemonic = 946, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -74720,6 +78569,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -74733,12 +78583,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2679 Instruction:"VBCSTNESH2PS Vx,Mw" Encoding:"vex m:2 p:1 l:x w:0 0xB1 /r:mem"/"RM" + // Pos:2720 Instruction:"VBCSTNESH2PS Vx,Mw" Encoding:"vex m:2 p:1 l:x w:0 0xB1 /r:mem"/"RM" { .Instruction = ND_INS_VBCSTNESH2PS, .Category = ND_CAT_AVXNECONVERT, .IsaSet = ND_SET_AVXNECONVERT, - .Mnemonic = 916, + .Mnemonic = 947, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -74747,6 +78597,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -74760,12 +78611,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2680 Instruction:"VBLENDMPD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x65 /r"/"RAVM" + // Pos:2721 Instruction:"VBLENDMPD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x65 /r"/"RAVM" { .Instruction = ND_INS_VBLENDMPD, .Category = ND_CAT_BLEND, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 917, + .Mnemonic = 948, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -74774,6 +78625,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -74789,12 +78641,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2681 Instruction:"VBLENDMPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x65 /r"/"RAVM" + // Pos:2722 Instruction:"VBLENDMPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x65 /r"/"RAVM" { .Instruction = ND_INS_VBLENDMPS, .Category = ND_CAT_BLEND, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 918, + .Mnemonic = 949, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -74803,6 +78655,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -74818,12 +78671,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2682 Instruction:"VBLENDPD Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0D /r ib"/"RVMI" + // Pos:2723 Instruction:"VBLENDPD Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0D /r ib"/"RVMI" { .Instruction = ND_INS_VBLENDPD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 919, + .Mnemonic = 950, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -74832,6 +78685,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -74847,12 +78701,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2683 Instruction:"VBLENDPS Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0C /r ib"/"RVMI" + // Pos:2724 Instruction:"VBLENDPS Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0C /r ib"/"RVMI" { .Instruction = ND_INS_VBLENDPS, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 920, + .Mnemonic = 951, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -74861,6 +78715,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -74876,12 +78731,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2684 Instruction:"VBLENDVPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x4B /r is4"/"RVML" + // Pos:2725 Instruction:"VBLENDVPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x4B /r is4"/"RVML" { .Instruction = ND_INS_VBLENDVPD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 921, + .Mnemonic = 952, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -74890,6 +78745,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -74905,12 +78761,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2685 Instruction:"VBLENDVPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x4A /r is4"/"RVML" + // Pos:2726 Instruction:"VBLENDVPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x4A /r is4"/"RVML" { .Instruction = ND_INS_VBLENDVPS, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 922, + .Mnemonic = 953, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -74919,6 +78775,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -74934,12 +78791,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2686 Instruction:"VBROADCASTF128 Vqq,Mdq" Encoding:"vex m:2 p:1 l:1 w:0 0x1A /r:mem"/"RM" + // Pos:2727 Instruction:"VBROADCASTF128 Vqq,Mdq" Encoding:"vex m:2 p:1 l:1 w:0 0x1A /r:mem"/"RM" { .Instruction = ND_INS_VBROADCASTF128, .Category = ND_CAT_BROADCAST, .IsaSet = ND_SET_AVX, - .Mnemonic = 923, + .Mnemonic = 954, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -74948,6 +78805,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_6, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -74961,12 +78819,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2687 Instruction:"VBROADCASTF32X2 Vuv{K}{z},aKq,Wq" Encoding:"evex m:2 p:1 l:x w:0 0x19 /r"/"RAM" + // Pos:2728 Instruction:"VBROADCASTF32X2 Vuv{K}{z},aKq,Wq" Encoding:"evex m:2 p:1 l:x w:0 0x19 /r"/"RAM" { .Instruction = ND_INS_VBROADCASTF32X2, .Category = ND_CAT_BROADCAST, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 924, + .Mnemonic = 955, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -74975,6 +78833,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E6, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -74989,12 +78848,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2688 Instruction:"VBROADCASTF32X4 Vuv{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:0 0x1A /r:mem"/"RAM" + // Pos:2729 Instruction:"VBROADCASTF32X4 Vuv{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:0 0x1A /r:mem"/"RAM" { .Instruction = ND_INS_VBROADCASTF32X4, .Category = ND_CAT_BROADCAST, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 925, + .Mnemonic = 956, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -75003,6 +78862,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E6, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -75017,12 +78877,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2689 Instruction:"VBROADCASTF32X8 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:0 0x1B /r:mem"/"RAM" + // Pos:2730 Instruction:"VBROADCASTF32X8 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:0 0x1B /r:mem"/"RAM" { .Instruction = ND_INS_VBROADCASTF32X8, .Category = ND_CAT_BROADCAST, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 926, + .Mnemonic = 957, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -75031,6 +78891,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E6, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -75045,12 +78906,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2690 Instruction:"VBROADCASTF64X2 Vuv{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:1 0x1A /r:mem"/"RAM" + // Pos:2731 Instruction:"VBROADCASTF64X2 Vuv{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:1 0x1A /r:mem"/"RAM" { .Instruction = ND_INS_VBROADCASTF64X2, .Category = ND_CAT_BROADCAST, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 927, + .Mnemonic = 958, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -75059,6 +78920,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E6, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -75073,12 +78935,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2691 Instruction:"VBROADCASTF64X4 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:1 0x1B /r:mem"/"RAM" + // Pos:2732 Instruction:"VBROADCASTF64X4 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:1 0x1B /r:mem"/"RAM" { .Instruction = ND_INS_VBROADCASTF64X4, .Category = ND_CAT_BROADCAST, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 928, + .Mnemonic = 959, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -75087,6 +78949,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E6, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -75101,12 +78964,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2692 Instruction:"VBROADCASTI128 Vqq,Mdq" Encoding:"vex m:2 p:1 l:1 w:0 0x5A /r:mem"/"RM" + // Pos:2733 Instruction:"VBROADCASTI128 Vqq,Mdq" Encoding:"vex m:2 p:1 l:1 w:0 0x5A /r:mem"/"RM" { .Instruction = ND_INS_VBROADCASTI128, .Category = ND_CAT_BROADCAST, .IsaSet = ND_SET_AVX2, - .Mnemonic = 929, + .Mnemonic = 960, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -75115,6 +78978,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_6, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -75128,12 +78992,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2693 Instruction:"VBROADCASTI32X2 Vfv{K}{z},aKq,Wq" Encoding:"evex m:2 p:1 l:x w:0 0x59 /r"/"RAM" + // Pos:2734 Instruction:"VBROADCASTI32X2 Vfv{K}{z},aKq,Wq" Encoding:"evex m:2 p:1 l:x w:0 0x59 /r"/"RAM" { .Instruction = ND_INS_VBROADCASTI32X2, .Category = ND_CAT_BROADCAST, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 930, + .Mnemonic = 961, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -75142,6 +79006,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E6, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -75156,12 +79021,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2694 Instruction:"VBROADCASTI32X4 Vuv{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:0 0x5A /r:mem"/"RAM" + // Pos:2735 Instruction:"VBROADCASTI32X4 Vuv{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:0 0x5A /r:mem"/"RAM" { .Instruction = ND_INS_VBROADCASTI32X4, .Category = ND_CAT_BROADCAST, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 931, + .Mnemonic = 962, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -75170,6 +79035,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E6, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -75184,12 +79050,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2695 Instruction:"VBROADCASTI32X8 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:0 0x5B /r:mem"/"RAM" + // Pos:2736 Instruction:"VBROADCASTI32X8 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:0 0x5B /r:mem"/"RAM" { .Instruction = ND_INS_VBROADCASTI32X8, .Category = ND_CAT_BROADCAST, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 932, + .Mnemonic = 963, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -75198,6 +79064,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E6, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -75212,12 +79079,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2696 Instruction:"VBROADCASTI64X2 Vuv{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:1 0x5A /r:mem"/"RAM" + // Pos:2737 Instruction:"VBROADCASTI64X2 Vuv{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:1 0x5A /r:mem"/"RAM" { .Instruction = ND_INS_VBROADCASTI64X2, .Category = ND_CAT_BROADCAST, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 933, + .Mnemonic = 964, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -75226,6 +79093,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E6, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -75240,12 +79108,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2697 Instruction:"VBROADCASTI64X4 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:1 0x5B /r:mem"/"RAM" + // Pos:2738 Instruction:"VBROADCASTI64X4 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:1 0x5B /r:mem"/"RAM" { .Instruction = ND_INS_VBROADCASTI64X4, .Category = ND_CAT_BROADCAST, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 934, + .Mnemonic = 965, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -75254,6 +79122,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E6, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -75268,12 +79137,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2698 Instruction:"VBROADCASTSD Vuv{K}{z},aKq,Wsd" Encoding:"evex m:2 p:1 l:x w:1 0x19 /r"/"RAM" + // Pos:2739 Instruction:"VBROADCASTSD Vuv{K}{z},aKq,Wsd" Encoding:"evex m:2 p:1 l:x w:1 0x19 /r"/"RAM" { .Instruction = ND_INS_VBROADCASTSD, .Category = ND_CAT_BROADCAST, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 935, + .Mnemonic = 966, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -75282,6 +79151,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E6, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -75296,12 +79166,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2699 Instruction:"VBROADCASTSD Vqq,Wsd" Encoding:"vex m:2 p:1 l:x w:0 0x19 /r"/"RM" + // Pos:2740 Instruction:"VBROADCASTSD Vqq,Wsd" Encoding:"vex m:2 p:1 l:x w:0 0x19 /r"/"RM" { .Instruction = ND_INS_VBROADCASTSD, .Category = ND_CAT_BROADCAST, .IsaSet = ND_SET_AVX, - .Mnemonic = 935, + .Mnemonic = 966, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -75310,6 +79180,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_6, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -75323,12 +79194,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2700 Instruction:"VBROADCASTSS Vfv{K}{z},aKq,Wss" Encoding:"evex m:2 p:1 l:x w:0 0x18 /r"/"RAM" + // Pos:2741 Instruction:"VBROADCASTSS Vfv{K}{z},aKq,Wss" Encoding:"evex m:2 p:1 l:x w:0 0x18 /r"/"RAM" { .Instruction = ND_INS_VBROADCASTSS, .Category = ND_CAT_BROADCAST, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 936, + .Mnemonic = 967, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -75337,6 +79208,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E6, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -75351,12 +79223,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2701 Instruction:"VBROADCASTSS Vx,Wss" Encoding:"vex m:2 p:1 l:x w:0 0x18 /r"/"RM" + // Pos:2742 Instruction:"VBROADCASTSS Vx,Wss" Encoding:"vex m:2 p:1 l:x w:0 0x18 /r"/"RM" { .Instruction = ND_INS_VBROADCASTSS, .Category = ND_CAT_BROADCAST, .IsaSet = ND_SET_AVX, - .Mnemonic = 936, + .Mnemonic = 967, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -75365,6 +79237,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_6, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -75378,12 +79251,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2702 Instruction:"VCMPPBF16 rK{K},aKq,Hfv,Wfv|B16,Ib" Encoding:"evex m:3 p:3 l:x w:0 0xC2 /r ib"/"RAVMI" + // Pos:2743 Instruction:"VCMPPBF16 rK{K},aKq,Hfv,Wfv|B16,Ib" Encoding:"evex m:3 p:3 l:x w:0 0xC2 /r ib"/"RAVMI" { .Instruction = ND_INS_VCMPPBF16, .Category = ND_CAT_AVX10BF16, .IsaSet = ND_SET_AVX102, - .Mnemonic = 937, + .Mnemonic = 968, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_BROADCAST, @@ -75392,6 +79265,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -75408,12 +79282,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2703 Instruction:"VCMPPD rKq{K},aKq,Hfv,Wfv|B64{sae},Ib" Encoding:"evex m:1 p:1 l:x w:1 0xC2 /r ib"/"RAVMI" + // Pos:2744 Instruction:"VCMPPD rKq{K},aKq,Hfv,Wfv|B64{sae},Ib" Encoding:"evex m:1 p:1 l:x w:1 0xC2 /r ib"/"RAVMI" { .Instruction = ND_INS_VCMPPD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 938, + .Mnemonic = 969, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -75422,6 +79296,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -75438,12 +79313,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2704 Instruction:"VCMPPD Vpd,Hpd,Wpd,Ib" Encoding:"vex m:1 p:1 l:x w:i 0xC2 /r ib"/"RVMI" + // Pos:2745 Instruction:"VCMPPD Vpd,Hpd,Wpd,Ib" Encoding:"vex m:1 p:1 l:x w:i 0xC2 /r ib"/"RVMI" { .Instruction = ND_INS_VCMPPD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 938, + .Mnemonic = 969, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -75452,6 +79327,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -75467,12 +79343,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2705 Instruction:"VCMPPH rK{K},aKq,Hfv,Wfv|B16{sae},Ib" Encoding:"evex m:3 p:0 l:x w:0 0xC2 /r ib"/"RAVMI" + // Pos:2746 Instruction:"VCMPPH rK{K},aKq,Hfv,Wfv|B16{sae},Ib" Encoding:"evex m:3 p:0 l:x w:0 0xC2 /r ib"/"RAVMI" { .Instruction = ND_INS_VCMPPH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 939, + .Mnemonic = 970, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -75481,6 +79357,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -75497,12 +79374,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2706 Instruction:"VCMPPS rKq{K},aKq,Hfv,Wfv|B32{sae},Ib" Encoding:"evex m:1 p:0 l:x w:0 0xC2 /r ib"/"RAVMI" + // Pos:2747 Instruction:"VCMPPS rKq{K},aKq,Hfv,Wfv|B32{sae},Ib" Encoding:"evex m:1 p:0 l:x w:0 0xC2 /r ib"/"RAVMI" { .Instruction = ND_INS_VCMPPS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 940, + .Mnemonic = 971, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -75511,6 +79388,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -75527,12 +79405,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2707 Instruction:"VCMPPS Vss,Hss,Wss,Ib" Encoding:"vex m:1 p:0 l:i w:i 0xC2 /r ib"/"RVMI" + // Pos:2748 Instruction:"VCMPPS Vss,Hss,Wss,Ib" Encoding:"vex m:1 p:0 l:i w:i 0xC2 /r ib"/"RVMI" { .Instruction = ND_INS_VCMPPS, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 940, + .Mnemonic = 971, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -75541,6 +79419,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -75556,12 +79435,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2708 Instruction:"VCMPSD rKq{K},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:1 p:3 l:x w:1 0xC2 /r ib"/"RAVMI" + // Pos:2749 Instruction:"VCMPSD rKq{K},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:1 p:3 l:x w:1 0xC2 /r ib"/"RAVMI" { .Instruction = ND_INS_VCMPSD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 941, + .Mnemonic = 972, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_SAE, @@ -75570,6 +79449,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -75586,12 +79466,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2709 Instruction:"VCMPSD Vsd,Hsd,Wsd,Ib" Encoding:"vex m:1 p:3 l:i w:i 0xC2 /r ib"/"RVMI" + // Pos:2750 Instruction:"VCMPSD Vsd,Hsd,Wsd,Ib" Encoding:"vex m:1 p:3 l:i w:i 0xC2 /r ib"/"RVMI" { .Instruction = ND_INS_VCMPSD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 941, + .Mnemonic = 972, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -75600,6 +79480,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -75615,12 +79496,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2710 Instruction:"VCMPSH rK{K},aKq,Hfv,Wsh{sae},Ib" Encoding:"evex m:3 p:2 l:i w:0 0xC2 /r ib"/"RAVMI" + // Pos:2751 Instruction:"VCMPSH rK{K},aKq,Hfv,Wsh{sae},Ib" Encoding:"evex m:3 p:2 l:i w:0 0xC2 /r ib"/"RAVMI" { .Instruction = ND_INS_VCMPSH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 942, + .Mnemonic = 973, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_SAE, @@ -75629,6 +79510,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -75645,12 +79527,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2711 Instruction:"VCMPSS rKq{K},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:1 p:2 l:x w:0 0xC2 /r ib"/"RAVMI" + // Pos:2752 Instruction:"VCMPSS rKq{K},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:1 p:2 l:x w:0 0xC2 /r ib"/"RAVMI" { .Instruction = ND_INS_VCMPSS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 943, + .Mnemonic = 974, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_SAE, @@ -75659,6 +79541,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -75675,12 +79558,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2712 Instruction:"VCMPSS Vss,Hss,Wss,Ib" Encoding:"vex m:1 p:2 l:i w:i 0xC2 /r ib"/"RVMI" + // Pos:2753 Instruction:"VCMPSS Vss,Hss,Wss,Ib" Encoding:"vex m:1 p:2 l:i w:i 0xC2 /r ib"/"RVMI" { .Instruction = ND_INS_VCMPSS, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 943, + .Mnemonic = 974, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -75689,6 +79572,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -75704,12 +79588,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2713 Instruction:"VCOMISD Vdq,Wsd{sae}" Encoding:"evex m:1 p:1 l:i w:1 0x2F /r"/"RM" + // Pos:2754 Instruction:"VCOMISD Vdq,Wsd{sae}" Encoding:"evex m:1 p:1 l:i w:1 0x2F /r"/"RM" { .Instruction = ND_INS_VCOMISD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 944, + .Mnemonic = 975, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_SAE, @@ -75718,6 +79602,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, .SetFlags = 0, @@ -75732,12 +79617,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2714 Instruction:"VCOMISD Vsd,Wsd" Encoding:"vex m:1 p:1 l:i w:i 0x2F /r"/"RM" + // Pos:2755 Instruction:"VCOMISD Vsd,Wsd" Encoding:"vex m:1 p:1 l:i w:i 0x2F /r"/"RM" { .Instruction = ND_INS_VCOMISD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 944, + .Mnemonic = 975, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -75746,6 +79631,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, .SetFlags = 0, @@ -75760,12 +79646,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2715 Instruction:"VCOMISH Vdq,Wsh{sae}" Encoding:"evex m:5 p:0 l:i w:0 0x2F /r"/"RM" + // Pos:2756 Instruction:"VCOMISH Vdq,Wsh{sae}" Encoding:"evex m:5 p:0 l:i w:0 0x2F /r"/"RM" { .Instruction = ND_INS_VCOMISH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 945, + .Mnemonic = 976, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_SAE, @@ -75774,6 +79660,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_ZF|NDR_RFLAG_PF|NDR_RFLAG_CF, .SetFlags = 0, @@ -75788,12 +79675,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2716 Instruction:"VCOMISS Vdq,Wss{sae}" Encoding:"evex m:1 p:0 l:i w:0 0x2F /r"/"RM" + // Pos:2757 Instruction:"VCOMISS Vdq,Wss{sae}" Encoding:"evex m:1 p:0 l:i w:0 0x2F /r"/"RM" { .Instruction = ND_INS_VCOMISS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 946, + .Mnemonic = 977, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_SAE, @@ -75802,6 +79689,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, .SetFlags = 0, @@ -75816,12 +79704,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2717 Instruction:"VCOMISS Vss,Wss" Encoding:"vex m:1 p:0 l:i w:i 0x2F /r"/"RM" + // Pos:2758 Instruction:"VCOMISS Vss,Wss" Encoding:"vex m:1 p:0 l:i w:i 0x2F /r"/"RM" { .Instruction = ND_INS_VCOMISS, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 946, + .Mnemonic = 977, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -75830,6 +79718,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, .SetFlags = 0, @@ -75844,12 +79733,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2718 Instruction:"VCOMPRESSPD Wfv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:1 0x8A /r"/"MAR" + // Pos:2759 Instruction:"VCOMPRESSPD Wfv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:1 0x8A /r"/"MAR" { .Instruction = ND_INS_VCOMPRESSPD, .Category = ND_CAT_COMPRESS, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 947, + .Mnemonic = 978, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -75858,6 +79747,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4nb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -75872,12 +79762,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2719 Instruction:"VCOMPRESSPS Wfv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:0 0x8A /r"/"MAR" + // Pos:2760 Instruction:"VCOMPRESSPS Wfv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:0 0x8A /r"/"MAR" { .Instruction = ND_INS_VCOMPRESSPS, .Category = ND_CAT_COMPRESS, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 948, + .Mnemonic = 979, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -75886,6 +79776,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4nb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -75900,12 +79791,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2720 Instruction:"VCOMSBF16 Vdq,Wsh" Encoding:"evex m:5 p:1 l:i w:0 0x2F /r"/"RM" + // Pos:2761 Instruction:"VCOMSBF16 Vdq,Wsh" Encoding:"evex m:5 p:1 l:i w:0 0x2F /r"/"RM" { .Instruction = ND_INS_VCOMSBF16, .Category = ND_CAT_AVX10BF16, .IsaSet = ND_SET_AVX102, - .Mnemonic = 949, + .Mnemonic = 980, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -75914,6 +79805,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E10NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_ZF|NDR_RFLAG_PF|NDR_RFLAG_CF, .SetFlags = 0, @@ -75928,12 +79820,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2721 Instruction:"VCOMXSD Vdq,Wsd{sae}" Encoding:"evex m:1 p:2 l:0 w:1 0x2F /r"/"RM" + // Pos:2762 Instruction:"VCOMXSD Vdq,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:1 0x2F /r"/"RM" { .Instruction = ND_INS_VCOMXSD, .Category = ND_CAT_AVX10CMPSFP, .IsaSet = ND_SET_AVX102, - .Mnemonic = 950, + .Mnemonic = 981, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_SAE, @@ -75942,11 +79834,12 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, .ClearedFlags = 0|NDR_RFLAG_AF, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, .CpuidFlag = 0, .Operands = { @@ -75956,12 +79849,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2722 Instruction:"VCOMXSH Vdq,Wsh{sae}" Encoding:"evex m:5 p:3 l:0 w:0 0x2F /r"/"RM" + // Pos:2763 Instruction:"VCOMXSH Vdq,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:0 0x2F /r"/"RM" { .Instruction = ND_INS_VCOMXSH, .Category = ND_CAT_AVX10CMPSFP, .IsaSet = ND_SET_AVX102, - .Mnemonic = 951, + .Mnemonic = 982, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_SAE, @@ -75970,11 +79863,12 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, .ClearedFlags = 0|NDR_RFLAG_AF, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, .CpuidFlag = 0, .Operands = { @@ -75984,12 +79878,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2723 Instruction:"VCOMXSS Vdq,Wss{sae}" Encoding:"evex m:1 p:3 l:0 w:0 0x2F /r"/"RM" + // Pos:2764 Instruction:"VCOMXSS Vdq,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:0 0x2F /r"/"RM" { .Instruction = ND_INS_VCOMXSS, .Category = ND_CAT_AVX10CMPSFP, .IsaSet = ND_SET_AVX102, - .Mnemonic = 952, + .Mnemonic = 983, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_SAE, @@ -75998,11 +79892,12 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, .ClearedFlags = 0|NDR_RFLAG_AF, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, .CpuidFlag = 0, .Operands = { @@ -76012,12 +79907,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2724 Instruction:"VCVT2PS2PHX Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x67 /r"/"RAVM" + // Pos:2765 Instruction:"VCVT2PS2PHX Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x67 /r"/"RAVM" { .Instruction = ND_INS_VCVT2PS2PHX, .Category = ND_CAT_AVX10CONVERT, .IsaSet = ND_SET_AVX102, - .Mnemonic = 953, + .Mnemonic = 984, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -76026,6 +79921,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -76041,12 +79937,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2725 Instruction:"VCVTBIASPH2BF8 Vhv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:2 p:0 l:x w:0 0x74 /r"/"RAVM" + // Pos:2766 Instruction:"VCVTBIASPH2BF8 Vhv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:2 p:0 l:x w:0 0x74 /r"/"RAVM" { .Instruction = ND_INS_VCVTBIASPH2BF8, .Category = ND_CAT_AVX10CONVERT, .IsaSet = ND_SET_AVX102, - .Mnemonic = 954, + .Mnemonic = 985, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -76055,6 +79951,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -76070,12 +79967,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2726 Instruction:"VCVTBIASPH2BF8S Vhv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:5 p:0 l:x w:0 0x74 /r"/"RAVM" + // Pos:2767 Instruction:"VCVTBIASPH2BF8S Vhv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:5 p:0 l:x w:0 0x74 /r"/"RAVM" { .Instruction = ND_INS_VCVTBIASPH2BF8S, .Category = ND_CAT_AVX10CONVERT, .IsaSet = ND_SET_AVX102, - .Mnemonic = 955, + .Mnemonic = 986, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -76084,6 +79981,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -76099,12 +79997,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2727 Instruction:"VCVTBIASPH2HF8 Vhv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:5 p:0 l:x w:0 0x18 /r"/"RAVM" + // Pos:2768 Instruction:"VCVTBIASPH2HF8 Vhv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:5 p:0 l:x w:0 0x18 /r"/"RAVM" { .Instruction = ND_INS_VCVTBIASPH2HF8, .Category = ND_CAT_AVX10CONVERT, .IsaSet = ND_SET_AVX102, - .Mnemonic = 956, + .Mnemonic = 987, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -76113,6 +80011,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -76128,12 +80027,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2728 Instruction:"VCVTBIASPH2HF8S Vhv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:5 p:0 l:x w:0 0x1B /r"/"RAVM" + // Pos:2769 Instruction:"VCVTBIASPH2HF8S Vhv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:5 p:0 l:x w:0 0x1B /r"/"RAVM" { .Instruction = ND_INS_VCVTBIASPH2HF8S, .Category = ND_CAT_AVX10CONVERT, .IsaSet = ND_SET_AVX102, - .Mnemonic = 957, + .Mnemonic = 988, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -76142,6 +80041,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -76157,12 +80057,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2729 Instruction:"VCVTDQ2PD Vfv{K}{z},aKq,Whv|B32" Encoding:"evex m:1 p:2 l:x w:0 0xE6 /r"/"RAM" + // Pos:2770 Instruction:"VCVTDQ2PD Vfv{K}{z},aKq,Whv|B32" Encoding:"evex m:1 p:2 l:x w:0 0xE6 /r"/"RAM" { .Instruction = ND_INS_VCVTDQ2PD, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 958, + .Mnemonic = 989, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -76171,6 +80071,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -76185,12 +80086,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2730 Instruction:"VCVTDQ2PD Vdq,Wq" Encoding:"vex m:1 p:2 l:0 w:i 0xE6 /r"/"RM" + // Pos:2771 Instruction:"VCVTDQ2PD Vdq,Wq" Encoding:"vex m:1 p:2 l:0 w:i 0xE6 /r"/"RM" { .Instruction = ND_INS_VCVTDQ2PD, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX, - .Mnemonic = 958, + .Mnemonic = 989, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -76199,6 +80100,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -76212,12 +80114,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2731 Instruction:"VCVTDQ2PD Vqq,Wdq" Encoding:"vex m:1 p:2 l:1 w:i 0xE6 /r"/"RM" + // Pos:2772 Instruction:"VCVTDQ2PD Vqq,Wdq" Encoding:"vex m:1 p:2 l:1 w:i 0xE6 /r"/"RM" { .Instruction = ND_INS_VCVTDQ2PD, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX, - .Mnemonic = 958, + .Mnemonic = 989, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -76226,6 +80128,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -76239,12 +80142,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2732 Instruction:"VCVTDQ2PH Vhv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:5 p:0 l:x w:0 0x5B /r"/"RAM" + // Pos:2773 Instruction:"VCVTDQ2PH Vhv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:5 p:0 l:x w:0 0x5B /r"/"RAM" { .Instruction = ND_INS_VCVTDQ2PH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 959, + .Mnemonic = 990, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -76253,6 +80156,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_PE|ND_SIMD_EXC_OE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -76267,12 +80171,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2733 Instruction:"VCVTDQ2PS Vfv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x5B /r"/"RAM" + // Pos:2774 Instruction:"VCVTDQ2PS Vfv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x5B /r"/"RAM" { .Instruction = ND_INS_VCVTDQ2PS, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 960, + .Mnemonic = 991, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -76281,6 +80185,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -76295,12 +80200,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2734 Instruction:"VCVTDQ2PS Vps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5B /r"/"RM" + // Pos:2775 Instruction:"VCVTDQ2PS Vps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5B /r"/"RM" { .Instruction = ND_INS_VCVTDQ2PS, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX, - .Mnemonic = 960, + .Mnemonic = 991, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -76309,6 +80214,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -76322,12 +80228,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2735 Instruction:"VCVTHF82PH Vfv{K}{z},aKq,Whv" Encoding:"evex m:5 p:3 l:x w:0 0x1E /r"/"RAM" + // Pos:2776 Instruction:"VCVTHF82PH Vfv{K}{z},aKq,Whv" Encoding:"evex m:5 p:3 l:x w:0 0x1E /r"/"RAM" { .Instruction = ND_INS_VCVTHF82PH, .Category = ND_CAT_AVX10CONVERT, .IsaSet = ND_SET_AVX102, - .Mnemonic = 961, + .Mnemonic = 992, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -76336,6 +80242,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -76350,12 +80257,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2736 Instruction:"VCVTNE2PH2BF8 Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:1 p:3 l:x w:0 0x74 /r"/"RAVM" + // Pos:2777 Instruction:"VCVTNE2PH2BF8 Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:2 p:3 l:x w:0 0x74 /r"/"RAVM" { .Instruction = ND_INS_VCVTNE2PH2BF8, .Category = ND_CAT_AVX10CONVERT, .IsaSet = ND_SET_AVX102, - .Mnemonic = 962, + .Mnemonic = 993, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -76364,6 +80271,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -76379,12 +80287,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2737 Instruction:"VCVTNE2PH2BF8S Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:5 p:3 l:x w:0 0x74 /r"/"RAVM" + // Pos:2778 Instruction:"VCVTNE2PH2BF8S Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:5 p:3 l:x w:0 0x74 /r"/"RAVM" { .Instruction = ND_INS_VCVTNE2PH2BF8S, .Category = ND_CAT_AVX10CONVERT, .IsaSet = ND_SET_AVX102, - .Mnemonic = 963, + .Mnemonic = 994, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -76393,6 +80301,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -76408,12 +80317,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2738 Instruction:"VCVTNE2PH2HF8 Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:5 p:3 l:x w:0 0x18 /r"/"RAVM" + // Pos:2779 Instruction:"VCVTNE2PH2HF8 Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:5 p:3 l:x w:0 0x18 /r"/"RAVM" { .Instruction = ND_INS_VCVTNE2PH2HF8, .Category = ND_CAT_AVX10CONVERT, .IsaSet = ND_SET_AVX102, - .Mnemonic = 964, + .Mnemonic = 995, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -76422,6 +80331,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -76437,12 +80347,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2739 Instruction:"VCVTNE2PH2HF8S Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:5 p:3 l:x w:0 0x1B /r"/"RAVM" + // Pos:2780 Instruction:"VCVTNE2PH2HF8S Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:5 p:3 l:x w:0 0x1B /r"/"RAVM" { .Instruction = ND_INS_VCVTNE2PH2HF8S, .Category = ND_CAT_AVX10CONVERT, .IsaSet = ND_SET_AVX102, - .Mnemonic = 965, + .Mnemonic = 996, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -76451,6 +80361,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -76466,12 +80377,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2740 Instruction:"VCVTNE2PS2BF16 Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:3 l:x w:0 0x72 /r"/"RAVM" + // Pos:2781 Instruction:"VCVTNE2PS2BF16 Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:3 l:x w:0 0x72 /r"/"RAVM" { .Instruction = ND_INS_VCVTNE2PS2BF16, .Category = ND_CAT_AVX512BF16, .IsaSet = ND_SET_AVX512BF16, - .Mnemonic = 966, + .Mnemonic = 997, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -76480,6 +80391,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -76495,12 +80407,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2741 Instruction:"VCVTNEBF162IBS Vfv{K}{z},aKq,Wfv|B16" Encoding:"evex m:5 p:3 l:x w:0 0x69 /r"/"RAM" + // Pos:2782 Instruction:"VCVTNEBF162IBS Vfv{K}{z},aKq,Wfv|B16" Encoding:"evex m:5 p:3 l:x w:0 0x69 /r"/"RAM" { .Instruction = ND_INS_VCVTNEBF162IBS, .Category = ND_CAT_AVX10SCONVERT, .IsaSet = ND_SET_AVX102, - .Mnemonic = 967, + .Mnemonic = 998, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -76509,6 +80421,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -76523,12 +80436,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2742 Instruction:"VCVTNEBF162IUBS Vfv{K}{z},aKq,Wfv|B16" Encoding:"evex m:5 p:3 l:x w:0 0x6B /r"/"RAM" + // Pos:2783 Instruction:"VCVTNEBF162IUBS Vfv{K}{z},aKq,Wfv|B16" Encoding:"evex m:5 p:3 l:x w:0 0x6B /r"/"RAM" { .Instruction = ND_INS_VCVTNEBF162IUBS, .Category = ND_CAT_AVX10SCONVERT, .IsaSet = ND_SET_AVX102, - .Mnemonic = 968, + .Mnemonic = 999, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -76537,6 +80450,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -76551,12 +80465,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2743 Instruction:"VCVTNEEBF162PS Vx,Mx" Encoding:"vex m:2 p:2 l:x w:0 0xB0 /r:mem"/"RM" + // Pos:2784 Instruction:"VCVTNEEBF162PS Vx,Mx" Encoding:"vex m:2 p:2 l:x w:0 0xB0 /r:mem"/"RM" { .Instruction = ND_INS_VCVTNEEBF162PS, .Category = ND_CAT_AVXNECONVERT, .IsaSet = ND_SET_AVXNECONVERT, - .Mnemonic = 969, + .Mnemonic = 1000, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -76565,6 +80479,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -76578,12 +80493,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2744 Instruction:"VCVTNEEPH2PS Vx,Mx" Encoding:"vex m:2 p:1 l:x w:0 0xB0 /r:mem"/"RM" + // Pos:2785 Instruction:"VCVTNEEPH2PS Vx,Mx" Encoding:"vex m:2 p:1 l:x w:0 0xB0 /r:mem"/"RM" { .Instruction = ND_INS_VCVTNEEPH2PS, .Category = ND_CAT_AVXNECONVERT, .IsaSet = ND_SET_AVXNECONVERT, - .Mnemonic = 970, + .Mnemonic = 1001, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -76592,6 +80507,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -76605,12 +80521,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2745 Instruction:"VCVTNEOBF162PS Vx,Mx" Encoding:"vex m:2 p:3 l:x w:0 0xB0 /r:mem"/"RM" + // Pos:2786 Instruction:"VCVTNEOBF162PS Vx,Mx" Encoding:"vex m:2 p:3 l:x w:0 0xB0 /r:mem"/"RM" { .Instruction = ND_INS_VCVTNEOBF162PS, .Category = ND_CAT_AVXNECONVERT, .IsaSet = ND_SET_AVXNECONVERT, - .Mnemonic = 971, + .Mnemonic = 1002, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -76619,6 +80535,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -76632,12 +80549,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2746 Instruction:"VCVTNEOPH2PS Vx,Mx" Encoding:"vex m:2 p:0 l:x w:0 0xB0 /r:mem"/"RM" + // Pos:2787 Instruction:"VCVTNEOPH2PS Vx,Mx" Encoding:"vex m:2 p:0 l:x w:0 0xB0 /r:mem"/"RM" { .Instruction = ND_INS_VCVTNEOPH2PS, .Category = ND_CAT_AVXNECONVERT, .IsaSet = ND_SET_AVXNECONVERT, - .Mnemonic = 972, + .Mnemonic = 1003, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -76646,6 +80563,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -76659,12 +80577,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2747 Instruction:"VCVTNEPH2BF8 Vhv{K}{z},aKq,Wfv|B16" Encoding:"evex m:1 p:2 l:x w:0 0x74 /r"/"RAM" + // Pos:2788 Instruction:"VCVTNEPH2BF8 Vhv{K}{z},aKq,Wfv|B16" Encoding:"evex m:2 p:2 l:x w:0 0x74 /r"/"RAM" { .Instruction = ND_INS_VCVTNEPH2BF8, .Category = ND_CAT_AVX10CONVERT, .IsaSet = ND_SET_AVX102, - .Mnemonic = 973, + .Mnemonic = 1004, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -76673,6 +80591,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -76687,12 +80606,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2748 Instruction:"VCVTNEPH2BF8S Vhv{K}{z},aKq,Wfv|B16" Encoding:"evex m:5 p:2 l:x w:0 0x74 /r"/"RAM" + // Pos:2789 Instruction:"VCVTNEPH2BF8S Vhv{K}{z},aKq,Wfv|B16" Encoding:"evex m:5 p:2 l:x w:0 0x74 /r"/"RAM" { .Instruction = ND_INS_VCVTNEPH2BF8S, .Category = ND_CAT_AVX10CONVERT, .IsaSet = ND_SET_AVX102, - .Mnemonic = 974, + .Mnemonic = 1005, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -76701,6 +80620,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -76715,12 +80635,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2749 Instruction:"VCVTNEPH2HF8 Vhv{K}{z},aKq,Wfv|B16" Encoding:"evex m:5 p:2 l:x w:0 0x18 /r"/"RAM" + // Pos:2790 Instruction:"VCVTNEPH2HF8 Vhv{K}{z},aKq,Wfv|B16" Encoding:"evex m:5 p:2 l:x w:0 0x18 /r"/"RAM" { .Instruction = ND_INS_VCVTNEPH2HF8, .Category = ND_CAT_AVX10CONVERT, .IsaSet = ND_SET_AVX102, - .Mnemonic = 975, + .Mnemonic = 1006, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -76729,6 +80649,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -76743,12 +80664,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2750 Instruction:"VCVTNEPH2HF8S Vhv{K}{z},aKq,Wfv|B16" Encoding:"evex m:5 p:2 l:x w:0 0x1B /r"/"RAM" + // Pos:2791 Instruction:"VCVTNEPH2HF8S Vhv{K}{z},aKq,Wfv|B16" Encoding:"evex m:5 p:2 l:x w:0 0x1B /r"/"RAM" { .Instruction = ND_INS_VCVTNEPH2HF8S, .Category = ND_CAT_AVX10CONVERT, .IsaSet = ND_SET_AVX102, - .Mnemonic = 976, + .Mnemonic = 1007, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -76757,6 +80678,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -76771,12 +80693,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2751 Instruction:"VCVTNEPS2BF16 Vhv{K}{z},aKq,Wfv|B32" Encoding:"evex m:2 p:2 l:x w:0 0x72 /r"/"RAM" + // Pos:2792 Instruction:"VCVTNEPS2BF16 Vhv{K}{z},aKq,Wfv|B32" Encoding:"evex m:2 p:2 l:x w:0 0x72 /r"/"RAM" { .Instruction = ND_INS_VCVTNEPS2BF16, .Category = ND_CAT_AVX512BF16, .IsaSet = ND_SET_AVX512BF16, - .Mnemonic = 977, + .Mnemonic = 1008, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -76785,6 +80707,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -76799,12 +80722,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2752 Instruction:"VCVTNEPS2BF16 Vx,Wx" Encoding:"vex m:2 p:2 l:x w:0 0x72 /r"/"RM" + // Pos:2793 Instruction:"VCVTNEPS2BF16 Vx,Wx" Encoding:"vex m:2 p:2 l:x w:0 0x72 /r"/"RM" { .Instruction = ND_INS_VCVTNEPS2BF16, .Category = ND_CAT_AVXNECONVERT, .IsaSet = ND_SET_AVXNECONVERT, - .Mnemonic = 977, + .Mnemonic = 1008, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -76813,6 +80736,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -76826,12 +80750,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2753 Instruction:"VCVTPD2DQ Vhv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:3 l:x w:1 0xE6 /r"/"RAM" + // Pos:2794 Instruction:"VCVTPD2DQ Vhv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:3 l:x w:1 0xE6 /r"/"RAM" { .Instruction = ND_INS_VCVTPD2DQ, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 978, + .Mnemonic = 1009, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -76840,6 +80764,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -76854,12 +80779,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2754 Instruction:"VCVTPD2DQ Vdq,Wx" Encoding:"vex m:1 p:3 l:x w:i 0xE6 /r"/"RM" + // Pos:2795 Instruction:"VCVTPD2DQ Vdq,Wx" Encoding:"vex m:1 p:3 l:x w:i 0xE6 /r"/"RM" { .Instruction = ND_INS_VCVTPD2DQ, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX, - .Mnemonic = 978, + .Mnemonic = 1009, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -76868,6 +80793,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -76881,12 +80807,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2755 Instruction:"VCVTPD2PH Vdq{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:5 p:1 l:x w:1 0x5A /r"/"RAM" + // Pos:2796 Instruction:"VCVTPD2PH Vdq{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:5 p:1 l:x w:1 0x5A /r"/"RAM" { .Instruction = ND_INS_VCVTPD2PH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 979, + .Mnemonic = 1010, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -76895,6 +80821,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -76909,12 +80836,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2756 Instruction:"VCVTPD2PS Vhv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x5A /r"/"RAM" + // Pos:2797 Instruction:"VCVTPD2PS Vhv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x5A /r"/"RAM" { .Instruction = ND_INS_VCVTPD2PS, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 980, + .Mnemonic = 1011, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -76923,6 +80850,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -76937,12 +80865,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2757 Instruction:"VCVTPD2PS Vdq,Wdq" Encoding:"vex m:1 p:1 l:0 w:i 0x5A /r"/"RM" + // Pos:2798 Instruction:"VCVTPD2PS Vdq,Wdq" Encoding:"vex m:1 p:1 l:0 w:i 0x5A /r"/"RM" { .Instruction = ND_INS_VCVTPD2PS, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX, - .Mnemonic = 980, + .Mnemonic = 1011, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -76951,6 +80879,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -76964,12 +80893,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2758 Instruction:"VCVTPD2PS Vdq,Wqq" Encoding:"vex m:1 p:1 l:1 w:i 0x5A /r"/"RM" + // Pos:2799 Instruction:"VCVTPD2PS Vdq,Wqq" Encoding:"vex m:1 p:1 l:1 w:i 0x5A /r"/"RM" { .Instruction = ND_INS_VCVTPD2PS, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX, - .Mnemonic = 980, + .Mnemonic = 1011, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -76978,6 +80907,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -76991,12 +80921,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2759 Instruction:"VCVTPD2QQ Vfv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x7B /r"/"RAM" + // Pos:2800 Instruction:"VCVTPD2QQ Vfv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x7B /r"/"RAM" { .Instruction = ND_INS_VCVTPD2QQ, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 981, + .Mnemonic = 1012, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -77005,6 +80935,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -77019,12 +80950,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2760 Instruction:"VCVTPD2UDQ Vhv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:0 l:x w:1 0x79 /r"/"RAM" + // Pos:2801 Instruction:"VCVTPD2UDQ Vhv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:0 l:x w:1 0x79 /r"/"RAM" { .Instruction = ND_INS_VCVTPD2UDQ, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 982, + .Mnemonic = 1013, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -77033,6 +80964,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -77047,12 +80979,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2761 Instruction:"VCVTPD2UQQ Vfv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x79 /r"/"RAM" + // Pos:2802 Instruction:"VCVTPD2UQQ Vfv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x79 /r"/"RAM" { .Instruction = ND_INS_VCVTPD2UQQ, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 983, + .Mnemonic = 1014, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -77061,6 +80993,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -77075,12 +81008,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2762 Instruction:"VCVTPH2DQ Vfv{K}{z},aKq,Whv|B16{er}" Encoding:"evex m:5 p:1 l:x w:0 0x5B /r"/"RAM" + // Pos:2803 Instruction:"VCVTPH2DQ Vfv{K}{z},aKq,Whv|B16{er}" Encoding:"evex m:5 p:1 l:x w:0 0x5B /r"/"RAM" { .Instruction = ND_INS_VCVTPH2DQ, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 984, + .Mnemonic = 1015, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -77089,6 +81022,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -77103,12 +81037,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2763 Instruction:"VCVTPH2IBS Vfv{K}{z},aKq,Wfv|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x69 /r"/"RAM" + // Pos:2804 Instruction:"VCVTPH2IBS Vfv{K}{z},aKq,Wfv|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x69 /r"/"RAM" { .Instruction = ND_INS_VCVTPH2IBS, .Category = ND_CAT_AVX10SCONVERT, .IsaSet = ND_SET_AVX102, - .Mnemonic = 985, + .Mnemonic = 1016, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -77117,6 +81051,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -77131,12 +81066,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2764 Instruction:"VCVTPH2IUBS Vfv{K}{z},aKq,Wfv|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x6B /r"/"RAM" + // Pos:2805 Instruction:"VCVTPH2IUBS Vfv{K}{z},aKq,Wfv|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x6B /r"/"RAM" { .Instruction = ND_INS_VCVTPH2IUBS, .Category = ND_CAT_AVX10SCONVERT, .IsaSet = ND_SET_AVX102, - .Mnemonic = 986, + .Mnemonic = 1017, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -77145,6 +81080,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -77159,12 +81095,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2765 Instruction:"VCVTPH2PD Vfv{K}{z},aKq,Wqv|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x5A /r"/"RAM" + // Pos:2806 Instruction:"VCVTPH2PD Vfv{K}{z},aKq,Wqv|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x5A /r"/"RAM" { .Instruction = ND_INS_VCVTPH2PD, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 987, + .Mnemonic = 1018, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -77173,6 +81109,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -77187,12 +81124,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2766 Instruction:"VCVTPH2PS Vfv{K}{z},aKq,Whv{sae}" Encoding:"evex m:2 p:1 l:x w:0 0x13 /r"/"RAM" + // Pos:2807 Instruction:"VCVTPH2PS Vfv{K}{z},aKq,Whv{sae}" Encoding:"evex m:2 p:1 l:x w:0 0x13 /r"/"RAM" { .Instruction = ND_INS_VCVTPH2PS, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 988, + .Mnemonic = 1019, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, @@ -77201,6 +81138,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E11, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -77215,12 +81153,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2767 Instruction:"VCVTPH2PS Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:0 0x13 /r"/"RM" + // Pos:2808 Instruction:"VCVTPH2PS Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:0 0x13 /r"/"RM" { .Instruction = ND_INS_VCVTPH2PS, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_F16C, - .Mnemonic = 988, + .Mnemonic = 1019, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -77229,6 +81167,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_11, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -77242,12 +81181,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2768 Instruction:"VCVTPH2PS Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:0 0x13 /r"/"RM" + // Pos:2809 Instruction:"VCVTPH2PS Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:0 0x13 /r"/"RM" { .Instruction = ND_INS_VCVTPH2PS, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_F16C, - .Mnemonic = 988, + .Mnemonic = 1019, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -77256,6 +81195,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_11, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -77269,12 +81209,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2769 Instruction:"VCVTPH2PSX Vfv{K}{z},aKq,Whv|B16{sae}" Encoding:"evex m:6 p:1 l:x w:0 0x13 /r"/"RAM" + // Pos:2810 Instruction:"VCVTPH2PSX Vfv{K}{z},aKq,Whv|B16{sae}" Encoding:"evex m:6 p:1 l:x w:0 0x13 /r"/"RAM" { .Instruction = ND_INS_VCVTPH2PSX, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 989, + .Mnemonic = 1020, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -77283,6 +81223,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -77297,12 +81238,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2770 Instruction:"VCVTPH2QQ Vfv{K}{z},aKq,Wqv|B16{er}" Encoding:"evex m:5 p:1 l:x w:0 0x7B /r"/"RAM" + // Pos:2811 Instruction:"VCVTPH2QQ Vfv{K}{z},aKq,Wqv|B16{er}" Encoding:"evex m:5 p:1 l:x w:0 0x7B /r"/"RAM" { .Instruction = ND_INS_VCVTPH2QQ, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 990, + .Mnemonic = 1021, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -77311,6 +81252,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -77325,12 +81267,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2771 Instruction:"VCVTPH2UDQ Vfv{K}{z},aKq,Whv|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x79 /r"/"RAM" + // Pos:2812 Instruction:"VCVTPH2UDQ Vfv{K}{z},aKq,Whv|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x79 /r"/"RAM" { .Instruction = ND_INS_VCVTPH2UDQ, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 991, + .Mnemonic = 1022, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -77339,6 +81281,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -77353,12 +81296,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2772 Instruction:"VCVTPH2UQQ Vfv{K}{z},aKq,Wqv|B16{er}" Encoding:"evex m:5 p:1 l:x w:0 0x79 /r"/"RAM" + // Pos:2813 Instruction:"VCVTPH2UQQ Vfv{K}{z},aKq,Wqv|B16{er}" Encoding:"evex m:5 p:1 l:x w:0 0x79 /r"/"RAM" { .Instruction = ND_INS_VCVTPH2UQQ, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 992, + .Mnemonic = 1023, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -77367,6 +81310,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -77381,12 +81325,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2773 Instruction:"VCVTPH2UW Vfv{K}{z},aKq,Wfv|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x7D /r"/"RAM" + // Pos:2814 Instruction:"VCVTPH2UW Vfv{K}{z},aKq,Wfv|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x7D /r"/"RAM" { .Instruction = ND_INS_VCVTPH2UW, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 993, + .Mnemonic = 1024, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -77395,6 +81339,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -77409,12 +81354,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2774 Instruction:"VCVTPH2W Vfv{K}{z},aKq,Wfv|B16{er}" Encoding:"evex m:5 p:1 l:x w:0 0x7D /r"/"RAM" + // Pos:2815 Instruction:"VCVTPH2W Vfv{K}{z},aKq,Wfv|B16{er}" Encoding:"evex m:5 p:1 l:x w:0 0x7D /r"/"RAM" { .Instruction = ND_INS_VCVTPH2W, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 994, + .Mnemonic = 1025, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -77423,6 +81368,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -77437,12 +81383,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2775 Instruction:"VCVTPS2DQ Vfv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:1 p:1 l:x w:0 0x5B /r"/"RAM" + // Pos:2816 Instruction:"VCVTPS2DQ Vfv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:1 p:1 l:x w:0 0x5B /r"/"RAM" { .Instruction = ND_INS_VCVTPS2DQ, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 995, + .Mnemonic = 1026, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -77451,6 +81397,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -77465,12 +81412,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2776 Instruction:"VCVTPS2DQ Vps,Wps" Encoding:"vex m:1 p:1 l:x w:i 0x5B /r"/"RM" + // Pos:2817 Instruction:"VCVTPS2DQ Vps,Wps" Encoding:"vex m:1 p:1 l:x w:i 0x5B /r"/"RM" { .Instruction = ND_INS_VCVTPS2DQ, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX, - .Mnemonic = 995, + .Mnemonic = 1026, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -77479,6 +81426,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -77492,12 +81440,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2777 Instruction:"VCVTPS2IBS Vfv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:5 p:1 l:x w:0 0x69 /r"/"RAM" + // Pos:2818 Instruction:"VCVTPS2IBS Vfv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:5 p:1 l:x w:0 0x69 /r"/"RAM" { .Instruction = ND_INS_VCVTPS2IBS, .Category = ND_CAT_AVX10SCONVERT, .IsaSet = ND_SET_AVX102, - .Mnemonic = 996, + .Mnemonic = 1027, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -77506,6 +81454,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -77520,12 +81469,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2778 Instruction:"VCVTPS2IUBS Vfv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:5 p:1 l:x w:0 0x6B /r"/"RAM" + // Pos:2819 Instruction:"VCVTPS2IUBS Vfv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:5 p:1 l:x w:0 0x6B /r"/"RAM" { .Instruction = ND_INS_VCVTPS2IUBS, .Category = ND_CAT_AVX10SCONVERT, .IsaSet = ND_SET_AVX102, - .Mnemonic = 997, + .Mnemonic = 1028, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -77534,6 +81483,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -77548,12 +81498,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2779 Instruction:"VCVTPS2PD Vfv{K}{z},aKq,Whv|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x5A /r"/"RAM" + // Pos:2820 Instruction:"VCVTPS2PD Vfv{K}{z},aKq,Whv|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x5A /r"/"RAM" { .Instruction = ND_INS_VCVTPS2PD, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 998, + .Mnemonic = 1029, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -77562,6 +81512,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -77576,12 +81527,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2780 Instruction:"VCVTPS2PD Vpd,Wq" Encoding:"vex m:1 p:0 l:0 w:i 0x5A /r"/"RM" + // Pos:2821 Instruction:"VCVTPS2PD Vpd,Wq" Encoding:"vex m:1 p:0 l:0 w:i 0x5A /r"/"RM" { .Instruction = ND_INS_VCVTPS2PD, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX, - .Mnemonic = 998, + .Mnemonic = 1029, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -77590,6 +81541,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -77603,12 +81555,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2781 Instruction:"VCVTPS2PD Vqq,Wdq" Encoding:"vex m:1 p:0 l:1 w:i 0x5A /r"/"RM" + // Pos:2822 Instruction:"VCVTPS2PD Vqq,Wdq" Encoding:"vex m:1 p:0 l:1 w:i 0x5A /r"/"RM" { .Instruction = ND_INS_VCVTPS2PD, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX, - .Mnemonic = 998, + .Mnemonic = 1029, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -77617,6 +81569,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -77630,12 +81583,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2782 Instruction:"VCVTPS2PH Whv{K}{z},aKq,Vfv{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x1D /r ib"/"MARI" + // Pos:2823 Instruction:"VCVTPS2PH Whv{K}{z},aKq,Vfv{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x1D /r ib"/"MARI" { .Instruction = ND_INS_VCVTPS2PH, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 999, + .Mnemonic = 1030, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, @@ -77644,6 +81597,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E11, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -77659,12 +81613,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2783 Instruction:"VCVTPS2PH Wq,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x1D /r ib"/"MRI" + // Pos:2824 Instruction:"VCVTPS2PH Wq,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x1D /r ib"/"MRI" { .Instruction = ND_INS_VCVTPS2PH, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_F16C, - .Mnemonic = 999, + .Mnemonic = 1030, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -77673,6 +81627,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_11, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -77687,12 +81642,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2784 Instruction:"VCVTPS2PH Wdq,Vqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x1D /r ib"/"MRI" + // Pos:2825 Instruction:"VCVTPS2PH Wdq,Vqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x1D /r ib"/"MRI" { .Instruction = ND_INS_VCVTPS2PH, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_F16C, - .Mnemonic = 999, + .Mnemonic = 1030, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -77701,6 +81656,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_11, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -77715,12 +81671,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2785 Instruction:"VCVTPS2PHX Vhv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:5 p:1 l:x w:0 0x1D /r"/"RAM" + // Pos:2826 Instruction:"VCVTPS2PHX Vhv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:5 p:1 l:x w:0 0x1D /r"/"RAM" { .Instruction = ND_INS_VCVTPS2PHX, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1000, + .Mnemonic = 1031, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -77729,6 +81685,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -77743,12 +81700,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2786 Instruction:"VCVTPS2QQ Vfv{K}{z},aKq,Whv|B32{er}" Encoding:"evex m:1 p:1 l:x w:0 0x7B /r"/"RAM" + // Pos:2827 Instruction:"VCVTPS2QQ Vfv{K}{z},aKq,Whv|B32{er}" Encoding:"evex m:1 p:1 l:x w:0 0x7B /r"/"RAM" { .Instruction = ND_INS_VCVTPS2QQ, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 1001, + .Mnemonic = 1032, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -77757,6 +81714,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -77771,12 +81729,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2787 Instruction:"VCVTPS2UDQ Vfv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x79 /r"/"RAM" + // Pos:2828 Instruction:"VCVTPS2UDQ Vfv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x79 /r"/"RAM" { .Instruction = ND_INS_VCVTPS2UDQ, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1002, + .Mnemonic = 1033, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -77785,6 +81743,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -77799,12 +81758,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2788 Instruction:"VCVTPS2UQQ Vfv{K}{z},aKq,Whv|B32{er}" Encoding:"evex m:1 p:1 l:x w:0 0x79 /r"/"RAM" + // Pos:2829 Instruction:"VCVTPS2UQQ Vfv{K}{z},aKq,Whv|B32{er}" Encoding:"evex m:1 p:1 l:x w:0 0x79 /r"/"RAM" { .Instruction = ND_INS_VCVTPS2UQQ, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 1003, + .Mnemonic = 1034, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -77813,6 +81772,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -77827,12 +81787,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2789 Instruction:"VCVTQQ2PD Vfv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:2 l:x w:1 0xE6 /r"/"RAM" + // Pos:2830 Instruction:"VCVTQQ2PD Vfv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:2 l:x w:1 0xE6 /r"/"RAM" { .Instruction = ND_INS_VCVTQQ2PD, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 1004, + .Mnemonic = 1035, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -77841,6 +81801,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -77855,12 +81816,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2790 Instruction:"VCVTQQ2PH Vdq{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:5 p:0 l:x w:1 0x5B /r"/"RAM" + // Pos:2831 Instruction:"VCVTQQ2PH Vdq{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:5 p:0 l:x w:1 0x5B /r"/"RAM" { .Instruction = ND_INS_VCVTQQ2PH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1005, + .Mnemonic = 1036, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -77869,6 +81830,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_PE|ND_SIMD_EXC_OE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -77883,12 +81845,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2791 Instruction:"VCVTQQ2PS Vhv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:0 l:x w:1 0x5B /r"/"RAM" + // Pos:2832 Instruction:"VCVTQQ2PS Vhv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:0 l:x w:1 0x5B /r"/"RAM" { .Instruction = ND_INS_VCVTQQ2PS, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 1006, + .Mnemonic = 1037, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -77897,6 +81859,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -77911,12 +81874,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2792 Instruction:"VCVTSD2SH Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:5 p:3 l:i w:1 0x5A /r"/"RAVM" + // Pos:2833 Instruction:"VCVTSD2SH Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:5 p:3 l:i w:1 0x5A /r"/"RAVM" { .Instruction = ND_INS_VCVTSD2SH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1007, + .Mnemonic = 1038, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -77925,6 +81888,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -77940,12 +81904,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2793 Instruction:"VCVTSD2SI Gy,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:x 0x2D /r"/"RM" + // Pos:2834 Instruction:"VCVTSD2SI Gy,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:x 0x2D /r"/"RM" { .Instruction = ND_INS_VCVTSD2SI, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1008, + .Mnemonic = 1039, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ER, @@ -77954,6 +81918,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -77967,12 +81932,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2794 Instruction:"VCVTSD2SI Gy,Wsd" Encoding:"vex m:1 p:3 l:i w:x 0x2D /r"/"RM" + // Pos:2835 Instruction:"VCVTSD2SI Gy,Wsd" Encoding:"vex m:1 p:3 l:i w:x 0x2D /r"/"RM" { .Instruction = ND_INS_VCVTSD2SI, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX, - .Mnemonic = 1008, + .Mnemonic = 1039, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -77981,6 +81946,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -77994,12 +81960,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2795 Instruction:"VCVTSD2SS Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x5A /r"/"RAVM" + // Pos:2836 Instruction:"VCVTSD2SS Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x5A /r"/"RAVM" { .Instruction = ND_INS_VCVTSD2SS, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1009, + .Mnemonic = 1040, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -78008,6 +81974,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -78023,12 +81990,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2796 Instruction:"VCVTSD2SS Vss,Hx,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5A /r"/"RVM" + // Pos:2837 Instruction:"VCVTSD2SS Vss,Hx,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5A /r"/"RVM" { .Instruction = ND_INS_VCVTSD2SS, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX, - .Mnemonic = 1009, + .Mnemonic = 1040, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -78037,6 +82004,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -78051,12 +82019,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2797 Instruction:"VCVTSD2USI Gy,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:x 0x79 /r"/"RM" + // Pos:2838 Instruction:"VCVTSD2USI Gy,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:x 0x79 /r"/"RM" { .Instruction = ND_INS_VCVTSD2USI, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1010, + .Mnemonic = 1041, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ER, @@ -78065,6 +82033,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -78078,12 +82047,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2798 Instruction:"VCVTSH2SD Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:0 0x5A /r"/"RAVM" + // Pos:2839 Instruction:"VCVTSH2SD Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:0 0x5A /r"/"RAVM" { .Instruction = ND_INS_VCVTSH2SD, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1011, + .Mnemonic = 1042, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, @@ -78092,6 +82061,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -78107,12 +82077,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2799 Instruction:"VCVTSH2SI Gy,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:x 0x2D /r"/"RM" + // Pos:2840 Instruction:"VCVTSH2SI Gy,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:x 0x2D /r"/"RM" { .Instruction = ND_INS_VCVTSH2SI, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1012, + .Mnemonic = 1043, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ER, @@ -78121,6 +82091,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -78134,12 +82105,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2800 Instruction:"VCVTSH2SS Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:6 p:0 l:i w:0 0x13 /r"/"RAVM" + // Pos:2841 Instruction:"VCVTSH2SS Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:6 p:0 l:i w:0 0x13 /r"/"RAVM" { .Instruction = ND_INS_VCVTSH2SS, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1013, + .Mnemonic = 1044, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, @@ -78148,6 +82119,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -78163,12 +82135,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2801 Instruction:"VCVTSH2USI Gy,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:x 0x79 /r"/"RM" + // Pos:2842 Instruction:"VCVTSH2USI Gy,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:x 0x79 /r"/"RM" { .Instruction = ND_INS_VCVTSH2USI, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1014, + .Mnemonic = 1045, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ER, @@ -78177,6 +82149,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -78190,12 +82163,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2802 Instruction:"VCVTSI2SD Vdq,Hdq,Ey" Encoding:"evex m:1 p:3 l:i w:0 0x2A /r"/"RVM" + // Pos:2843 Instruction:"VCVTSI2SD Vdq,Hdq,Ey" Encoding:"evex m:1 p:3 l:i w:0 0x2A /r"/"RVM" { .Instruction = ND_INS_VCVTSI2SD, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1015, + .Mnemonic = 1046, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -78204,6 +82177,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E10NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -78218,12 +82192,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2803 Instruction:"VCVTSI2SD Vdq,Hdq{er},Ey" Encoding:"evex m:1 p:3 l:i w:1 0x2A /r"/"RVM" + // Pos:2844 Instruction:"VCVTSI2SD Vdq,Hdq{er},Ey" Encoding:"evex m:1 p:3 l:i w:1 0x2A /r"/"RVM" { .Instruction = ND_INS_VCVTSI2SD, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1015, + .Mnemonic = 1046, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ER, @@ -78232,6 +82206,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -78246,12 +82221,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2804 Instruction:"VCVTSI2SD Vsd,Hsd,Ey" Encoding:"vex m:1 p:3 l:i w:x 0x2A /r"/"RVM" + // Pos:2845 Instruction:"VCVTSI2SD Vsd,Hsd,Ey" Encoding:"vex m:1 p:3 l:i w:x 0x2A /r"/"RVM" { .Instruction = ND_INS_VCVTSI2SD, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX, - .Mnemonic = 1015, + .Mnemonic = 1046, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -78260,6 +82235,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -78274,12 +82250,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2805 Instruction:"VCVTSI2SH Vdq,Hdq,Ey" Encoding:"evex m:5 p:2 l:i w:x 0x2A /r"/"RVM" + // Pos:2846 Instruction:"VCVTSI2SH Vdq,Hdq,Ey" Encoding:"evex m:5 p:2 l:i w:x 0x2A /r"/"RVM" { .Instruction = ND_INS_VCVTSI2SH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1016, + .Mnemonic = 1047, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -78288,6 +82264,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_OE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -78302,12 +82279,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2806 Instruction:"VCVTSI2SS Vdq,Hdq{er},Ey" Encoding:"evex m:1 p:2 l:i w:x 0x2A /r"/"RVM" + // Pos:2847 Instruction:"VCVTSI2SS Vdq,Hdq{er},Ey" Encoding:"evex m:1 p:2 l:i w:x 0x2A /r"/"RVM" { .Instruction = ND_INS_VCVTSI2SS, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1017, + .Mnemonic = 1048, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ER, @@ -78316,6 +82293,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -78330,12 +82308,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2807 Instruction:"VCVTSI2SS Vss,Hss,Ey" Encoding:"vex m:1 p:2 l:i w:x 0x2A /r"/"RVM" + // Pos:2848 Instruction:"VCVTSI2SS Vss,Hss,Ey" Encoding:"vex m:1 p:2 l:i w:x 0x2A /r"/"RVM" { .Instruction = ND_INS_VCVTSI2SS, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX, - .Mnemonic = 1017, + .Mnemonic = 1048, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -78344,6 +82322,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -78358,12 +82337,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2808 Instruction:"VCVTSS2SD Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:0 0x5A /r"/"RAVM" + // Pos:2849 Instruction:"VCVTSS2SD Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:0 0x5A /r"/"RAVM" { .Instruction = ND_INS_VCVTSS2SD, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1018, + .Mnemonic = 1049, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, @@ -78372,6 +82351,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -78387,12 +82367,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2809 Instruction:"VCVTSS2SD Vsd,Hx,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5A /r"/"RVM" + // Pos:2850 Instruction:"VCVTSS2SD Vsd,Hx,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5A /r"/"RVM" { .Instruction = ND_INS_VCVTSS2SD, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX, - .Mnemonic = 1018, + .Mnemonic = 1049, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -78401,6 +82381,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -78415,12 +82396,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2810 Instruction:"VCVTSS2SH Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:5 p:0 l:i w:0 0x1D /r"/"RAVM" + // Pos:2851 Instruction:"VCVTSS2SH Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:5 p:0 l:i w:0 0x1D /r"/"RAVM" { .Instruction = ND_INS_VCVTSS2SH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1019, + .Mnemonic = 1050, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -78429,6 +82410,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -78444,12 +82426,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2811 Instruction:"VCVTSS2SI Gy,Wss{er}" Encoding:"evex m:1 p:2 l:i w:x 0x2D /r"/"RM" + // Pos:2852 Instruction:"VCVTSS2SI Gy,Wss{er}" Encoding:"evex m:1 p:2 l:i w:x 0x2D /r"/"RM" { .Instruction = ND_INS_VCVTSS2SI, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1020, + .Mnemonic = 1051, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ER, @@ -78458,6 +82440,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -78471,12 +82454,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2812 Instruction:"VCVTSS2SI Gy,Wss" Encoding:"vex m:1 p:2 l:i w:x 0x2D /r"/"RM" + // Pos:2853 Instruction:"VCVTSS2SI Gy,Wss" Encoding:"vex m:1 p:2 l:i w:x 0x2D /r"/"RM" { .Instruction = ND_INS_VCVTSS2SI, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX, - .Mnemonic = 1020, + .Mnemonic = 1051, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -78485,6 +82468,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -78498,12 +82482,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2813 Instruction:"VCVTSS2USI Gy,Wss{er}" Encoding:"evex m:1 p:2 l:i w:x 0x79 /r"/"RM" + // Pos:2854 Instruction:"VCVTSS2USI Gy,Wss{er}" Encoding:"evex m:1 p:2 l:i w:x 0x79 /r"/"RM" { .Instruction = ND_INS_VCVTSS2USI, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1021, + .Mnemonic = 1052, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ER, @@ -78512,6 +82496,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -78525,12 +82510,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2814 Instruction:"VCVTTNEBF162IBS Vfv{K}{z},aKq,Wfv|B16" Encoding:"evex m:5 p:3 l:x w:0 0x68 /r"/"RAM" + // Pos:2855 Instruction:"VCVTTNEBF162IBS Vfv{K}{z},aKq,Wfv|B16" Encoding:"evex m:5 p:3 l:x w:0 0x68 /r"/"RAM" { .Instruction = ND_INS_VCVTTNEBF162IBS, .Category = ND_CAT_AVX10SCONVERT, .IsaSet = ND_SET_AVX102, - .Mnemonic = 1022, + .Mnemonic = 1053, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -78539,6 +82524,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -78553,12 +82539,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2815 Instruction:"VCVTTNEBF162IUBS Vfv{K}{z},aKq,Wfv|B16" Encoding:"evex m:5 p:3 l:x w:0 0x6A /r"/"RAM" + // Pos:2856 Instruction:"VCVTTNEBF162IUBS Vfv{K}{z},aKq,Wfv|B16" Encoding:"evex m:5 p:3 l:x w:0 0x6A /r"/"RAM" { .Instruction = ND_INS_VCVTTNEBF162IUBS, .Category = ND_CAT_AVX10SCONVERT, .IsaSet = ND_SET_AVX102, - .Mnemonic = 1023, + .Mnemonic = 1054, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -78567,6 +82553,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -78581,12 +82568,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2816 Instruction:"VCVTTPD2DQ Vhv{K}{z},aKq,Wfv|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0xE6 /r"/"RAM" + // Pos:2857 Instruction:"VCVTTPD2DQ Vhv{K}{z},aKq,Wfv|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0xE6 /r"/"RAM" { .Instruction = ND_INS_VCVTTPD2DQ, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1024, + .Mnemonic = 1055, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -78595,6 +82582,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -78609,12 +82597,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2817 Instruction:"VCVTTPD2DQ Vdq,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE6 /r"/"RM" + // Pos:2858 Instruction:"VCVTTPD2DQ Vdq,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE6 /r"/"RM" { .Instruction = ND_INS_VCVTTPD2DQ, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX, - .Mnemonic = 1024, + .Mnemonic = 1055, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -78623,6 +82611,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -78636,12 +82625,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2818 Instruction:"VCVTTPD2DQS Vhv{K}{z},aKq,Wfv|B64{sae}" Encoding:"evex m:5 p:0 l:x w:1 0x6D /r"/"RAM" + // Pos:2859 Instruction:"VCVTTPD2DQS Vhv{K}{z},aKq,Wfv|B64{sae}" Encoding:"evex m:5 p:0 l:x w:1 0x6D /r"/"RAM" { .Instruction = ND_INS_VCVTTPD2DQS, .Category = ND_CAT_AVX10SCONVERT, .IsaSet = ND_SET_AVX102, - .Mnemonic = 1025, + .Mnemonic = 1056, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -78650,6 +82639,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -78664,12 +82654,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2819 Instruction:"VCVTTPD2QQ Vfv{K}{z},aKq,Wfv|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x7A /r"/"RAM" + // Pos:2860 Instruction:"VCVTTPD2QQ Vfv{K}{z},aKq,Wfv|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x7A /r"/"RAM" { .Instruction = ND_INS_VCVTTPD2QQ, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 1026, + .Mnemonic = 1057, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -78678,6 +82668,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -78692,12 +82683,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2820 Instruction:"VCVTTPD2QQS Vfv{K}{z},aKq,Wfv|B64{sae}" Encoding:"evex m:5 p:1 l:x w:1 0x6D /r"/"RAM" + // Pos:2861 Instruction:"VCVTTPD2QQS Vfv{K}{z},aKq,Wfv|B64{sae}" Encoding:"evex m:5 p:1 l:x w:1 0x6D /r"/"RAM" { .Instruction = ND_INS_VCVTTPD2QQS, .Category = ND_CAT_AVX10SCONVERT, .IsaSet = ND_SET_AVX102, - .Mnemonic = 1027, + .Mnemonic = 1058, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -78706,6 +82697,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -78720,12 +82712,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2821 Instruction:"VCVTTPD2UDQ Vhv{K}{z},aKq,Wfv|B64{sae}" Encoding:"evex m:1 p:0 l:x w:1 0x78 /r"/"RAM" + // Pos:2862 Instruction:"VCVTTPD2UDQ Vhv{K}{z},aKq,Wfv|B64{sae}" Encoding:"evex m:1 p:0 l:x w:1 0x78 /r"/"RAM" { .Instruction = ND_INS_VCVTTPD2UDQ, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1028, + .Mnemonic = 1059, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -78734,6 +82726,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -78748,12 +82741,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2822 Instruction:"VCVTTPD2UDQS Vhv{K}{z},aKq,Wfv|B64{sae}" Encoding:"evex m:5 p:0 l:x w:1 0x6C /r"/"RAM" + // Pos:2863 Instruction:"VCVTTPD2UDQS Vhv{K}{z},aKq,Wfv|B64{sae}" Encoding:"evex m:5 p:0 l:x w:1 0x6C /r"/"RAM" { .Instruction = ND_INS_VCVTTPD2UDQS, .Category = ND_CAT_AVX10SCONVERT, .IsaSet = ND_SET_AVX102, - .Mnemonic = 1029, + .Mnemonic = 1060, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -78762,6 +82755,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -78776,12 +82770,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2823 Instruction:"VCVTTPD2UQQ Vfv{K}{z},aKq,Wfv|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x78 /r"/"RAM" + // Pos:2864 Instruction:"VCVTTPD2UQQ Vfv{K}{z},aKq,Wfv|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x78 /r"/"RAM" { .Instruction = ND_INS_VCVTTPD2UQQ, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 1030, + .Mnemonic = 1061, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -78790,6 +82784,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -78804,12 +82799,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2824 Instruction:"VCVTTPD2UQQS Vfv{K}{z},aKq,Wfv|B64{sae}" Encoding:"evex m:5 p:1 l:x w:1 0x6C /r"/"RAM" + // Pos:2865 Instruction:"VCVTTPD2UQQS Vfv{K}{z},aKq,Wfv|B64{sae}" Encoding:"evex m:5 p:1 l:x w:1 0x6C /r"/"RAM" { .Instruction = ND_INS_VCVTTPD2UQQS, .Category = ND_CAT_AVX10SCONVERT, .IsaSet = ND_SET_AVX102, - .Mnemonic = 1031, + .Mnemonic = 1062, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -78818,6 +82813,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -78832,12 +82828,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2825 Instruction:"VCVTTPH2DQ Vfv{K}{z},aKq,Whv|B16{sae}" Encoding:"evex m:5 p:2 l:x w:0 0x5B /r"/"RAM" + // Pos:2866 Instruction:"VCVTTPH2DQ Vfv{K}{z},aKq,Whv|B16{sae}" Encoding:"evex m:5 p:2 l:x w:0 0x5B /r"/"RAM" { .Instruction = ND_INS_VCVTTPH2DQ, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1032, + .Mnemonic = 1063, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -78846,6 +82842,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -78860,12 +82857,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2826 Instruction:"VCVTTPH2IBS Vfv{K}{z},aKq,Wfv|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x68 /r"/"RAM" + // Pos:2867 Instruction:"VCVTTPH2IBS Vfv{K}{z},aKq,Wfv|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x68 /r"/"RAM" { .Instruction = ND_INS_VCVTTPH2IBS, .Category = ND_CAT_AVX10SCONVERT, .IsaSet = ND_SET_AVX102, - .Mnemonic = 1033, + .Mnemonic = 1064, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -78874,6 +82871,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -78888,12 +82886,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2827 Instruction:"VCVTTPH2IUBS Vfv{K}{z},aKq,Wfv|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x6A /r"/"RAM" + // Pos:2868 Instruction:"VCVTTPH2IUBS Vfv{K}{z},aKq,Wfv|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x6A /r"/"RAM" { .Instruction = ND_INS_VCVTTPH2IUBS, .Category = ND_CAT_AVX10SCONVERT, .IsaSet = ND_SET_AVX102, - .Mnemonic = 1034, + .Mnemonic = 1065, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -78902,6 +82900,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -78916,12 +82915,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2828 Instruction:"VCVTTPH2QQ Vfv{K}{z},aKq,Wqv|B16{sae}" Encoding:"evex m:5 p:1 l:x w:0 0x7A /r"/"RAM" + // Pos:2869 Instruction:"VCVTTPH2QQ Vfv{K}{z},aKq,Wqv|B16{sae}" Encoding:"evex m:5 p:1 l:x w:0 0x7A /r"/"RAM" { .Instruction = ND_INS_VCVTTPH2QQ, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1035, + .Mnemonic = 1066, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -78930,6 +82929,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -78944,12 +82944,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2829 Instruction:"VCVTTPH2UDQ Vfv{K}{z},aKq,Whv|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x78 /r"/"RAM" + // Pos:2870 Instruction:"VCVTTPH2UDQ Vfv{K}{z},aKq,Whv|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x78 /r"/"RAM" { .Instruction = ND_INS_VCVTTPH2UDQ, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1036, + .Mnemonic = 1067, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -78958,6 +82958,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -78972,12 +82973,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2830 Instruction:"VCVTTPH2UQQ Vfv{K}{z},aKq,Wqv|B16{sae}" Encoding:"evex m:5 p:1 l:x w:0 0x78 /r"/"RAM" + // Pos:2871 Instruction:"VCVTTPH2UQQ Vfv{K}{z},aKq,Wqv|B16{sae}" Encoding:"evex m:5 p:1 l:x w:0 0x78 /r"/"RAM" { .Instruction = ND_INS_VCVTTPH2UQQ, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1037, + .Mnemonic = 1068, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -78986,6 +82987,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -79000,12 +83002,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2831 Instruction:"VCVTTPH2UW Vfv{K}{z},aKq,Wfv|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x7C /r"/"RAM" + // Pos:2872 Instruction:"VCVTTPH2UW Vfv{K}{z},aKq,Wfv|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x7C /r"/"RAM" { .Instruction = ND_INS_VCVTTPH2UW, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1038, + .Mnemonic = 1069, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -79014,6 +83016,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -79028,12 +83031,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2832 Instruction:"VCVTTPH2W Vfv{K}{z},aKq,Wfv|B16{sae}" Encoding:"evex m:5 p:1 l:x w:0 0x7C /r"/"RAM" + // Pos:2873 Instruction:"VCVTTPH2W Vfv{K}{z},aKq,Wfv|B16{sae}" Encoding:"evex m:5 p:1 l:x w:0 0x7C /r"/"RAM" { .Instruction = ND_INS_VCVTTPH2W, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1039, + .Mnemonic = 1070, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -79042,6 +83045,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -79056,12 +83060,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2833 Instruction:"VCVTTPS2DQ Vfv{K}{z},aKq,Wfv|B32{sae}" Encoding:"evex m:1 p:2 l:x w:0 0x5B /r"/"RAM" + // Pos:2874 Instruction:"VCVTTPS2DQ Vfv{K}{z},aKq,Wfv|B32{sae}" Encoding:"evex m:1 p:2 l:x w:0 0x5B /r"/"RAM" { .Instruction = ND_INS_VCVTTPS2DQ, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1040, + .Mnemonic = 1071, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -79070,6 +83074,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -79084,12 +83089,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2834 Instruction:"VCVTTPS2DQ Vps,Wps" Encoding:"vex m:1 p:2 l:x w:i 0x5B /r"/"RM" + // Pos:2875 Instruction:"VCVTTPS2DQ Vps,Wps" Encoding:"vex m:1 p:2 l:x w:i 0x5B /r"/"RM" { .Instruction = ND_INS_VCVTTPS2DQ, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX, - .Mnemonic = 1040, + .Mnemonic = 1071, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -79098,6 +83103,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -79111,12 +83117,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2835 Instruction:"VCVTTPS2DQS Vfv{K}{z},aKq,Wfv|B32{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x6D /r"/"RAM" + // Pos:2876 Instruction:"VCVTTPS2DQS Vfv{K}{z},aKq,Wfv|B32{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x6D /r"/"RAM" { .Instruction = ND_INS_VCVTTPS2DQS, .Category = ND_CAT_AVX10SCONVERT, .IsaSet = ND_SET_AVX102, - .Mnemonic = 1041, + .Mnemonic = 1072, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -79125,6 +83131,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -79139,12 +83146,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2836 Instruction:"VCVTTPS2IBS Vfv{K}{z},aKq,Wfv|B32{sae}" Encoding:"evex m:5 p:1 l:x w:0 0x68 /r"/"RAM" + // Pos:2877 Instruction:"VCVTTPS2IBS Vfv{K}{z},aKq,Wfv|B32{sae}" Encoding:"evex m:5 p:1 l:x w:0 0x68 /r"/"RAM" { .Instruction = ND_INS_VCVTTPS2IBS, .Category = ND_CAT_AVX10SCONVERT, .IsaSet = ND_SET_AVX102, - .Mnemonic = 1042, + .Mnemonic = 1073, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -79153,6 +83160,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -79167,12 +83175,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2837 Instruction:"VCVTTPS2IUBS Vfv{K}{z},aKq,Wfv|B32{sae}" Encoding:"evex m:5 p:1 l:x w:0 0x6A /r"/"RAM" + // Pos:2878 Instruction:"VCVTTPS2IUBS Vfv{K}{z},aKq,Wfv|B32{sae}" Encoding:"evex m:5 p:1 l:x w:0 0x6A /r"/"RAM" { .Instruction = ND_INS_VCVTTPS2IUBS, .Category = ND_CAT_AVX10SCONVERT, .IsaSet = ND_SET_AVX102, - .Mnemonic = 1043, + .Mnemonic = 1074, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -79181,6 +83189,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -79195,12 +83204,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2838 Instruction:"VCVTTPS2QQ Vfv{K}{z},aKq,Whv|B32{sae}" Encoding:"evex m:1 p:1 l:x w:0 0x7A /r"/"RAM" + // Pos:2879 Instruction:"VCVTTPS2QQ Vfv{K}{z},aKq,Whv|B32{sae}" Encoding:"evex m:1 p:1 l:x w:0 0x7A /r"/"RAM" { .Instruction = ND_INS_VCVTTPS2QQ, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 1044, + .Mnemonic = 1075, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -79209,6 +83218,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -79223,12 +83233,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2839 Instruction:"VCVTTPS2QQS Vfv{K}{z},aKq,Whv|B32{sae}" Encoding:"evex m:5 p:1 l:x w:0 0x6D /r"/"RAM" + // Pos:2880 Instruction:"VCVTTPS2QQS Vfv{K}{z},aKq,Whv|B32{sae}" Encoding:"evex m:5 p:1 l:x w:0 0x6D /r"/"RAM" { .Instruction = ND_INS_VCVTTPS2QQS, .Category = ND_CAT_AVX10SCONVERT, .IsaSet = ND_SET_AVX102, - .Mnemonic = 1045, + .Mnemonic = 1076, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -79237,6 +83247,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -79251,12 +83262,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2840 Instruction:"VCVTTPS2UDQ Vfv{K}{z},aKq,Wfv|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x78 /r"/"RAM" + // Pos:2881 Instruction:"VCVTTPS2UDQ Vfv{K}{z},aKq,Wfv|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x78 /r"/"RAM" { .Instruction = ND_INS_VCVTTPS2UDQ, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1046, + .Mnemonic = 1077, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -79265,6 +83276,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -79279,12 +83291,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2841 Instruction:"VCVTTPS2UDQS Vfv{K}{z},aKq,Wfv|B32{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x6C /r"/"RAM" + // Pos:2882 Instruction:"VCVTTPS2UDQS Vfv{K}{z},aKq,Wfv|B32{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x6C /r"/"RAM" { .Instruction = ND_INS_VCVTTPS2UDQS, .Category = ND_CAT_AVX10SCONVERT, .IsaSet = ND_SET_AVX102, - .Mnemonic = 1047, + .Mnemonic = 1078, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -79293,6 +83305,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -79307,12 +83320,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2842 Instruction:"VCVTTPS2UQQ Vfv{K}{z},aKq,Whv|B32{sae}" Encoding:"evex m:1 p:1 l:x w:0 0x78 /r"/"RAM" + // Pos:2883 Instruction:"VCVTTPS2UQQ Vfv{K}{z},aKq,Whv|B32{sae}" Encoding:"evex m:1 p:1 l:x w:0 0x78 /r"/"RAM" { .Instruction = ND_INS_VCVTTPS2UQQ, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 1048, + .Mnemonic = 1079, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -79321,6 +83334,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -79335,12 +83349,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2843 Instruction:"VCVTTPS2UQQS Vfv{K}{z},aKq,Whv|B32{sae}" Encoding:"evex m:5 p:1 l:x w:0 0x6C /r"/"RAM" + // Pos:2884 Instruction:"VCVTTPS2UQQS Vfv{K}{z},aKq,Whv|B32{sae}" Encoding:"evex m:5 p:1 l:x w:0 0x6C /r"/"RAM" { .Instruction = ND_INS_VCVTTPS2UQQS, .Category = ND_CAT_AVX10SCONVERT, .IsaSet = ND_SET_AVX102, - .Mnemonic = 1049, + .Mnemonic = 1080, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -79349,6 +83363,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -79363,12 +83378,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2844 Instruction:"VCVTTSD2SI Gy,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:x 0x2C /r"/"RM" + // Pos:2885 Instruction:"VCVTTSD2SI Gy,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:x 0x2C /r"/"RM" { .Instruction = ND_INS_VCVTTSD2SI, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1050, + .Mnemonic = 1081, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_SAE, @@ -79377,6 +83392,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -79390,12 +83406,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2845 Instruction:"VCVTTSD2SI Gy,Wsd" Encoding:"vex m:1 p:3 l:i w:x 0x2C /r"/"RM" + // Pos:2886 Instruction:"VCVTTSD2SI Gy,Wsd" Encoding:"vex m:1 p:3 l:i w:x 0x2C /r"/"RM" { .Instruction = ND_INS_VCVTTSD2SI, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX, - .Mnemonic = 1050, + .Mnemonic = 1081, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -79404,6 +83420,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -79417,12 +83434,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2846 Instruction:"VCVTTSD2SIS Gy,Wsd{sae}" Encoding:"evex m:5 p:3 l:i w:x 0x6D /r"/"RM" + // Pos:2887 Instruction:"VCVTTSD2SIS Gy,Wsd{sae}" Encoding:"evex m:5 p:3 l:i w:x 0x6D /r"/"RM" { .Instruction = ND_INS_VCVTTSD2SIS, .Category = ND_CAT_AVX10SCONVERT, .IsaSet = ND_SET_AVX102, - .Mnemonic = 1051, + .Mnemonic = 1082, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_SAE, @@ -79431,6 +83448,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -79444,12 +83462,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2847 Instruction:"VCVTTSD2USI Gy,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:x 0x78 /r"/"RM" + // Pos:2888 Instruction:"VCVTTSD2USI Gy,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:x 0x78 /r"/"RM" { .Instruction = ND_INS_VCVTTSD2USI, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1052, + .Mnemonic = 1083, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_SAE, @@ -79458,6 +83476,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -79471,12 +83490,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2848 Instruction:"VCVTTSD2USIS Gy,Wsd{sae}" Encoding:"evex m:5 p:3 l:i w:x 0x6C /r"/"RM" + // Pos:2889 Instruction:"VCVTTSD2USIS Gy,Wsd{sae}" Encoding:"evex m:5 p:3 l:i w:x 0x6C /r"/"RM" { .Instruction = ND_INS_VCVTTSD2USIS, .Category = ND_CAT_AVX10SCONVERT, .IsaSet = ND_SET_AVX102, - .Mnemonic = 1053, + .Mnemonic = 1084, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_SAE, @@ -79485,6 +83504,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -79498,12 +83518,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2849 Instruction:"VCVTTSH2SI Gy,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:x 0x2C /r"/"RM" + // Pos:2890 Instruction:"VCVTTSH2SI Gy,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:x 0x2C /r"/"RM" { .Instruction = ND_INS_VCVTTSH2SI, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1054, + .Mnemonic = 1085, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_SAE, @@ -79512,6 +83532,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -79525,12 +83546,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2850 Instruction:"VCVTTSH2USI Gy,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:0 0x78 /r"/"RM" + // Pos:2891 Instruction:"VCVTTSH2USI Gy,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:0 0x78 /r"/"RM" { .Instruction = ND_INS_VCVTTSH2USI, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1055, + .Mnemonic = 1086, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_SAE, @@ -79539,6 +83560,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -79552,12 +83574,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2851 Instruction:"VCVTTSS2SI Gy,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:x 0x2C /r"/"RM" + // Pos:2892 Instruction:"VCVTTSS2SI Gy,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:x 0x2C /r"/"RM" { .Instruction = ND_INS_VCVTTSS2SI, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1056, + .Mnemonic = 1087, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_SAE, @@ -79566,6 +83588,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -79579,12 +83602,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2852 Instruction:"VCVTTSS2SI Gy,Wss" Encoding:"vex m:1 p:2 l:i w:x 0x2C /r"/"RM" + // Pos:2893 Instruction:"VCVTTSS2SI Gy,Wss" Encoding:"vex m:1 p:2 l:i w:x 0x2C /r"/"RM" { .Instruction = ND_INS_VCVTTSS2SI, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX, - .Mnemonic = 1056, + .Mnemonic = 1087, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -79593,6 +83616,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -79606,12 +83630,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2853 Instruction:"VCVTTSS2SIS Gy,Wss{sae}" Encoding:"evex m:5 p:2 l:i w:x 0x6D /r"/"RM" + // Pos:2894 Instruction:"VCVTTSS2SIS Gy,Wss{sae}" Encoding:"evex m:5 p:2 l:i w:x 0x6D /r"/"RM" { .Instruction = ND_INS_VCVTTSS2SIS, .Category = ND_CAT_AVX10SCONVERT, .IsaSet = ND_SET_AVX102, - .Mnemonic = 1057, + .Mnemonic = 1088, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_SAE, @@ -79620,6 +83644,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -79633,12 +83658,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2854 Instruction:"VCVTTSS2USI Gy,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:x 0x78 /r"/"RM" + // Pos:2895 Instruction:"VCVTTSS2USI Gy,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:x 0x78 /r"/"RM" { .Instruction = ND_INS_VCVTTSS2USI, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1058, + .Mnemonic = 1089, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_SAE, @@ -79647,6 +83672,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -79660,12 +83686,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2855 Instruction:"VCVTTSS2USIS Gy,Wss{sae}" Encoding:"evex m:5 p:2 l:i w:x 0x6C /r"/"RM" + // Pos:2896 Instruction:"VCVTTSS2USIS Gy,Wss{sae}" Encoding:"evex m:5 p:2 l:i w:x 0x6C /r"/"RM" { .Instruction = ND_INS_VCVTTSS2USIS, .Category = ND_CAT_AVX10SCONVERT, .IsaSet = ND_SET_AVX102, - .Mnemonic = 1059, + .Mnemonic = 1090, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_SAE, @@ -79674,6 +83700,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -79687,12 +83714,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2856 Instruction:"VCVTUDQ2PD Vfv{K}{z},aKq,Whv|B32" Encoding:"evex m:1 p:2 l:x w:0 0x7A /r"/"RAM" + // Pos:2897 Instruction:"VCVTUDQ2PD Vfv{K}{z},aKq,Whv|B32" Encoding:"evex m:1 p:2 l:x w:0 0x7A /r"/"RAM" { .Instruction = ND_INS_VCVTUDQ2PD, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1060, + .Mnemonic = 1091, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -79701,6 +83728,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -79715,12 +83743,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2857 Instruction:"VCVTUDQ2PH Vhv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:5 p:3 l:x w:0 0x7A /r"/"RAM" + // Pos:2898 Instruction:"VCVTUDQ2PH Vhv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:5 p:3 l:x w:0 0x7A /r"/"RAM" { .Instruction = ND_INS_VCVTUDQ2PH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1061, + .Mnemonic = 1092, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -79729,6 +83757,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_PE|ND_SIMD_EXC_OE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -79743,12 +83772,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2858 Instruction:"VCVTUDQ2PS Vfv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:1 p:3 l:x w:0 0x7A /r"/"RAM" + // Pos:2899 Instruction:"VCVTUDQ2PS Vfv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:1 p:3 l:x w:0 0x7A /r"/"RAM" { .Instruction = ND_INS_VCVTUDQ2PS, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1062, + .Mnemonic = 1093, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -79757,6 +83786,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -79771,12 +83801,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2859 Instruction:"VCVTUQQ2PD Vfv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:2 l:x w:1 0x7A /r"/"RAM" + // Pos:2900 Instruction:"VCVTUQQ2PD Vfv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:2 l:x w:1 0x7A /r"/"RAM" { .Instruction = ND_INS_VCVTUQQ2PD, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 1063, + .Mnemonic = 1094, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -79785,6 +83815,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -79799,12 +83830,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2860 Instruction:"VCVTUQQ2PH Vqv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:5 p:3 l:x w:1 0x7A /r"/"RAM" + // Pos:2901 Instruction:"VCVTUQQ2PH Vqv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:5 p:3 l:x w:1 0x7A /r"/"RAM" { .Instruction = ND_INS_VCVTUQQ2PH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1064, + .Mnemonic = 1095, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -79813,6 +83844,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_PE|ND_SIMD_EXC_OE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -79827,12 +83859,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2861 Instruction:"VCVTUQQ2PS Vhv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:3 l:x w:1 0x7A /r"/"RAM" + // Pos:2902 Instruction:"VCVTUQQ2PS Vhv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:3 l:x w:1 0x7A /r"/"RAM" { .Instruction = ND_INS_VCVTUQQ2PS, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 1065, + .Mnemonic = 1096, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -79841,6 +83873,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -79855,12 +83888,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2862 Instruction:"VCVTUSI2SD Vdq,Hdq,Ey" Encoding:"evex m:1 p:3 l:i w:0 0x7B /r"/"RVM" + // Pos:2903 Instruction:"VCVTUSI2SD Vdq,Hdq,Ey" Encoding:"evex m:1 p:3 l:i w:0 0x7B /r"/"RVM" { .Instruction = ND_INS_VCVTUSI2SD, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1066, + .Mnemonic = 1097, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -79869,6 +83902,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E10NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -79883,12 +83917,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2863 Instruction:"VCVTUSI2SD Vdq,Hdq{er},Ey" Encoding:"evex m:1 p:3 l:i w:1 0x7B /r"/"RVM" + // Pos:2904 Instruction:"VCVTUSI2SD Vdq,Hdq{er},Ey" Encoding:"evex m:1 p:3 l:i w:1 0x7B /r"/"RVM" { .Instruction = ND_INS_VCVTUSI2SD, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1066, + .Mnemonic = 1097, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ER, @@ -79897,6 +83931,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -79911,12 +83946,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2864 Instruction:"VCVTUSI2SH Vdq,Hdq,Ey{er}" Encoding:"evex m:5 p:2 l:i w:x 0x7B /r"/"RVM" + // Pos:2905 Instruction:"VCVTUSI2SH Vdq,Hdq,Ey{er}" Encoding:"evex m:5 p:2 l:i w:x 0x7B /r"/"RVM" { .Instruction = ND_INS_VCVTUSI2SH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1067, + .Mnemonic = 1098, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ER, @@ -79925,6 +83960,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -79939,12 +83975,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2865 Instruction:"VCVTUSI2SS Vss,Hss{er},Ey" Encoding:"evex m:1 p:2 l:i w:x 0x7B /r"/"RVM" + // Pos:2906 Instruction:"VCVTUSI2SS Vss,Hss{er},Ey" Encoding:"evex m:1 p:2 l:i w:x 0x7B /r"/"RVM" { .Instruction = ND_INS_VCVTUSI2SS, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1068, + .Mnemonic = 1099, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ER, @@ -79953,6 +83989,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -79967,12 +84004,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2866 Instruction:"VCVTUW2PH Vfv{K}{z},aKq,Wfv|B16{er}" Encoding:"evex m:5 p:3 l:x w:0 0x7D /r"/"RAM" + // Pos:2907 Instruction:"VCVTUW2PH Vfv{K}{z},aKq,Wfv|B16{er}" Encoding:"evex m:5 p:3 l:x w:0 0x7D /r"/"RAM" { .Instruction = ND_INS_VCVTUW2PH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1069, + .Mnemonic = 1100, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -79981,6 +84018,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_PE|ND_SIMD_EXC_OE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -79995,12 +84033,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2867 Instruction:"VCVTW2PH Vfv{K}{z},aKq,Wfv|B16{er}" Encoding:"evex m:5 p:2 l:x w:0 0x7D /r"/"RAM" + // Pos:2908 Instruction:"VCVTW2PH Vfv{K}{z},aKq,Wfv|B16{er}" Encoding:"evex m:5 p:2 l:x w:0 0x7D /r"/"RAM" { .Instruction = ND_INS_VCVTW2PH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1070, + .Mnemonic = 1101, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -80009,6 +84047,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -80023,12 +84062,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2868 Instruction:"VDBPSADBW Vfv{K}{z},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x42 /r ib"/"RAVMI" + // Pos:2909 Instruction:"VDBPSADBW Vfv{K}{z},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x42 /r ib"/"RAVMI" { .Instruction = ND_INS_VDBPSADBW, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1071, + .Mnemonic = 1102, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -80037,6 +84076,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NFnb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -80053,12 +84093,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2869 Instruction:"VDIVNEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:5 p:1 l:x w:0 0x5E /r"/"RAVM" + // Pos:2910 Instruction:"VDIVNEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:5 p:1 l:x w:0 0x5E /r"/"RAVM" { .Instruction = ND_INS_VDIVNEPBF16, .Category = ND_CAT_AVX10BF16, .IsaSet = ND_SET_AVX102, - .Mnemonic = 1072, + .Mnemonic = 1103, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -80067,6 +84107,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -80082,12 +84123,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2870 Instruction:"VDIVPD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x5E /r"/"RAVM" + // Pos:2911 Instruction:"VDIVPD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x5E /r"/"RAVM" { .Instruction = ND_INS_VDIVPD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1073, + .Mnemonic = 1104, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -80096,6 +84137,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE|ND_SIMD_EXC_ZE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -80111,12 +84153,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2871 Instruction:"VDIVPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5E /r"/"RVM" + // Pos:2912 Instruction:"VDIVPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5E /r"/"RVM" { .Instruction = ND_INS_VDIVPD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1073, + .Mnemonic = 1104, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -80125,6 +84167,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE|ND_SIMD_EXC_ZE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -80139,12 +84182,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2872 Instruction:"VDIVPH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x5E /r"/"RAVM" + // Pos:2913 Instruction:"VDIVPH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x5E /r"/"RAVM" { .Instruction = ND_INS_VDIVPH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1074, + .Mnemonic = 1105, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -80153,6 +84196,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE|ND_SIMD_EXC_ZE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -80168,12 +84212,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2873 Instruction:"VDIVPS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x5E /r"/"RAVM" + // Pos:2914 Instruction:"VDIVPS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x5E /r"/"RAVM" { .Instruction = ND_INS_VDIVPS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1075, + .Mnemonic = 1106, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -80182,6 +84226,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE|ND_SIMD_EXC_ZE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -80197,12 +84242,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2874 Instruction:"VDIVPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5E /r"/"RVM" + // Pos:2915 Instruction:"VDIVPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5E /r"/"RVM" { .Instruction = ND_INS_VDIVPS, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1075, + .Mnemonic = 1106, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -80211,6 +84256,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE|ND_SIMD_EXC_ZE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -80225,12 +84271,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2875 Instruction:"VDIVSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x5E /r"/"RAVM" + // Pos:2916 Instruction:"VDIVSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x5E /r"/"RAVM" { .Instruction = ND_INS_VDIVSD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1076, + .Mnemonic = 1107, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -80239,6 +84285,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE|ND_SIMD_EXC_ZE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -80254,12 +84301,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2876 Instruction:"VDIVSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5E /r"/"RVM" + // Pos:2917 Instruction:"VDIVSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5E /r"/"RVM" { .Instruction = ND_INS_VDIVSD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1076, + .Mnemonic = 1107, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -80268,6 +84315,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE|ND_SIMD_EXC_ZE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -80282,12 +84330,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2877 Instruction:"VDIVSH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:0 0x5E /r"/"RAVM" + // Pos:2918 Instruction:"VDIVSH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:0 0x5E /r"/"RAVM" { .Instruction = ND_INS_VDIVSH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1077, + .Mnemonic = 1108, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -80296,6 +84344,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE|ND_SIMD_EXC_ZE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -80311,12 +84360,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2878 Instruction:"VDIVSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x5E /r"/"RAVM" + // Pos:2919 Instruction:"VDIVSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x5E /r"/"RAVM" { .Instruction = ND_INS_VDIVSS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1078, + .Mnemonic = 1109, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -80325,6 +84374,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE|ND_SIMD_EXC_ZE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -80340,12 +84390,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2879 Instruction:"VDIVSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5E /r"/"RVM" + // Pos:2920 Instruction:"VDIVSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5E /r"/"RVM" { .Instruction = ND_INS_VDIVSS, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1078, + .Mnemonic = 1109, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -80354,6 +84404,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE|ND_SIMD_EXC_ZE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -80368,12 +84419,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2880 Instruction:"VDPBF16PS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:2 l:x w:0 0x52 /r"/"RAVM" + // Pos:2921 Instruction:"VDPBF16PS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:2 l:x w:0 0x52 /r"/"RAVM" { .Instruction = ND_INS_VDPBF16PS, .Category = ND_CAT_AVX512BF16, .IsaSet = ND_SET_AVX512BF16, - .Mnemonic = 1079, + .Mnemonic = 1110, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -80382,6 +84433,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -80397,12 +84449,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2881 Instruction:"VDPPD Vdq,Hdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x41 /r ib"/"RVMI" + // Pos:2922 Instruction:"VDPPD Vdq,Hdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x41 /r ib"/"RVMI" { .Instruction = ND_INS_VDPPD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1080, + .Mnemonic = 1111, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -80411,6 +84463,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -80426,12 +84479,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2882 Instruction:"VDPPHPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:0 l:x w:0 0x52 /r"/"RAVM" + // Pos:2923 Instruction:"VDPPHPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:0 l:x w:0 0x52 /r"/"RAVM" { .Instruction = ND_INS_VDPPHPS, .Category = ND_CAT_AVX10INT, .IsaSet = ND_SET_AVX102, - .Mnemonic = 1081, + .Mnemonic = 1112, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -80440,6 +84493,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -80455,12 +84509,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2883 Instruction:"VDPPS Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x40 /r ib"/"RVMI" + // Pos:2924 Instruction:"VDPPS Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x40 /r ib"/"RVMI" { .Instruction = ND_INS_VDPPS, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1082, + .Mnemonic = 1113, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -80469,6 +84523,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -80484,12 +84539,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2884 Instruction:"VERR Ew" Encoding:"0x0F 0x00 /4"/"M" + // Pos:2925 Instruction:"VERR Ew" Encoding:"0x0F 0x00 /4"/"M" { .Instruction = ND_INS_VERR, .Category = ND_CAT_SYSTEM, .IsaSet = ND_SET_I286PROT, - .Mnemonic = 1083, + .Mnemonic = 1114, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -80498,6 +84553,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_ZF, .SetFlags = 0, @@ -80511,12 +84567,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2885 Instruction:"VERW Ew" Encoding:"0x0F 0x00 /5"/"M" + // Pos:2926 Instruction:"VERW Ew" Encoding:"0x0F 0x00 /5"/"M" { .Instruction = ND_INS_VERW, .Category = ND_CAT_SYSTEM, .IsaSet = ND_SET_I286PROT, - .Mnemonic = 1084, + .Mnemonic = 1115, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -80525,6 +84581,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_ZF, .SetFlags = 0, @@ -80538,12 +84595,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2886 Instruction:"VEXP2PD Voq{K}{z},aKq,Woq|B64{sae}" Encoding:"evex m:2 p:1 l:2 w:1 0xC8 /r"/"RAM" + // Pos:2927 Instruction:"VEXP2PD Voq{K}{z},aKq,Woq|B64{sae}" Encoding:"evex m:2 p:1 l:2 w:1 0xC8 /r"/"RAM" { .Instruction = ND_INS_VEXP2PD, .Category = ND_CAT_KNL, .IsaSet = ND_SET_AVX512ER, - .Mnemonic = 1085, + .Mnemonic = 1116, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -80552,6 +84609,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -80566,12 +84624,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2887 Instruction:"VEXP2PS Voq{K}{z},aKq,Woq|B32{sae}" Encoding:"evex m:2 p:1 l:2 w:0 0xC8 /r"/"RAM" + // Pos:2928 Instruction:"VEXP2PS Voq{K}{z},aKq,Woq|B32{sae}" Encoding:"evex m:2 p:1 l:2 w:0 0xC8 /r"/"RAM" { .Instruction = ND_INS_VEXP2PS, .Category = ND_CAT_KNL, .IsaSet = ND_SET_AVX512ER, - .Mnemonic = 1086, + .Mnemonic = 1117, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -80580,6 +84638,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -80594,12 +84653,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2888 Instruction:"VEXPANDPD Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x88 /r"/"RAM" + // Pos:2929 Instruction:"VEXPANDPD Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x88 /r"/"RAM" { .Instruction = ND_INS_VEXPANDPD, .Category = ND_CAT_EXPAND, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1087, + .Mnemonic = 1118, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -80608,6 +84667,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4nb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -80622,12 +84682,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2889 Instruction:"VEXPANDPS Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x88 /r"/"RAM" + // Pos:2930 Instruction:"VEXPANDPS Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x88 /r"/"RAM" { .Instruction = ND_INS_VEXPANDPS, .Category = ND_CAT_EXPAND, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1088, + .Mnemonic = 1119, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -80636,6 +84696,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4nb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -80650,12 +84711,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2890 Instruction:"VEXTRACTF128 Wdq,Vqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x19 /r ib"/"MRI" + // Pos:2931 Instruction:"VEXTRACTF128 Wdq,Vqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x19 /r ib"/"MRI" { .Instruction = ND_INS_VEXTRACTF128, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1089, + .Mnemonic = 1120, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -80664,6 +84725,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_6, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -80678,12 +84740,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2891 Instruction:"VEXTRACTF32X4 Wdq{K}{z},aKq,Vuv,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x19 /r ib"/"MARI" + // Pos:2932 Instruction:"VEXTRACTF32X4 Wdq{K}{z},aKq,Vuv,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x19 /r ib"/"MARI" { .Instruction = ND_INS_VEXTRACTF32X4, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1090, + .Mnemonic = 1121, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -80692,6 +84754,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E6NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -80707,12 +84770,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2892 Instruction:"VEXTRACTF32X8 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x1B /r ib"/"MARI" + // Pos:2933 Instruction:"VEXTRACTF32X8 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x1B /r ib"/"MARI" { .Instruction = ND_INS_VEXTRACTF32X8, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 1091, + .Mnemonic = 1122, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -80721,6 +84784,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E6NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -80736,12 +84800,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2893 Instruction:"VEXTRACTF64X2 Wdq{K}{z},aKq,Vuv,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x19 /r ib"/"MARI" + // Pos:2934 Instruction:"VEXTRACTF64X2 Wdq{K}{z},aKq,Vuv,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x19 /r ib"/"MARI" { .Instruction = ND_INS_VEXTRACTF64X2, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 1092, + .Mnemonic = 1123, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -80750,6 +84814,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E6NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -80765,12 +84830,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2894 Instruction:"VEXTRACTF64X4 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x1B /r ib"/"MARI" + // Pos:2935 Instruction:"VEXTRACTF64X4 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x1B /r ib"/"MARI" { .Instruction = ND_INS_VEXTRACTF64X4, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1093, + .Mnemonic = 1124, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -80779,6 +84844,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E6NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -80794,12 +84860,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2895 Instruction:"VEXTRACTI128 Wdq,Vqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x39 /r ib"/"MRI" + // Pos:2936 Instruction:"VEXTRACTI128 Wdq,Vqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x39 /r ib"/"MRI" { .Instruction = ND_INS_VEXTRACTI128, .Category = ND_CAT_AVX2, .IsaSet = ND_SET_AVX2, - .Mnemonic = 1094, + .Mnemonic = 1125, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -80808,6 +84874,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_6, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -80822,12 +84889,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2896 Instruction:"VEXTRACTI32X4 Wdq{K}{z},aKq,Vuv,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x39 /r ib"/"MARI" + // Pos:2937 Instruction:"VEXTRACTI32X4 Wdq{K}{z},aKq,Vuv,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x39 /r ib"/"MARI" { .Instruction = ND_INS_VEXTRACTI32X4, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1095, + .Mnemonic = 1126, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -80836,6 +84903,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E6NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -80851,12 +84919,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2897 Instruction:"VEXTRACTI32X8 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x3B /r ib"/"MARI" + // Pos:2938 Instruction:"VEXTRACTI32X8 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x3B /r ib"/"MARI" { .Instruction = ND_INS_VEXTRACTI32X8, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 1096, + .Mnemonic = 1127, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -80865,6 +84933,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E6NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -80880,12 +84949,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2898 Instruction:"VEXTRACTI64X2 Wdq{K}{z},aKq,Vuv,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x39 /r ib"/"MARI" + // Pos:2939 Instruction:"VEXTRACTI64X2 Wdq{K}{z},aKq,Vuv,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x39 /r ib"/"MARI" { .Instruction = ND_INS_VEXTRACTI64X2, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 1097, + .Mnemonic = 1128, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -80894,6 +84963,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E6NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -80909,12 +84979,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2899 Instruction:"VEXTRACTI64X4 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x3B /r ib"/"MARI" + // Pos:2940 Instruction:"VEXTRACTI64X4 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x3B /r ib"/"MARI" { .Instruction = ND_INS_VEXTRACTI64X4, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1098, + .Mnemonic = 1129, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -80923,6 +84993,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E6NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -80938,12 +85009,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2900 Instruction:"VEXTRACTPS Md,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x17 /r:mem ib"/"MRI" + // Pos:2941 Instruction:"VEXTRACTPS Md,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x17 /r:mem ib"/"MRI" { .Instruction = ND_INS_VEXTRACTPS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1099, + .Mnemonic = 1130, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -80952,6 +85023,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E9NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -80966,12 +85038,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2901 Instruction:"VEXTRACTPS Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x17 /r:reg ib"/"MRI" + // Pos:2942 Instruction:"VEXTRACTPS Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x17 /r:reg ib"/"MRI" { .Instruction = ND_INS_VEXTRACTPS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1099, + .Mnemonic = 1130, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -80980,6 +85052,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E9NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -80994,12 +85067,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2902 Instruction:"VEXTRACTPS Md,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x17 /r:mem ib"/"MRI" + // Pos:2943 Instruction:"VEXTRACTPS Md,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x17 /r:mem ib"/"MRI" { .Instruction = ND_INS_VEXTRACTPS, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1099, + .Mnemonic = 1130, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -81008,6 +85081,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -81022,12 +85096,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2903 Instruction:"VEXTRACTPS Ry,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x17 /r:reg ib"/"MRI" + // Pos:2944 Instruction:"VEXTRACTPS Ry,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x17 /r:reg ib"/"MRI" { .Instruction = ND_INS_VEXTRACTPS, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1099, + .Mnemonic = 1130, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -81036,6 +85110,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -81050,12 +85125,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2904 Instruction:"VFCMADDCPH Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:6 p:3 l:x w:0 0x56 /r"/"RAVM" + // Pos:2945 Instruction:"VFCMADDCPH Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:6 p:3 l:x w:0 0x56 /r"/"RAVM" { .Instruction = ND_INS_VFCMADDCPH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1100, + .Mnemonic = 1131, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -81064,6 +85139,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4S, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -81079,12 +85155,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2905 Instruction:"VFCMADDCSH Vdq{K}{z},aKq,Hdq,Wd{er}" Encoding:"evex m:6 p:3 l:i w:0 0x57 /r"/"RAVM" + // Pos:2946 Instruction:"VFCMADDCSH Vdq{K}{z},aKq,Hdq,Wd{er}" Encoding:"evex m:6 p:3 l:i w:0 0x57 /r"/"RAVM" { .Instruction = ND_INS_VFCMADDCSH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1101, + .Mnemonic = 1132, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -81093,6 +85169,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E10S, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -81108,12 +85185,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2906 Instruction:"VFCMULCPH Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:6 p:3 l:x w:0 0xD6 /r"/"RAVM" + // Pos:2947 Instruction:"VFCMULCPH Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:6 p:3 l:x w:0 0xD6 /r"/"RAVM" { .Instruction = ND_INS_VFCMULCPH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1102, + .Mnemonic = 1133, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -81122,6 +85199,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4S, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -81137,12 +85215,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2907 Instruction:"VFCMULCSH Vdq{K}{z},aKq,Hdq,Wd{er}" Encoding:"evex m:6 p:3 l:i w:0 0xD7 /r"/"RAVM" + // Pos:2948 Instruction:"VFCMULCSH Vdq{K}{z},aKq,Hdq,Wd{er}" Encoding:"evex m:6 p:3 l:i w:0 0xD7 /r"/"RAVM" { .Instruction = ND_INS_VFCMULCSH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1103, + .Mnemonic = 1134, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -81151,6 +85229,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E10S, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -81166,12 +85245,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2908 Instruction:"VFIXUPIMMPD Vfv{K}{z},aKq,Hfv,Wfv|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x54 /r ib"/"RAVMI" + // Pos:2949 Instruction:"VFIXUPIMMPD Vfv{K}{z},aKq,Hfv,Wfv|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x54 /r ib"/"RAVMI" { .Instruction = ND_INS_VFIXUPIMMPD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1104, + .Mnemonic = 1135, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -81180,6 +85259,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_ZE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -81196,12 +85276,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2909 Instruction:"VFIXUPIMMPS Vfv{K}{z},aKq,Hfv,Wfv|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x54 /r ib"/"RAVMI" + // Pos:2950 Instruction:"VFIXUPIMMPS Vfv{K}{z},aKq,Hfv,Wfv|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x54 /r ib"/"RAVMI" { .Instruction = ND_INS_VFIXUPIMMPS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1105, + .Mnemonic = 1136, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -81210,6 +85290,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_ZE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -81226,12 +85307,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2910 Instruction:"VFIXUPIMMSD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x55 /r ib"/"RAVMI" + // Pos:2951 Instruction:"VFIXUPIMMSD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x55 /r ib"/"RAVMI" { .Instruction = ND_INS_VFIXUPIMMSD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1106, + .Mnemonic = 1137, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, @@ -81240,6 +85321,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_ZE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -81256,12 +85338,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2911 Instruction:"VFIXUPIMMSS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x55 /r ib"/"RAVMI" + // Pos:2952 Instruction:"VFIXUPIMMSS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x55 /r ib"/"RAVMI" { .Instruction = ND_INS_VFIXUPIMMSS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1107, + .Mnemonic = 1138, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, @@ -81270,6 +85352,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_ZE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -81286,12 +85369,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2912 Instruction:"VFMADD132NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:6 p:0 l:x w:0 0x98 /r"/"RAVM" + // Pos:2953 Instruction:"VFMADD132NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:6 p:0 l:x w:0 0x98 /r"/"RAVM" { .Instruction = ND_INS_VFMADD132NEPBF16, .Category = ND_CAT_AVX10BF16, .IsaSet = ND_SET_AVX102, - .Mnemonic = 1108, + .Mnemonic = 1139, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -81300,6 +85383,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -81315,12 +85399,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2913 Instruction:"VFMADD132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x98 /r"/"RAVM" + // Pos:2954 Instruction:"VFMADD132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x98 /r"/"RAVM" { .Instruction = ND_INS_VFMADD132PD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1109, + .Mnemonic = 1140, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -81329,6 +85413,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -81344,12 +85429,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2914 Instruction:"VFMADD132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x98 /r"/"RVM" + // Pos:2955 Instruction:"VFMADD132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x98 /r"/"RVM" { .Instruction = ND_INS_VFMADD132PD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1109, + .Mnemonic = 1140, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -81358,6 +85443,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -81372,12 +85458,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2915 Instruction:"VFMADD132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x98 /r"/"RAVM" + // Pos:2956 Instruction:"VFMADD132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x98 /r"/"RAVM" { .Instruction = ND_INS_VFMADD132PH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1110, + .Mnemonic = 1141, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -81386,6 +85472,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -81401,12 +85488,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2916 Instruction:"VFMADD132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x98 /r"/"RAVM" + // Pos:2957 Instruction:"VFMADD132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x98 /r"/"RAVM" { .Instruction = ND_INS_VFMADD132PS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1111, + .Mnemonic = 1142, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -81415,6 +85502,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -81430,12 +85518,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2917 Instruction:"VFMADD132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x98 /r"/"RVM" + // Pos:2958 Instruction:"VFMADD132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x98 /r"/"RVM" { .Instruction = ND_INS_VFMADD132PS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1111, + .Mnemonic = 1142, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -81444,6 +85532,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -81458,12 +85547,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2918 Instruction:"VFMADD132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x99 /r"/"RAVM" + // Pos:2959 Instruction:"VFMADD132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x99 /r"/"RAVM" { .Instruction = ND_INS_VFMADD132SD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1112, + .Mnemonic = 1143, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -81472,6 +85561,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -81487,12 +85577,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2919 Instruction:"VFMADD132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x99 /r"/"RVM" + // Pos:2960 Instruction:"VFMADD132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x99 /r"/"RVM" { .Instruction = ND_INS_VFMADD132SD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1112, + .Mnemonic = 1143, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -81501,6 +85591,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -81515,12 +85606,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2920 Instruction:"VFMADD132SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0x99 /r"/"RAVM" + // Pos:2961 Instruction:"VFMADD132SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0x99 /r"/"RAVM" { .Instruction = ND_INS_VFMADD132SH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1113, + .Mnemonic = 1144, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -81529,6 +85620,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -81544,12 +85636,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2921 Instruction:"VFMADD132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x99 /r"/"RAVM" + // Pos:2962 Instruction:"VFMADD132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x99 /r"/"RAVM" { .Instruction = ND_INS_VFMADD132SS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1114, + .Mnemonic = 1145, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -81558,6 +85650,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -81573,12 +85666,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2922 Instruction:"VFMADD132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x99 /r"/"RVM" + // Pos:2963 Instruction:"VFMADD132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x99 /r"/"RVM" { .Instruction = ND_INS_VFMADD132SS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1114, + .Mnemonic = 1145, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -81587,6 +85680,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -81601,12 +85695,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2923 Instruction:"VFMADD213NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:6 p:0 l:x w:0 0xA8 /r"/"RAVM" + // Pos:2964 Instruction:"VFMADD213NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:6 p:0 l:x w:0 0xA8 /r"/"RAVM" { .Instruction = ND_INS_VFMADD213NEPBF16, .Category = ND_CAT_AVX10BF16, .IsaSet = ND_SET_AVX102, - .Mnemonic = 1115, + .Mnemonic = 1146, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -81615,6 +85709,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -81630,12 +85725,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2924 Instruction:"VFMADD213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xA8 /r"/"RAVM" + // Pos:2965 Instruction:"VFMADD213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xA8 /r"/"RAVM" { .Instruction = ND_INS_VFMADD213PD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1116, + .Mnemonic = 1147, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -81644,6 +85739,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -81659,12 +85755,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2925 Instruction:"VFMADD213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xA8 /r"/"RVM" + // Pos:2966 Instruction:"VFMADD213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xA8 /r"/"RVM" { .Instruction = ND_INS_VFMADD213PD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1116, + .Mnemonic = 1147, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -81673,6 +85769,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -81687,12 +85784,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2926 Instruction:"VFMADD213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xA8 /r"/"RAVM" + // Pos:2967 Instruction:"VFMADD213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xA8 /r"/"RAVM" { .Instruction = ND_INS_VFMADD213PH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1117, + .Mnemonic = 1148, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -81701,6 +85798,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -81716,12 +85814,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2927 Instruction:"VFMADD213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xA8 /r"/"RAVM" + // Pos:2968 Instruction:"VFMADD213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xA8 /r"/"RAVM" { .Instruction = ND_INS_VFMADD213PS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1118, + .Mnemonic = 1149, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -81730,6 +85828,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -81745,12 +85844,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2928 Instruction:"VFMADD213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xA8 /r"/"RVM" + // Pos:2969 Instruction:"VFMADD213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xA8 /r"/"RVM" { .Instruction = ND_INS_VFMADD213PS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1118, + .Mnemonic = 1149, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -81759,6 +85858,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -81773,12 +85873,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2929 Instruction:"VFMADD213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xA9 /r"/"RAVM" + // Pos:2970 Instruction:"VFMADD213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xA9 /r"/"RAVM" { .Instruction = ND_INS_VFMADD213SD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1119, + .Mnemonic = 1150, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -81787,6 +85887,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -81802,12 +85903,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2930 Instruction:"VFMADD213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xA9 /r"/"RVM" + // Pos:2971 Instruction:"VFMADD213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xA9 /r"/"RVM" { .Instruction = ND_INS_VFMADD213SD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1119, + .Mnemonic = 1150, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -81816,6 +85917,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -81830,12 +85932,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2931 Instruction:"VFMADD213SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xA9 /r"/"RAVM" + // Pos:2972 Instruction:"VFMADD213SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xA9 /r"/"RAVM" { .Instruction = ND_INS_VFMADD213SH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1120, + .Mnemonic = 1151, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -81844,6 +85946,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -81859,12 +85962,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2932 Instruction:"VFMADD213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xA9 /r"/"RAVM" + // Pos:2973 Instruction:"VFMADD213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xA9 /r"/"RAVM" { .Instruction = ND_INS_VFMADD213SS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1121, + .Mnemonic = 1152, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -81873,6 +85976,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -81888,12 +85992,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2933 Instruction:"VFMADD213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xA9 /r"/"RVM" + // Pos:2974 Instruction:"VFMADD213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xA9 /r"/"RVM" { .Instruction = ND_INS_VFMADD213SS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1121, + .Mnemonic = 1152, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -81902,6 +86006,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -81916,12 +86021,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2934 Instruction:"VFMADD231NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:6 p:0 l:x w:0 0xB8 /r"/"RAVM" + // Pos:2975 Instruction:"VFMADD231NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:6 p:0 l:x w:0 0xB8 /r"/"RAVM" { .Instruction = ND_INS_VFMADD231NEPBF16, .Category = ND_CAT_AVX10BF16, .IsaSet = ND_SET_AVX102, - .Mnemonic = 1122, + .Mnemonic = 1153, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -81930,6 +86035,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -81945,12 +86051,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2935 Instruction:"VFMADD231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xB8 /r"/"RAVM" + // Pos:2976 Instruction:"VFMADD231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xB8 /r"/"RAVM" { .Instruction = ND_INS_VFMADD231PD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1123, + .Mnemonic = 1154, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -81959,6 +86065,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -81974,12 +86081,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2936 Instruction:"VFMADD231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB8 /r"/"RVM" + // Pos:2977 Instruction:"VFMADD231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB8 /r"/"RVM" { .Instruction = ND_INS_VFMADD231PD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1123, + .Mnemonic = 1154, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -81988,6 +86095,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -82002,12 +86110,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2937 Instruction:"VFMADD231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xB8 /r"/"RAVM" + // Pos:2978 Instruction:"VFMADD231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xB8 /r"/"RAVM" { .Instruction = ND_INS_VFMADD231PH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1124, + .Mnemonic = 1155, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -82016,6 +86124,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -82031,12 +86140,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2938 Instruction:"VFMADD231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xB8 /r"/"RAVM" + // Pos:2979 Instruction:"VFMADD231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xB8 /r"/"RAVM" { .Instruction = ND_INS_VFMADD231PS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1125, + .Mnemonic = 1156, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -82045,6 +86154,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -82060,12 +86170,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2939 Instruction:"VFMADD231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xB8 /r"/"RVM" + // Pos:2980 Instruction:"VFMADD231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xB8 /r"/"RVM" { .Instruction = ND_INS_VFMADD231PS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1125, + .Mnemonic = 1156, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -82074,6 +86184,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -82088,12 +86199,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2940 Instruction:"VFMADD231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xB9 /r"/"RAVM" + // Pos:2981 Instruction:"VFMADD231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xB9 /r"/"RAVM" { .Instruction = ND_INS_VFMADD231SD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1126, + .Mnemonic = 1157, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -82102,6 +86213,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -82117,12 +86229,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2941 Instruction:"VFMADD231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xB9 /r"/"RVM" + // Pos:2982 Instruction:"VFMADD231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xB9 /r"/"RVM" { .Instruction = ND_INS_VFMADD231SD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1126, + .Mnemonic = 1157, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -82131,6 +86243,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -82145,12 +86258,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2942 Instruction:"VFMADD231SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xB9 /r"/"RAVM" + // Pos:2983 Instruction:"VFMADD231SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xB9 /r"/"RAVM" { .Instruction = ND_INS_VFMADD231SH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1127, + .Mnemonic = 1158, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -82159,6 +86272,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -82174,12 +86288,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2943 Instruction:"VFMADD231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xB9 /r"/"RAVM" + // Pos:2984 Instruction:"VFMADD231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xB9 /r"/"RAVM" { .Instruction = ND_INS_VFMADD231SS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1128, + .Mnemonic = 1159, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -82188,6 +86302,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -82203,12 +86318,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2944 Instruction:"VFMADD231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xB9 /r"/"RVM" + // Pos:2985 Instruction:"VFMADD231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xB9 /r"/"RVM" { .Instruction = ND_INS_VFMADD231SS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1128, + .Mnemonic = 1159, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -82217,6 +86332,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -82231,12 +86347,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2945 Instruction:"VFMADDCPH Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:6 p:2 l:x w:0 0x56 /r"/"RAVM" + // Pos:2986 Instruction:"VFMADDCPH Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:6 p:2 l:x w:0 0x56 /r"/"RAVM" { .Instruction = ND_INS_VFMADDCPH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1129, + .Mnemonic = 1160, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -82245,6 +86361,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4S, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -82260,12 +86377,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2946 Instruction:"VFMADDCSH Vdq{K}{z},aKq,Hdq,Wd{er}" Encoding:"evex m:6 p:2 l:i w:0 0x57 /r"/"RAVM" + // Pos:2987 Instruction:"VFMADDCSH Vdq{K}{z},aKq,Hdq,Wd{er}" Encoding:"evex m:6 p:2 l:i w:0 0x57 /r"/"RAVM" { .Instruction = ND_INS_VFMADDCSH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1130, + .Mnemonic = 1161, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -82274,6 +86391,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E10S, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -82289,12 +86407,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2947 Instruction:"VFMADDPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x69 /r is4"/"RVML" + // Pos:2988 Instruction:"VFMADDPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x69 /r is4"/"RVML" { .Instruction = ND_INS_VFMADDPD, .Category = ND_CAT_FMA4, .IsaSet = ND_SET_FMA4, - .Mnemonic = 1131, + .Mnemonic = 1162, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -82303,6 +86421,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -82318,12 +86437,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2948 Instruction:"VFMADDPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x69 /r is4"/"RVLM" + // Pos:2989 Instruction:"VFMADDPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x69 /r is4"/"RVLM" { .Instruction = ND_INS_VFMADDPD, .Category = ND_CAT_FMA4, .IsaSet = ND_SET_FMA4, - .Mnemonic = 1131, + .Mnemonic = 1162, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -82332,6 +86451,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -82347,12 +86467,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2949 Instruction:"VFMADDPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x68 /r is4"/"RVML" + // Pos:2990 Instruction:"VFMADDPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x68 /r is4"/"RVML" { .Instruction = ND_INS_VFMADDPS, .Category = ND_CAT_FMA4, .IsaSet = ND_SET_FMA4, - .Mnemonic = 1132, + .Mnemonic = 1163, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -82361,6 +86481,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -82376,12 +86497,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2950 Instruction:"VFMADDPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x68 /r is4"/"RVLM" + // Pos:2991 Instruction:"VFMADDPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x68 /r is4"/"RVLM" { .Instruction = ND_INS_VFMADDPS, .Category = ND_CAT_FMA4, .IsaSet = ND_SET_FMA4, - .Mnemonic = 1132, + .Mnemonic = 1163, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -82390,6 +86511,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -82405,12 +86527,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2951 Instruction:"VFMADDSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6B /r is4"/"RVML" + // Pos:2992 Instruction:"VFMADDSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6B /r is4"/"RVML" { .Instruction = ND_INS_VFMADDSD, .Category = ND_CAT_FMA4, .IsaSet = ND_SET_FMA4, - .Mnemonic = 1133, + .Mnemonic = 1164, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -82419,6 +86541,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -82434,12 +86557,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2952 Instruction:"VFMADDSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x6B /r is4"/"RVLM" + // Pos:2993 Instruction:"VFMADDSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x6B /r is4"/"RVLM" { .Instruction = ND_INS_VFMADDSD, .Category = ND_CAT_FMA4, .IsaSet = ND_SET_FMA4, - .Mnemonic = 1133, + .Mnemonic = 1164, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -82448,6 +86571,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -82463,12 +86587,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2953 Instruction:"VFMADDSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6A /r is4"/"RVML" + // Pos:2994 Instruction:"VFMADDSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6A /r is4"/"RVML" { .Instruction = ND_INS_VFMADDSS, .Category = ND_CAT_FMA4, .IsaSet = ND_SET_FMA4, - .Mnemonic = 1134, + .Mnemonic = 1165, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -82477,6 +86601,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -82492,12 +86617,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2954 Instruction:"VFMADDSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x6A /r is4"/"RVLM" + // Pos:2995 Instruction:"VFMADDSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x6A /r is4"/"RVLM" { .Instruction = ND_INS_VFMADDSS, .Category = ND_CAT_FMA4, .IsaSet = ND_SET_FMA4, - .Mnemonic = 1134, + .Mnemonic = 1165, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -82506,6 +86631,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -82521,12 +86647,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2955 Instruction:"VFMADDSUB132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x96 /r"/"RAVM" + // Pos:2996 Instruction:"VFMADDSUB132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x96 /r"/"RAVM" { .Instruction = ND_INS_VFMADDSUB132PD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1135, + .Mnemonic = 1166, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -82535,6 +86661,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -82550,12 +86677,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2956 Instruction:"VFMADDSUB132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x96 /r"/"RVM" + // Pos:2997 Instruction:"VFMADDSUB132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x96 /r"/"RVM" { .Instruction = ND_INS_VFMADDSUB132PD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1135, + .Mnemonic = 1166, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -82564,6 +86691,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -82578,12 +86706,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2957 Instruction:"VFMADDSUB132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x96 /r"/"RAVM" + // Pos:2998 Instruction:"VFMADDSUB132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x96 /r"/"RAVM" { .Instruction = ND_INS_VFMADDSUB132PH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1136, + .Mnemonic = 1167, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -82592,6 +86720,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -82607,12 +86736,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2958 Instruction:"VFMADDSUB132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x96 /r"/"RAVM" + // Pos:2999 Instruction:"VFMADDSUB132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x96 /r"/"RAVM" { .Instruction = ND_INS_VFMADDSUB132PS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1137, + .Mnemonic = 1168, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -82621,6 +86750,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -82636,12 +86766,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2959 Instruction:"VFMADDSUB132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x96 /r"/"RVM" + // Pos:3000 Instruction:"VFMADDSUB132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x96 /r"/"RVM" { .Instruction = ND_INS_VFMADDSUB132PS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1137, + .Mnemonic = 1168, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -82650,6 +86780,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -82664,12 +86795,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2960 Instruction:"VFMADDSUB213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xA6 /r"/"RAVM" + // Pos:3001 Instruction:"VFMADDSUB213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xA6 /r"/"RAVM" { .Instruction = ND_INS_VFMADDSUB213PD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1138, + .Mnemonic = 1169, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -82678,6 +86809,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -82693,12 +86825,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2961 Instruction:"VFMADDSUB213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xA6 /r"/"RVM" + // Pos:3002 Instruction:"VFMADDSUB213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xA6 /r"/"RVM" { .Instruction = ND_INS_VFMADDSUB213PD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1138, + .Mnemonic = 1169, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -82707,6 +86839,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -82721,12 +86854,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2962 Instruction:"VFMADDSUB213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xA6 /r"/"RAVM" + // Pos:3003 Instruction:"VFMADDSUB213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xA6 /r"/"RAVM" { .Instruction = ND_INS_VFMADDSUB213PH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1139, + .Mnemonic = 1170, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -82735,6 +86868,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -82750,12 +86884,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2963 Instruction:"VFMADDSUB213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xA6 /r"/"RAVM" + // Pos:3004 Instruction:"VFMADDSUB213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xA6 /r"/"RAVM" { .Instruction = ND_INS_VFMADDSUB213PS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1140, + .Mnemonic = 1171, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -82764,6 +86898,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -82779,12 +86914,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2964 Instruction:"VFMADDSUB213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xA6 /r"/"RVM" + // Pos:3005 Instruction:"VFMADDSUB213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xA6 /r"/"RVM" { .Instruction = ND_INS_VFMADDSUB213PS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1140, + .Mnemonic = 1171, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -82793,6 +86928,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -82807,12 +86943,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2965 Instruction:"VFMADDSUB231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xB6 /r"/"RAVM" + // Pos:3006 Instruction:"VFMADDSUB231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xB6 /r"/"RAVM" { .Instruction = ND_INS_VFMADDSUB231PD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1141, + .Mnemonic = 1172, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -82821,6 +86957,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -82836,12 +86973,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2966 Instruction:"VFMADDSUB231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB6 /r"/"RVM" + // Pos:3007 Instruction:"VFMADDSUB231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB6 /r"/"RVM" { .Instruction = ND_INS_VFMADDSUB231PD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1141, + .Mnemonic = 1172, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -82850,6 +86987,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -82864,12 +87002,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2967 Instruction:"VFMADDSUB231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xB6 /r"/"RAVM" + // Pos:3008 Instruction:"VFMADDSUB231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xB6 /r"/"RAVM" { .Instruction = ND_INS_VFMADDSUB231PH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1142, + .Mnemonic = 1173, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -82878,6 +87016,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -82893,12 +87032,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2968 Instruction:"VFMADDSUB231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xB6 /r"/"RAVM" + // Pos:3009 Instruction:"VFMADDSUB231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xB6 /r"/"RAVM" { .Instruction = ND_INS_VFMADDSUB231PS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1143, + .Mnemonic = 1174, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -82907,6 +87046,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -82922,12 +87062,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2969 Instruction:"VFMADDSUB231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xB6 /r"/"RVM" + // Pos:3010 Instruction:"VFMADDSUB231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xB6 /r"/"RVM" { .Instruction = ND_INS_VFMADDSUB231PS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1143, + .Mnemonic = 1174, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -82936,6 +87076,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -82950,12 +87091,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2970 Instruction:"VFMADDSUBPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5D /r is4"/"RVML" + // Pos:3011 Instruction:"VFMADDSUBPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5D /r is4"/"RVML" { .Instruction = ND_INS_VFMADDSUBPD, .Category = ND_CAT_FMA4, .IsaSet = ND_SET_FMA4, - .Mnemonic = 1144, + .Mnemonic = 1175, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -82964,6 +87105,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -82979,12 +87121,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2971 Instruction:"VFMADDSUBPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5D /r is4"/"RVLM" + // Pos:3012 Instruction:"VFMADDSUBPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5D /r is4"/"RVLM" { .Instruction = ND_INS_VFMADDSUBPD, .Category = ND_CAT_FMA4, .IsaSet = ND_SET_FMA4, - .Mnemonic = 1144, + .Mnemonic = 1175, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -82993,6 +87135,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -83008,12 +87151,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2972 Instruction:"VFMADDSUBPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5C /r is4"/"RVML" + // Pos:3013 Instruction:"VFMADDSUBPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5C /r is4"/"RVML" { .Instruction = ND_INS_VFMADDSUBPS, .Category = ND_CAT_FMA4, .IsaSet = ND_SET_FMA4, - .Mnemonic = 1145, + .Mnemonic = 1176, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -83022,6 +87165,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -83037,12 +87181,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2973 Instruction:"VFMADDSUBPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5C /r is4"/"RVLM" + // Pos:3014 Instruction:"VFMADDSUBPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5C /r is4"/"RVLM" { .Instruction = ND_INS_VFMADDSUBPS, .Category = ND_CAT_FMA4, .IsaSet = ND_SET_FMA4, - .Mnemonic = 1145, + .Mnemonic = 1176, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -83051,6 +87195,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -83066,12 +87211,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2974 Instruction:"VFMSUB132NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:6 p:0 l:x w:0 0x9A /r"/"RAVM" + // Pos:3015 Instruction:"VFMSUB132NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:6 p:0 l:x w:0 0x9A /r"/"RAVM" { .Instruction = ND_INS_VFMSUB132NEPBF16, .Category = ND_CAT_AVX10BF16, .IsaSet = ND_SET_AVX102, - .Mnemonic = 1146, + .Mnemonic = 1177, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -83080,6 +87225,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -83095,12 +87241,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2975 Instruction:"VFMSUB132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x9A /r"/"RAVM" + // Pos:3016 Instruction:"VFMSUB132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x9A /r"/"RAVM" { .Instruction = ND_INS_VFMSUB132PD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1147, + .Mnemonic = 1178, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -83109,6 +87255,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -83124,12 +87271,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2976 Instruction:"VFMSUB132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x9A /r"/"RVM" + // Pos:3017 Instruction:"VFMSUB132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x9A /r"/"RVM" { .Instruction = ND_INS_VFMSUB132PD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1147, + .Mnemonic = 1178, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -83138,6 +87285,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -83152,12 +87300,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2977 Instruction:"VFMSUB132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x9A /r"/"RAVM" + // Pos:3018 Instruction:"VFMSUB132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x9A /r"/"RAVM" { .Instruction = ND_INS_VFMSUB132PH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1148, + .Mnemonic = 1179, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -83166,6 +87314,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -83181,12 +87330,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2978 Instruction:"VFMSUB132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x9A /r"/"RAVM" + // Pos:3019 Instruction:"VFMSUB132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x9A /r"/"RAVM" { .Instruction = ND_INS_VFMSUB132PS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1149, + .Mnemonic = 1180, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -83195,6 +87344,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -83210,12 +87360,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2979 Instruction:"VFMSUB132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x9A /r"/"RVM" + // Pos:3020 Instruction:"VFMSUB132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x9A /r"/"RVM" { .Instruction = ND_INS_VFMSUB132PS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1149, + .Mnemonic = 1180, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -83224,6 +87374,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -83238,12 +87389,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2980 Instruction:"VFMSUB132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x9B /r"/"RAVM" + // Pos:3021 Instruction:"VFMSUB132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x9B /r"/"RAVM" { .Instruction = ND_INS_VFMSUB132SD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1150, + .Mnemonic = 1181, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -83252,6 +87403,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -83267,12 +87419,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2981 Instruction:"VFMSUB132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x9B /r"/"RVM" + // Pos:3022 Instruction:"VFMSUB132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x9B /r"/"RVM" { .Instruction = ND_INS_VFMSUB132SD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1150, + .Mnemonic = 1181, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -83281,6 +87433,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -83295,12 +87448,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2982 Instruction:"VFMSUB132SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0x9B /r"/"RAVM" + // Pos:3023 Instruction:"VFMSUB132SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0x9B /r"/"RAVM" { .Instruction = ND_INS_VFMSUB132SH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1151, + .Mnemonic = 1182, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -83309,6 +87462,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -83324,12 +87478,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2983 Instruction:"VFMSUB132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x9B /r"/"RAVM" + // Pos:3024 Instruction:"VFMSUB132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x9B /r"/"RAVM" { .Instruction = ND_INS_VFMSUB132SS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1152, + .Mnemonic = 1183, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -83338,6 +87492,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -83353,12 +87508,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2984 Instruction:"VFMSUB132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x9B /r"/"RVM" + // Pos:3025 Instruction:"VFMSUB132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x9B /r"/"RVM" { .Instruction = ND_INS_VFMSUB132SS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1152, + .Mnemonic = 1183, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -83367,6 +87522,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -83381,12 +87537,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2985 Instruction:"VFMSUB213NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:6 p:0 l:x w:0 0xAA /r"/"RAVM" + // Pos:3026 Instruction:"VFMSUB213NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:6 p:0 l:x w:0 0xAA /r"/"RAVM" { .Instruction = ND_INS_VFMSUB213NEPBF16, .Category = ND_CAT_AVX10BF16, .IsaSet = ND_SET_AVX102, - .Mnemonic = 1153, + .Mnemonic = 1184, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -83395,6 +87551,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -83410,12 +87567,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2986 Instruction:"VFMSUB213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xAA /r"/"RAVM" + // Pos:3027 Instruction:"VFMSUB213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xAA /r"/"RAVM" { .Instruction = ND_INS_VFMSUB213PD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1154, + .Mnemonic = 1185, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -83424,6 +87581,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -83439,12 +87597,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2987 Instruction:"VFMSUB213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xAA /r"/"RVM" + // Pos:3028 Instruction:"VFMSUB213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xAA /r"/"RVM" { .Instruction = ND_INS_VFMSUB213PD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1154, + .Mnemonic = 1185, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -83453,6 +87611,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -83467,12 +87626,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2988 Instruction:"VFMSUB213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xAA /r"/"RAVM" + // Pos:3029 Instruction:"VFMSUB213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xAA /r"/"RAVM" { .Instruction = ND_INS_VFMSUB213PH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1155, + .Mnemonic = 1186, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -83481,6 +87640,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -83496,12 +87656,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2989 Instruction:"VFMSUB213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xAA /r"/"RAVM" + // Pos:3030 Instruction:"VFMSUB213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xAA /r"/"RAVM" { .Instruction = ND_INS_VFMSUB213PS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1156, + .Mnemonic = 1187, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -83510,6 +87670,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -83525,12 +87686,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2990 Instruction:"VFMSUB213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xAA /r"/"RVM" + // Pos:3031 Instruction:"VFMSUB213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xAA /r"/"RVM" { .Instruction = ND_INS_VFMSUB213PS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1156, + .Mnemonic = 1187, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -83539,6 +87700,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -83553,12 +87715,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2991 Instruction:"VFMSUB213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xAB /r"/"RAVM" + // Pos:3032 Instruction:"VFMSUB213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xAB /r"/"RAVM" { .Instruction = ND_INS_VFMSUB213SD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1157, + .Mnemonic = 1188, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -83567,6 +87729,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -83582,12 +87745,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2992 Instruction:"VFMSUB213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xAB /r"/"RVM" + // Pos:3033 Instruction:"VFMSUB213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xAB /r"/"RVM" { .Instruction = ND_INS_VFMSUB213SD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1157, + .Mnemonic = 1188, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -83596,6 +87759,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -83610,12 +87774,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2993 Instruction:"VFMSUB213SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xAB /r"/"RAVM" + // Pos:3034 Instruction:"VFMSUB213SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xAB /r"/"RAVM" { .Instruction = ND_INS_VFMSUB213SH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1158, + .Mnemonic = 1189, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -83624,6 +87788,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -83639,12 +87804,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2994 Instruction:"VFMSUB213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xAB /r"/"RAVM" + // Pos:3035 Instruction:"VFMSUB213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xAB /r"/"RAVM" { .Instruction = ND_INS_VFMSUB213SS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1159, + .Mnemonic = 1190, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -83653,6 +87818,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -83668,12 +87834,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2995 Instruction:"VFMSUB213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xAB /r"/"RVM" + // Pos:3036 Instruction:"VFMSUB213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xAB /r"/"RVM" { .Instruction = ND_INS_VFMSUB213SS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1159, + .Mnemonic = 1190, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -83682,6 +87848,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -83696,12 +87863,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2996 Instruction:"VFMSUB231NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:6 p:0 l:x w:0 0xBA /r"/"RAVM" + // Pos:3037 Instruction:"VFMSUB231NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:6 p:0 l:x w:0 0xBA /r"/"RAVM" { .Instruction = ND_INS_VFMSUB231NEPBF16, .Category = ND_CAT_AVX10BF16, .IsaSet = ND_SET_AVX102, - .Mnemonic = 1160, + .Mnemonic = 1191, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -83710,6 +87877,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -83725,12 +87893,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2997 Instruction:"VFMSUB231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xBA /r"/"RAVM" + // Pos:3038 Instruction:"VFMSUB231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xBA /r"/"RAVM" { .Instruction = ND_INS_VFMSUB231PD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1161, + .Mnemonic = 1192, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -83739,6 +87907,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -83754,12 +87923,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2998 Instruction:"VFMSUB231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xBA /r"/"RVM" + // Pos:3039 Instruction:"VFMSUB231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xBA /r"/"RVM" { .Instruction = ND_INS_VFMSUB231PD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1161, + .Mnemonic = 1192, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -83768,6 +87937,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -83782,12 +87952,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:2999 Instruction:"VFMSUB231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xBA /r"/"RAVM" + // Pos:3040 Instruction:"VFMSUB231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xBA /r"/"RAVM" { .Instruction = ND_INS_VFMSUB231PH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1162, + .Mnemonic = 1193, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -83796,6 +87966,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -83811,12 +87982,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3000 Instruction:"VFMSUB231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xBA /r"/"RAVM" + // Pos:3041 Instruction:"VFMSUB231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xBA /r"/"RAVM" { .Instruction = ND_INS_VFMSUB231PS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1163, + .Mnemonic = 1194, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -83825,6 +87996,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -83840,12 +88012,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3001 Instruction:"VFMSUB231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xBA /r"/"RVM" + // Pos:3042 Instruction:"VFMSUB231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xBA /r"/"RVM" { .Instruction = ND_INS_VFMSUB231PS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1163, + .Mnemonic = 1194, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -83854,6 +88026,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -83868,12 +88041,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3002 Instruction:"VFMSUB231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xBB /r"/"RAVM" + // Pos:3043 Instruction:"VFMSUB231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xBB /r"/"RAVM" { .Instruction = ND_INS_VFMSUB231SD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1164, + .Mnemonic = 1195, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -83882,6 +88055,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -83897,12 +88071,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3003 Instruction:"VFMSUB231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xBB /r"/"RVM" + // Pos:3044 Instruction:"VFMSUB231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xBB /r"/"RVM" { .Instruction = ND_INS_VFMSUB231SD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1164, + .Mnemonic = 1195, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -83911,6 +88085,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -83925,12 +88100,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3004 Instruction:"VFMSUB231SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xBB /r"/"RAVM" + // Pos:3045 Instruction:"VFMSUB231SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xBB /r"/"RAVM" { .Instruction = ND_INS_VFMSUB231SH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1165, + .Mnemonic = 1196, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -83939,6 +88114,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -83954,12 +88130,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3005 Instruction:"VFMSUB231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xBB /r"/"RAVM" + // Pos:3046 Instruction:"VFMSUB231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xBB /r"/"RAVM" { .Instruction = ND_INS_VFMSUB231SS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1166, + .Mnemonic = 1197, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -83968,6 +88144,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -83983,12 +88160,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3006 Instruction:"VFMSUB231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xBB /r"/"RVM" + // Pos:3047 Instruction:"VFMSUB231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xBB /r"/"RVM" { .Instruction = ND_INS_VFMSUB231SS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1166, + .Mnemonic = 1197, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -83997,6 +88174,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -84011,12 +88189,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3007 Instruction:"VFMSUBADD132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x97 /r"/"RAVM" + // Pos:3048 Instruction:"VFMSUBADD132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x97 /r"/"RAVM" { .Instruction = ND_INS_VFMSUBADD132PD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1167, + .Mnemonic = 1198, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -84025,6 +88203,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -84040,12 +88219,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3008 Instruction:"VFMSUBADD132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x97 /r"/"RVM" + // Pos:3049 Instruction:"VFMSUBADD132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x97 /r"/"RVM" { .Instruction = ND_INS_VFMSUBADD132PD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1167, + .Mnemonic = 1198, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -84054,6 +88233,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -84068,12 +88248,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3009 Instruction:"VFMSUBADD132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x97 /r"/"RAVM" + // Pos:3050 Instruction:"VFMSUBADD132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x97 /r"/"RAVM" { .Instruction = ND_INS_VFMSUBADD132PH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1168, + .Mnemonic = 1199, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -84082,6 +88262,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -84097,12 +88278,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3010 Instruction:"VFMSUBADD132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x97 /r"/"RAVM" + // Pos:3051 Instruction:"VFMSUBADD132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x97 /r"/"RAVM" { .Instruction = ND_INS_VFMSUBADD132PS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1169, + .Mnemonic = 1200, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -84111,6 +88292,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -84126,12 +88308,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3011 Instruction:"VFMSUBADD132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x97 /r"/"RVM" + // Pos:3052 Instruction:"VFMSUBADD132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x97 /r"/"RVM" { .Instruction = ND_INS_VFMSUBADD132PS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1169, + .Mnemonic = 1200, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -84140,6 +88322,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -84154,12 +88337,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3012 Instruction:"VFMSUBADD213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xA7 /r"/"RAVM" + // Pos:3053 Instruction:"VFMSUBADD213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xA7 /r"/"RAVM" { .Instruction = ND_INS_VFMSUBADD213PD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1170, + .Mnemonic = 1201, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -84168,6 +88351,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -84183,12 +88367,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3013 Instruction:"VFMSUBADD213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xA7 /r"/"RVM" + // Pos:3054 Instruction:"VFMSUBADD213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xA7 /r"/"RVM" { .Instruction = ND_INS_VFMSUBADD213PD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1170, + .Mnemonic = 1201, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -84197,6 +88381,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -84211,12 +88396,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3014 Instruction:"VFMSUBADD213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xA7 /r"/"RAVM" + // Pos:3055 Instruction:"VFMSUBADD213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xA7 /r"/"RAVM" { .Instruction = ND_INS_VFMSUBADD213PH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1171, + .Mnemonic = 1202, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -84225,6 +88410,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -84240,12 +88426,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3015 Instruction:"VFMSUBADD213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xA7 /r"/"RAVM" + // Pos:3056 Instruction:"VFMSUBADD213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xA7 /r"/"RAVM" { .Instruction = ND_INS_VFMSUBADD213PS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1172, + .Mnemonic = 1203, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -84254,6 +88440,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -84269,12 +88456,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3016 Instruction:"VFMSUBADD213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xA7 /r"/"RVM" + // Pos:3057 Instruction:"VFMSUBADD213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xA7 /r"/"RVM" { .Instruction = ND_INS_VFMSUBADD213PS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1172, + .Mnemonic = 1203, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -84283,6 +88470,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -84297,12 +88485,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3017 Instruction:"VFMSUBADD231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xB7 /r"/"RAVM" + // Pos:3058 Instruction:"VFMSUBADD231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xB7 /r"/"RAVM" { .Instruction = ND_INS_VFMSUBADD231PD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1173, + .Mnemonic = 1204, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -84311,6 +88499,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -84326,12 +88515,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3018 Instruction:"VFMSUBADD231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB7 /r"/"RVM" + // Pos:3059 Instruction:"VFMSUBADD231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB7 /r"/"RVM" { .Instruction = ND_INS_VFMSUBADD231PD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1173, + .Mnemonic = 1204, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -84340,6 +88529,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -84354,12 +88544,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3019 Instruction:"VFMSUBADD231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xB7 /r"/"RAVM" + // Pos:3060 Instruction:"VFMSUBADD231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xB7 /r"/"RAVM" { .Instruction = ND_INS_VFMSUBADD231PH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1174, + .Mnemonic = 1205, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -84368,6 +88558,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -84383,12 +88574,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3020 Instruction:"VFMSUBADD231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xB7 /r"/"RAVM" + // Pos:3061 Instruction:"VFMSUBADD231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xB7 /r"/"RAVM" { .Instruction = ND_INS_VFMSUBADD231PS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1175, + .Mnemonic = 1206, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -84397,6 +88588,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -84412,12 +88604,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3021 Instruction:"VFMSUBADD231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xB7 /r"/"RVM" + // Pos:3062 Instruction:"VFMSUBADD231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xB7 /r"/"RVM" { .Instruction = ND_INS_VFMSUBADD231PS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1175, + .Mnemonic = 1206, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -84426,6 +88618,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -84440,12 +88633,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3022 Instruction:"VFMSUBADDPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5F /r is4"/"RVML" + // Pos:3063 Instruction:"VFMSUBADDPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5F /r is4"/"RVML" { .Instruction = ND_INS_VFMSUBADDPD, .Category = ND_CAT_FMA4, .IsaSet = ND_SET_FMA4, - .Mnemonic = 1176, + .Mnemonic = 1207, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -84454,6 +88647,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -84469,12 +88663,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3023 Instruction:"VFMSUBADDPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5F /r is4"/"RVLM" + // Pos:3064 Instruction:"VFMSUBADDPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5F /r is4"/"RVLM" { .Instruction = ND_INS_VFMSUBADDPD, .Category = ND_CAT_FMA4, .IsaSet = ND_SET_FMA4, - .Mnemonic = 1176, + .Mnemonic = 1207, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -84483,6 +88677,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -84498,12 +88693,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3024 Instruction:"VFMSUBADDPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5E /r is4"/"RVML" + // Pos:3065 Instruction:"VFMSUBADDPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5E /r is4"/"RVML" { .Instruction = ND_INS_VFMSUBADDPS, .Category = ND_CAT_FMA4, .IsaSet = ND_SET_FMA4, - .Mnemonic = 1177, + .Mnemonic = 1208, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -84512,6 +88707,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -84527,12 +88723,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3025 Instruction:"VFMSUBADDPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5E /r is4"/"RVLM" + // Pos:3066 Instruction:"VFMSUBADDPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5E /r is4"/"RVLM" { .Instruction = ND_INS_VFMSUBADDPS, .Category = ND_CAT_FMA4, .IsaSet = ND_SET_FMA4, - .Mnemonic = 1177, + .Mnemonic = 1208, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -84541,6 +88737,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -84556,12 +88753,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3026 Instruction:"VFMSUBPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x6D /r is4"/"RVML" + // Pos:3067 Instruction:"VFMSUBPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x6D /r is4"/"RVML" { .Instruction = ND_INS_VFMSUBPD, .Category = ND_CAT_FMA4, .IsaSet = ND_SET_FMA4, - .Mnemonic = 1178, + .Mnemonic = 1209, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -84570,6 +88767,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -84585,12 +88783,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3027 Instruction:"VFMSUBPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x6D /r is4"/"RVLM" + // Pos:3068 Instruction:"VFMSUBPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x6D /r is4"/"RVLM" { .Instruction = ND_INS_VFMSUBPD, .Category = ND_CAT_FMA4, .IsaSet = ND_SET_FMA4, - .Mnemonic = 1178, + .Mnemonic = 1209, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -84599,6 +88797,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -84614,12 +88813,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3028 Instruction:"VFMSUBPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x6C /r is4"/"RVML" + // Pos:3069 Instruction:"VFMSUBPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x6C /r is4"/"RVML" { .Instruction = ND_INS_VFMSUBPS, .Category = ND_CAT_FMA4, .IsaSet = ND_SET_FMA4, - .Mnemonic = 1179, + .Mnemonic = 1210, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -84628,6 +88827,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -84643,12 +88843,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3029 Instruction:"VFMSUBPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x6C /r is4"/"RVLM" + // Pos:3070 Instruction:"VFMSUBPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x6C /r is4"/"RVLM" { .Instruction = ND_INS_VFMSUBPS, .Category = ND_CAT_FMA4, .IsaSet = ND_SET_FMA4, - .Mnemonic = 1179, + .Mnemonic = 1210, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -84657,6 +88857,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -84672,12 +88873,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3030 Instruction:"VFMSUBSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6F /r is4"/"RVML" + // Pos:3071 Instruction:"VFMSUBSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6F /r is4"/"RVML" { .Instruction = ND_INS_VFMSUBSD, .Category = ND_CAT_FMA4, .IsaSet = ND_SET_FMA4, - .Mnemonic = 1180, + .Mnemonic = 1211, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -84686,6 +88887,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -84701,12 +88903,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3031 Instruction:"VFMSUBSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x6F /r is4"/"RVLM" + // Pos:3072 Instruction:"VFMSUBSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x6F /r is4"/"RVLM" { .Instruction = ND_INS_VFMSUBSD, .Category = ND_CAT_FMA4, .IsaSet = ND_SET_FMA4, - .Mnemonic = 1180, + .Mnemonic = 1211, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -84715,6 +88917,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -84730,12 +88933,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3032 Instruction:"VFMSUBSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6E /r is4"/"RVML" + // Pos:3073 Instruction:"VFMSUBSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6E /r is4"/"RVML" { .Instruction = ND_INS_VFMSUBSS, .Category = ND_CAT_FMA4, .IsaSet = ND_SET_FMA4, - .Mnemonic = 1181, + .Mnemonic = 1212, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -84744,6 +88947,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -84759,12 +88963,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3033 Instruction:"VFMSUBSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x6E /r is4"/"RVLM" + // Pos:3074 Instruction:"VFMSUBSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x6E /r is4"/"RVLM" { .Instruction = ND_INS_VFMSUBSS, .Category = ND_CAT_FMA4, .IsaSet = ND_SET_FMA4, - .Mnemonic = 1181, + .Mnemonic = 1212, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -84773,6 +88977,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -84788,12 +88993,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3034 Instruction:"VFMULCPH Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:6 p:2 l:x w:0 0xD6 /r"/"RAVM" + // Pos:3075 Instruction:"VFMULCPH Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:6 p:2 l:x w:0 0xD6 /r"/"RAVM" { .Instruction = ND_INS_VFMULCPH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1182, + .Mnemonic = 1213, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -84802,6 +89007,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4S, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -84817,12 +89023,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3035 Instruction:"VFMULCSH Vdq{K}{z},aKq,Hdq,Wd{er}" Encoding:"evex m:6 p:2 l:i w:0 0xD7 /r"/"RAVM" + // Pos:3076 Instruction:"VFMULCSH Vdq{K}{z},aKq,Hdq,Wd{er}" Encoding:"evex m:6 p:2 l:i w:0 0xD7 /r"/"RAVM" { .Instruction = ND_INS_VFMULCSH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1183, + .Mnemonic = 1214, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -84831,6 +89037,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E10S, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -84846,12 +89053,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3036 Instruction:"VFNMADD132NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:6 p:0 l:x w:0 0x9C /r"/"RAVM" + // Pos:3077 Instruction:"VFNMADD132NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:6 p:0 l:x w:0 0x9C /r"/"RAVM" { .Instruction = ND_INS_VFNMADD132NEPBF16, .Category = ND_CAT_AVX10BF16, .IsaSet = ND_SET_AVX102, - .Mnemonic = 1184, + .Mnemonic = 1215, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -84860,6 +89067,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -84875,12 +89083,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3037 Instruction:"VFNMADD132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x9C /r"/"RAVM" + // Pos:3078 Instruction:"VFNMADD132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x9C /r"/"RAVM" { .Instruction = ND_INS_VFNMADD132PD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1185, + .Mnemonic = 1216, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -84889,6 +89097,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -84904,12 +89113,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3038 Instruction:"VFNMADD132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x9C /r"/"RVM" + // Pos:3079 Instruction:"VFNMADD132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x9C /r"/"RVM" { .Instruction = ND_INS_VFNMADD132PD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1185, + .Mnemonic = 1216, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -84918,6 +89127,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -84932,12 +89142,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3039 Instruction:"VFNMADD132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x9C /r"/"RAVM" + // Pos:3080 Instruction:"VFNMADD132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x9C /r"/"RAVM" { .Instruction = ND_INS_VFNMADD132PH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1186, + .Mnemonic = 1217, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -84946,6 +89156,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -84961,12 +89172,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3040 Instruction:"VFNMADD132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x9C /r"/"RAVM" + // Pos:3081 Instruction:"VFNMADD132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x9C /r"/"RAVM" { .Instruction = ND_INS_VFNMADD132PS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1187, + .Mnemonic = 1218, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -84975,6 +89186,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -84990,12 +89202,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3041 Instruction:"VFNMADD132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x9C /r"/"RVM" + // Pos:3082 Instruction:"VFNMADD132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x9C /r"/"RVM" { .Instruction = ND_INS_VFNMADD132PS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1187, + .Mnemonic = 1218, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -85004,6 +89216,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -85018,12 +89231,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3042 Instruction:"VFNMADD132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x9D /r"/"RAVM" + // Pos:3083 Instruction:"VFNMADD132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x9D /r"/"RAVM" { .Instruction = ND_INS_VFNMADD132SD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1188, + .Mnemonic = 1219, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -85032,6 +89245,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -85047,12 +89261,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3043 Instruction:"VFNMADD132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x9D /r"/"RVM" + // Pos:3084 Instruction:"VFNMADD132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x9D /r"/"RVM" { .Instruction = ND_INS_VFNMADD132SD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1188, + .Mnemonic = 1219, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -85061,6 +89275,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -85075,12 +89290,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3044 Instruction:"VFNMADD132SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0x9D /r"/"RAVM" + // Pos:3085 Instruction:"VFNMADD132SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0x9D /r"/"RAVM" { .Instruction = ND_INS_VFNMADD132SH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1189, + .Mnemonic = 1220, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -85089,6 +89304,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -85104,12 +89320,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3045 Instruction:"VFNMADD132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x9D /r"/"RAVM" + // Pos:3086 Instruction:"VFNMADD132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x9D /r"/"RAVM" { .Instruction = ND_INS_VFNMADD132SS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1190, + .Mnemonic = 1221, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -85118,6 +89334,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -85133,12 +89350,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3046 Instruction:"VFNMADD132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x9D /r"/"RVM" + // Pos:3087 Instruction:"VFNMADD132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x9D /r"/"RVM" { .Instruction = ND_INS_VFNMADD132SS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1190, + .Mnemonic = 1221, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -85147,6 +89364,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -85161,12 +89379,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3047 Instruction:"VFNMADD213NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:6 p:0 l:x w:0 0xAC /r"/"RAVM" + // Pos:3088 Instruction:"VFNMADD213NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:6 p:0 l:x w:0 0xAC /r"/"RAVM" { .Instruction = ND_INS_VFNMADD213NEPBF16, .Category = ND_CAT_AVX10BF16, .IsaSet = ND_SET_AVX102, - .Mnemonic = 1191, + .Mnemonic = 1222, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -85175,6 +89393,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -85190,12 +89409,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3048 Instruction:"VFNMADD213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xAC /r"/"RAVM" + // Pos:3089 Instruction:"VFNMADD213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xAC /r"/"RAVM" { .Instruction = ND_INS_VFNMADD213PD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1192, + .Mnemonic = 1223, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -85204,6 +89423,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -85219,12 +89439,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3049 Instruction:"VFNMADD213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xAC /r"/"RVM" + // Pos:3090 Instruction:"VFNMADD213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xAC /r"/"RVM" { .Instruction = ND_INS_VFNMADD213PD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1192, + .Mnemonic = 1223, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -85233,6 +89453,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -85247,12 +89468,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3050 Instruction:"VFNMADD213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xAC /r"/"RAVM" + // Pos:3091 Instruction:"VFNMADD213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xAC /r"/"RAVM" { .Instruction = ND_INS_VFNMADD213PH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1193, + .Mnemonic = 1224, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -85261,6 +89482,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -85276,12 +89498,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3051 Instruction:"VFNMADD213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xAC /r"/"RAVM" + // Pos:3092 Instruction:"VFNMADD213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xAC /r"/"RAVM" { .Instruction = ND_INS_VFNMADD213PS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1194, + .Mnemonic = 1225, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -85290,6 +89512,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -85305,12 +89528,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3052 Instruction:"VFNMADD213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xAC /r"/"RVM" + // Pos:3093 Instruction:"VFNMADD213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xAC /r"/"RVM" { .Instruction = ND_INS_VFNMADD213PS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1194, + .Mnemonic = 1225, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -85319,6 +89542,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -85333,12 +89557,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3053 Instruction:"VFNMADD213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xAD /r"/"RAVM" + // Pos:3094 Instruction:"VFNMADD213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xAD /r"/"RAVM" { .Instruction = ND_INS_VFNMADD213SD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1195, + .Mnemonic = 1226, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -85347,6 +89571,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -85362,12 +89587,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3054 Instruction:"VFNMADD213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xAD /r"/"RVM" + // Pos:3095 Instruction:"VFNMADD213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xAD /r"/"RVM" { .Instruction = ND_INS_VFNMADD213SD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1195, + .Mnemonic = 1226, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -85376,6 +89601,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -85390,12 +89616,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3055 Instruction:"VFNMADD213SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xAD /r"/"RAVM" + // Pos:3096 Instruction:"VFNMADD213SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xAD /r"/"RAVM" { .Instruction = ND_INS_VFNMADD213SH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1196, + .Mnemonic = 1227, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -85404,6 +89630,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -85419,12 +89646,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3056 Instruction:"VFNMADD213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xAD /r"/"RAVM" + // Pos:3097 Instruction:"VFNMADD213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xAD /r"/"RAVM" { .Instruction = ND_INS_VFNMADD213SS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1197, + .Mnemonic = 1228, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -85433,6 +89660,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -85448,12 +89676,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3057 Instruction:"VFNMADD213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xAD /r"/"RVM" + // Pos:3098 Instruction:"VFNMADD213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xAD /r"/"RVM" { .Instruction = ND_INS_VFNMADD213SS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1197, + .Mnemonic = 1228, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -85462,6 +89690,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -85476,12 +89705,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3058 Instruction:"VFNMADD231NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:6 p:0 l:x w:0 0xBC /r"/"RAVM" + // Pos:3099 Instruction:"VFNMADD231NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:6 p:0 l:x w:0 0xBC /r"/"RAVM" { .Instruction = ND_INS_VFNMADD231NEPBF16, .Category = ND_CAT_AVX10BF16, .IsaSet = ND_SET_AVX102, - .Mnemonic = 1198, + .Mnemonic = 1229, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -85490,6 +89719,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -85505,12 +89735,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3059 Instruction:"VFNMADD231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xBC /r"/"RAVM" + // Pos:3100 Instruction:"VFNMADD231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xBC /r"/"RAVM" { .Instruction = ND_INS_VFNMADD231PD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1199, + .Mnemonic = 1230, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -85519,6 +89749,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -85534,12 +89765,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3060 Instruction:"VFNMADD231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xBC /r"/"RVM" + // Pos:3101 Instruction:"VFNMADD231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xBC /r"/"RVM" { .Instruction = ND_INS_VFNMADD231PD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1199, + .Mnemonic = 1230, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -85548,6 +89779,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -85562,12 +89794,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3061 Instruction:"VFNMADD231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xBC /r"/"RAVM" + // Pos:3102 Instruction:"VFNMADD231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xBC /r"/"RAVM" { .Instruction = ND_INS_VFNMADD231PH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1200, + .Mnemonic = 1231, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -85576,6 +89808,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -85591,12 +89824,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3062 Instruction:"VFNMADD231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xBC /r"/"RAVM" + // Pos:3103 Instruction:"VFNMADD231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xBC /r"/"RAVM" { .Instruction = ND_INS_VFNMADD231PS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1201, + .Mnemonic = 1232, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -85605,6 +89838,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -85620,12 +89854,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3063 Instruction:"VFNMADD231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xBC /r"/"RVM" + // Pos:3104 Instruction:"VFNMADD231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xBC /r"/"RVM" { .Instruction = ND_INS_VFNMADD231PS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1201, + .Mnemonic = 1232, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -85634,6 +89868,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -85648,12 +89883,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3064 Instruction:"VFNMADD231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xBD /r"/"RAVM" + // Pos:3105 Instruction:"VFNMADD231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xBD /r"/"RAVM" { .Instruction = ND_INS_VFNMADD231SD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1202, + .Mnemonic = 1233, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -85662,6 +89897,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -85677,12 +89913,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3065 Instruction:"VFNMADD231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xBD /r"/"RVM" + // Pos:3106 Instruction:"VFNMADD231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xBD /r"/"RVM" { .Instruction = ND_INS_VFNMADD231SD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1202, + .Mnemonic = 1233, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -85691,6 +89927,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -85705,12 +89942,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3066 Instruction:"VFNMADD231SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xBD /r"/"RAVM" + // Pos:3107 Instruction:"VFNMADD231SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xBD /r"/"RAVM" { .Instruction = ND_INS_VFNMADD231SH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1203, + .Mnemonic = 1234, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -85719,6 +89956,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -85734,12 +89972,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3067 Instruction:"VFNMADD231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xBD /r"/"RAVM" + // Pos:3108 Instruction:"VFNMADD231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xBD /r"/"RAVM" { .Instruction = ND_INS_VFNMADD231SS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1204, + .Mnemonic = 1235, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -85748,6 +89986,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -85763,12 +90002,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3068 Instruction:"VFNMADD231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xBD /r"/"RVM" + // Pos:3109 Instruction:"VFNMADD231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xBD /r"/"RVM" { .Instruction = ND_INS_VFNMADD231SS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1204, + .Mnemonic = 1235, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -85777,6 +90016,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -85791,12 +90031,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3069 Instruction:"VFNMADDPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x79 /r is4"/"RVML" + // Pos:3110 Instruction:"VFNMADDPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x79 /r is4"/"RVML" { .Instruction = ND_INS_VFNMADDPD, .Category = ND_CAT_FMA4, .IsaSet = ND_SET_FMA4, - .Mnemonic = 1205, + .Mnemonic = 1236, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -85805,6 +90045,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -85820,12 +90061,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3070 Instruction:"VFNMADDPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x79 /r is4"/"RVLM" + // Pos:3111 Instruction:"VFNMADDPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x79 /r is4"/"RVLM" { .Instruction = ND_INS_VFNMADDPD, .Category = ND_CAT_FMA4, .IsaSet = ND_SET_FMA4, - .Mnemonic = 1205, + .Mnemonic = 1236, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -85834,6 +90075,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -85849,12 +90091,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3071 Instruction:"VFNMADDPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x78 /r is4"/"RVML" + // Pos:3112 Instruction:"VFNMADDPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x78 /r is4"/"RVML" { .Instruction = ND_INS_VFNMADDPS, .Category = ND_CAT_FMA4, .IsaSet = ND_SET_FMA4, - .Mnemonic = 1206, + .Mnemonic = 1237, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -85863,6 +90105,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -85878,12 +90121,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3072 Instruction:"VFNMADDPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x78 /r is4"/"RVLM" + // Pos:3113 Instruction:"VFNMADDPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x78 /r is4"/"RVLM" { .Instruction = ND_INS_VFNMADDPS, .Category = ND_CAT_FMA4, .IsaSet = ND_SET_FMA4, - .Mnemonic = 1206, + .Mnemonic = 1237, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -85892,6 +90135,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -85907,12 +90151,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3073 Instruction:"VFNMADDSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7B /r is4"/"RVML" + // Pos:3114 Instruction:"VFNMADDSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7B /r is4"/"RVML" { .Instruction = ND_INS_VFNMADDSD, .Category = ND_CAT_FMA4, .IsaSet = ND_SET_FMA4, - .Mnemonic = 1207, + .Mnemonic = 1238, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -85921,6 +90165,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -85936,12 +90181,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3074 Instruction:"VFNMADDSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x7B /r is4"/"RVLM" + // Pos:3115 Instruction:"VFNMADDSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x7B /r is4"/"RVLM" { .Instruction = ND_INS_VFNMADDSD, .Category = ND_CAT_FMA4, .IsaSet = ND_SET_FMA4, - .Mnemonic = 1207, + .Mnemonic = 1238, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -85950,6 +90195,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -85965,12 +90211,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3075 Instruction:"VFNMADDSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7A /r is4"/"RVML" + // Pos:3116 Instruction:"VFNMADDSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7A /r is4"/"RVML" { .Instruction = ND_INS_VFNMADDSS, .Category = ND_CAT_FMA4, .IsaSet = ND_SET_FMA4, - .Mnemonic = 1208, + .Mnemonic = 1239, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -85979,6 +90225,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -85994,12 +90241,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3076 Instruction:"VFNMADDSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x7A /r is4"/"RVLM" + // Pos:3117 Instruction:"VFNMADDSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x7A /r is4"/"RVLM" { .Instruction = ND_INS_VFNMADDSS, .Category = ND_CAT_FMA4, .IsaSet = ND_SET_FMA4, - .Mnemonic = 1208, + .Mnemonic = 1239, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -86008,6 +90255,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -86023,12 +90271,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3077 Instruction:"VFNMSUB132NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:6 p:0 l:x w:0 0x9E /r"/"RAVM" + // Pos:3118 Instruction:"VFNMSUB132NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:6 p:0 l:x w:0 0x9E /r"/"RAVM" { .Instruction = ND_INS_VFNMSUB132NEPBF16, .Category = ND_CAT_AVX10BF16, .IsaSet = ND_SET_AVX102, - .Mnemonic = 1209, + .Mnemonic = 1240, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -86037,6 +90285,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -86052,12 +90301,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3078 Instruction:"VFNMSUB132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x9E /r"/"RAVM" + // Pos:3119 Instruction:"VFNMSUB132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x9E /r"/"RAVM" { .Instruction = ND_INS_VFNMSUB132PD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1210, + .Mnemonic = 1241, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -86066,6 +90315,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -86081,12 +90331,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3079 Instruction:"VFNMSUB132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x9E /r"/"RVM" + // Pos:3120 Instruction:"VFNMSUB132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x9E /r"/"RVM" { .Instruction = ND_INS_VFNMSUB132PD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1210, + .Mnemonic = 1241, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -86095,6 +90345,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -86109,12 +90360,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3080 Instruction:"VFNMSUB132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x9E /r"/"RAVM" + // Pos:3121 Instruction:"VFNMSUB132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x9E /r"/"RAVM" { .Instruction = ND_INS_VFNMSUB132PH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1211, + .Mnemonic = 1242, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -86123,6 +90374,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -86138,12 +90390,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3081 Instruction:"VFNMSUB132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x9E /r"/"RAVM" + // Pos:3122 Instruction:"VFNMSUB132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x9E /r"/"RAVM" { .Instruction = ND_INS_VFNMSUB132PS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1212, + .Mnemonic = 1243, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -86152,6 +90404,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -86167,12 +90420,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3082 Instruction:"VFNMSUB132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x9E /r"/"RVM" + // Pos:3123 Instruction:"VFNMSUB132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x9E /r"/"RVM" { .Instruction = ND_INS_VFNMSUB132PS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1212, + .Mnemonic = 1243, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -86181,6 +90434,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -86195,12 +90449,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3083 Instruction:"VFNMSUB132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x9F /r"/"RAVM" + // Pos:3124 Instruction:"VFNMSUB132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x9F /r"/"RAVM" { .Instruction = ND_INS_VFNMSUB132SD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1213, + .Mnemonic = 1244, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -86209,6 +90463,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -86224,12 +90479,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3084 Instruction:"VFNMSUB132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x9F /r"/"RVM" + // Pos:3125 Instruction:"VFNMSUB132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x9F /r"/"RVM" { .Instruction = ND_INS_VFNMSUB132SD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1213, + .Mnemonic = 1244, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -86238,6 +90493,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -86252,12 +90508,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3085 Instruction:"VFNMSUB132SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0x9F /r"/"RAVM" + // Pos:3126 Instruction:"VFNMSUB132SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0x9F /r"/"RAVM" { .Instruction = ND_INS_VFNMSUB132SH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1214, + .Mnemonic = 1245, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -86266,6 +90522,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -86281,12 +90538,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3086 Instruction:"VFNMSUB132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x9F /r"/"RAVM" + // Pos:3127 Instruction:"VFNMSUB132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x9F /r"/"RAVM" { .Instruction = ND_INS_VFNMSUB132SS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1215, + .Mnemonic = 1246, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -86295,6 +90552,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -86310,12 +90568,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3087 Instruction:"VFNMSUB132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x9F /r"/"RVM" + // Pos:3128 Instruction:"VFNMSUB132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x9F /r"/"RVM" { .Instruction = ND_INS_VFNMSUB132SS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1215, + .Mnemonic = 1246, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -86324,6 +90582,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -86338,12 +90597,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3088 Instruction:"VFNMSUB213NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:6 p:0 l:x w:0 0xAE /r"/"RAVM" + // Pos:3129 Instruction:"VFNMSUB213NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:6 p:0 l:x w:0 0xAE /r"/"RAVM" { .Instruction = ND_INS_VFNMSUB213NEPBF16, .Category = ND_CAT_AVX10BF16, .IsaSet = ND_SET_AVX102, - .Mnemonic = 1216, + .Mnemonic = 1247, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -86352,6 +90611,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -86367,12 +90627,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3089 Instruction:"VFNMSUB213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xAE /r"/"RAVM" + // Pos:3130 Instruction:"VFNMSUB213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xAE /r"/"RAVM" { .Instruction = ND_INS_VFNMSUB213PD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1217, + .Mnemonic = 1248, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -86381,6 +90641,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -86396,12 +90657,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3090 Instruction:"VFNMSUB213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xAE /r"/"RVM" + // Pos:3131 Instruction:"VFNMSUB213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xAE /r"/"RVM" { .Instruction = ND_INS_VFNMSUB213PD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1217, + .Mnemonic = 1248, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -86410,6 +90671,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -86424,12 +90686,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3091 Instruction:"VFNMSUB213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xAE /r"/"RAVM" + // Pos:3132 Instruction:"VFNMSUB213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xAE /r"/"RAVM" { .Instruction = ND_INS_VFNMSUB213PH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1218, + .Mnemonic = 1249, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -86438,6 +90700,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -86453,12 +90716,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3092 Instruction:"VFNMSUB213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xAE /r"/"RAVM" + // Pos:3133 Instruction:"VFNMSUB213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xAE /r"/"RAVM" { .Instruction = ND_INS_VFNMSUB213PS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1219, + .Mnemonic = 1250, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -86467,6 +90730,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -86482,12 +90746,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3093 Instruction:"VFNMSUB213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xAE /r"/"RVM" + // Pos:3134 Instruction:"VFNMSUB213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xAE /r"/"RVM" { .Instruction = ND_INS_VFNMSUB213PS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1219, + .Mnemonic = 1250, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -86496,6 +90760,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -86510,12 +90775,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3094 Instruction:"VFNMSUB213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xAF /r"/"RAVM" + // Pos:3135 Instruction:"VFNMSUB213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xAF /r"/"RAVM" { .Instruction = ND_INS_VFNMSUB213SD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1220, + .Mnemonic = 1251, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -86524,6 +90789,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -86539,12 +90805,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3095 Instruction:"VFNMSUB213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xAF /r"/"RVM" + // Pos:3136 Instruction:"VFNMSUB213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xAF /r"/"RVM" { .Instruction = ND_INS_VFNMSUB213SD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1220, + .Mnemonic = 1251, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -86553,6 +90819,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -86567,12 +90834,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3096 Instruction:"VFNMSUB213SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xAF /r"/"RAVM" + // Pos:3137 Instruction:"VFNMSUB213SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xAF /r"/"RAVM" { .Instruction = ND_INS_VFNMSUB213SH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1221, + .Mnemonic = 1252, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -86581,6 +90848,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -86596,12 +90864,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3097 Instruction:"VFNMSUB213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xAF /r"/"RAVM" + // Pos:3138 Instruction:"VFNMSUB213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xAF /r"/"RAVM" { .Instruction = ND_INS_VFNMSUB213SS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1222, + .Mnemonic = 1253, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -86610,6 +90878,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -86625,12 +90894,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3098 Instruction:"VFNMSUB213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xAF /r"/"RVM" + // Pos:3139 Instruction:"VFNMSUB213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xAF /r"/"RVM" { .Instruction = ND_INS_VFNMSUB213SS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1222, + .Mnemonic = 1253, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -86639,6 +90908,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -86653,12 +90923,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3099 Instruction:"VFNMSUB231NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:6 p:0 l:x w:0 0xBE /r"/"RAVM" + // Pos:3140 Instruction:"VFNMSUB231NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:6 p:0 l:x w:0 0xBE /r"/"RAVM" { .Instruction = ND_INS_VFNMSUB231NEPBF16, .Category = ND_CAT_AVX10BF16, .IsaSet = ND_SET_AVX102, - .Mnemonic = 1223, + .Mnemonic = 1254, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -86667,6 +90937,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -86682,12 +90953,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3100 Instruction:"VFNMSUB231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xBE /r"/"RAVM" + // Pos:3141 Instruction:"VFNMSUB231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xBE /r"/"RAVM" { .Instruction = ND_INS_VFNMSUB231PD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1224, + .Mnemonic = 1255, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -86696,6 +90967,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -86711,12 +90983,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3101 Instruction:"VFNMSUB231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xBE /r"/"RVM" + // Pos:3142 Instruction:"VFNMSUB231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xBE /r"/"RVM" { .Instruction = ND_INS_VFNMSUB231PD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1224, + .Mnemonic = 1255, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -86725,6 +90997,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -86739,12 +91012,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3102 Instruction:"VFNMSUB231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xBE /r"/"RAVM" + // Pos:3143 Instruction:"VFNMSUB231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xBE /r"/"RAVM" { .Instruction = ND_INS_VFNMSUB231PH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1225, + .Mnemonic = 1256, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -86753,6 +91026,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -86768,12 +91042,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3103 Instruction:"VFNMSUB231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xBE /r"/"RAVM" + // Pos:3144 Instruction:"VFNMSUB231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xBE /r"/"RAVM" { .Instruction = ND_INS_VFNMSUB231PS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1226, + .Mnemonic = 1257, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -86782,6 +91056,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -86797,12 +91072,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3104 Instruction:"VFNMSUB231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xBE /r"/"RVM" + // Pos:3145 Instruction:"VFNMSUB231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xBE /r"/"RVM" { .Instruction = ND_INS_VFNMSUB231PS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1226, + .Mnemonic = 1257, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -86811,6 +91086,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -86825,12 +91101,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3105 Instruction:"VFNMSUB231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xBF /r"/"RAVM" + // Pos:3146 Instruction:"VFNMSUB231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xBF /r"/"RAVM" { .Instruction = ND_INS_VFNMSUB231SD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1227, + .Mnemonic = 1258, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -86839,6 +91115,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -86854,12 +91131,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3106 Instruction:"VFNMSUB231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xBF /r"/"RVM" + // Pos:3147 Instruction:"VFNMSUB231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xBF /r"/"RVM" { .Instruction = ND_INS_VFNMSUB231SD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1227, + .Mnemonic = 1258, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -86868,6 +91145,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -86882,12 +91160,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3107 Instruction:"VFNMSUB231SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xBF /r"/"RAVM" + // Pos:3148 Instruction:"VFNMSUB231SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xBF /r"/"RAVM" { .Instruction = ND_INS_VFNMSUB231SH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1228, + .Mnemonic = 1259, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -86896,6 +91174,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -86911,12 +91190,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3108 Instruction:"VFNMSUB231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xBF /r"/"RAVM" + // Pos:3149 Instruction:"VFNMSUB231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xBF /r"/"RAVM" { .Instruction = ND_INS_VFNMSUB231SS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1229, + .Mnemonic = 1260, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -86925,6 +91204,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -86940,12 +91220,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3109 Instruction:"VFNMSUB231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xBF /r"/"RVM" + // Pos:3150 Instruction:"VFNMSUB231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xBF /r"/"RVM" { .Instruction = ND_INS_VFNMSUB231SS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1229, + .Mnemonic = 1260, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -86954,6 +91234,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -86968,12 +91249,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3110 Instruction:"VFNMSUBPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x7D /r is4"/"RVML" + // Pos:3151 Instruction:"VFNMSUBPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x7D /r is4"/"RVML" { .Instruction = ND_INS_VFNMSUBPD, .Category = ND_CAT_FMA4, .IsaSet = ND_SET_FMA4, - .Mnemonic = 1230, + .Mnemonic = 1261, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -86982,6 +91263,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -86997,12 +91279,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3111 Instruction:"VFNMSUBPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x7D /r is4"/"RVLM" + // Pos:3152 Instruction:"VFNMSUBPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x7D /r is4"/"RVLM" { .Instruction = ND_INS_VFNMSUBPD, .Category = ND_CAT_FMA4, .IsaSet = ND_SET_FMA4, - .Mnemonic = 1230, + .Mnemonic = 1261, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -87011,6 +91293,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -87026,12 +91309,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3112 Instruction:"VFNMSUBPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x7C /r is4"/"RVML" + // Pos:3153 Instruction:"VFNMSUBPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x7C /r is4"/"RVML" { .Instruction = ND_INS_VFNMSUBPS, .Category = ND_CAT_FMA4, .IsaSet = ND_SET_FMA4, - .Mnemonic = 1231, + .Mnemonic = 1262, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -87040,6 +91323,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -87055,12 +91339,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3113 Instruction:"VFNMSUBPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x7C /r is4"/"RVLM" + // Pos:3154 Instruction:"VFNMSUBPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x7C /r is4"/"RVLM" { .Instruction = ND_INS_VFNMSUBPS, .Category = ND_CAT_FMA4, .IsaSet = ND_SET_FMA4, - .Mnemonic = 1231, + .Mnemonic = 1262, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -87069,6 +91353,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -87084,12 +91369,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3114 Instruction:"VFNMSUBSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7F /r is4"/"RVML" + // Pos:3155 Instruction:"VFNMSUBSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7F /r is4"/"RVML" { .Instruction = ND_INS_VFNMSUBSD, .Category = ND_CAT_FMA4, .IsaSet = ND_SET_FMA4, - .Mnemonic = 1232, + .Mnemonic = 1263, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -87098,6 +91383,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -87113,12 +91399,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3115 Instruction:"VFNMSUBSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x7F /r is4"/"RVLM" + // Pos:3156 Instruction:"VFNMSUBSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x7F /r is4"/"RVLM" { .Instruction = ND_INS_VFNMSUBSD, .Category = ND_CAT_FMA4, .IsaSet = ND_SET_FMA4, - .Mnemonic = 1232, + .Mnemonic = 1263, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -87127,6 +91413,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -87142,12 +91429,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3116 Instruction:"VFNMSUBSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7E /r is4"/"RVML" + // Pos:3157 Instruction:"VFNMSUBSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7E /r is4"/"RVML" { .Instruction = ND_INS_VFNMSUBSS, .Category = ND_CAT_FMA4, .IsaSet = ND_SET_FMA4, - .Mnemonic = 1233, + .Mnemonic = 1264, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -87156,6 +91443,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -87171,12 +91459,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3117 Instruction:"VFNMSUBSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x7E /r is4"/"RVLM" + // Pos:3158 Instruction:"VFNMSUBSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x7E /r is4"/"RVLM" { .Instruction = ND_INS_VFNMSUBSS, .Category = ND_CAT_FMA4, .IsaSet = ND_SET_FMA4, - .Mnemonic = 1233, + .Mnemonic = 1264, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -87185,6 +91473,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -87200,12 +91489,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3118 Instruction:"VFPCLASSPBF16 rKq{K},aKq,Wfv|B16,Ib" Encoding:"evex m:3 p:3 l:x w:0 0x66 /r ib"/"RAMI" + // Pos:3159 Instruction:"VFPCLASSPBF16 rKq{K},aKq,Wfv|B16,Ib" Encoding:"evex m:3 p:3 l:x w:0 0x66 /r ib"/"RAMI" { .Instruction = ND_INS_VFPCLASSPBF16, .Category = ND_CAT_AVX10BF16, .IsaSet = ND_SET_AVX102, - .Mnemonic = 1234, + .Mnemonic = 1265, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_BROADCAST, @@ -87214,6 +91503,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -87229,12 +91519,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3119 Instruction:"VFPCLASSPD rKq{K},aKq,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x66 /r ib"/"RAMI" + // Pos:3160 Instruction:"VFPCLASSPD rKq{K},aKq,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x66 /r ib"/"RAMI" { .Instruction = ND_INS_VFPCLASSPD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 1235, + .Mnemonic = 1266, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_BROADCAST, @@ -87243,6 +91533,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -87258,12 +91549,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3120 Instruction:"VFPCLASSPH rKq{K},aKq,Wfv|B16,Ib" Encoding:"evex m:3 p:0 l:x w:0 0x66 /r ib"/"RAMI" + // Pos:3161 Instruction:"VFPCLASSPH rKq{K},aKq,Wfv|B16,Ib" Encoding:"evex m:3 p:0 l:x w:0 0x66 /r ib"/"RAMI" { .Instruction = ND_INS_VFPCLASSPH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1236, + .Mnemonic = 1267, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_BROADCAST, @@ -87272,6 +91563,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -87287,12 +91579,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3121 Instruction:"VFPCLASSPS rKq{K},aKq,Wfv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x66 /r ib"/"RAMI" + // Pos:3162 Instruction:"VFPCLASSPS rKq{K},aKq,Wfv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x66 /r ib"/"RAMI" { .Instruction = ND_INS_VFPCLASSPS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 1237, + .Mnemonic = 1268, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_BROADCAST, @@ -87301,6 +91593,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -87316,12 +91609,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3122 Instruction:"VFPCLASSSD rKq{K},aKq,Wsd,Ib" Encoding:"evex m:3 p:1 l:i w:1 0x67 /r ib"/"RAMI" + // Pos:3163 Instruction:"VFPCLASSSD rKq{K},aKq,Wsd,Ib" Encoding:"evex m:3 p:1 l:i w:1 0x67 /r ib"/"RAMI" { .Instruction = ND_INS_VFPCLASSSD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 1238, + .Mnemonic = 1269, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -87330,6 +91623,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E6, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -87345,12 +91639,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3123 Instruction:"VFPCLASSSH rKq{K},aKq,Wsh,Ib" Encoding:"evex m:3 p:0 l:i w:0 0x67 /r ib"/"RAMI" + // Pos:3164 Instruction:"VFPCLASSSH rKq{K},aKq,Wsh,Ib" Encoding:"evex m:3 p:0 l:i w:0 0x67 /r ib"/"RAMI" { .Instruction = ND_INS_VFPCLASSSH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1239, + .Mnemonic = 1270, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -87359,6 +91653,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E10, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -87374,12 +91669,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3124 Instruction:"VFPCLASSSS rKq{K},aKq,Wss,Ib" Encoding:"evex m:3 p:1 l:i w:0 0x67 /r ib"/"RAMI" + // Pos:3165 Instruction:"VFPCLASSSS rKq{K},aKq,Wss,Ib" Encoding:"evex m:3 p:1 l:i w:0 0x67 /r ib"/"RAMI" { .Instruction = ND_INS_VFPCLASSSS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 1240, + .Mnemonic = 1271, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -87388,6 +91683,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E6, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -87403,12 +91699,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3125 Instruction:"VFRCZPD Vx,Wx" Encoding:"xop m:9 0x81 /r"/"RM" + // Pos:3166 Instruction:"VFRCZPD Vx,Wx" Encoding:"xop m:9 0x81 /r"/"RM" { .Instruction = ND_INS_VFRCZPD, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1241, + .Mnemonic = 1272, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -87417,6 +91713,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -87430,12 +91727,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3126 Instruction:"VFRCZPS Vx,Wx" Encoding:"xop m:9 0x80 /r"/"RM" + // Pos:3167 Instruction:"VFRCZPS Vx,Wx" Encoding:"xop m:9 0x80 /r"/"RM" { .Instruction = ND_INS_VFRCZPS, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1242, + .Mnemonic = 1273, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -87444,6 +91741,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -87457,12 +91755,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3127 Instruction:"VFRCZSD Vdq,Wsd" Encoding:"xop m:9 0x83 /r"/"RM" + // Pos:3168 Instruction:"VFRCZSD Vdq,Wsd" Encoding:"xop m:9 0x83 /r"/"RM" { .Instruction = ND_INS_VFRCZSD, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1243, + .Mnemonic = 1274, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -87471,6 +91769,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -87484,12 +91783,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3128 Instruction:"VFRCZSS Vdq,Wss" Encoding:"xop m:9 0x82 /r"/"RM" + // Pos:3169 Instruction:"VFRCZSS Vdq,Wss" Encoding:"xop m:9 0x82 /r"/"RM" { .Instruction = ND_INS_VFRCZSS, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1244, + .Mnemonic = 1275, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -87498,6 +91797,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -87511,12 +91811,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3129 Instruction:"VGATHERDPD Vfv{K},aKq,Mvm32h" Encoding:"evex m:2 p:1 l:x w:1 0x92 /r:mem vsib"/"RAM" + // Pos:3170 Instruction:"VGATHERDPD Vfv{K},aKq,Mvm32h" Encoding:"evex m:2 p:1 l:x w:1 0x92 /r:mem vsib"/"RAM" { .Instruction = ND_INS_VGATHERDPD, .Category = ND_CAT_GATHER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1245, + .Mnemonic = 1276, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -87525,6 +91825,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E12, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -87539,12 +91840,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3130 Instruction:"VGATHERDPD Vx,Mvm32h,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x92 /r:mem vsib"/"RMV" + // Pos:3171 Instruction:"VGATHERDPD Vx,Mvm32h,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x92 /r:mem vsib"/"RMV" { .Instruction = ND_INS_VGATHERDPD, .Category = ND_CAT_AVX2GATHER, .IsaSet = ND_SET_AVX2GATHER, - .Mnemonic = 1245, + .Mnemonic = 1276, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -87553,6 +91854,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_12, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -87567,12 +91869,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3131 Instruction:"VGATHERDPS Vfv{K},aKq,Mvm32n" Encoding:"evex m:2 p:1 l:x w:0 0x92 /r:mem vsib"/"RAM" + // Pos:3172 Instruction:"VGATHERDPS Vfv{K},aKq,Mvm32n" Encoding:"evex m:2 p:1 l:x w:0 0x92 /r:mem vsib"/"RAM" { .Instruction = ND_INS_VGATHERDPS, .Category = ND_CAT_GATHER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1246, + .Mnemonic = 1277, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -87581,6 +91883,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E12, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -87595,12 +91898,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3132 Instruction:"VGATHERDPS Vx,Mvm32n,Hx" Encoding:"vex m:2 p:1 l:x w:0 0x92 /r:mem vsib"/"RMV" + // Pos:3173 Instruction:"VGATHERDPS Vx,Mvm32n,Hx" Encoding:"vex m:2 p:1 l:x w:0 0x92 /r:mem vsib"/"RMV" { .Instruction = ND_INS_VGATHERDPS, .Category = ND_CAT_AVX2GATHER, .IsaSet = ND_SET_AVX2GATHER, - .Mnemonic = 1246, + .Mnemonic = 1277, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -87609,6 +91912,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_12, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -87623,12 +91927,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3133 Instruction:"VGATHERPF0DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /1:mem vsib"/"MA" + // Pos:3174 Instruction:"VGATHERPF0DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /1:mem vsib"/"MA" { .Instruction = ND_INS_VGATHERPF0DPD, .Category = ND_CAT_GATHER, .IsaSet = ND_SET_AVX512PF, - .Mnemonic = 1247, + .Mnemonic = 1278, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -87637,6 +91941,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E12NP, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -87650,12 +91955,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3134 Instruction:"VGATHERPF0DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /1:mem vsib"/"MA" + // Pos:3175 Instruction:"VGATHERPF0DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /1:mem vsib"/"MA" { .Instruction = ND_INS_VGATHERPF0DPS, .Category = ND_CAT_GATHER, .IsaSet = ND_SET_AVX512PF, - .Mnemonic = 1248, + .Mnemonic = 1279, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -87664,6 +91969,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E12NP, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -87677,12 +91983,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3135 Instruction:"VGATHERPF0QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /1:mem vsib"/"MA" + // Pos:3176 Instruction:"VGATHERPF0QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /1:mem vsib"/"MA" { .Instruction = ND_INS_VGATHERPF0QPD, .Category = ND_CAT_GATHER, .IsaSet = ND_SET_AVX512PF, - .Mnemonic = 1249, + .Mnemonic = 1280, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -87691,6 +91997,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E12NP, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -87704,12 +92011,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3136 Instruction:"VGATHERPF0QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /1:mem vsib"/"MA" + // Pos:3177 Instruction:"VGATHERPF0QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /1:mem vsib"/"MA" { .Instruction = ND_INS_VGATHERPF0QPS, .Category = ND_CAT_GATHER, .IsaSet = ND_SET_AVX512PF, - .Mnemonic = 1250, + .Mnemonic = 1281, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -87718,6 +92025,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E12NP, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -87731,12 +92039,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3137 Instruction:"VGATHERPF1DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /2:mem vsib"/"MA" + // Pos:3178 Instruction:"VGATHERPF1DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /2:mem vsib"/"MA" { .Instruction = ND_INS_VGATHERPF1DPD, .Category = ND_CAT_GATHER, .IsaSet = ND_SET_AVX512PF, - .Mnemonic = 1251, + .Mnemonic = 1282, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -87745,6 +92053,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E12NP, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -87758,12 +92067,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3138 Instruction:"VGATHERPF1DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /2:mem vsib"/"MA" + // Pos:3179 Instruction:"VGATHERPF1DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /2:mem vsib"/"MA" { .Instruction = ND_INS_VGATHERPF1DPS, .Category = ND_CAT_GATHER, .IsaSet = ND_SET_AVX512PF, - .Mnemonic = 1252, + .Mnemonic = 1283, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -87772,6 +92081,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E12NP, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -87785,12 +92095,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3139 Instruction:"VGATHERPF1QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /2:mem vsib"/"MA" + // Pos:3180 Instruction:"VGATHERPF1QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /2:mem vsib"/"MA" { .Instruction = ND_INS_VGATHERPF1QPD, .Category = ND_CAT_GATHER, .IsaSet = ND_SET_AVX512PF, - .Mnemonic = 1253, + .Mnemonic = 1284, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -87799,6 +92109,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E12NP, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -87812,12 +92123,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3140 Instruction:"VGATHERPF1QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /2:mem vsib"/"MA" + // Pos:3181 Instruction:"VGATHERPF1QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /2:mem vsib"/"MA" { .Instruction = ND_INS_VGATHERPF1QPS, .Category = ND_CAT_GATHER, .IsaSet = ND_SET_AVX512PF, - .Mnemonic = 1254, + .Mnemonic = 1285, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -87826,6 +92137,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E12NP, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -87839,12 +92151,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3141 Instruction:"VGATHERQPD Vfv{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:1 0x93 /r:mem vsib"/"RAM" + // Pos:3182 Instruction:"VGATHERQPD Vfv{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:1 0x93 /r:mem vsib"/"RAM" { .Instruction = ND_INS_VGATHERQPD, .Category = ND_CAT_GATHER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1255, + .Mnemonic = 1286, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -87853,6 +92165,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E12, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -87867,12 +92180,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3142 Instruction:"VGATHERQPD Vx,Mvm64n,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x93 /r:mem vsib"/"RMV" + // Pos:3183 Instruction:"VGATHERQPD Vx,Mvm64n,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x93 /r:mem vsib"/"RMV" { .Instruction = ND_INS_VGATHERQPD, .Category = ND_CAT_AVX2GATHER, .IsaSet = ND_SET_AVX2GATHER, - .Mnemonic = 1255, + .Mnemonic = 1286, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -87881,6 +92194,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_12, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -87895,12 +92209,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3143 Instruction:"VGATHERQPS Vhv{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:0 0x93 /r:mem vsib"/"RAM" + // Pos:3184 Instruction:"VGATHERQPS Vhv{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:0 0x93 /r:mem vsib"/"RAM" { .Instruction = ND_INS_VGATHERQPS, .Category = ND_CAT_GATHER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1256, + .Mnemonic = 1287, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -87909,6 +92223,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E12, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -87923,12 +92238,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3144 Instruction:"VGATHERQPS Vdq,Mvm64n,Hdq" Encoding:"vex m:2 p:1 l:x w:0 0x93 /r:mem vsib"/"RMV" + // Pos:3185 Instruction:"VGATHERQPS Vdq,Mvm64n,Hdq" Encoding:"vex m:2 p:1 l:x w:0 0x93 /r:mem vsib"/"RMV" { .Instruction = ND_INS_VGATHERQPS, .Category = ND_CAT_AVX2GATHER, .IsaSet = ND_SET_AVX2GATHER, - .Mnemonic = 1256, + .Mnemonic = 1287, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -87937,6 +92252,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_12, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -87951,12 +92267,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3145 Instruction:"VGETEXPPBF16 Vfv{K}{z},aKq,Wfv|B16" Encoding:"evex m:5 p:1 l:x w:0 0x42 /r"/"RAM" + // Pos:3186 Instruction:"VGETEXPPBF16 Vfv{K}{z},aKq,Wfv|B16" Encoding:"evex m:6 p:0 l:x w:0 0x42 /r"/"RAM" { .Instruction = ND_INS_VGETEXPPBF16, .Category = ND_CAT_AVX10BF16, .IsaSet = ND_SET_AVX102, - .Mnemonic = 1257, + .Mnemonic = 1288, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -87965,6 +92281,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -87979,12 +92296,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3146 Instruction:"VGETEXPPD Vfv{K}{z},aKq,Wfv|B64{sae}" Encoding:"evex m:2 p:1 l:x w:1 0x42 /r"/"RAM" + // Pos:3187 Instruction:"VGETEXPPD Vfv{K}{z},aKq,Wfv|B64{sae}" Encoding:"evex m:2 p:1 l:x w:1 0x42 /r"/"RAM" { .Instruction = ND_INS_VGETEXPPD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1258, + .Mnemonic = 1289, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -87993,6 +92310,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -88007,12 +92325,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3147 Instruction:"VGETEXPPH Vfv{K}{z},aKq,Wfv|B16{sae}" Encoding:"evex m:6 p:1 l:x w:0 0x42 /r"/"RAM" + // Pos:3188 Instruction:"VGETEXPPH Vfv{K}{z},aKq,Wfv|B16{sae}" Encoding:"evex m:6 p:1 l:x w:0 0x42 /r"/"RAM" { .Instruction = ND_INS_VGETEXPPH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1259, + .Mnemonic = 1290, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -88021,6 +92339,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -88035,12 +92354,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3148 Instruction:"VGETEXPPS Vfv{K}{z},aKq,Wfv|B32{sae}" Encoding:"evex m:2 p:1 l:x w:0 0x42 /r"/"RAM" + // Pos:3189 Instruction:"VGETEXPPS Vfv{K}{z},aKq,Wfv|B32{sae}" Encoding:"evex m:2 p:1 l:x w:0 0x42 /r"/"RAM" { .Instruction = ND_INS_VGETEXPPS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1260, + .Mnemonic = 1291, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -88049,6 +92368,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -88063,12 +92383,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3149 Instruction:"VGETEXPSD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:2 p:1 l:x w:1 0x43 /r"/"RAVM" + // Pos:3190 Instruction:"VGETEXPSD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:2 p:1 l:x w:1 0x43 /r"/"RAVM" { .Instruction = ND_INS_VGETEXPSD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1261, + .Mnemonic = 1292, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, @@ -88077,6 +92397,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -88092,12 +92413,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3150 Instruction:"VGETEXPSH Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:6 p:1 l:i w:0 0x43 /r"/"RAVM" + // Pos:3191 Instruction:"VGETEXPSH Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:6 p:1 l:i w:0 0x43 /r"/"RAVM" { .Instruction = ND_INS_VGETEXPSH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1262, + .Mnemonic = 1293, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, @@ -88106,6 +92427,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -88121,12 +92443,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3151 Instruction:"VGETEXPSS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:2 p:1 l:x w:0 0x43 /r"/"RAVM" + // Pos:3192 Instruction:"VGETEXPSS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:2 p:1 l:x w:0 0x43 /r"/"RAVM" { .Instruction = ND_INS_VGETEXPSS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1263, + .Mnemonic = 1294, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, @@ -88135,6 +92457,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -88150,12 +92473,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3152 Instruction:"VGETMANTPBF16 Vfv{K}{z},aKq,Wfv|B16,Ib" Encoding:"evex m:3 p:3 l:x w:0 0x26 /r ib"/"RAMI" + // Pos:3193 Instruction:"VGETMANTPBF16 Vfv{K}{z},aKq,Wfv|B16,Ib" Encoding:"evex m:3 p:3 l:x w:0 0x26 /r ib"/"RAMI" { .Instruction = ND_INS_VGETMANTPBF16, .Category = ND_CAT_AVX10BF16, .IsaSet = ND_SET_AVX102, - .Mnemonic = 1264, + .Mnemonic = 1295, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -88164,6 +92487,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -88179,12 +92503,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3153 Instruction:"VGETMANTPD Vfv{K}{z},aKq,Wfv|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x26 /r ib"/"RAMI" + // Pos:3194 Instruction:"VGETMANTPD Vfv{K}{z},aKq,Wfv|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x26 /r ib"/"RAMI" { .Instruction = ND_INS_VGETMANTPD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1265, + .Mnemonic = 1296, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -88193,6 +92517,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -88208,12 +92533,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3154 Instruction:"VGETMANTPH Vfv{K}{z},aKq,Wfv|B16{sae},Ib" Encoding:"evex m:3 p:0 l:x w:0 0x26 /r ib"/"RAMI" + // Pos:3195 Instruction:"VGETMANTPH Vfv{K}{z},aKq,Wfv|B16{sae},Ib" Encoding:"evex m:3 p:0 l:x w:0 0x26 /r ib"/"RAMI" { .Instruction = ND_INS_VGETMANTPH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1266, + .Mnemonic = 1297, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -88222,6 +92547,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -88237,12 +92563,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3155 Instruction:"VGETMANTPS Vfv{K}{z},aKq,Wfv|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x26 /r ib"/"RAMI" + // Pos:3196 Instruction:"VGETMANTPS Vfv{K}{z},aKq,Wfv|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x26 /r ib"/"RAMI" { .Instruction = ND_INS_VGETMANTPS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1267, + .Mnemonic = 1298, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -88251,6 +92577,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -88266,12 +92593,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3156 Instruction:"VGETMANTSD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x27 /r ib"/"RAVMI" + // Pos:3197 Instruction:"VGETMANTSD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x27 /r ib"/"RAVMI" { .Instruction = ND_INS_VGETMANTSD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1268, + .Mnemonic = 1299, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, @@ -88280,6 +92607,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -88296,12 +92624,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3157 Instruction:"VGETMANTSH Vdq{K}{z},aKq,Hdq,Wsh{sae},Ib" Encoding:"evex m:3 p:0 l:i w:0 0x27 /r ib"/"RAVMI" + // Pos:3198 Instruction:"VGETMANTSH Vdq{K}{z},aKq,Hdq,Wsh{sae},Ib" Encoding:"evex m:3 p:0 l:i w:0 0x27 /r ib"/"RAVMI" { .Instruction = ND_INS_VGETMANTSH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1269, + .Mnemonic = 1300, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, @@ -88310,6 +92638,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -88326,12 +92655,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3158 Instruction:"VGETMANTSS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x27 /r ib"/"RAVMI" + // Pos:3199 Instruction:"VGETMANTSS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x27 /r ib"/"RAVMI" { .Instruction = ND_INS_VGETMANTSS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1270, + .Mnemonic = 1301, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, @@ -88340,6 +92669,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -88356,12 +92686,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3159 Instruction:"VGF2P8AFFINEINVQB Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0xCF /r ib"/"RAVMI" + // Pos:3200 Instruction:"VGF2P8AFFINEINVQB Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0xCF /r ib"/"RAVMI" { .Instruction = ND_INS_VGF2P8AFFINEINVQB, .Category = ND_CAT_GFNI, .IsaSet = ND_SET_GFNI, - .Mnemonic = 1271, + .Mnemonic = 1302, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -88370,6 +92700,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -88386,12 +92717,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3160 Instruction:"VGF2P8AFFINEINVQB Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:1 0xCF /r ib"/"RVMI" + // Pos:3201 Instruction:"VGF2P8AFFINEINVQB Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:1 0xCF /r ib"/"RVMI" { .Instruction = ND_INS_VGF2P8AFFINEINVQB, .Category = ND_CAT_GFNI, .IsaSet = ND_SET_GFNI, - .Mnemonic = 1271, + .Mnemonic = 1302, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -88400,6 +92731,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -88415,12 +92747,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3161 Instruction:"VGF2P8AFFINEQB Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0xCE /r ib"/"RAVMI" + // Pos:3202 Instruction:"VGF2P8AFFINEQB Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0xCE /r ib"/"RAVMI" { .Instruction = ND_INS_VGF2P8AFFINEQB, .Category = ND_CAT_GFNI, .IsaSet = ND_SET_GFNI, - .Mnemonic = 1272, + .Mnemonic = 1303, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -88429,6 +92761,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -88445,12 +92778,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3162 Instruction:"VGF2P8AFFINEQB Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:1 0xCE /r ib"/"RVMI" + // Pos:3203 Instruction:"VGF2P8AFFINEQB Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:1 0xCE /r ib"/"RVMI" { .Instruction = ND_INS_VGF2P8AFFINEQB, .Category = ND_CAT_GFNI, .IsaSet = ND_SET_GFNI, - .Mnemonic = 1272, + .Mnemonic = 1303, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -88459,6 +92792,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -88474,12 +92808,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3163 Instruction:"VGF2P8MULB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0xCF /r"/"RAVM" + // Pos:3204 Instruction:"VGF2P8MULB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0xCF /r"/"RAVM" { .Instruction = ND_INS_VGF2P8MULB, .Category = ND_CAT_GFNI, .IsaSet = ND_SET_GFNI, - .Mnemonic = 1273, + .Mnemonic = 1304, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -88488,6 +92822,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -88503,12 +92838,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3164 Instruction:"VGF2P8MULB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xCF /r"/"RVM" + // Pos:3205 Instruction:"VGF2P8MULB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xCF /r"/"RVM" { .Instruction = ND_INS_VGF2P8MULB, .Category = ND_CAT_GFNI, .IsaSet = ND_SET_GFNI, - .Mnemonic = 1273, + .Mnemonic = 1304, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -88517,6 +92852,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -88531,12 +92867,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3165 Instruction:"VHADDPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x7C /r"/"RVM" + // Pos:3206 Instruction:"VHADDPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x7C /r"/"RVM" { .Instruction = ND_INS_VHADDPD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1274, + .Mnemonic = 1305, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -88545,6 +92881,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -88559,12 +92896,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3166 Instruction:"VHADDPS Vps,Hps,Wps" Encoding:"vex m:1 p:3 l:x w:i 0x7C /r"/"RVM" + // Pos:3207 Instruction:"VHADDPS Vps,Hps,Wps" Encoding:"vex m:1 p:3 l:x w:i 0x7C /r"/"RVM" { .Instruction = ND_INS_VHADDPS, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1275, + .Mnemonic = 1306, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -88573,6 +92910,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -88587,12 +92925,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3167 Instruction:"VHSUBPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x7D /r"/"RVM" + // Pos:3208 Instruction:"VHSUBPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x7D /r"/"RVM" { .Instruction = ND_INS_VHSUBPD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1276, + .Mnemonic = 1307, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -88601,6 +92939,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -88615,12 +92954,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3168 Instruction:"VHSUBPS Vps,Hps,Wps" Encoding:"vex m:1 p:3 l:x w:i 0x7D /r"/"RVM" + // Pos:3209 Instruction:"VHSUBPS Vps,Hps,Wps" Encoding:"vex m:1 p:3 l:x w:i 0x7D /r"/"RVM" { .Instruction = ND_INS_VHSUBPS, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1277, + .Mnemonic = 1308, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -88629,6 +92968,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -88643,12 +92983,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3169 Instruction:"VINSERTF128 Vqq,Hqq,Wdq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x18 /r ib"/"RVMI" + // Pos:3210 Instruction:"VINSERTF128 Vqq,Hqq,Wdq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x18 /r ib"/"RVMI" { .Instruction = ND_INS_VINSERTF128, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1278, + .Mnemonic = 1309, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -88657,6 +92997,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_6, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -88672,12 +93013,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3170 Instruction:"VINSERTF32X4 Vuv{K}{z},aKq,Huv,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x18 /r ib"/"RAVMI" + // Pos:3211 Instruction:"VINSERTF32X4 Vuv{K}{z},aKq,Huv,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x18 /r ib"/"RAVMI" { .Instruction = ND_INS_VINSERTF32X4, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1279, + .Mnemonic = 1310, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -88686,6 +93027,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E6NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -88702,12 +93044,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3171 Instruction:"VINSERTF32X8 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x1A /r ib"/"RAVMI" + // Pos:3212 Instruction:"VINSERTF32X8 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x1A /r ib"/"RAVMI" { .Instruction = ND_INS_VINSERTF32X8, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 1280, + .Mnemonic = 1311, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -88716,6 +93058,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E6NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -88732,12 +93075,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3172 Instruction:"VINSERTF64X2 Vuv{K}{z},aKq,Huv,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x18 /r ib"/"RAVMI" + // Pos:3213 Instruction:"VINSERTF64X2 Vuv{K}{z},aKq,Huv,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x18 /r ib"/"RAVMI" { .Instruction = ND_INS_VINSERTF64X2, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 1281, + .Mnemonic = 1312, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -88746,6 +93089,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E6NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -88762,12 +93106,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3173 Instruction:"VINSERTF64X4 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x1A /r ib"/"RAVMI" + // Pos:3214 Instruction:"VINSERTF64X4 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x1A /r ib"/"RAVMI" { .Instruction = ND_INS_VINSERTF64X4, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1282, + .Mnemonic = 1313, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -88776,6 +93120,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E6NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -88792,12 +93137,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3174 Instruction:"VINSERTI128 Vqq,Hqq,Wdq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x38 /r ib"/"RVMI" + // Pos:3215 Instruction:"VINSERTI128 Vqq,Hqq,Wdq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x38 /r ib"/"RVMI" { .Instruction = ND_INS_VINSERTI128, .Category = ND_CAT_AVX2, .IsaSet = ND_SET_AVX2, - .Mnemonic = 1283, + .Mnemonic = 1314, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -88806,6 +93151,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_6, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -88821,12 +93167,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3175 Instruction:"VINSERTI32X4 Vuv{K}{z},aKq,Huv,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x38 /r ib"/"RAVMI" + // Pos:3216 Instruction:"VINSERTI32X4 Vuv{K}{z},aKq,Huv,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x38 /r ib"/"RAVMI" { .Instruction = ND_INS_VINSERTI32X4, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1284, + .Mnemonic = 1315, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -88835,6 +93181,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E6NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -88851,12 +93198,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3176 Instruction:"VINSERTI32X8 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x3A /r ib"/"RAVMI" + // Pos:3217 Instruction:"VINSERTI32X8 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x3A /r ib"/"RAVMI" { .Instruction = ND_INS_VINSERTI32X8, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 1285, + .Mnemonic = 1316, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -88865,6 +93212,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E6NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -88881,12 +93229,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3177 Instruction:"VINSERTI64X2 Vuv{K}{z},aKq,Huv,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x38 /r ib"/"RAVMI" + // Pos:3218 Instruction:"VINSERTI64X2 Vuv{K}{z},aKq,Huv,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x38 /r ib"/"RAVMI" { .Instruction = ND_INS_VINSERTI64X2, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 1286, + .Mnemonic = 1317, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -88895,6 +93243,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E6NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -88911,12 +93260,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3178 Instruction:"VINSERTI64X4 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x3A /r ib"/"RAVMI" + // Pos:3219 Instruction:"VINSERTI64X4 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x3A /r ib"/"RAVMI" { .Instruction = ND_INS_VINSERTI64X4, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1287, + .Mnemonic = 1318, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -88925,6 +93274,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E6NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -88941,12 +93291,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3179 Instruction:"VINSERTPS Vdq,Hdq,Md,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x21 /r:mem ib"/"RVMI" + // Pos:3220 Instruction:"VINSERTPS Vdq,Hdq,Md,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x21 /r:mem ib"/"RVMI" { .Instruction = ND_INS_VINSERTPS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1288, + .Mnemonic = 1319, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -88955,6 +93305,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E9NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -88970,12 +93321,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3180 Instruction:"VINSERTPS Vdq,Hdq,Udq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x21 /r:reg ib"/"RVMI" + // Pos:3221 Instruction:"VINSERTPS Vdq,Hdq,Udq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x21 /r:reg ib"/"RVMI" { .Instruction = ND_INS_VINSERTPS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1288, + .Mnemonic = 1319, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -88984,6 +93335,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E9NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -88999,12 +93351,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3181 Instruction:"VINSERTPS Vdq,Hdq,Md,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x21 /r:mem ib"/"RVMI" + // Pos:3222 Instruction:"VINSERTPS Vdq,Hdq,Md,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x21 /r:mem ib"/"RVMI" { .Instruction = ND_INS_VINSERTPS, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1288, + .Mnemonic = 1319, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -89013,6 +93365,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -89028,12 +93381,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3182 Instruction:"VINSERTPS Vdq,Hdq,Udq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x21 /r:reg ib"/"RVMI" + // Pos:3223 Instruction:"VINSERTPS Vdq,Hdq,Udq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x21 /r:reg ib"/"RVMI" { .Instruction = ND_INS_VINSERTPS, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1288, + .Mnemonic = 1319, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -89042,6 +93395,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -89057,12 +93411,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3183 Instruction:"VLDDQU Vx,Mx" Encoding:"vex m:1 p:3 l:x w:i 0xF0 /r:mem"/"RM" + // Pos:3224 Instruction:"VLDDQU Vx,Mx" Encoding:"vex m:1 p:3 l:x w:i 0xF0 /r:mem"/"RM" { .Instruction = ND_INS_VLDDQU, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1289, + .Mnemonic = 1320, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -89071,6 +93425,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -89084,12 +93439,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3184 Instruction:"VLDMXCSR Md" Encoding:"vex m:1 p:0 0xAE /2:mem"/"M" + // Pos:3225 Instruction:"VLDMXCSR Md" Encoding:"vex m:1 p:0 0xAE /2:mem"/"M" { .Instruction = ND_INS_VLDMXCSR, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1290, + .Mnemonic = 1321, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -89098,6 +93453,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -89111,12 +93467,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3185 Instruction:"VMASKMOVDQU Vdq,Udq" Encoding:"vex m:1 p:1 l:0 w:i 0xF7 /r:reg"/"RM" + // Pos:3226 Instruction:"VMASKMOVDQU Vdq,Udq" Encoding:"vex m:1 p:1 l:0 w:i 0xF7 /r:reg"/"RM" { .Instruction = ND_INS_VMASKMOVDQU, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1291, + .Mnemonic = 1322, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -89125,6 +93481,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -89139,12 +93496,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3186 Instruction:"VMASKMOVPD Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:0 0x2D /r:mem"/"RVM" + // Pos:3227 Instruction:"VMASKMOVPD Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:0 0x2D /r:mem"/"RVM" { .Instruction = ND_INS_VMASKMOVPD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1292, + .Mnemonic = 1323, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -89153,6 +93510,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_6, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -89167,12 +93525,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3187 Instruction:"VMASKMOVPD Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:0 0x2F /r:mem"/"MVR" + // Pos:3228 Instruction:"VMASKMOVPD Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:0 0x2F /r:mem"/"MVR" { .Instruction = ND_INS_VMASKMOVPD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1292, + .Mnemonic = 1323, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -89181,6 +93539,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_6, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -89195,12 +93554,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3188 Instruction:"VMASKMOVPS Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:0 0x2C /r:mem"/"RVM" + // Pos:3229 Instruction:"VMASKMOVPS Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:0 0x2C /r:mem"/"RVM" { .Instruction = ND_INS_VMASKMOVPS, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1293, + .Mnemonic = 1324, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -89209,6 +93568,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_6, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -89223,12 +93583,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3189 Instruction:"VMASKMOVPS Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:0 0x2E /r:mem"/"MVR" + // Pos:3230 Instruction:"VMASKMOVPS Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:0 0x2E /r:mem"/"MVR" { .Instruction = ND_INS_VMASKMOVPS, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1293, + .Mnemonic = 1324, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -89237,6 +93597,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_6, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -89251,12 +93612,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3190 Instruction:"VMAXPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:5 p:1 l:x w:0 0x5F /r"/"RAVM" + // Pos:3231 Instruction:"VMAXPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:5 p:1 l:x w:0 0x5F /r"/"RAVM" { .Instruction = ND_INS_VMAXPBF16, .Category = ND_CAT_AVX10BF16, .IsaSet = ND_SET_AVX102, - .Mnemonic = 1294, + .Mnemonic = 1325, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -89265,6 +93626,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -89280,12 +93642,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3191 Instruction:"VMAXPD Vfv{K}{z},aKq,Hfv,Wfv|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x5F /r"/"RAVM" + // Pos:3232 Instruction:"VMAXPD Vfv{K}{z},aKq,Hfv,Wfv|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x5F /r"/"RAVM" { .Instruction = ND_INS_VMAXPD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1295, + .Mnemonic = 1326, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -89294,6 +93656,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -89309,12 +93672,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3192 Instruction:"VMAXPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5F /r"/"RVM" + // Pos:3233 Instruction:"VMAXPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5F /r"/"RVM" { .Instruction = ND_INS_VMAXPD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1295, + .Mnemonic = 1326, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -89323,6 +93686,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -89337,12 +93701,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3193 Instruction:"VMAXPH Vfv{K}{z},aKq,Hfv,Wfv|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x5F /r"/"RAVM" + // Pos:3234 Instruction:"VMAXPH Vfv{K}{z},aKq,Hfv,Wfv|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x5F /r"/"RAVM" { .Instruction = ND_INS_VMAXPH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1296, + .Mnemonic = 1327, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -89351,6 +93715,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -89366,12 +93731,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3194 Instruction:"VMAXPS Vfv{K}{z},aKq,Hfv,Wfv|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x5F /r"/"RAVM" + // Pos:3235 Instruction:"VMAXPS Vfv{K}{z},aKq,Hfv,Wfv|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x5F /r"/"RAVM" { .Instruction = ND_INS_VMAXPS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1297, + .Mnemonic = 1328, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -89380,6 +93745,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -89395,12 +93761,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3195 Instruction:"VMAXPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5F /r"/"RVM" + // Pos:3236 Instruction:"VMAXPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5F /r"/"RVM" { .Instruction = ND_INS_VMAXPS, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1297, + .Mnemonic = 1328, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -89409,6 +93775,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -89423,12 +93790,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3196 Instruction:"VMAXSD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:1 0x5F /r"/"RAVM" + // Pos:3237 Instruction:"VMAXSD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:1 0x5F /r"/"RAVM" { .Instruction = ND_INS_VMAXSD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1298, + .Mnemonic = 1329, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, @@ -89437,6 +93804,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -89452,12 +93820,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3197 Instruction:"VMAXSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5F /r"/"RVM" + // Pos:3238 Instruction:"VMAXSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5F /r"/"RVM" { .Instruction = ND_INS_VMAXSD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1298, + .Mnemonic = 1329, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -89466,6 +93834,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -89480,12 +93849,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3198 Instruction:"VMAXSH Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:0 0x5F /r"/"RAVM" + // Pos:3239 Instruction:"VMAXSH Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:0 0x5F /r"/"RAVM" { .Instruction = ND_INS_VMAXSH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1299, + .Mnemonic = 1330, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, @@ -89494,6 +93863,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -89509,12 +93879,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3199 Instruction:"VMAXSS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:0 0x5F /r"/"RAVM" + // Pos:3240 Instruction:"VMAXSS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:0 0x5F /r"/"RAVM" { .Instruction = ND_INS_VMAXSS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1300, + .Mnemonic = 1331, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, @@ -89523,6 +93893,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -89538,12 +93909,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3200 Instruction:"VMAXSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5F /r"/"RVM" + // Pos:3241 Instruction:"VMAXSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5F /r"/"RVM" { .Instruction = ND_INS_VMAXSS, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1300, + .Mnemonic = 1331, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -89552,6 +93923,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -89566,12 +93938,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3201 Instruction:"VMCALL" Encoding:"NP 0x0F 0x01 /0xC1"/"" + // Pos:3242 Instruction:"VMCALL" Encoding:"NP 0x0F 0x01 /0xC1"/"" { .Instruction = ND_INS_VMCALL, .Category = ND_CAT_VTX, .IsaSet = ND_SET_VTX, - .Mnemonic = 1301, + .Mnemonic = 1332, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -89580,6 +93952,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -89592,12 +93965,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3202 Instruction:"VMCLEAR Mq" Encoding:"0x66 0x0F 0xC7 /6:mem"/"M" + // Pos:3243 Instruction:"VMCLEAR Mq" Encoding:"0x66 0x0F 0xC7 /6:mem"/"M" { .Instruction = ND_INS_VMCLEAR, .Category = ND_CAT_VTX, .IsaSet = ND_SET_VTX, - .Mnemonic = 1302, + .Mnemonic = 1333, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, .ValidDecorators = 0, @@ -89606,6 +93979,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .SetFlags = 0, @@ -89619,12 +93993,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3203 Instruction:"VMFUNC" Encoding:"NP 0x0F 0x01 /0xD4"/"" + // Pos:3244 Instruction:"VMFUNC" Encoding:"NP 0x0F 0x01 /0xD4"/"" { .Instruction = ND_INS_VMFUNC, .Category = ND_CAT_VTX, .IsaSet = ND_SET_VTX, - .Mnemonic = 1303, + .Mnemonic = 1334, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -89633,6 +94007,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -89645,12 +94020,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3204 Instruction:"VMGEXIT" Encoding:"0xF3 0x0F 0x01 /0xD9"/"" + // Pos:3245 Instruction:"VMGEXIT" Encoding:"0xF3 0x0F 0x01 /0xD9"/"" { .Instruction = ND_INS_VMGEXIT, .Category = ND_CAT_SYSTEM, .IsaSet = ND_SET_SVM, - .Mnemonic = 1304, + .Mnemonic = 1335, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -89659,6 +94034,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -89671,12 +94047,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3205 Instruction:"VMGEXIT" Encoding:"0xF2 0x0F 0x01 /0xD9"/"" + // Pos:3246 Instruction:"VMGEXIT" Encoding:"0xF2 0x0F 0x01 /0xD9"/"" { .Instruction = ND_INS_VMGEXIT, .Category = ND_CAT_SYSTEM, .IsaSet = ND_SET_SVM, - .Mnemonic = 1304, + .Mnemonic = 1335, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -89685,6 +94061,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -89697,12 +94074,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3206 Instruction:"VMINMAXNEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16,Ib" Encoding:"evex m:3 p:3 l:x w:0 0x52 /r ib"/"RAVMI" + // Pos:3247 Instruction:"VMINMAXNEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16,Ib" Encoding:"evex m:3 p:3 l:x w:0 0x52 /r ib"/"RAVMI" { .Instruction = ND_INS_VMINMAXNEPBF16, .Category = ND_CAT_AVX10MINMAX, .IsaSet = ND_SET_AVX102, - .Mnemonic = 1305, + .Mnemonic = 1336, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -89711,6 +94088,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -89727,12 +94105,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3207 Instruction:"VMINMAXPD Vfv{K}{z},aKq,Hfv,Wfv|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x52 /r ib"/"RAVMI" + // Pos:3248 Instruction:"VMINMAXPD Vfv{K}{z},aKq,Hfv,Wfv|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x52 /r ib"/"RAVMI" { .Instruction = ND_INS_VMINMAXPD, .Category = ND_CAT_AVX10MINMAX, .IsaSet = ND_SET_AVX102, - .Mnemonic = 1306, + .Mnemonic = 1337, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -89741,6 +94119,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -89757,12 +94136,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3208 Instruction:"VMINMAXPH Vfv{K}{z},aKq,Hfv,Wfv|B16{sae},Ib" Encoding:"evex m:3 p:0 l:x w:0 0x52 /r ib"/"RAVMI" + // Pos:3249 Instruction:"VMINMAXPH Vfv{K}{z},aKq,Hfv,Wfv|B16{sae},Ib" Encoding:"evex m:3 p:0 l:x w:0 0x52 /r ib"/"RAVMI" { .Instruction = ND_INS_VMINMAXPH, .Category = ND_CAT_AVX10MINMAX, .IsaSet = ND_SET_AVX102, - .Mnemonic = 1307, + .Mnemonic = 1338, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -89771,6 +94150,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -89787,12 +94167,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3209 Instruction:"VMINMAXPS Vfv{K}{z},aKq,Hfv,Wfv|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x52 /r ib"/"RAVMI" + // Pos:3250 Instruction:"VMINMAXPS Vfv{K}{z},aKq,Hfv,Wfv|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x52 /r ib"/"RAVMI" { .Instruction = ND_INS_VMINMAXPS, .Category = ND_CAT_AVX10MINMAX, .IsaSet = ND_SET_AVX102, - .Mnemonic = 1308, + .Mnemonic = 1339, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -89801,6 +94181,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -89817,12 +94198,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3210 Instruction:"VMINMAXSD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x53 /r ib"/"RAVMI" + // Pos:3251 Instruction:"VMINMAXSD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x53 /r ib"/"RAVMI" { .Instruction = ND_INS_VMINMAXSD, .Category = ND_CAT_AVX10MINMAX, .IsaSet = ND_SET_AVX102, - .Mnemonic = 1309, + .Mnemonic = 1340, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, @@ -89831,6 +94212,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -89847,12 +94229,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3211 Instruction:"VMINMAXSH Vdq{K}{z},aKq,Hdq,Wsh{sae},Ib" Encoding:"evex m:3 p:0 l:i w:0 0x53 /r ib"/"RAVMI" + // Pos:3252 Instruction:"VMINMAXSH Vdq{K}{z},aKq,Hdq,Wsh{sae},Ib" Encoding:"evex m:3 p:0 l:i w:0 0x53 /r ib"/"RAVMI" { .Instruction = ND_INS_VMINMAXSH, .Category = ND_CAT_AVX10MINMAX, .IsaSet = ND_SET_AVX102, - .Mnemonic = 1310, + .Mnemonic = 1341, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, @@ -89861,6 +94243,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -89877,12 +94260,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3212 Instruction:"VMINMAXSS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x53 /r ib"/"RAVMI" + // Pos:3253 Instruction:"VMINMAXSS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x53 /r ib"/"RAVMI" { .Instruction = ND_INS_VMINMAXSS, .Category = ND_CAT_AVX10MINMAX, .IsaSet = ND_SET_AVX102, - .Mnemonic = 1311, + .Mnemonic = 1342, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, @@ -89891,6 +94274,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -89907,12 +94291,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3213 Instruction:"VMINPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:5 p:1 l:x w:0 0x5D /r"/"RAVM" + // Pos:3254 Instruction:"VMINPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:5 p:1 l:x w:0 0x5D /r"/"RAVM" { .Instruction = ND_INS_VMINPBF16, .Category = ND_CAT_AVX10BF16, .IsaSet = ND_SET_AVX102, - .Mnemonic = 1312, + .Mnemonic = 1343, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -89921,6 +94305,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -89936,12 +94321,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3214 Instruction:"VMINPD Vfv{K}{z},aKq,Hfv,Wfv|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x5D /r"/"RAVM" + // Pos:3255 Instruction:"VMINPD Vfv{K}{z},aKq,Hfv,Wfv|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x5D /r"/"RAVM" { .Instruction = ND_INS_VMINPD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1313, + .Mnemonic = 1344, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -89950,6 +94335,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -89965,12 +94351,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3215 Instruction:"VMINPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5D /r"/"RVM" + // Pos:3256 Instruction:"VMINPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5D /r"/"RVM" { .Instruction = ND_INS_VMINPD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1313, + .Mnemonic = 1344, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -89979,6 +94365,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -89993,12 +94380,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3216 Instruction:"VMINPH Vfv{K}{z},aKq,Hfv,Wfv|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x5D /r"/"RAVM" + // Pos:3257 Instruction:"VMINPH Vfv{K}{z},aKq,Hfv,Wfv|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x5D /r"/"RAVM" { .Instruction = ND_INS_VMINPH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1314, + .Mnemonic = 1345, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -90007,6 +94394,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -90022,12 +94410,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3217 Instruction:"VMINPS Vfv{K}{z},aKq,Hfv,Wfv|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x5D /r"/"RAVM" + // Pos:3258 Instruction:"VMINPS Vfv{K}{z},aKq,Hfv,Wfv|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x5D /r"/"RAVM" { .Instruction = ND_INS_VMINPS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1315, + .Mnemonic = 1346, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -90036,6 +94424,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -90051,12 +94440,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3218 Instruction:"VMINPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5D /r"/"RVM" + // Pos:3259 Instruction:"VMINPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5D /r"/"RVM" { .Instruction = ND_INS_VMINPS, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1315, + .Mnemonic = 1346, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -90065,6 +94454,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -90079,12 +94469,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3219 Instruction:"VMINSD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:1 0x5D /r"/"RAVM" + // Pos:3260 Instruction:"VMINSD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:1 0x5D /r"/"RAVM" { .Instruction = ND_INS_VMINSD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1316, + .Mnemonic = 1347, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, @@ -90093,6 +94483,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -90108,12 +94499,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3220 Instruction:"VMINSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5D /r"/"RVM" + // Pos:3261 Instruction:"VMINSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5D /r"/"RVM" { .Instruction = ND_INS_VMINSD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1316, + .Mnemonic = 1347, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -90122,6 +94513,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -90136,12 +94528,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3221 Instruction:"VMINSH Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:0 0x5D /r"/"RAVM" + // Pos:3262 Instruction:"VMINSH Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:0 0x5D /r"/"RAVM" { .Instruction = ND_INS_VMINSH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1317, + .Mnemonic = 1348, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, @@ -90150,6 +94542,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -90165,12 +94558,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3222 Instruction:"VMINSS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:0 0x5D /r"/"RAVM" + // Pos:3263 Instruction:"VMINSS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:0 0x5D /r"/"RAVM" { .Instruction = ND_INS_VMINSS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1318, + .Mnemonic = 1349, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, @@ -90179,6 +94572,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -90194,12 +94588,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3223 Instruction:"VMINSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5D /r"/"RVM" + // Pos:3264 Instruction:"VMINSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5D /r"/"RVM" { .Instruction = ND_INS_VMINSS, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1318, + .Mnemonic = 1349, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -90208,6 +94602,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -90222,12 +94617,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3224 Instruction:"VMLAUNCH" Encoding:"NP 0x0F 0x01 /0xC2"/"" + // Pos:3265 Instruction:"VMLAUNCH" Encoding:"NP 0x0F 0x01 /0xC2"/"" { .Instruction = ND_INS_VMLAUNCH, .Category = ND_CAT_VTX, .IsaSet = ND_SET_VTX, - .Mnemonic = 1319, + .Mnemonic = 1350, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, .ValidDecorators = 0, @@ -90236,6 +94631,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .SetFlags = 0, @@ -90248,12 +94644,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3225 Instruction:"VMLOAD" Encoding:"0x0F 0x01 /0xDA"/"" + // Pos:3266 Instruction:"VMLOAD" Encoding:"0x0F 0x01 /0xDA"/"" { .Instruction = ND_INS_VMLOAD, .Category = ND_CAT_SYSTEM, .IsaSet = ND_SET_SVM, - .Mnemonic = 1320, + .Mnemonic = 1351, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, .ValidDecorators = 0, @@ -90262,6 +94658,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -90274,12 +94671,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3226 Instruction:"VMMCALL" Encoding:"NP 0x0F 0x01 /0xD9"/"" + // Pos:3267 Instruction:"VMMCALL" Encoding:"NP 0x0F 0x01 /0xD9"/"" { .Instruction = ND_INS_VMMCALL, .Category = ND_CAT_SYSTEM, .IsaSet = ND_SET_SVM, - .Mnemonic = 1321, + .Mnemonic = 1352, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -90288,6 +94685,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -90300,12 +94698,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3227 Instruction:"VMMCALL" Encoding:"0x66 0x0F 0x01 /0xD9"/"" + // Pos:3268 Instruction:"VMMCALL" Encoding:"0x66 0x0F 0x01 /0xD9"/"" { .Instruction = ND_INS_VMMCALL, .Category = ND_CAT_SYSTEM, .IsaSet = ND_SET_SVM, - .Mnemonic = 1321, + .Mnemonic = 1352, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -90314,6 +94712,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -90326,12 +94725,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3228 Instruction:"VMOVAPD Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:1 l:x w:1 0x28 /r"/"RAM" + // Pos:3269 Instruction:"VMOVAPD Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:1 l:x w:1 0x28 /r"/"RAM" { .Instruction = ND_INS_VMOVAPD, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1322, + .Mnemonic = 1353, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -90340,6 +94739,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E1, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -90354,12 +94754,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3229 Instruction:"VMOVAPD Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:1 l:x w:1 0x29 /r"/"MAR" + // Pos:3270 Instruction:"VMOVAPD Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:1 l:x w:1 0x29 /r"/"MAR" { .Instruction = ND_INS_VMOVAPD, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1322, + .Mnemonic = 1353, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -90368,6 +94768,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E1, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -90382,12 +94783,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3230 Instruction:"VMOVAPD Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x28 /r"/"RM" + // Pos:3271 Instruction:"VMOVAPD Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x28 /r"/"RM" { .Instruction = ND_INS_VMOVAPD, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX, - .Mnemonic = 1322, + .Mnemonic = 1353, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -90396,6 +94797,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_1, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -90409,12 +94811,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3231 Instruction:"VMOVAPD Wx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x29 /r"/"MR" + // Pos:3272 Instruction:"VMOVAPD Wx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x29 /r"/"MR" { .Instruction = ND_INS_VMOVAPD, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX, - .Mnemonic = 1322, + .Mnemonic = 1353, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -90423,6 +94825,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_1, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -90436,12 +94839,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3232 Instruction:"VMOVAPS Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:0 l:x w:0 0x28 /r"/"RAM" + // Pos:3273 Instruction:"VMOVAPS Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:0 l:x w:0 0x28 /r"/"RAM" { .Instruction = ND_INS_VMOVAPS, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1323, + .Mnemonic = 1354, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -90450,6 +94853,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E1, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -90464,12 +94868,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3233 Instruction:"VMOVAPS Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:0 l:x w:0 0x29 /r"/"MAR" + // Pos:3274 Instruction:"VMOVAPS Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:0 l:x w:0 0x29 /r"/"MAR" { .Instruction = ND_INS_VMOVAPS, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1323, + .Mnemonic = 1354, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -90478,6 +94882,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E1, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -90492,12 +94897,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3234 Instruction:"VMOVAPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x28 /r"/"RM" + // Pos:3275 Instruction:"VMOVAPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x28 /r"/"RM" { .Instruction = ND_INS_VMOVAPS, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX, - .Mnemonic = 1323, + .Mnemonic = 1354, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -90506,6 +94911,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_1, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -90519,12 +94925,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3235 Instruction:"VMOVAPS Wx,Vx" Encoding:"vex m:1 p:0 l:x w:i 0x29 /r"/"MR" + // Pos:3276 Instruction:"VMOVAPS Wx,Vx" Encoding:"vex m:1 p:0 l:x w:i 0x29 /r"/"MR" { .Instruction = ND_INS_VMOVAPS, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX, - .Mnemonic = 1323, + .Mnemonic = 1354, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -90533,6 +94939,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_1, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -90546,12 +94953,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3236 Instruction:"VMOVD Vdq,Ed" Encoding:"evex m:1 p:1 l:0 w:0 0x6E /r"/"RM" + // Pos:3277 Instruction:"VMOVD Vdq,Ed" Encoding:"evex m:1 p:1 l:0 w:0 0x6E /r"/"RM" { .Instruction = ND_INS_VMOVD, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1324, + .Mnemonic = 1355, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -90560,6 +94967,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E9NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -90573,12 +94981,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3237 Instruction:"VMOVD Ey,Vdq" Encoding:"evex m:1 p:1 l:0 w:0 0x7E /r"/"MR" + // Pos:3278 Instruction:"VMOVD Ey,Vdq" Encoding:"evex m:1 p:1 l:0 w:0 0x7E /r"/"MR" { .Instruction = ND_INS_VMOVD, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1324, + .Mnemonic = 1355, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -90587,6 +94995,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E9NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -90600,12 +95009,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3238 Instruction:"VMOVD Vdq,Wd" Encoding:"evex m:1 p:2 l:0 w:0 0x7E /r"/"RM" + // Pos:3279 Instruction:"VMOVD Vdq,Wd" Encoding:"evex m:1 p:2 l:0 w:0 0x7E /r"/"RM" { .Instruction = ND_INS_VMOVD, .Category = ND_CAT_AVX10PARTCOPY, .IsaSet = ND_SET_AVX102, - .Mnemonic = 1324, + .Mnemonic = 1355, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -90614,6 +95023,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E9NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -90627,12 +95037,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3239 Instruction:"VMOVD Wd,Vdq" Encoding:"evex m:1 p:1 l:0 w:0 0xD6 /r"/"MR" + // Pos:3280 Instruction:"VMOVD Wd,Vdq" Encoding:"evex m:1 p:1 l:0 w:0 0xD6 /r"/"MR" { .Instruction = ND_INS_VMOVD, .Category = ND_CAT_AVX10PARTCOPY, .IsaSet = ND_SET_AVX102, - .Mnemonic = 1324, + .Mnemonic = 1355, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -90641,6 +95051,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E9NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -90654,12 +95065,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3240 Instruction:"VMOVD Vdq,Ey" Encoding:"vex m:1 p:1 l:0 w:0 0x6E /r"/"RM" + // Pos:3281 Instruction:"VMOVD Vdq,Ey" Encoding:"vex m:1 p:1 l:0 w:0 0x6E /r"/"RM" { .Instruction = ND_INS_VMOVD, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX, - .Mnemonic = 1324, + .Mnemonic = 1355, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -90668,6 +95079,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -90681,12 +95093,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3241 Instruction:"VMOVD Ey,Vd" Encoding:"vex m:1 p:1 l:0 w:0 0x7E /r"/"MR" + // Pos:3282 Instruction:"VMOVD Ey,Vd" Encoding:"vex m:1 p:1 l:0 w:0 0x7E /r"/"MR" { .Instruction = ND_INS_VMOVD, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX, - .Mnemonic = 1324, + .Mnemonic = 1355, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -90695,6 +95107,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -90708,12 +95121,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3242 Instruction:"VMOVDDUP Vdq{K}{z},aKq,Wq" Encoding:"evex m:1 p:3 l:0 w:1 0x12 /r"/"RAM" + // Pos:3283 Instruction:"VMOVDDUP Vdq{K}{z},aKq,Wq" Encoding:"evex m:1 p:3 l:0 w:1 0x12 /r"/"RAM" { .Instruction = ND_INS_VMOVDDUP, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1325, + .Mnemonic = 1356, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -90722,6 +95135,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E5NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -90736,12 +95150,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3243 Instruction:"VMOVDDUP Vqq{K}{z},aKq,Wqq" Encoding:"evex m:1 p:3 l:1 w:1 0x12 /r"/"RAM" + // Pos:3284 Instruction:"VMOVDDUP Vqq{K}{z},aKq,Wqq" Encoding:"evex m:1 p:3 l:1 w:1 0x12 /r"/"RAM" { .Instruction = ND_INS_VMOVDDUP, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1325, + .Mnemonic = 1356, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -90750,6 +95164,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E5NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -90764,12 +95179,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3244 Instruction:"VMOVDDUP Voq{K}{z},aKq,Woq" Encoding:"evex m:1 p:3 l:2 w:1 0x12 /r"/"RAM" + // Pos:3285 Instruction:"VMOVDDUP Voq{K}{z},aKq,Woq" Encoding:"evex m:1 p:3 l:2 w:1 0x12 /r"/"RAM" { .Instruction = ND_INS_VMOVDDUP, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1325, + .Mnemonic = 1356, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -90778,6 +95193,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E5NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -90792,12 +95208,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3245 Instruction:"VMOVDDUP Vdq,Wq" Encoding:"vex m:1 p:3 l:0 w:i 0x12 /r"/"RM" + // Pos:3286 Instruction:"VMOVDDUP Vdq,Wq" Encoding:"vex m:1 p:3 l:0 w:i 0x12 /r"/"RM" { .Instruction = ND_INS_VMOVDDUP, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX, - .Mnemonic = 1325, + .Mnemonic = 1356, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -90806,6 +95222,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -90819,12 +95236,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3246 Instruction:"VMOVDDUP Vqq,Wqq" Encoding:"vex m:1 p:3 l:1 w:i 0x12 /r"/"RM" + // Pos:3287 Instruction:"VMOVDDUP Vqq,Wqq" Encoding:"vex m:1 p:3 l:1 w:i 0x12 /r"/"RM" { .Instruction = ND_INS_VMOVDDUP, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX, - .Mnemonic = 1325, + .Mnemonic = 1356, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -90833,6 +95250,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -90846,12 +95264,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3247 Instruction:"VMOVDQA Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6F /r"/"RM" + // Pos:3288 Instruction:"VMOVDQA Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6F /r"/"RM" { .Instruction = ND_INS_VMOVDQA, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX, - .Mnemonic = 1326, + .Mnemonic = 1357, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -90860,6 +95278,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_1, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -90873,12 +95292,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3248 Instruction:"VMOVDQA Wx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x7F /r"/"MR" + // Pos:3289 Instruction:"VMOVDQA Wx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x7F /r"/"MR" { .Instruction = ND_INS_VMOVDQA, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX, - .Mnemonic = 1326, + .Mnemonic = 1357, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -90887,6 +95306,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_1, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -90900,12 +95320,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3249 Instruction:"VMOVDQA32 Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:1 l:x w:0 0x6F /r"/"RAM" + // Pos:3290 Instruction:"VMOVDQA32 Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:1 l:x w:0 0x6F /r"/"RAM" { .Instruction = ND_INS_VMOVDQA32, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1327, + .Mnemonic = 1358, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -90914,6 +95334,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E1, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -90928,12 +95349,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3250 Instruction:"VMOVDQA32 Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:1 l:x w:0 0x7F /r"/"MAR" + // Pos:3291 Instruction:"VMOVDQA32 Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:1 l:x w:0 0x7F /r"/"MAR" { .Instruction = ND_INS_VMOVDQA32, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1327, + .Mnemonic = 1358, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -90942,6 +95363,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E1, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -90956,12 +95378,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3251 Instruction:"VMOVDQA64 Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:1 l:x w:1 0x6F /r"/"RAM" + // Pos:3292 Instruction:"VMOVDQA64 Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:1 l:x w:1 0x6F /r"/"RAM" { .Instruction = ND_INS_VMOVDQA64, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1328, + .Mnemonic = 1359, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -90970,6 +95392,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E1, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -90984,12 +95407,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3252 Instruction:"VMOVDQA64 Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:1 l:x w:1 0x7F /r"/"MAR" + // Pos:3293 Instruction:"VMOVDQA64 Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:1 l:x w:1 0x7F /r"/"MAR" { .Instruction = ND_INS_VMOVDQA64, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1328, + .Mnemonic = 1359, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -90998,6 +95421,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E1, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -91012,12 +95436,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3253 Instruction:"VMOVDQU Vx,Wx" Encoding:"vex m:1 p:2 l:x w:i 0x6F /r"/"RM" + // Pos:3294 Instruction:"VMOVDQU Vx,Wx" Encoding:"vex m:1 p:2 l:x w:i 0x6F /r"/"RM" { .Instruction = ND_INS_VMOVDQU, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX, - .Mnemonic = 1329, + .Mnemonic = 1360, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -91026,6 +95450,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -91039,12 +95464,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3254 Instruction:"VMOVDQU Wx,Vx" Encoding:"vex m:1 p:2 l:x w:i 0x7F /r"/"MR" + // Pos:3295 Instruction:"VMOVDQU Wx,Vx" Encoding:"vex m:1 p:2 l:x w:i 0x7F /r"/"MR" { .Instruction = ND_INS_VMOVDQU, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX, - .Mnemonic = 1329, + .Mnemonic = 1360, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -91053,6 +95478,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -91066,12 +95492,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3255 Instruction:"VMOVDQU16 Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:3 l:x w:1 0x6F /r"/"RAM" + // Pos:3296 Instruction:"VMOVDQU16 Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:3 l:x w:1 0x6F /r"/"RAM" { .Instruction = ND_INS_VMOVDQU16, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1330, + .Mnemonic = 1361, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -91080,6 +95506,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4nb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -91094,12 +95521,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3256 Instruction:"VMOVDQU16 Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:3 l:x w:1 0x7F /r"/"MAR" + // Pos:3297 Instruction:"VMOVDQU16 Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:3 l:x w:1 0x7F /r"/"MAR" { .Instruction = ND_INS_VMOVDQU16, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1330, + .Mnemonic = 1361, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -91108,6 +95535,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4nb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -91122,12 +95550,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3257 Instruction:"VMOVDQU32 Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:2 l:x w:0 0x6F /r"/"RAM" + // Pos:3298 Instruction:"VMOVDQU32 Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:2 l:x w:0 0x6F /r"/"RAM" { .Instruction = ND_INS_VMOVDQU32, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1331, + .Mnemonic = 1362, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -91136,6 +95564,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4nb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -91150,12 +95579,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3258 Instruction:"VMOVDQU32 Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:2 l:x w:0 0x7F /r"/"MAR" + // Pos:3299 Instruction:"VMOVDQU32 Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:2 l:x w:0 0x7F /r"/"MAR" { .Instruction = ND_INS_VMOVDQU32, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1331, + .Mnemonic = 1362, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -91164,6 +95593,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4nb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -91178,12 +95608,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3259 Instruction:"VMOVDQU64 Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:2 l:x w:1 0x6F /r"/"RAM" + // Pos:3300 Instruction:"VMOVDQU64 Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:2 l:x w:1 0x6F /r"/"RAM" { .Instruction = ND_INS_VMOVDQU64, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1332, + .Mnemonic = 1363, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -91192,6 +95622,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4nb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -91206,12 +95637,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3260 Instruction:"VMOVDQU64 Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:2 l:x w:1 0x7F /r"/"MAR" + // Pos:3301 Instruction:"VMOVDQU64 Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:2 l:x w:1 0x7F /r"/"MAR" { .Instruction = ND_INS_VMOVDQU64, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1332, + .Mnemonic = 1363, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -91220,6 +95651,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4nb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -91234,12 +95666,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3261 Instruction:"VMOVDQU8 Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:3 l:x w:0 0x6F /r"/"RAM" + // Pos:3302 Instruction:"VMOVDQU8 Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:3 l:x w:0 0x6F /r"/"RAM" { .Instruction = ND_INS_VMOVDQU8, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1333, + .Mnemonic = 1364, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -91248,6 +95680,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4nb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -91262,12 +95695,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3262 Instruction:"VMOVDQU8 Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:3 l:x w:0 0x7F /r"/"MAR" + // Pos:3303 Instruction:"VMOVDQU8 Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:3 l:x w:0 0x7F /r"/"MAR" { .Instruction = ND_INS_VMOVDQU8, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1333, + .Mnemonic = 1364, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -91276,6 +95709,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4nb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -91290,12 +95724,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3263 Instruction:"VMOVHLPS Vdq,Hdq,Udq" Encoding:"evex m:1 p:0 l:0 w:0 0x12 /r:reg"/"RVM" + // Pos:3304 Instruction:"VMOVHLPS Vdq,Hdq,Udq" Encoding:"evex m:1 p:0 l:0 w:0 0x12 /r:reg"/"RVM" { .Instruction = ND_INS_VMOVHLPS, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1334, + .Mnemonic = 1365, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -91304,6 +95738,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E7NM, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -91318,12 +95753,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3264 Instruction:"VMOVHLPS Vdq,Hdq,Udq" Encoding:"vex m:1 p:0 l:0 w:i 0x12 /r:reg"/"RVM" + // Pos:3305 Instruction:"VMOVHLPS Vdq,Hdq,Udq" Encoding:"vex m:1 p:0 l:0 w:i 0x12 /r:reg"/"RVM" { .Instruction = ND_INS_VMOVHLPS, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1334, + .Mnemonic = 1365, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -91332,6 +95767,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_7, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -91346,12 +95782,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3265 Instruction:"VMOVHPD Vdq,Hdq,Mq" Encoding:"evex m:1 p:1 l:0 w:1 0x16 /r:mem"/"RVM" + // Pos:3306 Instruction:"VMOVHPD Vdq,Hdq,Mq" Encoding:"evex m:1 p:1 l:0 w:1 0x16 /r:mem"/"RVM" { .Instruction = ND_INS_VMOVHPD, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1335, + .Mnemonic = 1366, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -91360,6 +95796,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E9NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -91374,12 +95811,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3266 Instruction:"VMOVHPD Mq,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0x17 /r:mem"/"MR" + // Pos:3307 Instruction:"VMOVHPD Mq,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0x17 /r:mem"/"MR" { .Instruction = ND_INS_VMOVHPD, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1335, + .Mnemonic = 1366, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -91388,6 +95825,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E9NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -91401,12 +95839,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3267 Instruction:"VMOVHPD Vdq,Hdq,Mq" Encoding:"vex m:1 p:1 l:0 w:i 0x16 /r:mem"/"RVM" + // Pos:3308 Instruction:"VMOVHPD Vdq,Hdq,Mq" Encoding:"vex m:1 p:1 l:0 w:i 0x16 /r:mem"/"RVM" { .Instruction = ND_INS_VMOVHPD, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX, - .Mnemonic = 1335, + .Mnemonic = 1366, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -91415,6 +95853,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -91429,12 +95868,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3268 Instruction:"VMOVHPD Mq,Vdq" Encoding:"vex m:1 p:1 l:0 w:i 0x17 /r:mem"/"MR" + // Pos:3309 Instruction:"VMOVHPD Mq,Vdq" Encoding:"vex m:1 p:1 l:0 w:i 0x17 /r:mem"/"MR" { .Instruction = ND_INS_VMOVHPD, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX, - .Mnemonic = 1335, + .Mnemonic = 1366, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -91443,6 +95882,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -91456,12 +95896,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3269 Instruction:"VMOVHPS Vdq,Hdq,Mq" Encoding:"evex m:1 p:0 l:0 w:0 0x16 /r:mem"/"RVM" + // Pos:3310 Instruction:"VMOVHPS Vdq,Hdq,Mq" Encoding:"evex m:1 p:0 l:0 w:0 0x16 /r:mem"/"RVM" { .Instruction = ND_INS_VMOVHPS, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1336, + .Mnemonic = 1367, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -91470,6 +95910,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E9NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -91484,12 +95925,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3270 Instruction:"VMOVHPS Mq,Vdq" Encoding:"evex m:1 p:0 l:0 w:0 0x17 /r:mem"/"MR" + // Pos:3311 Instruction:"VMOVHPS Mq,Vdq" Encoding:"evex m:1 p:0 l:0 w:0 0x17 /r:mem"/"MR" { .Instruction = ND_INS_VMOVHPS, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1336, + .Mnemonic = 1367, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -91498,6 +95939,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E9NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -91511,12 +95953,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3271 Instruction:"VMOVHPS Vdq,Hdq,Mq" Encoding:"vex m:1 p:0 l:0 w:i 0x16 /r:mem"/"RVM" + // Pos:3312 Instruction:"VMOVHPS Vdq,Hdq,Mq" Encoding:"vex m:1 p:0 l:0 w:i 0x16 /r:mem"/"RVM" { .Instruction = ND_INS_VMOVHPS, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX, - .Mnemonic = 1336, + .Mnemonic = 1367, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -91525,6 +95967,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -91539,12 +95982,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3272 Instruction:"VMOVHPS Mq,Vdq" Encoding:"vex m:1 p:0 l:0 w:i 0x17 /r:mem"/"MR" + // Pos:3313 Instruction:"VMOVHPS Mq,Vdq" Encoding:"vex m:1 p:0 l:0 w:i 0x17 /r:mem"/"MR" { .Instruction = ND_INS_VMOVHPS, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX, - .Mnemonic = 1336, + .Mnemonic = 1367, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -91553,6 +95996,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -91566,12 +96010,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3273 Instruction:"VMOVLHPS Vdq,Hdq,Udq" Encoding:"evex m:1 p:0 l:0 w:0 0x16 /r:reg"/"RVM" + // Pos:3314 Instruction:"VMOVLHPS Vdq,Hdq,Udq" Encoding:"evex m:1 p:0 l:0 w:0 0x16 /r:reg"/"RVM" { .Instruction = ND_INS_VMOVLHPS, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1337, + .Mnemonic = 1368, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -91580,6 +96024,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E7NM, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -91594,12 +96039,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3274 Instruction:"VMOVLHPS Vdq,Hdq,Udq" Encoding:"vex m:1 p:0 l:0 w:i 0x16 /r:reg"/"RVM" + // Pos:3315 Instruction:"VMOVLHPS Vdq,Hdq,Udq" Encoding:"vex m:1 p:0 l:0 w:i 0x16 /r:reg"/"RVM" { .Instruction = ND_INS_VMOVLHPS, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1337, + .Mnemonic = 1368, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -91608,6 +96053,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_7, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -91622,12 +96068,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3275 Instruction:"VMOVLPD Vdq,Hdq,Mq" Encoding:"evex m:1 p:1 l:0 w:1 0x12 /r:mem"/"RVM" + // Pos:3316 Instruction:"VMOVLPD Vdq,Hdq,Mq" Encoding:"evex m:1 p:1 l:0 w:1 0x12 /r:mem"/"RVM" { .Instruction = ND_INS_VMOVLPD, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1338, + .Mnemonic = 1369, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -91636,6 +96082,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E9NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -91650,12 +96097,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3276 Instruction:"VMOVLPD Mq,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0x13 /r:mem"/"MR" + // Pos:3317 Instruction:"VMOVLPD Mq,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0x13 /r:mem"/"MR" { .Instruction = ND_INS_VMOVLPD, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1338, + .Mnemonic = 1369, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -91664,6 +96111,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E9NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -91677,12 +96125,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3277 Instruction:"VMOVLPD Vdq,Hdq,Mq" Encoding:"vex m:1 p:1 l:0 w:i 0x12 /r:mem"/"RVM" + // Pos:3318 Instruction:"VMOVLPD Vdq,Hdq,Mq" Encoding:"vex m:1 p:1 l:0 w:i 0x12 /r:mem"/"RVM" { .Instruction = ND_INS_VMOVLPD, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX, - .Mnemonic = 1338, + .Mnemonic = 1369, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -91691,6 +96139,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -91705,12 +96154,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3278 Instruction:"VMOVLPD Mq,Vdq" Encoding:"vex m:1 p:1 l:0 w:i 0x13 /r:mem"/"MR" + // Pos:3319 Instruction:"VMOVLPD Mq,Vdq" Encoding:"vex m:1 p:1 l:0 w:i 0x13 /r:mem"/"MR" { .Instruction = ND_INS_VMOVLPD, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX, - .Mnemonic = 1338, + .Mnemonic = 1369, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -91719,6 +96168,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -91732,12 +96182,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3279 Instruction:"VMOVLPS Vdq,Hdq,Mq" Encoding:"evex m:1 p:0 l:0 w:0 0x12 /r:mem"/"RVM" + // Pos:3320 Instruction:"VMOVLPS Vdq,Hdq,Mq" Encoding:"evex m:1 p:0 l:0 w:0 0x12 /r:mem"/"RVM" { .Instruction = ND_INS_VMOVLPS, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1339, + .Mnemonic = 1370, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -91746,6 +96196,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E9NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -91760,12 +96211,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3280 Instruction:"VMOVLPS Mq,Vdq" Encoding:"evex m:1 p:0 l:0 w:0 0x13 /r:mem"/"MR" + // Pos:3321 Instruction:"VMOVLPS Mq,Vdq" Encoding:"evex m:1 p:0 l:0 w:0 0x13 /r:mem"/"MR" { .Instruction = ND_INS_VMOVLPS, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1339, + .Mnemonic = 1370, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -91774,6 +96225,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E9NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -91787,12 +96239,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3281 Instruction:"VMOVLPS Vdq,Hdq,Mq" Encoding:"vex m:1 p:0 l:0 w:i 0x12 /r:mem"/"RVM" + // Pos:3322 Instruction:"VMOVLPS Vdq,Hdq,Mq" Encoding:"vex m:1 p:0 l:0 w:i 0x12 /r:mem"/"RVM" { .Instruction = ND_INS_VMOVLPS, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX, - .Mnemonic = 1339, + .Mnemonic = 1370, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -91801,6 +96253,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -91815,12 +96268,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3282 Instruction:"VMOVLPS Mq,Vdq" Encoding:"vex m:1 p:0 l:0 w:i 0x13 /r:mem"/"MR" + // Pos:3323 Instruction:"VMOVLPS Mq,Vdq" Encoding:"vex m:1 p:0 l:0 w:i 0x13 /r:mem"/"MR" { .Instruction = ND_INS_VMOVLPS, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX, - .Mnemonic = 1339, + .Mnemonic = 1370, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -91829,6 +96282,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -91842,12 +96296,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3283 Instruction:"VMOVMSKPD Gy,Ux" Encoding:"vex m:1 p:1 l:x w:i 0x50 /r:reg"/"RM" + // Pos:3324 Instruction:"VMOVMSKPD Gy,Ux" Encoding:"vex m:1 p:1 l:x w:i 0x50 /r:reg"/"RM" { .Instruction = ND_INS_VMOVMSKPD, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX, - .Mnemonic = 1340, + .Mnemonic = 1371, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -91856,6 +96310,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_7, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -91869,12 +96324,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3284 Instruction:"VMOVMSKPS Gy,Ux" Encoding:"vex m:1 p:0 l:x w:i 0x50 /r:reg"/"RM" + // Pos:3325 Instruction:"VMOVMSKPS Gy,Ux" Encoding:"vex m:1 p:0 l:x w:i 0x50 /r:reg"/"RM" { .Instruction = ND_INS_VMOVMSKPS, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX, - .Mnemonic = 1341, + .Mnemonic = 1372, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -91883,6 +96338,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_7, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -91896,12 +96352,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3285 Instruction:"VMOVNTDQ Mfv,Vfv" Encoding:"evex m:1 p:1 l:x w:0 0xE7 /r:mem"/"MR" + // Pos:3326 Instruction:"VMOVNTDQ Mfv,Vfv" Encoding:"evex m:1 p:1 l:x w:0 0xE7 /r:mem"/"MR" { .Instruction = ND_INS_VMOVNTDQ, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1342, + .Mnemonic = 1373, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -91910,6 +96366,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E1NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -91923,12 +96380,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3286 Instruction:"VMOVNTDQ Mx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0xE7 /r:mem"/"MR" + // Pos:3327 Instruction:"VMOVNTDQ Mx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0xE7 /r:mem"/"MR" { .Instruction = ND_INS_VMOVNTDQ, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1342, + .Mnemonic = 1373, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -91937,6 +96394,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_1, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -91950,12 +96408,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3287 Instruction:"VMOVNTDQA Vfv,Mfv" Encoding:"evex m:2 p:1 l:x w:0 0x2A /r:mem"/"RM" + // Pos:3328 Instruction:"VMOVNTDQA Vfv,Mfv" Encoding:"evex m:2 p:1 l:x w:0 0x2A /r:mem"/"RM" { .Instruction = ND_INS_VMOVNTDQA, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1343, + .Mnemonic = 1374, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -91964,6 +96422,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E1NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -91977,12 +96436,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3288 Instruction:"VMOVNTDQA Vx,Mx" Encoding:"vex m:2 p:1 l:x w:i 0x2A /r:mem"/"RM" + // Pos:3329 Instruction:"VMOVNTDQA Vx,Mx" Encoding:"vex m:2 p:1 l:x w:i 0x2A /r:mem"/"RM" { .Instruction = ND_INS_VMOVNTDQA, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1343, + .Mnemonic = 1374, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -91991,6 +96450,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_1, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -92004,12 +96464,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3289 Instruction:"VMOVNTPD Mfv,Vfv" Encoding:"evex m:1 p:1 l:x w:1 0x2B /r:mem"/"MR" + // Pos:3330 Instruction:"VMOVNTPD Mfv,Vfv" Encoding:"evex m:1 p:1 l:x w:1 0x2B /r:mem"/"MR" { .Instruction = ND_INS_VMOVNTPD, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1344, + .Mnemonic = 1375, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -92018,6 +96478,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E1NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -92031,12 +96492,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3290 Instruction:"VMOVNTPD Mx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x2B /r:mem"/"MR" + // Pos:3331 Instruction:"VMOVNTPD Mx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x2B /r:mem"/"MR" { .Instruction = ND_INS_VMOVNTPD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1344, + .Mnemonic = 1375, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -92045,6 +96506,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_1, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -92058,12 +96520,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3291 Instruction:"VMOVNTPS Mfv,Vfv" Encoding:"evex m:1 p:0 l:x w:0 0x2B /r:mem"/"MR" + // Pos:3332 Instruction:"VMOVNTPS Mfv,Vfv" Encoding:"evex m:1 p:0 l:x w:0 0x2B /r:mem"/"MR" { .Instruction = ND_INS_VMOVNTPS, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1345, + .Mnemonic = 1376, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -92072,6 +96534,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E1NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -92085,12 +96548,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3292 Instruction:"VMOVNTPS Mx,Vx" Encoding:"vex m:1 p:0 l:x w:i 0x2B /r:mem"/"MR" + // Pos:3333 Instruction:"VMOVNTPS Mx,Vx" Encoding:"vex m:1 p:0 l:x w:i 0x2B /r:mem"/"MR" { .Instruction = ND_INS_VMOVNTPS, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1345, + .Mnemonic = 1376, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -92099,6 +96562,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_1, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -92112,12 +96576,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3293 Instruction:"VMOVQ Vdq,Eq" Encoding:"evex m:1 p:1 l:0 w:1 0x6E /r"/"RM" + // Pos:3334 Instruction:"VMOVQ Vdq,Eq" Encoding:"evex m:1 p:1 l:0 w:1 0x6E /r"/"RM" { .Instruction = ND_INS_VMOVQ, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1346, + .Mnemonic = 1377, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -92126,6 +96590,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E9NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -92139,12 +96604,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3294 Instruction:"VMOVQ Ey,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0x7E /r"/"MR" + // Pos:3335 Instruction:"VMOVQ Ey,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0x7E /r"/"MR" { .Instruction = ND_INS_VMOVQ, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1346, + .Mnemonic = 1377, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -92153,6 +96618,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E9NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -92166,12 +96632,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3295 Instruction:"VMOVQ Vdq,Wq" Encoding:"evex m:1 p:2 l:0 w:1 0x7E /r"/"RM" + // Pos:3336 Instruction:"VMOVQ Vdq,Wq" Encoding:"evex m:1 p:2 l:0 w:1 0x7E /r"/"RM" { .Instruction = ND_INS_VMOVQ, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1346, + .Mnemonic = 1377, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -92180,6 +96646,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E9NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -92193,12 +96660,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3296 Instruction:"VMOVQ Wq,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0xD6 /r"/"MR" + // Pos:3337 Instruction:"VMOVQ Wq,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0xD6 /r"/"MR" { .Instruction = ND_INS_VMOVQ, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1346, + .Mnemonic = 1377, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -92207,6 +96674,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E9NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -92220,12 +96688,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3297 Instruction:"VMOVQ Vdq,Ey" Encoding:"vex m:1 p:1 l:0 w:1 0x6E /r"/"RM" + // Pos:3338 Instruction:"VMOVQ Vdq,Ey" Encoding:"vex m:1 p:1 l:0 w:1 0x6E /r"/"RM" { .Instruction = ND_INS_VMOVQ, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX, - .Mnemonic = 1346, + .Mnemonic = 1377, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -92234,6 +96702,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -92247,12 +96716,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3298 Instruction:"VMOVQ Ey,Vq" Encoding:"vex m:1 p:1 l:0 w:1 0x7E /r"/"MR" + // Pos:3339 Instruction:"VMOVQ Ey,Vq" Encoding:"vex m:1 p:1 l:0 w:1 0x7E /r"/"MR" { .Instruction = ND_INS_VMOVQ, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX, - .Mnemonic = 1346, + .Mnemonic = 1377, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -92261,6 +96730,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -92274,12 +96744,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3299 Instruction:"VMOVQ Vdq,Wq" Encoding:"vex m:1 p:2 l:0 w:i 0x7E /r"/"RM" + // Pos:3340 Instruction:"VMOVQ Vdq,Wq" Encoding:"vex m:1 p:2 l:0 w:i 0x7E /r"/"RM" { .Instruction = ND_INS_VMOVQ, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX, - .Mnemonic = 1346, + .Mnemonic = 1377, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -92288,6 +96758,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -92301,12 +96772,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3300 Instruction:"VMOVQ Wq,Vdq" Encoding:"vex m:1 p:1 l:0 w:i 0xD6 /r"/"MR" + // Pos:3341 Instruction:"VMOVQ Wq,Vdq" Encoding:"vex m:1 p:1 l:0 w:i 0xD6 /r"/"MR" { .Instruction = ND_INS_VMOVQ, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX, - .Mnemonic = 1346, + .Mnemonic = 1377, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -92315,6 +96786,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -92328,12 +96800,128 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3301 Instruction:"VMOVSD Vdq{K}{z},aKq,Msd" Encoding:"evex m:1 p:3 l:i w:1 0x10 /r:mem"/"RAM" + // Pos:3342 Instruction:"VMOVRSB Vfv{K}{z},aKq,Wfv" Encoding:"evex m:5 p:3 l:x w:0 0x6F /r:mem"/"RAM" + { + .Instruction = ND_INS_VMOVRSB, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_MOVRS, + .Mnemonic = 1378, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .SimdExc = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_MOVRS, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3343 Instruction:"VMOVRSD Vfv{K}{z},aKq,Wfv" Encoding:"evex m:5 p:2 l:x w:0 0x6F /r:mem"/"RAM" + { + .Instruction = ND_INS_VMOVRSD, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_MOVRS, + .Mnemonic = 1379, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .SimdExc = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_MOVRS, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3344 Instruction:"VMOVRSQ Vfv{K}{z},aKq,Wfv" Encoding:"evex m:5 p:2 l:x w:1 0x6F /r:mem"/"RAM" + { + .Instruction = ND_INS_VMOVRSQ, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_MOVRS, + .Mnemonic = 1380, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .SimdExc = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_MOVRS, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3345 Instruction:"VMOVRSW Vfv{K}{z},aKq,Wfv" Encoding:"evex m:5 p:3 l:x w:1 0x6F /r:mem"/"RAM" + { + .Instruction = ND_INS_VMOVRSW, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_MOVRS, + .Mnemonic = 1381, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .SimdExc = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_MOVRS, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3346 Instruction:"VMOVSD Vdq{K}{z},aKq,Msd" Encoding:"evex m:1 p:3 l:i w:1 0x10 /r:mem"/"RAM" { .Instruction = ND_INS_VMOVSD, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1347, + .Mnemonic = 1382, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -92342,6 +96930,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E10, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -92356,12 +96945,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3302 Instruction:"VMOVSD Vdq{K}{z},aKq,Hdq,Udq" Encoding:"evex m:1 p:3 l:i w:1 0x10 /r:reg"/"RAVM" + // Pos:3347 Instruction:"VMOVSD Vdq{K}{z},aKq,Hdq,Udq" Encoding:"evex m:1 p:3 l:i w:1 0x10 /r:reg"/"RAVM" { .Instruction = ND_INS_VMOVSD, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1347, + .Mnemonic = 1382, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -92370,6 +96959,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E10, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -92385,12 +96975,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3303 Instruction:"VMOVSD Msd{K},aKq,Vdq" Encoding:"evex m:1 p:3 l:i w:1 0x11 /r:mem"/"MAR" + // Pos:3348 Instruction:"VMOVSD Msd{K},aKq,Vdq" Encoding:"evex m:1 p:3 l:i w:1 0x11 /r:mem"/"MAR" { .Instruction = ND_INS_VMOVSD, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1347, + .Mnemonic = 1382, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -92399,6 +96989,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E10, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -92413,12 +97004,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3304 Instruction:"VMOVSD Udq{K}{z},aKq,Hdq,Vdq" Encoding:"evex m:1 p:3 l:i w:1 0x11 /r:reg"/"MAVR" + // Pos:3349 Instruction:"VMOVSD Udq{K}{z},aKq,Hdq,Vdq" Encoding:"evex m:1 p:3 l:i w:1 0x11 /r:reg"/"MAVR" { .Instruction = ND_INS_VMOVSD, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1347, + .Mnemonic = 1382, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -92427,6 +97018,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E10, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -92442,12 +97034,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3305 Instruction:"VMOVSD Vdq,Hdq,Usd" Encoding:"vex m:1 p:3 l:i w:i 0x10 /r:reg"/"RVM" + // Pos:3350 Instruction:"VMOVSD Vdq,Hdq,Usd" Encoding:"vex m:1 p:3 l:i w:i 0x10 /r:reg"/"RVM" { .Instruction = ND_INS_VMOVSD, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX, - .Mnemonic = 1347, + .Mnemonic = 1382, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -92456,6 +97048,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -92470,12 +97063,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3306 Instruction:"VMOVSD Vdq,Mq" Encoding:"vex m:1 p:3 l:i w:i 0x10 /r:mem"/"RM" + // Pos:3351 Instruction:"VMOVSD Vdq,Mq" Encoding:"vex m:1 p:3 l:i w:i 0x10 /r:mem"/"RM" { .Instruction = ND_INS_VMOVSD, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX, - .Mnemonic = 1347, + .Mnemonic = 1382, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -92484,6 +97077,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -92497,12 +97091,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3307 Instruction:"VMOVSD Usd,Hsd,Vsd" Encoding:"vex m:1 p:3 l:i w:i 0x11 /r:reg"/"MVR" + // Pos:3352 Instruction:"VMOVSD Usd,Hsd,Vsd" Encoding:"vex m:1 p:3 l:i w:i 0x11 /r:reg"/"MVR" { .Instruction = ND_INS_VMOVSD, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX, - .Mnemonic = 1347, + .Mnemonic = 1382, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -92511,6 +97105,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -92525,12 +97120,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3308 Instruction:"VMOVSD Mq,Vsd" Encoding:"vex m:1 p:3 l:i w:i 0x11 /r:mem"/"MR" + // Pos:3353 Instruction:"VMOVSD Mq,Vsd" Encoding:"vex m:1 p:3 l:i w:i 0x11 /r:mem"/"MR" { .Instruction = ND_INS_VMOVSD, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX, - .Mnemonic = 1347, + .Mnemonic = 1382, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -92539,6 +97134,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -92552,12 +97148,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3309 Instruction:"VMOVSH Vdq{K}{z},aKq,Wsh" Encoding:"evex m:5 p:2 l:i w:0 0x10 /r:mem"/"RAM" + // Pos:3354 Instruction:"VMOVSH Vdq{K}{z},aKq,Wsh" Encoding:"evex m:5 p:2 l:i w:0 0x10 /r:mem"/"RAM" { .Instruction = ND_INS_VMOVSH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1348, + .Mnemonic = 1383, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -92566,6 +97162,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -92580,12 +97177,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3310 Instruction:"VMOVSH Vdq{K}{z},aKq,Hdq,Wsh" Encoding:"evex m:5 p:2 l:i w:0 0x10 /r:reg"/"RAVM" + // Pos:3355 Instruction:"VMOVSH Vdq{K}{z},aKq,Hdq,Wsh" Encoding:"evex m:5 p:2 l:i w:0 0x10 /r:reg"/"RAVM" { .Instruction = ND_INS_VMOVSH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1348, + .Mnemonic = 1383, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -92594,6 +97191,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -92609,12 +97207,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3311 Instruction:"VMOVSH Wsh{K},aKq,Vdq" Encoding:"evex m:5 p:2 l:i w:0 0x11 /r:mem"/"MAR" + // Pos:3356 Instruction:"VMOVSH Wsh{K},aKq,Vdq" Encoding:"evex m:5 p:2 l:i w:0 0x11 /r:mem"/"MAR" { .Instruction = ND_INS_VMOVSH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1348, + .Mnemonic = 1383, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -92623,6 +97221,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -92637,12 +97236,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3312 Instruction:"VMOVSH Wsh{K}{z},aKq,Hdq,Vdq" Encoding:"evex m:5 p:2 l:i w:0 0x11 /r:reg"/"MAVR" + // Pos:3357 Instruction:"VMOVSH Wsh{K}{z},aKq,Hdq,Vdq" Encoding:"evex m:5 p:2 l:i w:0 0x11 /r:reg"/"MAVR" { .Instruction = ND_INS_VMOVSH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1348, + .Mnemonic = 1383, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -92651,6 +97250,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -92666,12 +97266,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3313 Instruction:"VMOVSHDUP Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:2 l:x w:0 0x16 /r"/"RAM" + // Pos:3358 Instruction:"VMOVSHDUP Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:2 l:x w:0 0x16 /r"/"RAM" { .Instruction = ND_INS_VMOVSHDUP, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1349, + .Mnemonic = 1384, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -92680,6 +97280,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NFnb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -92694,12 +97295,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3314 Instruction:"VMOVSHDUP Vx,Wx" Encoding:"vex m:1 p:2 l:x w:i 0x16 /r"/"RM" + // Pos:3359 Instruction:"VMOVSHDUP Vx,Wx" Encoding:"vex m:1 p:2 l:x w:i 0x16 /r"/"RM" { .Instruction = ND_INS_VMOVSHDUP, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1349, + .Mnemonic = 1384, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -92708,6 +97309,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -92721,12 +97323,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3315 Instruction:"VMOVSLDUP Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:2 l:x w:0 0x12 /r"/"RAM" + // Pos:3360 Instruction:"VMOVSLDUP Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:2 l:x w:0 0x12 /r"/"RAM" { .Instruction = ND_INS_VMOVSLDUP, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1350, + .Mnemonic = 1385, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -92735,6 +97337,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NFnb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -92749,12 +97352,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3316 Instruction:"VMOVSLDUP Vx,Wx" Encoding:"vex m:1 p:2 l:x w:i 0x12 /r"/"RM" + // Pos:3361 Instruction:"VMOVSLDUP Vx,Wx" Encoding:"vex m:1 p:2 l:x w:i 0x12 /r"/"RM" { .Instruction = ND_INS_VMOVSLDUP, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1350, + .Mnemonic = 1385, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -92763,6 +97366,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -92776,12 +97380,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3317 Instruction:"VMOVSS Vdq{K}{z},aKq,Mss" Encoding:"evex m:1 p:2 l:i w:0 0x10 /r:mem"/"RAM" + // Pos:3362 Instruction:"VMOVSS Vdq{K}{z},aKq,Mss" Encoding:"evex m:1 p:2 l:i w:0 0x10 /r:mem"/"RAM" { .Instruction = ND_INS_VMOVSS, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1351, + .Mnemonic = 1386, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -92790,6 +97394,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E10, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -92804,12 +97409,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3318 Instruction:"VMOVSS Vdq{K}{z},aKq,Hdq,Udq" Encoding:"evex m:1 p:2 l:i w:0 0x10 /r:reg"/"RAVM" + // Pos:3363 Instruction:"VMOVSS Vdq{K}{z},aKq,Hdq,Udq" Encoding:"evex m:1 p:2 l:i w:0 0x10 /r:reg"/"RAVM" { .Instruction = ND_INS_VMOVSS, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1351, + .Mnemonic = 1386, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -92818,6 +97423,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E10, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -92833,12 +97439,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3319 Instruction:"VMOVSS Mss{K},aKq,Vdq" Encoding:"evex m:1 p:2 l:i w:0 0x11 /r:mem"/"MAR" + // Pos:3364 Instruction:"VMOVSS Mss{K},aKq,Vdq" Encoding:"evex m:1 p:2 l:i w:0 0x11 /r:mem"/"MAR" { .Instruction = ND_INS_VMOVSS, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1351, + .Mnemonic = 1386, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -92847,6 +97453,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E10, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -92861,12 +97468,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3320 Instruction:"VMOVSS Udq{K}{z},aKq,Hdq,Vdq" Encoding:"evex m:1 p:2 l:i w:0 0x11 /r:reg"/"MAVR" + // Pos:3365 Instruction:"VMOVSS Udq{K}{z},aKq,Hdq,Vdq" Encoding:"evex m:1 p:2 l:i w:0 0x11 /r:reg"/"MAVR" { .Instruction = ND_INS_VMOVSS, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1351, + .Mnemonic = 1386, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -92875,6 +97482,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E10, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -92890,12 +97498,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3321 Instruction:"VMOVSS Vdq,Hdq,Uss" Encoding:"vex m:1 p:2 l:i w:i 0x10 /r:reg"/"RVM" + // Pos:3366 Instruction:"VMOVSS Vdq,Hdq,Uss" Encoding:"vex m:1 p:2 l:i w:i 0x10 /r:reg"/"RVM" { .Instruction = ND_INS_VMOVSS, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX, - .Mnemonic = 1351, + .Mnemonic = 1386, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -92904,6 +97512,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -92918,12 +97527,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3322 Instruction:"VMOVSS Vdq,Md" Encoding:"vex m:1 p:2 l:i w:i 0x10 /r:mem"/"RM" + // Pos:3367 Instruction:"VMOVSS Vdq,Md" Encoding:"vex m:1 p:2 l:i w:i 0x10 /r:mem"/"RM" { .Instruction = ND_INS_VMOVSS, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX, - .Mnemonic = 1351, + .Mnemonic = 1386, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -92932,6 +97541,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -92945,12 +97555,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3323 Instruction:"VMOVSS Uss,Hss,Vss" Encoding:"vex m:1 p:2 l:i w:i 0x11 /r:reg"/"MVR" + // Pos:3368 Instruction:"VMOVSS Uss,Hss,Vss" Encoding:"vex m:1 p:2 l:i w:i 0x11 /r:reg"/"MVR" { .Instruction = ND_INS_VMOVSS, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX, - .Mnemonic = 1351, + .Mnemonic = 1386, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -92959,6 +97569,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -92973,12 +97584,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3324 Instruction:"VMOVSS Md,Vss" Encoding:"vex m:1 p:2 l:i w:i 0x11 /r:mem"/"MR" + // Pos:3369 Instruction:"VMOVSS Md,Vss" Encoding:"vex m:1 p:2 l:i w:i 0x11 /r:mem"/"MR" { .Instruction = ND_INS_VMOVSS, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX, - .Mnemonic = 1351, + .Mnemonic = 1386, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -92987,6 +97598,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -93000,12 +97612,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3325 Instruction:"VMOVUPD Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:1 l:x w:1 0x10 /r"/"RAM" + // Pos:3370 Instruction:"VMOVUPD Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:1 l:x w:1 0x10 /r"/"RAM" { .Instruction = ND_INS_VMOVUPD, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1352, + .Mnemonic = 1387, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -93014,6 +97626,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4nb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -93028,12 +97641,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3326 Instruction:"VMOVUPD Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:1 l:x w:1 0x11 /r"/"MAR" + // Pos:3371 Instruction:"VMOVUPD Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:1 l:x w:1 0x11 /r"/"MAR" { .Instruction = ND_INS_VMOVUPD, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1352, + .Mnemonic = 1387, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -93042,6 +97655,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4nb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -93056,12 +97670,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3327 Instruction:"VMOVUPD Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x10 /r"/"RM" + // Pos:3372 Instruction:"VMOVUPD Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x10 /r"/"RM" { .Instruction = ND_INS_VMOVUPD, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX, - .Mnemonic = 1352, + .Mnemonic = 1387, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -93070,6 +97684,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -93083,12 +97698,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3328 Instruction:"VMOVUPD Wx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x11 /r"/"MR" + // Pos:3373 Instruction:"VMOVUPD Wx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x11 /r"/"MR" { .Instruction = ND_INS_VMOVUPD, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX, - .Mnemonic = 1352, + .Mnemonic = 1387, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -93097,6 +97712,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -93110,12 +97726,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3329 Instruction:"VMOVUPS Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:0 l:x w:0 0x10 /r"/"RAM" + // Pos:3374 Instruction:"VMOVUPS Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:0 l:x w:0 0x10 /r"/"RAM" { .Instruction = ND_INS_VMOVUPS, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1353, + .Mnemonic = 1388, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -93124,6 +97740,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4nb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -93138,12 +97755,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3330 Instruction:"VMOVUPS Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:0 l:x w:0 0x11 /r"/"MAR" + // Pos:3375 Instruction:"VMOVUPS Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:0 l:x w:0 0x11 /r"/"MAR" { .Instruction = ND_INS_VMOVUPS, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1353, + .Mnemonic = 1388, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -93152,6 +97769,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4nb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -93166,12 +97784,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3331 Instruction:"VMOVUPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x10 /r"/"RM" + // Pos:3376 Instruction:"VMOVUPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x10 /r"/"RM" { .Instruction = ND_INS_VMOVUPS, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX, - .Mnemonic = 1353, + .Mnemonic = 1388, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -93180,6 +97798,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -93193,12 +97812,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3332 Instruction:"VMOVUPS Wx,Vx" Encoding:"vex m:1 p:0 l:x w:i 0x11 /r"/"MR" + // Pos:3377 Instruction:"VMOVUPS Wx,Vx" Encoding:"vex m:1 p:0 l:x w:i 0x11 /r"/"MR" { .Instruction = ND_INS_VMOVUPS, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX, - .Mnemonic = 1353, + .Mnemonic = 1388, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -93207,6 +97826,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -93220,12 +97840,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3333 Instruction:"VMOVW Vdq,Mw" Encoding:"evex m:5 p:1 l:0 w:i 0x6E /r:mem"/"RM" + // Pos:3378 Instruction:"VMOVW Vdq,Mw" Encoding:"evex m:5 p:1 l:0 w:i 0x6E /r:mem"/"RM" { .Instruction = ND_INS_VMOVW, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1354, + .Mnemonic = 1389, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -93234,6 +97854,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E9NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -93247,12 +97868,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3334 Instruction:"VMOVW Vdq,Rd" Encoding:"evex m:5 p:1 l:0 w:i 0x6E /r:reg"/"RM" + // Pos:3379 Instruction:"VMOVW Vdq,Rd" Encoding:"evex m:5 p:1 l:0 w:i 0x6E /r:reg"/"RM" { .Instruction = ND_INS_VMOVW, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1354, + .Mnemonic = 1389, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -93261,6 +97882,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E9NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -93274,12 +97896,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3335 Instruction:"VMOVW Vdq,Ww" Encoding:"evex m:5 p:2 l:0 w:0 0x6E /r"/"RM" + // Pos:3380 Instruction:"VMOVW Vdq,Ww" Encoding:"evex m:5 p:2 l:0 w:0 0x6E /r"/"RM" { .Instruction = ND_INS_VMOVW, .Category = ND_CAT_AVX10PARTCOPY, .IsaSet = ND_SET_AVX102, - .Mnemonic = 1354, + .Mnemonic = 1389, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -93288,6 +97910,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E9NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -93301,12 +97924,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3336 Instruction:"VMOVW Mw,Vdq" Encoding:"evex m:5 p:1 l:0 w:i 0x7E /r:mem"/"MR" + // Pos:3381 Instruction:"VMOVW Mw,Vdq" Encoding:"evex m:5 p:1 l:0 w:i 0x7E /r:mem"/"MR" { .Instruction = ND_INS_VMOVW, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1354, + .Mnemonic = 1389, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -93315,6 +97938,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E9NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -93328,12 +97952,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3337 Instruction:"VMOVW Rd,Vdq" Encoding:"evex m:5 p:1 l:0 w:i 0x7E /r:reg"/"MR" + // Pos:3382 Instruction:"VMOVW Rd,Vdq" Encoding:"evex m:5 p:1 l:0 w:i 0x7E /r:reg"/"MR" { .Instruction = ND_INS_VMOVW, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1354, + .Mnemonic = 1389, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -93342,6 +97966,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E9NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -93355,12 +97980,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3338 Instruction:"VMOVW Ww,Vdq" Encoding:"evex m:5 p:2 l:0 w:0 0x7E /r"/"MR" + // Pos:3383 Instruction:"VMOVW Ww,Vdq" Encoding:"evex m:5 p:2 l:0 w:0 0x7E /r"/"MR" { .Instruction = ND_INS_VMOVW, .Category = ND_CAT_AVX10PARTCOPY, .IsaSet = ND_SET_AVX102, - .Mnemonic = 1354, + .Mnemonic = 1389, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -93369,6 +97994,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E9NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -93382,12 +98008,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3339 Instruction:"VMPSADBW Vfv{K}{z},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:2 l:x w:0 0x42 /r ib"/"RAVMI" + // Pos:3384 Instruction:"VMPSADBW Vfv{K}{z},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:2 l:x w:0 0x42 /r ib"/"RAVMI" { .Instruction = ND_INS_VMPSADBW, .Category = ND_CAT_AVX10INT, .IsaSet = ND_SET_AVX102, - .Mnemonic = 1355, + .Mnemonic = 1390, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -93396,6 +98022,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -93412,12 +98039,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3340 Instruction:"VMPSADBW Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x42 /r ib"/"RVMI" + // Pos:3385 Instruction:"VMPSADBW Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x42 /r ib"/"RVMI" { .Instruction = ND_INS_VMPSADBW, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1355, + .Mnemonic = 1390, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -93426,6 +98053,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -93441,12 +98069,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3341 Instruction:"VMPTRLD Mq" Encoding:"NP 0x0F 0xC7 /6:mem"/"M" + // Pos:3386 Instruction:"VMPTRLD Mq" Encoding:"NP 0x0F 0xC7 /6:mem"/"M" { .Instruction = ND_INS_VMPTRLD, .Category = ND_CAT_VTX, .IsaSet = ND_SET_VTX, - .Mnemonic = 1356, + .Mnemonic = 1391, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, .ValidDecorators = 0, @@ -93455,6 +98083,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .SetFlags = 0, @@ -93468,12 +98097,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3342 Instruction:"VMPTRST Mq" Encoding:"NP 0x0F 0xC7 /7:mem"/"M" + // Pos:3387 Instruction:"VMPTRST Mq" Encoding:"NP 0x0F 0xC7 /7:mem"/"M" { .Instruction = ND_INS_VMPTRST, .Category = ND_CAT_VTX, .IsaSet = ND_SET_VTX, - .Mnemonic = 1357, + .Mnemonic = 1392, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, .ValidDecorators = 0, @@ -93482,6 +98111,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .SetFlags = 0, @@ -93495,12 +98125,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3343 Instruction:"VMREAD Ey,Gy" Encoding:"NP 0x0F 0x78 /r"/"MR" + // Pos:3388 Instruction:"VMREAD Ey,Gy" Encoding:"NP 0x0F 0x78 /r"/"MR" { .Instruction = ND_INS_VMREAD, .Category = ND_CAT_VTX, .IsaSet = ND_SET_VTX, - .Mnemonic = 1358, + .Mnemonic = 1393, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, .ValidDecorators = 0, @@ -93509,6 +98139,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .SetFlags = 0, @@ -93523,12 +98154,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3344 Instruction:"VMRESUME" Encoding:"NP 0x0F 0x01 /0xC3"/"" + // Pos:3389 Instruction:"VMRESUME" Encoding:"NP 0x0F 0x01 /0xC3"/"" { .Instruction = ND_INS_VMRESUME, .Category = ND_CAT_VTX, .IsaSet = ND_SET_VTX, - .Mnemonic = 1359, + .Mnemonic = 1394, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, .ValidDecorators = 0, @@ -93537,6 +98168,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .SetFlags = 0, @@ -93549,12 +98181,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3345 Instruction:"VMRUN" Encoding:"0x0F 0x01 /0xD8"/"" + // Pos:3390 Instruction:"VMRUN" Encoding:"0x0F 0x01 /0xD8"/"" { .Instruction = ND_INS_VMRUN, .Category = ND_CAT_SYSTEM, .IsaSet = ND_SET_SVM, - .Mnemonic = 1360, + .Mnemonic = 1395, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, .ValidDecorators = 0, @@ -93563,6 +98195,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -93575,12 +98208,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3346 Instruction:"VMSAVE" Encoding:"0x0F 0x01 /0xDB"/"" + // Pos:3391 Instruction:"VMSAVE" Encoding:"0x0F 0x01 /0xDB"/"" { .Instruction = ND_INS_VMSAVE, .Category = ND_CAT_SYSTEM, .IsaSet = ND_SET_SVM, - .Mnemonic = 1361, + .Mnemonic = 1396, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, .ValidDecorators = 0, @@ -93589,6 +98222,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -93601,12 +98235,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3347 Instruction:"VMULNEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:5 p:1 l:x w:0 0x59 /r"/"RAVM" + // Pos:3392 Instruction:"VMULNEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:5 p:1 l:x w:0 0x59 /r"/"RAVM" { .Instruction = ND_INS_VMULNEPBF16, .Category = ND_CAT_AVX10BF16, .IsaSet = ND_SET_AVX102, - .Mnemonic = 1362, + .Mnemonic = 1397, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -93615,6 +98249,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -93630,12 +98265,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3348 Instruction:"VMULPD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x59 /r"/"RAVM" + // Pos:3393 Instruction:"VMULPD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x59 /r"/"RAVM" { .Instruction = ND_INS_VMULPD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1363, + .Mnemonic = 1398, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -93644,6 +98279,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -93659,12 +98295,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3349 Instruction:"VMULPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x59 /r"/"RVM" + // Pos:3394 Instruction:"VMULPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x59 /r"/"RVM" { .Instruction = ND_INS_VMULPD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1363, + .Mnemonic = 1398, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -93673,6 +98309,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -93687,12 +98324,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3350 Instruction:"VMULPH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x59 /r"/"RAVM" + // Pos:3395 Instruction:"VMULPH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x59 /r"/"RAVM" { .Instruction = ND_INS_VMULPH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1364, + .Mnemonic = 1399, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -93701,6 +98338,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -93716,12 +98354,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3351 Instruction:"VMULPS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x59 /r"/"RAVM" + // Pos:3396 Instruction:"VMULPS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x59 /r"/"RAVM" { .Instruction = ND_INS_VMULPS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1365, + .Mnemonic = 1400, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -93730,6 +98368,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -93745,12 +98384,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3352 Instruction:"VMULPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x59 /r"/"RVM" + // Pos:3397 Instruction:"VMULPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x59 /r"/"RVM" { .Instruction = ND_INS_VMULPS, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1365, + .Mnemonic = 1400, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -93759,6 +98398,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -93773,12 +98413,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3353 Instruction:"VMULSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x59 /r"/"RAVM" + // Pos:3398 Instruction:"VMULSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x59 /r"/"RAVM" { .Instruction = ND_INS_VMULSD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1366, + .Mnemonic = 1401, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -93787,6 +98427,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -93802,12 +98443,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3354 Instruction:"VMULSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x59 /r"/"RVM" + // Pos:3399 Instruction:"VMULSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x59 /r"/"RVM" { .Instruction = ND_INS_VMULSD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1366, + .Mnemonic = 1401, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -93816,6 +98457,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -93830,12 +98472,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3355 Instruction:"VMULSH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:0 0x59 /r"/"RAVM" + // Pos:3400 Instruction:"VMULSH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:0 0x59 /r"/"RAVM" { .Instruction = ND_INS_VMULSH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1367, + .Mnemonic = 1402, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -93844,6 +98486,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -93859,12 +98502,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3356 Instruction:"VMULSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x59 /r"/"RAVM" + // Pos:3401 Instruction:"VMULSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x59 /r"/"RAVM" { .Instruction = ND_INS_VMULSS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1368, + .Mnemonic = 1403, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -93873,6 +98516,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -93888,12 +98532,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3357 Instruction:"VMULSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x59 /r"/"RVM" + // Pos:3402 Instruction:"VMULSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x59 /r"/"RVM" { .Instruction = ND_INS_VMULSS, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1368, + .Mnemonic = 1403, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -93902,6 +98546,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -93916,12 +98561,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3358 Instruction:"VMWRITE Gy,Ey" Encoding:"NP 0x0F 0x79 /r"/"RM" + // Pos:3403 Instruction:"VMWRITE Gy,Ey" Encoding:"NP 0x0F 0x79 /r"/"RM" { .Instruction = ND_INS_VMWRITE, .Category = ND_CAT_VTX, .IsaSet = ND_SET_VTX, - .Mnemonic = 1369, + .Mnemonic = 1404, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, .ValidDecorators = 0, @@ -93930,6 +98575,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .SetFlags = 0, @@ -93944,12 +98590,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3359 Instruction:"VMXOFF" Encoding:"NP 0x0F 0x01 /0xC4"/"" + // Pos:3404 Instruction:"VMXOFF" Encoding:"NP 0x0F 0x01 /0xC4"/"" { .Instruction = ND_INS_VMXOFF, .Category = ND_CAT_VTX, .IsaSet = ND_SET_VTX, - .Mnemonic = 1370, + .Mnemonic = 1405, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, .ValidDecorators = 0, @@ -93958,6 +98604,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .SetFlags = 0, @@ -93970,12 +98617,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3360 Instruction:"VMXON Mq" Encoding:"0xF3 0x0F 0xC7 /6:mem"/"M" + // Pos:3405 Instruction:"VMXON Mq" Encoding:"0xF3 0x0F 0xC7 /6:mem"/"M" { .Instruction = ND_INS_VMXON, .Category = ND_CAT_VTX, .IsaSet = ND_SET_VTX, - .Mnemonic = 1371, + .Mnemonic = 1406, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, .ValidDecorators = 0, @@ -93984,6 +98631,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .SetFlags = 0, @@ -93997,12 +98645,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3361 Instruction:"VORPD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0x56 /r"/"RAVM" + // Pos:3406 Instruction:"VORPD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0x56 /r"/"RAVM" { .Instruction = ND_INS_VORPD, .Category = ND_CAT_LOGICAL_FP, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 1372, + .Mnemonic = 1407, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -94011,6 +98659,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -94026,12 +98675,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3362 Instruction:"VORPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x56 /r"/"RVM" + // Pos:3407 Instruction:"VORPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x56 /r"/"RVM" { .Instruction = ND_INS_VORPD, .Category = ND_CAT_LOGICAL_FP, .IsaSet = ND_SET_AVX, - .Mnemonic = 1372, + .Mnemonic = 1407, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -94040,6 +98689,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -94054,12 +98704,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3363 Instruction:"VORPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:0 l:x w:0 0x56 /r"/"RAVM" + // Pos:3408 Instruction:"VORPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:0 l:x w:0 0x56 /r"/"RAVM" { .Instruction = ND_INS_VORPS, .Category = ND_CAT_LOGICAL_FP, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 1373, + .Mnemonic = 1408, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -94068,6 +98718,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -94083,12 +98734,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3364 Instruction:"VORPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x56 /r"/"RVM" + // Pos:3409 Instruction:"VORPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x56 /r"/"RVM" { .Instruction = ND_INS_VORPS, .Category = ND_CAT_LOGICAL_FP, .IsaSet = ND_SET_AVX, - .Mnemonic = 1373, + .Mnemonic = 1408, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -94097,6 +98748,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -94111,12 +98763,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3365 Instruction:"VP2INTERSECTD rKq+1,Hfv,Wfv|B32" Encoding:"evex m:2 p:3 l:x w:0 0x68 /r"/"RVM" + // Pos:3410 Instruction:"VP2INTERSECTD rKq+1,Hfv,Wfv|B32" Encoding:"evex m:2 p:3 l:x w:0 0x68 /r"/"RVM" { .Instruction = ND_INS_VP2INTERSECTD, .Category = ND_CAT_AVX512VP2INTERSECT, .IsaSet = ND_SET_AVX512VP2INTERSECT, - .Mnemonic = 1374, + .Mnemonic = 1409, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_BROADCAST, @@ -94125,6 +98777,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -94139,12 +98792,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3366 Instruction:"VP2INTERSECTQ rKq+1,Hfv,Wfv|B64" Encoding:"evex m:2 p:3 l:x w:1 0x68 /r"/"RVM" + // Pos:3411 Instruction:"VP2INTERSECTQ rKq+1,Hfv,Wfv|B64" Encoding:"evex m:2 p:3 l:x w:1 0x68 /r"/"RVM" { .Instruction = ND_INS_VP2INTERSECTQ, .Category = ND_CAT_AVX512VP2INTERSECT, .IsaSet = ND_SET_AVX512VP2INTERSECT, - .Mnemonic = 1375, + .Mnemonic = 1410, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_BROADCAST, @@ -94153,6 +98806,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -94167,12 +98821,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3367 Instruction:"VP4DPWSSD Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0x52 /r:mem"/"RAVM" + // Pos:3412 Instruction:"VP4DPWSSD Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0x52 /r:mem"/"RAVM" { .Instruction = ND_INS_VP4DPWSSD, .Category = ND_CAT_VNNIW, .IsaSet = ND_SET_AVX5124VNNIW, - .Mnemonic = 1376, + .Mnemonic = 1411, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -94181,6 +98835,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -94196,12 +98851,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3368 Instruction:"VP4DPWSSDS Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0x53 /r:mem"/"RAVM" + // Pos:3413 Instruction:"VP4DPWSSDS Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0x53 /r:mem"/"RAVM" { .Instruction = ND_INS_VP4DPWSSDS, .Category = ND_CAT_VNNIW, .IsaSet = ND_SET_AVX5124VNNIW, - .Mnemonic = 1377, + .Mnemonic = 1412, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -94210,6 +98865,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -94225,12 +98881,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3369 Instruction:"VPABSB Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:x 0x1C /r"/"RAM" + // Pos:3414 Instruction:"VPABSB Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:x 0x1C /r"/"RAM" { .Instruction = ND_INS_VPABSB, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1378, + .Mnemonic = 1413, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -94239,6 +98895,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4nb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -94253,12 +98910,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3370 Instruction:"VPABSB Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x1C /r"/"RM" + // Pos:3415 Instruction:"VPABSB Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x1C /r"/"RM" { .Instruction = ND_INS_VPABSB, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1378, + .Mnemonic = 1413, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -94267,6 +98924,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -94280,12 +98938,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3371 Instruction:"VPABSD Vfv{K}{z},aKq,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x1E /r"/"RAM" + // Pos:3416 Instruction:"VPABSD Vfv{K}{z},aKq,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x1E /r"/"RAM" { .Instruction = ND_INS_VPABSD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1379, + .Mnemonic = 1414, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -94294,6 +98952,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -94308,12 +98967,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3372 Instruction:"VPABSD Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x1E /r"/"RM" + // Pos:3417 Instruction:"VPABSD Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x1E /r"/"RM" { .Instruction = ND_INS_VPABSD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1379, + .Mnemonic = 1414, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -94322,6 +98981,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -94335,12 +98995,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3373 Instruction:"VPABSQ Vfv{K}{z},aKq,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x1F /r"/"RAM" + // Pos:3418 Instruction:"VPABSQ Vfv{K}{z},aKq,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x1F /r"/"RAM" { .Instruction = ND_INS_VPABSQ, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1380, + .Mnemonic = 1415, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -94349,6 +99009,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -94363,12 +99024,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3374 Instruction:"VPABSW Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:x 0x1D /r"/"RAM" + // Pos:3419 Instruction:"VPABSW Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:x 0x1D /r"/"RAM" { .Instruction = ND_INS_VPABSW, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1381, + .Mnemonic = 1416, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -94377,6 +99038,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4nb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -94391,12 +99053,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3375 Instruction:"VPABSW Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x1D /r"/"RM" + // Pos:3420 Instruction:"VPABSW Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x1D /r"/"RM" { .Instruction = ND_INS_VPABSW, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1381, + .Mnemonic = 1416, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -94405,6 +99067,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -94418,12 +99081,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3376 Instruction:"VPACKSSDW Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0x6B /r"/"RAVM" + // Pos:3421 Instruction:"VPACKSSDW Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0x6B /r"/"RAVM" { .Instruction = ND_INS_VPACKSSDW, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1382, + .Mnemonic = 1417, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -94432,6 +99095,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -94447,12 +99111,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3377 Instruction:"VPACKSSDW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6B /r"/"RVM" + // Pos:3422 Instruction:"VPACKSSDW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6B /r"/"RVM" { .Instruction = ND_INS_VPACKSSDW, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1382, + .Mnemonic = 1417, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -94461,6 +99125,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -94475,12 +99140,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3378 Instruction:"VPACKSSWB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0x63 /r"/"RAVM" + // Pos:3423 Instruction:"VPACKSSWB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0x63 /r"/"RAVM" { .Instruction = ND_INS_VPACKSSWB, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1383, + .Mnemonic = 1418, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -94489,6 +99154,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NFnb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -94504,12 +99170,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3379 Instruction:"VPACKSSWB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x63 /r"/"RVM" + // Pos:3424 Instruction:"VPACKSSWB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x63 /r"/"RVM" { .Instruction = ND_INS_VPACKSSWB, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1383, + .Mnemonic = 1418, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -94518,6 +99184,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -94532,12 +99199,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3380 Instruction:"VPACKUSDW Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x2B /r"/"RAVM" + // Pos:3425 Instruction:"VPACKUSDW Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x2B /r"/"RAVM" { .Instruction = ND_INS_VPACKUSDW, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1384, + .Mnemonic = 1419, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -94546,6 +99213,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -94561,12 +99229,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3381 Instruction:"VPACKUSDW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x2B /r"/"RVM" + // Pos:3426 Instruction:"VPACKUSDW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x2B /r"/"RVM" { .Instruction = ND_INS_VPACKUSDW, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1384, + .Mnemonic = 1419, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -94575,6 +99243,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -94589,12 +99258,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3382 Instruction:"VPACKUSWB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0x67 /r"/"RAVM" + // Pos:3427 Instruction:"VPACKUSWB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0x67 /r"/"RAVM" { .Instruction = ND_INS_VPACKUSWB, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1385, + .Mnemonic = 1420, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -94603,6 +99272,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NFnb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -94618,12 +99288,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3383 Instruction:"VPACKUSWB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x67 /r"/"RVM" + // Pos:3428 Instruction:"VPACKUSWB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x67 /r"/"RVM" { .Instruction = ND_INS_VPACKUSWB, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1385, + .Mnemonic = 1420, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -94632,6 +99302,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -94646,12 +99317,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3384 Instruction:"VPADDB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xFC /r"/"RAVM" + // Pos:3429 Instruction:"VPADDB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xFC /r"/"RAVM" { .Instruction = ND_INS_VPADDB, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1386, + .Mnemonic = 1421, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -94660,6 +99331,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4nb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -94675,12 +99347,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3385 Instruction:"VPADDB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFC /r"/"RVM" + // Pos:3430 Instruction:"VPADDB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFC /r"/"RVM" { .Instruction = ND_INS_VPADDB, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1386, + .Mnemonic = 1421, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -94689,6 +99361,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -94703,12 +99376,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3386 Instruction:"VPADDD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0xFE /r"/"RAVM" + // Pos:3431 Instruction:"VPADDD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0xFE /r"/"RAVM" { .Instruction = ND_INS_VPADDD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1387, + .Mnemonic = 1422, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -94717,6 +99390,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -94732,12 +99406,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3387 Instruction:"VPADDD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFE /r"/"RVM" + // Pos:3432 Instruction:"VPADDD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFE /r"/"RVM" { .Instruction = ND_INS_VPADDD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1387, + .Mnemonic = 1422, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -94746,6 +99420,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -94760,12 +99435,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3388 Instruction:"VPADDQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0xD4 /r"/"RAVM" + // Pos:3433 Instruction:"VPADDQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0xD4 /r"/"RAVM" { .Instruction = ND_INS_VPADDQ, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1388, + .Mnemonic = 1423, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -94774,6 +99449,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -94789,12 +99465,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3389 Instruction:"VPADDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD4 /r"/"RVM" + // Pos:3434 Instruction:"VPADDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD4 /r"/"RVM" { .Instruction = ND_INS_VPADDQ, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1388, + .Mnemonic = 1423, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -94803,6 +99479,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -94817,12 +99494,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3390 Instruction:"VPADDSB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xEC /r"/"RAVM" + // Pos:3435 Instruction:"VPADDSB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xEC /r"/"RAVM" { .Instruction = ND_INS_VPADDSB, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1389, + .Mnemonic = 1424, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -94831,6 +99508,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4nb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -94846,12 +99524,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3391 Instruction:"VPADDSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEC /r"/"RVM" + // Pos:3436 Instruction:"VPADDSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEC /r"/"RVM" { .Instruction = ND_INS_VPADDSB, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1389, + .Mnemonic = 1424, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -94860,6 +99538,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -94874,12 +99553,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3392 Instruction:"VPADDSW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xED /r"/"RAVM" + // Pos:3437 Instruction:"VPADDSW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xED /r"/"RAVM" { .Instruction = ND_INS_VPADDSW, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1390, + .Mnemonic = 1425, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -94888,6 +99567,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4nb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -94903,12 +99583,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3393 Instruction:"VPADDSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xED /r"/"RVM" + // Pos:3438 Instruction:"VPADDSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xED /r"/"RVM" { .Instruction = ND_INS_VPADDSW, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1390, + .Mnemonic = 1425, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -94917,6 +99597,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -94931,12 +99612,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3394 Instruction:"VPADDUSB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xDC /r"/"RAVM" + // Pos:3439 Instruction:"VPADDUSB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xDC /r"/"RAVM" { .Instruction = ND_INS_VPADDUSB, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1391, + .Mnemonic = 1426, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -94945,6 +99626,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4nb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -94960,12 +99642,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3395 Instruction:"VPADDUSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDC /r"/"RVM" + // Pos:3440 Instruction:"VPADDUSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDC /r"/"RVM" { .Instruction = ND_INS_VPADDUSB, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1391, + .Mnemonic = 1426, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -94974,6 +99656,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -94988,12 +99671,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3396 Instruction:"VPADDUSW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xDD /r"/"RAVM" + // Pos:3441 Instruction:"VPADDUSW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xDD /r"/"RAVM" { .Instruction = ND_INS_VPADDUSW, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1392, + .Mnemonic = 1427, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -95002,6 +99685,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4nb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -95017,12 +99701,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3397 Instruction:"VPADDUSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDD /r"/"RVM" + // Pos:3442 Instruction:"VPADDUSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDD /r"/"RVM" { .Instruction = ND_INS_VPADDUSW, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1392, + .Mnemonic = 1427, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -95031,6 +99715,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -95045,12 +99730,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3398 Instruction:"VPADDW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xFD /r"/"RAVM" + // Pos:3443 Instruction:"VPADDW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xFD /r"/"RAVM" { .Instruction = ND_INS_VPADDW, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1393, + .Mnemonic = 1428, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -95059,6 +99744,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4nb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -95074,12 +99760,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3399 Instruction:"VPADDW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFD /r"/"RVM" + // Pos:3444 Instruction:"VPADDW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFD /r"/"RVM" { .Instruction = ND_INS_VPADDW, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1393, + .Mnemonic = 1428, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -95088,6 +99774,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -95102,12 +99789,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3400 Instruction:"VPALIGNR Vfv{K}{z},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:i 0x0F /r ib"/"RAVMI" + // Pos:3445 Instruction:"VPALIGNR Vfv{K}{z},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:i 0x0F /r ib"/"RAVMI" { .Instruction = ND_INS_VPALIGNR, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1394, + .Mnemonic = 1429, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -95116,6 +99803,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NFnb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -95132,12 +99820,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3401 Instruction:"VPALIGNR Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0F /r ib"/"RVMI" + // Pos:3446 Instruction:"VPALIGNR Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0F /r ib"/"RVMI" { .Instruction = ND_INS_VPALIGNR, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1394, + .Mnemonic = 1429, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -95146,6 +99834,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -95161,12 +99850,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3402 Instruction:"VPAND Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDB /r"/"RVM" + // Pos:3447 Instruction:"VPAND Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDB /r"/"RVM" { .Instruction = ND_INS_VPAND, .Category = ND_CAT_LOGICAL, .IsaSet = ND_SET_AVX, - .Mnemonic = 1395, + .Mnemonic = 1430, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -95175,6 +99864,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -95189,12 +99879,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3403 Instruction:"VPANDD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0xDB /r"/"RAVM" + // Pos:3448 Instruction:"VPANDD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0xDB /r"/"RAVM" { .Instruction = ND_INS_VPANDD, .Category = ND_CAT_LOGICAL, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1396, + .Mnemonic = 1431, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -95203,6 +99893,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -95218,12 +99909,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3404 Instruction:"VPANDN Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDF /r"/"RVM" + // Pos:3449 Instruction:"VPANDN Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDF /r"/"RVM" { .Instruction = ND_INS_VPANDN, .Category = ND_CAT_LOGICAL, .IsaSet = ND_SET_AVX, - .Mnemonic = 1397, + .Mnemonic = 1432, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -95232,6 +99923,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -95246,12 +99938,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3405 Instruction:"VPANDND Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0xDF /r"/"RAVM" + // Pos:3450 Instruction:"VPANDND Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0xDF /r"/"RAVM" { .Instruction = ND_INS_VPANDND, .Category = ND_CAT_LOGICAL, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1398, + .Mnemonic = 1433, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -95260,6 +99952,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -95275,12 +99968,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3406 Instruction:"VPANDNQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0xDF /r"/"RAVM" + // Pos:3451 Instruction:"VPANDNQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0xDF /r"/"RAVM" { .Instruction = ND_INS_VPANDNQ, .Category = ND_CAT_LOGICAL, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1399, + .Mnemonic = 1434, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -95289,6 +99982,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -95304,12 +99998,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3407 Instruction:"VPANDQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0xDB /r"/"RAVM" + // Pos:3452 Instruction:"VPANDQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0xDB /r"/"RAVM" { .Instruction = ND_INS_VPANDQ, .Category = ND_CAT_LOGICAL, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1400, + .Mnemonic = 1435, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -95318,6 +100012,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -95333,12 +100028,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3408 Instruction:"VPAVGB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xE0 /r"/"RAVM" + // Pos:3453 Instruction:"VPAVGB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xE0 /r"/"RAVM" { .Instruction = ND_INS_VPAVGB, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1401, + .Mnemonic = 1436, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -95347,6 +100042,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4nb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -95362,12 +100058,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3409 Instruction:"VPAVGB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE0 /r"/"RVM" + // Pos:3454 Instruction:"VPAVGB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE0 /r"/"RVM" { .Instruction = ND_INS_VPAVGB, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1401, + .Mnemonic = 1436, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -95376,6 +100072,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -95390,12 +100087,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3410 Instruction:"VPAVGW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xE3 /r"/"RAVM" + // Pos:3455 Instruction:"VPAVGW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xE3 /r"/"RAVM" { .Instruction = ND_INS_VPAVGW, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1402, + .Mnemonic = 1437, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -95404,6 +100101,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4nb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -95419,12 +100117,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3411 Instruction:"VPAVGW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE3 /r"/"RVM" + // Pos:3456 Instruction:"VPAVGW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE3 /r"/"RVM" { .Instruction = ND_INS_VPAVGW, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1402, + .Mnemonic = 1437, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -95433,6 +100131,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -95447,12 +100146,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3412 Instruction:"VPBLENDD Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:0 0x02 /r ib"/"RVMI" + // Pos:3457 Instruction:"VPBLENDD Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:0 0x02 /r ib"/"RVMI" { .Instruction = ND_INS_VPBLENDD, .Category = ND_CAT_AVX2, .IsaSet = ND_SET_AVX2, - .Mnemonic = 1403, + .Mnemonic = 1438, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -95461,6 +100160,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -95476,12 +100176,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3413 Instruction:"VPBLENDMB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x66 /r"/"RAVM" + // Pos:3458 Instruction:"VPBLENDMB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x66 /r"/"RAVM" { .Instruction = ND_INS_VPBLENDMB, .Category = ND_CAT_BLEND, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1404, + .Mnemonic = 1439, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -95490,6 +100190,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -95505,12 +100206,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3414 Instruction:"VPBLENDMD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x64 /r"/"RAVM" + // Pos:3459 Instruction:"VPBLENDMD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x64 /r"/"RAVM" { .Instruction = ND_INS_VPBLENDMD, .Category = ND_CAT_BLEND, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1405, + .Mnemonic = 1440, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -95519,6 +100220,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -95534,12 +100236,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3415 Instruction:"VPBLENDMQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x64 /r"/"RAVM" + // Pos:3460 Instruction:"VPBLENDMQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x64 /r"/"RAVM" { .Instruction = ND_INS_VPBLENDMQ, .Category = ND_CAT_BLEND, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1406, + .Mnemonic = 1441, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -95548,6 +100250,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -95563,12 +100266,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3416 Instruction:"VPBLENDMW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x66 /r"/"RAVM" + // Pos:3461 Instruction:"VPBLENDMW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x66 /r"/"RAVM" { .Instruction = ND_INS_VPBLENDMW, .Category = ND_CAT_BLEND, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1407, + .Mnemonic = 1442, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -95577,6 +100280,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -95592,12 +100296,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3417 Instruction:"VPBLENDVB Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x4C /r is4"/"RVML" + // Pos:3462 Instruction:"VPBLENDVB Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x4C /r is4"/"RVML" { .Instruction = ND_INS_VPBLENDVB, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1408, + .Mnemonic = 1443, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -95606,6 +100310,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -95621,12 +100326,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3418 Instruction:"VPBLENDW Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0E /r ib"/"RVMI" + // Pos:3463 Instruction:"VPBLENDW Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0E /r ib"/"RVMI" { .Instruction = ND_INS_VPBLENDW, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1409, + .Mnemonic = 1444, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -95635,6 +100340,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -95650,12 +100356,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3419 Instruction:"VPBROADCASTB Vfv{K}{z},aKq,Wb" Encoding:"evex m:2 p:1 l:x w:0 0x78 /r"/"RAM" + // Pos:3464 Instruction:"VPBROADCASTB Vfv{K}{z},aKq,Wb" Encoding:"evex m:2 p:1 l:x w:0 0x78 /r"/"RAM" { .Instruction = ND_INS_VPBROADCASTB, .Category = ND_CAT_BROADCAST, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1410, + .Mnemonic = 1445, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -95664,6 +100370,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E6, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -95678,12 +100385,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3420 Instruction:"VPBROADCASTB Vfv{K}{z},aKq,Rb" Encoding:"evex m:2 p:1 l:x w:0 0x7A /r:reg"/"RAM" + // Pos:3465 Instruction:"VPBROADCASTB Vfv{K}{z},aKq,Rb" Encoding:"evex m:2 p:1 l:x w:0 0x7A /r:reg"/"RAM" { .Instruction = ND_INS_VPBROADCASTB, .Category = ND_CAT_BROADCAST, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1410, + .Mnemonic = 1445, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -95692,6 +100399,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E7NM, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -95706,12 +100414,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3421 Instruction:"VPBROADCASTB Vx,Wb" Encoding:"vex m:2 p:1 l:x w:0 0x78 /r"/"RM" + // Pos:3466 Instruction:"VPBROADCASTB Vx,Wb" Encoding:"vex m:2 p:1 l:x w:0 0x78 /r"/"RM" { .Instruction = ND_INS_VPBROADCASTB, .Category = ND_CAT_BROADCAST, .IsaSet = ND_SET_AVX2, - .Mnemonic = 1410, + .Mnemonic = 1445, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -95720,6 +100428,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_6, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -95733,12 +100442,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3422 Instruction:"VPBROADCASTD Vfv{K}{z},aKq,Wd" Encoding:"evex m:2 p:1 l:x w:0 0x58 /r"/"RAM" + // Pos:3467 Instruction:"VPBROADCASTD Vfv{K}{z},aKq,Wd" Encoding:"evex m:2 p:1 l:x w:0 0x58 /r"/"RAM" { .Instruction = ND_INS_VPBROADCASTD, .Category = ND_CAT_BROADCAST, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1411, + .Mnemonic = 1446, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -95747,6 +100456,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E6, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -95761,12 +100471,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3423 Instruction:"VPBROADCASTD Vfv{K}{z},aKq,Rd" Encoding:"evex m:2 p:1 l:x w:0 0x7C /r:reg"/"RAM" + // Pos:3468 Instruction:"VPBROADCASTD Vfv{K}{z},aKq,Rd" Encoding:"evex m:2 p:1 l:x w:0 0x7C /r:reg"/"RAM" { .Instruction = ND_INS_VPBROADCASTD, .Category = ND_CAT_BROADCAST, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1411, + .Mnemonic = 1446, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -95775,6 +100485,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E7NM, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -95789,12 +100500,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3424 Instruction:"VPBROADCASTD Vx,Wd" Encoding:"vex m:2 p:1 l:x w:0 0x58 /r"/"RM" + // Pos:3469 Instruction:"VPBROADCASTD Vx,Wd" Encoding:"vex m:2 p:1 l:x w:0 0x58 /r"/"RM" { .Instruction = ND_INS_VPBROADCASTD, .Category = ND_CAT_BROADCAST, .IsaSet = ND_SET_AVX2, - .Mnemonic = 1411, + .Mnemonic = 1446, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -95803,6 +100514,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_6, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -95816,12 +100528,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3425 Instruction:"VPBROADCASTMB2Q Vfv,mKq" Encoding:"evex m:2 p:2 l:x w:1 0x2A /r:reg"/"RM" + // Pos:3470 Instruction:"VPBROADCASTMB2Q Vfv,mKq" Encoding:"evex m:2 p:2 l:x w:1 0x2A /r:reg"/"RM" { .Instruction = ND_INS_VPBROADCASTMB2Q, .Category = ND_CAT_BROADCAST, .IsaSet = ND_SET_AVX512CD, - .Mnemonic = 1412, + .Mnemonic = 1447, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -95830,6 +100542,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E6NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -95843,12 +100556,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3426 Instruction:"VPBROADCASTMW2D Vfv,mKq" Encoding:"evex m:2 p:2 l:x w:0 0x3A /r:reg"/"RM" + // Pos:3471 Instruction:"VPBROADCASTMW2D Vfv,mKq" Encoding:"evex m:2 p:2 l:x w:0 0x3A /r:reg"/"RM" { .Instruction = ND_INS_VPBROADCASTMW2D, .Category = ND_CAT_BROADCAST, .IsaSet = ND_SET_AVX512CD, - .Mnemonic = 1413, + .Mnemonic = 1448, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -95857,6 +100570,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E6NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -95870,12 +100584,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3427 Instruction:"VPBROADCASTQ Vfv{K}{z},aKq,Wq" Encoding:"evex m:2 p:1 l:x w:1 0x59 /r"/"RAM" + // Pos:3472 Instruction:"VPBROADCASTQ Vfv{K}{z},aKq,Wq" Encoding:"evex m:2 p:1 l:x w:1 0x59 /r"/"RAM" { .Instruction = ND_INS_VPBROADCASTQ, .Category = ND_CAT_BROADCAST, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1414, + .Mnemonic = 1449, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -95884,6 +100598,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E6, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -95898,12 +100613,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3428 Instruction:"VPBROADCASTQ Vfv{K}{z},aKq,Rq" Encoding:"evex m:2 p:1 l:x w:1 0x7C /r:reg"/"RAM" + // Pos:3473 Instruction:"VPBROADCASTQ Vfv{K}{z},aKq,Rq" Encoding:"evex m:2 p:1 l:x w:1 0x7C /r:reg"/"RAM" { .Instruction = ND_INS_VPBROADCASTQ, .Category = ND_CAT_BROADCAST, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1414, + .Mnemonic = 1449, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -95912,6 +100627,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E7NM, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -95926,12 +100642,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3429 Instruction:"VPBROADCASTQ Vx,Wq" Encoding:"vex m:2 p:1 l:x w:0 0x59 /r"/"RM" + // Pos:3474 Instruction:"VPBROADCASTQ Vx,Wq" Encoding:"vex m:2 p:1 l:x w:0 0x59 /r"/"RM" { .Instruction = ND_INS_VPBROADCASTQ, .Category = ND_CAT_BROADCAST, .IsaSet = ND_SET_AVX2, - .Mnemonic = 1414, + .Mnemonic = 1449, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -95940,6 +100656,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_6, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -95953,12 +100670,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3430 Instruction:"VPBROADCASTW Vfv{K}{z},aKq,Ww" Encoding:"evex m:2 p:1 l:x w:0 0x79 /r"/"RAM" + // Pos:3475 Instruction:"VPBROADCASTW Vfv{K}{z},aKq,Ww" Encoding:"evex m:2 p:1 l:x w:0 0x79 /r"/"RAM" { .Instruction = ND_INS_VPBROADCASTW, .Category = ND_CAT_BROADCAST, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1415, + .Mnemonic = 1450, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -95967,6 +100684,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E6, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -95981,12 +100699,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3431 Instruction:"VPBROADCASTW Vfv{K}{z},aKq,Rw" Encoding:"evex m:2 p:1 l:x w:0 0x7B /r:reg"/"RAM" + // Pos:3476 Instruction:"VPBROADCASTW Vfv{K}{z},aKq,Rw" Encoding:"evex m:2 p:1 l:x w:0 0x7B /r:reg"/"RAM" { .Instruction = ND_INS_VPBROADCASTW, .Category = ND_CAT_BROADCAST, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1415, + .Mnemonic = 1450, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -95995,6 +100713,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E7NM, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -96009,12 +100728,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3432 Instruction:"VPBROADCASTW Vx,Ww" Encoding:"vex m:2 p:1 l:x w:0 0x79 /r"/"RM" + // Pos:3477 Instruction:"VPBROADCASTW Vx,Ww" Encoding:"vex m:2 p:1 l:x w:0 0x79 /r"/"RM" { .Instruction = ND_INS_VPBROADCASTW, .Category = ND_CAT_BROADCAST, .IsaSet = ND_SET_AVX2, - .Mnemonic = 1415, + .Mnemonic = 1450, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -96023,6 +100742,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_6, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -96036,12 +100756,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3433 Instruction:"VPCLMULQDQ Vfv,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:i 0x44 /r ib"/"RVMI" + // Pos:3478 Instruction:"VPCLMULQDQ Vfv,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:i 0x44 /r ib"/"RVMI" { .Instruction = ND_INS_VPCLMULQDQ, .Category = ND_CAT_VPCLMULQDQ, .IsaSet = ND_SET_VPCLMULQDQ, - .Mnemonic = 1416, + .Mnemonic = 1451, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -96050,6 +100770,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -96065,12 +100786,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3434 Instruction:"VPCLMULQDQ Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x44 /r ib"/"RVMI" + // Pos:3479 Instruction:"VPCLMULQDQ Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x44 /r ib"/"RVMI" { .Instruction = ND_INS_VPCLMULQDQ, .Category = ND_CAT_VPCLMULQDQ, .IsaSet = ND_SET_VPCLMULQDQ, - .Mnemonic = 1416, + .Mnemonic = 1451, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -96079,6 +100800,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -96094,12 +100816,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3435 Instruction:"VPCMOV Vx,Hx,Wx,Lx" Encoding:"xop m:8 w:0 0xA2 /r is4"/"RVML" + // Pos:3480 Instruction:"VPCMOV Vx,Hx,Wx,Lx" Encoding:"xop m:8 w:0 0xA2 /r is4"/"RVML" { .Instruction = ND_INS_VPCMOV, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1417, + .Mnemonic = 1452, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -96108,6 +100830,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -96123,12 +100846,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3436 Instruction:"VPCMOV Vx,Hx,Lx,Wx" Encoding:"xop m:8 w:1 0xA2 /r is4"/"RVLM" + // Pos:3481 Instruction:"VPCMOV Vx,Hx,Lx,Wx" Encoding:"xop m:8 w:1 0xA2 /r is4"/"RVLM" { .Instruction = ND_INS_VPCMOV, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1417, + .Mnemonic = 1452, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -96137,6 +100860,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -96152,12 +100876,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3437 Instruction:"VPCMPB rKq{K},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x3F /r ib"/"RAVMI" + // Pos:3482 Instruction:"VPCMPB rKq{K},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x3F /r ib"/"RAVMI" { .Instruction = ND_INS_VPCMPB, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1418, + .Mnemonic = 1453, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -96166,6 +100890,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4nb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -96182,12 +100907,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3438 Instruction:"VPCMPD rKq{K},aKq,Hfv,Wfv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x1F /r ib"/"RAVMI" + // Pos:3483 Instruction:"VPCMPD rKq{K},aKq,Hfv,Wfv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x1F /r ib"/"RAVMI" { .Instruction = ND_INS_VPCMPD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1419, + .Mnemonic = 1454, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_BROADCAST, @@ -96196,6 +100921,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -96212,12 +100938,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3439 Instruction:"VPCMPEQB rKq{K},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0x74 /r"/"RAVM" + // Pos:3484 Instruction:"VPCMPEQB rKq{K},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0x74 /r"/"RAVM" { .Instruction = ND_INS_VPCMPEQB, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1420, + .Mnemonic = 1455, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -96226,6 +100952,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4nb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -96241,12 +100968,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3440 Instruction:"VPCMPEQB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x74 /r"/"RVM" + // Pos:3485 Instruction:"VPCMPEQB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x74 /r"/"RVM" { .Instruction = ND_INS_VPCMPEQB, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1420, + .Mnemonic = 1455, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -96255,6 +100982,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -96269,12 +100997,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3441 Instruction:"VPCMPEQD rKq{K},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:i 0x76 /r"/"RAVM" + // Pos:3486 Instruction:"VPCMPEQD rKq{K},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:i 0x76 /r"/"RAVM" { .Instruction = ND_INS_VPCMPEQD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1421, + .Mnemonic = 1456, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_BROADCAST, @@ -96283,6 +101011,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -96298,12 +101027,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3442 Instruction:"VPCMPEQD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x76 /r"/"RVM" + // Pos:3487 Instruction:"VPCMPEQD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x76 /r"/"RVM" { .Instruction = ND_INS_VPCMPEQD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1421, + .Mnemonic = 1456, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -96312,6 +101041,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -96326,12 +101056,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3443 Instruction:"VPCMPEQQ rKq{K},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x29 /r"/"RAVM" + // Pos:3488 Instruction:"VPCMPEQQ rKq{K},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x29 /r"/"RAVM" { .Instruction = ND_INS_VPCMPEQQ, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1422, + .Mnemonic = 1457, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_BROADCAST, @@ -96340,6 +101070,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -96355,12 +101086,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3444 Instruction:"VPCMPEQQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x29 /r"/"RVM" + // Pos:3489 Instruction:"VPCMPEQQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x29 /r"/"RVM" { .Instruction = ND_INS_VPCMPEQQ, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1422, + .Mnemonic = 1457, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -96369,6 +101100,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -96383,12 +101115,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3445 Instruction:"VPCMPEQW rKq{K},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0x75 /r"/"RAVM" + // Pos:3490 Instruction:"VPCMPEQW rKq{K},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0x75 /r"/"RAVM" { .Instruction = ND_INS_VPCMPEQW, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1423, + .Mnemonic = 1458, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -96397,6 +101129,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4nb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -96412,12 +101145,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3446 Instruction:"VPCMPEQW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x75 /r"/"RVM" + // Pos:3491 Instruction:"VPCMPEQW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x75 /r"/"RVM" { .Instruction = ND_INS_VPCMPEQW, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1423, + .Mnemonic = 1458, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -96426,6 +101159,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -96440,12 +101174,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3447 Instruction:"VPCMPESTRI Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x61 /r ib"/"RMI" + // Pos:3492 Instruction:"VPCMPESTRI Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x61 /r ib"/"RMI" { .Instruction = ND_INS_VPCMPESTRI, .Category = ND_CAT_STTNI, .IsaSet = ND_SET_AVX, - .Mnemonic = 1424, + .Mnemonic = 1459, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -96454,6 +101188,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -96472,12 +101207,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3448 Instruction:"VPCMPESTRM Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x60 /r ib"/"RMI" + // Pos:3493 Instruction:"VPCMPESTRM Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x60 /r ib"/"RMI" { .Instruction = ND_INS_VPCMPESTRM, .Category = ND_CAT_STTNI, .IsaSet = ND_SET_AVX, - .Mnemonic = 1425, + .Mnemonic = 1460, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -96486,6 +101221,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -96504,12 +101240,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3449 Instruction:"VPCMPGTB rKq{K},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0x64 /r"/"RAVM" + // Pos:3494 Instruction:"VPCMPGTB rKq{K},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0x64 /r"/"RAVM" { .Instruction = ND_INS_VPCMPGTB, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1426, + .Mnemonic = 1461, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -96518,6 +101254,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4nb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -96533,12 +101270,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3450 Instruction:"VPCMPGTB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x64 /r"/"RVM" + // Pos:3495 Instruction:"VPCMPGTB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x64 /r"/"RVM" { .Instruction = ND_INS_VPCMPGTB, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1426, + .Mnemonic = 1461, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -96547,6 +101284,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -96561,12 +101299,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3451 Instruction:"VPCMPGTD rKq{K},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0x66 /r"/"RAVM" + // Pos:3496 Instruction:"VPCMPGTD rKq{K},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0x66 /r"/"RAVM" { .Instruction = ND_INS_VPCMPGTD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1427, + .Mnemonic = 1462, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_BROADCAST, @@ -96575,6 +101313,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -96590,12 +101329,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3452 Instruction:"VPCMPGTD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x66 /r"/"RVM" + // Pos:3497 Instruction:"VPCMPGTD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x66 /r"/"RVM" { .Instruction = ND_INS_VPCMPGTD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1427, + .Mnemonic = 1462, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -96604,6 +101343,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -96618,12 +101358,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3453 Instruction:"VPCMPGTQ rKq{K},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x37 /r"/"RAVM" + // Pos:3498 Instruction:"VPCMPGTQ rKq{K},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x37 /r"/"RAVM" { .Instruction = ND_INS_VPCMPGTQ, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1428, + .Mnemonic = 1463, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_BROADCAST, @@ -96632,6 +101372,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -96647,12 +101388,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3454 Instruction:"VPCMPGTQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x37 /r"/"RVM" + // Pos:3499 Instruction:"VPCMPGTQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x37 /r"/"RVM" { .Instruction = ND_INS_VPCMPGTQ, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1428, + .Mnemonic = 1463, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -96661,6 +101402,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -96675,12 +101417,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3455 Instruction:"VPCMPGTW rKq{K},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0x65 /r"/"RAVM" + // Pos:3500 Instruction:"VPCMPGTW rKq{K},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0x65 /r"/"RAVM" { .Instruction = ND_INS_VPCMPGTW, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1429, + .Mnemonic = 1464, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -96689,6 +101431,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4nb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -96704,12 +101447,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3456 Instruction:"VPCMPGTW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x65 /r"/"RVM" + // Pos:3501 Instruction:"VPCMPGTW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x65 /r"/"RVM" { .Instruction = ND_INS_VPCMPGTW, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1429, + .Mnemonic = 1464, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -96718,6 +101461,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -96732,12 +101476,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3457 Instruction:"VPCMPISTRI Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x63 /r ib"/"RMI" + // Pos:3502 Instruction:"VPCMPISTRI Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x63 /r ib"/"RMI" { .Instruction = ND_INS_VPCMPISTRI, .Category = ND_CAT_STTNI, .IsaSet = ND_SET_AVX, - .Mnemonic = 1430, + .Mnemonic = 1465, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -96746,6 +101490,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -96762,12 +101507,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3458 Instruction:"VPCMPISTRM Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x62 /r ib"/"RMI" + // Pos:3503 Instruction:"VPCMPISTRM Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x62 /r ib"/"RMI" { .Instruction = ND_INS_VPCMPISTRM, .Category = ND_CAT_STTNI, .IsaSet = ND_SET_AVX, - .Mnemonic = 1431, + .Mnemonic = 1466, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -96776,6 +101521,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -96792,12 +101538,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3459 Instruction:"VPCMPQ rKq{K},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x1F /r ib"/"RAVMI" + // Pos:3504 Instruction:"VPCMPQ rKq{K},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x1F /r ib"/"RAVMI" { .Instruction = ND_INS_VPCMPQ, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1432, + .Mnemonic = 1467, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_BROADCAST, @@ -96806,6 +101552,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -96822,12 +101569,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3460 Instruction:"VPCMPUB rKq{K},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x3E /r ib"/"RAVMI" + // Pos:3505 Instruction:"VPCMPUB rKq{K},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x3E /r ib"/"RAVMI" { .Instruction = ND_INS_VPCMPUB, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1433, + .Mnemonic = 1468, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -96836,6 +101583,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4nb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -96852,12 +101600,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3461 Instruction:"VPCMPUD rKq{K},aKq,Hfv,Wfv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x1E /r ib"/"RAVMI" + // Pos:3506 Instruction:"VPCMPUD rKq{K},aKq,Hfv,Wfv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x1E /r ib"/"RAVMI" { .Instruction = ND_INS_VPCMPUD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1434, + .Mnemonic = 1469, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_BROADCAST, @@ -96866,6 +101614,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -96882,12 +101631,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3462 Instruction:"VPCMPUQ rKq{K},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x1E /r ib"/"RAVMI" + // Pos:3507 Instruction:"VPCMPUQ rKq{K},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x1E /r ib"/"RAVMI" { .Instruction = ND_INS_VPCMPUQ, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1435, + .Mnemonic = 1470, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_BROADCAST, @@ -96896,6 +101645,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -96912,12 +101662,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3463 Instruction:"VPCMPUW rKq{K},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x3E /r ib"/"RAVMI" + // Pos:3508 Instruction:"VPCMPUW rKq{K},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x3E /r ib"/"RAVMI" { .Instruction = ND_INS_VPCMPUW, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1436, + .Mnemonic = 1471, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -96926,6 +101676,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4nb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -96942,12 +101693,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3464 Instruction:"VPCMPW rKq{K},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x3F /r ib"/"RAVMI" + // Pos:3509 Instruction:"VPCMPW rKq{K},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x3F /r ib"/"RAVMI" { .Instruction = ND_INS_VPCMPW, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1437, + .Mnemonic = 1472, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -96956,6 +101707,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4nb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -96972,12 +101724,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3465 Instruction:"VPCOMB Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCC /r ib"/"RVMI" + // Pos:3510 Instruction:"VPCOMB Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCC /r ib"/"RVMI" { .Instruction = ND_INS_VPCOMB, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1438, + .Mnemonic = 1473, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -96986,6 +101738,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -97001,12 +101754,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3466 Instruction:"VPCOMD Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCE /r ib"/"RVMI" + // Pos:3511 Instruction:"VPCOMD Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCE /r ib"/"RVMI" { .Instruction = ND_INS_VPCOMD, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1439, + .Mnemonic = 1474, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -97015,6 +101768,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -97030,12 +101784,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3467 Instruction:"VPCOMPRESSB Wfv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:0 0x63 /r"/"MAR" + // Pos:3512 Instruction:"VPCOMPRESSB Wfv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:0 0x63 /r"/"MAR" { .Instruction = ND_INS_VPCOMPRESSB, .Category = ND_CAT_AVX512VBMI, .IsaSet = ND_SET_AVX512VBMI2, - .Mnemonic = 1440, + .Mnemonic = 1475, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -97044,6 +101798,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -97058,12 +101813,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3468 Instruction:"VPCOMPRESSD Wfv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:0 0x8B /r"/"MAR" + // Pos:3513 Instruction:"VPCOMPRESSD Wfv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:0 0x8B /r"/"MAR" { .Instruction = ND_INS_VPCOMPRESSD, .Category = ND_CAT_COMPRESS, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1441, + .Mnemonic = 1476, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -97072,6 +101827,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4nb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -97086,12 +101842,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3469 Instruction:"VPCOMPRESSQ Wfv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:1 0x8B /r"/"MAR" + // Pos:3514 Instruction:"VPCOMPRESSQ Wfv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:1 0x8B /r"/"MAR" { .Instruction = ND_INS_VPCOMPRESSQ, .Category = ND_CAT_COMPRESS, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1442, + .Mnemonic = 1477, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -97100,6 +101856,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4nb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -97114,12 +101871,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3470 Instruction:"VPCOMPRESSW Wfv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:1 0x63 /r"/"MAR" + // Pos:3515 Instruction:"VPCOMPRESSW Wfv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:1 0x63 /r"/"MAR" { .Instruction = ND_INS_VPCOMPRESSW, .Category = ND_CAT_AVX512VBMI, .IsaSet = ND_SET_AVX512VBMI2, - .Mnemonic = 1443, + .Mnemonic = 1478, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -97128,6 +101885,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -97142,12 +101900,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3471 Instruction:"VPCOMQ Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCF /r ib"/"RVMI" + // Pos:3516 Instruction:"VPCOMQ Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCF /r ib"/"RVMI" { .Instruction = ND_INS_VPCOMQ, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1444, + .Mnemonic = 1479, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -97156,6 +101914,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -97171,12 +101930,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3472 Instruction:"VPCOMUB Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xEC /r ib"/"RVMI" + // Pos:3517 Instruction:"VPCOMUB Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xEC /r ib"/"RVMI" { .Instruction = ND_INS_VPCOMUB, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1445, + .Mnemonic = 1480, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -97185,6 +101944,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -97200,12 +101960,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3473 Instruction:"VPCOMUD Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xEE /r ib"/"RVMI" + // Pos:3518 Instruction:"VPCOMUD Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xEE /r ib"/"RVMI" { .Instruction = ND_INS_VPCOMUD, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1446, + .Mnemonic = 1481, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -97214,6 +101974,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -97229,12 +101990,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3474 Instruction:"VPCOMUQ Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xEF /r ib"/"RVMI" + // Pos:3519 Instruction:"VPCOMUQ Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xEF /r ib"/"RVMI" { .Instruction = ND_INS_VPCOMUQ, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1447, + .Mnemonic = 1482, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -97243,6 +102004,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -97258,12 +102020,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3475 Instruction:"VPCOMUW Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xED /r ib"/"RVMI" + // Pos:3520 Instruction:"VPCOMUW Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xED /r ib"/"RVMI" { .Instruction = ND_INS_VPCOMUW, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1448, + .Mnemonic = 1483, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -97272,6 +102034,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -97287,12 +102050,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3476 Instruction:"VPCOMW Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCD /r ib"/"RVMI" + // Pos:3521 Instruction:"VPCOMW Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCD /r ib"/"RVMI" { .Instruction = ND_INS_VPCOMW, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1449, + .Mnemonic = 1484, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -97301,6 +102064,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -97316,12 +102080,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3477 Instruction:"VPCONFLICTD Vfv{K}{z},aKq,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0xC4 /r"/"RAM" + // Pos:3522 Instruction:"VPCONFLICTD Vfv{K}{z},aKq,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0xC4 /r"/"RAM" { .Instruction = ND_INS_VPCONFLICTD, .Category = ND_CAT_CONFLICT, .IsaSet = ND_SET_AVX512CD, - .Mnemonic = 1450, + .Mnemonic = 1485, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -97330,6 +102094,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -97344,12 +102109,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3478 Instruction:"VPCONFLICTQ Vfv{K}{z},aKq,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0xC4 /r"/"RAM" + // Pos:3523 Instruction:"VPCONFLICTQ Vfv{K}{z},aKq,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0xC4 /r"/"RAM" { .Instruction = ND_INS_VPCONFLICTQ, .Category = ND_CAT_CONFLICT, .IsaSet = ND_SET_AVX512CD, - .Mnemonic = 1451, + .Mnemonic = 1486, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -97358,6 +102123,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -97372,12 +102138,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3479 Instruction:"VPDPBSSD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:3 l:x w:0 0x50 /r"/"RAVM" + // Pos:3524 Instruction:"VPDPBSSD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:3 l:x w:0 0x50 /r"/"RAVM" { .Instruction = ND_INS_VPDPBSSD, .Category = ND_CAT_AVX10INT, .IsaSet = ND_SET_AVX102, - .Mnemonic = 1452, + .Mnemonic = 1487, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -97386,6 +102152,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -97401,12 +102168,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3480 Instruction:"VPDPBSSD Vx,Hx,Wx" Encoding:"vex m:2 p:3 l:x w:0 0x50 /r"/"RVM" + // Pos:3525 Instruction:"VPDPBSSD Vx,Hx,Wx" Encoding:"vex m:2 p:3 l:x w:0 0x50 /r"/"RVM" { .Instruction = ND_INS_VPDPBSSD, .Category = ND_CAT_AVXVNNIINT8, .IsaSet = ND_SET_AVXVNNIINT8, - .Mnemonic = 1452, + .Mnemonic = 1487, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -97415,6 +102182,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -97429,12 +102197,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3481 Instruction:"VPDPBSSDS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:3 l:x w:0 0x51 /r"/"RAVM" + // Pos:3526 Instruction:"VPDPBSSDS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:3 l:x w:0 0x51 /r"/"RAVM" { .Instruction = ND_INS_VPDPBSSDS, .Category = ND_CAT_AVX10INT, .IsaSet = ND_SET_AVX102, - .Mnemonic = 1453, + .Mnemonic = 1488, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -97443,6 +102211,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -97458,12 +102227,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3482 Instruction:"VPDPBSSDS Vx,Hx,Wx" Encoding:"vex m:2 p:3 l:x w:0 0x51 /r"/"RVM" + // Pos:3527 Instruction:"VPDPBSSDS Vx,Hx,Wx" Encoding:"vex m:2 p:3 l:x w:0 0x51 /r"/"RVM" { .Instruction = ND_INS_VPDPBSSDS, .Category = ND_CAT_AVXVNNIINT8, .IsaSet = ND_SET_AVXVNNIINT8, - .Mnemonic = 1453, + .Mnemonic = 1488, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -97472,6 +102241,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -97486,12 +102256,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3483 Instruction:"VPDPBSUD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:2 l:x w:0 0x50 /r"/"RAVM" + // Pos:3528 Instruction:"VPDPBSUD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:2 l:x w:0 0x50 /r"/"RAVM" { .Instruction = ND_INS_VPDPBSUD, .Category = ND_CAT_AVX10INT, .IsaSet = ND_SET_AVX102, - .Mnemonic = 1454, + .Mnemonic = 1489, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -97500,6 +102270,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -97515,12 +102286,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3484 Instruction:"VPDPBSUD Vx,Hx,Wx" Encoding:"vex m:2 p:2 l:x w:0 0x50 /r"/"RVM" + // Pos:3529 Instruction:"VPDPBSUD Vx,Hx,Wx" Encoding:"vex m:2 p:2 l:x w:0 0x50 /r"/"RVM" { .Instruction = ND_INS_VPDPBSUD, .Category = ND_CAT_AVXVNNIINT8, .IsaSet = ND_SET_AVXVNNIINT8, - .Mnemonic = 1454, + .Mnemonic = 1489, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -97529,6 +102300,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -97543,12 +102315,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3485 Instruction:"VPDPBSUDS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:2 l:x w:0 0x51 /r"/"RAVM" + // Pos:3530 Instruction:"VPDPBSUDS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:2 l:x w:0 0x51 /r"/"RAVM" { .Instruction = ND_INS_VPDPBSUDS, .Category = ND_CAT_AVX10INT, .IsaSet = ND_SET_AVX102, - .Mnemonic = 1455, + .Mnemonic = 1490, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -97557,6 +102329,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -97572,12 +102345,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3486 Instruction:"VPDPBSUDS Vx,Hx,Wx" Encoding:"vex m:2 p:2 l:x w:0 0x51 /r"/"RVM" + // Pos:3531 Instruction:"VPDPBSUDS Vx,Hx,Wx" Encoding:"vex m:2 p:2 l:x w:0 0x51 /r"/"RVM" { .Instruction = ND_INS_VPDPBSUDS, .Category = ND_CAT_AVXVNNIINT8, .IsaSet = ND_SET_AVXVNNIINT8, - .Mnemonic = 1455, + .Mnemonic = 1490, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -97586,6 +102359,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -97600,12 +102374,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3487 Instruction:"VPDPBUSD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x50 /r"/"RAVM" + // Pos:3532 Instruction:"VPDPBUSD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x50 /r"/"RAVM" { .Instruction = ND_INS_VPDPBUSD, .Category = ND_CAT_VNNI, .IsaSet = ND_SET_AVX512VNNI, - .Mnemonic = 1456, + .Mnemonic = 1491, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -97614,6 +102388,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -97629,12 +102404,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3488 Instruction:"VPDPBUSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x50 /r"/"RVM" + // Pos:3533 Instruction:"VPDPBUSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x50 /r"/"RVM" { .Instruction = ND_INS_VPDPBUSD, .Category = ND_CAT_AVXVNNI, .IsaSet = ND_SET_AVXVNNI, - .Mnemonic = 1456, + .Mnemonic = 1491, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -97643,6 +102418,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -97657,12 +102433,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3489 Instruction:"VPDPBUSDS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x51 /r"/"RAVM" + // Pos:3534 Instruction:"VPDPBUSDS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x51 /r"/"RAVM" { .Instruction = ND_INS_VPDPBUSDS, .Category = ND_CAT_VNNI, .IsaSet = ND_SET_AVX512VNNI, - .Mnemonic = 1457, + .Mnemonic = 1492, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -97671,6 +102447,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -97686,12 +102463,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3490 Instruction:"VPDPBUSDS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x51 /r"/"RVM" + // Pos:3535 Instruction:"VPDPBUSDS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x51 /r"/"RVM" { .Instruction = ND_INS_VPDPBUSDS, .Category = ND_CAT_AVXVNNI, .IsaSet = ND_SET_AVXVNNI, - .Mnemonic = 1457, + .Mnemonic = 1492, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -97700,6 +102477,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -97714,12 +102492,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3491 Instruction:"VPDPBUUD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:0 l:x w:0 0x50 /r"/"RAVM" + // Pos:3536 Instruction:"VPDPBUUD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:0 l:x w:0 0x50 /r"/"RAVM" { .Instruction = ND_INS_VPDPBUUD, .Category = ND_CAT_AVX10INT, .IsaSet = ND_SET_AVX102, - .Mnemonic = 1458, + .Mnemonic = 1493, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -97728,6 +102506,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -97743,12 +102522,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3492 Instruction:"VPDPBUUD Vx,Hx,Wx" Encoding:"vex m:2 p:0 l:x w:0 0x50 /r"/"RVM" + // Pos:3537 Instruction:"VPDPBUUD Vx,Hx,Wx" Encoding:"vex m:2 p:0 l:x w:0 0x50 /r"/"RVM" { .Instruction = ND_INS_VPDPBUUD, .Category = ND_CAT_AVXVNNIINT8, .IsaSet = ND_SET_AVXVNNIINT8, - .Mnemonic = 1458, + .Mnemonic = 1493, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -97757,6 +102536,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -97771,12 +102551,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3493 Instruction:"VPDPBUUDS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:0 l:x w:0 0x51 /r"/"RAVM" + // Pos:3538 Instruction:"VPDPBUUDS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:0 l:x w:0 0x51 /r"/"RAVM" { .Instruction = ND_INS_VPDPBUUDS, .Category = ND_CAT_AVX10INT, .IsaSet = ND_SET_AVX102, - .Mnemonic = 1459, + .Mnemonic = 1494, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -97785,6 +102565,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -97800,12 +102581,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3494 Instruction:"VPDPBUUDS Vx,Hx,Wx" Encoding:"vex m:2 p:0 l:x w:0 0x51 /r"/"RVM" + // Pos:3539 Instruction:"VPDPBUUDS Vx,Hx,Wx" Encoding:"vex m:2 p:0 l:x w:0 0x51 /r"/"RVM" { .Instruction = ND_INS_VPDPBUUDS, .Category = ND_CAT_AVXVNNIINT8, .IsaSet = ND_SET_AVXVNNIINT8, - .Mnemonic = 1459, + .Mnemonic = 1494, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -97814,6 +102595,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -97828,12 +102610,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3495 Instruction:"VPDPWSSD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x52 /r"/"RAVM" + // Pos:3540 Instruction:"VPDPWSSD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x52 /r"/"RAVM" { .Instruction = ND_INS_VPDPWSSD, .Category = ND_CAT_VNNI, .IsaSet = ND_SET_AVX512VNNI, - .Mnemonic = 1460, + .Mnemonic = 1495, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -97842,6 +102624,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -97857,12 +102640,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3496 Instruction:"VPDPWSSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x52 /r"/"RVM" + // Pos:3541 Instruction:"VPDPWSSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x52 /r"/"RVM" { .Instruction = ND_INS_VPDPWSSD, .Category = ND_CAT_AVXVNNI, .IsaSet = ND_SET_AVXVNNI, - .Mnemonic = 1460, + .Mnemonic = 1495, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -97871,6 +102654,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -97885,12 +102669,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3497 Instruction:"VPDPWSSDS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x53 /r"/"RAVM" + // Pos:3542 Instruction:"VPDPWSSDS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x53 /r"/"RAVM" { .Instruction = ND_INS_VPDPWSSDS, .Category = ND_CAT_VNNI, .IsaSet = ND_SET_AVX512VNNI, - .Mnemonic = 1461, + .Mnemonic = 1496, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -97899,6 +102683,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -97914,12 +102699,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3498 Instruction:"VPDPWSSDS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x53 /r"/"RVM" + // Pos:3543 Instruction:"VPDPWSSDS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x53 /r"/"RVM" { .Instruction = ND_INS_VPDPWSSDS, .Category = ND_CAT_AVXVNNI, .IsaSet = ND_SET_AVXVNNI, - .Mnemonic = 1461, + .Mnemonic = 1496, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -97928,6 +102713,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -97942,12 +102728,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3499 Instruction:"VPDPWSUD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:2 l:x w:0 0xD2 /r"/"RAVM" + // Pos:3544 Instruction:"VPDPWSUD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:2 l:x w:0 0xD2 /r"/"RAVM" { .Instruction = ND_INS_VPDPWSUD, .Category = ND_CAT_AVX10INT, .IsaSet = ND_SET_AVX102, - .Mnemonic = 1462, + .Mnemonic = 1497, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -97956,6 +102742,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -97971,12 +102758,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3500 Instruction:"VPDPWSUD Vx,Hx,Wx" Encoding:"vex m:2 p:2 l:x w:0 0xD2 /r"/"RVM" + // Pos:3545 Instruction:"VPDPWSUD Vx,Hx,Wx" Encoding:"vex m:2 p:2 l:x w:0 0xD2 /r"/"RVM" { .Instruction = ND_INS_VPDPWSUD, .Category = ND_CAT_AVXVNNIINT16, .IsaSet = ND_SET_AVXVNNIINT16, - .Mnemonic = 1462, + .Mnemonic = 1497, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -97985,6 +102772,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -97999,12 +102787,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3501 Instruction:"VPDPWSUDS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:2 l:x w:0 0xD3 /r"/"RAVM" + // Pos:3546 Instruction:"VPDPWSUDS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:2 l:x w:0 0xD3 /r"/"RAVM" { .Instruction = ND_INS_VPDPWSUDS, .Category = ND_CAT_AVX10INT, .IsaSet = ND_SET_AVX102, - .Mnemonic = 1463, + .Mnemonic = 1498, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -98013,6 +102801,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -98028,12 +102817,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3502 Instruction:"VPDPWSUDS Vx,Hx,Wx" Encoding:"vex m:2 p:2 l:x w:0 0xD3 /r"/"RVM" + // Pos:3547 Instruction:"VPDPWSUDS Vx,Hx,Wx" Encoding:"vex m:2 p:2 l:x w:0 0xD3 /r"/"RVM" { .Instruction = ND_INS_VPDPWSUDS, .Category = ND_CAT_AVXVNNIINT16, .IsaSet = ND_SET_AVXVNNIINT16, - .Mnemonic = 1463, + .Mnemonic = 1498, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -98042,6 +102831,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -98056,12 +102846,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3503 Instruction:"VPDPWUSD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0xD2 /r"/"RAVM" + // Pos:3548 Instruction:"VPDPWUSD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0xD2 /r"/"RAVM" { .Instruction = ND_INS_VPDPWUSD, .Category = ND_CAT_AVX10INT, .IsaSet = ND_SET_AVX102, - .Mnemonic = 1464, + .Mnemonic = 1499, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -98070,6 +102860,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -98085,12 +102876,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3504 Instruction:"VPDPWUSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xD2 /r"/"RVM" + // Pos:3549 Instruction:"VPDPWUSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xD2 /r"/"RVM" { .Instruction = ND_INS_VPDPWUSD, .Category = ND_CAT_AVXVNNIINT16, .IsaSet = ND_SET_AVXVNNIINT16, - .Mnemonic = 1464, + .Mnemonic = 1499, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -98099,6 +102890,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -98113,12 +102905,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3505 Instruction:"VPDPWUSDS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0xD3 /r"/"RAVM" + // Pos:3550 Instruction:"VPDPWUSDS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0xD3 /r"/"RAVM" { .Instruction = ND_INS_VPDPWUSDS, .Category = ND_CAT_AVX10INT, .IsaSet = ND_SET_AVX102, - .Mnemonic = 1465, + .Mnemonic = 1500, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -98127,6 +102919,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -98142,12 +102935,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3506 Instruction:"VPDPWUSDS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xD3 /r"/"RVM" + // Pos:3551 Instruction:"VPDPWUSDS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xD3 /r"/"RVM" { .Instruction = ND_INS_VPDPWUSDS, .Category = ND_CAT_AVXVNNIINT16, .IsaSet = ND_SET_AVXVNNIINT16, - .Mnemonic = 1465, + .Mnemonic = 1500, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -98156,6 +102949,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -98170,12 +102964,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3507 Instruction:"VPDPWUUD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:0 l:x w:0 0xD2 /r"/"RAVM" + // Pos:3552 Instruction:"VPDPWUUD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:0 l:x w:0 0xD2 /r"/"RAVM" { .Instruction = ND_INS_VPDPWUUD, .Category = ND_CAT_AVX10INT, .IsaSet = ND_SET_AVX102, - .Mnemonic = 1466, + .Mnemonic = 1501, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -98184,6 +102978,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -98199,12 +102994,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3508 Instruction:"VPDPWUUD Vx,Hx,Wx" Encoding:"vex m:2 p:0 l:x w:0 0xD2 /r"/"RVM" + // Pos:3553 Instruction:"VPDPWUUD Vx,Hx,Wx" Encoding:"vex m:2 p:0 l:x w:0 0xD2 /r"/"RVM" { .Instruction = ND_INS_VPDPWUUD, .Category = ND_CAT_AVXVNNIINT16, .IsaSet = ND_SET_AVXVNNIINT16, - .Mnemonic = 1466, + .Mnemonic = 1501, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -98213,6 +103008,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -98227,12 +103023,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3509 Instruction:"VPDPWUUDS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:0 l:x w:0 0xD3 /r"/"RAVM" + // Pos:3554 Instruction:"VPDPWUUDS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:0 l:x w:0 0xD3 /r"/"RAVM" { .Instruction = ND_INS_VPDPWUUDS, .Category = ND_CAT_AVX10INT, .IsaSet = ND_SET_AVX102, - .Mnemonic = 1467, + .Mnemonic = 1502, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -98241,6 +103037,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -98256,12 +103053,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3510 Instruction:"VPDPWUUDS Vx,Hx,Wx" Encoding:"vex m:2 p:0 l:x w:0 0xD3 /r"/"RVM" + // Pos:3555 Instruction:"VPDPWUUDS Vx,Hx,Wx" Encoding:"vex m:2 p:0 l:x w:0 0xD3 /r"/"RVM" { .Instruction = ND_INS_VPDPWUUDS, .Category = ND_CAT_AVXVNNIINT16, .IsaSet = ND_SET_AVXVNNIINT16, - .Mnemonic = 1467, + .Mnemonic = 1502, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -98270,6 +103067,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -98284,12 +103082,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3511 Instruction:"VPERM2F128 Vqq,Hqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x06 /r ib"/"RVMI" + // Pos:3556 Instruction:"VPERM2F128 Vqq,Hqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x06 /r ib"/"RVMI" { .Instruction = ND_INS_VPERM2F128, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1468, + .Mnemonic = 1503, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -98298,6 +103096,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -98313,12 +103112,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3512 Instruction:"VPERM2I128 Vqq,Hqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x46 /r ib"/"RVMI" + // Pos:3557 Instruction:"VPERM2I128 Vqq,Hqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x46 /r ib"/"RVMI" { .Instruction = ND_INS_VPERM2I128, .Category = ND_CAT_AVX2, .IsaSet = ND_SET_AVX2, - .Mnemonic = 1469, + .Mnemonic = 1504, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -98327,6 +103126,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_6, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -98342,12 +103142,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3513 Instruction:"VPERMB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x8D /r"/"RAVM" + // Pos:3558 Instruction:"VPERMB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x8D /r"/"RAVM" { .Instruction = ND_INS_VPERMB, .Category = ND_CAT_AVX512VBMI, .IsaSet = ND_SET_AVX512VBMI, - .Mnemonic = 1470, + .Mnemonic = 1505, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -98356,6 +103156,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NFnb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -98371,12 +103172,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3514 Instruction:"VPERMD Vuv{K}{z},aKq,Huv,Wuv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x36 /r"/"RAVM" + // Pos:3559 Instruction:"VPERMD Vuv{K}{z},aKq,Huv,Wuv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x36 /r"/"RAVM" { .Instruction = ND_INS_VPERMD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1471, + .Mnemonic = 1506, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -98385,6 +103186,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -98400,12 +103202,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3515 Instruction:"VPERMD Vqq,Hqq,Wqq" Encoding:"vex m:2 p:1 l:1 w:0 0x36 /r"/"RVM" + // Pos:3560 Instruction:"VPERMD Vqq,Hqq,Wqq" Encoding:"vex m:2 p:1 l:1 w:0 0x36 /r"/"RVM" { .Instruction = ND_INS_VPERMD, .Category = ND_CAT_AVX2, .IsaSet = ND_SET_AVX2, - .Mnemonic = 1471, + .Mnemonic = 1506, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -98414,6 +103216,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -98428,12 +103231,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3516 Instruction:"VPERMI2B Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x75 /r"/"RAVM" + // Pos:3561 Instruction:"VPERMI2B Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x75 /r"/"RAVM" { .Instruction = ND_INS_VPERMI2B, .Category = ND_CAT_AVX512VBMI, .IsaSet = ND_SET_AVX512VBMI, - .Mnemonic = 1472, + .Mnemonic = 1507, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -98442,6 +103245,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NFnb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -98457,12 +103261,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3517 Instruction:"VPERMI2D Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x76 /r"/"RAVM" + // Pos:3562 Instruction:"VPERMI2D Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x76 /r"/"RAVM" { .Instruction = ND_INS_VPERMI2D, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1473, + .Mnemonic = 1508, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -98471,6 +103275,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -98486,12 +103291,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3518 Instruction:"VPERMI2PD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x77 /r"/"RAVM" + // Pos:3563 Instruction:"VPERMI2PD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x77 /r"/"RAVM" { .Instruction = ND_INS_VPERMI2PD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1474, + .Mnemonic = 1509, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -98500,6 +103305,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -98515,12 +103321,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3519 Instruction:"VPERMI2PS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x77 /r"/"RAVM" + // Pos:3564 Instruction:"VPERMI2PS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x77 /r"/"RAVM" { .Instruction = ND_INS_VPERMI2PS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1475, + .Mnemonic = 1510, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -98529,6 +103335,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -98544,12 +103351,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3520 Instruction:"VPERMI2Q Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x76 /r"/"RAVM" + // Pos:3565 Instruction:"VPERMI2Q Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x76 /r"/"RAVM" { .Instruction = ND_INS_VPERMI2Q, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1476, + .Mnemonic = 1511, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -98558,6 +103365,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -98573,12 +103381,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3521 Instruction:"VPERMI2W Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x75 /r"/"RAVM" + // Pos:3566 Instruction:"VPERMI2W Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x75 /r"/"RAVM" { .Instruction = ND_INS_VPERMI2W, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1477, + .Mnemonic = 1512, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -98587,6 +103395,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NFnb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -98602,12 +103411,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3522 Instruction:"VPERMIL2PD Vx,Hx,Wx,Lx,m2zIb" Encoding:"vex m:3 p:1 l:x w:0 0x49 /r is4"/"RVMLL" + // Pos:3567 Instruction:"VPERMIL2PD Vx,Hx,Wx,Lx,m2zIb" Encoding:"vex m:3 p:1 l:x w:0 0x49 /r is4"/"RVMLL" { .Instruction = ND_INS_VPERMIL2PD, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1478, + .Mnemonic = 1513, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -98616,6 +103425,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -98632,12 +103442,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3523 Instruction:"VPERMIL2PD Vx,Hx,Lx,Wx,m2zIb" Encoding:"vex m:3 p:1 l:x w:1 0x49 /r is4"/"RVLML" + // Pos:3568 Instruction:"VPERMIL2PD Vx,Hx,Lx,Wx,m2zIb" Encoding:"vex m:3 p:1 l:x w:1 0x49 /r is4"/"RVLML" { .Instruction = ND_INS_VPERMIL2PD, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1478, + .Mnemonic = 1513, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -98646,6 +103456,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -98662,12 +103473,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3524 Instruction:"VPERMIL2PS Vx,Hx,Wx,Lx,m2zIb" Encoding:"vex m:3 p:1 l:x w:0 0x48 /r is4"/"RVMLL" + // Pos:3569 Instruction:"VPERMIL2PS Vx,Hx,Wx,Lx,m2zIb" Encoding:"vex m:3 p:1 l:x w:0 0x48 /r is4"/"RVMLL" { .Instruction = ND_INS_VPERMIL2PS, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1479, + .Mnemonic = 1514, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -98676,6 +103487,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -98692,12 +103504,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3525 Instruction:"VPERMIL2PS Vx,Hx,Lx,Wx,m2zIb" Encoding:"vex m:3 p:1 l:x w:1 0x48 /r is4"/"RVLML" + // Pos:3570 Instruction:"VPERMIL2PS Vx,Hx,Lx,Wx,m2zIb" Encoding:"vex m:3 p:1 l:x w:1 0x48 /r is4"/"RVLML" { .Instruction = ND_INS_VPERMIL2PS, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1479, + .Mnemonic = 1514, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -98706,6 +103518,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -98722,12 +103535,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3526 Instruction:"VPERMILPD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x0D /r"/"RAVM" + // Pos:3571 Instruction:"VPERMILPD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x0D /r"/"RAVM" { .Instruction = ND_INS_VPERMILPD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1480, + .Mnemonic = 1515, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -98736,6 +103549,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -98751,12 +103565,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3527 Instruction:"VPERMILPD Vfv{K}{z},aKq,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x05 /r ib"/"RAMI" + // Pos:3572 Instruction:"VPERMILPD Vfv{K}{z},aKq,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x05 /r ib"/"RAMI" { .Instruction = ND_INS_VPERMILPD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1480, + .Mnemonic = 1515, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -98765,6 +103579,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -98780,12 +103595,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3528 Instruction:"VPERMILPD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0D /r"/"RVM" + // Pos:3573 Instruction:"VPERMILPD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0D /r"/"RVM" { .Instruction = ND_INS_VPERMILPD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1480, + .Mnemonic = 1515, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -98794,6 +103609,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -98808,12 +103624,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3529 Instruction:"VPERMILPD Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:0 0x05 /r ib"/"RMI" + // Pos:3574 Instruction:"VPERMILPD Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:0 0x05 /r ib"/"RMI" { .Instruction = ND_INS_VPERMILPD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1480, + .Mnemonic = 1515, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -98822,6 +103638,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -98836,12 +103653,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3530 Instruction:"VPERMILPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x0C /r"/"RAVM" + // Pos:3575 Instruction:"VPERMILPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x0C /r"/"RAVM" { .Instruction = ND_INS_VPERMILPS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1481, + .Mnemonic = 1516, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -98850,6 +103667,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -98865,12 +103683,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3531 Instruction:"VPERMILPS Vfv{K}{z},aKq,Wfv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x04 /r ib"/"RAMI" + // Pos:3576 Instruction:"VPERMILPS Vfv{K}{z},aKq,Wfv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x04 /r ib"/"RAMI" { .Instruction = ND_INS_VPERMILPS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1481, + .Mnemonic = 1516, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -98879,6 +103697,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -98894,12 +103713,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3532 Instruction:"VPERMILPS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0C /r"/"RVM" + // Pos:3577 Instruction:"VPERMILPS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0C /r"/"RVM" { .Instruction = ND_INS_VPERMILPS, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1481, + .Mnemonic = 1516, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -98908,6 +103727,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -98922,12 +103742,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3533 Instruction:"VPERMILPS Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:0 0x04 /r ib"/"RMI" + // Pos:3578 Instruction:"VPERMILPS Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:0 0x04 /r ib"/"RMI" { .Instruction = ND_INS_VPERMILPS, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1481, + .Mnemonic = 1516, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -98936,6 +103756,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -98950,12 +103771,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3534 Instruction:"VPERMPD Vuv{K}{z},aKq,Huv,Wuv|B64" Encoding:"evex m:2 p:1 l:1 w:1 0x16 /r"/"RAVM" + // Pos:3579 Instruction:"VPERMPD Vuv{K}{z},aKq,Huv,Wuv|B64" Encoding:"evex m:2 p:1 l:1 w:1 0x16 /r"/"RAVM" { .Instruction = ND_INS_VPERMPD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1482, + .Mnemonic = 1517, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -98964,6 +103785,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -98979,12 +103801,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3535 Instruction:"VPERMPD Vuv{K}{z},aKq,Huv,Wuv|B64" Encoding:"evex m:2 p:1 l:2 w:1 0x16 /r"/"RAVM" + // Pos:3580 Instruction:"VPERMPD Vuv{K}{z},aKq,Huv,Wuv|B64" Encoding:"evex m:2 p:1 l:2 w:1 0x16 /r"/"RAVM" { .Instruction = ND_INS_VPERMPD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1482, + .Mnemonic = 1517, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -98993,6 +103815,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -99008,12 +103831,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3536 Instruction:"VPERMPD Vuv{K}{z},aKq,Wuv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x01 /r ib"/"RAMI" + // Pos:3581 Instruction:"VPERMPD Vuv{K}{z},aKq,Wuv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x01 /r ib"/"RAMI" { .Instruction = ND_INS_VPERMPD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1482, + .Mnemonic = 1517, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -99022,6 +103845,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -99037,12 +103861,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3537 Instruction:"VPERMPD Vqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:1 0x01 /r ib"/"RMI" + // Pos:3582 Instruction:"VPERMPD Vqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:1 0x01 /r ib"/"RMI" { .Instruction = ND_INS_VPERMPD, .Category = ND_CAT_AVX2, .IsaSet = ND_SET_AVX2, - .Mnemonic = 1482, + .Mnemonic = 1517, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -99051,6 +103875,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -99065,12 +103890,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3538 Instruction:"VPERMPS Vuv{K}{z},aKq,Huv,Wuv|B32" Encoding:"evex m:2 p:1 l:1 w:0 0x16 /r"/"RAVM" + // Pos:3583 Instruction:"VPERMPS Vuv{K}{z},aKq,Huv,Wuv|B32" Encoding:"evex m:2 p:1 l:1 w:0 0x16 /r"/"RAVM" { .Instruction = ND_INS_VPERMPS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1483, + .Mnemonic = 1518, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -99079,6 +103904,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -99094,12 +103920,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3539 Instruction:"VPERMPS Vuv{K}{z},aKq,Huv,Wuv|B32" Encoding:"evex m:2 p:1 l:2 w:0 0x16 /r"/"RAVM" + // Pos:3584 Instruction:"VPERMPS Vuv{K}{z},aKq,Huv,Wuv|B32" Encoding:"evex m:2 p:1 l:2 w:0 0x16 /r"/"RAVM" { .Instruction = ND_INS_VPERMPS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1483, + .Mnemonic = 1518, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -99108,6 +103934,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -99123,12 +103950,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3540 Instruction:"VPERMPS Vqq,Hqq,Wqq" Encoding:"vex m:2 p:1 l:1 w:0 0x16 /r"/"RVM" + // Pos:3585 Instruction:"VPERMPS Vqq,Hqq,Wqq" Encoding:"vex m:2 p:1 l:1 w:0 0x16 /r"/"RVM" { .Instruction = ND_INS_VPERMPS, .Category = ND_CAT_AVX2, .IsaSet = ND_SET_AVX2, - .Mnemonic = 1483, + .Mnemonic = 1518, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -99137,6 +103964,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -99151,12 +103979,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3541 Instruction:"VPERMQ Vuv{K}{z},aKq,Huv,Wuv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x36 /r"/"RAVM" + // Pos:3586 Instruction:"VPERMQ Vuv{K}{z},aKq,Huv,Wuv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x36 /r"/"RAVM" { .Instruction = ND_INS_VPERMQ, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1484, + .Mnemonic = 1519, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -99165,6 +103993,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -99180,12 +104009,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3542 Instruction:"VPERMQ Vuv{K}{z},aKq,Wuv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x00 /r ib"/"RAMI" + // Pos:3587 Instruction:"VPERMQ Vuv{K}{z},aKq,Wuv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x00 /r ib"/"RAMI" { .Instruction = ND_INS_VPERMQ, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1484, + .Mnemonic = 1519, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -99194,6 +104023,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -99209,12 +104039,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3543 Instruction:"VPERMQ Vqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:1 0x00 /r ib"/"RMI" + // Pos:3588 Instruction:"VPERMQ Vqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:1 0x00 /r ib"/"RMI" { .Instruction = ND_INS_VPERMQ, .Category = ND_CAT_AVX2, .IsaSet = ND_SET_AVX2, - .Mnemonic = 1484, + .Mnemonic = 1519, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -99223,6 +104053,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -99237,12 +104068,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3544 Instruction:"VPERMT2B Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x7D /r"/"RAVM" + // Pos:3589 Instruction:"VPERMT2B Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x7D /r"/"RAVM" { .Instruction = ND_INS_VPERMT2B, .Category = ND_CAT_AVX512VBMI, .IsaSet = ND_SET_AVX512VBMI, - .Mnemonic = 1485, + .Mnemonic = 1520, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -99251,6 +104082,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NFnb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -99266,12 +104098,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3545 Instruction:"VPERMT2D Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x7E /r"/"RAVM" + // Pos:3590 Instruction:"VPERMT2D Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x7E /r"/"RAVM" { .Instruction = ND_INS_VPERMT2D, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1486, + .Mnemonic = 1521, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -99280,6 +104112,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -99295,12 +104128,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3546 Instruction:"VPERMT2PD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x7F /r"/"RAVM" + // Pos:3591 Instruction:"VPERMT2PD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x7F /r"/"RAVM" { .Instruction = ND_INS_VPERMT2PD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1487, + .Mnemonic = 1522, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -99309,6 +104142,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -99324,12 +104158,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3547 Instruction:"VPERMT2PS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x7F /r"/"RAVM" + // Pos:3592 Instruction:"VPERMT2PS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x7F /r"/"RAVM" { .Instruction = ND_INS_VPERMT2PS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1488, + .Mnemonic = 1523, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -99338,6 +104172,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -99353,12 +104188,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3548 Instruction:"VPERMT2Q Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x7E /r"/"RAVM" + // Pos:3593 Instruction:"VPERMT2Q Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x7E /r"/"RAVM" { .Instruction = ND_INS_VPERMT2Q, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1489, + .Mnemonic = 1524, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -99367,6 +104202,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -99382,12 +104218,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3549 Instruction:"VPERMT2W Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x7D /r"/"RAVM" + // Pos:3594 Instruction:"VPERMT2W Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x7D /r"/"RAVM" { .Instruction = ND_INS_VPERMT2W, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1490, + .Mnemonic = 1525, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -99396,6 +104232,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NFnb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -99411,12 +104248,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3550 Instruction:"VPERMW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x8D /r"/"RAVM" + // Pos:3595 Instruction:"VPERMW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x8D /r"/"RAVM" { .Instruction = ND_INS_VPERMW, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1491, + .Mnemonic = 1526, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -99425,6 +104262,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NFnb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -99440,12 +104278,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3551 Instruction:"VPEXPANDB Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x62 /r"/"RAM" + // Pos:3596 Instruction:"VPEXPANDB Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x62 /r"/"RAM" { .Instruction = ND_INS_VPEXPANDB, .Category = ND_CAT_AVX512VBMI, .IsaSet = ND_SET_AVX512VBMI2, - .Mnemonic = 1492, + .Mnemonic = 1527, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -99454,6 +104292,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -99468,12 +104307,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3552 Instruction:"VPEXPANDD Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x89 /r"/"RAM" + // Pos:3597 Instruction:"VPEXPANDD Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x89 /r"/"RAM" { .Instruction = ND_INS_VPEXPANDD, .Category = ND_CAT_EXPAND, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1493, + .Mnemonic = 1528, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -99482,6 +104321,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4nb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -99496,12 +104336,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3553 Instruction:"VPEXPANDQ Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x89 /r"/"RAM" + // Pos:3598 Instruction:"VPEXPANDQ Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x89 /r"/"RAM" { .Instruction = ND_INS_VPEXPANDQ, .Category = ND_CAT_EXPAND, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1494, + .Mnemonic = 1529, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -99510,6 +104350,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4nb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -99524,12 +104365,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3554 Instruction:"VPEXPANDW Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x62 /r"/"RAM" + // Pos:3599 Instruction:"VPEXPANDW Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x62 /r"/"RAM" { .Instruction = ND_INS_VPEXPANDW, .Category = ND_CAT_AVX512VBMI, .IsaSet = ND_SET_AVX512VBMI2, - .Mnemonic = 1495, + .Mnemonic = 1530, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -99538,6 +104379,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -99552,12 +104394,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3555 Instruction:"VPEXTRB Mb,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x14 /r:mem ib"/"MRI" + // Pos:3600 Instruction:"VPEXTRB Mb,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x14 /r:mem ib"/"MRI" { .Instruction = ND_INS_VPEXTRB, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1496, + .Mnemonic = 1531, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -99566,6 +104408,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E9NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -99580,12 +104423,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3556 Instruction:"VPEXTRB Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x14 /r:reg ib"/"MRI" + // Pos:3601 Instruction:"VPEXTRB Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x14 /r:reg ib"/"MRI" { .Instruction = ND_INS_VPEXTRB, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1496, + .Mnemonic = 1531, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -99594,6 +104437,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E9NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -99608,12 +104452,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3557 Instruction:"VPEXTRB Mb,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x14 /r:mem ib"/"MRI" + // Pos:3602 Instruction:"VPEXTRB Mb,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x14 /r:mem ib"/"MRI" { .Instruction = ND_INS_VPEXTRB, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1496, + .Mnemonic = 1531, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -99622,6 +104466,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -99636,12 +104481,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3558 Instruction:"VPEXTRB Ry,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x14 /r:reg ib"/"MRI" + // Pos:3603 Instruction:"VPEXTRB Ry,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x14 /r:reg ib"/"MRI" { .Instruction = ND_INS_VPEXTRB, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1496, + .Mnemonic = 1531, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -99650,6 +104495,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -99664,12 +104510,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3559 Instruction:"VPEXTRD Md,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:0 0x16 /r:mem ib"/"MRI" + // Pos:3604 Instruction:"VPEXTRD Md,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:0 0x16 /r:mem ib"/"MRI" { .Instruction = ND_INS_VPEXTRD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 1497, + .Mnemonic = 1532, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -99678,6 +104524,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E9NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -99692,12 +104539,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3560 Instruction:"VPEXTRD Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:0 0x16 /r:reg ib"/"MRI" + // Pos:3605 Instruction:"VPEXTRD Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:0 0x16 /r:reg ib"/"MRI" { .Instruction = ND_INS_VPEXTRD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 1497, + .Mnemonic = 1532, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -99706,6 +104553,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E9NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -99720,12 +104568,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3561 Instruction:"VPEXTRD Md,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x16 /r:mem ib"/"MRI" + // Pos:3606 Instruction:"VPEXTRD Md,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x16 /r:mem ib"/"MRI" { .Instruction = ND_INS_VPEXTRD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1497, + .Mnemonic = 1532, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -99734,6 +104582,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -99748,12 +104597,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3562 Instruction:"VPEXTRD Ry,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x16 /r:reg ib"/"MRI" + // Pos:3607 Instruction:"VPEXTRD Ry,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x16 /r:reg ib"/"MRI" { .Instruction = ND_INS_VPEXTRD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1497, + .Mnemonic = 1532, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -99762,6 +104611,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -99776,12 +104626,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3563 Instruction:"VPEXTRQ Mq,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:1 0x16 /r:mem ib"/"MRI" + // Pos:3608 Instruction:"VPEXTRQ Mq,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:1 0x16 /r:mem ib"/"MRI" { .Instruction = ND_INS_VPEXTRQ, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 1498, + .Mnemonic = 1533, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -99790,6 +104640,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E9NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -99804,12 +104655,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3564 Instruction:"VPEXTRQ Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:1 0x16 /r:reg ib"/"MRI" + // Pos:3609 Instruction:"VPEXTRQ Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:1 0x16 /r:reg ib"/"MRI" { .Instruction = ND_INS_VPEXTRQ, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 1498, + .Mnemonic = 1533, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -99818,6 +104669,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E9NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -99832,12 +104684,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3565 Instruction:"VPEXTRQ Mq,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x16 /r:mem ib"/"MRI" + // Pos:3610 Instruction:"VPEXTRQ Mq,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x16 /r:mem ib"/"MRI" { .Instruction = ND_INS_VPEXTRQ, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1498, + .Mnemonic = 1533, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -99846,6 +104698,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -99860,12 +104713,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3566 Instruction:"VPEXTRQ Ry,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x16 /r:reg ib"/"MRI" + // Pos:3611 Instruction:"VPEXTRQ Ry,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x16 /r:reg ib"/"MRI" { .Instruction = ND_INS_VPEXTRQ, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1498, + .Mnemonic = 1533, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -99874,6 +104727,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -99888,12 +104742,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3567 Instruction:"VPEXTRW Gy,Udq,Ib" Encoding:"evex m:1 p:1 l:0 w:i 0xC5 /r:reg ib"/"RMI" + // Pos:3612 Instruction:"VPEXTRW Gy,Udq,Ib" Encoding:"evex m:1 p:1 l:0 w:i 0xC5 /r:reg ib"/"RMI" { .Instruction = ND_INS_VPEXTRW, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1499, + .Mnemonic = 1534, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -99902,6 +104756,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E9NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -99916,12 +104771,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3568 Instruction:"VPEXTRW Mw,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x15 /r:mem ib"/"MRI" + // Pos:3613 Instruction:"VPEXTRW Mw,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x15 /r:mem ib"/"MRI" { .Instruction = ND_INS_VPEXTRW, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1499, + .Mnemonic = 1534, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -99930,6 +104785,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E9NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -99944,12 +104800,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3569 Instruction:"VPEXTRW Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x15 /r:reg ib"/"MRI" + // Pos:3614 Instruction:"VPEXTRW Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x15 /r:reg ib"/"MRI" { .Instruction = ND_INS_VPEXTRW, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1499, + .Mnemonic = 1534, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -99958,6 +104814,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E9NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -99972,12 +104829,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3570 Instruction:"VPEXTRW Gy,Udq,Ib" Encoding:"vex m:1 p:1 l:0 w:i 0xC5 /r:reg ib"/"RMI" + // Pos:3615 Instruction:"VPEXTRW Gy,Udq,Ib" Encoding:"vex m:1 p:1 l:0 w:i 0xC5 /r:reg ib"/"RMI" { .Instruction = ND_INS_VPEXTRW, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1499, + .Mnemonic = 1534, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -99986,6 +104843,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -100000,12 +104858,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3571 Instruction:"VPEXTRW Mw,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x15 /r:mem ib"/"MRI" + // Pos:3616 Instruction:"VPEXTRW Mw,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x15 /r:mem ib"/"MRI" { .Instruction = ND_INS_VPEXTRW, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1499, + .Mnemonic = 1534, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -100014,6 +104872,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -100028,12 +104887,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3572 Instruction:"VPEXTRW Ry,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x15 /r:reg ib"/"MRI" + // Pos:3617 Instruction:"VPEXTRW Ry,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x15 /r:reg ib"/"MRI" { .Instruction = ND_INS_VPEXTRW, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1499, + .Mnemonic = 1534, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -100042,6 +104901,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -100056,12 +104916,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3573 Instruction:"VPGATHERDD Vfv{K},aKq,Mvm32n" Encoding:"evex m:2 p:1 l:x w:0 0x90 /r:mem vsib"/"RAM" + // Pos:3618 Instruction:"VPGATHERDD Vfv{K},aKq,Mvm32n" Encoding:"evex m:2 p:1 l:x w:0 0x90 /r:mem vsib"/"RAM" { .Instruction = ND_INS_VPGATHERDD, .Category = ND_CAT_GATHER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1500, + .Mnemonic = 1535, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -100070,6 +104930,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E12, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -100084,12 +104945,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3574 Instruction:"VPGATHERDD Vx,Mvm32n,Hx" Encoding:"vex m:2 p:1 l:x w:0 0x90 /r:mem vsib"/"RMV" + // Pos:3619 Instruction:"VPGATHERDD Vx,Mvm32n,Hx" Encoding:"vex m:2 p:1 l:x w:0 0x90 /r:mem vsib"/"RMV" { .Instruction = ND_INS_VPGATHERDD, .Category = ND_CAT_AVX2GATHER, .IsaSet = ND_SET_AVX2GATHER, - .Mnemonic = 1500, + .Mnemonic = 1535, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -100098,6 +104959,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_12, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -100112,12 +104974,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3575 Instruction:"VPGATHERDQ Vfv{K},aKq,Mvm32h" Encoding:"evex m:2 p:1 l:x w:1 0x90 /r:mem vsib"/"RAM" + // Pos:3620 Instruction:"VPGATHERDQ Vfv{K},aKq,Mvm32h" Encoding:"evex m:2 p:1 l:x w:1 0x90 /r:mem vsib"/"RAM" { .Instruction = ND_INS_VPGATHERDQ, .Category = ND_CAT_GATHER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1501, + .Mnemonic = 1536, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -100126,6 +104988,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E12, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -100140,12 +105003,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3576 Instruction:"VPGATHERDQ Vx,Mvm32h,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x90 /r:mem vsib"/"RMV" + // Pos:3621 Instruction:"VPGATHERDQ Vx,Mvm32h,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x90 /r:mem vsib"/"RMV" { .Instruction = ND_INS_VPGATHERDQ, .Category = ND_CAT_AVX2GATHER, .IsaSet = ND_SET_AVX2GATHER, - .Mnemonic = 1501, + .Mnemonic = 1536, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -100154,6 +105017,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_12, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -100168,12 +105032,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3577 Instruction:"VPGATHERQD Vhv{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:0 0x91 /r:mem vsib"/"RAM" + // Pos:3622 Instruction:"VPGATHERQD Vhv{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:0 0x91 /r:mem vsib"/"RAM" { .Instruction = ND_INS_VPGATHERQD, .Category = ND_CAT_GATHER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1502, + .Mnemonic = 1537, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -100182,6 +105046,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E12, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -100196,12 +105061,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3578 Instruction:"VPGATHERQD Vdq,Mvm64n,Hdq" Encoding:"vex m:2 p:1 l:x w:0 0x91 /r:mem vsib"/"RMV" + // Pos:3623 Instruction:"VPGATHERQD Vdq,Mvm64n,Hdq" Encoding:"vex m:2 p:1 l:x w:0 0x91 /r:mem vsib"/"RMV" { .Instruction = ND_INS_VPGATHERQD, .Category = ND_CAT_AVX2GATHER, .IsaSet = ND_SET_AVX2GATHER, - .Mnemonic = 1502, + .Mnemonic = 1537, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -100210,6 +105075,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_12, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -100224,12 +105090,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3579 Instruction:"VPGATHERQQ Vfv{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:1 0x91 /r:mem vsib"/"RAM" + // Pos:3624 Instruction:"VPGATHERQQ Vfv{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:1 0x91 /r:mem vsib"/"RAM" { .Instruction = ND_INS_VPGATHERQQ, .Category = ND_CAT_GATHER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1503, + .Mnemonic = 1538, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -100238,6 +105104,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E12, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -100252,12 +105119,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3580 Instruction:"VPGATHERQQ Vx,Mvm64n,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x91 /r:mem vsib"/"RMV" + // Pos:3625 Instruction:"VPGATHERQQ Vx,Mvm64n,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x91 /r:mem vsib"/"RMV" { .Instruction = ND_INS_VPGATHERQQ, .Category = ND_CAT_AVX2GATHER, .IsaSet = ND_SET_AVX2GATHER, - .Mnemonic = 1503, + .Mnemonic = 1538, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -100266,6 +105133,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_12, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -100280,12 +105148,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3581 Instruction:"VPHADDBD Vdq,Wdq" Encoding:"xop m:9 0xC2 /r"/"RM" + // Pos:3626 Instruction:"VPHADDBD Vdq,Wdq" Encoding:"xop m:9 0xC2 /r"/"RM" { .Instruction = ND_INS_VPHADDBD, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1504, + .Mnemonic = 1539, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -100294,6 +105162,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -100307,12 +105176,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3582 Instruction:"VPHADDBQ Vdq,Wdq" Encoding:"xop m:9 0xC3 /r"/"RM" + // Pos:3627 Instruction:"VPHADDBQ Vdq,Wdq" Encoding:"xop m:9 0xC3 /r"/"RM" { .Instruction = ND_INS_VPHADDBQ, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1505, + .Mnemonic = 1540, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -100321,6 +105190,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -100334,12 +105204,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3583 Instruction:"VPHADDBW Vdq,Wdq" Encoding:"xop m:9 0xC1 /r"/"RM" + // Pos:3628 Instruction:"VPHADDBW Vdq,Wdq" Encoding:"xop m:9 0xC1 /r"/"RM" { .Instruction = ND_INS_VPHADDBW, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1506, + .Mnemonic = 1541, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -100348,6 +105218,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -100361,12 +105232,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3584 Instruction:"VPHADDD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x02 /r"/"RVM" + // Pos:3629 Instruction:"VPHADDD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x02 /r"/"RVM" { .Instruction = ND_INS_VPHADDD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1507, + .Mnemonic = 1542, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -100375,6 +105246,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -100389,12 +105261,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3585 Instruction:"VPHADDDQ Vdq,Wdq" Encoding:"xop m:9 0xCB /r"/"RM" + // Pos:3630 Instruction:"VPHADDDQ Vdq,Wdq" Encoding:"xop m:9 0xCB /r"/"RM" { .Instruction = ND_INS_VPHADDDQ, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1508, + .Mnemonic = 1543, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -100403,6 +105275,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -100416,12 +105289,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3586 Instruction:"VPHADDSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x03 /r"/"RVM" + // Pos:3631 Instruction:"VPHADDSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x03 /r"/"RVM" { .Instruction = ND_INS_VPHADDSW, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1509, + .Mnemonic = 1544, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -100430,6 +105303,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -100444,12 +105318,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3587 Instruction:"VPHADDUBD Vdq,Wdq" Encoding:"xop m:9 0xD2 /r"/"RM" + // Pos:3632 Instruction:"VPHADDUBD Vdq,Wdq" Encoding:"xop m:9 0xD2 /r"/"RM" { .Instruction = ND_INS_VPHADDUBD, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1510, + .Mnemonic = 1545, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -100458,6 +105332,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -100471,12 +105346,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3588 Instruction:"VPHADDUBQ Vdq,Wdq" Encoding:"xop m:9 0xD3 /r"/"RM" + // Pos:3633 Instruction:"VPHADDUBQ Vdq,Wdq" Encoding:"xop m:9 0xD3 /r"/"RM" { .Instruction = ND_INS_VPHADDUBQ, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1511, + .Mnemonic = 1546, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -100485,6 +105360,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -100498,12 +105374,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3589 Instruction:"VPHADDUBW Vdq,Wdq" Encoding:"xop m:9 0xD1 /r"/"RM" + // Pos:3634 Instruction:"VPHADDUBW Vdq,Wdq" Encoding:"xop m:9 0xD1 /r"/"RM" { .Instruction = ND_INS_VPHADDUBW, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1512, + .Mnemonic = 1547, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -100512,6 +105388,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -100525,12 +105402,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3590 Instruction:"VPHADDUDQ Vdq,Wdq" Encoding:"xop m:9 0xDB /r"/"RM" + // Pos:3635 Instruction:"VPHADDUDQ Vdq,Wdq" Encoding:"xop m:9 0xDB /r"/"RM" { .Instruction = ND_INS_VPHADDUDQ, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1513, + .Mnemonic = 1548, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -100539,6 +105416,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -100552,12 +105430,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3591 Instruction:"VPHADDUWD Vdq,Wdq" Encoding:"xop m:9 0xD6 /r"/"RM" + // Pos:3636 Instruction:"VPHADDUWD Vdq,Wdq" Encoding:"xop m:9 0xD6 /r"/"RM" { .Instruction = ND_INS_VPHADDUWD, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1514, + .Mnemonic = 1549, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -100566,6 +105444,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -100579,12 +105458,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3592 Instruction:"VPHADDUWQ Vdq,Wdq" Encoding:"xop m:9 0xD7 /r"/"RM" + // Pos:3637 Instruction:"VPHADDUWQ Vdq,Wdq" Encoding:"xop m:9 0xD7 /r"/"RM" { .Instruction = ND_INS_VPHADDUWQ, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1515, + .Mnemonic = 1550, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -100593,6 +105472,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -100606,12 +105486,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3593 Instruction:"VPHADDW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x01 /r"/"RVM" + // Pos:3638 Instruction:"VPHADDW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x01 /r"/"RVM" { .Instruction = ND_INS_VPHADDW, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1516, + .Mnemonic = 1551, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -100620,6 +105500,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -100634,12 +105515,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3594 Instruction:"VPHADDWD Vdq,Wdq" Encoding:"xop m:9 0xC6 /r"/"RM" + // Pos:3639 Instruction:"VPHADDWD Vdq,Wdq" Encoding:"xop m:9 0xC6 /r"/"RM" { .Instruction = ND_INS_VPHADDWD, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1517, + .Mnemonic = 1552, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -100648,6 +105529,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -100661,12 +105543,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3595 Instruction:"VPHADDWQ Vdq,Wdq" Encoding:"xop m:9 0xC7 /r"/"RM" + // Pos:3640 Instruction:"VPHADDWQ Vdq,Wdq" Encoding:"xop m:9 0xC7 /r"/"RM" { .Instruction = ND_INS_VPHADDWQ, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1518, + .Mnemonic = 1553, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -100675,6 +105557,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -100688,12 +105571,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3596 Instruction:"VPHMINPOSUW Vdq,Wdq" Encoding:"vex m:2 p:1 l:0 w:i 0x41 /r"/"RM" + // Pos:3641 Instruction:"VPHMINPOSUW Vdq,Wdq" Encoding:"vex m:2 p:1 l:0 w:i 0x41 /r"/"RM" { .Instruction = ND_INS_VPHMINPOSUW, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1519, + .Mnemonic = 1554, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -100702,6 +105585,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -100715,12 +105599,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3597 Instruction:"VPHSUBBW Vdq,Wdq" Encoding:"xop m:9 0xE1 /r"/"RM" + // Pos:3642 Instruction:"VPHSUBBW Vdq,Wdq" Encoding:"xop m:9 0xE1 /r"/"RM" { .Instruction = ND_INS_VPHSUBBW, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1520, + .Mnemonic = 1555, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -100729,6 +105613,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -100742,12 +105627,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3598 Instruction:"VPHSUBD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x06 /r"/"RVM" + // Pos:3643 Instruction:"VPHSUBD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x06 /r"/"RVM" { .Instruction = ND_INS_VPHSUBD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1521, + .Mnemonic = 1556, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -100756,6 +105641,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -100770,12 +105656,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3599 Instruction:"VPHSUBDQ Vdq,Wdq" Encoding:"xop m:9 0xE3 /r"/"RM" + // Pos:3644 Instruction:"VPHSUBDQ Vdq,Wdq" Encoding:"xop m:9 0xE3 /r"/"RM" { .Instruction = ND_INS_VPHSUBDQ, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1522, + .Mnemonic = 1557, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -100784,6 +105670,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -100797,12 +105684,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3600 Instruction:"VPHSUBSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x07 /r"/"RVM" + // Pos:3645 Instruction:"VPHSUBSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x07 /r"/"RVM" { .Instruction = ND_INS_VPHSUBSW, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1523, + .Mnemonic = 1558, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -100811,6 +105698,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -100825,12 +105713,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3601 Instruction:"VPHSUBW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x05 /r"/"RVM" + // Pos:3646 Instruction:"VPHSUBW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x05 /r"/"RVM" { .Instruction = ND_INS_VPHSUBW, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1524, + .Mnemonic = 1559, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -100839,6 +105727,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -100853,12 +105742,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3602 Instruction:"VPHSUBWD Vdq,Wdq" Encoding:"xop m:9 0xE2 /r"/"RM" + // Pos:3647 Instruction:"VPHSUBWD Vdq,Wdq" Encoding:"xop m:9 0xE2 /r"/"RM" { .Instruction = ND_INS_VPHSUBWD, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1525, + .Mnemonic = 1560, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -100867,6 +105756,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -100880,12 +105770,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3603 Instruction:"VPINSRB Vdq,Hdq,Mb,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x20 /r:mem ib"/"RVMI" + // Pos:3648 Instruction:"VPINSRB Vdq,Hdq,Mb,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x20 /r:mem ib"/"RVMI" { .Instruction = ND_INS_VPINSRB, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1526, + .Mnemonic = 1561, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -100894,6 +105784,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E9NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -100909,12 +105800,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3604 Instruction:"VPINSRB Vdq,Hdq,Rd,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x20 /r:reg ib"/"RVMI" + // Pos:3649 Instruction:"VPINSRB Vdq,Hdq,Rd,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x20 /r:reg ib"/"RVMI" { .Instruction = ND_INS_VPINSRB, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1526, + .Mnemonic = 1561, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -100923,6 +105814,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E9NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -100938,12 +105830,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3605 Instruction:"VPINSRB Vdq,Hdq,Mb,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x20 /r:mem ib"/"RVMI" + // Pos:3650 Instruction:"VPINSRB Vdq,Hdq,Mb,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x20 /r:mem ib"/"RVMI" { .Instruction = ND_INS_VPINSRB, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1526, + .Mnemonic = 1561, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -100952,6 +105844,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -100967,12 +105860,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3606 Instruction:"VPINSRB Vdq,Hdq,Rd,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x20 /r:reg ib"/"RVMI" + // Pos:3651 Instruction:"VPINSRB Vdq,Hdq,Rd,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x20 /r:reg ib"/"RVMI" { .Instruction = ND_INS_VPINSRB, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1526, + .Mnemonic = 1561, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -100981,6 +105874,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -100996,12 +105890,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3607 Instruction:"VPINSRD Vdq,Hdq,Ed,Ib" Encoding:"evex m:3 p:1 l:0 w:0 0x22 /r ib"/"RVMI" + // Pos:3652 Instruction:"VPINSRD Vdq,Hdq,Ed,Ib" Encoding:"evex m:3 p:1 l:0 w:0 0x22 /r ib"/"RVMI" { .Instruction = ND_INS_VPINSRD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 1527, + .Mnemonic = 1562, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -101010,6 +105904,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E9NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -101025,12 +105920,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3608 Instruction:"VPINSRD Vdq,Hdq,Ey,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x22 /r ib"/"RVMI" + // Pos:3653 Instruction:"VPINSRD Vdq,Hdq,Ey,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x22 /r ib"/"RVMI" { .Instruction = ND_INS_VPINSRD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1527, + .Mnemonic = 1562, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -101039,6 +105934,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -101054,12 +105950,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3609 Instruction:"VPINSRQ Vdq,Hdq,Eq,Ib" Encoding:"evex m:3 p:1 l:0 w:1 0x22 /r ib"/"RVMI" + // Pos:3654 Instruction:"VPINSRQ Vdq,Hdq,Eq,Ib" Encoding:"evex m:3 p:1 l:0 w:1 0x22 /r ib"/"RVMI" { .Instruction = ND_INS_VPINSRQ, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 1528, + .Mnemonic = 1563, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -101068,6 +105964,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E9NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -101083,12 +105980,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3610 Instruction:"VPINSRQ Vdq,Hdq,Ey,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x22 /r ib"/"RVMI" + // Pos:3655 Instruction:"VPINSRQ Vdq,Hdq,Ey,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x22 /r ib"/"RVMI" { .Instruction = ND_INS_VPINSRQ, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1528, + .Mnemonic = 1563, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -101097,6 +105994,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -101112,12 +106010,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3611 Instruction:"VPINSRW Vdq,Hdq,Mw,Ib" Encoding:"evex m:1 p:1 l:0 w:i 0xC4 /r:mem ib"/"RVMI" + // Pos:3656 Instruction:"VPINSRW Vdq,Hdq,Mw,Ib" Encoding:"evex m:1 p:1 l:0 w:i 0xC4 /r:mem ib"/"RVMI" { .Instruction = ND_INS_VPINSRW, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1529, + .Mnemonic = 1564, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -101126,6 +106024,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E9NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -101141,12 +106040,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3612 Instruction:"VPINSRW Vdq,Hdq,Rv,Ib" Encoding:"evex m:1 p:1 l:0 w:i 0xC4 /r:reg ib"/"RVMI" + // Pos:3657 Instruction:"VPINSRW Vdq,Hdq,Rv,Ib" Encoding:"evex m:1 p:1 l:0 w:i 0xC4 /r:reg ib"/"RVMI" { .Instruction = ND_INS_VPINSRW, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1529, + .Mnemonic = 1564, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -101155,6 +106054,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E9NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -101170,12 +106070,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3613 Instruction:"VPINSRW Vdq,Hdq,Mw,Ib" Encoding:"vex m:1 p:1 l:0 w:i 0xC4 /r:mem ib"/"RVMI" + // Pos:3658 Instruction:"VPINSRW Vdq,Hdq,Mw,Ib" Encoding:"vex m:1 p:1 l:0 w:i 0xC4 /r:mem ib"/"RVMI" { .Instruction = ND_INS_VPINSRW, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1529, + .Mnemonic = 1564, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -101184,6 +106084,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -101199,12 +106100,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3614 Instruction:"VPINSRW Vdq,Hdq,Rd,Ib" Encoding:"vex m:1 p:1 l:0 w:i 0xC4 /r:reg ib"/"RVMI" + // Pos:3659 Instruction:"VPINSRW Vdq,Hdq,Rd,Ib" Encoding:"vex m:1 p:1 l:0 w:i 0xC4 /r:reg ib"/"RVMI" { .Instruction = ND_INS_VPINSRW, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1529, + .Mnemonic = 1564, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -101213,6 +106114,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -101228,12 +106130,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3615 Instruction:"VPLZCNTD Vfv{K}{z},aKq,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x44 /r"/"RAM" + // Pos:3660 Instruction:"VPLZCNTD Vfv{K}{z},aKq,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x44 /r"/"RAM" { .Instruction = ND_INS_VPLZCNTD, .Category = ND_CAT_CONFLICT, .IsaSet = ND_SET_AVX512CD, - .Mnemonic = 1530, + .Mnemonic = 1565, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -101242,6 +106144,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -101256,12 +106159,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3616 Instruction:"VPLZCNTQ Vfv{K}{z},aKq,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x44 /r"/"RAM" + // Pos:3661 Instruction:"VPLZCNTQ Vfv{K}{z},aKq,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x44 /r"/"RAM" { .Instruction = ND_INS_VPLZCNTQ, .Category = ND_CAT_CONFLICT, .IsaSet = ND_SET_AVX512CD, - .Mnemonic = 1531, + .Mnemonic = 1566, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -101270,6 +106173,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -101284,12 +106188,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3617 Instruction:"VPMACSDD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x9E /r is4"/"RVML" + // Pos:3662 Instruction:"VPMACSDD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x9E /r is4"/"RVML" { .Instruction = ND_INS_VPMACSDD, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1532, + .Mnemonic = 1567, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -101298,6 +106202,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -101313,12 +106218,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3618 Instruction:"VPMACSDQH Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x9F /r is4"/"RVML" + // Pos:3663 Instruction:"VPMACSDQH Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x9F /r is4"/"RVML" { .Instruction = ND_INS_VPMACSDQH, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1533, + .Mnemonic = 1568, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -101327,6 +106232,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -101342,12 +106248,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3619 Instruction:"VPMACSDQL Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x97 /r is4"/"RVML" + // Pos:3664 Instruction:"VPMACSDQL Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x97 /r is4"/"RVML" { .Instruction = ND_INS_VPMACSDQL, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1534, + .Mnemonic = 1569, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -101356,6 +106262,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -101371,12 +106278,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3620 Instruction:"VPMACSSDD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x8E /r is4"/"RVML" + // Pos:3665 Instruction:"VPMACSSDD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x8E /r is4"/"RVML" { .Instruction = ND_INS_VPMACSSDD, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1535, + .Mnemonic = 1570, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -101385,6 +106292,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -101400,12 +106308,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3621 Instruction:"VPMACSSDQH Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x8F /r is4"/"RVML" + // Pos:3666 Instruction:"VPMACSSDQH Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x8F /r is4"/"RVML" { .Instruction = ND_INS_VPMACSSDQH, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1536, + .Mnemonic = 1571, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -101414,6 +106322,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -101429,12 +106338,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3622 Instruction:"VPMACSSDQL Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x87 /r is4"/"RVML" + // Pos:3667 Instruction:"VPMACSSDQL Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x87 /r is4"/"RVML" { .Instruction = ND_INS_VPMACSSDQL, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1537, + .Mnemonic = 1572, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -101443,6 +106352,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -101458,12 +106368,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3623 Instruction:"VPMACSSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x86 /r is4"/"RVML" + // Pos:3668 Instruction:"VPMACSSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x86 /r is4"/"RVML" { .Instruction = ND_INS_VPMACSSWD, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1538, + .Mnemonic = 1573, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -101472,6 +106382,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -101487,12 +106398,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3624 Instruction:"VPMACSSWW Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x85 /r is4"/"RVML" + // Pos:3669 Instruction:"VPMACSSWW Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x85 /r is4"/"RVML" { .Instruction = ND_INS_VPMACSSWW, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1539, + .Mnemonic = 1574, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -101501,6 +106412,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -101516,12 +106428,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3625 Instruction:"VPMACSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x96 /r is4"/"RVML" + // Pos:3670 Instruction:"VPMACSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x96 /r is4"/"RVML" { .Instruction = ND_INS_VPMACSWD, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1540, + .Mnemonic = 1575, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -101530,6 +106442,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -101545,12 +106458,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3626 Instruction:"VPMACSWW Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x95 /r is4"/"RVML" + // Pos:3671 Instruction:"VPMACSWW Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x95 /r is4"/"RVML" { .Instruction = ND_INS_VPMACSWW, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1541, + .Mnemonic = 1576, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -101559,6 +106472,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -101574,12 +106488,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3627 Instruction:"VPMADCSSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0xA6 /r is4"/"RVML" + // Pos:3672 Instruction:"VPMADCSSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0xA6 /r is4"/"RVML" { .Instruction = ND_INS_VPMADCSSWD, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1542, + .Mnemonic = 1577, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -101588,6 +106502,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -101603,12 +106518,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3628 Instruction:"VPMADCSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0xB6 /r is4"/"RVML" + // Pos:3673 Instruction:"VPMADCSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0xB6 /r is4"/"RVML" { .Instruction = ND_INS_VPMADCSWD, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1543, + .Mnemonic = 1578, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -101617,6 +106532,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -101632,12 +106548,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3629 Instruction:"VPMADD52HUQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0xB5 /r"/"RAVM" + // Pos:3674 Instruction:"VPMADD52HUQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0xB5 /r"/"RAVM" { .Instruction = ND_INS_VPMADD52HUQ, .Category = ND_CAT_IFMA, .IsaSet = ND_SET_AVX512IFMA, - .Mnemonic = 1544, + .Mnemonic = 1579, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -101646,6 +106562,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -101661,12 +106578,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3630 Instruction:"VPMADD52HUQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB5 /r"/"RVM" + // Pos:3675 Instruction:"VPMADD52HUQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB5 /r"/"RVM" { .Instruction = ND_INS_VPMADD52HUQ, .Category = ND_CAT_AVXIFMA, .IsaSet = ND_SET_AVXIFMA, - .Mnemonic = 1544, + .Mnemonic = 1579, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -101675,6 +106592,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -101689,12 +106607,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3631 Instruction:"VPMADD52LUQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0xB4 /r"/"RAVM" + // Pos:3676 Instruction:"VPMADD52LUQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0xB4 /r"/"RAVM" { .Instruction = ND_INS_VPMADD52LUQ, .Category = ND_CAT_IFMA, .IsaSet = ND_SET_AVX512IFMA, - .Mnemonic = 1545, + .Mnemonic = 1580, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -101703,6 +106621,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -101718,12 +106637,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3632 Instruction:"VPMADD52LUQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB4 /r"/"RVM" + // Pos:3677 Instruction:"VPMADD52LUQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB4 /r"/"RVM" { .Instruction = ND_INS_VPMADD52LUQ, .Category = ND_CAT_AVXIFMA, .IsaSet = ND_SET_AVXIFMA, - .Mnemonic = 1545, + .Mnemonic = 1580, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -101732,6 +106651,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -101746,12 +106666,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3633 Instruction:"VPMADDUBSW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0x04 /r"/"RAVM" + // Pos:3678 Instruction:"VPMADDUBSW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0x04 /r"/"RAVM" { .Instruction = ND_INS_VPMADDUBSW, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1546, + .Mnemonic = 1581, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -101760,6 +106680,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NFnb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -101775,12 +106696,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3634 Instruction:"VPMADDUBSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x04 /r"/"RVM" + // Pos:3679 Instruction:"VPMADDUBSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x04 /r"/"RVM" { .Instruction = ND_INS_VPMADDUBSW, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1546, + .Mnemonic = 1581, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -101789,6 +106710,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -101803,12 +106725,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3635 Instruction:"VPMADDWD Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xF5 /r"/"RAVM" + // Pos:3680 Instruction:"VPMADDWD Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xF5 /r"/"RAVM" { .Instruction = ND_INS_VPMADDWD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1547, + .Mnemonic = 1582, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -101817,6 +106739,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4nb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -101832,12 +106755,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3636 Instruction:"VPMADDWD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF5 /r"/"RVM" + // Pos:3681 Instruction:"VPMADDWD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF5 /r"/"RVM" { .Instruction = ND_INS_VPMADDWD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1547, + .Mnemonic = 1582, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -101846,6 +106769,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -101860,12 +106784,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3637 Instruction:"VPMASKMOVD Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:0 0x8C /r:mem"/"RVM" + // Pos:3682 Instruction:"VPMASKMOVD Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:0 0x8C /r:mem"/"RVM" { .Instruction = ND_INS_VPMASKMOVD, .Category = ND_CAT_AVX2, .IsaSet = ND_SET_AVX2, - .Mnemonic = 1548, + .Mnemonic = 1583, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -101874,6 +106798,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_6, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -101888,12 +106813,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3638 Instruction:"VPMASKMOVD Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:0 0x8E /r:mem"/"MVR" + // Pos:3683 Instruction:"VPMASKMOVD Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:0 0x8E /r:mem"/"MVR" { .Instruction = ND_INS_VPMASKMOVD, .Category = ND_CAT_AVX2, .IsaSet = ND_SET_AVX2, - .Mnemonic = 1548, + .Mnemonic = 1583, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -101902,6 +106827,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_6, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -101916,12 +106842,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3639 Instruction:"VPMASKMOVQ Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:1 0x8C /r:mem"/"RVM" + // Pos:3684 Instruction:"VPMASKMOVQ Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:1 0x8C /r:mem"/"RVM" { .Instruction = ND_INS_VPMASKMOVQ, .Category = ND_CAT_AVX2, .IsaSet = ND_SET_AVX2, - .Mnemonic = 1549, + .Mnemonic = 1584, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -101930,6 +106856,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_6, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -101944,12 +106871,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3640 Instruction:"VPMASKMOVQ Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:1 0x8E /r:mem"/"MVR" + // Pos:3685 Instruction:"VPMASKMOVQ Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:1 0x8E /r:mem"/"MVR" { .Instruction = ND_INS_VPMASKMOVQ, .Category = ND_CAT_AVX2, .IsaSet = ND_SET_AVX2, - .Mnemonic = 1549, + .Mnemonic = 1584, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -101958,6 +106885,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_6, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -101972,12 +106900,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3641 Instruction:"VPMAXSB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0x3C /r"/"RAVM" + // Pos:3686 Instruction:"VPMAXSB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0x3C /r"/"RAVM" { .Instruction = ND_INS_VPMAXSB, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1550, + .Mnemonic = 1585, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -101986,6 +106914,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4nb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -102001,12 +106930,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3642 Instruction:"VPMAXSB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3C /r"/"RVM" + // Pos:3687 Instruction:"VPMAXSB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3C /r"/"RVM" { .Instruction = ND_INS_VPMAXSB, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1550, + .Mnemonic = 1585, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -102015,6 +106944,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -102029,12 +106959,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3643 Instruction:"VPMAXSD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x3D /r"/"RAVM" + // Pos:3688 Instruction:"VPMAXSD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x3D /r"/"RAVM" { .Instruction = ND_INS_VPMAXSD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1551, + .Mnemonic = 1586, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -102043,6 +106973,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -102058,12 +106989,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3644 Instruction:"VPMAXSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3D /r"/"RVM" + // Pos:3689 Instruction:"VPMAXSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3D /r"/"RVM" { .Instruction = ND_INS_VPMAXSD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1551, + .Mnemonic = 1586, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -102072,6 +107003,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -102086,12 +107018,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3645 Instruction:"VPMAXSQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x3D /r"/"RAVM" + // Pos:3690 Instruction:"VPMAXSQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x3D /r"/"RAVM" { .Instruction = ND_INS_VPMAXSQ, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1552, + .Mnemonic = 1587, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -102100,6 +107032,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -102115,12 +107048,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3646 Instruction:"VPMAXSW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xEE /r"/"RAVM" + // Pos:3691 Instruction:"VPMAXSW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xEE /r"/"RAVM" { .Instruction = ND_INS_VPMAXSW, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1553, + .Mnemonic = 1588, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -102129,6 +107062,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4nb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -102144,12 +107078,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3647 Instruction:"VPMAXSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEE /r"/"RVM" + // Pos:3692 Instruction:"VPMAXSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEE /r"/"RVM" { .Instruction = ND_INS_VPMAXSW, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1553, + .Mnemonic = 1588, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -102158,6 +107092,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -102172,12 +107107,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3648 Instruction:"VPMAXUB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xDE /r"/"RAVM" + // Pos:3693 Instruction:"VPMAXUB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xDE /r"/"RAVM" { .Instruction = ND_INS_VPMAXUB, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1554, + .Mnemonic = 1589, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -102186,6 +107121,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4nb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -102201,12 +107137,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3649 Instruction:"VPMAXUB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDE /r"/"RVM" + // Pos:3694 Instruction:"VPMAXUB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDE /r"/"RVM" { .Instruction = ND_INS_VPMAXUB, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1554, + .Mnemonic = 1589, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -102215,6 +107151,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -102229,12 +107166,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3650 Instruction:"VPMAXUD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x3F /r"/"RAVM" + // Pos:3695 Instruction:"VPMAXUD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x3F /r"/"RAVM" { .Instruction = ND_INS_VPMAXUD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1555, + .Mnemonic = 1590, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -102243,6 +107180,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4nb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -102258,12 +107196,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3651 Instruction:"VPMAXUD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3F /r"/"RVM" + // Pos:3696 Instruction:"VPMAXUD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3F /r"/"RVM" { .Instruction = ND_INS_VPMAXUD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1555, + .Mnemonic = 1590, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -102272,6 +107210,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -102286,12 +107225,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3652 Instruction:"VPMAXUQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x3F /r"/"RAVM" + // Pos:3697 Instruction:"VPMAXUQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x3F /r"/"RAVM" { .Instruction = ND_INS_VPMAXUQ, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1556, + .Mnemonic = 1591, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -102300,6 +107239,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -102315,12 +107255,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3653 Instruction:"VPMAXUW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0x3E /r"/"RAVM" + // Pos:3698 Instruction:"VPMAXUW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0x3E /r"/"RAVM" { .Instruction = ND_INS_VPMAXUW, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1557, + .Mnemonic = 1592, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -102329,6 +107269,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4nb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -102344,12 +107285,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3654 Instruction:"VPMAXUW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3E /r"/"RVM" + // Pos:3699 Instruction:"VPMAXUW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3E /r"/"RVM" { .Instruction = ND_INS_VPMAXUW, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1557, + .Mnemonic = 1592, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -102358,6 +107299,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -102372,12 +107314,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3655 Instruction:"VPMINSB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0x38 /r"/"RAVM" + // Pos:3700 Instruction:"VPMINSB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0x38 /r"/"RAVM" { .Instruction = ND_INS_VPMINSB, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1558, + .Mnemonic = 1593, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -102386,6 +107328,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4nb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -102401,12 +107344,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3656 Instruction:"VPMINSB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x38 /r"/"RVM" + // Pos:3701 Instruction:"VPMINSB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x38 /r"/"RVM" { .Instruction = ND_INS_VPMINSB, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1558, + .Mnemonic = 1593, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -102415,6 +107358,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -102429,12 +107373,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3657 Instruction:"VPMINSD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x39 /r"/"RAVM" + // Pos:3702 Instruction:"VPMINSD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x39 /r"/"RAVM" { .Instruction = ND_INS_VPMINSD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1559, + .Mnemonic = 1594, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -102443,6 +107387,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -102458,12 +107403,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3658 Instruction:"VPMINSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x39 /r"/"RVM" + // Pos:3703 Instruction:"VPMINSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x39 /r"/"RVM" { .Instruction = ND_INS_VPMINSD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1559, + .Mnemonic = 1594, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -102472,6 +107417,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -102486,12 +107432,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3659 Instruction:"VPMINSQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x39 /r"/"RAVM" + // Pos:3704 Instruction:"VPMINSQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x39 /r"/"RAVM" { .Instruction = ND_INS_VPMINSQ, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1560, + .Mnemonic = 1595, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -102500,6 +107446,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -102515,12 +107462,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3660 Instruction:"VPMINSW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xEA /r"/"RAVM" + // Pos:3705 Instruction:"VPMINSW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xEA /r"/"RAVM" { .Instruction = ND_INS_VPMINSW, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1561, + .Mnemonic = 1596, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -102529,6 +107476,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4nb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -102544,12 +107492,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3661 Instruction:"VPMINSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEA /r"/"RVM" + // Pos:3706 Instruction:"VPMINSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEA /r"/"RVM" { .Instruction = ND_INS_VPMINSW, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1561, + .Mnemonic = 1596, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -102558,6 +107506,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -102572,12 +107521,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3662 Instruction:"VPMINUB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xDA /r"/"RAVM" + // Pos:3707 Instruction:"VPMINUB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xDA /r"/"RAVM" { .Instruction = ND_INS_VPMINUB, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1562, + .Mnemonic = 1597, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -102586,6 +107535,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4nb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -102601,12 +107551,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3663 Instruction:"VPMINUB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDA /r"/"RVM" + // Pos:3708 Instruction:"VPMINUB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDA /r"/"RVM" { .Instruction = ND_INS_VPMINUB, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1562, + .Mnemonic = 1597, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -102615,6 +107565,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -102629,12 +107580,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3664 Instruction:"VPMINUD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x3B /r"/"RAVM" + // Pos:3709 Instruction:"VPMINUD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x3B /r"/"RAVM" { .Instruction = ND_INS_VPMINUD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1563, + .Mnemonic = 1598, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -102643,6 +107594,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -102658,12 +107610,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3665 Instruction:"VPMINUD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3B /r"/"RVM" + // Pos:3710 Instruction:"VPMINUD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3B /r"/"RVM" { .Instruction = ND_INS_VPMINUD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1563, + .Mnemonic = 1598, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -102672,6 +107624,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -102686,12 +107639,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3666 Instruction:"VPMINUQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x3B /r"/"RAVM" + // Pos:3711 Instruction:"VPMINUQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x3B /r"/"RAVM" { .Instruction = ND_INS_VPMINUQ, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1564, + .Mnemonic = 1599, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -102700,6 +107653,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -102715,12 +107669,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3667 Instruction:"VPMINUW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0x3A /r"/"RAVM" + // Pos:3712 Instruction:"VPMINUW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0x3A /r"/"RAVM" { .Instruction = ND_INS_VPMINUW, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1565, + .Mnemonic = 1600, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -102729,6 +107683,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4nb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -102744,12 +107699,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3668 Instruction:"VPMINUW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3A /r"/"RVM" + // Pos:3713 Instruction:"VPMINUW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3A /r"/"RVM" { .Instruction = ND_INS_VPMINUW, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1565, + .Mnemonic = 1600, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -102758,6 +107713,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -102772,12 +107728,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3669 Instruction:"VPMOVB2M rKq,Ufv" Encoding:"evex m:2 p:2 l:x w:0 0x29 /r:reg"/"RM" + // Pos:3714 Instruction:"VPMOVB2M rKq,Ufv" Encoding:"evex m:2 p:2 l:x w:0 0x29 /r:reg"/"RM" { .Instruction = ND_INS_VPMOVB2M, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1566, + .Mnemonic = 1601, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -102786,6 +107742,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E7NM, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -102799,12 +107756,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3670 Instruction:"VPMOVD2M rKq,Ufv" Encoding:"evex m:2 p:2 l:x w:0 0x39 /r:reg"/"RM" + // Pos:3715 Instruction:"VPMOVD2M rKq,Ufv" Encoding:"evex m:2 p:2 l:x w:0 0x39 /r:reg"/"RM" { .Instruction = ND_INS_VPMOVD2M, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 1567, + .Mnemonic = 1602, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -102813,6 +107770,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E7NM, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -102826,12 +107784,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3671 Instruction:"VPMOVDB Wqv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x31 /r"/"MAR" + // Pos:3716 Instruction:"VPMOVDB Wqv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x31 /r"/"MAR" { .Instruction = ND_INS_VPMOVDB, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1568, + .Mnemonic = 1603, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -102840,6 +107798,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E6, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -102854,12 +107813,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3672 Instruction:"VPMOVDW Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x33 /r"/"MAR" + // Pos:3717 Instruction:"VPMOVDW Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x33 /r"/"MAR" { .Instruction = ND_INS_VPMOVDW, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1569, + .Mnemonic = 1604, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -102868,6 +107827,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E6, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -102882,12 +107842,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3673 Instruction:"VPMOVM2B Vfv,mKq" Encoding:"evex m:2 p:2 l:x w:0 0x28 /r:reg"/"RM" + // Pos:3718 Instruction:"VPMOVM2B Vfv,mKq" Encoding:"evex m:2 p:2 l:x w:0 0x28 /r:reg"/"RM" { .Instruction = ND_INS_VPMOVM2B, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1570, + .Mnemonic = 1605, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -102896,6 +107856,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E7NM, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -102909,12 +107870,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3674 Instruction:"VPMOVM2D Vfv,mKq" Encoding:"evex m:2 p:2 l:x w:0 0x38 /r:reg"/"RM" + // Pos:3719 Instruction:"VPMOVM2D Vfv,mKq" Encoding:"evex m:2 p:2 l:x w:0 0x38 /r:reg"/"RM" { .Instruction = ND_INS_VPMOVM2D, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 1571, + .Mnemonic = 1606, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -102923,6 +107884,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E7NM, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -102936,12 +107898,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3675 Instruction:"VPMOVM2Q Vfv,mKq" Encoding:"evex m:2 p:2 l:x w:1 0x38 /r:reg"/"RM" + // Pos:3720 Instruction:"VPMOVM2Q Vfv,mKq" Encoding:"evex m:2 p:2 l:x w:1 0x38 /r:reg"/"RM" { .Instruction = ND_INS_VPMOVM2Q, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 1572, + .Mnemonic = 1607, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -102950,6 +107912,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E7NM, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -102963,12 +107926,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3676 Instruction:"VPMOVM2W Vfv,mKq" Encoding:"evex m:2 p:2 l:x w:1 0x28 /r:reg"/"RM" + // Pos:3721 Instruction:"VPMOVM2W Vfv,mKq" Encoding:"evex m:2 p:2 l:x w:1 0x28 /r:reg"/"RM" { .Instruction = ND_INS_VPMOVM2W, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1573, + .Mnemonic = 1608, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -102977,6 +107940,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E7NM, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -102990,12 +107954,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3677 Instruction:"VPMOVMSKB Gy,Ux" Encoding:"vex m:1 p:1 l:x w:i 0xD7 /r:reg"/"RM" + // Pos:3722 Instruction:"VPMOVMSKB Gy,Ux" Encoding:"vex m:1 p:1 l:x w:i 0xD7 /r:reg"/"RM" { .Instruction = ND_INS_VPMOVMSKB, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX, - .Mnemonic = 1574, + .Mnemonic = 1609, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -103004,6 +107968,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_7, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -103017,12 +107982,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3678 Instruction:"VPMOVQ2M rKq,Ufv" Encoding:"evex m:2 p:2 l:x w:1 0x39 /r:reg"/"RM" + // Pos:3723 Instruction:"VPMOVQ2M rKq,Ufv" Encoding:"evex m:2 p:2 l:x w:1 0x39 /r:reg"/"RM" { .Instruction = ND_INS_VPMOVQ2M, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 1575, + .Mnemonic = 1610, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -103031,6 +107996,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E7NM, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -103044,12 +108010,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3679 Instruction:"VPMOVQB Wev{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x32 /r"/"MAR" + // Pos:3724 Instruction:"VPMOVQB Wev{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x32 /r"/"MAR" { .Instruction = ND_INS_VPMOVQB, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1576, + .Mnemonic = 1611, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -103058,6 +108024,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E6, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -103072,12 +108039,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3680 Instruction:"VPMOVQD Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x35 /r"/"MAR" + // Pos:3725 Instruction:"VPMOVQD Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x35 /r"/"MAR" { .Instruction = ND_INS_VPMOVQD, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1577, + .Mnemonic = 1612, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -103086,6 +108053,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E6, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -103100,12 +108068,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3681 Instruction:"VPMOVQW Wqv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x34 /r"/"MAR" + // Pos:3726 Instruction:"VPMOVQW Wqv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x34 /r"/"MAR" { .Instruction = ND_INS_VPMOVQW, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1578, + .Mnemonic = 1613, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -103114,6 +108082,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E6, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -103128,12 +108097,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3682 Instruction:"VPMOVSDB Wqv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x21 /r"/"MAR" + // Pos:3727 Instruction:"VPMOVSDB Wqv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x21 /r"/"MAR" { .Instruction = ND_INS_VPMOVSDB, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1579, + .Mnemonic = 1614, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -103142,6 +108111,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E6, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -103156,12 +108126,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3683 Instruction:"VPMOVSDW Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x23 /r"/"MAR" + // Pos:3728 Instruction:"VPMOVSDW Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x23 /r"/"MAR" { .Instruction = ND_INS_VPMOVSDW, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1580, + .Mnemonic = 1615, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -103170,6 +108140,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E6, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -103184,12 +108155,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3684 Instruction:"VPMOVSQB Wev{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x22 /r"/"MAR" + // Pos:3729 Instruction:"VPMOVSQB Wev{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x22 /r"/"MAR" { .Instruction = ND_INS_VPMOVSQB, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1581, + .Mnemonic = 1616, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -103198,6 +108169,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E6, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -103212,12 +108184,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3685 Instruction:"VPMOVSQD Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x25 /r"/"MAR" + // Pos:3730 Instruction:"VPMOVSQD Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x25 /r"/"MAR" { .Instruction = ND_INS_VPMOVSQD, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1582, + .Mnemonic = 1617, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -103226,6 +108198,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E6, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -103240,12 +108213,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3686 Instruction:"VPMOVSQW Wqv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x24 /r"/"MAR" + // Pos:3731 Instruction:"VPMOVSQW Wqv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x24 /r"/"MAR" { .Instruction = ND_INS_VPMOVSQW, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1583, + .Mnemonic = 1618, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -103254,6 +108227,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E6, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -103268,12 +108242,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3687 Instruction:"VPMOVSWB Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x20 /r"/"MAR" + // Pos:3732 Instruction:"VPMOVSWB Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x20 /r"/"MAR" { .Instruction = ND_INS_VPMOVSWB, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1584, + .Mnemonic = 1619, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -103282,6 +108256,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E6, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -103296,12 +108271,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3688 Instruction:"VPMOVSXBD Vfv{K}{z},aKq,Wqv" Encoding:"evex m:2 p:1 l:x w:i 0x21 /r"/"RAM" + // Pos:3733 Instruction:"VPMOVSXBD Vfv{K}{z},aKq,Wqv" Encoding:"evex m:2 p:1 l:x w:i 0x21 /r"/"RAM" { .Instruction = ND_INS_VPMOVSXBD, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1585, + .Mnemonic = 1620, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -103310,6 +108285,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -103324,12 +108300,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3689 Instruction:"VPMOVSXBD Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x21 /r"/"RM" + // Pos:3734 Instruction:"VPMOVSXBD Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x21 /r"/"RM" { .Instruction = ND_INS_VPMOVSXBD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1585, + .Mnemonic = 1620, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -103338,6 +108314,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -103351,12 +108328,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3690 Instruction:"VPMOVSXBD Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x21 /r"/"RM" + // Pos:3735 Instruction:"VPMOVSXBD Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x21 /r"/"RM" { .Instruction = ND_INS_VPMOVSXBD, .Category = ND_CAT_AVX2, .IsaSet = ND_SET_AVX2, - .Mnemonic = 1585, + .Mnemonic = 1620, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -103365,6 +108342,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -103378,12 +108356,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3691 Instruction:"VPMOVSXBQ Vfv{K}{z},aKq,Wev" Encoding:"evex m:2 p:1 l:x w:i 0x22 /r"/"RAM" + // Pos:3736 Instruction:"VPMOVSXBQ Vfv{K}{z},aKq,Wev" Encoding:"evex m:2 p:1 l:x w:i 0x22 /r"/"RAM" { .Instruction = ND_INS_VPMOVSXBQ, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1586, + .Mnemonic = 1621, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -103392,6 +108370,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -103406,12 +108385,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3692 Instruction:"VPMOVSXBQ Vdq,Ww" Encoding:"vex m:2 p:1 l:0 w:i 0x22 /r"/"RM" + // Pos:3737 Instruction:"VPMOVSXBQ Vdq,Ww" Encoding:"vex m:2 p:1 l:0 w:i 0x22 /r"/"RM" { .Instruction = ND_INS_VPMOVSXBQ, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1586, + .Mnemonic = 1621, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -103420,6 +108399,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -103433,12 +108413,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3693 Instruction:"VPMOVSXBQ Vqq,Wd" Encoding:"vex m:2 p:1 l:1 w:i 0x22 /r"/"RM" + // Pos:3738 Instruction:"VPMOVSXBQ Vqq,Wd" Encoding:"vex m:2 p:1 l:1 w:i 0x22 /r"/"RM" { .Instruction = ND_INS_VPMOVSXBQ, .Category = ND_CAT_AVX2, .IsaSet = ND_SET_AVX2, - .Mnemonic = 1586, + .Mnemonic = 1621, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -103447,6 +108427,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -103460,12 +108441,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3694 Instruction:"VPMOVSXBW Vfv{K}{z},aKq,Whv" Encoding:"evex m:2 p:1 l:x w:i 0x20 /r"/"RAM" + // Pos:3739 Instruction:"VPMOVSXBW Vfv{K}{z},aKq,Whv" Encoding:"evex m:2 p:1 l:x w:i 0x20 /r"/"RAM" { .Instruction = ND_INS_VPMOVSXBW, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1587, + .Mnemonic = 1622, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -103474,6 +108455,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -103488,12 +108470,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3695 Instruction:"VPMOVSXBW Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x20 /r"/"RM" + // Pos:3740 Instruction:"VPMOVSXBW Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x20 /r"/"RM" { .Instruction = ND_INS_VPMOVSXBW, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1587, + .Mnemonic = 1622, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -103502,6 +108484,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -103515,12 +108498,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3696 Instruction:"VPMOVSXBW Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x20 /r"/"RM" + // Pos:3741 Instruction:"VPMOVSXBW Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x20 /r"/"RM" { .Instruction = ND_INS_VPMOVSXBW, .Category = ND_CAT_AVX2, .IsaSet = ND_SET_AVX2, - .Mnemonic = 1587, + .Mnemonic = 1622, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -103529,6 +108512,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -103542,12 +108526,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3697 Instruction:"VPMOVSXDQ Vfv{K}{z},aKq,Whv" Encoding:"evex m:2 p:1 l:x w:0 0x25 /r"/"RAM" + // Pos:3742 Instruction:"VPMOVSXDQ Vfv{K}{z},aKq,Whv" Encoding:"evex m:2 p:1 l:x w:0 0x25 /r"/"RAM" { .Instruction = ND_INS_VPMOVSXDQ, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1588, + .Mnemonic = 1623, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -103556,6 +108540,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -103570,12 +108555,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3698 Instruction:"VPMOVSXDQ Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x25 /r"/"RM" + // Pos:3743 Instruction:"VPMOVSXDQ Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x25 /r"/"RM" { .Instruction = ND_INS_VPMOVSXDQ, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1588, + .Mnemonic = 1623, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -103584,6 +108569,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -103597,12 +108583,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3699 Instruction:"VPMOVSXDQ Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x25 /r"/"RM" + // Pos:3744 Instruction:"VPMOVSXDQ Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x25 /r"/"RM" { .Instruction = ND_INS_VPMOVSXDQ, .Category = ND_CAT_AVX2, .IsaSet = ND_SET_AVX2, - .Mnemonic = 1588, + .Mnemonic = 1623, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -103611,6 +108597,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -103624,12 +108611,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3700 Instruction:"VPMOVSXWD Vfv{K}{z},aKq,Whv" Encoding:"evex m:2 p:1 l:x w:i 0x23 /r"/"RAM" + // Pos:3745 Instruction:"VPMOVSXWD Vfv{K}{z},aKq,Whv" Encoding:"evex m:2 p:1 l:x w:i 0x23 /r"/"RAM" { .Instruction = ND_INS_VPMOVSXWD, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1589, + .Mnemonic = 1624, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -103638,6 +108625,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -103652,12 +108640,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3701 Instruction:"VPMOVSXWD Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x23 /r"/"RM" + // Pos:3746 Instruction:"VPMOVSXWD Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x23 /r"/"RM" { .Instruction = ND_INS_VPMOVSXWD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1589, + .Mnemonic = 1624, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -103666,6 +108654,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -103679,12 +108668,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3702 Instruction:"VPMOVSXWD Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x23 /r"/"RM" + // Pos:3747 Instruction:"VPMOVSXWD Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x23 /r"/"RM" { .Instruction = ND_INS_VPMOVSXWD, .Category = ND_CAT_AVX2, .IsaSet = ND_SET_AVX2, - .Mnemonic = 1589, + .Mnemonic = 1624, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -103693,6 +108682,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -103706,12 +108696,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3703 Instruction:"VPMOVSXWQ Vfv{K}{z},aKq,Wqv" Encoding:"evex m:2 p:1 l:x w:i 0x24 /r"/"RAM" + // Pos:3748 Instruction:"VPMOVSXWQ Vfv{K}{z},aKq,Wqv" Encoding:"evex m:2 p:1 l:x w:i 0x24 /r"/"RAM" { .Instruction = ND_INS_VPMOVSXWQ, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1590, + .Mnemonic = 1625, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -103720,6 +108710,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -103734,12 +108725,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3704 Instruction:"VPMOVSXWQ Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x24 /r"/"RM" + // Pos:3749 Instruction:"VPMOVSXWQ Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x24 /r"/"RM" { .Instruction = ND_INS_VPMOVSXWQ, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1590, + .Mnemonic = 1625, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -103748,6 +108739,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -103761,12 +108753,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3705 Instruction:"VPMOVSXWQ Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x24 /r"/"RM" + // Pos:3750 Instruction:"VPMOVSXWQ Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x24 /r"/"RM" { .Instruction = ND_INS_VPMOVSXWQ, .Category = ND_CAT_AVX2, .IsaSet = ND_SET_AVX2, - .Mnemonic = 1590, + .Mnemonic = 1625, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -103775,6 +108767,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -103788,12 +108781,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3706 Instruction:"VPMOVUSDB Wqv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x11 /r"/"MAR" + // Pos:3751 Instruction:"VPMOVUSDB Wqv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x11 /r"/"MAR" { .Instruction = ND_INS_VPMOVUSDB, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1591, + .Mnemonic = 1626, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -103802,6 +108795,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E6, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -103816,12 +108810,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3707 Instruction:"VPMOVUSDW Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x13 /r"/"MAR" + // Pos:3752 Instruction:"VPMOVUSDW Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x13 /r"/"MAR" { .Instruction = ND_INS_VPMOVUSDW, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1592, + .Mnemonic = 1627, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -103830,6 +108824,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E6, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -103844,12 +108839,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3708 Instruction:"VPMOVUSQB Wev{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x12 /r"/"MAR" + // Pos:3753 Instruction:"VPMOVUSQB Wev{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x12 /r"/"MAR" { .Instruction = ND_INS_VPMOVUSQB, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1593, + .Mnemonic = 1628, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -103858,6 +108853,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E6, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -103872,12 +108868,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3709 Instruction:"VPMOVUSQD Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x15 /r"/"MAR" + // Pos:3754 Instruction:"VPMOVUSQD Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x15 /r"/"MAR" { .Instruction = ND_INS_VPMOVUSQD, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1594, + .Mnemonic = 1629, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -103886,6 +108882,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E6, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -103900,12 +108897,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3710 Instruction:"VPMOVUSQW Wqv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x14 /r"/"MAR" + // Pos:3755 Instruction:"VPMOVUSQW Wqv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x14 /r"/"MAR" { .Instruction = ND_INS_VPMOVUSQW, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1595, + .Mnemonic = 1630, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -103914,6 +108911,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E6, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -103928,12 +108926,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3711 Instruction:"VPMOVUSWB Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x10 /r"/"MAR" + // Pos:3756 Instruction:"VPMOVUSWB Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x10 /r"/"MAR" { .Instruction = ND_INS_VPMOVUSWB, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1596, + .Mnemonic = 1631, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -103942,6 +108940,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E6, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -103956,12 +108955,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3712 Instruction:"VPMOVW2M rKq,Ufv" Encoding:"evex m:2 p:2 l:x w:1 0x29 /r:reg"/"RM" + // Pos:3757 Instruction:"VPMOVW2M rKq,Ufv" Encoding:"evex m:2 p:2 l:x w:1 0x29 /r:reg"/"RM" { .Instruction = ND_INS_VPMOVW2M, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1597, + .Mnemonic = 1632, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -103970,6 +108969,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E7NM, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -103983,12 +108983,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3713 Instruction:"VPMOVWB Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x30 /r"/"MAR" + // Pos:3758 Instruction:"VPMOVWB Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x30 /r"/"MAR" { .Instruction = ND_INS_VPMOVWB, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1598, + .Mnemonic = 1633, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -103997,6 +108997,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E6, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -104011,12 +109012,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3714 Instruction:"VPMOVZXBD Vfv{K}{z},aKq,Wqv" Encoding:"evex m:2 p:1 l:x w:i 0x31 /r"/"RAM" + // Pos:3759 Instruction:"VPMOVZXBD Vfv{K}{z},aKq,Wqv" Encoding:"evex m:2 p:1 l:x w:i 0x31 /r"/"RAM" { .Instruction = ND_INS_VPMOVZXBD, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1599, + .Mnemonic = 1634, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -104025,6 +109026,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -104039,12 +109041,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3715 Instruction:"VPMOVZXBD Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x31 /r"/"RM" + // Pos:3760 Instruction:"VPMOVZXBD Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x31 /r"/"RM" { .Instruction = ND_INS_VPMOVZXBD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1599, + .Mnemonic = 1634, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -104053,6 +109055,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -104066,12 +109069,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3716 Instruction:"VPMOVZXBD Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x31 /r"/"RM" + // Pos:3761 Instruction:"VPMOVZXBD Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x31 /r"/"RM" { .Instruction = ND_INS_VPMOVZXBD, .Category = ND_CAT_AVX2, .IsaSet = ND_SET_AVX2, - .Mnemonic = 1599, + .Mnemonic = 1634, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -104080,6 +109083,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -104093,12 +109097,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3717 Instruction:"VPMOVZXBQ Vfv{K}{z},aKq,Wev" Encoding:"evex m:2 p:1 l:x w:i 0x32 /r"/"RAM" + // Pos:3762 Instruction:"VPMOVZXBQ Vfv{K}{z},aKq,Wev" Encoding:"evex m:2 p:1 l:x w:i 0x32 /r"/"RAM" { .Instruction = ND_INS_VPMOVZXBQ, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1600, + .Mnemonic = 1635, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -104107,6 +109111,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -104121,12 +109126,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3718 Instruction:"VPMOVZXBQ Vdq,Ww" Encoding:"vex m:2 p:1 l:0 w:i 0x32 /r"/"RM" + // Pos:3763 Instruction:"VPMOVZXBQ Vdq,Ww" Encoding:"vex m:2 p:1 l:0 w:i 0x32 /r"/"RM" { .Instruction = ND_INS_VPMOVZXBQ, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1600, + .Mnemonic = 1635, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -104135,6 +109140,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -104148,12 +109154,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3719 Instruction:"VPMOVZXBQ Vqq,Wd" Encoding:"vex m:2 p:1 l:1 w:i 0x32 /r"/"RM" + // Pos:3764 Instruction:"VPMOVZXBQ Vqq,Wd" Encoding:"vex m:2 p:1 l:1 w:i 0x32 /r"/"RM" { .Instruction = ND_INS_VPMOVZXBQ, .Category = ND_CAT_AVX2, .IsaSet = ND_SET_AVX2, - .Mnemonic = 1600, + .Mnemonic = 1635, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -104162,6 +109168,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -104175,12 +109182,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3720 Instruction:"VPMOVZXBW Vfv{K}{z},aKq,Whv" Encoding:"evex m:2 p:1 l:x w:i 0x30 /r"/"RAM" + // Pos:3765 Instruction:"VPMOVZXBW Vfv{K}{z},aKq,Whv" Encoding:"evex m:2 p:1 l:x w:i 0x30 /r"/"RAM" { .Instruction = ND_INS_VPMOVZXBW, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1601, + .Mnemonic = 1636, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -104189,6 +109196,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -104203,12 +109211,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3721 Instruction:"VPMOVZXBW Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x30 /r"/"RM" + // Pos:3766 Instruction:"VPMOVZXBW Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x30 /r"/"RM" { .Instruction = ND_INS_VPMOVZXBW, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1601, + .Mnemonic = 1636, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -104217,6 +109225,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -104230,12 +109239,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3722 Instruction:"VPMOVZXBW Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x30 /r"/"RM" + // Pos:3767 Instruction:"VPMOVZXBW Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x30 /r"/"RM" { .Instruction = ND_INS_VPMOVZXBW, .Category = ND_CAT_AVX2, .IsaSet = ND_SET_AVX2, - .Mnemonic = 1601, + .Mnemonic = 1636, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -104244,6 +109253,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -104257,12 +109267,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3723 Instruction:"VPMOVZXDQ Vfv{K}{z},aKq,Whv" Encoding:"evex m:2 p:1 l:x w:0 0x35 /r"/"RAM" + // Pos:3768 Instruction:"VPMOVZXDQ Vfv{K}{z},aKq,Whv" Encoding:"evex m:2 p:1 l:x w:0 0x35 /r"/"RAM" { .Instruction = ND_INS_VPMOVZXDQ, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1602, + .Mnemonic = 1637, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -104271,6 +109281,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -104285,12 +109296,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3724 Instruction:"VPMOVZXDQ Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x35 /r"/"RM" + // Pos:3769 Instruction:"VPMOVZXDQ Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x35 /r"/"RM" { .Instruction = ND_INS_VPMOVZXDQ, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1602, + .Mnemonic = 1637, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -104299,6 +109310,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -104312,12 +109324,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3725 Instruction:"VPMOVZXDQ Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x35 /r"/"RM" + // Pos:3770 Instruction:"VPMOVZXDQ Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x35 /r"/"RM" { .Instruction = ND_INS_VPMOVZXDQ, .Category = ND_CAT_AVX2, .IsaSet = ND_SET_AVX2, - .Mnemonic = 1602, + .Mnemonic = 1637, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -104326,6 +109338,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -104339,12 +109352,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3726 Instruction:"VPMOVZXWD Vfv{K}{z},aKq,Whv" Encoding:"evex m:2 p:1 l:x w:i 0x33 /r"/"RAM" + // Pos:3771 Instruction:"VPMOVZXWD Vfv{K}{z},aKq,Whv" Encoding:"evex m:2 p:1 l:x w:i 0x33 /r"/"RAM" { .Instruction = ND_INS_VPMOVZXWD, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1603, + .Mnemonic = 1638, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -104353,6 +109366,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -104367,12 +109381,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3727 Instruction:"VPMOVZXWD Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x33 /r"/"RM" + // Pos:3772 Instruction:"VPMOVZXWD Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x33 /r"/"RM" { .Instruction = ND_INS_VPMOVZXWD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1603, + .Mnemonic = 1638, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -104381,6 +109395,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -104394,12 +109409,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3728 Instruction:"VPMOVZXWD Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x33 /r"/"RM" + // Pos:3773 Instruction:"VPMOVZXWD Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x33 /r"/"RM" { .Instruction = ND_INS_VPMOVZXWD, .Category = ND_CAT_AVX2, .IsaSet = ND_SET_AVX2, - .Mnemonic = 1603, + .Mnemonic = 1638, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -104408,6 +109423,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -104421,12 +109437,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3729 Instruction:"VPMOVZXWQ Vfv{K}{z},aKq,Wqv" Encoding:"evex m:2 p:1 l:x w:i 0x34 /r"/"RAM" + // Pos:3774 Instruction:"VPMOVZXWQ Vfv{K}{z},aKq,Wqv" Encoding:"evex m:2 p:1 l:x w:i 0x34 /r"/"RAM" { .Instruction = ND_INS_VPMOVZXWQ, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1604, + .Mnemonic = 1639, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -104435,6 +109451,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -104449,12 +109466,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3730 Instruction:"VPMOVZXWQ Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x34 /r"/"RM" + // Pos:3775 Instruction:"VPMOVZXWQ Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x34 /r"/"RM" { .Instruction = ND_INS_VPMOVZXWQ, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1604, + .Mnemonic = 1639, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -104463,6 +109480,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -104476,12 +109494,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3731 Instruction:"VPMOVZXWQ Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x34 /r"/"RM" + // Pos:3776 Instruction:"VPMOVZXWQ Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x34 /r"/"RM" { .Instruction = ND_INS_VPMOVZXWQ, .Category = ND_CAT_AVX2, .IsaSet = ND_SET_AVX2, - .Mnemonic = 1604, + .Mnemonic = 1639, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -104490,6 +109508,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -104503,12 +109522,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3732 Instruction:"VPMULDQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x28 /r"/"RAVM" + // Pos:3777 Instruction:"VPMULDQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x28 /r"/"RAVM" { .Instruction = ND_INS_VPMULDQ, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1605, + .Mnemonic = 1640, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -104517,6 +109536,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -104532,12 +109552,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3733 Instruction:"VPMULDQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x28 /r"/"RVM" + // Pos:3778 Instruction:"VPMULDQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x28 /r"/"RVM" { .Instruction = ND_INS_VPMULDQ, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1605, + .Mnemonic = 1640, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -104546,6 +109566,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -104560,12 +109581,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3734 Instruction:"VPMULHRSW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0x0B /r"/"RAVM" + // Pos:3779 Instruction:"VPMULHRSW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0x0B /r"/"RAVM" { .Instruction = ND_INS_VPMULHRSW, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1606, + .Mnemonic = 1641, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -104574,6 +109595,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4nb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -104589,12 +109611,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3735 Instruction:"VPMULHRSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x0B /r"/"RVM" + // Pos:3780 Instruction:"VPMULHRSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x0B /r"/"RVM" { .Instruction = ND_INS_VPMULHRSW, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1606, + .Mnemonic = 1641, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -104603,6 +109625,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -104617,12 +109640,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3736 Instruction:"VPMULHUW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xE4 /r"/"RAVM" + // Pos:3781 Instruction:"VPMULHUW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xE4 /r"/"RAVM" { .Instruction = ND_INS_VPMULHUW, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1607, + .Mnemonic = 1642, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -104631,6 +109654,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4nb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -104646,12 +109670,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3737 Instruction:"VPMULHUW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE4 /r"/"RVM" + // Pos:3782 Instruction:"VPMULHUW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE4 /r"/"RVM" { .Instruction = ND_INS_VPMULHUW, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1607, + .Mnemonic = 1642, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -104660,6 +109684,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -104674,12 +109699,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3738 Instruction:"VPMULHW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xE5 /r"/"RAVM" + // Pos:3783 Instruction:"VPMULHW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xE5 /r"/"RAVM" { .Instruction = ND_INS_VPMULHW, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1608, + .Mnemonic = 1643, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -104688,6 +109713,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4nb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -104703,12 +109729,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3739 Instruction:"VPMULHW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE5 /r"/"RVM" + // Pos:3784 Instruction:"VPMULHW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE5 /r"/"RVM" { .Instruction = ND_INS_VPMULHW, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1608, + .Mnemonic = 1643, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -104717,6 +109743,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -104731,12 +109758,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3740 Instruction:"VPMULLD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x40 /r"/"RAVM" + // Pos:3785 Instruction:"VPMULLD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x40 /r"/"RAVM" { .Instruction = ND_INS_VPMULLD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1609, + .Mnemonic = 1644, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -104745,6 +109772,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -104760,12 +109788,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3741 Instruction:"VPMULLD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x40 /r"/"RVM" + // Pos:3786 Instruction:"VPMULLD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x40 /r"/"RVM" { .Instruction = ND_INS_VPMULLD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1609, + .Mnemonic = 1644, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -104774,6 +109802,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -104788,12 +109817,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3742 Instruction:"VPMULLQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x40 /r"/"RAVM" + // Pos:3787 Instruction:"VPMULLQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x40 /r"/"RAVM" { .Instruction = ND_INS_VPMULLQ, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 1610, + .Mnemonic = 1645, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -104802,6 +109831,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -104817,12 +109847,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3743 Instruction:"VPMULLW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xD5 /r"/"RAVM" + // Pos:3788 Instruction:"VPMULLW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xD5 /r"/"RAVM" { .Instruction = ND_INS_VPMULLW, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1611, + .Mnemonic = 1646, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -104831,6 +109861,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4nb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -104846,12 +109877,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3744 Instruction:"VPMULLW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD5 /r"/"RVM" + // Pos:3789 Instruction:"VPMULLW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD5 /r"/"RVM" { .Instruction = ND_INS_VPMULLW, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1611, + .Mnemonic = 1646, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -104860,6 +109891,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -104874,12 +109906,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3745 Instruction:"VPMULTISHIFTQB Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x83 /r"/"RAVM" + // Pos:3790 Instruction:"VPMULTISHIFTQB Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x83 /r"/"RAVM" { .Instruction = ND_INS_VPMULTISHIFTQB, .Category = ND_CAT_AVX512VBMI, .IsaSet = ND_SET_AVX512VBMI, - .Mnemonic = 1612, + .Mnemonic = 1647, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -104888,6 +109920,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -104903,12 +109936,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3746 Instruction:"VPMULUDQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0xF4 /r"/"RAVM" + // Pos:3791 Instruction:"VPMULUDQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0xF4 /r"/"RAVM" { .Instruction = ND_INS_VPMULUDQ, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1613, + .Mnemonic = 1648, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -104917,6 +109950,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -104932,12 +109966,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3747 Instruction:"VPMULUDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF4 /r"/"RVM" + // Pos:3792 Instruction:"VPMULUDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF4 /r"/"RVM" { .Instruction = ND_INS_VPMULUDQ, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1613, + .Mnemonic = 1648, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -104946,6 +109980,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -104960,12 +109995,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3748 Instruction:"VPOPCNTB Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x54 /r"/"RAM" + // Pos:3793 Instruction:"VPOPCNTB Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x54 /r"/"RAM" { .Instruction = ND_INS_VPOPCNTB, .Category = ND_CAT_VPOPCNT, .IsaSet = ND_SET_AVX512BITALG, - .Mnemonic = 1614, + .Mnemonic = 1649, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -104974,6 +110009,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -104988,12 +110024,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3749 Instruction:"VPOPCNTD Vfv{K}{z},aKq,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x55 /r"/"RAM" + // Pos:3794 Instruction:"VPOPCNTD Vfv{K}{z},aKq,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x55 /r"/"RAM" { .Instruction = ND_INS_VPOPCNTD, .Category = ND_CAT_VPOPCNT, .IsaSet = ND_SET_AVX512VPOPCNTDQ, - .Mnemonic = 1615, + .Mnemonic = 1650, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -105002,6 +110038,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -105016,12 +110053,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3750 Instruction:"VPOPCNTQ Vfv{K}{z},aKq,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x55 /r"/"RAM" + // Pos:3795 Instruction:"VPOPCNTQ Vfv{K}{z},aKq,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x55 /r"/"RAM" { .Instruction = ND_INS_VPOPCNTQ, .Category = ND_CAT_VPOPCNT, .IsaSet = ND_SET_AVX512VPOPCNTDQ, - .Mnemonic = 1616, + .Mnemonic = 1651, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -105030,6 +110067,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -105044,12 +110082,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3751 Instruction:"VPOPCNTW Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x54 /r"/"RAM" + // Pos:3796 Instruction:"VPOPCNTW Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x54 /r"/"RAM" { .Instruction = ND_INS_VPOPCNTW, .Category = ND_CAT_VPOPCNT, .IsaSet = ND_SET_AVX512BITALG, - .Mnemonic = 1617, + .Mnemonic = 1652, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -105058,6 +110096,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -105072,12 +110111,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3752 Instruction:"VPOR Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEB /r"/"RVM" + // Pos:3797 Instruction:"VPOR Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEB /r"/"RVM" { .Instruction = ND_INS_VPOR, .Category = ND_CAT_LOGICAL, .IsaSet = ND_SET_AVX, - .Mnemonic = 1618, + .Mnemonic = 1653, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -105086,6 +110125,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -105100,12 +110140,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3753 Instruction:"VPORD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0xEB /r"/"RAVM" + // Pos:3798 Instruction:"VPORD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0xEB /r"/"RAVM" { .Instruction = ND_INS_VPORD, .Category = ND_CAT_LOGICAL, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1619, + .Mnemonic = 1654, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -105114,6 +110154,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -105129,12 +110170,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3754 Instruction:"VPORQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0xEB /r"/"RAVM" + // Pos:3799 Instruction:"VPORQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0xEB /r"/"RAVM" { .Instruction = ND_INS_VPORQ, .Category = ND_CAT_LOGICAL, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1620, + .Mnemonic = 1655, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -105143,6 +110184,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -105158,12 +110200,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3755 Instruction:"VPPERM Vx,Hx,Wx,Lx" Encoding:"xop m:8 w:0 0xA3 /r is4"/"RVML" + // Pos:3800 Instruction:"VPPERM Vx,Hx,Wx,Lx" Encoding:"xop m:8 w:0 0xA3 /r is4"/"RVML" { .Instruction = ND_INS_VPPERM, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1621, + .Mnemonic = 1656, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -105172,6 +110214,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -105187,12 +110230,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3756 Instruction:"VPPERM Vx,Hx,Lx,Wx" Encoding:"xop m:8 w:1 0xA3 /r is4"/"RVLM" + // Pos:3801 Instruction:"VPPERM Vx,Hx,Lx,Wx" Encoding:"xop m:8 w:1 0xA3 /r is4"/"RVLM" { .Instruction = ND_INS_VPPERM, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1621, + .Mnemonic = 1656, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -105201,6 +110244,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -105216,12 +110260,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3757 Instruction:"VPROLD Hfv{K}{z},aKq,Wfv|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /1 ib"/"VAMI" + // Pos:3802 Instruction:"VPROLD Hfv{K}{z},aKq,Wfv|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /1 ib"/"VAMI" { .Instruction = ND_INS_VPROLD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1622, + .Mnemonic = 1657, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -105230,6 +110274,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -105245,12 +110290,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3758 Instruction:"VPROLQ Hfv{K}{z},aKq,Wfv|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x72 /1 ib"/"VAMI" + // Pos:3803 Instruction:"VPROLQ Hfv{K}{z},aKq,Wfv|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x72 /1 ib"/"VAMI" { .Instruction = ND_INS_VPROLQ, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1623, + .Mnemonic = 1658, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -105259,6 +110304,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -105274,12 +110320,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3759 Instruction:"VPROLVD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x15 /r"/"RAVM" + // Pos:3804 Instruction:"VPROLVD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x15 /r"/"RAVM" { .Instruction = ND_INS_VPROLVD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1624, + .Mnemonic = 1659, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -105288,6 +110334,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -105303,12 +110350,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3760 Instruction:"VPROLVQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x15 /r"/"RAVM" + // Pos:3805 Instruction:"VPROLVQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x15 /r"/"RAVM" { .Instruction = ND_INS_VPROLVQ, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1625, + .Mnemonic = 1660, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -105317,6 +110364,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -105332,12 +110380,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3761 Instruction:"VPRORD Hfv{K}{z},aKq,Wfv|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /0 ib"/"VAMI" + // Pos:3806 Instruction:"VPRORD Hfv{K}{z},aKq,Wfv|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /0 ib"/"VAMI" { .Instruction = ND_INS_VPRORD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1626, + .Mnemonic = 1661, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -105346,6 +110394,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -105361,12 +110410,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3762 Instruction:"VPRORQ Hfv{K}{z},aKq,Wfv|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x72 /0 ib"/"VAMI" + // Pos:3807 Instruction:"VPRORQ Hfv{K}{z},aKq,Wfv|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x72 /0 ib"/"VAMI" { .Instruction = ND_INS_VPRORQ, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1627, + .Mnemonic = 1662, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -105375,6 +110424,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -105390,12 +110440,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3763 Instruction:"VPRORVD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x14 /r"/"RAVM" + // Pos:3808 Instruction:"VPRORVD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x14 /r"/"RAVM" { .Instruction = ND_INS_VPRORVD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1628, + .Mnemonic = 1663, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -105404,6 +110454,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -105419,12 +110470,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3764 Instruction:"VPRORVQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x14 /r"/"RAVM" + // Pos:3809 Instruction:"VPRORVQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x14 /r"/"RAVM" { .Instruction = ND_INS_VPRORVQ, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1629, + .Mnemonic = 1664, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -105433,6 +110484,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -105448,12 +110500,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3765 Instruction:"VPROTB Vdq,Wdq,Ib" Encoding:"xop m:8 0xC0 /r ib"/"RMI" + // Pos:3810 Instruction:"VPROTB Vdq,Wdq,Ib" Encoding:"xop m:8 0xC0 /r ib"/"RMI" { .Instruction = ND_INS_VPROTB, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1630, + .Mnemonic = 1665, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -105462,6 +110514,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -105476,12 +110529,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3766 Instruction:"VPROTB Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x90 /r"/"RMV" + // Pos:3811 Instruction:"VPROTB Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x90 /r"/"RMV" { .Instruction = ND_INS_VPROTB, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1630, + .Mnemonic = 1665, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -105490,6 +110543,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -105504,12 +110558,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3767 Instruction:"VPROTB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x90 /r"/"RVM" + // Pos:3812 Instruction:"VPROTB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x90 /r"/"RVM" { .Instruction = ND_INS_VPROTB, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1630, + .Mnemonic = 1665, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -105518,6 +110572,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -105532,12 +110587,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3768 Instruction:"VPROTD Vdq,Wdq,Ib" Encoding:"xop m:8 0xC2 /r ib"/"RMI" + // Pos:3813 Instruction:"VPROTD Vdq,Wdq,Ib" Encoding:"xop m:8 0xC2 /r ib"/"RMI" { .Instruction = ND_INS_VPROTD, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1631, + .Mnemonic = 1666, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -105546,6 +110601,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -105560,12 +110616,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3769 Instruction:"VPROTD Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x92 /r"/"RMV" + // Pos:3814 Instruction:"VPROTD Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x92 /r"/"RMV" { .Instruction = ND_INS_VPROTD, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1631, + .Mnemonic = 1666, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -105574,6 +110630,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -105588,12 +110645,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3770 Instruction:"VPROTD Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x92 /r"/"RVM" + // Pos:3815 Instruction:"VPROTD Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x92 /r"/"RVM" { .Instruction = ND_INS_VPROTD, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1631, + .Mnemonic = 1666, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -105602,6 +110659,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -105616,12 +110674,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3771 Instruction:"VPROTQ Vdq,Wdq,Ib" Encoding:"xop m:8 0xC3 /r ib"/"RMI" + // Pos:3816 Instruction:"VPROTQ Vdq,Wdq,Ib" Encoding:"xop m:8 0xC3 /r ib"/"RMI" { .Instruction = ND_INS_VPROTQ, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1632, + .Mnemonic = 1667, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -105630,6 +110688,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -105644,12 +110703,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3772 Instruction:"VPROTQ Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x93 /r"/"RMV" + // Pos:3817 Instruction:"VPROTQ Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x93 /r"/"RMV" { .Instruction = ND_INS_VPROTQ, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1632, + .Mnemonic = 1667, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -105658,6 +110717,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -105672,12 +110732,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3773 Instruction:"VPROTQ Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x93 /r"/"RVM" + // Pos:3818 Instruction:"VPROTQ Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x93 /r"/"RVM" { .Instruction = ND_INS_VPROTQ, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1632, + .Mnemonic = 1667, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -105686,6 +110746,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -105700,12 +110761,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3774 Instruction:"VPROTW Vdq,Wdq,Ib" Encoding:"xop m:8 0xC1 /r ib"/"RMI" + // Pos:3819 Instruction:"VPROTW Vdq,Wdq,Ib" Encoding:"xop m:8 0xC1 /r ib"/"RMI" { .Instruction = ND_INS_VPROTW, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1633, + .Mnemonic = 1668, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -105714,6 +110775,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -105728,12 +110790,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3775 Instruction:"VPROTW Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x91 /r"/"RMV" + // Pos:3820 Instruction:"VPROTW Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x91 /r"/"RMV" { .Instruction = ND_INS_VPROTW, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1633, + .Mnemonic = 1668, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -105742,6 +110804,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -105756,12 +110819,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3776 Instruction:"VPROTW Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x91 /r"/"RVM" + // Pos:3821 Instruction:"VPROTW Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x91 /r"/"RVM" { .Instruction = ND_INS_VPROTW, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1633, + .Mnemonic = 1668, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -105770,6 +110833,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -105784,12 +110848,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3777 Instruction:"VPSADBW Vfv,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xF6 /r"/"RVM" + // Pos:3822 Instruction:"VPSADBW Vfv,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xF6 /r"/"RVM" { .Instruction = ND_INS_VPSADBW, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1634, + .Mnemonic = 1669, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -105798,6 +110862,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NFnb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -105812,12 +110877,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3778 Instruction:"VPSADBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF6 /r"/"RVM" + // Pos:3823 Instruction:"VPSADBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF6 /r"/"RVM" { .Instruction = ND_INS_VPSADBW, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1634, + .Mnemonic = 1669, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -105826,6 +110891,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -105840,12 +110906,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3779 Instruction:"VPSCATTERDD Mvm32n{K},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:0 0xA0 /r:mem vsib"/"MAR" + // Pos:3824 Instruction:"VPSCATTERDD Mvm32n{K},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:0 0xA0 /r:mem vsib"/"MAR" { .Instruction = ND_INS_VPSCATTERDD, .Category = ND_CAT_SCATTER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1635, + .Mnemonic = 1670, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -105854,6 +110920,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E12, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -105868,12 +110935,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3780 Instruction:"VPSCATTERDQ Mvm32h{K},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:1 0xA0 /r:mem vsib"/"MAR" + // Pos:3825 Instruction:"VPSCATTERDQ Mvm32h{K},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:1 0xA0 /r:mem vsib"/"MAR" { .Instruction = ND_INS_VPSCATTERDQ, .Category = ND_CAT_SCATTER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1636, + .Mnemonic = 1671, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -105882,6 +110949,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E12, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -105896,12 +110964,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3781 Instruction:"VPSCATTERQD Mvm64n{K},aKq,Vhv" Encoding:"evex m:2 p:1 l:x w:0 0xA1 /r:mem vsib"/"MAR" + // Pos:3826 Instruction:"VPSCATTERQD Mvm64n{K},aKq,Vhv" Encoding:"evex m:2 p:1 l:x w:0 0xA1 /r:mem vsib"/"MAR" { .Instruction = ND_INS_VPSCATTERQD, .Category = ND_CAT_SCATTER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1637, + .Mnemonic = 1672, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -105910,6 +110978,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E12, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -105924,12 +110993,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3782 Instruction:"VPSCATTERQQ Mvm64n{K},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:1 0xA1 /r:mem vsib"/"MAR" + // Pos:3827 Instruction:"VPSCATTERQQ Mvm64n{K},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:1 0xA1 /r:mem vsib"/"MAR" { .Instruction = ND_INS_VPSCATTERQQ, .Category = ND_CAT_SCATTER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1638, + .Mnemonic = 1673, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -105938,6 +111007,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E12, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -105952,12 +111022,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3783 Instruction:"VPSHAB Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x98 /r"/"RMV" + // Pos:3828 Instruction:"VPSHAB Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x98 /r"/"RMV" { .Instruction = ND_INS_VPSHAB, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1639, + .Mnemonic = 1674, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -105966,6 +111036,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -105980,12 +111051,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3784 Instruction:"VPSHAB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x98 /r"/"RVM" + // Pos:3829 Instruction:"VPSHAB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x98 /r"/"RVM" { .Instruction = ND_INS_VPSHAB, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1639, + .Mnemonic = 1674, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -105994,6 +111065,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -106008,12 +111080,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3785 Instruction:"VPSHAD Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x9A /r"/"RMV" + // Pos:3830 Instruction:"VPSHAD Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x9A /r"/"RMV" { .Instruction = ND_INS_VPSHAD, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1640, + .Mnemonic = 1675, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -106022,6 +111094,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -106036,12 +111109,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3786 Instruction:"VPSHAD Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x9A /r"/"RVM" + // Pos:3831 Instruction:"VPSHAD Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x9A /r"/"RVM" { .Instruction = ND_INS_VPSHAD, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1640, + .Mnemonic = 1675, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -106050,6 +111123,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -106064,12 +111138,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3787 Instruction:"VPSHAQ Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x9B /r"/"RMV" + // Pos:3832 Instruction:"VPSHAQ Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x9B /r"/"RMV" { .Instruction = ND_INS_VPSHAQ, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1641, + .Mnemonic = 1676, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -106078,6 +111152,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -106092,12 +111167,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3788 Instruction:"VPSHAQ Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x9B /r"/"RVM" + // Pos:3833 Instruction:"VPSHAQ Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x9B /r"/"RVM" { .Instruction = ND_INS_VPSHAQ, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1641, + .Mnemonic = 1676, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -106106,6 +111181,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -106120,12 +111196,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3789 Instruction:"VPSHAW Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x99 /r"/"RMV" + // Pos:3834 Instruction:"VPSHAW Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x99 /r"/"RMV" { .Instruction = ND_INS_VPSHAW, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1642, + .Mnemonic = 1677, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -106134,6 +111210,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -106148,12 +111225,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3790 Instruction:"VPSHAW Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x99 /r"/"RVM" + // Pos:3835 Instruction:"VPSHAW Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x99 /r"/"RVM" { .Instruction = ND_INS_VPSHAW, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1642, + .Mnemonic = 1677, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -106162,6 +111239,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -106176,12 +111254,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3791 Instruction:"VPSHLB Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x94 /r"/"RMV" + // Pos:3836 Instruction:"VPSHLB Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x94 /r"/"RMV" { .Instruction = ND_INS_VPSHLB, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1643, + .Mnemonic = 1678, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -106190,6 +111268,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -106204,12 +111283,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3792 Instruction:"VPSHLB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x94 /r"/"RVM" + // Pos:3837 Instruction:"VPSHLB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x94 /r"/"RVM" { .Instruction = ND_INS_VPSHLB, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1643, + .Mnemonic = 1678, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -106218,6 +111297,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -106232,12 +111312,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3793 Instruction:"VPSHLB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x95 /r"/"RVM" + // Pos:3838 Instruction:"VPSHLB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x95 /r"/"RVM" { .Instruction = ND_INS_VPSHLB, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1643, + .Mnemonic = 1678, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -106246,6 +111326,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -106260,12 +111341,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3794 Instruction:"VPSHLB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x96 /r"/"RVM" + // Pos:3839 Instruction:"VPSHLB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x96 /r"/"RVM" { .Instruction = ND_INS_VPSHLB, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1643, + .Mnemonic = 1678, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -106274,6 +111355,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -106288,12 +111370,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3795 Instruction:"VPSHLD Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x96 /r"/"RMV" + // Pos:3840 Instruction:"VPSHLD Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x96 /r"/"RMV" { .Instruction = ND_INS_VPSHLD, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1644, + .Mnemonic = 1679, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -106302,6 +111384,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -106316,12 +111399,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3796 Instruction:"VPSHLDD Vfv{K}{z},aKq,Hfv,Wfv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x71 /r ib"/"RAVMI" + // Pos:3841 Instruction:"VPSHLDD Vfv{K}{z},aKq,Hfv,Wfv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x71 /r ib"/"RAVMI" { .Instruction = ND_INS_VPSHLDD, .Category = ND_CAT_AVX512VBMI, .IsaSet = ND_SET_AVX512VBMI2, - .Mnemonic = 1645, + .Mnemonic = 1680, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -106330,6 +111413,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -106346,12 +111430,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3797 Instruction:"VPSHLDQ Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x71 /r ib"/"RAVMI" + // Pos:3842 Instruction:"VPSHLDQ Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x71 /r ib"/"RAVMI" { .Instruction = ND_INS_VPSHLDQ, .Category = ND_CAT_AVX512VBMI, .IsaSet = ND_SET_AVX512VBMI2, - .Mnemonic = 1646, + .Mnemonic = 1681, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -106360,6 +111444,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -106376,12 +111461,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3798 Instruction:"VPSHLDVD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x71 /r"/"RAVM" + // Pos:3843 Instruction:"VPSHLDVD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x71 /r"/"RAVM" { .Instruction = ND_INS_VPSHLDVD, .Category = ND_CAT_AVX512VBMI, .IsaSet = ND_SET_AVX512VBMI2, - .Mnemonic = 1647, + .Mnemonic = 1682, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -106390,6 +111475,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -106405,12 +111491,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3799 Instruction:"VPSHLDVQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x71 /r"/"RAVM" + // Pos:3844 Instruction:"VPSHLDVQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x71 /r"/"RAVM" { .Instruction = ND_INS_VPSHLDVQ, .Category = ND_CAT_AVX512VBMI, .IsaSet = ND_SET_AVX512VBMI2, - .Mnemonic = 1648, + .Mnemonic = 1683, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -106419,6 +111505,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -106434,12 +111521,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3800 Instruction:"VPSHLDVW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x70 /r"/"RAVM" + // Pos:3845 Instruction:"VPSHLDVW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x70 /r"/"RAVM" { .Instruction = ND_INS_VPSHLDVW, .Category = ND_CAT_AVX512VBMI, .IsaSet = ND_SET_AVX512VBMI2, - .Mnemonic = 1649, + .Mnemonic = 1684, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -106448,6 +111535,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -106463,12 +111551,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3801 Instruction:"VPSHLDW Vfv{K}{z},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x70 /r ib"/"RAVMI" + // Pos:3846 Instruction:"VPSHLDW Vfv{K}{z},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x70 /r ib"/"RAVMI" { .Instruction = ND_INS_VPSHLDW, .Category = ND_CAT_AVX512VBMI, .IsaSet = ND_SET_AVX512VBMI2, - .Mnemonic = 1650, + .Mnemonic = 1685, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -106477,6 +111565,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -106493,12 +111582,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3802 Instruction:"VPSHLQ Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x97 /r"/"RMV" + // Pos:3847 Instruction:"VPSHLQ Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x97 /r"/"RMV" { .Instruction = ND_INS_VPSHLQ, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1651, + .Mnemonic = 1686, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -106507,6 +111596,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -106521,12 +111611,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3803 Instruction:"VPSHLQ Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x97 /r"/"RVM" + // Pos:3848 Instruction:"VPSHLQ Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x97 /r"/"RVM" { .Instruction = ND_INS_VPSHLQ, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1651, + .Mnemonic = 1686, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -106535,6 +111625,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -106549,12 +111640,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3804 Instruction:"VPSHLW Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x95 /r"/"RMV" + // Pos:3849 Instruction:"VPSHLW Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x95 /r"/"RMV" { .Instruction = ND_INS_VPSHLW, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1652, + .Mnemonic = 1687, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -106563,6 +111654,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -106577,12 +111669,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3805 Instruction:"VPSHRDD Vfv{K}{z},aKq,Hfv,Wfv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x73 /r ib"/"RAVMI" + // Pos:3850 Instruction:"VPSHRDD Vfv{K}{z},aKq,Hfv,Wfv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x73 /r ib"/"RAVMI" { .Instruction = ND_INS_VPSHRDD, .Category = ND_CAT_AVX512VBMI, .IsaSet = ND_SET_AVX512VBMI2, - .Mnemonic = 1653, + .Mnemonic = 1688, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -106591,6 +111683,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -106607,12 +111700,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3806 Instruction:"VPSHRDQ Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x73 /r ib"/"RAVMI" + // Pos:3851 Instruction:"VPSHRDQ Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x73 /r ib"/"RAVMI" { .Instruction = ND_INS_VPSHRDQ, .Category = ND_CAT_AVX512VBMI, .IsaSet = ND_SET_AVX512VBMI2, - .Mnemonic = 1654, + .Mnemonic = 1689, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -106621,6 +111714,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -106637,12 +111731,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3807 Instruction:"VPSHRDVD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x73 /r"/"RAVM" + // Pos:3852 Instruction:"VPSHRDVD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x73 /r"/"RAVM" { .Instruction = ND_INS_VPSHRDVD, .Category = ND_CAT_AVX512VBMI, .IsaSet = ND_SET_AVX512VBMI2, - .Mnemonic = 1655, + .Mnemonic = 1690, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -106651,6 +111745,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -106666,12 +111761,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3808 Instruction:"VPSHRDVQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x73 /r"/"RAVM" + // Pos:3853 Instruction:"VPSHRDVQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x73 /r"/"RAVM" { .Instruction = ND_INS_VPSHRDVQ, .Category = ND_CAT_AVX512VBMI, .IsaSet = ND_SET_AVX512VBMI2, - .Mnemonic = 1656, + .Mnemonic = 1691, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -106680,6 +111775,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -106695,12 +111791,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3809 Instruction:"VPSHRDVW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x72 /r"/"RAVM" + // Pos:3854 Instruction:"VPSHRDVW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x72 /r"/"RAVM" { .Instruction = ND_INS_VPSHRDVW, .Category = ND_CAT_AVX512VBMI, .IsaSet = ND_SET_AVX512VBMI2, - .Mnemonic = 1657, + .Mnemonic = 1692, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -106709,6 +111805,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -106724,12 +111821,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3810 Instruction:"VPSHRDW Vfv{K}{z},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x72 /r ib"/"RAVMI" + // Pos:3855 Instruction:"VPSHRDW Vfv{K}{z},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x72 /r ib"/"RAVMI" { .Instruction = ND_INS_VPSHRDW, .Category = ND_CAT_AVX512VBMI, .IsaSet = ND_SET_AVX512VBMI2, - .Mnemonic = 1658, + .Mnemonic = 1693, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -106738,6 +111835,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -106754,12 +111852,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3811 Instruction:"VPSHUFB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0x00 /r"/"RAVM" + // Pos:3856 Instruction:"VPSHUFB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0x00 /r"/"RAVM" { .Instruction = ND_INS_VPSHUFB, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1659, + .Mnemonic = 1694, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -106768,6 +111866,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NFnb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -106783,12 +111882,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3812 Instruction:"VPSHUFB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x00 /r"/"RVM" + // Pos:3857 Instruction:"VPSHUFB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x00 /r"/"RVM" { .Instruction = ND_INS_VPSHUFB, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1659, + .Mnemonic = 1694, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -106797,6 +111896,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -106811,12 +111911,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3813 Instruction:"VPSHUFBITQMB rK{K},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x8F /r"/"RAVM" + // Pos:3858 Instruction:"VPSHUFBITQMB rK{K},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x8F /r"/"RAVM" { .Instruction = ND_INS_VPSHUFBITQMB, .Category = ND_CAT_AVX512VBMI, .IsaSet = ND_SET_AVX512BITALG, - .Mnemonic = 1660, + .Mnemonic = 1695, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -106825,6 +111925,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -106840,12 +111941,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3814 Instruction:"VPSHUFD Vfv{K}{z},aKq,Wfv|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x70 /r ib"/"RAMI" + // Pos:3859 Instruction:"VPSHUFD Vfv{K}{z},aKq,Wfv|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x70 /r ib"/"RAMI" { .Instruction = ND_INS_VPSHUFD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1661, + .Mnemonic = 1696, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -106854,6 +111955,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -106869,12 +111971,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3815 Instruction:"VPSHUFD Vx,Wx,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x70 /r ib"/"RMI" + // Pos:3860 Instruction:"VPSHUFD Vx,Wx,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x70 /r ib"/"RMI" { .Instruction = ND_INS_VPSHUFD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1661, + .Mnemonic = 1696, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -106883,6 +111985,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -106897,12 +112000,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3816 Instruction:"VPSHUFHW Vfv{K}{z},aKq,Wfv,Ib" Encoding:"evex m:1 p:2 l:x w:i 0x70 /r ib"/"RAMI" + // Pos:3861 Instruction:"VPSHUFHW Vfv{K}{z},aKq,Wfv,Ib" Encoding:"evex m:1 p:2 l:x w:i 0x70 /r ib"/"RAMI" { .Instruction = ND_INS_VPSHUFHW, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1662, + .Mnemonic = 1697, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -106911,6 +112014,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NFnb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -106926,12 +112030,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3817 Instruction:"VPSHUFHW Vx,Wx,Ib" Encoding:"vex m:1 p:2 l:x w:i 0x70 /r ib"/"RMI" + // Pos:3862 Instruction:"VPSHUFHW Vx,Wx,Ib" Encoding:"vex m:1 p:2 l:x w:i 0x70 /r ib"/"RMI" { .Instruction = ND_INS_VPSHUFHW, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1662, + .Mnemonic = 1697, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -106940,6 +112044,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -106954,12 +112059,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3818 Instruction:"VPSHUFLW Vfv{K}{z},aKq,Wfv,Ib" Encoding:"evex m:1 p:3 l:x w:i 0x70 /r ib"/"RAMI" + // Pos:3863 Instruction:"VPSHUFLW Vfv{K}{z},aKq,Wfv,Ib" Encoding:"evex m:1 p:3 l:x w:i 0x70 /r ib"/"RAMI" { .Instruction = ND_INS_VPSHUFLW, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1663, + .Mnemonic = 1698, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -106968,6 +112073,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NFnb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -106983,12 +112089,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3819 Instruction:"VPSHUFLW Vx,Wx,Ib" Encoding:"vex m:1 p:3 l:x w:i 0x70 /r ib"/"RMI" + // Pos:3864 Instruction:"VPSHUFLW Vx,Wx,Ib" Encoding:"vex m:1 p:3 l:x w:i 0x70 /r ib"/"RMI" { .Instruction = ND_INS_VPSHUFLW, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1663, + .Mnemonic = 1698, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -106997,6 +112103,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -107011,12 +112118,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3820 Instruction:"VPSIGNB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x08 /r"/"RVM" + // Pos:3865 Instruction:"VPSIGNB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x08 /r"/"RVM" { .Instruction = ND_INS_VPSIGNB, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1664, + .Mnemonic = 1699, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -107025,6 +112132,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -107039,12 +112147,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3821 Instruction:"VPSIGND Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x0A /r"/"RVM" + // Pos:3866 Instruction:"VPSIGND Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x0A /r"/"RVM" { .Instruction = ND_INS_VPSIGND, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1665, + .Mnemonic = 1700, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -107053,6 +112161,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -107067,12 +112176,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3822 Instruction:"VPSIGNW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x09 /r"/"RVM" + // Pos:3867 Instruction:"VPSIGNW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x09 /r"/"RVM" { .Instruction = ND_INS_VPSIGNW, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1666, + .Mnemonic = 1701, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -107081,6 +112190,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -107095,12 +112205,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3823 Instruction:"VPSLLD Hfv{K}{z},aKq,Wfv|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /6 ib"/"VAMI" + // Pos:3868 Instruction:"VPSLLD Hfv{K}{z},aKq,Wfv|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /6 ib"/"VAMI" { .Instruction = ND_INS_VPSLLD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1667, + .Mnemonic = 1702, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -107109,6 +112219,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -107124,12 +112235,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3824 Instruction:"VPSLLD Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:0 0xF2 /r"/"RAVM" + // Pos:3869 Instruction:"VPSLLD Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:0 0xF2 /r"/"RAVM" { .Instruction = ND_INS_VPSLLD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1667, + .Mnemonic = 1702, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -107138,6 +112249,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NFnb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -107153,12 +112265,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3825 Instruction:"VPSLLD Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x72 /6:reg ib"/"VMI" + // Pos:3870 Instruction:"VPSLLD Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x72 /6:reg ib"/"VMI" { .Instruction = ND_INS_VPSLLD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1667, + .Mnemonic = 1702, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -107167,6 +112279,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_7, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -107181,12 +112294,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3826 Instruction:"VPSLLD Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xF2 /r"/"RVM" + // Pos:3871 Instruction:"VPSLLD Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xF2 /r"/"RVM" { .Instruction = ND_INS_VPSLLD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1667, + .Mnemonic = 1702, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -107195,6 +112308,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -107209,12 +112323,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3827 Instruction:"VPSLLDQ Hfv,Wfv,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x73 /7 ib"/"VMI" + // Pos:3872 Instruction:"VPSLLDQ Hfv,Wfv,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x73 /7 ib"/"VMI" { .Instruction = ND_INS_VPSLLDQ, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1668, + .Mnemonic = 1703, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -107223,6 +112337,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NFnb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -107237,12 +112352,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3828 Instruction:"VPSLLDQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /7:reg ib"/"VMI" + // Pos:3873 Instruction:"VPSLLDQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /7:reg ib"/"VMI" { .Instruction = ND_INS_VPSLLDQ, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1668, + .Mnemonic = 1703, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -107251,6 +112366,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_7, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -107265,12 +112381,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3829 Instruction:"VPSLLQ Hfv{K}{z},aKq,Wfv|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x73 /6 ib"/"VAMI" + // Pos:3874 Instruction:"VPSLLQ Hfv{K}{z},aKq,Wfv|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x73 /6 ib"/"VAMI" { .Instruction = ND_INS_VPSLLQ, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1669, + .Mnemonic = 1704, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -107279,6 +112395,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -107294,12 +112411,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3830 Instruction:"VPSLLQ Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:1 0xF3 /r"/"RAVM" + // Pos:3875 Instruction:"VPSLLQ Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:1 0xF3 /r"/"RAVM" { .Instruction = ND_INS_VPSLLQ, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1669, + .Mnemonic = 1704, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -107308,6 +112425,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NFnb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -107323,12 +112441,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3831 Instruction:"VPSLLQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /6:reg ib"/"VMI" + // Pos:3876 Instruction:"VPSLLQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /6:reg ib"/"VMI" { .Instruction = ND_INS_VPSLLQ, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1669, + .Mnemonic = 1704, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -107337,6 +112455,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_7, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -107351,12 +112470,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3832 Instruction:"VPSLLQ Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xF3 /r"/"RVM" + // Pos:3877 Instruction:"VPSLLQ Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xF3 /r"/"RVM" { .Instruction = ND_INS_VPSLLQ, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1669, + .Mnemonic = 1704, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -107365,6 +112484,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -107379,12 +112499,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3833 Instruction:"VPSLLVD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x47 /r"/"RAVM" + // Pos:3878 Instruction:"VPSLLVD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x47 /r"/"RAVM" { .Instruction = ND_INS_VPSLLVD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1670, + .Mnemonic = 1705, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -107393,6 +112513,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -107408,12 +112529,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3834 Instruction:"VPSLLVD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x47 /r"/"RVM" + // Pos:3879 Instruction:"VPSLLVD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x47 /r"/"RVM" { .Instruction = ND_INS_VPSLLVD, .Category = ND_CAT_AVX2, .IsaSet = ND_SET_AVX2, - .Mnemonic = 1670, + .Mnemonic = 1705, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -107422,6 +112543,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -107436,12 +112558,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3835 Instruction:"VPSLLVQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x47 /r"/"RAVM" + // Pos:3880 Instruction:"VPSLLVQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x47 /r"/"RAVM" { .Instruction = ND_INS_VPSLLVQ, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1671, + .Mnemonic = 1706, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -107450,6 +112572,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -107465,12 +112588,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3836 Instruction:"VPSLLVQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x47 /r"/"RVM" + // Pos:3881 Instruction:"VPSLLVQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x47 /r"/"RVM" { .Instruction = ND_INS_VPSLLVQ, .Category = ND_CAT_AVX2, .IsaSet = ND_SET_AVX2, - .Mnemonic = 1671, + .Mnemonic = 1706, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -107479,6 +112602,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -107493,12 +112617,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3837 Instruction:"VPSLLVW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x12 /r"/"RAVM" + // Pos:3882 Instruction:"VPSLLVW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x12 /r"/"RAVM" { .Instruction = ND_INS_VPSLLVW, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1672, + .Mnemonic = 1707, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -107507,6 +112631,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4nb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -107522,12 +112647,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3838 Instruction:"VPSLLW Hfv{K}{z},aKq,Wfv,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x71 /6 ib"/"VAMI" + // Pos:3883 Instruction:"VPSLLW Hfv{K}{z},aKq,Wfv,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x71 /6 ib"/"VAMI" { .Instruction = ND_INS_VPSLLW, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1673, + .Mnemonic = 1708, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -107536,6 +112661,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4nb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -107551,12 +112677,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3839 Instruction:"VPSLLW Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:i 0xF1 /r"/"RAVM" + // Pos:3884 Instruction:"VPSLLW Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:i 0xF1 /r"/"RAVM" { .Instruction = ND_INS_VPSLLW, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1673, + .Mnemonic = 1708, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -107565,6 +112691,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4nb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -107580,12 +112707,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3840 Instruction:"VPSLLW Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x71 /6:reg ib"/"VMI" + // Pos:3885 Instruction:"VPSLLW Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x71 /6:reg ib"/"VMI" { .Instruction = ND_INS_VPSLLW, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1673, + .Mnemonic = 1708, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -107594,6 +112721,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_7, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -107608,12 +112736,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3841 Instruction:"VPSLLW Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xF1 /r"/"RVM" + // Pos:3886 Instruction:"VPSLLW Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xF1 /r"/"RVM" { .Instruction = ND_INS_VPSLLW, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1673, + .Mnemonic = 1708, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -107622,6 +112750,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -107636,12 +112765,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3842 Instruction:"VPSRAD Hfv{K}{z},aKq,Wfv|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /4 ib"/"VAMI" + // Pos:3887 Instruction:"VPSRAD Hfv{K}{z},aKq,Wfv|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /4 ib"/"VAMI" { .Instruction = ND_INS_VPSRAD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1674, + .Mnemonic = 1709, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -107650,6 +112779,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -107665,12 +112795,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3843 Instruction:"VPSRAD Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:0 0xE2 /r"/"RAVM" + // Pos:3888 Instruction:"VPSRAD Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:0 0xE2 /r"/"RAVM" { .Instruction = ND_INS_VPSRAD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1674, + .Mnemonic = 1709, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -107679,6 +112809,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NFnb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -107694,12 +112825,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3844 Instruction:"VPSRAD Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x72 /4:reg ib"/"VMI" + // Pos:3889 Instruction:"VPSRAD Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x72 /4:reg ib"/"VMI" { .Instruction = ND_INS_VPSRAD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1674, + .Mnemonic = 1709, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -107708,6 +112839,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_7, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -107722,12 +112854,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3845 Instruction:"VPSRAD Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xE2 /r"/"RVM" + // Pos:3890 Instruction:"VPSRAD Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xE2 /r"/"RVM" { .Instruction = ND_INS_VPSRAD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1674, + .Mnemonic = 1709, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -107736,6 +112868,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -107750,12 +112883,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3846 Instruction:"VPSRAQ Hfv{K}{z},aKq,Wfv|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x72 /4 ib"/"VAMI" + // Pos:3891 Instruction:"VPSRAQ Hfv{K}{z},aKq,Wfv|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x72 /4 ib"/"VAMI" { .Instruction = ND_INS_VPSRAQ, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1675, + .Mnemonic = 1710, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -107764,6 +112897,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -107779,12 +112913,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3847 Instruction:"VPSRAQ Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:1 0xE2 /r"/"RAVM" + // Pos:3892 Instruction:"VPSRAQ Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:1 0xE2 /r"/"RAVM" { .Instruction = ND_INS_VPSRAQ, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1675, + .Mnemonic = 1710, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -107793,6 +112927,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NFnb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -107808,12 +112943,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3848 Instruction:"VPSRAVD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x46 /r"/"RAVM" + // Pos:3893 Instruction:"VPSRAVD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x46 /r"/"RAVM" { .Instruction = ND_INS_VPSRAVD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1676, + .Mnemonic = 1711, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -107822,6 +112957,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -107837,12 +112973,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3849 Instruction:"VPSRAVD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x46 /r"/"RVM" + // Pos:3894 Instruction:"VPSRAVD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x46 /r"/"RVM" { .Instruction = ND_INS_VPSRAVD, .Category = ND_CAT_AVX2, .IsaSet = ND_SET_AVX2, - .Mnemonic = 1676, + .Mnemonic = 1711, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -107851,6 +112987,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -107865,12 +113002,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3850 Instruction:"VPSRAVQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x46 /r"/"RAVM" + // Pos:3895 Instruction:"VPSRAVQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x46 /r"/"RAVM" { .Instruction = ND_INS_VPSRAVQ, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1677, + .Mnemonic = 1712, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -107879,6 +113016,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -107894,12 +113032,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3851 Instruction:"VPSRAVW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x11 /r"/"RAVM" + // Pos:3896 Instruction:"VPSRAVW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x11 /r"/"RAVM" { .Instruction = ND_INS_VPSRAVW, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1678, + .Mnemonic = 1713, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -107908,6 +113046,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -107923,12 +113062,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3852 Instruction:"VPSRAW Hfv{K}{z},aKq,Wfv,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x71 /4 ib"/"VAMI" + // Pos:3897 Instruction:"VPSRAW Hfv{K}{z},aKq,Wfv,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x71 /4 ib"/"VAMI" { .Instruction = ND_INS_VPSRAW, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1679, + .Mnemonic = 1714, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -107937,6 +113076,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4nb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -107952,12 +113092,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3853 Instruction:"VPSRAW Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:i 0xE1 /r"/"RAVM" + // Pos:3898 Instruction:"VPSRAW Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:i 0xE1 /r"/"RAVM" { .Instruction = ND_INS_VPSRAW, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1679, + .Mnemonic = 1714, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -107966,6 +113106,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4nb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -107981,12 +113122,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3854 Instruction:"VPSRAW Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x71 /4:reg ib"/"VMI" + // Pos:3899 Instruction:"VPSRAW Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x71 /4:reg ib"/"VMI" { .Instruction = ND_INS_VPSRAW, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1679, + .Mnemonic = 1714, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -107995,6 +113136,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_7, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -108009,12 +113151,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3855 Instruction:"VPSRAW Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xE1 /r"/"RVM" + // Pos:3900 Instruction:"VPSRAW Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xE1 /r"/"RVM" { .Instruction = ND_INS_VPSRAW, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1679, + .Mnemonic = 1714, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -108023,6 +113165,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -108037,12 +113180,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3856 Instruction:"VPSRLD Hfv{K}{z},aKq,Wfv|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /2 ib"/"VAMI" + // Pos:3901 Instruction:"VPSRLD Hfv{K}{z},aKq,Wfv|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /2 ib"/"VAMI" { .Instruction = ND_INS_VPSRLD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1680, + .Mnemonic = 1715, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -108051,6 +113194,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -108066,12 +113210,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3857 Instruction:"VPSRLD Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:0 0xD2 /r"/"RAVM" + // Pos:3902 Instruction:"VPSRLD Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:0 0xD2 /r"/"RAVM" { .Instruction = ND_INS_VPSRLD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1680, + .Mnemonic = 1715, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -108080,6 +113224,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NFnb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -108095,12 +113240,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3858 Instruction:"VPSRLD Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x72 /2:reg ib"/"VMI" + // Pos:3903 Instruction:"VPSRLD Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x72 /2:reg ib"/"VMI" { .Instruction = ND_INS_VPSRLD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1680, + .Mnemonic = 1715, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -108109,6 +113254,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_7, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -108123,12 +113269,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3859 Instruction:"VPSRLD Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xD2 /r"/"RVM" + // Pos:3904 Instruction:"VPSRLD Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xD2 /r"/"RVM" { .Instruction = ND_INS_VPSRLD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1680, + .Mnemonic = 1715, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -108137,6 +113283,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -108151,12 +113298,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3860 Instruction:"VPSRLDQ Hfv,Wfv,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x73 /3 ib"/"VMI" + // Pos:3905 Instruction:"VPSRLDQ Hfv,Wfv,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x73 /3 ib"/"VMI" { .Instruction = ND_INS_VPSRLDQ, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1681, + .Mnemonic = 1716, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -108165,6 +113312,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NFnb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -108179,12 +113327,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3861 Instruction:"VPSRLDQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /3:reg ib"/"VMI" + // Pos:3906 Instruction:"VPSRLDQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /3:reg ib"/"VMI" { .Instruction = ND_INS_VPSRLDQ, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1681, + .Mnemonic = 1716, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -108193,6 +113341,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_7, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -108207,12 +113356,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3862 Instruction:"VPSRLQ Hfv{K}{z},aKq,Wfv|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x73 /2 ib"/"VAMI" + // Pos:3907 Instruction:"VPSRLQ Hfv{K}{z},aKq,Wfv|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x73 /2 ib"/"VAMI" { .Instruction = ND_INS_VPSRLQ, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1682, + .Mnemonic = 1717, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -108221,6 +113370,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -108236,12 +113386,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3863 Instruction:"VPSRLQ Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:1 0xD3 /r"/"RAVM" + // Pos:3908 Instruction:"VPSRLQ Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:1 0xD3 /r"/"RAVM" { .Instruction = ND_INS_VPSRLQ, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1682, + .Mnemonic = 1717, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -108250,6 +113400,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NFnb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -108265,12 +113416,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3864 Instruction:"VPSRLQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /2:reg ib"/"VMI" + // Pos:3909 Instruction:"VPSRLQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /2:reg ib"/"VMI" { .Instruction = ND_INS_VPSRLQ, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1682, + .Mnemonic = 1717, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -108279,6 +113430,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_7, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -108293,12 +113445,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3865 Instruction:"VPSRLQ Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xD3 /r"/"RVM" + // Pos:3910 Instruction:"VPSRLQ Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xD3 /r"/"RVM" { .Instruction = ND_INS_VPSRLQ, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1682, + .Mnemonic = 1717, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -108307,6 +113459,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -108321,12 +113474,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3866 Instruction:"VPSRLVD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x45 /r"/"RAVM" + // Pos:3911 Instruction:"VPSRLVD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x45 /r"/"RAVM" { .Instruction = ND_INS_VPSRLVD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1683, + .Mnemonic = 1718, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -108335,6 +113488,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -108350,12 +113504,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3867 Instruction:"VPSRLVD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x45 /r"/"RVM" + // Pos:3912 Instruction:"VPSRLVD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x45 /r"/"RVM" { .Instruction = ND_INS_VPSRLVD, .Category = ND_CAT_AVX2, .IsaSet = ND_SET_AVX2, - .Mnemonic = 1683, + .Mnemonic = 1718, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -108364,6 +113518,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -108378,12 +113533,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3868 Instruction:"VPSRLVQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x45 /r"/"RAVM" + // Pos:3913 Instruction:"VPSRLVQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x45 /r"/"RAVM" { .Instruction = ND_INS_VPSRLVQ, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1684, + .Mnemonic = 1719, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -108392,6 +113547,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -108407,12 +113563,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3869 Instruction:"VPSRLVQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x45 /r"/"RVM" + // Pos:3914 Instruction:"VPSRLVQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x45 /r"/"RVM" { .Instruction = ND_INS_VPSRLVQ, .Category = ND_CAT_AVX2, .IsaSet = ND_SET_AVX2, - .Mnemonic = 1684, + .Mnemonic = 1719, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -108421,6 +113577,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -108435,12 +113592,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3870 Instruction:"VPSRLVW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x10 /r"/"RAVM" + // Pos:3915 Instruction:"VPSRLVW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x10 /r"/"RAVM" { .Instruction = ND_INS_VPSRLVW, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1685, + .Mnemonic = 1720, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -108449,6 +113606,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4nb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -108464,12 +113622,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3871 Instruction:"VPSRLW Hfv{K}{z},aKq,Wfv,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x71 /2 ib"/"VAMI" + // Pos:3916 Instruction:"VPSRLW Hfv{K}{z},aKq,Wfv,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x71 /2 ib"/"VAMI" { .Instruction = ND_INS_VPSRLW, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1686, + .Mnemonic = 1721, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -108478,6 +113636,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4nb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -108493,12 +113652,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3872 Instruction:"VPSRLW Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:i 0xD1 /r"/"RAVM" + // Pos:3917 Instruction:"VPSRLW Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:i 0xD1 /r"/"RAVM" { .Instruction = ND_INS_VPSRLW, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1686, + .Mnemonic = 1721, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -108507,6 +113666,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4nb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -108522,12 +113682,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3873 Instruction:"VPSRLW Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x71 /2:reg ib"/"VMI" + // Pos:3918 Instruction:"VPSRLW Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x71 /2:reg ib"/"VMI" { .Instruction = ND_INS_VPSRLW, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1686, + .Mnemonic = 1721, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -108536,6 +113696,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_7, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -108550,12 +113711,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3874 Instruction:"VPSRLW Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xD1 /r"/"RVM" + // Pos:3919 Instruction:"VPSRLW Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xD1 /r"/"RVM" { .Instruction = ND_INS_VPSRLW, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1686, + .Mnemonic = 1721, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -108564,6 +113725,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -108578,12 +113740,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3875 Instruction:"VPSUBB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xF8 /r"/"RAVM" + // Pos:3920 Instruction:"VPSUBB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xF8 /r"/"RAVM" { .Instruction = ND_INS_VPSUBB, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1687, + .Mnemonic = 1722, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -108592,6 +113754,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4nb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -108607,12 +113770,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3876 Instruction:"VPSUBB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF8 /r"/"RVM" + // Pos:3921 Instruction:"VPSUBB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF8 /r"/"RVM" { .Instruction = ND_INS_VPSUBB, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1687, + .Mnemonic = 1722, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -108621,6 +113784,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -108635,12 +113799,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3877 Instruction:"VPSUBD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0xFA /r"/"RAVM" + // Pos:3922 Instruction:"VPSUBD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0xFA /r"/"RAVM" { .Instruction = ND_INS_VPSUBD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1688, + .Mnemonic = 1723, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -108649,6 +113813,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -108664,12 +113829,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3878 Instruction:"VPSUBD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFA /r"/"RVM" + // Pos:3923 Instruction:"VPSUBD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFA /r"/"RVM" { .Instruction = ND_INS_VPSUBD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1688, + .Mnemonic = 1723, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -108678,6 +113843,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -108692,12 +113858,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3879 Instruction:"VPSUBQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0xFB /r"/"RAVM" + // Pos:3924 Instruction:"VPSUBQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0xFB /r"/"RAVM" { .Instruction = ND_INS_VPSUBQ, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1689, + .Mnemonic = 1724, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -108706,6 +113872,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -108721,12 +113888,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3880 Instruction:"VPSUBQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFB /r"/"RVM" + // Pos:3925 Instruction:"VPSUBQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFB /r"/"RVM" { .Instruction = ND_INS_VPSUBQ, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1689, + .Mnemonic = 1724, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -108735,6 +113902,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -108749,12 +113917,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3881 Instruction:"VPSUBSB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xE8 /r"/"RAVM" + // Pos:3926 Instruction:"VPSUBSB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xE8 /r"/"RAVM" { .Instruction = ND_INS_VPSUBSB, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1690, + .Mnemonic = 1725, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -108763,6 +113931,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4nb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -108778,12 +113947,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3882 Instruction:"VPSUBSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE8 /r"/"RVM" + // Pos:3927 Instruction:"VPSUBSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE8 /r"/"RVM" { .Instruction = ND_INS_VPSUBSB, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1690, + .Mnemonic = 1725, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -108792,6 +113961,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -108806,12 +113976,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3883 Instruction:"VPSUBSW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xE9 /r"/"RAVM" + // Pos:3928 Instruction:"VPSUBSW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xE9 /r"/"RAVM" { .Instruction = ND_INS_VPSUBSW, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1691, + .Mnemonic = 1726, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -108820,6 +113990,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4nb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -108835,12 +114006,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3884 Instruction:"VPSUBSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE9 /r"/"RVM" + // Pos:3929 Instruction:"VPSUBSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE9 /r"/"RVM" { .Instruction = ND_INS_VPSUBSW, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1691, + .Mnemonic = 1726, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -108849,6 +114020,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -108863,12 +114035,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3885 Instruction:"VPSUBUSB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xD8 /r"/"RAVM" + // Pos:3930 Instruction:"VPSUBUSB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xD8 /r"/"RAVM" { .Instruction = ND_INS_VPSUBUSB, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1692, + .Mnemonic = 1727, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -108877,6 +114049,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -108892,12 +114065,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3886 Instruction:"VPSUBUSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD8 /r"/"RVM" + // Pos:3931 Instruction:"VPSUBUSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD8 /r"/"RVM" { .Instruction = ND_INS_VPSUBUSB, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1692, + .Mnemonic = 1727, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -108906,6 +114079,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -108920,12 +114094,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3887 Instruction:"VPSUBUSW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xD9 /r"/"RAVM" + // Pos:3932 Instruction:"VPSUBUSW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xD9 /r"/"RAVM" { .Instruction = ND_INS_VPSUBUSW, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1693, + .Mnemonic = 1728, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -108934,6 +114108,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -108949,12 +114124,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3888 Instruction:"VPSUBUSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD9 /r"/"RVM" + // Pos:3933 Instruction:"VPSUBUSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD9 /r"/"RVM" { .Instruction = ND_INS_VPSUBUSW, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1693, + .Mnemonic = 1728, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -108963,6 +114138,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -108977,12 +114153,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3889 Instruction:"VPSUBW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xF9 /r"/"RAVM" + // Pos:3934 Instruction:"VPSUBW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xF9 /r"/"RAVM" { .Instruction = ND_INS_VPSUBW, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1694, + .Mnemonic = 1729, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -108991,6 +114167,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4nb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -109006,12 +114183,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3890 Instruction:"VPSUBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF9 /r"/"RVM" + // Pos:3935 Instruction:"VPSUBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF9 /r"/"RVM" { .Instruction = ND_INS_VPSUBW, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1694, + .Mnemonic = 1729, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -109020,6 +114197,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -109034,12 +114212,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3891 Instruction:"VPTERNLOGD Vfv{K}{z},aKq,Hfv,Wfv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x25 /r ib"/"RAVMI" + // Pos:3936 Instruction:"VPTERNLOGD Vfv{K}{z},aKq,Hfv,Wfv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x25 /r ib"/"RAVMI" { .Instruction = ND_INS_VPTERNLOGD, .Category = ND_CAT_LOGICAL, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1695, + .Mnemonic = 1730, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -109048,6 +114226,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -109064,12 +114243,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3892 Instruction:"VPTERNLOGQ Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x25 /r ib"/"RAVMI" + // Pos:3937 Instruction:"VPTERNLOGQ Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x25 /r ib"/"RAVMI" { .Instruction = ND_INS_VPTERNLOGQ, .Category = ND_CAT_LOGICAL, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1696, + .Mnemonic = 1731, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -109078,6 +114257,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -109094,12 +114274,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3893 Instruction:"VPTEST Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x17 /r"/"RM" + // Pos:3938 Instruction:"VPTEST Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x17 /r"/"RM" { .Instruction = ND_INS_VPTEST, .Category = ND_CAT_LOGICAL, .IsaSet = ND_SET_AVX, - .Mnemonic = 1697, + .Mnemonic = 1732, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -109108,6 +114288,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .SetFlags = 0, @@ -109122,12 +114303,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3894 Instruction:"VPTESTMB rKq{K},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x26 /r"/"RAVM" + // Pos:3939 Instruction:"VPTESTMB rKq{K},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x26 /r"/"RAVM" { .Instruction = ND_INS_VPTESTMB, .Category = ND_CAT_LOGICAL, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1698, + .Mnemonic = 1733, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -109136,6 +114317,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4nb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -109151,12 +114333,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3895 Instruction:"VPTESTMD rKq{K},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x27 /r"/"RAVM" + // Pos:3940 Instruction:"VPTESTMD rKq{K},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x27 /r"/"RAVM" { .Instruction = ND_INS_VPTESTMD, .Category = ND_CAT_LOGICAL, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1699, + .Mnemonic = 1734, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_BROADCAST, @@ -109165,6 +114347,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -109180,12 +114363,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3896 Instruction:"VPTESTMQ rKq{K},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x27 /r"/"RAVM" + // Pos:3941 Instruction:"VPTESTMQ rKq{K},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x27 /r"/"RAVM" { .Instruction = ND_INS_VPTESTMQ, .Category = ND_CAT_LOGICAL, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1700, + .Mnemonic = 1735, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_BROADCAST, @@ -109194,6 +114377,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -109209,12 +114393,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3897 Instruction:"VPTESTMW rKq{K},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x26 /r"/"RAVM" + // Pos:3942 Instruction:"VPTESTMW rKq{K},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x26 /r"/"RAVM" { .Instruction = ND_INS_VPTESTMW, .Category = ND_CAT_LOGICAL, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1701, + .Mnemonic = 1736, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -109223,6 +114407,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4nb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -109238,12 +114423,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3898 Instruction:"VPTESTNMB rKq{K},aKq,Hfv,Wfv" Encoding:"evex m:2 p:2 l:x w:0 0x26 /r"/"RAVM" + // Pos:3943 Instruction:"VPTESTNMB rKq{K},aKq,Hfv,Wfv" Encoding:"evex m:2 p:2 l:x w:0 0x26 /r"/"RAVM" { .Instruction = ND_INS_VPTESTNMB, .Category = ND_CAT_LOGICAL, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1702, + .Mnemonic = 1737, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -109252,6 +114437,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4nb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -109267,12 +114453,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3899 Instruction:"VPTESTNMD rKq{K},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:2 l:x w:0 0x27 /r"/"RAVM" + // Pos:3944 Instruction:"VPTESTNMD rKq{K},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:2 l:x w:0 0x27 /r"/"RAVM" { .Instruction = ND_INS_VPTESTNMD, .Category = ND_CAT_LOGICAL, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1703, + .Mnemonic = 1738, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_BROADCAST, @@ -109281,6 +114467,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -109296,12 +114483,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3900 Instruction:"VPTESTNMQ rKq{K},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:2 l:x w:1 0x27 /r"/"RAVM" + // Pos:3945 Instruction:"VPTESTNMQ rKq{K},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:2 l:x w:1 0x27 /r"/"RAVM" { .Instruction = ND_INS_VPTESTNMQ, .Category = ND_CAT_LOGICAL, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1704, + .Mnemonic = 1739, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_BROADCAST, @@ -109310,6 +114497,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -109325,12 +114513,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3901 Instruction:"VPTESTNMW rKq{K},aKq,Hfv,Wfv" Encoding:"evex m:2 p:2 l:x w:1 0x26 /r"/"RAVM" + // Pos:3946 Instruction:"VPTESTNMW rKq{K},aKq,Hfv,Wfv" Encoding:"evex m:2 p:2 l:x w:1 0x26 /r"/"RAVM" { .Instruction = ND_INS_VPTESTNMW, .Category = ND_CAT_LOGICAL, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1705, + .Mnemonic = 1740, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -109339,6 +114527,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4nb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -109354,12 +114543,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3902 Instruction:"VPUNPCKHBW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0x68 /r"/"RAVM" + // Pos:3947 Instruction:"VPUNPCKHBW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0x68 /r"/"RAVM" { .Instruction = ND_INS_VPUNPCKHBW, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1706, + .Mnemonic = 1741, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -109368,6 +114557,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NFnb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -109383,12 +114573,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3903 Instruction:"VPUNPCKHBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x68 /r"/"RVM" + // Pos:3948 Instruction:"VPUNPCKHBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x68 /r"/"RVM" { .Instruction = ND_INS_VPUNPCKHBW, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1706, + .Mnemonic = 1741, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -109397,6 +114587,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -109411,12 +114602,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3904 Instruction:"VPUNPCKHDQ Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0x6A /r"/"RAVM" + // Pos:3949 Instruction:"VPUNPCKHDQ Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0x6A /r"/"RAVM" { .Instruction = ND_INS_VPUNPCKHDQ, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1707, + .Mnemonic = 1742, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -109425,6 +114616,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -109440,12 +114632,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3905 Instruction:"VPUNPCKHDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6A /r"/"RVM" + // Pos:3950 Instruction:"VPUNPCKHDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6A /r"/"RVM" { .Instruction = ND_INS_VPUNPCKHDQ, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1707, + .Mnemonic = 1742, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -109454,6 +114646,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -109468,12 +114661,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3906 Instruction:"VPUNPCKHQDQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0x6D /r"/"RAVM" + // Pos:3951 Instruction:"VPUNPCKHQDQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0x6D /r"/"RAVM" { .Instruction = ND_INS_VPUNPCKHQDQ, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1708, + .Mnemonic = 1743, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -109482,6 +114675,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -109497,12 +114691,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3907 Instruction:"VPUNPCKHQDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6D /r"/"RVM" + // Pos:3952 Instruction:"VPUNPCKHQDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6D /r"/"RVM" { .Instruction = ND_INS_VPUNPCKHQDQ, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1708, + .Mnemonic = 1743, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -109511,6 +114705,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -109525,12 +114720,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3908 Instruction:"VPUNPCKHWD Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0x69 /r"/"RAVM" + // Pos:3953 Instruction:"VPUNPCKHWD Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0x69 /r"/"RAVM" { .Instruction = ND_INS_VPUNPCKHWD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1709, + .Mnemonic = 1744, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -109539,6 +114734,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NFnb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -109554,12 +114750,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3909 Instruction:"VPUNPCKHWD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x69 /r"/"RVM" + // Pos:3954 Instruction:"VPUNPCKHWD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x69 /r"/"RVM" { .Instruction = ND_INS_VPUNPCKHWD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1709, + .Mnemonic = 1744, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -109568,6 +114764,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -109582,12 +114779,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3910 Instruction:"VPUNPCKLBW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:x 0x60 /r"/"RAVM" + // Pos:3955 Instruction:"VPUNPCKLBW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:x 0x60 /r"/"RAVM" { .Instruction = ND_INS_VPUNPCKLBW, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1710, + .Mnemonic = 1745, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -109596,6 +114793,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NFnb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -109611,12 +114809,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3911 Instruction:"VPUNPCKLBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x60 /r"/"RVM" + // Pos:3956 Instruction:"VPUNPCKLBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x60 /r"/"RVM" { .Instruction = ND_INS_VPUNPCKLBW, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1710, + .Mnemonic = 1745, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -109625,6 +114823,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -109639,12 +114838,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3912 Instruction:"VPUNPCKLDQ Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0x62 /r"/"RAVM" + // Pos:3957 Instruction:"VPUNPCKLDQ Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0x62 /r"/"RAVM" { .Instruction = ND_INS_VPUNPCKLDQ, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1711, + .Mnemonic = 1746, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -109653,6 +114852,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -109668,12 +114868,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3913 Instruction:"VPUNPCKLDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x62 /r"/"RVM" + // Pos:3958 Instruction:"VPUNPCKLDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x62 /r"/"RVM" { .Instruction = ND_INS_VPUNPCKLDQ, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1711, + .Mnemonic = 1746, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -109682,6 +114882,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -109696,12 +114897,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3914 Instruction:"VPUNPCKLQDQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0x6C /r"/"RAVM" + // Pos:3959 Instruction:"VPUNPCKLQDQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0x6C /r"/"RAVM" { .Instruction = ND_INS_VPUNPCKLQDQ, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1712, + .Mnemonic = 1747, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -109710,6 +114911,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -109725,12 +114927,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3915 Instruction:"VPUNPCKLQDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6C /r"/"RVM" + // Pos:3960 Instruction:"VPUNPCKLQDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6C /r"/"RVM" { .Instruction = ND_INS_VPUNPCKLQDQ, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1712, + .Mnemonic = 1747, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -109739,6 +114941,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -109753,12 +114956,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3916 Instruction:"VPUNPCKLWD Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:x 0x61 /r"/"RAVM" + // Pos:3961 Instruction:"VPUNPCKLWD Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:x 0x61 /r"/"RAVM" { .Instruction = ND_INS_VPUNPCKLWD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1713, + .Mnemonic = 1748, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -109767,6 +114970,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NFnb, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -109782,12 +114986,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3917 Instruction:"VPUNPCKLWD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x61 /r"/"RVM" + // Pos:3962 Instruction:"VPUNPCKLWD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x61 /r"/"RVM" { .Instruction = ND_INS_VPUNPCKLWD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1713, + .Mnemonic = 1748, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -109796,6 +115000,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -109810,12 +115015,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3918 Instruction:"VPXOR Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEF /r"/"RVM" + // Pos:3963 Instruction:"VPXOR Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEF /r"/"RVM" { .Instruction = ND_INS_VPXOR, .Category = ND_CAT_LOGICAL, .IsaSet = ND_SET_AVX, - .Mnemonic = 1714, + .Mnemonic = 1749, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -109824,6 +115029,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -109838,12 +115044,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3919 Instruction:"VPXORD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0xEF /r"/"RAVM" + // Pos:3964 Instruction:"VPXORD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0xEF /r"/"RAVM" { .Instruction = ND_INS_VPXORD, .Category = ND_CAT_LOGICAL, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1715, + .Mnemonic = 1750, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -109852,6 +115058,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -109867,12 +115074,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3920 Instruction:"VPXORQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0xEF /r"/"RAVM" + // Pos:3965 Instruction:"VPXORQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0xEF /r"/"RAVM" { .Instruction = ND_INS_VPXORQ, .Category = ND_CAT_LOGICAL, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1716, + .Mnemonic = 1751, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -109881,6 +115088,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -109896,12 +115104,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3921 Instruction:"VRANGEPD Vfv{K}{z},aKq,Hfv,Wfv|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x50 /r ib"/"RAVMI" + // Pos:3966 Instruction:"VRANGEPD Vfv{K}{z},aKq,Hfv,Wfv|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x50 /r ib"/"RAVMI" { .Instruction = ND_INS_VRANGEPD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 1717, + .Mnemonic = 1752, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -109910,6 +115118,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -109926,12 +115135,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3922 Instruction:"VRANGEPS Vfv{K}{z},aKq,Hfv,Wfv|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x50 /r ib"/"RAVMI" + // Pos:3967 Instruction:"VRANGEPS Vfv{K}{z},aKq,Hfv,Wfv|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x50 /r ib"/"RAVMI" { .Instruction = ND_INS_VRANGEPS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 1718, + .Mnemonic = 1753, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -109940,6 +115149,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -109956,12 +115166,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3923 Instruction:"VRANGESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x51 /r ib"/"RAVMI" + // Pos:3968 Instruction:"VRANGESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x51 /r ib"/"RAVMI" { .Instruction = ND_INS_VRANGESD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 1719, + .Mnemonic = 1754, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, @@ -109970,6 +115180,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -109986,12 +115197,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3924 Instruction:"VRANGESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x51 /r ib"/"RAVMI" + // Pos:3969 Instruction:"VRANGESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x51 /r ib"/"RAVMI" { .Instruction = ND_INS_VRANGESS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 1720, + .Mnemonic = 1755, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, @@ -110000,6 +115211,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -110016,12 +115228,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3925 Instruction:"VRCP14PD Vfv{K}{z},aKq,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x4C /r"/"RAM" + // Pos:3970 Instruction:"VRCP14PD Vfv{K}{z},aKq,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x4C /r"/"RAM" { .Instruction = ND_INS_VRCP14PD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1721, + .Mnemonic = 1756, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -110030,6 +115242,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -110044,12 +115257,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3926 Instruction:"VRCP14PS Vfv{K}{z},aKq,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x4C /r"/"RAM" + // Pos:3971 Instruction:"VRCP14PS Vfv{K}{z},aKq,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x4C /r"/"RAM" { .Instruction = ND_INS_VRCP14PS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1722, + .Mnemonic = 1757, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -110058,6 +115271,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -110072,12 +115286,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3927 Instruction:"VRCP14SD Vdq{K}{z},aKq,Hdq,Wsd" Encoding:"evex m:2 p:1 l:x w:1 0x4D /r"/"RAVM" + // Pos:3972 Instruction:"VRCP14SD Vdq{K}{z},aKq,Hdq,Wsd" Encoding:"evex m:2 p:1 l:x w:1 0x4D /r"/"RAVM" { .Instruction = ND_INS_VRCP14SD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1723, + .Mnemonic = 1758, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -110086,6 +115300,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E10, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -110101,12 +115316,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3928 Instruction:"VRCP14SS Vdq{K}{z},aKq,Hdq,Wss" Encoding:"evex m:2 p:1 l:x w:0 0x4D /r"/"RAVM" + // Pos:3973 Instruction:"VRCP14SS Vdq{K}{z},aKq,Hdq,Wss" Encoding:"evex m:2 p:1 l:x w:0 0x4D /r"/"RAVM" { .Instruction = ND_INS_VRCP14SS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1724, + .Mnemonic = 1759, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -110115,6 +115330,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E10, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -110130,12 +115346,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3929 Instruction:"VRCP28PD Voq{K}{z},aKq,Woq|B64{sae}" Encoding:"evex m:2 p:1 l:2 w:1 0xCA /r"/"RAM" + // Pos:3974 Instruction:"VRCP28PD Voq{K}{z},aKq,Woq|B64{sae}" Encoding:"evex m:2 p:1 l:2 w:1 0xCA /r"/"RAM" { .Instruction = ND_INS_VRCP28PD, .Category = ND_CAT_KNL, .IsaSet = ND_SET_AVX512ER, - .Mnemonic = 1725, + .Mnemonic = 1760, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -110144,6 +115360,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_ZE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -110158,12 +115375,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3930 Instruction:"VRCP28PS Voq{K}{z},aKq,Woq|B32{sae}" Encoding:"evex m:2 p:1 l:2 w:0 0xCA /r"/"RAM" + // Pos:3975 Instruction:"VRCP28PS Voq{K}{z},aKq,Woq|B32{sae}" Encoding:"evex m:2 p:1 l:2 w:0 0xCA /r"/"RAM" { .Instruction = ND_INS_VRCP28PS, .Category = ND_CAT_KNL, .IsaSet = ND_SET_AVX512ER, - .Mnemonic = 1726, + .Mnemonic = 1761, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -110172,6 +115389,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_ZE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -110186,12 +115404,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3931 Instruction:"VRCP28SD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:2 p:1 l:i w:1 0xCB /r"/"RAVM" + // Pos:3976 Instruction:"VRCP28SD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:2 p:1 l:i w:1 0xCB /r"/"RAVM" { .Instruction = ND_INS_VRCP28SD, .Category = ND_CAT_KNL, .IsaSet = ND_SET_AVX512ER, - .Mnemonic = 1727, + .Mnemonic = 1762, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, @@ -110200,6 +115418,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_ZE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -110215,12 +115434,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3932 Instruction:"VRCP28SS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:2 p:1 l:i w:0 0xCB /r"/"RAVM" + // Pos:3977 Instruction:"VRCP28SS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:2 p:1 l:i w:0 0xCB /r"/"RAVM" { .Instruction = ND_INS_VRCP28SS, .Category = ND_CAT_KNL, .IsaSet = ND_SET_AVX512ER, - .Mnemonic = 1728, + .Mnemonic = 1763, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, @@ -110229,6 +115448,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_ZE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -110244,12 +115464,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3933 Instruction:"VRCPPBF16 Vfv{K}{z},aKq,Wfv|B16" Encoding:"evex m:6 p:0 l:x w:0 0x4C /r"/"RAM" + // Pos:3978 Instruction:"VRCPPBF16 Vfv{K}{z},aKq,Wfv|B16" Encoding:"evex m:6 p:0 l:x w:0 0x4C /r"/"RAM" { .Instruction = ND_INS_VRCPPBF16, .Category = ND_CAT_AVX10BF16, .IsaSet = ND_SET_AVX102, - .Mnemonic = 1729, + .Mnemonic = 1764, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -110258,6 +115478,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -110272,12 +115493,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3934 Instruction:"VRCPPH Vfv{K}{z},aKq,Wfv|B16" Encoding:"evex m:6 p:1 l:x w:0 0x4C /r"/"RAM" + // Pos:3979 Instruction:"VRCPPH Vfv{K}{z},aKq,Wfv|B16" Encoding:"evex m:6 p:1 l:x w:0 0x4C /r"/"RAM" { .Instruction = ND_INS_VRCPPH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1730, + .Mnemonic = 1765, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -110286,6 +115507,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -110300,12 +115522,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3935 Instruction:"VRCPPS Vps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x53 /r"/"RM" + // Pos:3980 Instruction:"VRCPPS Vps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x53 /r"/"RM" { .Instruction = ND_INS_VRCPPS, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1731, + .Mnemonic = 1766, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -110314,6 +115536,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -110327,12 +115550,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3936 Instruction:"VRCPSH Vdq{K}{z},aKq,Hdq,Wsh" Encoding:"evex m:6 p:1 l:i w:0 0x4D /r"/"RAVM" + // Pos:3981 Instruction:"VRCPSH Vdq{K}{z},aKq,Hdq,Wsh" Encoding:"evex m:6 p:1 l:i w:0 0x4D /r"/"RAVM" { .Instruction = ND_INS_VRCPSH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1732, + .Mnemonic = 1767, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -110341,6 +115564,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E10, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -110356,12 +115580,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3937 Instruction:"VRCPSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x53 /r"/"RVM" + // Pos:3982 Instruction:"VRCPSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x53 /r"/"RVM" { .Instruction = ND_INS_VRCPSS, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1733, + .Mnemonic = 1768, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -110370,6 +115594,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -110384,12 +115609,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3938 Instruction:"VREDUCENEPBF16 Vfv{K}{z},aKq,Wfv|B16,Ib" Encoding:"evex m:3 p:3 l:x w:0 0x56 /r ib"/"RAMI" + // Pos:3983 Instruction:"VREDUCENEPBF16 Vfv{K}{z},aKq,Wfv|B16,Ib" Encoding:"evex m:3 p:3 l:x w:0 0x56 /r ib"/"RAMI" { .Instruction = ND_INS_VREDUCENEPBF16, .Category = ND_CAT_AVX10BF16, .IsaSet = ND_SET_AVX102, - .Mnemonic = 1734, + .Mnemonic = 1769, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -110398,6 +115623,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -110413,12 +115639,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3939 Instruction:"VREDUCEPD Vfv{K}{z},aKq,Wfv|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x56 /r ib"/"RAMI" + // Pos:3984 Instruction:"VREDUCEPD Vfv{K}{z},aKq,Wfv|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x56 /r ib"/"RAMI" { .Instruction = ND_INS_VREDUCEPD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 1735, + .Mnemonic = 1770, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -110427,6 +115653,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -110442,12 +115669,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3940 Instruction:"VREDUCEPH Vfv{K}{z},aKq,Wfv|B16{sae},Ib" Encoding:"evex m:3 p:0 l:x w:0 0x56 /r ib"/"RAMI" + // Pos:3985 Instruction:"VREDUCEPH Vfv{K}{z},aKq,Wfv|B16{sae},Ib" Encoding:"evex m:3 p:0 l:x w:0 0x56 /r ib"/"RAMI" { .Instruction = ND_INS_VREDUCEPH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1736, + .Mnemonic = 1771, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -110456,6 +115683,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -110471,12 +115699,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3941 Instruction:"VREDUCEPS Vfv{K}{z},aKq,Wfv|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x56 /r ib"/"RAMI" + // Pos:3986 Instruction:"VREDUCEPS Vfv{K}{z},aKq,Wfv|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x56 /r ib"/"RAMI" { .Instruction = ND_INS_VREDUCEPS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 1737, + .Mnemonic = 1772, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -110485,6 +115713,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -110500,12 +115729,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3942 Instruction:"VREDUCESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x57 /r ib"/"RAVMI" + // Pos:3987 Instruction:"VREDUCESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x57 /r ib"/"RAVMI" { .Instruction = ND_INS_VREDUCESD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 1738, + .Mnemonic = 1773, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, @@ -110514,6 +115743,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -110530,12 +115760,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3943 Instruction:"VREDUCESH Vdq{K}{z},aKq,Hdq,Wsh{sae},Ib" Encoding:"evex m:3 p:0 l:i w:0 0x57 /r ib"/"RAVMI" + // Pos:3988 Instruction:"VREDUCESH Vdq{K}{z},aKq,Hdq,Wsh{sae},Ib" Encoding:"evex m:3 p:0 l:i w:0 0x57 /r ib"/"RAVMI" { .Instruction = ND_INS_VREDUCESH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1739, + .Mnemonic = 1774, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, @@ -110544,6 +115774,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -110560,12 +115791,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3944 Instruction:"VREDUCESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x57 /r ib"/"RAVMI" + // Pos:3989 Instruction:"VREDUCESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x57 /r ib"/"RAVMI" { .Instruction = ND_INS_VREDUCESS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 1740, + .Mnemonic = 1775, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, @@ -110574,6 +115805,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -110590,12 +115822,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3945 Instruction:"VRNDSCALENEPBF16 Vfv{K}{z},aKq,Wfv|B16,Ib" Encoding:"evex m:3 p:3 l:x w:0 0x08 /r ib"/"RAMI" + // Pos:3990 Instruction:"VRNDSCALENEPBF16 Vfv{K}{z},aKq,Wfv|B16,Ib" Encoding:"evex m:3 p:3 l:x w:0 0x08 /r ib"/"RAMI" { .Instruction = ND_INS_VRNDSCALENEPBF16, .Category = ND_CAT_AVX10BF16, .IsaSet = ND_SET_AVX102, - .Mnemonic = 1741, + .Mnemonic = 1776, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -110604,6 +115836,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -110619,12 +115852,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3946 Instruction:"VRNDSCALEPD Vfv{K}{z},aKq,Wfv|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x09 /r ib"/"RAMI" + // Pos:3991 Instruction:"VRNDSCALEPD Vfv{K}{z},aKq,Wfv|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x09 /r ib"/"RAMI" { .Instruction = ND_INS_VRNDSCALEPD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1742, + .Mnemonic = 1777, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -110633,6 +115866,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -110648,12 +115882,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3947 Instruction:"VRNDSCALEPH Vfv{K}{z},aKq,Wfv|B16{sae},Ib" Encoding:"evex m:3 p:0 l:x w:0 0x08 /r ib"/"RAMI" + // Pos:3992 Instruction:"VRNDSCALEPH Vfv{K}{z},aKq,Wfv|B16{sae},Ib" Encoding:"evex m:3 p:0 l:x w:0 0x08 /r ib"/"RAMI" { .Instruction = ND_INS_VRNDSCALEPH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1743, + .Mnemonic = 1778, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -110662,6 +115896,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE|ND_SIMD_EXC_UE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -110677,12 +115912,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3948 Instruction:"VRNDSCALEPS Vfv{K}{z},aKq,Wfv|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x08 /r ib"/"RAMI" + // Pos:3993 Instruction:"VRNDSCALEPS Vfv{K}{z},aKq,Wfv|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x08 /r ib"/"RAMI" { .Instruction = ND_INS_VRNDSCALEPS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1744, + .Mnemonic = 1779, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -110691,6 +115926,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -110706,12 +115942,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3949 Instruction:"VRNDSCALESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x0B /r ib"/"RAVMI" + // Pos:3994 Instruction:"VRNDSCALESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x0B /r ib"/"RAVMI" { .Instruction = ND_INS_VRNDSCALESD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1745, + .Mnemonic = 1780, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, @@ -110720,6 +115956,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -110736,12 +115973,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3950 Instruction:"VRNDSCALESH Vdq{K}{z},aKq,Hdq,Wsh{sae},Ib" Encoding:"evex m:3 p:0 l:i w:0 0x0A /r ib"/"RAVMI" + // Pos:3995 Instruction:"VRNDSCALESH Vdq{K}{z},aKq,Hdq,Wsh{sae},Ib" Encoding:"evex m:3 p:0 l:i w:0 0x0A /r ib"/"RAVMI" { .Instruction = ND_INS_VRNDSCALESH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1746, + .Mnemonic = 1781, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, @@ -110750,6 +115987,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -110766,12 +116004,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3951 Instruction:"VRNDSCALESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x0A /r ib"/"RAVMI" + // Pos:3996 Instruction:"VRNDSCALESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x0A /r ib"/"RAVMI" { .Instruction = ND_INS_VRNDSCALESS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1747, + .Mnemonic = 1782, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, @@ -110780,6 +116018,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -110796,12 +116035,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3952 Instruction:"VROUNDPD Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x09 /r ib"/"RMI" + // Pos:3997 Instruction:"VROUNDPD Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x09 /r ib"/"RMI" { .Instruction = ND_INS_VROUNDPD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1748, + .Mnemonic = 1783, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -110810,6 +116049,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -110824,12 +116064,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3953 Instruction:"VROUNDPS Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x08 /r ib"/"RMI" + // Pos:3998 Instruction:"VROUNDPS Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x08 /r ib"/"RMI" { .Instruction = ND_INS_VROUNDPS, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1749, + .Mnemonic = 1784, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -110838,6 +116078,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -110852,12 +116093,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3954 Instruction:"VROUNDSD Vsd,Hsd,Wsd,Ib" Encoding:"vex m:3 p:1 l:i w:i 0x0B /r ib"/"RVMI" + // Pos:3999 Instruction:"VROUNDSD Vsd,Hsd,Wsd,Ib" Encoding:"vex m:3 p:1 l:i w:i 0x0B /r ib"/"RVMI" { .Instruction = ND_INS_VROUNDSD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1750, + .Mnemonic = 1785, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -110866,6 +116107,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -110881,12 +116123,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3955 Instruction:"VROUNDSS Vss,Hss,Wss,Ib" Encoding:"vex m:3 p:1 l:i w:i 0x0A /r ib"/"RVMI" + // Pos:4000 Instruction:"VROUNDSS Vss,Hss,Wss,Ib" Encoding:"vex m:3 p:1 l:i w:i 0x0A /r ib"/"RVMI" { .Instruction = ND_INS_VROUNDSS, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1751, + .Mnemonic = 1786, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -110895,6 +116137,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -110910,12 +116153,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3956 Instruction:"VRSQRT14PD Vfv{K}{z},aKq,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x4E /r"/"RAM" + // Pos:4001 Instruction:"VRSQRT14PD Vfv{K}{z},aKq,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x4E /r"/"RAM" { .Instruction = ND_INS_VRSQRT14PD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1752, + .Mnemonic = 1787, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -110924,6 +116167,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -110938,12 +116182,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3957 Instruction:"VRSQRT14PS Vfv{K}{z},aKq,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x4E /r"/"RAM" + // Pos:4002 Instruction:"VRSQRT14PS Vfv{K}{z},aKq,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x4E /r"/"RAM" { .Instruction = ND_INS_VRSQRT14PS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1753, + .Mnemonic = 1788, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -110952,6 +116196,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -110966,12 +116211,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3958 Instruction:"VRSQRT14SD Vdq{K}{z},aKq,Hdq,Wsd" Encoding:"evex m:2 p:1 l:x w:1 0x4F /r"/"RAVM" + // Pos:4003 Instruction:"VRSQRT14SD Vdq{K}{z},aKq,Hdq,Wsd" Encoding:"evex m:2 p:1 l:x w:1 0x4F /r"/"RAVM" { .Instruction = ND_INS_VRSQRT14SD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1754, + .Mnemonic = 1789, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -110980,6 +116225,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E10, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -110995,12 +116241,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3959 Instruction:"VRSQRT14SS Vdq{K}{z},aKq,Hdq,Wss" Encoding:"evex m:2 p:1 l:x w:0 0x4F /r"/"RAVM" + // Pos:4004 Instruction:"VRSQRT14SS Vdq{K}{z},aKq,Hdq,Wss" Encoding:"evex m:2 p:1 l:x w:0 0x4F /r"/"RAVM" { .Instruction = ND_INS_VRSQRT14SS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1755, + .Mnemonic = 1790, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -111009,6 +116255,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E10, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -111024,12 +116271,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3960 Instruction:"VRSQRT28PD Voq{K}{z},aKq,Woq|B64{sae}" Encoding:"evex m:2 p:1 l:2 w:1 0xCC /r"/"RAM" + // Pos:4005 Instruction:"VRSQRT28PD Voq{K}{z},aKq,Woq|B64{sae}" Encoding:"evex m:2 p:1 l:2 w:1 0xCC /r"/"RAM" { .Instruction = ND_INS_VRSQRT28PD, .Category = ND_CAT_KNL, .IsaSet = ND_SET_AVX512ER, - .Mnemonic = 1756, + .Mnemonic = 1791, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -111038,6 +116285,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_ZE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -111052,12 +116300,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3961 Instruction:"VRSQRT28PS Voq{K}{z},aKq,Woq|B32{sae}" Encoding:"evex m:2 p:1 l:2 w:0 0xCC /r"/"RAM" + // Pos:4006 Instruction:"VRSQRT28PS Voq{K}{z},aKq,Woq|B32{sae}" Encoding:"evex m:2 p:1 l:2 w:0 0xCC /r"/"RAM" { .Instruction = ND_INS_VRSQRT28PS, .Category = ND_CAT_KNL, .IsaSet = ND_SET_AVX512ER, - .Mnemonic = 1757, + .Mnemonic = 1792, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -111066,6 +116314,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_ZE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -111080,12 +116329,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3962 Instruction:"VRSQRT28SD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:2 p:1 l:i w:1 0xCD /r"/"RAVM" + // Pos:4007 Instruction:"VRSQRT28SD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:2 p:1 l:i w:1 0xCD /r"/"RAVM" { .Instruction = ND_INS_VRSQRT28SD, .Category = ND_CAT_KNL, .IsaSet = ND_SET_AVX512ER, - .Mnemonic = 1758, + .Mnemonic = 1793, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, @@ -111094,6 +116343,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_ZE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -111109,12 +116359,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3963 Instruction:"VRSQRT28SS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:2 p:1 l:i w:0 0xCD /r"/"RAVM" + // Pos:4008 Instruction:"VRSQRT28SS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:2 p:1 l:i w:0 0xCD /r"/"RAVM" { .Instruction = ND_INS_VRSQRT28SS, .Category = ND_CAT_KNL, .IsaSet = ND_SET_AVX512ER, - .Mnemonic = 1759, + .Mnemonic = 1794, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, @@ -111123,6 +116373,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_ZE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -111138,12 +116389,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3964 Instruction:"VRSQRTPBF16 Vfv{K}{z},aKq,Wfv|B16" Encoding:"evex m:6 p:0 l:x w:0 0x4E /r"/"RAM" + // Pos:4009 Instruction:"VRSQRTPBF16 Vfv{K}{z},aKq,Wfv|B16" Encoding:"evex m:6 p:0 l:x w:0 0x4E /r"/"RAM" { .Instruction = ND_INS_VRSQRTPBF16, .Category = ND_CAT_AVX10BF16, .IsaSet = ND_SET_AVX102, - .Mnemonic = 1760, + .Mnemonic = 1795, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -111152,6 +116403,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -111166,12 +116418,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3965 Instruction:"VRSQRTPH Vfv{K}{z},aKq,Wfv|B16" Encoding:"evex m:6 p:1 l:x w:0 0x4E /r"/"RAM" + // Pos:4010 Instruction:"VRSQRTPH Vfv{K}{z},aKq,Wfv|B16" Encoding:"evex m:6 p:1 l:x w:0 0x4E /r"/"RAM" { .Instruction = ND_INS_VRSQRTPH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1761, + .Mnemonic = 1796, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -111180,6 +116432,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -111194,12 +116447,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3966 Instruction:"VRSQRTPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x52 /r"/"RM" + // Pos:4011 Instruction:"VRSQRTPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x52 /r"/"RM" { .Instruction = ND_INS_VRSQRTPS, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1762, + .Mnemonic = 1797, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -111208,6 +116461,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -111221,12 +116475,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3967 Instruction:"VRSQRTSH Vdq{K}{z},aKq,Hdq,Wsh" Encoding:"evex m:6 p:1 l:i w:0 0x4F /r"/"RAVM" + // Pos:4012 Instruction:"VRSQRTSH Vdq{K}{z},aKq,Hdq,Wsh" Encoding:"evex m:6 p:1 l:i w:0 0x4F /r"/"RAVM" { .Instruction = ND_INS_VRSQRTSH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1763, + .Mnemonic = 1798, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -111235,6 +116489,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E10, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -111250,12 +116505,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3968 Instruction:"VRSQRTSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x52 /r"/"RVM" + // Pos:4013 Instruction:"VRSQRTSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x52 /r"/"RVM" { .Instruction = ND_INS_VRSQRTSS, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1764, + .Mnemonic = 1799, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -111264,6 +116519,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -111278,12 +116534,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3969 Instruction:"VSCALEFPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:6 p:0 l:x w:0 0x2C /r"/"RAVM" + // Pos:4014 Instruction:"VSCALEFPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:6 p:0 l:x w:0 0x2C /r"/"RAVM" { .Instruction = ND_INS_VSCALEFPBF16, .Category = ND_CAT_AVX10BF16, .IsaSet = ND_SET_AVX102, - .Mnemonic = 1765, + .Mnemonic = 1800, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -111292,6 +116548,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -111307,12 +116564,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3970 Instruction:"VSCALEFPD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x2C /r"/"RAVM" + // Pos:4015 Instruction:"VSCALEFPD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x2C /r"/"RAVM" { .Instruction = ND_INS_VSCALEFPD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1766, + .Mnemonic = 1801, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -111321,6 +116578,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -111336,12 +116594,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3971 Instruction:"VSCALEFPH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x2C /r"/"RAVM" + // Pos:4016 Instruction:"VSCALEFPH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x2C /r"/"RAVM" { .Instruction = ND_INS_VSCALEFPH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1767, + .Mnemonic = 1802, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -111350,6 +116608,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -111365,12 +116624,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3972 Instruction:"VSCALEFPS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x2C /r"/"RAVM" + // Pos:4017 Instruction:"VSCALEFPS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x2C /r"/"RAVM" { .Instruction = ND_INS_VSCALEFPS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1768, + .Mnemonic = 1803, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -111379,6 +116638,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -111394,12 +116654,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3973 Instruction:"VSCALEFSD Vsd{K}{z},aKq,Hsd,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x2D /r"/"RAVM" + // Pos:4018 Instruction:"VSCALEFSD Vsd{K}{z},aKq,Hsd,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x2D /r"/"RAVM" { .Instruction = ND_INS_VSCALEFSD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1769, + .Mnemonic = 1804, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -111408,6 +116668,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -111423,12 +116684,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3974 Instruction:"VSCALEFSH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0x2D /r"/"RAVM" + // Pos:4019 Instruction:"VSCALEFSH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0x2D /r"/"RAVM" { .Instruction = ND_INS_VSCALEFSH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1770, + .Mnemonic = 1805, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -111437,6 +116698,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -111452,12 +116714,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3975 Instruction:"VSCALEFSS Vss{K}{z},aKq,Hss,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x2D /r"/"RAVM" + // Pos:4020 Instruction:"VSCALEFSS Vss{K}{z},aKq,Hss,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x2D /r"/"RAVM" { .Instruction = ND_INS_VSCALEFSS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1771, + .Mnemonic = 1806, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -111466,6 +116728,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -111481,12 +116744,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3976 Instruction:"VSCATTERDPD Mvm32h{K},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:1 0xA2 /r:mem vsib"/"MAR" + // Pos:4021 Instruction:"VSCATTERDPD Mvm32h{K},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:1 0xA2 /r:mem vsib"/"MAR" { .Instruction = ND_INS_VSCATTERDPD, .Category = ND_CAT_SCATTER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1772, + .Mnemonic = 1807, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -111495,6 +116758,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E12, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -111509,12 +116773,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3977 Instruction:"VSCATTERDPS Mvm32n{K},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:0 0xA2 /r:mem vsib"/"MAR" + // Pos:4022 Instruction:"VSCATTERDPS Mvm32n{K},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:0 0xA2 /r:mem vsib"/"MAR" { .Instruction = ND_INS_VSCATTERDPS, .Category = ND_CAT_SCATTER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1773, + .Mnemonic = 1808, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -111523,6 +116787,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E12, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -111537,12 +116802,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3978 Instruction:"VSCATTERPF0DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /5:mem vsib"/"MA" + // Pos:4023 Instruction:"VSCATTERPF0DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /5:mem vsib"/"MA" { .Instruction = ND_INS_VSCATTERPF0DPD, .Category = ND_CAT_SCATTER, .IsaSet = ND_SET_AVX512PF, - .Mnemonic = 1774, + .Mnemonic = 1809, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -111551,6 +116816,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E12NP, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -111564,12 +116830,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3979 Instruction:"VSCATTERPF0DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /5:mem vsib"/"MA" + // Pos:4024 Instruction:"VSCATTERPF0DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /5:mem vsib"/"MA" { .Instruction = ND_INS_VSCATTERPF0DPS, .Category = ND_CAT_SCATTER, .IsaSet = ND_SET_AVX512PF, - .Mnemonic = 1775, + .Mnemonic = 1810, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -111578,6 +116844,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E12NP, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -111591,12 +116858,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3980 Instruction:"VSCATTERPF0QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /5:mem vsib"/"MA" + // Pos:4025 Instruction:"VSCATTERPF0QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /5:mem vsib"/"MA" { .Instruction = ND_INS_VSCATTERPF0QPD, .Category = ND_CAT_SCATTER, .IsaSet = ND_SET_AVX512PF, - .Mnemonic = 1776, + .Mnemonic = 1811, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -111605,6 +116872,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E12NP, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -111618,12 +116886,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3981 Instruction:"VSCATTERPF0QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /5:mem vsib"/"MA" + // Pos:4026 Instruction:"VSCATTERPF0QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /5:mem vsib"/"MA" { .Instruction = ND_INS_VSCATTERPF0QPS, .Category = ND_CAT_SCATTER, .IsaSet = ND_SET_AVX512PF, - .Mnemonic = 1777, + .Mnemonic = 1812, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -111632,6 +116900,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E12NP, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -111645,12 +116914,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3982 Instruction:"VSCATTERPF1DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /6:mem vsib"/"MA" + // Pos:4027 Instruction:"VSCATTERPF1DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /6:mem vsib"/"MA" { .Instruction = ND_INS_VSCATTERPF1DPD, .Category = ND_CAT_SCATTER, .IsaSet = ND_SET_AVX512PF, - .Mnemonic = 1778, + .Mnemonic = 1813, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -111659,6 +116928,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E12NP, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -111672,12 +116942,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3983 Instruction:"VSCATTERPF1DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /6:mem vsib"/"MA" + // Pos:4028 Instruction:"VSCATTERPF1DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /6:mem vsib"/"MA" { .Instruction = ND_INS_VSCATTERPF1DPS, .Category = ND_CAT_SCATTER, .IsaSet = ND_SET_AVX512PF, - .Mnemonic = 1779, + .Mnemonic = 1814, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -111686,6 +116956,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E12NP, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -111699,12 +116970,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3984 Instruction:"VSCATTERPF1QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /6:mem vsib"/"MA" + // Pos:4029 Instruction:"VSCATTERPF1QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /6:mem vsib"/"MA" { .Instruction = ND_INS_VSCATTERPF1QPD, .Category = ND_CAT_SCATTER, .IsaSet = ND_SET_AVX512PF, - .Mnemonic = 1780, + .Mnemonic = 1815, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -111713,6 +116984,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E12NP, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -111726,12 +116998,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3985 Instruction:"VSCATTERPF1QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /6:mem vsib"/"MA" + // Pos:4030 Instruction:"VSCATTERPF1QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /6:mem vsib"/"MA" { .Instruction = ND_INS_VSCATTERPF1QPS, .Category = ND_CAT_SCATTER, .IsaSet = ND_SET_AVX512PF, - .Mnemonic = 1781, + .Mnemonic = 1816, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -111740,6 +117012,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E12NP, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -111753,12 +117026,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3986 Instruction:"VSCATTERQPD Mvm64n{K},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:1 0xA3 /r:mem vsib"/"MAR" + // Pos:4031 Instruction:"VSCATTERQPD Mvm64n{K},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:1 0xA3 /r:mem vsib"/"MAR" { .Instruction = ND_INS_VSCATTERQPD, .Category = ND_CAT_SCATTER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1782, + .Mnemonic = 1817, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -111767,6 +117040,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E12, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -111781,12 +117055,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3987 Instruction:"VSCATTERQPS Mvm64n{K},aKq,Vhv" Encoding:"evex m:2 p:1 l:x w:0 0xA3 /r:mem vsib"/"MAR" + // Pos:4032 Instruction:"VSCATTERQPS Mvm64n{K},aKq,Vhv" Encoding:"evex m:2 p:1 l:x w:0 0xA3 /r:mem vsib"/"MAR" { .Instruction = ND_INS_VSCATTERQPS, .Category = ND_CAT_SCATTER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1783, + .Mnemonic = 1818, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -111795,6 +117069,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E12, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -111809,12 +117084,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3988 Instruction:"VSHA512MSG1 Vqq,Udq" Encoding:"vex m:2 p:3 l:1 w:0 0xCC /r:reg"/"RM" + // Pos:4033 Instruction:"VSHA512MSG1 Vqq,Udq" Encoding:"vex m:2 p:3 l:1 w:0 0xCC /r:reg"/"RM" { .Instruction = ND_INS_VSHA512MSG1, .Category = ND_CAT_SHA512, .IsaSet = ND_SET_SHA512, - .Mnemonic = 1784, + .Mnemonic = 1819, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -111823,6 +117098,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_6, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -111836,12 +117112,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3989 Instruction:"VSHA512MSG2 Vqq,Uqq" Encoding:"vex m:2 p:3 l:1 w:0 0xCD /r:reg"/"RM" + // Pos:4034 Instruction:"VSHA512MSG2 Vqq,Uqq" Encoding:"vex m:2 p:3 l:1 w:0 0xCD /r:reg"/"RM" { .Instruction = ND_INS_VSHA512MSG2, .Category = ND_CAT_SHA512, .IsaSet = ND_SET_SHA512, - .Mnemonic = 1785, + .Mnemonic = 1820, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -111850,6 +117126,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_6, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -111863,12 +117140,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3990 Instruction:"VSHA512RNDS2 Vqq,Hqq,Udq" Encoding:"vex m:2 p:3 l:1 w:0 0xCB /r:reg"/"RVM" + // Pos:4035 Instruction:"VSHA512RNDS2 Vqq,Hqq,Udq" Encoding:"vex m:2 p:3 l:1 w:0 0xCB /r:reg"/"RVM" { .Instruction = ND_INS_VSHA512RNDS2, .Category = ND_CAT_SHA512, .IsaSet = ND_SET_SHA512, - .Mnemonic = 1786, + .Mnemonic = 1821, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -111877,6 +117154,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_6, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -111891,12 +117169,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3991 Instruction:"VSHUFF32X4 Vuv{K}{z},aKq,Huv,Wuv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x23 /r ib"/"RAVMI" + // Pos:4036 Instruction:"VSHUFF32X4 Vuv{K}{z},aKq,Huv,Wuv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x23 /r ib"/"RAVMI" { .Instruction = ND_INS_VSHUFF32X4, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1787, + .Mnemonic = 1822, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -111905,6 +117183,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -111921,12 +117200,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3992 Instruction:"VSHUFF64X2 Vuv{K}{z},aKq,Huv,Wuv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x23 /r ib"/"RAVMI" + // Pos:4037 Instruction:"VSHUFF64X2 Vuv{K}{z},aKq,Huv,Wuv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x23 /r ib"/"RAVMI" { .Instruction = ND_INS_VSHUFF64X2, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1788, + .Mnemonic = 1823, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -111935,6 +117214,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -111951,12 +117231,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3993 Instruction:"VSHUFI32X4 Vuv{K}{z},aKq,Huv,Wuv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x43 /r ib"/"RAVMI" + // Pos:4038 Instruction:"VSHUFI32X4 Vuv{K}{z},aKq,Huv,Wuv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x43 /r ib"/"RAVMI" { .Instruction = ND_INS_VSHUFI32X4, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1789, + .Mnemonic = 1824, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -111965,6 +117245,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -111981,12 +117262,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3994 Instruction:"VSHUFI64X2 Vuv{K}{z},aKq,Huv,Wuv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x43 /r ib"/"RAVMI" + // Pos:4039 Instruction:"VSHUFI64X2 Vuv{K}{z},aKq,Huv,Wuv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x43 /r ib"/"RAVMI" { .Instruction = ND_INS_VSHUFI64X2, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1790, + .Mnemonic = 1825, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -111995,6 +117276,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -112011,12 +117293,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3995 Instruction:"VSHUFPD Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0xC6 /r ib"/"RAVMI" + // Pos:4040 Instruction:"VSHUFPD Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0xC6 /r ib"/"RAVMI" { .Instruction = ND_INS_VSHUFPD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1791, + .Mnemonic = 1826, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -112025,6 +117307,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -112041,12 +117324,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3996 Instruction:"VSHUFPD Vpd,Hpd,Wpd,Ib" Encoding:"vex m:1 p:1 l:x w:i 0xC6 /r ib"/"RVMI" + // Pos:4041 Instruction:"VSHUFPD Vpd,Hpd,Wpd,Ib" Encoding:"vex m:1 p:1 l:x w:i 0xC6 /r ib"/"RVMI" { .Instruction = ND_INS_VSHUFPD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1791, + .Mnemonic = 1826, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -112055,6 +117338,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -112070,12 +117354,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3997 Instruction:"VSHUFPS Vfv{K}{z},aKq,Hfv,Wfv|B32,Ib" Encoding:"evex m:1 p:0 l:x w:0 0xC6 /r ib"/"RAVMI" + // Pos:4042 Instruction:"VSHUFPS Vfv{K}{z},aKq,Hfv,Wfv|B32,Ib" Encoding:"evex m:1 p:0 l:x w:0 0xC6 /r ib"/"RAVMI" { .Instruction = ND_INS_VSHUFPS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1792, + .Mnemonic = 1827, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -112084,6 +117368,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -112100,12 +117385,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3998 Instruction:"VSHUFPS Vps,Hps,Wps,Ib" Encoding:"vex m:1 p:0 l:x w:i 0xC6 /r ib"/"RVMI" + // Pos:4043 Instruction:"VSHUFPS Vps,Hps,Wps,Ib" Encoding:"vex m:1 p:0 l:x w:i 0xC6 /r ib"/"RVMI" { .Instruction = ND_INS_VSHUFPS, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1792, + .Mnemonic = 1827, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -112114,6 +117399,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -112129,12 +117415,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:3999 Instruction:"VSM3MSG1 Vdq,Hdq,Wdq" Encoding:"vex m:2 p:0 l:0 w:0 0xDA /r"/"RVM" + // Pos:4044 Instruction:"VSM3MSG1 Vdq,Hdq,Wdq" Encoding:"vex m:2 p:0 l:0 w:0 0xDA /r"/"RVM" { .Instruction = ND_INS_VSM3MSG1, .Category = ND_CAT_SM3, .IsaSet = ND_SET_SM3, - .Mnemonic = 1793, + .Mnemonic = 1828, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -112143,6 +117429,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -112157,12 +117444,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4000 Instruction:"VSM3MSG2 Vdq,Hdq,Wdq" Encoding:"vex m:2 p:1 l:0 w:0 0xDA /r"/"RVM" + // Pos:4045 Instruction:"VSM3MSG2 Vdq,Hdq,Wdq" Encoding:"vex m:2 p:1 l:0 w:0 0xDA /r"/"RVM" { .Instruction = ND_INS_VSM3MSG2, .Category = ND_CAT_SM3, .IsaSet = ND_SET_SM3, - .Mnemonic = 1794, + .Mnemonic = 1829, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -112171,6 +117458,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -112185,12 +117473,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4001 Instruction:"VSM3RNDS2 Vdq,Hdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0xDE /r ib"/"RVMI" + // Pos:4046 Instruction:"VSM3RNDS2 Vdq,Hdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0xDE /r ib"/"RVMI" { .Instruction = ND_INS_VSM3RNDS2, .Category = ND_CAT_SM3, .IsaSet = ND_SET_SM3, - .Mnemonic = 1795, + .Mnemonic = 1830, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -112199,6 +117487,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -112214,12 +117503,41 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4002 Instruction:"VSM4KEY4 Vx,Hx,Wx" Encoding:"vex m:2 p:2 l:x w:0 0xDA /r"/"RVM" + // Pos:4047 Instruction:"VSM4KEY4 Vfv,Hfv,Wfv" Encoding:"evex m:2 p:2 l:x w:0 0xDA /r"/"RVM" { .Instruction = ND_INS_VSM4KEY4, .Category = ND_CAT_SM4, .IsaSet = ND_SET_SM4, - .Mnemonic = 1796, + .Mnemonic = 1831, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E6, + .FpuFlags = 0, + .EvexMode = 0, + .SimdExc = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SM4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:4048 Instruction:"VSM4KEY4 Vx,Hx,Wx" Encoding:"vex m:2 p:2 l:x w:0 0xDA /r"/"RVM" + { + .Instruction = ND_INS_VSM4KEY4, + .Category = ND_CAT_SM4, + .IsaSet = ND_SET_SM4, + .Mnemonic = 1831, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -112228,6 +117546,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_6, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -112242,12 +117561,41 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4003 Instruction:"VSM4RNDS4 Vx,Hx,Wx" Encoding:"vex m:2 p:3 l:x w:0 0xDA /r"/"RVM" + // Pos:4049 Instruction:"VSM4RNDS4 Vfv,Hfv,Wfv" Encoding:"evex m:2 p:3 l:x w:0 0xDA /r"/"RVM" { .Instruction = ND_INS_VSM4RNDS4, .Category = ND_CAT_SM4, .IsaSet = ND_SET_SM4, - .Mnemonic = 1797, + .Mnemonic = 1832, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E6, + .FpuFlags = 0, + .EvexMode = 0, + .SimdExc = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SM4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:4050 Instruction:"VSM4RNDS4 Vx,Hx,Wx" Encoding:"vex m:2 p:3 l:x w:0 0xDA /r"/"RVM" + { + .Instruction = ND_INS_VSM4RNDS4, + .Category = ND_CAT_SM4, + .IsaSet = ND_SET_SM4, + .Mnemonic = 1832, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -112256,6 +117604,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_6, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -112270,12 +117619,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4004 Instruction:"VSQRTNEPBF16 Vfv{K}{z},aKq,Wfv|B16" Encoding:"evex m:5 p:1 l:x w:0 0x51 /r"/"RAM" + // Pos:4051 Instruction:"VSQRTNEPBF16 Vfv{K}{z},aKq,Wfv|B16" Encoding:"evex m:5 p:1 l:x w:0 0x51 /r"/"RAM" { .Instruction = ND_INS_VSQRTNEPBF16, .Category = ND_CAT_AVX10BF16, .IsaSet = ND_SET_AVX102, - .Mnemonic = 1798, + .Mnemonic = 1833, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -112284,6 +117633,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -112298,12 +117648,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4005 Instruction:"VSQRTPD Vfv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x51 /r"/"RAM" + // Pos:4052 Instruction:"VSQRTPD Vfv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x51 /r"/"RAM" { .Instruction = ND_INS_VSQRTPD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1799, + .Mnemonic = 1834, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -112312,6 +117662,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -112326,12 +117677,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4006 Instruction:"VSQRTPD Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x51 /r"/"RM" + // Pos:4053 Instruction:"VSQRTPD Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x51 /r"/"RM" { .Instruction = ND_INS_VSQRTPD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1799, + .Mnemonic = 1834, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -112340,6 +117691,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -112353,12 +117705,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4007 Instruction:"VSQRTPH Vfv{K}{z},aKq,Wfv|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x51 /r"/"RAM" + // Pos:4054 Instruction:"VSQRTPH Vfv{K}{z},aKq,Wfv|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x51 /r"/"RAM" { .Instruction = ND_INS_VSQRTPH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1800, + .Mnemonic = 1835, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -112367,6 +117719,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -112381,12 +117734,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4008 Instruction:"VSQRTPS Vfv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x51 /r"/"RAM" + // Pos:4055 Instruction:"VSQRTPS Vfv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x51 /r"/"RAM" { .Instruction = ND_INS_VSQRTPS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1801, + .Mnemonic = 1836, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -112395,6 +117748,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -112409,12 +117763,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4009 Instruction:"VSQRTPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x51 /r"/"RM" + // Pos:4056 Instruction:"VSQRTPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x51 /r"/"RM" { .Instruction = ND_INS_VSQRTPS, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1801, + .Mnemonic = 1836, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -112423,6 +117777,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -112436,12 +117791,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4010 Instruction:"VSQRTSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x51 /r"/"RAVM" + // Pos:4057 Instruction:"VSQRTSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x51 /r"/"RAVM" { .Instruction = ND_INS_VSQRTSD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1802, + .Mnemonic = 1837, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -112450,6 +117805,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -112465,12 +117821,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4011 Instruction:"VSQRTSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x51 /r"/"RVM" + // Pos:4058 Instruction:"VSQRTSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x51 /r"/"RVM" { .Instruction = ND_INS_VSQRTSD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1802, + .Mnemonic = 1837, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -112479,6 +117835,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -112493,12 +117850,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4012 Instruction:"VSQRTSH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:0 0x51 /r"/"RAVM" + // Pos:4059 Instruction:"VSQRTSH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:0 0x51 /r"/"RAVM" { .Instruction = ND_INS_VSQRTSH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1803, + .Mnemonic = 1838, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -112507,6 +117864,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -112522,12 +117880,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4013 Instruction:"VSQRTSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x51 /r"/"RAVM" + // Pos:4060 Instruction:"VSQRTSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x51 /r"/"RAVM" { .Instruction = ND_INS_VSQRTSS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1804, + .Mnemonic = 1839, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -112536,6 +117894,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -112551,12 +117910,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4014 Instruction:"VSQRTSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x51 /r"/"RVM" + // Pos:4061 Instruction:"VSQRTSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x51 /r"/"RVM" { .Instruction = ND_INS_VSQRTSS, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1804, + .Mnemonic = 1839, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -112565,6 +117924,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -112579,12 +117939,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4015 Instruction:"VSTMXCSR Md" Encoding:"vex m:1 p:0 0xAE /3:mem"/"M" + // Pos:4062 Instruction:"VSTMXCSR Md" Encoding:"vex m:1 p:0 0xAE /3:mem"/"M" { .Instruction = ND_INS_VSTMXCSR, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1805, + .Mnemonic = 1840, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -112593,6 +117953,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -112606,12 +117967,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4016 Instruction:"VSUBNEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:5 p:1 l:x w:0 0x5C /r"/"RAVM" + // Pos:4063 Instruction:"VSUBNEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:5 p:1 l:x w:0 0x5C /r"/"RAVM" { .Instruction = ND_INS_VSUBNEPBF16, .Category = ND_CAT_AVX10BF16, .IsaSet = ND_SET_AVX102, - .Mnemonic = 1806, + .Mnemonic = 1841, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -112620,6 +117981,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -112635,12 +117997,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4017 Instruction:"VSUBPD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x5C /r"/"RAVM" + // Pos:4064 Instruction:"VSUBPD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x5C /r"/"RAVM" { .Instruction = ND_INS_VSUBPD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1807, + .Mnemonic = 1842, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -112649,6 +118011,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -112664,12 +118027,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4018 Instruction:"VSUBPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5C /r"/"RVM" + // Pos:4065 Instruction:"VSUBPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5C /r"/"RVM" { .Instruction = ND_INS_VSUBPD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1807, + .Mnemonic = 1842, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -112678,6 +118041,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -112692,12 +118056,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4019 Instruction:"VSUBPH Vfv{K}{z},aKq,Hfv,Wfv|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x5C /r"/"RAVM" + // Pos:4066 Instruction:"VSUBPH Vfv{K}{z},aKq,Hfv,Wfv|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x5C /r"/"RAVM" { .Instruction = ND_INS_VSUBPH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1808, + .Mnemonic = 1843, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -112706,6 +118070,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -112721,12 +118086,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4020 Instruction:"VSUBPS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x5C /r"/"RAVM" + // Pos:4067 Instruction:"VSUBPS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x5C /r"/"RAVM" { .Instruction = ND_INS_VSUBPS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1809, + .Mnemonic = 1844, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -112735,6 +118100,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -112750,12 +118116,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4021 Instruction:"VSUBPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5C /r"/"RVM" + // Pos:4068 Instruction:"VSUBPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5C /r"/"RVM" { .Instruction = ND_INS_VSUBPS, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1809, + .Mnemonic = 1844, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -112764,6 +118130,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -112778,12 +118145,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4022 Instruction:"VSUBSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x5C /r"/"RAVM" + // Pos:4069 Instruction:"VSUBSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x5C /r"/"RAVM" { .Instruction = ND_INS_VSUBSD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1810, + .Mnemonic = 1845, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -112792,6 +118159,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -112807,12 +118175,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4023 Instruction:"VSUBSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5C /r"/"RVM" + // Pos:4070 Instruction:"VSUBSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5C /r"/"RVM" { .Instruction = ND_INS_VSUBSD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1810, + .Mnemonic = 1845, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -112821,6 +118189,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -112835,12 +118204,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4024 Instruction:"VSUBSH Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:0 0x5C /r"/"RAVM" + // Pos:4071 Instruction:"VSUBSH Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:0 0x5C /r"/"RAVM" { .Instruction = ND_INS_VSUBSH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1811, + .Mnemonic = 1846, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, @@ -112849,6 +118218,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -112864,12 +118234,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4025 Instruction:"VSUBSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x5C /r"/"RAVM" + // Pos:4072 Instruction:"VSUBSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x5C /r"/"RAVM" { .Instruction = ND_INS_VSUBSS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1812, + .Mnemonic = 1847, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -112878,6 +118248,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -112893,12 +118264,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4026 Instruction:"VSUBSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5C /r"/"RVM" + // Pos:4073 Instruction:"VSUBSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5C /r"/"RVM" { .Instruction = ND_INS_VSUBSS, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1812, + .Mnemonic = 1847, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -112907,6 +118278,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_2, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -112921,12 +118293,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4027 Instruction:"VTESTPD Vx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0F /r"/"RM" + // Pos:4074 Instruction:"VTESTPD Vx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0F /r"/"RM" { .Instruction = ND_INS_VTESTPD, .Category = ND_CAT_LOGICAL_FP, .IsaSet = ND_SET_AVX, - .Mnemonic = 1813, + .Mnemonic = 1848, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -112935,6 +118307,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .SetFlags = 0, @@ -112949,12 +118322,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4028 Instruction:"VTESTPS Vx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0E /r"/"RM" + // Pos:4075 Instruction:"VTESTPS Vx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0E /r"/"RM" { .Instruction = ND_INS_VTESTPS, .Category = ND_CAT_LOGICAL_FP, .IsaSet = ND_SET_AVX, - .Mnemonic = 1814, + .Mnemonic = 1849, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -112963,6 +118336,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .SetFlags = 0, @@ -112977,12 +118351,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4029 Instruction:"VUCOMISD Vdq,Wsd{sae}" Encoding:"evex m:1 p:1 l:i w:1 0x2E /r"/"RM" + // Pos:4076 Instruction:"VUCOMISD Vdq,Wsd{sae}" Encoding:"evex m:1 p:1 l:i w:1 0x2E /r"/"RM" { .Instruction = ND_INS_VUCOMISD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1815, + .Mnemonic = 1850, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_SAE, @@ -112991,6 +118365,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, .SetFlags = 0, @@ -113005,12 +118380,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4030 Instruction:"VUCOMISD Vsd,Wsd" Encoding:"vex m:1 p:1 l:i w:i 0x2E /r"/"RM" + // Pos:4077 Instruction:"VUCOMISD Vsd,Wsd" Encoding:"vex m:1 p:1 l:i w:i 0x2E /r"/"RM" { .Instruction = ND_INS_VUCOMISD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1815, + .Mnemonic = 1850, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -113019,6 +118394,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, .SetFlags = 0, @@ -113033,12 +118409,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4031 Instruction:"VUCOMISH Vdq,Wsh{sae}" Encoding:"evex m:5 p:0 l:i w:0 0x2E /r"/"RM" + // Pos:4078 Instruction:"VUCOMISH Vdq,Wsh{sae}" Encoding:"evex m:5 p:0 l:i w:0 0x2E /r"/"RM" { .Instruction = ND_INS_VUCOMISH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1816, + .Mnemonic = 1851, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_SAE, @@ -113047,6 +118423,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_ZF|NDR_RFLAG_PF|NDR_RFLAG_CF, .SetFlags = 0, @@ -113061,12 +118438,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4032 Instruction:"VUCOMISS Vdq,Wss{sae}" Encoding:"evex m:1 p:0 l:i w:0 0x2E /r"/"RM" + // Pos:4079 Instruction:"VUCOMISS Vdq,Wss{sae}" Encoding:"evex m:1 p:0 l:i w:0 0x2E /r"/"RM" { .Instruction = ND_INS_VUCOMISS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1817, + .Mnemonic = 1852, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_SAE, @@ -113075,6 +118452,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, .SetFlags = 0, @@ -113089,12 +118467,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4033 Instruction:"VUCOMISS Vss,Wss" Encoding:"vex m:1 p:0 l:i w:i 0x2E /r"/"RM" + // Pos:4080 Instruction:"VUCOMISS Vss,Wss" Encoding:"vex m:1 p:0 l:i w:i 0x2E /r"/"RM" { .Instruction = ND_INS_VUCOMISS, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1817, + .Mnemonic = 1852, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -113103,6 +118481,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_3, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, .SetFlags = 0, @@ -113117,12 +118496,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4034 Instruction:"VUCOMXSD Vdq,Wsd{sae}" Encoding:"evex m:1 p:2 l:0 w:1 0x2E /r"/"RM" + // Pos:4081 Instruction:"VUCOMXSD Vdq,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:1 0x2E /r"/"RM" { .Instruction = ND_INS_VUCOMXSD, .Category = ND_CAT_AVX10CMPSFP, .IsaSet = ND_SET_AVX102, - .Mnemonic = 1818, + .Mnemonic = 1853, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_SAE, @@ -113131,11 +118510,12 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, .ClearedFlags = 0|NDR_RFLAG_AF, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, .CpuidFlag = 0, .Operands = { @@ -113145,12 +118525,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4035 Instruction:"VUCOMXSH Vdq,Wsh{sae}" Encoding:"evex m:5 p:3 l:0 w:0 0x2E /r"/"RM" + // Pos:4082 Instruction:"VUCOMXSH Vdq,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:0 0x2E /r"/"RM" { .Instruction = ND_INS_VUCOMXSH, .Category = ND_CAT_AVX10CMPSFP, .IsaSet = ND_SET_AVX102, - .Mnemonic = 1819, + .Mnemonic = 1854, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_SAE, @@ -113159,11 +118539,12 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, .ClearedFlags = 0|NDR_RFLAG_AF, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, .CpuidFlag = 0, .Operands = { @@ -113173,12 +118554,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4036 Instruction:"VUCOMXSS Vdq,Wss{sae}" Encoding:"evex m:1 p:3 l:0 w:0 0x2E /r"/"RM" + // Pos:4083 Instruction:"VUCOMXSS Vdq,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:0 0x2E /r"/"RM" { .Instruction = ND_INS_VUCOMXSS, .Category = ND_CAT_AVX10CMPSFP, .IsaSet = ND_SET_AVX102, - .Mnemonic = 1820, + .Mnemonic = 1855, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_SAE, @@ -113187,11 +118568,12 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E3NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, .ClearedFlags = 0|NDR_RFLAG_AF, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, .CpuidFlag = 0, .Operands = { @@ -113201,12 +118583,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4037 Instruction:"VUNPCKHPD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0x15 /r"/"RAVM" + // Pos:4084 Instruction:"VUNPCKHPD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0x15 /r"/"RAVM" { .Instruction = ND_INS_VUNPCKHPD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1821, + .Mnemonic = 1856, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -113215,6 +118597,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -113230,12 +118613,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4038 Instruction:"VUNPCKHPD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x15 /r"/"RVM" + // Pos:4085 Instruction:"VUNPCKHPD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x15 /r"/"RVM" { .Instruction = ND_INS_VUNPCKHPD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1821, + .Mnemonic = 1856, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -113244,6 +118627,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -113258,12 +118642,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4039 Instruction:"VUNPCKHPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:0 l:x w:0 0x15 /r"/"RAVM" + // Pos:4086 Instruction:"VUNPCKHPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:0 l:x w:0 0x15 /r"/"RAVM" { .Instruction = ND_INS_VUNPCKHPS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1822, + .Mnemonic = 1857, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -113272,6 +118656,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -113287,12 +118672,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4040 Instruction:"VUNPCKHPS Vx,Hx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x15 /r"/"RVM" + // Pos:4087 Instruction:"VUNPCKHPS Vx,Hx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x15 /r"/"RVM" { .Instruction = ND_INS_VUNPCKHPS, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1822, + .Mnemonic = 1857, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -113301,6 +118686,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -113315,12 +118701,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4041 Instruction:"VUNPCKLPD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0x14 /r"/"RAVM" + // Pos:4088 Instruction:"VUNPCKLPD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0x14 /r"/"RAVM" { .Instruction = ND_INS_VUNPCKLPD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1823, + .Mnemonic = 1858, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -113329,6 +118715,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -113344,12 +118731,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4042 Instruction:"VUNPCKLPD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x14 /r"/"RVM" + // Pos:4089 Instruction:"VUNPCKLPD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x14 /r"/"RVM" { .Instruction = ND_INS_VUNPCKLPD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1823, + .Mnemonic = 1858, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -113358,6 +118745,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -113372,12 +118760,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4043 Instruction:"VUNPCKLPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:0 l:x w:0 0x14 /r"/"RAVM" + // Pos:4090 Instruction:"VUNPCKLPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:0 l:x w:0 0x14 /r"/"RAVM" { .Instruction = ND_INS_VUNPCKLPS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1824, + .Mnemonic = 1859, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -113386,6 +118774,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4NF, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -113401,12 +118790,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4044 Instruction:"VUNPCKLPS Vx,Hx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x14 /r"/"RVM" + // Pos:4091 Instruction:"VUNPCKLPS Vx,Hx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x14 /r"/"RVM" { .Instruction = ND_INS_VUNPCKLPS, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1824, + .Mnemonic = 1859, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -113415,6 +118804,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -113429,12 +118819,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4045 Instruction:"VXORPD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0x57 /r"/"RAVM" + // Pos:4092 Instruction:"VXORPD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0x57 /r"/"RAVM" { .Instruction = ND_INS_VXORPD, .Category = ND_CAT_LOGICAL_FP, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 1825, + .Mnemonic = 1860, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -113443,6 +118833,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -113458,12 +118849,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4046 Instruction:"VXORPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x57 /r"/"RVM" + // Pos:4093 Instruction:"VXORPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x57 /r"/"RVM" { .Instruction = ND_INS_VXORPD, .Category = ND_CAT_LOGICAL_FP, .IsaSet = ND_SET_AVX, - .Mnemonic = 1825, + .Mnemonic = 1860, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -113472,6 +118863,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -113486,12 +118878,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4047 Instruction:"VXORPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:0 l:x w:0 0x57 /r"/"RAVM" + // Pos:4094 Instruction:"VXORPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:0 l:x w:0 0x57 /r"/"RAVM" { .Instruction = ND_INS_VXORPS, .Category = ND_CAT_LOGICAL_FP, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 1826, + .Mnemonic = 1861, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -113500,6 +118892,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -113515,12 +118908,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4048 Instruction:"VXORPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x57 /r"/"RVM" + // Pos:4095 Instruction:"VXORPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x57 /r"/"RVM" { .Instruction = ND_INS_VXORPS, .Category = ND_CAT_LOGICAL_FP, .IsaSet = ND_SET_AVX, - .Mnemonic = 1826, + .Mnemonic = 1861, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -113529,6 +118922,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -113543,12 +118937,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4049 Instruction:"VZEROALL" Encoding:"vex m:1 p:0 l:1 0x77"/"" + // Pos:4096 Instruction:"VZEROALL" Encoding:"vex m:1 p:0 l:1 0x77"/"" { .Instruction = ND_INS_VZEROALL, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1827, + .Mnemonic = 1862, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -113557,6 +118951,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_8, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -113569,12 +118964,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4050 Instruction:"VZEROUPPER" Encoding:"vex m:1 p:0 l:0 0x77"/"" + // Pos:4097 Instruction:"VZEROUPPER" Encoding:"vex m:1 p:0 l:0 0x77"/"" { .Instruction = ND_INS_VZEROUPPER, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1828, + .Mnemonic = 1863, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -113583,6 +118978,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_8, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -113595,12 +118991,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4051 Instruction:"WAIT" Encoding:"0x9B"/"" + // Pos:4098 Instruction:"WAIT" Encoding:"0x9B"/"" { .Instruction = ND_INS_WAIT, .Category = ND_CAT_X87_ALU, .IsaSet = ND_SET_X87, - .Mnemonic = 1829, + .Mnemonic = 1864, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -113609,6 +119005,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0xff, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -113621,12 +119018,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4052 Instruction:"WBINVD" Encoding:"0x0F 0x09"/"" + // Pos:4099 Instruction:"WBINVD" Encoding:"0x0F 0x09"/"" { .Instruction = ND_INS_WBINVD, .Category = ND_CAT_SYSTEM, .IsaSet = ND_SET_I486REAL, - .Mnemonic = 1830, + .Mnemonic = 1865, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -113635,6 +119032,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -113647,12 +119045,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4053 Instruction:"WBNOINVD" Encoding:"repz 0x0F 0x09"/"" + // Pos:4100 Instruction:"WBNOINVD" Encoding:"repz 0x0F 0x09"/"" { .Instruction = ND_INS_WBNOINVD, .Category = ND_CAT_WBNOINVD, .IsaSet = ND_SET_WBNOINVD, - .Mnemonic = 1831, + .Mnemonic = 1866, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -113661,6 +119059,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -113673,12 +119072,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4054 Instruction:"WRFSBASE Ry" Encoding:"mo64 0xF3 0x0F 0xAE /2:reg"/"M" + // Pos:4101 Instruction:"WRFSBASE Ry" Encoding:"mo64 0xF3 0x0F 0xAE /2:reg"/"M" { .Instruction = ND_INS_WRFSBASE, .Category = ND_CAT_RDWRFSGS, .IsaSet = ND_SET_RDWRFSGS, - .Mnemonic = 1832, + .Mnemonic = 1867, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -113687,6 +119086,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -113700,12 +119100,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4055 Instruction:"WRGSBASE Ry" Encoding:"mo64 0xF3 0x0F 0xAE /3:reg"/"M" + // Pos:4102 Instruction:"WRGSBASE Ry" Encoding:"mo64 0xF3 0x0F 0xAE /3:reg"/"M" { .Instruction = ND_INS_WRGSBASE, .Category = ND_CAT_RDWRFSGS, .IsaSet = ND_SET_RDWRFSGS, - .Mnemonic = 1833, + .Mnemonic = 1868, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -113714,6 +119114,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -113727,12 +119128,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4056 Instruction:"WRMSR" Encoding:"0x0F 0x30"/"" + // Pos:4103 Instruction:"WRMSR" Encoding:"0x0F 0x30"/"" { .Instruction = ND_INS_WRMSR, .Category = ND_CAT_SYSTEM, .IsaSet = ND_SET_PENTIUMREAL, - .Mnemonic = 1834, + .Mnemonic = 1869, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -113741,6 +119142,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -113756,12 +119158,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4057 Instruction:"WRMSRLIST" Encoding:"0xF3 0x0F 0x01 /0xC6"/"" + // Pos:4104 Instruction:"WRMSRLIST" Encoding:"0xF3 0x0F 0x01 /0xC6"/"" { .Instruction = ND_INS_WRMSRLIST, .Category = ND_CAT_SYSTEM, .IsaSet = ND_SET_MSRLIST, - .Mnemonic = 1835, + .Mnemonic = 1870, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -113770,6 +119172,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -113784,12 +119187,41 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4058 Instruction:"WRMSRNS" Encoding:"NP 0x0F 0x01 /0xC6"/"" + // Pos:4105 Instruction:"WRMSRNS Id,Rq" Encoding:"evex m:7 nf:0 p:2 l:0 w:0 0xF6 /0:reg id"/"IM" + { + .Instruction = ND_INS_WRMSRNS, + .Category = ND_CAT_SYSTEM, + .IsaSet = ND_SET_MSR_IMM, + .Mnemonic = 1871, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_VEX, + .SimdExc = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP|ND_FLAG_O64, + .CpuidFlag = ND_CFF_MSR_IMM, + .Operands = + { + OP(ND_OPT_I, ND_OPS_d, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_R, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_MSR, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:4106 Instruction:"WRMSRNS" Encoding:"NP 0x0F 0x01 /0xC6"/"" { .Instruction = ND_INS_WRMSRNS, .Category = ND_CAT_SYSTEM, .IsaSet = ND_SET_WRMSRNS, - .Mnemonic = 1836, + .Mnemonic = 1871, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -113798,6 +119230,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -113813,12 +119246,41 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4059 Instruction:"WRPKRU" Encoding:"NP 0x0F 0x01 /0xEF"/"" + // Pos:4107 Instruction:"WRMSRNS Id,Rq" Encoding:"vex m:7 p:2 l:0 w:0 0xF6 /0:reg id"/"IM" + { + .Instruction = ND_INS_WRMSRNS, + .Category = ND_CAT_SYSTEM, + .IsaSet = ND_SET_MSR_IMM, + .Mnemonic = 1871, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .SimdExc = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_O64, + .CpuidFlag = ND_CFF_MSR_IMM, + .Operands = + { + OP(ND_OPT_I, ND_OPS_d, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_R, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_MSR, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:4108 Instruction:"WRPKRU" Encoding:"NP 0x0F 0x01 /0xEF"/"" { .Instruction = ND_INS_WRPKRU, .Category = ND_CAT_MISC, .IsaSet = ND_SET_PKU, - .Mnemonic = 1837, + .Mnemonic = 1872, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -113827,6 +119289,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -113842,12 +119305,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4060 Instruction:"WRSSD My,Gy" Encoding:"evex m:4 l:0 p:0 w:0 nd:0 nf:0 0x66 /r:mem"/"MR" + // Pos:4109 Instruction:"WRSSD My,Gy" Encoding:"evex m:4 l:0 p:0 w:0 nd:0 nf:0 0x66 /r:mem"/"MR" { .Instruction = ND_INS_WRSS, .Category = ND_CAT_CET, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1838, + .Mnemonic = 1873, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -113856,6 +119319,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_WRSS, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -113869,12 +119333,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4061 Instruction:"WRSSD My,Gy" Encoding:"NP 0x0F 0x38 0xF6 /r:mem"/"MR" + // Pos:4110 Instruction:"WRSSD My,Gy" Encoding:"NP 0x0F 0x38 0xF6 /r:mem"/"MR" { .Instruction = ND_INS_WRSS, .Category = ND_CAT_CET, .IsaSet = ND_SET_CET_SS, - .Mnemonic = 1838, + .Mnemonic = 1873, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -113883,6 +119347,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -113896,12 +119361,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4062 Instruction:"WRSSQ My,Gy" Encoding:"evex m:4 l:0 p:0 w:1 nd:0 nf:0 0x66 /r:mem"/"MR" + // Pos:4111 Instruction:"WRSSQ My,Gy" Encoding:"evex m:4 l:0 p:0 w:1 nd:0 nf:0 0x66 /r:mem"/"MR" { .Instruction = ND_INS_WRSS, .Category = ND_CAT_CET, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1839, + .Mnemonic = 1874, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -113910,6 +119375,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_WRSS, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -113923,12 +119389,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4063 Instruction:"WRSSQ My,Gy" Encoding:"rexw NP 0x0F 0x38 0xF6 /r:mem"/"MR" + // Pos:4112 Instruction:"WRSSQ My,Gy" Encoding:"rexw NP 0x0F 0x38 0xF6 /r:mem"/"MR" { .Instruction = ND_INS_WRSS, .Category = ND_CAT_CET, .IsaSet = ND_SET_CET_SS, - .Mnemonic = 1839, + .Mnemonic = 1874, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -113937,6 +119403,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -113950,12 +119417,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4064 Instruction:"WRUSSD My,Gy" Encoding:"evex m:4 l:0 p:1 w:0 nd:0 nf:0 0x65 /r:mem"/"MR" + // Pos:4113 Instruction:"WRUSSD My,Gy" Encoding:"evex m:4 l:0 p:1 w:0 nd:0 nf:0 0x65 /r:mem"/"MR" { .Instruction = ND_INS_WRUSS, .Category = ND_CAT_CET, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1840, + .Mnemonic = 1875, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -113964,6 +119431,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_WRUSS, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -113977,12 +119445,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4065 Instruction:"WRUSSD My,Gy" Encoding:"0x66 0x0F 0x38 0xF5 /r:mem"/"MR" + // Pos:4114 Instruction:"WRUSSD My,Gy" Encoding:"0x66 0x0F 0x38 0xF5 /r:mem"/"MR" { .Instruction = ND_INS_WRUSS, .Category = ND_CAT_CET, .IsaSet = ND_SET_CET_SS, - .Mnemonic = 1840, + .Mnemonic = 1875, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -113991,6 +119459,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -114004,12 +119473,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4066 Instruction:"WRUSSQ My,Gy" Encoding:"evex m:4 l:0 p:1 w:1 nd:0 nf:0 0x65 /r:mem"/"MR" + // Pos:4115 Instruction:"WRUSSQ My,Gy" Encoding:"evex m:4 l:0 p:1 w:1 nd:0 nf:0 0x65 /r:mem"/"MR" { .Instruction = ND_INS_WRUSS, .Category = ND_CAT_CET, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1841, + .Mnemonic = 1876, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -114018,6 +119487,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_WRUSS, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -114031,12 +119501,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4067 Instruction:"WRUSSQ My,Gy" Encoding:"rexw 0x66 0x0F 0x38 0xF5 /r:mem"/"MR" + // Pos:4116 Instruction:"WRUSSQ My,Gy" Encoding:"rexw 0x66 0x0F 0x38 0xF5 /r:mem"/"MR" { .Instruction = ND_INS_WRUSS, .Category = ND_CAT_CET, .IsaSet = ND_SET_CET_SS, - .Mnemonic = 1841, + .Mnemonic = 1876, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -114045,6 +119515,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -114058,12 +119529,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4068 Instruction:"XABORT Ib" Encoding:"0xC6 /0xF8 ib"/"I" + // Pos:4117 Instruction:"XABORT Ib" Encoding:"0xC6 /0xF8 ib"/"I" { .Instruction = ND_INS_XABORT, .Category = ND_CAT_UNCOND_BR, .IsaSet = ND_SET_TSX, - .Mnemonic = 1842, + .Mnemonic = 1877, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -114072,6 +119543,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -114086,12 +119558,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4069 Instruction:"XADD Eb,Gb" Encoding:"0x0F 0xC0 /r"/"MR" + // Pos:4118 Instruction:"XADD Eb,Gb" Encoding:"0x0F 0xC0 /r"/"MR" { .Instruction = ND_INS_XADD, .Category = ND_CAT_SEMAPHORE, .IsaSet = ND_SET_I486REAL, - .Mnemonic = 1843, + .Mnemonic = 1878, .ValidPrefixes = ND_PREF_LOCK|ND_PREF_HLE, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -114100,6 +119572,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -114114,12 +119587,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4070 Instruction:"XADD Ev,Gv" Encoding:"0x0F 0xC1 /r"/"MR" + // Pos:4119 Instruction:"XADD Ev,Gv" Encoding:"0x0F 0xC1 /r"/"MR" { .Instruction = ND_INS_XADD, .Category = ND_CAT_SEMAPHORE, .IsaSet = ND_SET_I486REAL, - .Mnemonic = 1843, + .Mnemonic = 1878, .ValidPrefixes = ND_PREF_LOCK|ND_PREF_HLE, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -114128,6 +119601,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, .SetFlags = 0, @@ -114142,12 +119616,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4071 Instruction:"XBEGIN Jz" Encoding:"0xC7 /0xF8 cz"/"D" + // Pos:4120 Instruction:"XBEGIN Jz" Encoding:"0xC7 /0xF8 cz"/"D" { .Instruction = ND_INS_XBEGIN, .Category = ND_CAT_COND_BR, .IsaSet = ND_SET_TSX, - .Mnemonic = 1844, + .Mnemonic = 1879, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -114156,6 +119630,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -114170,12 +119645,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4072 Instruction:"XCHG Eb,Gb" Encoding:"0x86 /r"/"MR" + // Pos:4121 Instruction:"XCHG Eb,Gb" Encoding:"0x86 /r"/"MR" { .Instruction = ND_INS_XCHG, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_I86, - .Mnemonic = 1845, + .Mnemonic = 1880, .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK|ND_PREF_HLEWOL, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -114184,6 +119659,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -114197,12 +119673,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4073 Instruction:"XCHG Ev,Gv" Encoding:"0x87 /r"/"MR" + // Pos:4122 Instruction:"XCHG Ev,Gv" Encoding:"0x87 /r"/"MR" { .Instruction = ND_INS_XCHG, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_I86, - .Mnemonic = 1845, + .Mnemonic = 1880, .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK|ND_PREF_HLEWOL, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -114211,6 +119687,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -114224,12 +119701,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4074 Instruction:"XCHG Zv,rAX" Encoding:"rexb 0x90"/"O" + // Pos:4123 Instruction:"XCHG Zv,rAX" Encoding:"rexb 0x90"/"O" { .Instruction = ND_INS_XCHG, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_I86, - .Mnemonic = 1845, + .Mnemonic = 1880, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -114238,6 +119715,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -114251,12 +119729,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4075 Instruction:"XCHG Zv,rAX" Encoding:"0x91"/"O" + // Pos:4124 Instruction:"XCHG Zv,rAX" Encoding:"0x91"/"O" { .Instruction = ND_INS_XCHG, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_I86, - .Mnemonic = 1845, + .Mnemonic = 1880, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -114265,6 +119743,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -114278,12 +119757,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4076 Instruction:"XCHG Zv,rAX" Encoding:"0x92"/"O" + // Pos:4125 Instruction:"XCHG Zv,rAX" Encoding:"0x92"/"O" { .Instruction = ND_INS_XCHG, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_I86, - .Mnemonic = 1845, + .Mnemonic = 1880, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -114292,6 +119771,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -114305,12 +119785,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4077 Instruction:"XCHG Zv,rAX" Encoding:"0x93"/"O" + // Pos:4126 Instruction:"XCHG Zv,rAX" Encoding:"0x93"/"O" { .Instruction = ND_INS_XCHG, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_I86, - .Mnemonic = 1845, + .Mnemonic = 1880, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -114319,6 +119799,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -114332,12 +119813,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4078 Instruction:"XCHG Zv,rAX" Encoding:"0x94"/"O" + // Pos:4127 Instruction:"XCHG Zv,rAX" Encoding:"0x94"/"O" { .Instruction = ND_INS_XCHG, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_I86, - .Mnemonic = 1845, + .Mnemonic = 1880, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -114346,6 +119827,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -114359,12 +119841,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4079 Instruction:"XCHG Zv,rAX" Encoding:"0x95"/"O" + // Pos:4128 Instruction:"XCHG Zv,rAX" Encoding:"0x95"/"O" { .Instruction = ND_INS_XCHG, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_I86, - .Mnemonic = 1845, + .Mnemonic = 1880, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -114373,6 +119855,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -114386,12 +119869,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4080 Instruction:"XCHG Zv,rAX" Encoding:"0x96"/"O" + // Pos:4129 Instruction:"XCHG Zv,rAX" Encoding:"0x96"/"O" { .Instruction = ND_INS_XCHG, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_I86, - .Mnemonic = 1845, + .Mnemonic = 1880, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -114400,6 +119883,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -114413,12 +119897,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4081 Instruction:"XCHG Zv,rAX" Encoding:"0x97"/"O" + // Pos:4130 Instruction:"XCHG Zv,rAX" Encoding:"0x97"/"O" { .Instruction = ND_INS_XCHG, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_I86, - .Mnemonic = 1845, + .Mnemonic = 1880, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -114427,6 +119911,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -114440,12 +119925,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4082 Instruction:"XEND" Encoding:"NP 0x0F 0x01 /0xD5"/"" + // Pos:4131 Instruction:"XEND" Encoding:"NP 0x0F 0x01 /0xD5"/"" { .Instruction = ND_INS_XEND, .Category = ND_CAT_COND_BR, .IsaSet = ND_SET_TSX, - .Mnemonic = 1846, + .Mnemonic = 1881, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -114454,6 +119939,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -114466,12 +119952,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4083 Instruction:"XGETBV" Encoding:"NP 0x0F 0x01 /0xD0"/"" + // Pos:4132 Instruction:"XGETBV" Encoding:"NP 0x0F 0x01 /0xD0"/"" { .Instruction = ND_INS_XGETBV, .Category = ND_CAT_XSAVE, .IsaSet = ND_SET_XSAVE, - .Mnemonic = 1847, + .Mnemonic = 1882, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -114480,6 +119966,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -114495,12 +119982,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4084 Instruction:"XLATB" Encoding:"0xD7"/"" + // Pos:4133 Instruction:"XLATB" Encoding:"0xD7"/"" { .Instruction = ND_INS_XLATB, .Category = ND_CAT_MISC, .IsaSet = ND_SET_I86, - .Mnemonic = 1848, + .Mnemonic = 1883, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -114509,6 +119996,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -114522,12 +120010,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4085 Instruction:"XOR Eb,Gb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x30 /r"/"MR" + // Pos:4134 Instruction:"XOR Eb,Gb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x30 /r"/"MR" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1849, + .Mnemonic = 1884, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -114536,6 +120024,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -114550,12 +120039,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4086 Instruction:"XOR Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x31 /r"/"MR" + // Pos:4135 Instruction:"XOR Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x31 /r"/"MR" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1849, + .Mnemonic = 1884, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -114564,6 +120053,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -114578,12 +120068,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4087 Instruction:"XOR Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x31 /r"/"MR" + // Pos:4136 Instruction:"XOR Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x31 /r"/"MR" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1849, + .Mnemonic = 1884, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -114592,6 +120082,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -114606,12 +120097,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4088 Instruction:"XOR Gb,Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x32 /r"/"RM" + // Pos:4137 Instruction:"XOR Gb,Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x32 /r"/"RM" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1849, + .Mnemonic = 1884, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -114620,6 +120111,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -114634,12 +120126,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4089 Instruction:"XOR Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x33 /r"/"RM" + // Pos:4138 Instruction:"XOR Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x33 /r"/"RM" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1849, + .Mnemonic = 1884, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -114648,6 +120140,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -114662,12 +120155,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4090 Instruction:"XOR Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x33 /r"/"RM" + // Pos:4139 Instruction:"XOR Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x33 /r"/"RM" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1849, + .Mnemonic = 1884, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -114676,6 +120169,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -114690,12 +120184,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4091 Instruction:"XOR Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x80 /6 ib"/"MI" + // Pos:4140 Instruction:"XOR Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x80 /6 ib"/"MI" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1849, + .Mnemonic = 1884, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -114704,6 +120198,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -114718,12 +120213,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4092 Instruction:"XOR Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x81 /6 iz"/"MI" + // Pos:4141 Instruction:"XOR Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x81 /6 iz"/"MI" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1849, + .Mnemonic = 1884, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -114732,6 +120227,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -114746,12 +120242,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4093 Instruction:"XOR Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x81 /6 iz"/"MI" + // Pos:4142 Instruction:"XOR Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x81 /6 iz"/"MI" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1849, + .Mnemonic = 1884, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -114760,6 +120256,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -114774,12 +120271,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4094 Instruction:"XOR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x83 /6 ib"/"MI" + // Pos:4143 Instruction:"XOR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x83 /6 ib"/"MI" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1849, + .Mnemonic = 1884, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -114788,6 +120285,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -114802,12 +120300,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4095 Instruction:"XOR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x83 /6 ib"/"MI" + // Pos:4144 Instruction:"XOR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x83 /6 ib"/"MI" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1849, + .Mnemonic = 1884, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -114816,6 +120314,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -114830,12 +120329,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4096 Instruction:"XOR Eb,Gb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x30 /r"/"MR" + // Pos:4145 Instruction:"XOR Eb,Gb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x30 /r"/"MR" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1849, + .Mnemonic = 1884, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -114844,6 +120343,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -114857,12 +120357,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4097 Instruction:"XOR Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x31 /r"/"MR" + // Pos:4146 Instruction:"XOR Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x31 /r"/"MR" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1849, + .Mnemonic = 1884, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -114871,6 +120371,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -114884,12 +120385,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4098 Instruction:"XOR Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x31 /r"/"MR" + // Pos:4147 Instruction:"XOR Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x31 /r"/"MR" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1849, + .Mnemonic = 1884, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -114898,6 +120399,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -114911,12 +120413,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4099 Instruction:"XOR Gb,Eb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x32 /r"/"RM" + // Pos:4148 Instruction:"XOR Gb,Eb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x32 /r"/"RM" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1849, + .Mnemonic = 1884, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -114925,6 +120427,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -114938,12 +120441,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4100 Instruction:"XOR Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x33 /r"/"RM" + // Pos:4149 Instruction:"XOR Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x33 /r"/"RM" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1849, + .Mnemonic = 1884, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -114952,6 +120455,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -114965,12 +120469,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4101 Instruction:"XOR Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x33 /r"/"RM" + // Pos:4150 Instruction:"XOR Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x33 /r"/"RM" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1849, + .Mnemonic = 1884, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -114979,6 +120483,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -114992,12 +120497,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4102 Instruction:"XOR Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x80 /6 ib"/"MI" + // Pos:4151 Instruction:"XOR Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x80 /6 ib"/"MI" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1849, + .Mnemonic = 1884, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -115006,6 +120511,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -115019,12 +120525,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4103 Instruction:"XOR Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x81 /6 iz"/"MI" + // Pos:4152 Instruction:"XOR Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x81 /6 iz"/"MI" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1849, + .Mnemonic = 1884, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -115033,6 +120539,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -115046,12 +120553,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4104 Instruction:"XOR Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x81 /6 iz"/"MI" + // Pos:4153 Instruction:"XOR Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x81 /6 iz"/"MI" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1849, + .Mnemonic = 1884, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -115060,6 +120567,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -115073,12 +120581,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4105 Instruction:"XOR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x83 /6 ib"/"MI" + // Pos:4154 Instruction:"XOR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x83 /6 ib"/"MI" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1849, + .Mnemonic = 1884, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -115087,6 +120595,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -115100,12 +120609,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4106 Instruction:"XOR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x83 /6 ib"/"MI" + // Pos:4155 Instruction:"XOR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x83 /6 ib"/"MI" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1849, + .Mnemonic = 1884, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -115114,6 +120623,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -115127,12 +120637,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4107 Instruction:"XOR Bb,Eb,Gb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x30 /r"/"VMR" + // Pos:4156 Instruction:"XOR Bb,Eb,Gb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x30 /r"/"VMR" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1849, + .Mnemonic = 1884, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -115141,6 +120651,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -115156,12 +120667,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4108 Instruction:"XOR Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x31 /r"/"VMR" + // Pos:4157 Instruction:"XOR Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x31 /r"/"VMR" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1849, + .Mnemonic = 1884, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -115170,6 +120681,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -115185,12 +120697,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4109 Instruction:"XOR Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x31 /r"/"VMR" + // Pos:4158 Instruction:"XOR Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x31 /r"/"VMR" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1849, + .Mnemonic = 1884, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -115199,6 +120711,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -115214,12 +120727,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4110 Instruction:"XOR Bb,Gb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x32 /r"/"VRM" + // Pos:4159 Instruction:"XOR Bb,Gb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x32 /r"/"VRM" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1849, + .Mnemonic = 1884, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -115228,6 +120741,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -115243,12 +120757,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4111 Instruction:"XOR Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x33 /r"/"VRM" + // Pos:4160 Instruction:"XOR Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x33 /r"/"VRM" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1849, + .Mnemonic = 1884, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -115257,6 +120771,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -115272,12 +120787,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4112 Instruction:"XOR Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x33 /r"/"VRM" + // Pos:4161 Instruction:"XOR Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x33 /r"/"VRM" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1849, + .Mnemonic = 1884, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -115286,6 +120801,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -115301,12 +120817,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4113 Instruction:"XOR Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x80 /6 ib"/"VMI" + // Pos:4162 Instruction:"XOR Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x80 /6 ib"/"VMI" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1849, + .Mnemonic = 1884, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -115315,6 +120831,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -115330,12 +120847,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4114 Instruction:"XOR Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x81 /6 iz"/"VMI" + // Pos:4163 Instruction:"XOR Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x81 /6 iz"/"VMI" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1849, + .Mnemonic = 1884, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -115344,6 +120861,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -115359,12 +120877,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4115 Instruction:"XOR Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x81 /6 iz"/"VMI" + // Pos:4164 Instruction:"XOR Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x81 /6 iz"/"VMI" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1849, + .Mnemonic = 1884, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -115373,6 +120891,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -115388,12 +120907,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4116 Instruction:"XOR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x83 /6 ib"/"VMI" + // Pos:4165 Instruction:"XOR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x83 /6 ib"/"VMI" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1849, + .Mnemonic = 1884, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -115402,6 +120921,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -115417,12 +120937,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4117 Instruction:"XOR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x83 /6 ib"/"VMI" + // Pos:4166 Instruction:"XOR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x83 /6 ib"/"VMI" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1849, + .Mnemonic = 1884, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -115431,6 +120951,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -115446,12 +120967,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4118 Instruction:"XOR Bb,Eb,Gb" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x30 /r"/"VMR" + // Pos:4167 Instruction:"XOR Bb,Eb,Gb" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x30 /r"/"VMR" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1849, + .Mnemonic = 1884, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -115460,6 +120981,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -115474,12 +120996,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4119 Instruction:"XOR Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x31 /r"/"VMR" + // Pos:4168 Instruction:"XOR Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x31 /r"/"VMR" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1849, + .Mnemonic = 1884, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -115488,6 +121010,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -115502,12 +121025,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4120 Instruction:"XOR Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x31 /r"/"VMR" + // Pos:4169 Instruction:"XOR Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x31 /r"/"VMR" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1849, + .Mnemonic = 1884, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -115516,6 +121039,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -115530,12 +121054,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4121 Instruction:"XOR Bb,Gb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x32 /r"/"VRM" + // Pos:4170 Instruction:"XOR Bb,Gb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x32 /r"/"VRM" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1849, + .Mnemonic = 1884, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -115544,6 +121068,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -115558,12 +121083,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4122 Instruction:"XOR Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x33 /r"/"VRM" + // Pos:4171 Instruction:"XOR Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x33 /r"/"VRM" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1849, + .Mnemonic = 1884, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -115572,6 +121097,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -115586,12 +121112,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4123 Instruction:"XOR Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x33 /r"/"VRM" + // Pos:4172 Instruction:"XOR Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x33 /r"/"VRM" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1849, + .Mnemonic = 1884, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -115600,6 +121126,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -115614,12 +121141,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4124 Instruction:"XOR Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x80 /6 ib"/"VMI" + // Pos:4173 Instruction:"XOR Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x80 /6 ib"/"VMI" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1849, + .Mnemonic = 1884, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -115628,6 +121155,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -115642,12 +121170,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4125 Instruction:"XOR Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x81 /6 iz"/"VMI" + // Pos:4174 Instruction:"XOR Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x81 /6 iz"/"VMI" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1849, + .Mnemonic = 1884, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -115656,6 +121184,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -115670,12 +121199,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4126 Instruction:"XOR Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x81 /6 iz"/"VMI" + // Pos:4175 Instruction:"XOR Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x81 /6 iz"/"VMI" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1849, + .Mnemonic = 1884, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -115684,6 +121213,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -115698,12 +121228,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4127 Instruction:"XOR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x83 /6 ib"/"VMI" + // Pos:4176 Instruction:"XOR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x83 /6 ib"/"VMI" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1849, + .Mnemonic = 1884, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -115712,6 +121242,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -115726,12 +121257,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4128 Instruction:"XOR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x83 /6 ib"/"VMI" + // Pos:4177 Instruction:"XOR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x83 /6 ib"/"VMI" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1849, + .Mnemonic = 1884, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -115740,6 +121271,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -115754,12 +121286,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4129 Instruction:"XOR Eb,Gb" Encoding:"0x30 /r"/"MR" + // Pos:4178 Instruction:"XOR Eb,Gb" Encoding:"0x30 /r"/"MR" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_I86, - .Mnemonic = 1849, + .Mnemonic = 1884, .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -115768,6 +121300,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -115782,12 +121315,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4130 Instruction:"XOR Ev,Gv" Encoding:"0x31 /r"/"MR" + // Pos:4179 Instruction:"XOR Ev,Gv" Encoding:"0x31 /r"/"MR" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_I86, - .Mnemonic = 1849, + .Mnemonic = 1884, .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -115796,6 +121329,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -115810,12 +121344,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4131 Instruction:"XOR Gb,Eb" Encoding:"0x32 /r"/"RM" + // Pos:4180 Instruction:"XOR Gb,Eb" Encoding:"0x32 /r"/"RM" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_I86, - .Mnemonic = 1849, + .Mnemonic = 1884, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -115824,6 +121358,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -115838,12 +121373,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4132 Instruction:"XOR Gv,Ev" Encoding:"0x33 /r"/"RM" + // Pos:4181 Instruction:"XOR Gv,Ev" Encoding:"0x33 /r"/"RM" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_I86, - .Mnemonic = 1849, + .Mnemonic = 1884, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -115852,6 +121387,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -115866,12 +121402,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4133 Instruction:"XOR AL,Ib" Encoding:"0x34 ib"/"I" + // Pos:4182 Instruction:"XOR AL,Ib" Encoding:"0x34 ib"/"I" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_I86, - .Mnemonic = 1849, + .Mnemonic = 1884, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -115880,6 +121416,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -115894,12 +121431,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4134 Instruction:"XOR rAX,Iz" Encoding:"0x35 iz"/"I" + // Pos:4183 Instruction:"XOR rAX,Iz" Encoding:"0x35 iz"/"I" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_I86, - .Mnemonic = 1849, + .Mnemonic = 1884, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -115908,6 +121445,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -115922,12 +121460,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4135 Instruction:"XOR Eb,Ib" Encoding:"0x80 /6 ib"/"MI" + // Pos:4184 Instruction:"XOR Eb,Ib" Encoding:"0x80 /6 ib"/"MI" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_I86, - .Mnemonic = 1849, + .Mnemonic = 1884, .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -115936,6 +121474,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -115950,12 +121489,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4136 Instruction:"XOR Ev,Iz" Encoding:"0x81 /6 iz"/"MI" + // Pos:4185 Instruction:"XOR Ev,Iz" Encoding:"0x81 /6 iz"/"MI" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_I86, - .Mnemonic = 1849, + .Mnemonic = 1884, .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -115964,6 +121503,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -115978,12 +121518,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4137 Instruction:"XOR Eb,Ib" Encoding:"0x82 /6 iz"/"MI" + // Pos:4186 Instruction:"XOR Eb,Ib" Encoding:"0x82 /6 iz"/"MI" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_I86, - .Mnemonic = 1849, + .Mnemonic = 1884, .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -115992,6 +121532,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -116006,12 +121547,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4138 Instruction:"XOR Ev,Ib" Encoding:"0x83 /6 ib"/"MI" + // Pos:4187 Instruction:"XOR Ev,Ib" Encoding:"0x83 /6 ib"/"MI" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_I86, - .Mnemonic = 1849, + .Mnemonic = 1884, .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -116020,6 +121561,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, .SetFlags = 0|NDR_RFLAG_AF, @@ -116034,12 +121576,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4139 Instruction:"XORPD Vpd,Wpd" Encoding:"0x66 0x0F 0x57 /r"/"RM" + // Pos:4188 Instruction:"XORPD Vpd,Wpd" Encoding:"0x66 0x0F 0x57 /r"/"RM" { .Instruction = ND_INS_XORPD, .Category = ND_CAT_LOGICAL_FP, .IsaSet = ND_SET_SSE2, - .Mnemonic = 1850, + .Mnemonic = 1885, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -116048,6 +121590,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -116061,12 +121604,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4140 Instruction:"XORPS Vps,Wps" Encoding:"NP 0x0F 0x57 /r"/"RM" + // Pos:4189 Instruction:"XORPS Vps,Wps" Encoding:"NP 0x0F 0x57 /r"/"RM" { .Instruction = ND_INS_XORPS, .Category = ND_CAT_LOGICAL_FP, .IsaSet = ND_SET_SSE, - .Mnemonic = 1851, + .Mnemonic = 1886, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -116075,6 +121618,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -116088,12 +121632,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4141 Instruction:"XRESLDTRK" Encoding:"0xF2 0x0F 0x01 /0xE9"/"" + // Pos:4190 Instruction:"XRESLDTRK" Encoding:"0xF2 0x0F 0x01 /0xE9"/"" { .Instruction = ND_INS_XRESLDTRK, .Category = ND_CAT_MISC, .IsaSet = ND_SET_TSXLDTRK, - .Mnemonic = 1852, + .Mnemonic = 1887, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -116102,6 +121646,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -116114,12 +121659,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4142 Instruction:"XRSTOR M?" Encoding:"NP 0x0F 0xAE /5:mem"/"M" + // Pos:4191 Instruction:"XRSTOR M?" Encoding:"NP 0x0F 0xAE /5:mem"/"M" { .Instruction = ND_INS_XRSTOR, .Category = ND_CAT_XSAVE, .IsaSet = ND_SET_XSAVE, - .Mnemonic = 1853, + .Mnemonic = 1888, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -116128,6 +121673,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -116144,12 +121690,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4143 Instruction:"XRSTOR64 M?" Encoding:"rexw NP 0x0F 0xAE /5:mem"/"M" + // Pos:4192 Instruction:"XRSTOR64 M?" Encoding:"rexw NP 0x0F 0xAE /5:mem"/"M" { .Instruction = ND_INS_XRSTOR, .Category = ND_CAT_XSAVE, .IsaSet = ND_SET_XSAVE, - .Mnemonic = 1854, + .Mnemonic = 1889, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -116158,6 +121704,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -116174,12 +121721,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4144 Instruction:"XRSTORS M?" Encoding:"NP 0x0F 0xC7 /3:mem"/"M" + // Pos:4193 Instruction:"XRSTORS M?" Encoding:"NP 0x0F 0xC7 /3:mem"/"M" { .Instruction = ND_INS_XRSTORS, .Category = ND_CAT_XSAVE, .IsaSet = ND_SET_XSAVES, - .Mnemonic = 1855, + .Mnemonic = 1890, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -116188,6 +121735,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -116204,12 +121752,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4145 Instruction:"XRSTORS64 M?" Encoding:"rexw NP 0x0F 0xC7 /3:mem"/"M" + // Pos:4194 Instruction:"XRSTORS64 M?" Encoding:"rexw NP 0x0F 0xC7 /3:mem"/"M" { .Instruction = ND_INS_XRSTORS, .Category = ND_CAT_XSAVE, .IsaSet = ND_SET_XSAVES, - .Mnemonic = 1856, + .Mnemonic = 1891, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -116218,6 +121766,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -116234,12 +121783,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4146 Instruction:"XSAVE M?" Encoding:"NP 0x0F 0xAE /4:mem"/"M" + // Pos:4195 Instruction:"XSAVE M?" Encoding:"NP 0x0F 0xAE /4:mem"/"M" { .Instruction = ND_INS_XSAVE, .Category = ND_CAT_XSAVE, .IsaSet = ND_SET_XSAVE, - .Mnemonic = 1857, + .Mnemonic = 1892, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -116248,6 +121797,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -116264,12 +121814,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4147 Instruction:"XSAVE64 M?" Encoding:"rexw NP 0x0F 0xAE /4:mem"/"M" + // Pos:4196 Instruction:"XSAVE64 M?" Encoding:"rexw NP 0x0F 0xAE /4:mem"/"M" { .Instruction = ND_INS_XSAVE, .Category = ND_CAT_XSAVE, .IsaSet = ND_SET_XSAVE, - .Mnemonic = 1858, + .Mnemonic = 1893, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -116278,6 +121828,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -116294,12 +121845,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4148 Instruction:"XSAVEC M?" Encoding:"NP 0x0F 0xC7 /4:mem"/"M" + // Pos:4197 Instruction:"XSAVEC M?" Encoding:"NP 0x0F 0xC7 /4:mem"/"M" { .Instruction = ND_INS_XSAVEC, .Category = ND_CAT_XSAVE, .IsaSet = ND_SET_XSAVEC, - .Mnemonic = 1859, + .Mnemonic = 1894, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -116308,6 +121859,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -116324,12 +121876,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4149 Instruction:"XSAVEC64 M?" Encoding:"rexw NP 0x0F 0xC7 /4:mem"/"M" + // Pos:4198 Instruction:"XSAVEC64 M?" Encoding:"rexw NP 0x0F 0xC7 /4:mem"/"M" { .Instruction = ND_INS_XSAVEC, .Category = ND_CAT_XSAVE, .IsaSet = ND_SET_XSAVEC, - .Mnemonic = 1860, + .Mnemonic = 1895, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -116338,6 +121890,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -116354,12 +121907,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4150 Instruction:"XSAVEOPT M?" Encoding:"NP 0x0F 0xAE /6:mem"/"M" + // Pos:4199 Instruction:"XSAVEOPT M?" Encoding:"NP 0x0F 0xAE /6:mem"/"M" { .Instruction = ND_INS_XSAVEOPT, .Category = ND_CAT_XSAVE, .IsaSet = ND_SET_XSAVE, - .Mnemonic = 1861, + .Mnemonic = 1896, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -116368,6 +121921,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -116384,12 +121938,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4151 Instruction:"XSAVEOPT64 M?" Encoding:"rexw NP 0x0F 0xAE /6:mem"/"M" + // Pos:4200 Instruction:"XSAVEOPT64 M?" Encoding:"rexw NP 0x0F 0xAE /6:mem"/"M" { .Instruction = ND_INS_XSAVEOPT, .Category = ND_CAT_XSAVE, .IsaSet = ND_SET_XSAVE, - .Mnemonic = 1862, + .Mnemonic = 1897, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -116398,6 +121952,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -116414,12 +121969,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4152 Instruction:"XSAVES M?" Encoding:"NP 0x0F 0xC7 /5:mem"/"M" + // Pos:4201 Instruction:"XSAVES M?" Encoding:"NP 0x0F 0xC7 /5:mem"/"M" { .Instruction = ND_INS_XSAVES, .Category = ND_CAT_XSAVE, .IsaSet = ND_SET_XSAVES, - .Mnemonic = 1863, + .Mnemonic = 1898, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -116428,6 +121983,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -116444,12 +122000,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4153 Instruction:"XSAVES64 M?" Encoding:"rexw NP 0x0F 0xC7 /5:mem"/"M" + // Pos:4202 Instruction:"XSAVES64 M?" Encoding:"rexw NP 0x0F 0xC7 /5:mem"/"M" { .Instruction = ND_INS_XSAVES, .Category = ND_CAT_XSAVE, .IsaSet = ND_SET_XSAVES, - .Mnemonic = 1864, + .Mnemonic = 1899, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -116458,6 +122014,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -116474,12 +122031,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4154 Instruction:"XSETBV" Encoding:"NP 0x0F 0x01 /0xD1"/"" + // Pos:4203 Instruction:"XSETBV" Encoding:"NP 0x0F 0x01 /0xD1"/"" { .Instruction = ND_INS_XSETBV, .Category = ND_CAT_XSAVE, .IsaSet = ND_SET_XSAVE, - .Mnemonic = 1865, + .Mnemonic = 1900, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -116488,6 +122045,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -116503,12 +122061,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4155 Instruction:"XSUSLDTRK" Encoding:"0xF2 0x0F 0x01 /0xE8"/"" + // Pos:4204 Instruction:"XSUSLDTRK" Encoding:"0xF2 0x0F 0x01 /0xE8"/"" { .Instruction = ND_INS_XSUSLDTRK, .Category = ND_CAT_MISC, .IsaSet = ND_SET_TSXLDTRK, - .Mnemonic = 1866, + .Mnemonic = 1901, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -116517,6 +122075,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -116529,12 +122088,12 @@ const ND_IDBE gInstructions[4157] = }, }, - // Pos:4156 Instruction:"XTEST" Encoding:"NP 0x0F 0x01 /0xD6"/"" + // Pos:4205 Instruction:"XTEST" Encoding:"NP 0x0F 0x01 /0xD6"/"" { .Instruction = ND_INS_XTEST, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_TSX, - .Mnemonic = 1867, + .Mnemonic = 1902, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -116543,6 +122102,7 @@ const ND_IDBE gInstructions[4157] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0|NDR_RFLAG_ZF, .SetFlags = 0, diff --git a/bddisasm/include/bdx86_mnemonics.h b/bddisasm/include/bdx86_mnemonics.h index 09ef09a..43546da 100644 --- a/bddisasm/include/bdx86_mnemonics.h +++ b/bddisasm/include/bdx86_mnemonics.h @@ -12,7 +12,7 @@ #ifndef BDDISASM_NO_MNEMONIC -const char *gMnemonics[1868] = +const char *gMnemonics[1903] = { "AAA", "AAD", "AADD", "AAM", "AAND", "AAS", "ADC", "ADCX", "ADD", "ADDPD", "ADDPS", "ADDSD", "ADDSS", "ADDSUBPD", "ADDSUBPS", "ADOX", @@ -92,9 +92,9 @@ const char *gMnemonics[1868] = "MOVHLPS", "MOVHPD", "MOVHPS", "MOVLHPS", "MOVLPD", "MOVLPS", "MOVMSKPD", "MOVMSKPS", "MOVNTDQ", "MOVNTDQA", "MOVNTI", "MOVNTPD", "MOVNTPS", "MOVNTQ", "MOVNTSD", "MOVNTSS", "MOVQ", "MOVQ2DQ", - "MOVSB", "MOVSD", "MOVSHDUP", "MOVSLDUP", "MOVSQ", "MOVSS", "MOVSW", - "MOVSX", "MOVSXD", "MOVUPD", "MOVUPS", "MOVZX", "MPSADBW", "MUL", - "MULPD", "MULPS", "MULSD", "MULSS", "MULX", "MWAIT", "MWAITX", + "MOVRS", "MOVSB", "MOVSD", "MOVSHDUP", "MOVSLDUP", "MOVSQ", "MOVSS", + "MOVSW", "MOVSX", "MOVSXD", "MOVUPD", "MOVUPS", "MOVZX", "MPSADBW", + "MUL", "MULPD", "MULPS", "MULSD", "MULSS", "MULX", "MWAIT", "MWAITX", "NEG", "NOP", "NOT", "OR", "ORPD", "ORPS", "OUT", "OUTSB", "OUTSD", "OUTSW", "PABSB", "PABSD", "PABSW", "PACKSSDW", "PACKSSWB", "PACKUSDW", "PACKUSWB", "PADDB", "PADDD", "PADDQ", "PADDSB", "PADDSW", "PADDUSB", @@ -116,77 +116,85 @@ const char *gMnemonics[1868] = "PMULHUW", "PMULHW", "PMULLD", "PMULLW", "PMULUDQ", "POP", "POP2", "POP2P", "POPA", "POPAD", "POPCNT", "POPFD", "POPFQ", "POPFW", "POPP", "POR", "PREFETCH", "PREFETCHE", "PREFETCHIT0", "PREFETCHIT1", - "PREFETCHM", "PREFETCHNTA", "PREFETCHT0", "PREFETCHT1", "PREFETCHT2", - "PREFETCHW", "PREFETCHWT1", "PSADBW", "PSHUFB", "PSHUFD", "PSHUFHW", - "PSHUFLW", "PSHUFW", "PSIGNB", "PSIGND", "PSIGNW", "PSLLD", "PSLLDQ", - "PSLLQ", "PSLLW", "PSMASH", "PSRAD", "PSRAW", "PSRLD", "PSRLDQ", - "PSRLQ", "PSRLW", "PSUBB", "PSUBD", "PSUBQ", "PSUBSB", "PSUBSW", - "PSUBUSB", "PSUBUSW", "PSUBW", "PSWAPD", "PTEST", "PTWRITE", - "PUNPCKHBW", "PUNPCKHDQ", "PUNPCKHQDQ", "PUNPCKHWD", "PUNPCKLBW", - "PUNPCKLDQ", "PUNPCKLQDQ", "PUNPCKLWD", "PUSH", "PUSH2", "PUSH2P", - "PUSHA", "PUSHAD", "PUSHFD", "PUSHFQ", "PUSHFW", "PUSHP", "PVALIDATE", - "PXOR", "RCL", "RCPPS", "RCPSS", "RCR", "RDFSBASE", "RDGSBASE", - "RDMSR", "RDMSRLIST", "RDPID", "RDPKRU", "RDPMC", "RDPRU", "RDRAND", - "RDSEED", "RDSSPD", "RDSSPQ", "RDTSC", "RDTSCP", "RETF", "RETN", - "RMPADJUST", "RMPQUERY", "RMPREAD", "RMPUPDATE", "ROL", "ROR", - "RORX", "ROUNDPD", "ROUNDPS", "ROUNDSD", "ROUNDSS", "RSM", "RSQRTPS", - "RSQRTSS", "RSTORSSP", "SAHF", "SAL", "SALC", "SAR", "SARX", - "SAVEPREVSSP", "SBB", "SCASB", "SCASD", "SCASQ", "SCASW", "SEAMCALL", - "SEAMOPS", "SEAMRET", "SENDUIPI", "SERIALIZE", "SETBE", "SETC", - "SETL", "SETLE", "SETNBE", "SETNC", "SETNL", "SETNLE", "SETNO", - "SETNP", "SETNS", "SETNZ", "SETO", "SETP", "SETS", "SETSSBSY", - "SETZ", "SFENCE", "SGDT", "SHA1MSG1", "SHA1MSG2", "SHA1NEXTE", - "SHA1RNDS4", "SHA256MSG1", "SHA256MSG2", "SHA256RNDS2", "SHL", - "SHLD", "SHLX", "SHR", "SHRD", "SHRX", "SHUFPD", "SHUFPS", "SIDT", - "SKINIT", "SLDT", "SLWPCB", "SMSW", "SPFLT", "SQRTPD", "SQRTPS", - "SQRTSD", "SQRTSS", "STAC", "STC", "STD", "STGI", "STI", "STMXCSR", - "STOSB", "STOSD", "STOSQ", "STOSW", "STR", "STTILECFG", "STUI", - "SUB", "SUBPD", "SUBPS", "SUBSD", "SUBSS", "SWAPGS", "SYSCALL", - "SYSENTER", "SYSEXIT", "SYSRET", "T1MSKC", "TCMMIMFP16PS", "TCMMRLFP16PS", - "TDCALL", "TDPBF16PS", "TDPBSSD", "TDPBSUD", "TDPBUSD", "TDPBUUD", - "TDPFP16PS", "TEST", "TESTUI", "TILELOADD", "TILELOADDT1", "TILERELEASE", - "TILESTORED", "TILEZERO", "TLBSYNC", "TPAUSE", "TZCNT", "TZMSK", - "UCOMISD", "UCOMISS", "UD0", "UD1", "UD2", "UIRET", "UMONITOR", - "UMWAIT", "UNPCKHPD", "UNPCKHPS", "UNPCKLPD", "UNPCKLPS", "URDMSR", - "UWRMSR", "V4FMADDPS", "V4FMADDSS", "V4FNMADDPS", "V4FNMADDSS", - "VADDNEPBF16", "VADDPD", "VADDPH", "VADDPS", "VADDSD", "VADDSH", - "VADDSS", "VADDSUBPD", "VADDSUBPS", "VAESDEC", "VAESDECLAST", - "VAESENC", "VAESENCLAST", "VAESIMC", "VAESKEYGENASSIST", "VALIGND", - "VALIGNQ", "VANDNPD", "VANDNPS", "VANDPD", "VANDPS", "VBCSTNEBF162PS", - "VBCSTNESH2PS", "VBLENDMPD", "VBLENDMPS", "VBLENDPD", "VBLENDPS", - "VBLENDVPD", "VBLENDVPS", "VBROADCASTF128", "VBROADCASTF32X2", - "VBROADCASTF32X4", "VBROADCASTF32X8", "VBROADCASTF64X2", "VBROADCASTF64X4", - "VBROADCASTI128", "VBROADCASTI32X2", "VBROADCASTI32X4", "VBROADCASTI32X8", - "VBROADCASTI64X2", "VBROADCASTI64X4", "VBROADCASTSD", "VBROADCASTSS", - "VCMPPBF16", "VCMPPD", "VCMPPH", "VCMPPS", "VCMPSD", "VCMPSH", - "VCMPSS", "VCOMISD", "VCOMISH", "VCOMISS", "VCOMPRESSPD", "VCOMPRESSPS", - "VCOMSBF16", "VCOMXSD", "VCOMXSH", "VCOMXSS", "VCVT2PS2PHX", - "VCVTBIASPH2BF8", "VCVTBIASPH2BF8S", "VCVTBIASPH2HF8", "VCVTBIASPH2HF8S", - "VCVTDQ2PD", "VCVTDQ2PH", "VCVTDQ2PS", "VCVTHF82PH", "VCVTNE2PH2BF8", - "VCVTNE2PH2BF8S", "VCVTNE2PH2HF8", "VCVTNE2PH2HF8S", "VCVTNE2PS2BF16", - "VCVTNEBF162IBS", "VCVTNEBF162IUBS", "VCVTNEEBF162PS", "VCVTNEEPH2PS", - "VCVTNEOBF162PS", "VCVTNEOPH2PS", "VCVTNEPH2BF8", "VCVTNEPH2BF8S", - "VCVTNEPH2HF8", "VCVTNEPH2HF8S", "VCVTNEPS2BF16", "VCVTPD2DQ", - "VCVTPD2PH", "VCVTPD2PS", "VCVTPD2QQ", "VCVTPD2UDQ", "VCVTPD2UQQ", - "VCVTPH2DQ", "VCVTPH2IBS", "VCVTPH2IUBS", "VCVTPH2PD", "VCVTPH2PS", - "VCVTPH2PSX", "VCVTPH2QQ", "VCVTPH2UDQ", "VCVTPH2UQQ", "VCVTPH2UW", - "VCVTPH2W", "VCVTPS2DQ", "VCVTPS2IBS", "VCVTPS2IUBS", "VCVTPS2PD", - "VCVTPS2PH", "VCVTPS2PHX", "VCVTPS2QQ", "VCVTPS2UDQ", "VCVTPS2UQQ", - "VCVTQQ2PD", "VCVTQQ2PH", "VCVTQQ2PS", "VCVTSD2SH", "VCVTSD2SI", - "VCVTSD2SS", "VCVTSD2USI", "VCVTSH2SD", "VCVTSH2SI", "VCVTSH2SS", - "VCVTSH2USI", "VCVTSI2SD", "VCVTSI2SH", "VCVTSI2SS", "VCVTSS2SD", - "VCVTSS2SH", "VCVTSS2SI", "VCVTSS2USI", "VCVTTNEBF162IBS", "VCVTTNEBF162IUBS", - "VCVTTPD2DQ", "VCVTTPD2DQS", "VCVTTPD2QQ", "VCVTTPD2QQS", "VCVTTPD2UDQ", - "VCVTTPD2UDQS", "VCVTTPD2UQQ", "VCVTTPD2UQQS", "VCVTTPH2DQ", - "VCVTTPH2IBS", "VCVTTPH2IUBS", "VCVTTPH2QQ", "VCVTTPH2UDQ", "VCVTTPH2UQQ", - "VCVTTPH2UW", "VCVTTPH2W", "VCVTTPS2DQ", "VCVTTPS2DQS", "VCVTTPS2IBS", - "VCVTTPS2IUBS", "VCVTTPS2QQ", "VCVTTPS2QQS", "VCVTTPS2UDQ", "VCVTTPS2UDQS", - "VCVTTPS2UQQ", "VCVTTPS2UQQS", "VCVTTSD2SI", "VCVTTSD2SIS", "VCVTTSD2USI", - "VCVTTSD2USIS", "VCVTTSH2SI", "VCVTTSH2USI", "VCVTTSS2SI", "VCVTTSS2SIS", - "VCVTTSS2USI", "VCVTTSS2USIS", "VCVTUDQ2PD", "VCVTUDQ2PH", "VCVTUDQ2PS", - "VCVTUQQ2PD", "VCVTUQQ2PH", "VCVTUQQ2PS", "VCVTUSI2SD", "VCVTUSI2SH", - "VCVTUSI2SS", "VCVTUW2PH", "VCVTW2PH", "VDBPSADBW", "VDIVNEPBF16", - "VDIVPD", "VDIVPH", "VDIVPS", "VDIVSD", "VDIVSH", "VDIVSS", "VDPBF16PS", + "PREFETCHM", "PREFETCHNTA", "PREFETCHRST2", "PREFETCHT0", "PREFETCHT1", + "PREFETCHT2", "PREFETCHW", "PREFETCHWT1", "PSADBW", "PSHUFB", + "PSHUFD", "PSHUFHW", "PSHUFLW", "PSHUFW", "PSIGNB", "PSIGND", + "PSIGNW", "PSLLD", "PSLLDQ", "PSLLQ", "PSLLW", "PSMASH", "PSRAD", + "PSRAW", "PSRLD", "PSRLDQ", "PSRLQ", "PSRLW", "PSUBB", "PSUBD", + "PSUBQ", "PSUBSB", "PSUBSW", "PSUBUSB", "PSUBUSW", "PSUBW", "PSWAPD", + "PTEST", "PTWRITE", "PUNPCKHBW", "PUNPCKHDQ", "PUNPCKHQDQ", "PUNPCKHWD", + "PUNPCKLBW", "PUNPCKLDQ", "PUNPCKLQDQ", "PUNPCKLWD", "PUSH", + "PUSH2", "PUSH2P", "PUSHA", "PUSHAD", "PUSHFD", "PUSHFQ", "PUSHFW", + "PUSHP", "PVALIDATE", "PXOR", "RCL", "RCPPS", "RCPSS", "RCR", + "RDFSBASE", "RDGSBASE", "RDMSR", "RDMSRLIST", "RDPID", "RDPKRU", + "RDPMC", "RDPRU", "RDRAND", "RDSEED", "RDSSPD", "RDSSPQ", "RDTSC", + "RDTSCP", "RETF", "RETN", "RMPADJUST", "RMPQUERY", "RMPREAD", + "RMPUPDATE", "ROL", "ROR", "RORX", "ROUNDPD", "ROUNDPS", "ROUNDSD", + "ROUNDSS", "RSM", "RSQRTPS", "RSQRTSS", "RSTORSSP", "SAHF", "SAL", + "SALC", "SAR", "SARX", "SAVEPREVSSP", "SBB", "SCASB", "SCASD", + "SCASQ", "SCASW", "SEAMCALL", "SEAMOPS", "SEAMRET", "SENDUIPI", + "SERIALIZE", "SETBE", "SETC", "SETL", "SETLE", "SETNBE", "SETNC", + "SETNL", "SETNLE", "SETNO", "SETNP", "SETNS", "SETNZ", "SETO", + "SETP", "SETS", "SETSSBSY", "SETZ", "SFENCE", "SGDT", "SHA1MSG1", + "SHA1MSG2", "SHA1NEXTE", "SHA1RNDS4", "SHA256MSG1", "SHA256MSG2", + "SHA256RNDS2", "SHL", "SHLD", "SHLX", "SHR", "SHRD", "SHRX", + "SHUFPD", "SHUFPS", "SIDT", "SKINIT", "SLDT", "SLWPCB", "SMSW", + "SPFLT", "SQRTPD", "SQRTPS", "SQRTSD", "SQRTSS", "STAC", "STC", + "STD", "STGI", "STI", "STMXCSR", "STOSB", "STOSD", "STOSQ", "STOSW", + "STR", "STTILECFG", "STUI", "SUB", "SUBPD", "SUBPS", "SUBSD", + "SUBSS", "SWAPGS", "SYSCALL", "SYSENTER", "SYSEXIT", "SYSRET", + "T1MSKC", "T2RPNTLVWZ0", "T2RPNTLVWZ0RS", "T2RPNTLVWZ0RST1", + "T2RPNTLVWZ0T1", "T2RPNTLVWZ1", "T2RPNTLVWZ1RS", "T2RPNTLVWZ1RST1", + "T2RPNTLVWZ1T1", "TCMMIMFP16PS", "TCMMRLFP16PS", "TCONJTCMMIMFP16PS", + "TCONJTFP16", "TCVTROWD2PS", "TCVTROWPS2PBF16H", "TCVTROWPS2PBF16L", + "TCVTROWPS2PHH", "TCVTROWPS2PHL", "TDCALL", "TDPBF16PS", "TDPBF8PS", + "TDPBHF8PS", "TDPBSSD", "TDPBSUD", "TDPBUSD", "TDPBUUD", "TDPFP16PS", + "TDPHBF8PS", "TDPHF8PS", "TEST", "TESTUI", "TILELOADD", "TILELOADDRS", + "TILELOADDRST1", "TILELOADDT1", "TILEMOVROW", "TILERELEASE", + "TILESTORED", "TILEZERO", "TLBSYNC", "TMMULTF32PS", "TPAUSE", + "TTCMMIMFP16PS", "TTCMMRLFP16PS", "TTDPBF16PS", "TTDPFP16PS", + "TTMMULTF32PS", "TTRANSPOSED", "TZCNT", "TZMSK", "UCOMISD", "UCOMISS", + "UD0", "UD1", "UD2", "UIRET", "UMONITOR", "UMWAIT", "UNPCKHPD", + "UNPCKHPS", "UNPCKLPD", "UNPCKLPS", "URDMSR", "UWRMSR", "V4FMADDPS", + "V4FMADDSS", "V4FNMADDPS", "V4FNMADDSS", "VADDNEPBF16", "VADDPD", + "VADDPH", "VADDPS", "VADDSD", "VADDSH", "VADDSS", "VADDSUBPD", + "VADDSUBPS", "VAESDEC", "VAESDECLAST", "VAESENC", "VAESENCLAST", + "VAESIMC", "VAESKEYGENASSIST", "VALIGND", "VALIGNQ", "VANDNPD", + "VANDNPS", "VANDPD", "VANDPS", "VBCSTNEBF162PS", "VBCSTNESH2PS", + "VBLENDMPD", "VBLENDMPS", "VBLENDPD", "VBLENDPS", "VBLENDVPD", + "VBLENDVPS", "VBROADCASTF128", "VBROADCASTF32X2", "VBROADCASTF32X4", + "VBROADCASTF32X8", "VBROADCASTF64X2", "VBROADCASTF64X4", "VBROADCASTI128", + "VBROADCASTI32X2", "VBROADCASTI32X4", "VBROADCASTI32X8", "VBROADCASTI64X2", + "VBROADCASTI64X4", "VBROADCASTSD", "VBROADCASTSS", "VCMPPBF16", + "VCMPPD", "VCMPPH", "VCMPPS", "VCMPSD", "VCMPSH", "VCMPSS", "VCOMISD", + "VCOMISH", "VCOMISS", "VCOMPRESSPD", "VCOMPRESSPS", "VCOMSBF16", + "VCOMXSD", "VCOMXSH", "VCOMXSS", "VCVT2PS2PHX", "VCVTBIASPH2BF8", + "VCVTBIASPH2BF8S", "VCVTBIASPH2HF8", "VCVTBIASPH2HF8S", "VCVTDQ2PD", + "VCVTDQ2PH", "VCVTDQ2PS", "VCVTHF82PH", "VCVTNE2PH2BF8", "VCVTNE2PH2BF8S", + "VCVTNE2PH2HF8", "VCVTNE2PH2HF8S", "VCVTNE2PS2BF16", "VCVTNEBF162IBS", + "VCVTNEBF162IUBS", "VCVTNEEBF162PS", "VCVTNEEPH2PS", "VCVTNEOBF162PS", + "VCVTNEOPH2PS", "VCVTNEPH2BF8", "VCVTNEPH2BF8S", "VCVTNEPH2HF8", + "VCVTNEPH2HF8S", "VCVTNEPS2BF16", "VCVTPD2DQ", "VCVTPD2PH", "VCVTPD2PS", + "VCVTPD2QQ", "VCVTPD2UDQ", "VCVTPD2UQQ", "VCVTPH2DQ", "VCVTPH2IBS", + "VCVTPH2IUBS", "VCVTPH2PD", "VCVTPH2PS", "VCVTPH2PSX", "VCVTPH2QQ", + "VCVTPH2UDQ", "VCVTPH2UQQ", "VCVTPH2UW", "VCVTPH2W", "VCVTPS2DQ", + "VCVTPS2IBS", "VCVTPS2IUBS", "VCVTPS2PD", "VCVTPS2PH", "VCVTPS2PHX", + "VCVTPS2QQ", "VCVTPS2UDQ", "VCVTPS2UQQ", "VCVTQQ2PD", "VCVTQQ2PH", + "VCVTQQ2PS", "VCVTSD2SH", "VCVTSD2SI", "VCVTSD2SS", "VCVTSD2USI", + "VCVTSH2SD", "VCVTSH2SI", "VCVTSH2SS", "VCVTSH2USI", "VCVTSI2SD", + "VCVTSI2SH", "VCVTSI2SS", "VCVTSS2SD", "VCVTSS2SH", "VCVTSS2SI", + "VCVTSS2USI", "VCVTTNEBF162IBS", "VCVTTNEBF162IUBS", "VCVTTPD2DQ", + "VCVTTPD2DQS", "VCVTTPD2QQ", "VCVTTPD2QQS", "VCVTTPD2UDQ", "VCVTTPD2UDQS", + "VCVTTPD2UQQ", "VCVTTPD2UQQS", "VCVTTPH2DQ", "VCVTTPH2IBS", "VCVTTPH2IUBS", + "VCVTTPH2QQ", "VCVTTPH2UDQ", "VCVTTPH2UQQ", "VCVTTPH2UW", "VCVTTPH2W", + "VCVTTPS2DQ", "VCVTTPS2DQS", "VCVTTPS2IBS", "VCVTTPS2IUBS", "VCVTTPS2QQ", + "VCVTTPS2QQS", "VCVTTPS2UDQ", "VCVTTPS2UDQS", "VCVTTPS2UQQ", + "VCVTTPS2UQQS", "VCVTTSD2SI", "VCVTTSD2SIS", "VCVTTSD2USI", "VCVTTSD2USIS", + "VCVTTSH2SI", "VCVTTSH2USI", "VCVTTSS2SI", "VCVTTSS2SIS", "VCVTTSS2USI", + "VCVTTSS2USIS", "VCVTUDQ2PD", "VCVTUDQ2PH", "VCVTUDQ2PS", "VCVTUQQ2PD", + "VCVTUQQ2PH", "VCVTUQQ2PS", "VCVTUSI2SD", "VCVTUSI2SH", "VCVTUSI2SS", + "VCVTUW2PH", "VCVTW2PH", "VDBPSADBW", "VDIVNEPBF16", "VDIVPD", + "VDIVPH", "VDIVPS", "VDIVSD", "VDIVSH", "VDIVSS", "VDPBF16PS", "VDPPD", "VDPPHPS", "VDPPS", "VERR", "VERW", "VEXP2PD", "VEXP2PS", "VEXPANDPD", "VEXPANDPS", "VEXTRACTF128", "VEXTRACTF32X4", "VEXTRACTF32X8", "VEXTRACTF64X2", "VEXTRACTF64X4", "VEXTRACTI128", "VEXTRACTI32X4", @@ -243,101 +251,102 @@ const char *gMnemonics[1868] = "VMOVDQA64", "VMOVDQU", "VMOVDQU16", "VMOVDQU32", "VMOVDQU64", "VMOVDQU8", "VMOVHLPS", "VMOVHPD", "VMOVHPS", "VMOVLHPS", "VMOVLPD", "VMOVLPS", "VMOVMSKPD", "VMOVMSKPS", "VMOVNTDQ", "VMOVNTDQA", - "VMOVNTPD", "VMOVNTPS", "VMOVQ", "VMOVSD", "VMOVSH", "VMOVSHDUP", - "VMOVSLDUP", "VMOVSS", "VMOVUPD", "VMOVUPS", "VMOVW", "VMPSADBW", - "VMPTRLD", "VMPTRST", "VMREAD", "VMRESUME", "VMRUN", "VMSAVE", - "VMULNEPBF16", "VMULPD", "VMULPH", "VMULPS", "VMULSD", "VMULSH", - "VMULSS", "VMWRITE", "VMXOFF", "VMXON", "VORPD", "VORPS", "VP2INTERSECTD", - "VP2INTERSECTQ", "VP4DPWSSD", "VP4DPWSSDS", "VPABSB", "VPABSD", - "VPABSQ", "VPABSW", "VPACKSSDW", "VPACKSSWB", "VPACKUSDW", "VPACKUSWB", - "VPADDB", "VPADDD", "VPADDQ", "VPADDSB", "VPADDSW", "VPADDUSB", - "VPADDUSW", "VPADDW", "VPALIGNR", "VPAND", "VPANDD", "VPANDN", - "VPANDND", "VPANDNQ", "VPANDQ", "VPAVGB", "VPAVGW", "VPBLENDD", - "VPBLENDMB", "VPBLENDMD", "VPBLENDMQ", "VPBLENDMW", "VPBLENDVB", - "VPBLENDW", "VPBROADCASTB", "VPBROADCASTD", "VPBROADCASTMB2Q", - "VPBROADCASTMW2D", "VPBROADCASTQ", "VPBROADCASTW", "VPCLMULQDQ", - "VPCMOV", "VPCMPB", "VPCMPD", "VPCMPEQB", "VPCMPEQD", "VPCMPEQQ", - "VPCMPEQW", "VPCMPESTRI", "VPCMPESTRM", "VPCMPGTB", "VPCMPGTD", - "VPCMPGTQ", "VPCMPGTW", "VPCMPISTRI", "VPCMPISTRM", "VPCMPQ", - "VPCMPUB", "VPCMPUD", "VPCMPUQ", "VPCMPUW", "VPCMPW", "VPCOMB", - "VPCOMD", "VPCOMPRESSB", "VPCOMPRESSD", "VPCOMPRESSQ", "VPCOMPRESSW", - "VPCOMQ", "VPCOMUB", "VPCOMUD", "VPCOMUQ", "VPCOMUW", "VPCOMW", - "VPCONFLICTD", "VPCONFLICTQ", "VPDPBSSD", "VPDPBSSDS", "VPDPBSUD", - "VPDPBSUDS", "VPDPBUSD", "VPDPBUSDS", "VPDPBUUD", "VPDPBUUDS", - "VPDPWSSD", "VPDPWSSDS", "VPDPWSUD", "VPDPWSUDS", "VPDPWUSD", - "VPDPWUSDS", "VPDPWUUD", "VPDPWUUDS", "VPERM2F128", "VPERM2I128", - "VPERMB", "VPERMD", "VPERMI2B", "VPERMI2D", "VPERMI2PD", "VPERMI2PS", - "VPERMI2Q", "VPERMI2W", "VPERMIL2PD", "VPERMIL2PS", "VPERMILPD", - "VPERMILPS", "VPERMPD", "VPERMPS", "VPERMQ", "VPERMT2B", "VPERMT2D", - "VPERMT2PD", "VPERMT2PS", "VPERMT2Q", "VPERMT2W", "VPERMW", "VPEXPANDB", - "VPEXPANDD", "VPEXPANDQ", "VPEXPANDW", "VPEXTRB", "VPEXTRD", - "VPEXTRQ", "VPEXTRW", "VPGATHERDD", "VPGATHERDQ", "VPGATHERQD", - "VPGATHERQQ", "VPHADDBD", "VPHADDBQ", "VPHADDBW", "VPHADDD", - "VPHADDDQ", "VPHADDSW", "VPHADDUBD", "VPHADDUBQ", "VPHADDUBW", - "VPHADDUDQ", "VPHADDUWD", "VPHADDUWQ", "VPHADDW", "VPHADDWD", - "VPHADDWQ", "VPHMINPOSUW", "VPHSUBBW", "VPHSUBD", "VPHSUBDQ", - "VPHSUBSW", "VPHSUBW", "VPHSUBWD", "VPINSRB", "VPINSRD", "VPINSRQ", - "VPINSRW", "VPLZCNTD", "VPLZCNTQ", "VPMACSDD", "VPMACSDQH", "VPMACSDQL", - "VPMACSSDD", "VPMACSSDQH", "VPMACSSDQL", "VPMACSSWD", "VPMACSSWW", - "VPMACSWD", "VPMACSWW", "VPMADCSSWD", "VPMADCSWD", "VPMADD52HUQ", - "VPMADD52LUQ", "VPMADDUBSW", "VPMADDWD", "VPMASKMOVD", "VPMASKMOVQ", - "VPMAXSB", "VPMAXSD", "VPMAXSQ", "VPMAXSW", "VPMAXUB", "VPMAXUD", - "VPMAXUQ", "VPMAXUW", "VPMINSB", "VPMINSD", "VPMINSQ", "VPMINSW", - "VPMINUB", "VPMINUD", "VPMINUQ", "VPMINUW", "VPMOVB2M", "VPMOVD2M", - "VPMOVDB", "VPMOVDW", "VPMOVM2B", "VPMOVM2D", "VPMOVM2Q", "VPMOVM2W", - "VPMOVMSKB", "VPMOVQ2M", "VPMOVQB", "VPMOVQD", "VPMOVQW", "VPMOVSDB", - "VPMOVSDW", "VPMOVSQB", "VPMOVSQD", "VPMOVSQW", "VPMOVSWB", "VPMOVSXBD", - "VPMOVSXBQ", "VPMOVSXBW", "VPMOVSXDQ", "VPMOVSXWD", "VPMOVSXWQ", - "VPMOVUSDB", "VPMOVUSDW", "VPMOVUSQB", "VPMOVUSQD", "VPMOVUSQW", - "VPMOVUSWB", "VPMOVW2M", "VPMOVWB", "VPMOVZXBD", "VPMOVZXBQ", - "VPMOVZXBW", "VPMOVZXDQ", "VPMOVZXWD", "VPMOVZXWQ", "VPMULDQ", - "VPMULHRSW", "VPMULHUW", "VPMULHW", "VPMULLD", "VPMULLQ", "VPMULLW", - "VPMULTISHIFTQB", "VPMULUDQ", "VPOPCNTB", "VPOPCNTD", "VPOPCNTQ", - "VPOPCNTW", "VPOR", "VPORD", "VPORQ", "VPPERM", "VPROLD", "VPROLQ", - "VPROLVD", "VPROLVQ", "VPRORD", "VPRORQ", "VPRORVD", "VPRORVQ", - "VPROTB", "VPROTD", "VPROTQ", "VPROTW", "VPSADBW", "VPSCATTERDD", - "VPSCATTERDQ", "VPSCATTERQD", "VPSCATTERQQ", "VPSHAB", "VPSHAD", - "VPSHAQ", "VPSHAW", "VPSHLB", "VPSHLD", "VPSHLDD", "VPSHLDQ", - "VPSHLDVD", "VPSHLDVQ", "VPSHLDVW", "VPSHLDW", "VPSHLQ", "VPSHLW", - "VPSHRDD", "VPSHRDQ", "VPSHRDVD", "VPSHRDVQ", "VPSHRDVW", "VPSHRDW", - "VPSHUFB", "VPSHUFBITQMB", "VPSHUFD", "VPSHUFHW", "VPSHUFLW", - "VPSIGNB", "VPSIGND", "VPSIGNW", "VPSLLD", "VPSLLDQ", "VPSLLQ", - "VPSLLVD", "VPSLLVQ", "VPSLLVW", "VPSLLW", "VPSRAD", "VPSRAQ", - "VPSRAVD", "VPSRAVQ", "VPSRAVW", "VPSRAW", "VPSRLD", "VPSRLDQ", - "VPSRLQ", "VPSRLVD", "VPSRLVQ", "VPSRLVW", "VPSRLW", "VPSUBB", - "VPSUBD", "VPSUBQ", "VPSUBSB", "VPSUBSW", "VPSUBUSB", "VPSUBUSW", - "VPSUBW", "VPTERNLOGD", "VPTERNLOGQ", "VPTEST", "VPTESTMB", "VPTESTMD", - "VPTESTMQ", "VPTESTMW", "VPTESTNMB", "VPTESTNMD", "VPTESTNMQ", - "VPTESTNMW", "VPUNPCKHBW", "VPUNPCKHDQ", "VPUNPCKHQDQ", "VPUNPCKHWD", - "VPUNPCKLBW", "VPUNPCKLDQ", "VPUNPCKLQDQ", "VPUNPCKLWD", "VPXOR", - "VPXORD", "VPXORQ", "VRANGEPD", "VRANGEPS", "VRANGESD", "VRANGESS", - "VRCP14PD", "VRCP14PS", "VRCP14SD", "VRCP14SS", "VRCP28PD", "VRCP28PS", - "VRCP28SD", "VRCP28SS", "VRCPPBF16", "VRCPPH", "VRCPPS", "VRCPSH", - "VRCPSS", "VREDUCENEPBF16", "VREDUCEPD", "VREDUCEPH", "VREDUCEPS", - "VREDUCESD", "VREDUCESH", "VREDUCESS", "VRNDSCALENEPBF16", "VRNDSCALEPD", - "VRNDSCALEPH", "VRNDSCALEPS", "VRNDSCALESD", "VRNDSCALESH", "VRNDSCALESS", - "VROUNDPD", "VROUNDPS", "VROUNDSD", "VROUNDSS", "VRSQRT14PD", - "VRSQRT14PS", "VRSQRT14SD", "VRSQRT14SS", "VRSQRT28PD", "VRSQRT28PS", - "VRSQRT28SD", "VRSQRT28SS", "VRSQRTPBF16", "VRSQRTPH", "VRSQRTPS", - "VRSQRTSH", "VRSQRTSS", "VSCALEFPBF16", "VSCALEFPD", "VSCALEFPH", - "VSCALEFPS", "VSCALEFSD", "VSCALEFSH", "VSCALEFSS", "VSCATTERDPD", - "VSCATTERDPS", "VSCATTERPF0DPD", "VSCATTERPF0DPS", "VSCATTERPF0QPD", - "VSCATTERPF0QPS", "VSCATTERPF1DPD", "VSCATTERPF1DPS", "VSCATTERPF1QPD", - "VSCATTERPF1QPS", "VSCATTERQPD", "VSCATTERQPS", "VSHA512MSG1", - "VSHA512MSG2", "VSHA512RNDS2", "VSHUFF32X4", "VSHUFF64X2", "VSHUFI32X4", - "VSHUFI64X2", "VSHUFPD", "VSHUFPS", "VSM3MSG1", "VSM3MSG2", "VSM3RNDS2", - "VSM4KEY4", "VSM4RNDS4", "VSQRTNEPBF16", "VSQRTPD", "VSQRTPH", - "VSQRTPS", "VSQRTSD", "VSQRTSH", "VSQRTSS", "VSTMXCSR", "VSUBNEPBF16", - "VSUBPD", "VSUBPH", "VSUBPS", "VSUBSD", "VSUBSH", "VSUBSS", "VTESTPD", - "VTESTPS", "VUCOMISD", "VUCOMISH", "VUCOMISS", "VUCOMXSD", "VUCOMXSH", - "VUCOMXSS", "VUNPCKHPD", "VUNPCKHPS", "VUNPCKLPD", "VUNPCKLPS", - "VXORPD", "VXORPS", "VZEROALL", "VZEROUPPER", "WAIT", "WBINVD", - "WBNOINVD", "WRFSBASE", "WRGSBASE", "WRMSR", "WRMSRLIST", "WRMSRNS", - "WRPKRU", "WRSSD", "WRSSQ", "WRUSSD", "WRUSSQ", "XABORT", "XADD", - "XBEGIN", "XCHG", "XEND", "XGETBV", "XLATB", "XOR", "XORPD", - "XORPS", "XRESLDTRK", "XRSTOR", "XRSTOR64", "XRSTORS", "XRSTORS64", - "XSAVE", "XSAVE64", "XSAVEC", "XSAVEC64", "XSAVEOPT", "XSAVEOPT64", - "XSAVES", "XSAVES64", "XSETBV", "XSUSLDTRK", "XTEST", + "VMOVNTPD", "VMOVNTPS", "VMOVQ", "VMOVRSB", "VMOVRSD", "VMOVRSQ", + "VMOVRSW", "VMOVSD", "VMOVSH", "VMOVSHDUP", "VMOVSLDUP", "VMOVSS", + "VMOVUPD", "VMOVUPS", "VMOVW", "VMPSADBW", "VMPTRLD", "VMPTRST", + "VMREAD", "VMRESUME", "VMRUN", "VMSAVE", "VMULNEPBF16", "VMULPD", + "VMULPH", "VMULPS", "VMULSD", "VMULSH", "VMULSS", "VMWRITE", + "VMXOFF", "VMXON", "VORPD", "VORPS", "VP2INTERSECTD", "VP2INTERSECTQ", + "VP4DPWSSD", "VP4DPWSSDS", "VPABSB", "VPABSD", "VPABSQ", "VPABSW", + "VPACKSSDW", "VPACKSSWB", "VPACKUSDW", "VPACKUSWB", "VPADDB", + "VPADDD", "VPADDQ", "VPADDSB", "VPADDSW", "VPADDUSB", "VPADDUSW", + "VPADDW", "VPALIGNR", "VPAND", "VPANDD", "VPANDN", "VPANDND", + "VPANDNQ", "VPANDQ", "VPAVGB", "VPAVGW", "VPBLENDD", "VPBLENDMB", + "VPBLENDMD", "VPBLENDMQ", "VPBLENDMW", "VPBLENDVB", "VPBLENDW", + "VPBROADCASTB", "VPBROADCASTD", "VPBROADCASTMB2Q", "VPBROADCASTMW2D", + "VPBROADCASTQ", "VPBROADCASTW", "VPCLMULQDQ", "VPCMOV", "VPCMPB", + "VPCMPD", "VPCMPEQB", "VPCMPEQD", "VPCMPEQQ", "VPCMPEQW", "VPCMPESTRI", + "VPCMPESTRM", "VPCMPGTB", "VPCMPGTD", "VPCMPGTQ", "VPCMPGTW", + "VPCMPISTRI", "VPCMPISTRM", "VPCMPQ", "VPCMPUB", "VPCMPUD", "VPCMPUQ", + "VPCMPUW", "VPCMPW", "VPCOMB", "VPCOMD", "VPCOMPRESSB", "VPCOMPRESSD", + "VPCOMPRESSQ", "VPCOMPRESSW", "VPCOMQ", "VPCOMUB", "VPCOMUD", + "VPCOMUQ", "VPCOMUW", "VPCOMW", "VPCONFLICTD", "VPCONFLICTQ", + "VPDPBSSD", "VPDPBSSDS", "VPDPBSUD", "VPDPBSUDS", "VPDPBUSD", + "VPDPBUSDS", "VPDPBUUD", "VPDPBUUDS", "VPDPWSSD", "VPDPWSSDS", + "VPDPWSUD", "VPDPWSUDS", "VPDPWUSD", "VPDPWUSDS", "VPDPWUUD", + "VPDPWUUDS", "VPERM2F128", "VPERM2I128", "VPERMB", "VPERMD", + "VPERMI2B", "VPERMI2D", "VPERMI2PD", "VPERMI2PS", "VPERMI2Q", + "VPERMI2W", "VPERMIL2PD", "VPERMIL2PS", "VPERMILPD", "VPERMILPS", + "VPERMPD", "VPERMPS", "VPERMQ", "VPERMT2B", "VPERMT2D", "VPERMT2PD", + "VPERMT2PS", "VPERMT2Q", "VPERMT2W", "VPERMW", "VPEXPANDB", "VPEXPANDD", + "VPEXPANDQ", "VPEXPANDW", "VPEXTRB", "VPEXTRD", "VPEXTRQ", "VPEXTRW", + "VPGATHERDD", "VPGATHERDQ", "VPGATHERQD", "VPGATHERQQ", "VPHADDBD", + "VPHADDBQ", "VPHADDBW", "VPHADDD", "VPHADDDQ", "VPHADDSW", "VPHADDUBD", + "VPHADDUBQ", "VPHADDUBW", "VPHADDUDQ", "VPHADDUWD", "VPHADDUWQ", + "VPHADDW", "VPHADDWD", "VPHADDWQ", "VPHMINPOSUW", "VPHSUBBW", + "VPHSUBD", "VPHSUBDQ", "VPHSUBSW", "VPHSUBW", "VPHSUBWD", "VPINSRB", + "VPINSRD", "VPINSRQ", "VPINSRW", "VPLZCNTD", "VPLZCNTQ", "VPMACSDD", + "VPMACSDQH", "VPMACSDQL", "VPMACSSDD", "VPMACSSDQH", "VPMACSSDQL", + "VPMACSSWD", "VPMACSSWW", "VPMACSWD", "VPMACSWW", "VPMADCSSWD", + "VPMADCSWD", "VPMADD52HUQ", "VPMADD52LUQ", "VPMADDUBSW", "VPMADDWD", + "VPMASKMOVD", "VPMASKMOVQ", "VPMAXSB", "VPMAXSD", "VPMAXSQ", + "VPMAXSW", "VPMAXUB", "VPMAXUD", "VPMAXUQ", "VPMAXUW", "VPMINSB", + "VPMINSD", "VPMINSQ", "VPMINSW", "VPMINUB", "VPMINUD", "VPMINUQ", + "VPMINUW", "VPMOVB2M", "VPMOVD2M", "VPMOVDB", "VPMOVDW", "VPMOVM2B", + "VPMOVM2D", "VPMOVM2Q", "VPMOVM2W", "VPMOVMSKB", "VPMOVQ2M", + "VPMOVQB", "VPMOVQD", "VPMOVQW", "VPMOVSDB", "VPMOVSDW", "VPMOVSQB", + "VPMOVSQD", "VPMOVSQW", "VPMOVSWB", "VPMOVSXBD", "VPMOVSXBQ", + "VPMOVSXBW", "VPMOVSXDQ", "VPMOVSXWD", "VPMOVSXWQ", "VPMOVUSDB", + "VPMOVUSDW", "VPMOVUSQB", "VPMOVUSQD", "VPMOVUSQW", "VPMOVUSWB", + "VPMOVW2M", "VPMOVWB", "VPMOVZXBD", "VPMOVZXBQ", "VPMOVZXBW", + "VPMOVZXDQ", "VPMOVZXWD", "VPMOVZXWQ", "VPMULDQ", "VPMULHRSW", + "VPMULHUW", "VPMULHW", "VPMULLD", "VPMULLQ", "VPMULLW", "VPMULTISHIFTQB", + "VPMULUDQ", "VPOPCNTB", "VPOPCNTD", "VPOPCNTQ", "VPOPCNTW", "VPOR", + "VPORD", "VPORQ", "VPPERM", "VPROLD", "VPROLQ", "VPROLVD", "VPROLVQ", + "VPRORD", "VPRORQ", "VPRORVD", "VPRORVQ", "VPROTB", "VPROTD", + "VPROTQ", "VPROTW", "VPSADBW", "VPSCATTERDD", "VPSCATTERDQ", + "VPSCATTERQD", "VPSCATTERQQ", "VPSHAB", "VPSHAD", "VPSHAQ", "VPSHAW", + "VPSHLB", "VPSHLD", "VPSHLDD", "VPSHLDQ", "VPSHLDVD", "VPSHLDVQ", + "VPSHLDVW", "VPSHLDW", "VPSHLQ", "VPSHLW", "VPSHRDD", "VPSHRDQ", + "VPSHRDVD", "VPSHRDVQ", "VPSHRDVW", "VPSHRDW", "VPSHUFB", "VPSHUFBITQMB", + "VPSHUFD", "VPSHUFHW", "VPSHUFLW", "VPSIGNB", "VPSIGND", "VPSIGNW", + "VPSLLD", "VPSLLDQ", "VPSLLQ", "VPSLLVD", "VPSLLVQ", "VPSLLVW", + "VPSLLW", "VPSRAD", "VPSRAQ", "VPSRAVD", "VPSRAVQ", "VPSRAVW", + "VPSRAW", "VPSRLD", "VPSRLDQ", "VPSRLQ", "VPSRLVD", "VPSRLVQ", + "VPSRLVW", "VPSRLW", "VPSUBB", "VPSUBD", "VPSUBQ", "VPSUBSB", + "VPSUBSW", "VPSUBUSB", "VPSUBUSW", "VPSUBW", "VPTERNLOGD", "VPTERNLOGQ", + "VPTEST", "VPTESTMB", "VPTESTMD", "VPTESTMQ", "VPTESTMW", "VPTESTNMB", + "VPTESTNMD", "VPTESTNMQ", "VPTESTNMW", "VPUNPCKHBW", "VPUNPCKHDQ", + "VPUNPCKHQDQ", "VPUNPCKHWD", "VPUNPCKLBW", "VPUNPCKLDQ", "VPUNPCKLQDQ", + "VPUNPCKLWD", "VPXOR", "VPXORD", "VPXORQ", "VRANGEPD", "VRANGEPS", + "VRANGESD", "VRANGESS", "VRCP14PD", "VRCP14PS", "VRCP14SD", "VRCP14SS", + "VRCP28PD", "VRCP28PS", "VRCP28SD", "VRCP28SS", "VRCPPBF16", + "VRCPPH", "VRCPPS", "VRCPSH", "VRCPSS", "VREDUCENEPBF16", "VREDUCEPD", + "VREDUCEPH", "VREDUCEPS", "VREDUCESD", "VREDUCESH", "VREDUCESS", + "VRNDSCALENEPBF16", "VRNDSCALEPD", "VRNDSCALEPH", "VRNDSCALEPS", + "VRNDSCALESD", "VRNDSCALESH", "VRNDSCALESS", "VROUNDPD", "VROUNDPS", + "VROUNDSD", "VROUNDSS", "VRSQRT14PD", "VRSQRT14PS", "VRSQRT14SD", + "VRSQRT14SS", "VRSQRT28PD", "VRSQRT28PS", "VRSQRT28SD", "VRSQRT28SS", + "VRSQRTPBF16", "VRSQRTPH", "VRSQRTPS", "VRSQRTSH", "VRSQRTSS", + "VSCALEFPBF16", "VSCALEFPD", "VSCALEFPH", "VSCALEFPS", "VSCALEFSD", + "VSCALEFSH", "VSCALEFSS", "VSCATTERDPD", "VSCATTERDPS", "VSCATTERPF0DPD", + "VSCATTERPF0DPS", "VSCATTERPF0QPD", "VSCATTERPF0QPS", "VSCATTERPF1DPD", + "VSCATTERPF1DPS", "VSCATTERPF1QPD", "VSCATTERPF1QPS", "VSCATTERQPD", + "VSCATTERQPS", "VSHA512MSG1", "VSHA512MSG2", "VSHA512RNDS2", + "VSHUFF32X4", "VSHUFF64X2", "VSHUFI32X4", "VSHUFI64X2", "VSHUFPD", + "VSHUFPS", "VSM3MSG1", "VSM3MSG2", "VSM3RNDS2", "VSM4KEY4", "VSM4RNDS4", + "VSQRTNEPBF16", "VSQRTPD", "VSQRTPH", "VSQRTPS", "VSQRTSD", "VSQRTSH", + "VSQRTSS", "VSTMXCSR", "VSUBNEPBF16", "VSUBPD", "VSUBPH", "VSUBPS", + "VSUBSD", "VSUBSH", "VSUBSS", "VTESTPD", "VTESTPS", "VUCOMISD", + "VUCOMISH", "VUCOMISS", "VUCOMXSD", "VUCOMXSH", "VUCOMXSS", "VUNPCKHPD", + "VUNPCKHPS", "VUNPCKLPD", "VUNPCKLPS", "VXORPD", "VXORPS", "VZEROALL", + "VZEROUPPER", "WAIT", "WBINVD", "WBNOINVD", "WRFSBASE", "WRGSBASE", + "WRMSR", "WRMSRLIST", "WRMSRNS", "WRPKRU", "WRSSD", "WRSSQ", + "WRUSSD", "WRUSSQ", "XABORT", "XADD", "XBEGIN", "XCHG", "XEND", + "XGETBV", "XLATB", "XOR", "XORPD", "XORPS", "XRESLDTRK", "XRSTOR", + "XRSTOR64", "XRSTORS", "XRSTORS64", "XSAVE", "XSAVE64", "XSAVEC", + "XSAVEC64", "XSAVEOPT", "XSAVEOPT64", "XSAVES", "XSAVES64", "XSETBV", + "XSUSLDTRK", "XTEST", }; #endif // !BDDISASM_NO_MNEMONIC diff --git a/bddisasm/include/bdx86_table_evex.h b/bddisasm/include/bdx86_table_evex.h index 872303f..aed26d1 100644 --- a/bddisasm/include/bdx86_table_evex.h +++ b/bddisasm/include/bdx86_table_evex.h @@ -13,7 +13,7 @@ const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_07_opcode_f8_pp_03_modrmreg_00_modrmmod_01_l_00_w_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2634] // URDMSR Rq,Id + (const void *)&gInstructions[ 2675] // URDMSR Rq,Id }; const ND_TABLE_EX_NF gEvexMap_mmmmm_07_opcode_f8_pp_03_modrmreg_00_modrmmod_01_l_00_w_00_nf = @@ -72,7 +72,7 @@ const ND_TABLE_MODRM_REG gEvexMap_mmmmm_07_opcode_f8_pp_03_modrmreg = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_07_opcode_f8_pp_02_modrmreg_00_modrmmod_01_l_00_w_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2638] // UWRMSR Id,Rq + (const void *)&gInstructions[ 2679] // UWRMSR Id,Rq }; const ND_TABLE_EX_NF gEvexMap_mmmmm_07_opcode_f8_pp_02_modrmreg_00_modrmmod_01_l_00_w_00_nf = @@ -139,6 +139,135 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_07_opcode_f8_pp = } }; +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_07_opcode_f6_pp_03_modrmreg_00_modrmmod_01_l_00_w_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2078] // RDMSR Rq,Id +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_07_opcode_f6_pp_03_modrmreg_00_modrmmod_01_l_00_w_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_07_opcode_f6_pp_03_modrmreg_00_modrmmod_01_l_00_w_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_07_opcode_f6_pp_03_modrmreg_00_modrmmod_01_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_07_opcode_f6_pp_03_modrmreg_00_modrmmod_01_l_00_w_00_nf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_07_opcode_f6_pp_03_modrmreg_00_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_07_opcode_f6_pp_03_modrmreg_00_modrmmod_01_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_07_opcode_f6_pp_03_modrmreg_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_07_opcode_f6_pp_03_modrmreg_00_modrmmod_01_l, + } +}; + +const ND_TABLE_MODRM_REG gEvexMap_mmmmm_07_opcode_f6_pp_03_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_07_opcode_f6_pp_03_modrmreg_00_modrmmod, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_07_opcode_f6_pp_02_modrmreg_00_modrmmod_01_l_00_w_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 4105] // WRMSRNS Id,Rq +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_07_opcode_f6_pp_02_modrmreg_00_modrmmod_01_l_00_w_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_07_opcode_f6_pp_02_modrmreg_00_modrmmod_01_l_00_w_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_07_opcode_f6_pp_02_modrmreg_00_modrmmod_01_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_07_opcode_f6_pp_02_modrmreg_00_modrmmod_01_l_00_w_00_nf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_07_opcode_f6_pp_02_modrmreg_00_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_07_opcode_f6_pp_02_modrmreg_00_modrmmod_01_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_07_opcode_f6_pp_02_modrmreg_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_07_opcode_f6_pp_02_modrmreg_00_modrmmod_01_l, + } +}; + +const ND_TABLE_MODRM_REG gEvexMap_mmmmm_07_opcode_f6_pp_02_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_07_opcode_f6_pp_02_modrmreg_00_modrmmod, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_07_opcode_f6_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gEvexMap_mmmmm_07_opcode_f6_pp_02_modrmreg, + /* 03 */ (const void *)&gEvexMap_mmmmm_07_opcode_f6_pp_03_modrmreg, + } +}; + const ND_TABLE_OPCODE gEvexMap_mmmmm_07_opcode = { ND_ILUT_OPCODE, @@ -389,7 +518,7 @@ const ND_TABLE_OPCODE gEvexMap_mmmmm_07_opcode = /* f3 */ (const void *)ND_NULL, /* f4 */ (const void *)ND_NULL, /* f5 */ (const void *)ND_NULL, - /* f6 */ (const void *)ND_NULL, + /* f6 */ (const void *)&gEvexMap_mmmmm_07_opcode_f6_pp, /* f7 */ (const void *)ND_NULL, /* f8 */ (const void *)&gEvexMap_mmmmm_07_opcode_f8_pp, /* f9 */ (const void *)ND_NULL, @@ -405,7 +534,7 @@ const ND_TABLE_OPCODE gEvexMap_mmmmm_07_opcode = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_d7_pp_03_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2907] // VFCMULCSH Vdq{K}{z},aKq,Hdq,Wd{er} + (const void *)&gInstructions[ 2948] // VFCMULCSH Vdq{K}{z},aKq,Hdq,Wd{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_d7_pp_03_w = @@ -420,7 +549,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_d7_pp_03_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_d7_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3035] // VFMULCSH Vdq{K}{z},aKq,Hdq,Wd{er} + (const void *)&gInstructions[ 3076] // VFMULCSH Vdq{K}{z},aKq,Hdq,Wd{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_d7_pp_02_w = @@ -446,7 +575,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_d7_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_d6_pp_03_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2906] // VFCMULCPH Vfv{K}{z},aKq,Hfv,Wfv|B32{er} + (const void *)&gInstructions[ 2947] // VFCMULCPH Vfv{K}{z},aKq,Hfv,Wfv|B32{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_d6_pp_03_w = @@ -461,7 +590,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_d6_pp_03_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_d6_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3034] // VFMULCPH Vfv{K}{z},aKq,Hfv,Wfv|B32{er} + (const void *)&gInstructions[ 3075] // VFMULCPH Vfv{K}{z},aKq,Hfv,Wfv|B32{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_d6_pp_02_w = @@ -487,7 +616,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_d6_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_bf_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3107] // VFNMSUB231SH Vdq{K}{z},aKq,Hdq,Wsh{er} + (const void *)&gInstructions[ 3148] // VFNMSUB231SH Vdq{K}{z},aKq,Hdq,Wsh{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_bf_pp_01_w = @@ -513,7 +642,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_bf_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_be_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3102] // VFNMSUB231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} + (const void *)&gInstructions[ 3143] // VFNMSUB231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_be_pp_01_w = @@ -528,7 +657,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_be_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_be_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3099] // VFNMSUB231NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16 + (const void *)&gInstructions[ 3140] // VFNMSUB231NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16 }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_be_pp_00_w = @@ -554,7 +683,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_be_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_bd_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3066] // VFNMADD231SH Vdq{K}{z},aKq,Hdq,Wsh{er} + (const void *)&gInstructions[ 3107] // VFNMADD231SH Vdq{K}{z},aKq,Hdq,Wsh{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_bd_pp_01_w = @@ -580,7 +709,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_bd_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_bc_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3061] // VFNMADD231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} + (const void *)&gInstructions[ 3102] // VFNMADD231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_bc_pp_01_w = @@ -595,7 +724,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_bc_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_bc_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3058] // VFNMADD231NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16 + (const void *)&gInstructions[ 3099] // VFNMADD231NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16 }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_bc_pp_00_w = @@ -621,7 +750,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_bc_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_bb_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3004] // VFMSUB231SH Vdq{K}{z},aKq,Hdq,Wsh{er} + (const void *)&gInstructions[ 3045] // VFMSUB231SH Vdq{K}{z},aKq,Hdq,Wsh{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_bb_pp_01_w = @@ -647,7 +776,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_bb_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_ba_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2999] // VFMSUB231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} + (const void *)&gInstructions[ 3040] // VFMSUB231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_ba_pp_01_w = @@ -662,7 +791,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_ba_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_ba_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2996] // VFMSUB231NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16 + (const void *)&gInstructions[ 3037] // VFMSUB231NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16 }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_ba_pp_00_w = @@ -688,7 +817,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_ba_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_b9_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2942] // VFMADD231SH Vdq{K}{z},aKq,Hdq,Wsh{er} + (const void *)&gInstructions[ 2983] // VFMADD231SH Vdq{K}{z},aKq,Hdq,Wsh{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_b9_pp_01_w = @@ -714,7 +843,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_b9_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_b8_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2937] // VFMADD231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} + (const void *)&gInstructions[ 2978] // VFMADD231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_b8_pp_01_w = @@ -729,7 +858,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_b8_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_b8_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2934] // VFMADD231NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16 + (const void *)&gInstructions[ 2975] // VFMADD231NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16 }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_b8_pp_00_w = @@ -755,7 +884,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_b8_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_b7_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3019] // VFMSUBADD231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} + (const void *)&gInstructions[ 3060] // VFMSUBADD231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_b7_pp_01_w = @@ -781,7 +910,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_b7_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_b6_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2967] // VFMADDSUB231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} + (const void *)&gInstructions[ 3008] // VFMADDSUB231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_b6_pp_01_w = @@ -807,7 +936,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_b6_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_af_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3096] // VFNMSUB213SH Vdq{K}{z},aKq,Hdq,Wsh{er} + (const void *)&gInstructions[ 3137] // VFNMSUB213SH Vdq{K}{z},aKq,Hdq,Wsh{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_af_pp_01_w = @@ -833,7 +962,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_af_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_ae_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3091] // VFNMSUB213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} + (const void *)&gInstructions[ 3132] // VFNMSUB213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_ae_pp_01_w = @@ -848,7 +977,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_ae_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_ae_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3088] // VFNMSUB213NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16 + (const void *)&gInstructions[ 3129] // VFNMSUB213NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16 }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_ae_pp_00_w = @@ -874,7 +1003,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_ae_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_ad_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3055] // VFNMADD213SH Vdq{K}{z},aKq,Hdq,Wsh{er} + (const void *)&gInstructions[ 3096] // VFNMADD213SH Vdq{K}{z},aKq,Hdq,Wsh{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_ad_pp_01_w = @@ -900,7 +1029,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_ad_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_ac_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3050] // VFNMADD213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} + (const void *)&gInstructions[ 3091] // VFNMADD213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_ac_pp_01_w = @@ -915,7 +1044,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_ac_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_ac_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3047] // VFNMADD213NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16 + (const void *)&gInstructions[ 3088] // VFNMADD213NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16 }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_ac_pp_00_w = @@ -941,7 +1070,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_ac_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_ab_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2993] // VFMSUB213SH Vdq{K}{z},aKq,Hdq,Wsh{er} + (const void *)&gInstructions[ 3034] // VFMSUB213SH Vdq{K}{z},aKq,Hdq,Wsh{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_ab_pp_01_w = @@ -967,7 +1096,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_ab_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_aa_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2988] // VFMSUB213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} + (const void *)&gInstructions[ 3029] // VFMSUB213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_aa_pp_01_w = @@ -982,7 +1111,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_aa_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_aa_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2985] // VFMSUB213NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16 + (const void *)&gInstructions[ 3026] // VFMSUB213NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16 }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_aa_pp_00_w = @@ -1008,7 +1137,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_aa_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_a9_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2931] // VFMADD213SH Vdq{K}{z},aKq,Hdq,Wsh{er} + (const void *)&gInstructions[ 2972] // VFMADD213SH Vdq{K}{z},aKq,Hdq,Wsh{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_a9_pp_01_w = @@ -1034,7 +1163,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_a9_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_a8_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2926] // VFMADD213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} + (const void *)&gInstructions[ 2967] // VFMADD213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_a8_pp_01_w = @@ -1049,7 +1178,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_a8_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_a8_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2923] // VFMADD213NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16 + (const void *)&gInstructions[ 2964] // VFMADD213NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16 }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_a8_pp_00_w = @@ -1075,7 +1204,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_a8_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_a7_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3014] // VFMSUBADD213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} + (const void *)&gInstructions[ 3055] // VFMSUBADD213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_a7_pp_01_w = @@ -1101,7 +1230,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_a7_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_a6_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2962] // VFMADDSUB213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} + (const void *)&gInstructions[ 3003] // VFMADDSUB213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_a6_pp_01_w = @@ -1127,7 +1256,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_a6_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_9f_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3085] // VFNMSUB132SH Vdq{K}{z},aKq,Hdq,Wsh{er} + (const void *)&gInstructions[ 3126] // VFNMSUB132SH Vdq{K}{z},aKq,Hdq,Wsh{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_9f_pp_01_w = @@ -1153,7 +1282,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_9f_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_9e_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3080] // VFNMSUB132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} + (const void *)&gInstructions[ 3121] // VFNMSUB132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_9e_pp_01_w = @@ -1168,7 +1297,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_9e_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_9e_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3077] // VFNMSUB132NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16 + (const void *)&gInstructions[ 3118] // VFNMSUB132NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16 }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_9e_pp_00_w = @@ -1194,7 +1323,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_9e_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_9d_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3044] // VFNMADD132SH Vdq{K}{z},aKq,Hdq,Wsh{er} + (const void *)&gInstructions[ 3085] // VFNMADD132SH Vdq{K}{z},aKq,Hdq,Wsh{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_9d_pp_01_w = @@ -1220,7 +1349,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_9d_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_9c_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3039] // VFNMADD132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} + (const void *)&gInstructions[ 3080] // VFNMADD132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_9c_pp_01_w = @@ -1235,7 +1364,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_9c_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_9c_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3036] // VFNMADD132NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16 + (const void *)&gInstructions[ 3077] // VFNMADD132NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16 }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_9c_pp_00_w = @@ -1261,7 +1390,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_9c_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_9b_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2982] // VFMSUB132SH Vdq{K}{z},aKq,Hdq,Wsh{er} + (const void *)&gInstructions[ 3023] // VFMSUB132SH Vdq{K}{z},aKq,Hdq,Wsh{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_9b_pp_01_w = @@ -1287,7 +1416,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_9b_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_9a_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2977] // VFMSUB132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} + (const void *)&gInstructions[ 3018] // VFMSUB132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_9a_pp_01_w = @@ -1302,7 +1431,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_9a_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_9a_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2974] // VFMSUB132NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16 + (const void *)&gInstructions[ 3015] // VFMSUB132NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16 }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_9a_pp_00_w = @@ -1328,7 +1457,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_9a_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_99_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2920] // VFMADD132SH Vdq{K}{z},aKq,Hdq,Wsh{er} + (const void *)&gInstructions[ 2961] // VFMADD132SH Vdq{K}{z},aKq,Hdq,Wsh{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_99_pp_01_w = @@ -1354,7 +1483,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_99_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_98_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2915] // VFMADD132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} + (const void *)&gInstructions[ 2956] // VFMADD132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_98_pp_01_w = @@ -1369,7 +1498,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_98_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_98_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2912] // VFMADD132NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16 + (const void *)&gInstructions[ 2953] // VFMADD132NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16 }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_98_pp_00_w = @@ -1395,7 +1524,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_98_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_97_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3009] // VFMSUBADD132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} + (const void *)&gInstructions[ 3050] // VFMSUBADD132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_97_pp_01_w = @@ -1421,7 +1550,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_97_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_96_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2957] // VFMADDSUB132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} + (const void *)&gInstructions[ 2998] // VFMADDSUB132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_96_pp_01_w = @@ -1447,7 +1576,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_96_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_57_pp_03_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2905] // VFCMADDCSH Vdq{K}{z},aKq,Hdq,Wd{er} + (const void *)&gInstructions[ 2946] // VFCMADDCSH Vdq{K}{z},aKq,Hdq,Wd{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_57_pp_03_w = @@ -1462,7 +1591,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_57_pp_03_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_57_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2946] // VFMADDCSH Vdq{K}{z},aKq,Hdq,Wd{er} + (const void *)&gInstructions[ 2987] // VFMADDCSH Vdq{K}{z},aKq,Hdq,Wd{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_57_pp_02_w = @@ -1488,7 +1617,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_57_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_56_pp_03_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2904] // VFCMADDCPH Vfv{K}{z},aKq,Hfv,Wfv|B32{er} + (const void *)&gInstructions[ 2945] // VFCMADDCPH Vfv{K}{z},aKq,Hfv,Wfv|B32{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_56_pp_03_w = @@ -1503,7 +1632,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_56_pp_03_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_56_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2945] // VFMADDCPH Vfv{K}{z},aKq,Hfv,Wfv|B32{er} + (const void *)&gInstructions[ 2986] // VFMADDCPH Vfv{K}{z},aKq,Hfv,Wfv|B32{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_56_pp_02_w = @@ -1529,7 +1658,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_56_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_4f_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3967] // VRSQRTSH Vdq{K}{z},aKq,Hdq,Wsh + (const void *)&gInstructions[ 4012] // VRSQRTSH Vdq{K}{z},aKq,Hdq,Wsh }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_4f_pp_01_w = @@ -1555,7 +1684,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_4f_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_4e_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3965] // VRSQRTPH Vfv{K}{z},aKq,Wfv|B16 + (const void *)&gInstructions[ 4010] // VRSQRTPH Vfv{K}{z},aKq,Wfv|B16 }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_4e_pp_01_w = @@ -1570,7 +1699,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_4e_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_4e_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3964] // VRSQRTPBF16 Vfv{K}{z},aKq,Wfv|B16 + (const void *)&gInstructions[ 4009] // VRSQRTPBF16 Vfv{K}{z},aKq,Wfv|B16 }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_4e_pp_00_w = @@ -1596,7 +1725,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_4e_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_4d_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3936] // VRCPSH Vdq{K}{z},aKq,Hdq,Wsh + (const void *)&gInstructions[ 3981] // VRCPSH Vdq{K}{z},aKq,Hdq,Wsh }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_4d_pp_01_w = @@ -1622,7 +1751,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_4d_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_4c_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3934] // VRCPPH Vfv{K}{z},aKq,Wfv|B16 + (const void *)&gInstructions[ 3979] // VRCPPH Vfv{K}{z},aKq,Wfv|B16 }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_4c_pp_01_w = @@ -1637,7 +1766,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_4c_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_4c_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3933] // VRCPPBF16 Vfv{K}{z},aKq,Wfv|B16 + (const void *)&gInstructions[ 3978] // VRCPPBF16 Vfv{K}{z},aKq,Wfv|B16 }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_4c_pp_00_w = @@ -1663,7 +1792,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_4c_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_43_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3150] // VGETEXPSH Vdq{K}{z},aKq,Hdq,Wsh{sae} + (const void *)&gInstructions[ 3191] // VGETEXPSH Vdq{K}{z},aKq,Hdq,Wsh{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_43_pp_01_w = @@ -1689,7 +1818,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_43_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_42_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3147] // VGETEXPPH Vfv{K}{z},aKq,Wfv|B16{sae} + (const void *)&gInstructions[ 3188] // VGETEXPPH Vfv{K}{z},aKq,Wfv|B16{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_42_pp_01_w = @@ -1701,11 +1830,26 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_42_pp_01_w = } }; +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_42_pp_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3186] // VGETEXPPBF16 Vfv{K}{z},aKq,Wfv|B16 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_42_pp_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_42_pp_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_42_pp = { ND_ILUT_EX_PP, { - /* 00 */ (const void *)ND_NULL, + /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_42_pp_00_w, /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_42_pp_01_w, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, @@ -1715,7 +1859,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_42_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_2d_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3974] // VSCALEFSH Vdq{K}{z},aKq,Hdq,Wsh{er} + (const void *)&gInstructions[ 4019] // VSCALEFSH Vdq{K}{z},aKq,Hdq,Wsh{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_2d_pp_01_w = @@ -1741,7 +1885,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_2d_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_2c_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3971] // VSCALEFPH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} + (const void *)&gInstructions[ 4016] // VSCALEFPH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_2c_pp_01_w = @@ -1756,7 +1900,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_2c_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_2c_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3969] // VSCALEFPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16 + (const void *)&gInstructions[ 4014] // VSCALEFPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16 }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_2c_pp_00_w = @@ -1782,7 +1926,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_2c_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_13_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2769] // VCVTPH2PSX Vfv{K}{z},aKq,Whv|B16{sae} + (const void *)&gInstructions[ 2810] // VCVTPH2PSX Vfv{K}{z},aKq,Whv|B16{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_13_pp_01_w = @@ -1797,7 +1941,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_13_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_13_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2800] // VCVTSH2SS Vdq{K}{z},aKq,Hdq,Wsh{sae} + (const void *)&gInstructions[ 2841] // VCVTSH2SS Vdq{K}{z},aKq,Hdq,Wsh{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_13_pp_00_w = @@ -2086,7 +2230,7 @@ const ND_TABLE_OPCODE gEvexMap_mmmmm_06_opcode = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_7e_pp_02_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3338] // VMOVW Ww,Vdq + (const void *)&gInstructions[ 3383] // VMOVW Ww,Vdq }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_7e_pp_02_l_00_w = @@ -2112,7 +2256,7 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_05_opcode_7e_pp_02_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_7e_pp_01_modrmmod_01_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3337] // VMOVW Rd,Vdq + (const void *)&gInstructions[ 3382] // VMOVW Rd,Vdq }; const ND_TABLE_EX_L gEvexMap_mmmmm_05_opcode_7e_pp_01_modrmmod_01_l = @@ -2129,7 +2273,7 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_05_opcode_7e_pp_01_modrmmod_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_7e_pp_01_modrmmod_00_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3336] // VMOVW Mw,Vdq + (const void *)&gInstructions[ 3381] // VMOVW Mw,Vdq }; const ND_TABLE_EX_L gEvexMap_mmmmm_05_opcode_7e_pp_01_modrmmod_00_l = @@ -2166,7 +2310,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_7e_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_7d_pp_03_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2866] // VCVTUW2PH Vfv{K}{z},aKq,Wfv|B16{er} + (const void *)&gInstructions[ 2907] // VCVTUW2PH Vfv{K}{z},aKq,Wfv|B16{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_7d_pp_03_w = @@ -2181,7 +2325,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_7d_pp_03_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_7d_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2867] // VCVTW2PH Vfv{K}{z},aKq,Wfv|B16{er} + (const void *)&gInstructions[ 2908] // VCVTW2PH Vfv{K}{z},aKq,Wfv|B16{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_7d_pp_02_w = @@ -2196,7 +2340,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_7d_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_7d_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2774] // VCVTPH2W Vfv{K}{z},aKq,Wfv|B16{er} + (const void *)&gInstructions[ 2815] // VCVTPH2W Vfv{K}{z},aKq,Wfv|B16{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_7d_pp_01_w = @@ -2211,7 +2355,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_7d_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_7d_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2773] // VCVTPH2UW Vfv{K}{z},aKq,Wfv|B16{er} + (const void *)&gInstructions[ 2814] // VCVTPH2UW Vfv{K}{z},aKq,Wfv|B16{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_7d_pp_00_w = @@ -2237,7 +2381,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_7d_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_7c_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2832] // VCVTTPH2W Vfv{K}{z},aKq,Wfv|B16{sae} + (const void *)&gInstructions[ 2873] // VCVTTPH2W Vfv{K}{z},aKq,Wfv|B16{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_7c_pp_01_w = @@ -2252,7 +2396,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_7c_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_7c_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2831] // VCVTTPH2UW Vfv{K}{z},aKq,Wfv|B16{sae} + (const void *)&gInstructions[ 2872] // VCVTTPH2UW Vfv{K}{z},aKq,Wfv|B16{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_7c_pp_00_w = @@ -2278,13 +2422,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_7c_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_7b_pp_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2864] // VCVTUSI2SH Vdq,Hdq,Ey{er} + (const void *)&gInstructions[ 2905] // VCVTUSI2SH Vdq,Hdq,Ey{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_7b_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2770] // VCVTPH2QQ Vfv{K}{z},aKq,Wqv|B16{er} + (const void *)&gInstructions[ 2811] // VCVTPH2QQ Vfv{K}{z},aKq,Wqv|B16{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_7b_pp_01_w = @@ -2310,13 +2454,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_7b_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_7a_pp_03_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2860] // VCVTUQQ2PH Vqv{K}{z},aKq,Wfv|B64{er} + (const void *)&gInstructions[ 2901] // VCVTUQQ2PH Vqv{K}{z},aKq,Wfv|B64{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_7a_pp_03_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2857] // VCVTUDQ2PH Vhv{K}{z},aKq,Wfv|B32{er} + (const void *)&gInstructions[ 2898] // VCVTUDQ2PH Vhv{K}{z},aKq,Wfv|B32{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_7a_pp_03_w = @@ -2331,7 +2475,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_7a_pp_03_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_7a_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2828] // VCVTTPH2QQ Vfv{K}{z},aKq,Wqv|B16{sae} + (const void *)&gInstructions[ 2869] // VCVTTPH2QQ Vfv{K}{z},aKq,Wqv|B16{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_7a_pp_01_w = @@ -2357,13 +2501,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_7a_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_79_pp_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2801] // VCVTSH2USI Gy,Wsh{er} + (const void *)&gInstructions[ 2842] // VCVTSH2USI Gy,Wsh{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_79_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2772] // VCVTPH2UQQ Vfv{K}{z},aKq,Wqv|B16{er} + (const void *)&gInstructions[ 2813] // VCVTPH2UQQ Vfv{K}{z},aKq,Wqv|B16{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_79_pp_01_w = @@ -2378,7 +2522,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_79_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_79_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2771] // VCVTPH2UDQ Vfv{K}{z},aKq,Whv|B16{er} + (const void *)&gInstructions[ 2812] // VCVTPH2UDQ Vfv{K}{z},aKq,Whv|B16{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_79_pp_00_w = @@ -2404,7 +2548,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_79_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_78_pp_02_wi_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2850] // VCVTTSH2USI Gy,Wsh{sae} + (const void *)&gInstructions[ 2891] // VCVTTSH2USI Gy,Wsh{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_78_pp_02_wi = @@ -2419,7 +2563,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_78_pp_02_wi = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_78_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2830] // VCVTTPH2UQQ Vfv{K}{z},aKq,Wqv|B16{sae} + (const void *)&gInstructions[ 2871] // VCVTTPH2UQQ Vfv{K}{z},aKq,Wqv|B16{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_78_pp_01_w = @@ -2434,7 +2578,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_78_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_78_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2829] // VCVTTPH2UDQ Vfv{K}{z},aKq,Whv|B16{sae} + (const void *)&gInstructions[ 2870] // VCVTTPH2UDQ Vfv{K}{z},aKq,Whv|B16{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_78_pp_00_w = @@ -2460,7 +2604,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_78_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_74_pp_03_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2737] // VCVTNE2PH2BF8S Vfv{K}{z},aKq,Hfv,Wfv|B16 + (const void *)&gInstructions[ 2778] // VCVTNE2PH2BF8S Vfv{K}{z},aKq,Hfv,Wfv|B16 }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_74_pp_03_w = @@ -2475,7 +2619,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_74_pp_03_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_74_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2748] // VCVTNEPH2BF8S Vhv{K}{z},aKq,Wfv|B16 + (const void *)&gInstructions[ 2789] // VCVTNEPH2BF8S Vhv{K}{z},aKq,Wfv|B16 }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_74_pp_02_w = @@ -2490,7 +2634,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_74_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_74_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2726] // VCVTBIASPH2BF8S Vhv{K}{z},aKq,Hfv,Wfv|B16 + (const void *)&gInstructions[ 2767] // VCVTBIASPH2BF8S Vhv{K}{z},aKq,Hfv,Wfv|B16 }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_74_pp_00_w = @@ -2513,10 +2657,81 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_74_pp = } }; +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_6f_pp_03_modrmmod_00_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3345] // VMOVRSW Vfv{K}{z},aKq,Wfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_6f_pp_03_modrmmod_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3342] // VMOVRSB Vfv{K}{z},aKq,Wfv +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_6f_pp_03_modrmmod_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_6f_pp_03_modrmmod_00_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_05_opcode_6f_pp_03_modrmmod_00_w_01_leaf, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_05_opcode_6f_pp_03_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_6f_pp_03_modrmmod_00_w, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_6f_pp_02_modrmmod_00_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3344] // VMOVRSQ Vfv{K}{z},aKq,Wfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_6f_pp_02_modrmmod_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3343] // VMOVRSD Vfv{K}{z},aKq,Wfv +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_6f_pp_02_modrmmod_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_6f_pp_02_modrmmod_00_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_05_opcode_6f_pp_02_modrmmod_00_w_01_leaf, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_05_opcode_6f_pp_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_6f_pp_02_modrmmod_00_w, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_6f_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gEvexMap_mmmmm_05_opcode_6f_pp_02_modrmmod, + /* 03 */ (const void *)&gEvexMap_mmmmm_05_opcode_6f_pp_03_modrmmod, + } +}; + const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_6e_pp_02_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3335] // VMOVW Vdq,Ww + (const void *)&gInstructions[ 3380] // VMOVW Vdq,Ww }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_6e_pp_02_l_00_w = @@ -2542,7 +2757,7 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_05_opcode_6e_pp_02_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_6e_pp_01_modrmmod_01_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3334] // VMOVW Vdq,Rd + (const void *)&gInstructions[ 3379] // VMOVW Vdq,Rd }; const ND_TABLE_EX_L gEvexMap_mmmmm_05_opcode_6e_pp_01_modrmmod_01_l = @@ -2559,7 +2774,7 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_05_opcode_6e_pp_01_modrmmod_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_6e_pp_01_modrmmod_00_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3333] // VMOVW Vdq,Mw + (const void *)&gInstructions[ 3378] // VMOVW Vdq,Mw }; const ND_TABLE_EX_L gEvexMap_mmmmm_05_opcode_6e_pp_01_modrmmod_00_l = @@ -2596,25 +2811,25 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_6e_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_6d_pp_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2846] // VCVTTSD2SIS Gy,Wsd{sae} + (const void *)&gInstructions[ 2887] // VCVTTSD2SIS Gy,Wsd{sae} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_6d_pp_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2853] // VCVTTSS2SIS Gy,Wss{sae} + (const void *)&gInstructions[ 2894] // VCVTTSS2SIS Gy,Wss{sae} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_6d_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2820] // VCVTTPD2QQS Vfv{K}{z},aKq,Wfv|B64{sae} + (const void *)&gInstructions[ 2861] // VCVTTPD2QQS Vfv{K}{z},aKq,Wfv|B64{sae} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_6d_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2839] // VCVTTPS2QQS Vfv{K}{z},aKq,Whv|B32{sae} + (const void *)&gInstructions[ 2880] // VCVTTPS2QQS Vfv{K}{z},aKq,Whv|B32{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_6d_pp_01_w = @@ -2629,13 +2844,13 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_6d_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_6d_pp_00_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2818] // VCVTTPD2DQS Vhv{K}{z},aKq,Wfv|B64{sae} + (const void *)&gInstructions[ 2859] // VCVTTPD2DQS Vhv{K}{z},aKq,Wfv|B64{sae} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_6d_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2835] // VCVTTPS2DQS Vfv{K}{z},aKq,Wfv|B32{sae} + (const void *)&gInstructions[ 2876] // VCVTTPS2DQS Vfv{K}{z},aKq,Wfv|B32{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_6d_pp_00_w = @@ -2661,25 +2876,25 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_6d_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_6c_pp_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2848] // VCVTTSD2USIS Gy,Wsd{sae} + (const void *)&gInstructions[ 2889] // VCVTTSD2USIS Gy,Wsd{sae} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_6c_pp_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2855] // VCVTTSS2USIS Gy,Wss{sae} + (const void *)&gInstructions[ 2896] // VCVTTSS2USIS Gy,Wss{sae} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_6c_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2824] // VCVTTPD2UQQS Vfv{K}{z},aKq,Wfv|B64{sae} + (const void *)&gInstructions[ 2865] // VCVTTPD2UQQS Vfv{K}{z},aKq,Wfv|B64{sae} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_6c_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2843] // VCVTTPS2UQQS Vfv{K}{z},aKq,Whv|B32{sae} + (const void *)&gInstructions[ 2884] // VCVTTPS2UQQS Vfv{K}{z},aKq,Whv|B32{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_6c_pp_01_w = @@ -2694,13 +2909,13 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_6c_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_6c_pp_00_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2822] // VCVTTPD2UDQS Vhv{K}{z},aKq,Wfv|B64{sae} + (const void *)&gInstructions[ 2863] // VCVTTPD2UDQS Vhv{K}{z},aKq,Wfv|B64{sae} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_6c_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2841] // VCVTTPS2UDQS Vfv{K}{z},aKq,Wfv|B32{sae} + (const void *)&gInstructions[ 2882] // VCVTTPS2UDQS Vfv{K}{z},aKq,Wfv|B32{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_6c_pp_00_w = @@ -2726,7 +2941,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_6c_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_6b_pp_03_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2742] // VCVTNEBF162IUBS Vfv{K}{z},aKq,Wfv|B16 + (const void *)&gInstructions[ 2783] // VCVTNEBF162IUBS Vfv{K}{z},aKq,Wfv|B16 }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_6b_pp_03_w = @@ -2741,7 +2956,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_6b_pp_03_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_6b_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2778] // VCVTPS2IUBS Vfv{K}{z},aKq,Wfv|B32{er} + (const void *)&gInstructions[ 2819] // VCVTPS2IUBS Vfv{K}{z},aKq,Wfv|B32{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_6b_pp_01_w = @@ -2756,7 +2971,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_6b_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_6b_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2764] // VCVTPH2IUBS Vfv{K}{z},aKq,Wfv|B16{er} + (const void *)&gInstructions[ 2805] // VCVTPH2IUBS Vfv{K}{z},aKq,Wfv|B16{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_6b_pp_00_w = @@ -2782,7 +2997,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_6b_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_6a_pp_03_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2815] // VCVTTNEBF162IUBS Vfv{K}{z},aKq,Wfv|B16 + (const void *)&gInstructions[ 2856] // VCVTTNEBF162IUBS Vfv{K}{z},aKq,Wfv|B16 }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_6a_pp_03_w = @@ -2797,7 +3012,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_6a_pp_03_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_6a_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2837] // VCVTTPS2IUBS Vfv{K}{z},aKq,Wfv|B32{sae} + (const void *)&gInstructions[ 2878] // VCVTTPS2IUBS Vfv{K}{z},aKq,Wfv|B32{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_6a_pp_01_w = @@ -2812,7 +3027,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_6a_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_6a_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2827] // VCVTTPH2IUBS Vfv{K}{z},aKq,Wfv|B16{sae} + (const void *)&gInstructions[ 2868] // VCVTTPH2IUBS Vfv{K}{z},aKq,Wfv|B16{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_6a_pp_00_w = @@ -2838,7 +3053,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_6a_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_69_pp_03_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2741] // VCVTNEBF162IBS Vfv{K}{z},aKq,Wfv|B16 + (const void *)&gInstructions[ 2782] // VCVTNEBF162IBS Vfv{K}{z},aKq,Wfv|B16 }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_69_pp_03_w = @@ -2853,7 +3068,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_69_pp_03_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_69_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2777] // VCVTPS2IBS Vfv{K}{z},aKq,Wfv|B32{er} + (const void *)&gInstructions[ 2818] // VCVTPS2IBS Vfv{K}{z},aKq,Wfv|B32{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_69_pp_01_w = @@ -2868,7 +3083,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_69_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_69_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2763] // VCVTPH2IBS Vfv{K}{z},aKq,Wfv|B16{er} + (const void *)&gInstructions[ 2804] // VCVTPH2IBS Vfv{K}{z},aKq,Wfv|B16{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_69_pp_00_w = @@ -2894,7 +3109,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_69_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_68_pp_03_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2814] // VCVTTNEBF162IBS Vfv{K}{z},aKq,Wfv|B16 + (const void *)&gInstructions[ 2855] // VCVTTNEBF162IBS Vfv{K}{z},aKq,Wfv|B16 }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_68_pp_03_w = @@ -2909,7 +3124,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_68_pp_03_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_68_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2836] // VCVTTPS2IBS Vfv{K}{z},aKq,Wfv|B32{sae} + (const void *)&gInstructions[ 2877] // VCVTTPS2IBS Vfv{K}{z},aKq,Wfv|B32{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_68_pp_01_w = @@ -2924,7 +3139,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_68_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_68_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2826] // VCVTTPH2IBS Vfv{K}{z},aKq,Wfv|B16{sae} + (const void *)&gInstructions[ 2867] // VCVTTPH2IBS Vfv{K}{z},aKq,Wfv|B16{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_68_pp_00_w = @@ -2950,7 +3165,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_68_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_5f_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3198] // VMAXSH Vdq{K}{z},aKq,Hdq,Wsh{sae} + (const void *)&gInstructions[ 3239] // VMAXSH Vdq{K}{z},aKq,Hdq,Wsh{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5f_pp_02_w = @@ -2965,7 +3180,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5f_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_5f_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3190] // VMAXPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16 + (const void *)&gInstructions[ 3231] // VMAXPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16 }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5f_pp_01_w = @@ -2980,7 +3195,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5f_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_5f_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3193] // VMAXPH Vfv{K}{z},aKq,Hfv,Wfv|B16{sae} + (const void *)&gInstructions[ 3234] // VMAXPH Vfv{K}{z},aKq,Hfv,Wfv|B16{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5f_pp_00_w = @@ -3006,7 +3221,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_5f_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_5e_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2877] // VDIVSH Vdq{K}{z},aKq,Hdq,Wsh{er} + (const void *)&gInstructions[ 2918] // VDIVSH Vdq{K}{z},aKq,Hdq,Wsh{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5e_pp_02_w = @@ -3021,7 +3236,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5e_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_5e_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2869] // VDIVNEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16 + (const void *)&gInstructions[ 2910] // VDIVNEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16 }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5e_pp_01_w = @@ -3036,7 +3251,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5e_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_5e_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2872] // VDIVPH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} + (const void *)&gInstructions[ 2913] // VDIVPH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5e_pp_00_w = @@ -3062,7 +3277,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_5e_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_5d_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3221] // VMINSH Vdq{K}{z},aKq,Hdq,Wsh{sae} + (const void *)&gInstructions[ 3262] // VMINSH Vdq{K}{z},aKq,Hdq,Wsh{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5d_pp_02_w = @@ -3077,7 +3292,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5d_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_5d_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3213] // VMINPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16 + (const void *)&gInstructions[ 3254] // VMINPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16 }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5d_pp_01_w = @@ -3092,7 +3307,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5d_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_5d_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3216] // VMINPH Vfv{K}{z},aKq,Hfv,Wfv|B16{sae} + (const void *)&gInstructions[ 3257] // VMINPH Vfv{K}{z},aKq,Hfv,Wfv|B16{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5d_pp_00_w = @@ -3118,7 +3333,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_5d_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_5c_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4024] // VSUBSH Vdq{K}{z},aKq,Hdq,Wsh{sae} + (const void *)&gInstructions[ 4071] // VSUBSH Vdq{K}{z},aKq,Hdq,Wsh{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5c_pp_02_w = @@ -3133,7 +3348,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5c_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_5c_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4016] // VSUBNEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16 + (const void *)&gInstructions[ 4063] // VSUBNEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16 }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5c_pp_01_w = @@ -3148,7 +3363,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5c_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_5c_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4019] // VSUBPH Vfv{K}{z},aKq,Hfv,Wfv|B16{sae} + (const void *)&gInstructions[ 4066] // VSUBPH Vfv{K}{z},aKq,Hfv,Wfv|B16{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5c_pp_00_w = @@ -3174,7 +3389,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_5c_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_5b_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2825] // VCVTTPH2DQ Vfv{K}{z},aKq,Whv|B16{sae} + (const void *)&gInstructions[ 2866] // VCVTTPH2DQ Vfv{K}{z},aKq,Whv|B16{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5b_pp_02_w = @@ -3189,7 +3404,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5b_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_5b_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2762] // VCVTPH2DQ Vfv{K}{z},aKq,Whv|B16{er} + (const void *)&gInstructions[ 2803] // VCVTPH2DQ Vfv{K}{z},aKq,Whv|B16{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5b_pp_01_w = @@ -3204,13 +3419,13 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5b_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_5b_pp_00_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2790] // VCVTQQ2PH Vdq{K}{z},aKq,Wfv|B64{er} + (const void *)&gInstructions[ 2831] // VCVTQQ2PH Vdq{K}{z},aKq,Wfv|B64{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_5b_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2732] // VCVTDQ2PH Vhv{K}{z},aKq,Wfv|B32{er} + (const void *)&gInstructions[ 2773] // VCVTDQ2PH Vhv{K}{z},aKq,Wfv|B32{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5b_pp_00_w = @@ -3236,7 +3451,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_5b_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_5a_pp_03_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2792] // VCVTSD2SH Vdq{K}{z},aKq,Hdq,Wsd{er} + (const void *)&gInstructions[ 2833] // VCVTSD2SH Vdq{K}{z},aKq,Hdq,Wsd{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5a_pp_03_w = @@ -3251,7 +3466,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5a_pp_03_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_5a_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2798] // VCVTSH2SD Vdq{K}{z},aKq,Hdq,Wsh{sae} + (const void *)&gInstructions[ 2839] // VCVTSH2SD Vdq{K}{z},aKq,Hdq,Wsh{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5a_pp_02_w = @@ -3266,7 +3481,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5a_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_5a_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2755] // VCVTPD2PH Vdq{K}{z},aKq,Wfv|B64{er} + (const void *)&gInstructions[ 2796] // VCVTPD2PH Vdq{K}{z},aKq,Wfv|B64{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5a_pp_01_w = @@ -3281,7 +3496,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5a_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_5a_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2765] // VCVTPH2PD Vfv{K}{z},aKq,Wqv|B16{sae} + (const void *)&gInstructions[ 2806] // VCVTPH2PD Vfv{K}{z},aKq,Wqv|B16{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5a_pp_00_w = @@ -3307,7 +3522,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_5a_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_59_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3355] // VMULSH Vdq{K}{z},aKq,Hdq,Wsh{er} + (const void *)&gInstructions[ 3400] // VMULSH Vdq{K}{z},aKq,Hdq,Wsh{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_59_pp_02_w = @@ -3322,7 +3537,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_59_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_59_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3347] // VMULNEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16 + (const void *)&gInstructions[ 3392] // VMULNEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16 }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_59_pp_01_w = @@ -3337,7 +3552,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_59_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_59_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3350] // VMULPH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} + (const void *)&gInstructions[ 3395] // VMULPH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_59_pp_00_w = @@ -3363,7 +3578,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_59_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_58_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2653] // VADDSH Vdq{K}{z},aKq,Hdq,Wsh{er} + (const void *)&gInstructions[ 2694] // VADDSH Vdq{K}{z},aKq,Hdq,Wsh{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_58_pp_02_w = @@ -3378,7 +3593,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_58_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_58_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2645] // VADDNEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16 + (const void *)&gInstructions[ 2686] // VADDNEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16 }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_58_pp_01_w = @@ -3393,7 +3608,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_58_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_58_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2648] // VADDPH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} + (const void *)&gInstructions[ 2689] // VADDPH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_58_pp_00_w = @@ -3419,7 +3634,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_58_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_51_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4012] // VSQRTSH Vdq{K}{z},aKq,Hdq,Wsh{er} + (const void *)&gInstructions[ 4059] // VSQRTSH Vdq{K}{z},aKq,Hdq,Wsh{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_51_pp_02_w = @@ -3434,7 +3649,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_51_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_51_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4004] // VSQRTNEPBF16 Vfv{K}{z},aKq,Wfv|B16 + (const void *)&gInstructions[ 4051] // VSQRTNEPBF16 Vfv{K}{z},aKq,Wfv|B16 }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_51_pp_01_w = @@ -3449,7 +3664,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_51_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_51_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4007] // VSQRTPH Vfv{K}{z},aKq,Wfv|B16{er} + (const void *)&gInstructions[ 4054] // VSQRTPH Vfv{K}{z},aKq,Wfv|B16{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_51_pp_00_w = @@ -3472,62 +3687,25 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_51_pp = } }; -const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_42_pp_01_w_00_leaf = +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_2f_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3145] // VGETEXPPBF16 Vfv{K}{z},aKq,Wfv|B16 + (const void *)&gInstructions[ 2763] // VCOMXSH Vdq,Wsh{sae} }; -const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_42_pp_01_w = +const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_2f_pp_02_w = { ND_ILUT_EX_W, { - /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_42_pp_01_w_00_leaf, + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_2f_pp_02_w_00_leaf, /* 01 */ (const void *)ND_NULL, } }; -const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_42_pp = -{ - ND_ILUT_EX_PP, - { - /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gEvexMap_mmmmm_05_opcode_42_pp_01_w, - /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_2f_pp_03_l_00_w_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2722] // VCOMXSH Vdq,Wsh{sae} -}; - -const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_2f_pp_03_l_00_w = -{ - ND_ILUT_EX_W, - { - /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_2f_pp_03_l_00_w_00_leaf, - /* 01 */ (const void *)ND_NULL, - } -}; - -const ND_TABLE_EX_L gEvexMap_mmmmm_05_opcode_2f_pp_03_l = -{ - ND_ILUT_EX_L, - { - /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_2f_pp_03_l_00_w, - /* 01 */ (const void *)ND_NULL, - /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)ND_NULL, - } -}; - const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_2f_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2720] // VCOMSBF16 Vdq,Wsh + (const void *)&gInstructions[ 2761] // VCOMSBF16 Vdq,Wsh }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_2f_pp_01_w = @@ -3542,7 +3720,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_2f_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_2f_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2715] // VCOMISH Vdq,Wsh{sae} + (const void *)&gInstructions[ 2756] // VCOMISH Vdq,Wsh{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_2f_pp_00_w = @@ -3560,41 +3738,30 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_2f_pp = { /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_2f_pp_00_w, /* 01 */ (const void *)&gEvexMap_mmmmm_05_opcode_2f_pp_01_w, - /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)&gEvexMap_mmmmm_05_opcode_2f_pp_03_l, + /* 02 */ (const void *)&gEvexMap_mmmmm_05_opcode_2f_pp_02_w, + /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_2e_pp_03_l_00_w_00_leaf = +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_2e_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4035] // VUCOMXSH Vdq,Wsh{sae} + (const void *)&gInstructions[ 4082] // VUCOMXSH Vdq,Wsh{sae} }; -const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_2e_pp_03_l_00_w = +const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_2e_pp_02_w = { ND_ILUT_EX_W, { - /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_2e_pp_03_l_00_w_00_leaf, - /* 01 */ (const void *)ND_NULL, - } -}; - -const ND_TABLE_EX_L gEvexMap_mmmmm_05_opcode_2e_pp_03_l = -{ - ND_ILUT_EX_L, - { - /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_2e_pp_03_l_00_w, + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_2e_pp_02_w_00_leaf, /* 01 */ (const void *)ND_NULL, - /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)ND_NULL, } }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_2e_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4031] // VUCOMISH Vdq,Wsh{sae} + (const void *)&gInstructions[ 4078] // VUCOMISH Vdq,Wsh{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_2e_pp_00_w = @@ -3612,15 +3779,15 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_2e_pp = { /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_2e_pp_00_w, /* 01 */ (const void *)ND_NULL, - /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)&gEvexMap_mmmmm_05_opcode_2e_pp_03_l, + /* 02 */ (const void *)&gEvexMap_mmmmm_05_opcode_2e_pp_02_w, + /* 03 */ (const void *)ND_NULL, } }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_2d_pp_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2799] // VCVTSH2SI Gy,Wsh{er} + (const void *)&gInstructions[ 2840] // VCVTSH2SI Gy,Wsh{er} }; const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_2d_pp = @@ -3637,7 +3804,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_2d_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_2c_pp_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2849] // VCVTTSH2SI Gy,Wsh{sae} + (const void *)&gInstructions[ 2890] // VCVTTSH2SI Gy,Wsh{sae} }; const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_2c_pp = @@ -3654,7 +3821,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_2c_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_2a_pp_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2805] // VCVTSI2SH Vdq,Hdq,Ey + (const void *)&gInstructions[ 2846] // VCVTSI2SH Vdq,Hdq,Ey }; const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_2a_pp = @@ -3671,7 +3838,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_2a_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_1e_pp_03_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2735] // VCVTHF82PH Vfv{K}{z},aKq,Whv + (const void *)&gInstructions[ 2776] // VCVTHF82PH Vfv{K}{z},aKq,Whv }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_1e_pp_03_w = @@ -3697,7 +3864,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_1e_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_1d_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2785] // VCVTPS2PHX Vhv{K}{z},aKq,Wfv|B32{er} + (const void *)&gInstructions[ 2826] // VCVTPS2PHX Vhv{K}{z},aKq,Wfv|B32{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_1d_pp_01_w = @@ -3712,7 +3879,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_1d_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_1d_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2810] // VCVTSS2SH Vdq{K}{z},aKq,Hdq,Wss{er} + (const void *)&gInstructions[ 2851] // VCVTSS2SH Vdq{K}{z},aKq,Hdq,Wss{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_1d_pp_00_w = @@ -3738,7 +3905,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_1d_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_1b_pp_03_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2739] // VCVTNE2PH2HF8S Vfv{K}{z},aKq,Hfv,Wfv|B16 + (const void *)&gInstructions[ 2780] // VCVTNE2PH2HF8S Vfv{K}{z},aKq,Hfv,Wfv|B16 }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_1b_pp_03_w = @@ -3753,7 +3920,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_1b_pp_03_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_1b_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2750] // VCVTNEPH2HF8S Vhv{K}{z},aKq,Wfv|B16 + (const void *)&gInstructions[ 2791] // VCVTNEPH2HF8S Vhv{K}{z},aKq,Wfv|B16 }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_1b_pp_02_w = @@ -3768,7 +3935,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_1b_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_1b_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2728] // VCVTBIASPH2HF8S Vhv{K}{z},aKq,Hfv,Wfv|B16 + (const void *)&gInstructions[ 2769] // VCVTBIASPH2HF8S Vhv{K}{z},aKq,Hfv,Wfv|B16 }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_1b_pp_00_w = @@ -3794,7 +3961,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_1b_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_18_pp_03_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2738] // VCVTNE2PH2HF8 Vfv{K}{z},aKq,Hfv,Wfv|B16 + (const void *)&gInstructions[ 2779] // VCVTNE2PH2HF8 Vfv{K}{z},aKq,Hfv,Wfv|B16 }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_18_pp_03_w = @@ -3809,7 +3976,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_18_pp_03_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_18_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2749] // VCVTNEPH2HF8 Vhv{K}{z},aKq,Wfv|B16 + (const void *)&gInstructions[ 2790] // VCVTNEPH2HF8 Vhv{K}{z},aKq,Wfv|B16 }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_18_pp_02_w = @@ -3824,7 +3991,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_18_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_18_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2727] // VCVTBIASPH2HF8 Vhv{K}{z},aKq,Hfv,Wfv|B16 + (const void *)&gInstructions[ 2768] // VCVTBIASPH2HF8 Vhv{K}{z},aKq,Hfv,Wfv|B16 }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_18_pp_00_w = @@ -3850,7 +4017,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_18_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_11_pp_02_modrmmod_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3312] // VMOVSH Wsh{K}{z},aKq,Hdq,Vdq + (const void *)&gInstructions[ 3357] // VMOVSH Wsh{K}{z},aKq,Hdq,Vdq }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_11_pp_02_modrmmod_01_w = @@ -3865,7 +4032,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_11_pp_02_modrmmod_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_11_pp_02_modrmmod_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3311] // VMOVSH Wsh{K},aKq,Vdq + (const void *)&gInstructions[ 3356] // VMOVSH Wsh{K},aKq,Vdq }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_11_pp_02_modrmmod_00_w = @@ -3900,7 +4067,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_11_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_10_pp_02_modrmmod_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3310] // VMOVSH Vdq{K}{z},aKq,Hdq,Wsh + (const void *)&gInstructions[ 3355] // VMOVSH Vdq{K}{z},aKq,Hdq,Wsh }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_10_pp_02_modrmmod_01_w = @@ -3915,7 +4082,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_10_pp_02_modrmmod_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_10_pp_02_modrmmod_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3309] // VMOVSH Vdq{K}{z},aKq,Wsh + (const void *)&gInstructions[ 3354] // VMOVSH Vdq{K}{z},aKq,Wsh }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_10_pp_02_modrmmod_00_w = @@ -4017,7 +4184,7 @@ const ND_TABLE_OPCODE gEvexMap_mmmmm_05_opcode = /* 3f */ (const void *)ND_NULL, /* 40 */ (const void *)ND_NULL, /* 41 */ (const void *)ND_NULL, - /* 42 */ (const void *)&gEvexMap_mmmmm_05_opcode_42_pp, + /* 42 */ (const void *)ND_NULL, /* 43 */ (const void *)ND_NULL, /* 44 */ (const void *)ND_NULL, /* 45 */ (const void *)ND_NULL, @@ -4062,7 +4229,7 @@ const ND_TABLE_OPCODE gEvexMap_mmmmm_05_opcode = /* 6c */ (const void *)&gEvexMap_mmmmm_05_opcode_6c_pp, /* 6d */ (const void *)&gEvexMap_mmmmm_05_opcode_6d_pp, /* 6e */ (const void *)&gEvexMap_mmmmm_05_opcode_6e_pp, - /* 6f */ (const void *)ND_NULL, + /* 6f */ (const void *)&gEvexMap_mmmmm_05_opcode_6f_pp, /* 70 */ (const void *)ND_NULL, /* 71 */ (const void *)ND_NULL, /* 72 */ (const void *)ND_NULL, @@ -4352,7 +4519,7 @@ const ND_TABLE_MODRM_REG gEvexMap_mmmmm_04_opcode_ff_pp_01_modrmreg = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_06_modrmmod_01_l_00_w_01_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1969] // PUSH2P Bv,Rv + (const void *)&gInstructions[ 1973] // PUSH2P Bv,Rv }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_06_modrmmod_01_l_00_w_01_nd_01_nf = @@ -4376,7 +4543,7 @@ const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_06_modrmmod_01_l const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_06_modrmmod_01_l_00_w_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1968] // PUSH2 Bv,Rv + (const void *)&gInstructions[ 1972] // PUSH2 Bv,Rv }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_06_modrmmod_01_l_00_w_00_nd_01_nf = @@ -4971,7 +5138,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_f9_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f8_pp_03_modrmmod_01_l_00_w_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2633] // URDMSR Eq,Gq + (const void *)&gInstructions[ 2674] // URDMSR Eq,Gq }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f8_pp_03_modrmmod_01_l_00_w_00_nd_00_nf = @@ -5059,7 +5226,7 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_f8_pp_03_modrmmod = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f8_pp_02_modrmmod_01_l_00_w_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2637] // UWRMSR Gq,Eq + (const void *)&gInstructions[ 2678] // UWRMSR Gq,Eq }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f8_pp_02_modrmmod_01_l_00_w_00_nd_00_nf = @@ -5325,13 +5492,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_05_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_04_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1476] // MUL Ev + (const void *)&gInstructions[ 1478] // MUL Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_04_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1473] // MUL Ev + (const void *)&gInstructions[ 1475] // MUL Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_04_l_00_nd_00_nf = @@ -5366,13 +5533,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_04_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_03_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1498] // NEG Bv,Ev + (const void *)&gInstructions[ 1500] // NEG Bv,Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_03_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1495] // NEG Bv,Ev + (const void *)&gInstructions[ 1497] // NEG Bv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_03_l_00_nd_01_nf = @@ -5387,13 +5554,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_03_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_03_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1492] // NEG Ev + (const void *)&gInstructions[ 1494] // NEG Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_03_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1489] // NEG Ev + (const void *)&gInstructions[ 1491] // NEG Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_03_l_00_nd_00_nf = @@ -5428,7 +5595,7 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_03_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_02_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1577] // NOT Bv,Ev + (const void *)&gInstructions[ 1579] // NOT Bv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_02_l_00_nd_01_nf = @@ -5443,7 +5610,7 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_02_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_02_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1574] // NOT Ev + (const void *)&gInstructions[ 1576] // NOT Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_02_l_00_nd_00_nf = @@ -5894,13 +6061,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_05_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_04_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1475] // MUL Ev + (const void *)&gInstructions[ 1477] // MUL Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_04_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1472] // MUL Ev + (const void *)&gInstructions[ 1474] // MUL Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_04_l_00_nd_00_nf = @@ -5935,13 +6102,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_04_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_03_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1497] // NEG Bv,Ev + (const void *)&gInstructions[ 1499] // NEG Bv,Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_03_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1494] // NEG Bv,Ev + (const void *)&gInstructions[ 1496] // NEG Bv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_03_l_00_nd_01_nf = @@ -5956,13 +6123,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_03_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_03_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1491] // NEG Ev + (const void *)&gInstructions[ 1493] // NEG Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_03_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1488] // NEG Ev + (const void *)&gInstructions[ 1490] // NEG Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_03_l_00_nd_00_nf = @@ -5997,7 +6164,7 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_03_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_02_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1576] // NOT Bv,Ev + (const void *)&gInstructions[ 1578] // NOT Bv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_02_l_00_nd_01_nf = @@ -6012,7 +6179,7 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_02_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_02_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1573] // NOT Ev + (const void *)&gInstructions[ 1575] // NOT Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_02_l_00_nd_00_nf = @@ -6474,13 +6641,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_05_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_04_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1474] // MUL Eb + (const void *)&gInstructions[ 1476] // MUL Eb }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_04_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1471] // MUL Eb + (const void *)&gInstructions[ 1473] // MUL Eb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_04_l_00_nd_00_nf = @@ -6515,13 +6682,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_04_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_03_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1496] // NEG Bb,Eb + (const void *)&gInstructions[ 1498] // NEG Bb,Eb }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_03_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1493] // NEG Bb,Eb + (const void *)&gInstructions[ 1495] // NEG Bb,Eb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_03_l_00_nd_01_nf = @@ -6536,13 +6703,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_03_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_03_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1490] // NEG Eb + (const void *)&gInstructions[ 1492] // NEG Eb }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_03_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1487] // NEG Eb + (const void *)&gInstructions[ 1489] // NEG Eb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_03_l_00_nd_00_nf = @@ -6577,7 +6744,7 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_03_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_02_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1575] // NOT Bb,Eb + (const void *)&gInstructions[ 1577] // NOT Bb,Eb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_02_l_00_nd_01_nf = @@ -6592,7 +6759,7 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_02_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_02_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1572] // NOT Eb + (const void *)&gInstructions[ 1574] // NOT Eb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_02_l_00_nd_00_nf = @@ -7024,13 +7191,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_f5_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f4_pp_01_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2618] // TZCNT Gv,Ev + (const void *)&gInstructions[ 2659] // TZCNT Gv,Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f4_pp_01_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2616] // TZCNT Gv,Ev + (const void *)&gInstructions[ 2657] // TZCNT Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f4_pp_01_l_00_nd_00_nf = @@ -7065,13 +7232,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f4_pp_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f4_pp_00_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2617] // TZCNT Gv,Ev + (const void *)&gInstructions[ 2658] // TZCNT Gv,Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f4_pp_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2615] // TZCNT Gv,Ev + (const void *)&gInstructions[ 2656] // TZCNT Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f4_pp_00_l_00_nd_00_nf = @@ -7387,13 +7554,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_f0_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_07_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2269] // SAR Bv,Ev,CL + (const void *)&gInstructions[ 2275] // SAR Bv,Ev,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_07_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2260] // SAR Bv,Ev,CL + (const void *)&gInstructions[ 2266] // SAR Bv,Ev,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_07_l_00_nd_01_nf = @@ -7408,13 +7575,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_07_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_07_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2251] // SAR Ev,CL + (const void *)&gInstructions[ 2257] // SAR Ev,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_07_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2242] // SAR Ev,CL + (const void *)&gInstructions[ 2248] // SAR Ev,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_07_l_00_nd_00_nf = @@ -7449,13 +7616,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_07_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_06_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2226] // SAL Bv,Ev,CL + (const void *)&gInstructions[ 2232] // SAL Bv,Ev,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_06_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2217] // SAL Bv,Ev,CL + (const void *)&gInstructions[ 2223] // SAL Bv,Ev,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_06_l_00_nd_01_nf = @@ -7470,13 +7637,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_06_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_06_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2208] // SAL Ev,CL + (const void *)&gInstructions[ 2214] // SAL Ev,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_06_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2199] // SAL Ev,CL + (const void *)&gInstructions[ 2205] // SAL Ev,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_06_l_00_nd_00_nf = @@ -7511,13 +7678,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_06_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_05_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2463] // SHR Bv,Ev,CL + (const void *)&gInstructions[ 2469] // SHR Bv,Ev,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_05_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2454] // SHR Bv,Ev,CL + (const void *)&gInstructions[ 2460] // SHR Bv,Ev,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_05_l_00_nd_01_nf = @@ -7532,13 +7699,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_05_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_05_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2445] // SHR Ev,CL + (const void *)&gInstructions[ 2451] // SHR Ev,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_05_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2436] // SHR Ev,CL + (const void *)&gInstructions[ 2442] // SHR Ev,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_05_l_00_nd_00_nf = @@ -7573,13 +7740,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_05_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_04_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2401] // SHL Bv,Ev,CL + (const void *)&gInstructions[ 2407] // SHL Bv,Ev,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_04_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2392] // SHL Bv,Ev,CL + (const void *)&gInstructions[ 2398] // SHL Bv,Ev,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_04_l_00_nd_01_nf = @@ -7594,13 +7761,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_04_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_04_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2383] // SHL Ev,CL + (const void *)&gInstructions[ 2389] // SHL Ev,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_04_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2374] // SHL Ev,CL + (const void *)&gInstructions[ 2380] // SHL Ev,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_04_l_00_nd_00_nf = @@ -7635,13 +7802,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_04_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_03_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2065] // RCR Bv,Ev,CL + (const void *)&gInstructions[ 2069] // RCR Bv,Ev,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_03_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2056] // RCR Bv,Ev,CL + (const void *)&gInstructions[ 2060] // RCR Bv,Ev,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_03_l_00_nd_01_nf = @@ -7656,13 +7823,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_03_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_03_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2047] // RCR Ev,CL + (const void *)&gInstructions[ 2051] // RCR Ev,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_03_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2038] // RCR Ev,CL + (const void *)&gInstructions[ 2042] // RCR Ev,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_03_l_00_nd_00_nf = @@ -7697,13 +7864,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_03_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_02_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2021] // RCL Bv,Ev,CL + (const void *)&gInstructions[ 2025] // RCL Bv,Ev,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_02_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2012] // RCL Bv,Ev,CL + (const void *)&gInstructions[ 2016] // RCL Bv,Ev,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_02_l_00_nd_01_nf = @@ -7718,13 +7885,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_02_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_02_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2003] // RCL Ev,CL + (const void *)&gInstructions[ 2007] // RCL Ev,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_02_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1994] // RCL Ev,CL + (const void *)&gInstructions[ 1998] // RCL Ev,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_02_l_00_nd_00_nf = @@ -7759,13 +7926,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_02_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_01_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2173] // ROR Bv,Ev,CL + (const void *)&gInstructions[ 2179] // ROR Bv,Ev,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_01_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2164] // ROR Bv,Ev,CL + (const void *)&gInstructions[ 2170] // ROR Bv,Ev,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_01_l_00_nd_01_nf = @@ -7780,13 +7947,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_01_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_01_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2155] // ROR Ev,CL + (const void *)&gInstructions[ 2161] // ROR Ev,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_01_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2146] // ROR Ev,CL + (const void *)&gInstructions[ 2152] // ROR Ev,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_01_l_00_nd_00_nf = @@ -7821,13 +7988,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_00_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2131] // ROL Bv,Ev,CL + (const void *)&gInstructions[ 2137] // ROL Bv,Ev,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_00_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2122] // ROL Bv,Ev,CL + (const void *)&gInstructions[ 2128] // ROL Bv,Ev,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_00_l_00_nd_01_nf = @@ -7842,13 +8009,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_00_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_00_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2113] // ROL Ev,CL + (const void *)&gInstructions[ 2119] // ROL Ev,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2104] // ROL Ev,CL + (const void *)&gInstructions[ 2110] // ROL Ev,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_00_l_00_nd_00_nf = @@ -7898,13 +8065,13 @@ const ND_TABLE_MODRM_REG gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_07_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2268] // SAR Bv,Ev,CL + (const void *)&gInstructions[ 2274] // SAR Bv,Ev,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_07_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2259] // SAR Bv,Ev,CL + (const void *)&gInstructions[ 2265] // SAR Bv,Ev,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_07_l_00_nd_01_nf = @@ -7919,13 +8086,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_07_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_07_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2250] // SAR Ev,CL + (const void *)&gInstructions[ 2256] // SAR Ev,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_07_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2241] // SAR Ev,CL + (const void *)&gInstructions[ 2247] // SAR Ev,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_07_l_00_nd_00_nf = @@ -7960,13 +8127,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_07_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_06_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2225] // SAL Bv,Ev,CL + (const void *)&gInstructions[ 2231] // SAL Bv,Ev,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_06_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2216] // SAL Bv,Ev,CL + (const void *)&gInstructions[ 2222] // SAL Bv,Ev,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_06_l_00_nd_01_nf = @@ -7981,13 +8148,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_06_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_06_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2207] // SAL Ev,CL + (const void *)&gInstructions[ 2213] // SAL Ev,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_06_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2198] // SAL Ev,CL + (const void *)&gInstructions[ 2204] // SAL Ev,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_06_l_00_nd_00_nf = @@ -8022,13 +8189,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_06_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_05_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2462] // SHR Bv,Ev,CL + (const void *)&gInstructions[ 2468] // SHR Bv,Ev,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_05_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2453] // SHR Bv,Ev,CL + (const void *)&gInstructions[ 2459] // SHR Bv,Ev,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_05_l_00_nd_01_nf = @@ -8043,13 +8210,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_05_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_05_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2444] // SHR Ev,CL + (const void *)&gInstructions[ 2450] // SHR Ev,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_05_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2435] // SHR Ev,CL + (const void *)&gInstructions[ 2441] // SHR Ev,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_05_l_00_nd_00_nf = @@ -8084,13 +8251,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_05_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_04_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2400] // SHL Bv,Ev,CL + (const void *)&gInstructions[ 2406] // SHL Bv,Ev,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_04_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2391] // SHL Bv,Ev,CL + (const void *)&gInstructions[ 2397] // SHL Bv,Ev,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_04_l_00_nd_01_nf = @@ -8105,13 +8272,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_04_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_04_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2382] // SHL Ev,CL + (const void *)&gInstructions[ 2388] // SHL Ev,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_04_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2373] // SHL Ev,CL + (const void *)&gInstructions[ 2379] // SHL Ev,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_04_l_00_nd_00_nf = @@ -8146,13 +8313,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_04_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_03_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2064] // RCR Bv,Ev,CL + (const void *)&gInstructions[ 2068] // RCR Bv,Ev,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_03_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2055] // RCR Bv,Ev,CL + (const void *)&gInstructions[ 2059] // RCR Bv,Ev,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_03_l_00_nd_01_nf = @@ -8167,13 +8334,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_03_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_03_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2046] // RCR Ev,CL + (const void *)&gInstructions[ 2050] // RCR Ev,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_03_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2037] // RCR Ev,CL + (const void *)&gInstructions[ 2041] // RCR Ev,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_03_l_00_nd_00_nf = @@ -8208,13 +8375,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_03_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_02_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2020] // RCL Bv,Ev,CL + (const void *)&gInstructions[ 2024] // RCL Bv,Ev,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_02_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2011] // RCL Bv,Ev,CL + (const void *)&gInstructions[ 2015] // RCL Bv,Ev,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_02_l_00_nd_01_nf = @@ -8229,13 +8396,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_02_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_02_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2002] // RCL Ev,CL + (const void *)&gInstructions[ 2006] // RCL Ev,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_02_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1993] // RCL Ev,CL + (const void *)&gInstructions[ 1997] // RCL Ev,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_02_l_00_nd_00_nf = @@ -8270,13 +8437,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_02_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_01_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2172] // ROR Bv,Ev,CL + (const void *)&gInstructions[ 2178] // ROR Bv,Ev,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_01_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2163] // ROR Bv,Ev,CL + (const void *)&gInstructions[ 2169] // ROR Bv,Ev,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_01_l_00_nd_01_nf = @@ -8291,13 +8458,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_01_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_01_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2154] // ROR Ev,CL + (const void *)&gInstructions[ 2160] // ROR Ev,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_01_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2145] // ROR Ev,CL + (const void *)&gInstructions[ 2151] // ROR Ev,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_01_l_00_nd_00_nf = @@ -8332,13 +8499,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_00_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2130] // ROL Bv,Ev,CL + (const void *)&gInstructions[ 2136] // ROL Bv,Ev,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_00_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2121] // ROL Bv,Ev,CL + (const void *)&gInstructions[ 2127] // ROL Bv,Ev,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_00_l_00_nd_01_nf = @@ -8353,13 +8520,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_00_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_00_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2112] // ROL Ev,CL + (const void *)&gInstructions[ 2118] // ROL Ev,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2103] // ROL Ev,CL + (const void *)&gInstructions[ 2109] // ROL Ev,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_00_l_00_nd_00_nf = @@ -8420,13 +8587,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_d3_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_07_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2267] // SAR Bb,Eb,CL + (const void *)&gInstructions[ 2273] // SAR Bb,Eb,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_07_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2258] // SAR Bb,Eb,CL + (const void *)&gInstructions[ 2264] // SAR Bb,Eb,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_07_l_00_nd_01_nf = @@ -8441,13 +8608,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_07_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_07_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2249] // SAR Eb,CL + (const void *)&gInstructions[ 2255] // SAR Eb,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_07_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2240] // SAR Eb,CL + (const void *)&gInstructions[ 2246] // SAR Eb,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_07_l_00_nd_00_nf = @@ -8482,13 +8649,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_07_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_06_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2224] // SAL Bb,Eb,CL + (const void *)&gInstructions[ 2230] // SAL Bb,Eb,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_06_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2215] // SAL Bb,Eb,CL + (const void *)&gInstructions[ 2221] // SAL Bb,Eb,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_06_l_00_nd_01_nf = @@ -8503,13 +8670,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_06_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_06_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2206] // SAL Eb,CL + (const void *)&gInstructions[ 2212] // SAL Eb,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_06_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2197] // SAL Eb,CL + (const void *)&gInstructions[ 2203] // SAL Eb,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_06_l_00_nd_00_nf = @@ -8544,13 +8711,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_06_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_05_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2461] // SHR Bb,Eb,CL + (const void *)&gInstructions[ 2467] // SHR Bb,Eb,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_05_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2452] // SHR Bb,Eb,CL + (const void *)&gInstructions[ 2458] // SHR Bb,Eb,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_05_l_00_nd_01_nf = @@ -8565,13 +8732,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_05_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_05_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2443] // SHR Eb,CL + (const void *)&gInstructions[ 2449] // SHR Eb,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_05_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2434] // SHR Eb,CL + (const void *)&gInstructions[ 2440] // SHR Eb,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_05_l_00_nd_00_nf = @@ -8606,13 +8773,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_05_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_04_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2399] // SHL Bb,Eb,CL + (const void *)&gInstructions[ 2405] // SHL Bb,Eb,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_04_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2390] // SHL Bb,Eb,CL + (const void *)&gInstructions[ 2396] // SHL Bb,Eb,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_04_l_00_nd_01_nf = @@ -8627,13 +8794,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_04_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_04_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2381] // SHL Eb,CL + (const void *)&gInstructions[ 2387] // SHL Eb,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_04_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2372] // SHL Eb,CL + (const void *)&gInstructions[ 2378] // SHL Eb,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_04_l_00_nd_00_nf = @@ -8668,13 +8835,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_04_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_03_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2063] // RCR Bb,Eb,CL + (const void *)&gInstructions[ 2067] // RCR Bb,Eb,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_03_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2054] // RCR Bb,Eb,CL + (const void *)&gInstructions[ 2058] // RCR Bb,Eb,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_03_l_00_nd_01_nf = @@ -8689,13 +8856,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_03_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_03_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2045] // RCR Eb,CL + (const void *)&gInstructions[ 2049] // RCR Eb,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_03_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2036] // RCR Eb,CL + (const void *)&gInstructions[ 2040] // RCR Eb,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_03_l_00_nd_00_nf = @@ -8730,13 +8897,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_03_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_02_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2019] // RCL Bb,Eb,CL + (const void *)&gInstructions[ 2023] // RCL Bb,Eb,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_02_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2010] // RCL Bb,Eb,CL + (const void *)&gInstructions[ 2014] // RCL Bb,Eb,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_02_l_00_nd_01_nf = @@ -8751,13 +8918,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_02_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_02_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2001] // RCL Eb,CL + (const void *)&gInstructions[ 2005] // RCL Eb,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_02_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1992] // RCL Eb,CL + (const void *)&gInstructions[ 1996] // RCL Eb,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_02_l_00_nd_00_nf = @@ -8792,13 +8959,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_02_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_01_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2171] // ROR Bb,Eb,CL + (const void *)&gInstructions[ 2177] // ROR Bb,Eb,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_01_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2162] // ROR Bb,Eb,CL + (const void *)&gInstructions[ 2168] // ROR Bb,Eb,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_01_l_00_nd_01_nf = @@ -8813,13 +8980,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_01_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_01_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2153] // ROR Eb,CL + (const void *)&gInstructions[ 2159] // ROR Eb,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_01_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2144] // ROR Eb,CL + (const void *)&gInstructions[ 2150] // ROR Eb,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_01_l_00_nd_00_nf = @@ -8854,13 +9021,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_00_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2129] // ROL Bb,Eb,CL + (const void *)&gInstructions[ 2135] // ROL Bb,Eb,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_00_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2120] // ROL Bb,Eb,CL + (const void *)&gInstructions[ 2126] // ROL Bb,Eb,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_00_l_00_nd_01_nf = @@ -8875,13 +9042,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_00_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_00_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2111] // ROL Eb,CL + (const void *)&gInstructions[ 2117] // ROL Eb,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2102] // ROL Eb,CL + (const void *)&gInstructions[ 2108] // ROL Eb,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_00_l_00_nd_00_nf = @@ -8942,13 +9109,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_d2_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_07_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2266] // SAR Bv,Ev,1 + (const void *)&gInstructions[ 2272] // SAR Bv,Ev,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_07_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2257] // SAR Bv,Ev,1 + (const void *)&gInstructions[ 2263] // SAR Bv,Ev,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_07_l_00_nd_01_nf = @@ -8963,13 +9130,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_07_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_07_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2248] // SAR Ev,1 + (const void *)&gInstructions[ 2254] // SAR Ev,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_07_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2239] // SAR Ev,1 + (const void *)&gInstructions[ 2245] // SAR Ev,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_07_l_00_nd_00_nf = @@ -9004,13 +9171,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_07_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_06_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2223] // SAL Bv,Ev,1 + (const void *)&gInstructions[ 2229] // SAL Bv,Ev,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_06_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2214] // SAL Bv,Ev,1 + (const void *)&gInstructions[ 2220] // SAL Bv,Ev,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_06_l_00_nd_01_nf = @@ -9025,13 +9192,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_06_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_06_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2205] // SAL Ev,1 + (const void *)&gInstructions[ 2211] // SAL Ev,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_06_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2196] // SAL Ev,1 + (const void *)&gInstructions[ 2202] // SAL Ev,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_06_l_00_nd_00_nf = @@ -9066,13 +9233,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_06_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_05_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2460] // SHR Bv,Ev,1 + (const void *)&gInstructions[ 2466] // SHR Bv,Ev,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_05_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2451] // SHR Bv,Ev,1 + (const void *)&gInstructions[ 2457] // SHR Bv,Ev,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_05_l_00_nd_01_nf = @@ -9087,13 +9254,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_05_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_05_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2442] // SHR Ev,1 + (const void *)&gInstructions[ 2448] // SHR Ev,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_05_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2433] // SHR Ev,1 + (const void *)&gInstructions[ 2439] // SHR Ev,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_05_l_00_nd_00_nf = @@ -9128,13 +9295,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_05_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_04_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2398] // SHL Bv,Ev,1 + (const void *)&gInstructions[ 2404] // SHL Bv,Ev,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_04_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2389] // SHL Bv,Ev,1 + (const void *)&gInstructions[ 2395] // SHL Bv,Ev,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_04_l_00_nd_01_nf = @@ -9149,13 +9316,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_04_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_04_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2380] // SHL Ev,1 + (const void *)&gInstructions[ 2386] // SHL Ev,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_04_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2371] // SHL Ev,1 + (const void *)&gInstructions[ 2377] // SHL Ev,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_04_l_00_nd_00_nf = @@ -9190,13 +9357,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_04_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_03_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2062] // RCR Bv,Ev,1 + (const void *)&gInstructions[ 2066] // RCR Bv,Ev,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_03_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2053] // RCR Bv,Ev,1 + (const void *)&gInstructions[ 2057] // RCR Bv,Ev,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_03_l_00_nd_01_nf = @@ -9211,13 +9378,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_03_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_03_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2044] // RCR Ev,1 + (const void *)&gInstructions[ 2048] // RCR Ev,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_03_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2035] // RCR Ev,1 + (const void *)&gInstructions[ 2039] // RCR Ev,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_03_l_00_nd_00_nf = @@ -9252,13 +9419,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_03_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_02_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2018] // RCL Bv,Ev,1 + (const void *)&gInstructions[ 2022] // RCL Bv,Ev,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_02_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2009] // RCL Bv,Ev,1 + (const void *)&gInstructions[ 2013] // RCL Bv,Ev,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_02_l_00_nd_01_nf = @@ -9273,13 +9440,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_02_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_02_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2000] // RCL Ev,1 + (const void *)&gInstructions[ 2004] // RCL Ev,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_02_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1991] // RCL Ev,1 + (const void *)&gInstructions[ 1995] // RCL Ev,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_02_l_00_nd_00_nf = @@ -9314,13 +9481,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_02_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_01_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2170] // ROR Bv,Ev,1 + (const void *)&gInstructions[ 2176] // ROR Bv,Ev,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_01_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2161] // ROR Bv,Ev,1 + (const void *)&gInstructions[ 2167] // ROR Bv,Ev,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_01_l_00_nd_01_nf = @@ -9335,13 +9502,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_01_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_01_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2152] // ROR Ev,1 + (const void *)&gInstructions[ 2158] // ROR Ev,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_01_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2143] // ROR Ev,1 + (const void *)&gInstructions[ 2149] // ROR Ev,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_01_l_00_nd_00_nf = @@ -9376,13 +9543,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_00_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2128] // ROL Bv,Ev,1 + (const void *)&gInstructions[ 2134] // ROL Bv,Ev,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_00_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2119] // ROL Bv,Ev,1 + (const void *)&gInstructions[ 2125] // ROL Bv,Ev,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_00_l_00_nd_01_nf = @@ -9397,13 +9564,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_00_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_00_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2110] // ROL Ev,1 + (const void *)&gInstructions[ 2116] // ROL Ev,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2101] // ROL Ev,1 + (const void *)&gInstructions[ 2107] // ROL Ev,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_00_l_00_nd_00_nf = @@ -9453,13 +9620,13 @@ const ND_TABLE_MODRM_REG gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_07_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2265] // SAR Bv,Ev,1 + (const void *)&gInstructions[ 2271] // SAR Bv,Ev,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_07_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2256] // SAR Bv,Ev,1 + (const void *)&gInstructions[ 2262] // SAR Bv,Ev,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_07_l_00_nd_01_nf = @@ -9474,13 +9641,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_07_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_07_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2247] // SAR Ev,1 + (const void *)&gInstructions[ 2253] // SAR Ev,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_07_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2238] // SAR Ev,1 + (const void *)&gInstructions[ 2244] // SAR Ev,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_07_l_00_nd_00_nf = @@ -9515,13 +9682,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_07_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_06_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2222] // SAL Bv,Ev,1 + (const void *)&gInstructions[ 2228] // SAL Bv,Ev,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_06_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2213] // SAL Bv,Ev,1 + (const void *)&gInstructions[ 2219] // SAL Bv,Ev,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_06_l_00_nd_01_nf = @@ -9536,13 +9703,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_06_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_06_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2204] // SAL Ev,1 + (const void *)&gInstructions[ 2210] // SAL Ev,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_06_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2195] // SAL Ev,1 + (const void *)&gInstructions[ 2201] // SAL Ev,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_06_l_00_nd_00_nf = @@ -9577,13 +9744,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_06_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_05_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2459] // SHR Bv,Ev,1 + (const void *)&gInstructions[ 2465] // SHR Bv,Ev,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_05_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2450] // SHR Bv,Ev,1 + (const void *)&gInstructions[ 2456] // SHR Bv,Ev,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_05_l_00_nd_01_nf = @@ -9598,13 +9765,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_05_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_05_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2441] // SHR Ev,1 + (const void *)&gInstructions[ 2447] // SHR Ev,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_05_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2432] // SHR Ev,1 + (const void *)&gInstructions[ 2438] // SHR Ev,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_05_l_00_nd_00_nf = @@ -9639,13 +9806,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_05_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_04_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2397] // SHL Bv,Ev,1 + (const void *)&gInstructions[ 2403] // SHL Bv,Ev,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_04_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2388] // SHL Bv,Ev,1 + (const void *)&gInstructions[ 2394] // SHL Bv,Ev,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_04_l_00_nd_01_nf = @@ -9660,13 +9827,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_04_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_04_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2379] // SHL Ev,1 + (const void *)&gInstructions[ 2385] // SHL Ev,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_04_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2370] // SHL Ev,1 + (const void *)&gInstructions[ 2376] // SHL Ev,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_04_l_00_nd_00_nf = @@ -9701,13 +9868,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_04_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_03_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2061] // RCR Bv,Ev,1 + (const void *)&gInstructions[ 2065] // RCR Bv,Ev,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_03_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2052] // RCR Bv,Ev,1 + (const void *)&gInstructions[ 2056] // RCR Bv,Ev,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_03_l_00_nd_01_nf = @@ -9722,13 +9889,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_03_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_03_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2043] // RCR Ev,1 + (const void *)&gInstructions[ 2047] // RCR Ev,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_03_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2034] // RCR Ev,1 + (const void *)&gInstructions[ 2038] // RCR Ev,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_03_l_00_nd_00_nf = @@ -9763,13 +9930,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_03_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_02_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2017] // RCL Bv,Ev,1 + (const void *)&gInstructions[ 2021] // RCL Bv,Ev,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_02_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2008] // RCL Bv,Ev,1 + (const void *)&gInstructions[ 2012] // RCL Bv,Ev,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_02_l_00_nd_01_nf = @@ -9784,13 +9951,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_02_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_02_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1999] // RCL Ev,1 + (const void *)&gInstructions[ 2003] // RCL Ev,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_02_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1990] // RCL Ev,1 + (const void *)&gInstructions[ 1994] // RCL Ev,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_02_l_00_nd_00_nf = @@ -9825,13 +9992,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_02_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_01_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2169] // ROR Bv,Ev,1 + (const void *)&gInstructions[ 2175] // ROR Bv,Ev,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_01_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2160] // ROR Bv,Ev,1 + (const void *)&gInstructions[ 2166] // ROR Bv,Ev,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_01_l_00_nd_01_nf = @@ -9846,13 +10013,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_01_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_01_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2151] // ROR Ev,1 + (const void *)&gInstructions[ 2157] // ROR Ev,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_01_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2142] // ROR Ev,1 + (const void *)&gInstructions[ 2148] // ROR Ev,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_01_l_00_nd_00_nf = @@ -9887,13 +10054,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_00_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2127] // ROL Bv,Ev,1 + (const void *)&gInstructions[ 2133] // ROL Bv,Ev,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_00_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2118] // ROL Bv,Ev,1 + (const void *)&gInstructions[ 2124] // ROL Bv,Ev,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_00_l_00_nd_01_nf = @@ -9908,13 +10075,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_00_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_00_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2109] // ROL Ev,1 + (const void *)&gInstructions[ 2115] // ROL Ev,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2100] // ROL Ev,1 + (const void *)&gInstructions[ 2106] // ROL Ev,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_00_l_00_nd_00_nf = @@ -9975,13 +10142,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_d1_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_07_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2264] // SAR Bb,Eb,1 + (const void *)&gInstructions[ 2270] // SAR Bb,Eb,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_07_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2255] // SAR Bb,Eb,1 + (const void *)&gInstructions[ 2261] // SAR Bb,Eb,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_07_l_00_nd_01_nf = @@ -9996,13 +10163,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_07_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_07_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2246] // SAR Eb,1 + (const void *)&gInstructions[ 2252] // SAR Eb,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_07_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2237] // SAR Eb,1 + (const void *)&gInstructions[ 2243] // SAR Eb,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_07_l_00_nd_00_nf = @@ -10037,13 +10204,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_07_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_06_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2221] // SAL Bb,Eb,1 + (const void *)&gInstructions[ 2227] // SAL Bb,Eb,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_06_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2212] // SAL Bb,Eb,1 + (const void *)&gInstructions[ 2218] // SAL Bb,Eb,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_06_l_00_nd_01_nf = @@ -10058,13 +10225,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_06_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_06_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2203] // SAL Eb,1 + (const void *)&gInstructions[ 2209] // SAL Eb,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_06_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2194] // SAL Eb,1 + (const void *)&gInstructions[ 2200] // SAL Eb,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_06_l_00_nd_00_nf = @@ -10099,13 +10266,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_06_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_05_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2458] // SHR Bb,Eb,1 + (const void *)&gInstructions[ 2464] // SHR Bb,Eb,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_05_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2449] // SHR Bb,Eb,1 + (const void *)&gInstructions[ 2455] // SHR Bb,Eb,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_05_l_00_nd_01_nf = @@ -10120,13 +10287,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_05_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_05_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2440] // SHR Eb,1 + (const void *)&gInstructions[ 2446] // SHR Eb,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_05_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2431] // SHR Eb,1 + (const void *)&gInstructions[ 2437] // SHR Eb,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_05_l_00_nd_00_nf = @@ -10161,13 +10328,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_05_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_04_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2396] // SHL Bb,Eb,1 + (const void *)&gInstructions[ 2402] // SHL Bb,Eb,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_04_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2387] // SHL Bb,Eb,1 + (const void *)&gInstructions[ 2393] // SHL Bb,Eb,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_04_l_00_nd_01_nf = @@ -10182,13 +10349,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_04_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_04_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2378] // SHL Eb,1 + (const void *)&gInstructions[ 2384] // SHL Eb,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_04_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2369] // SHL Eb,1 + (const void *)&gInstructions[ 2375] // SHL Eb,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_04_l_00_nd_00_nf = @@ -10223,13 +10390,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_04_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_03_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2060] // RCR Bb,Eb,1 + (const void *)&gInstructions[ 2064] // RCR Bb,Eb,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_03_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2051] // RCR Bb,Eb,1 + (const void *)&gInstructions[ 2055] // RCR Bb,Eb,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_03_l_00_nd_01_nf = @@ -10244,13 +10411,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_03_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_03_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2042] // RCR Eb,1 + (const void *)&gInstructions[ 2046] // RCR Eb,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_03_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2033] // RCR Eb,1 + (const void *)&gInstructions[ 2037] // RCR Eb,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_03_l_00_nd_00_nf = @@ -10285,13 +10452,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_03_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_02_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2016] // RCL Bb,Eb,1 + (const void *)&gInstructions[ 2020] // RCL Bb,Eb,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_02_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2007] // RCL Bb,Eb,1 + (const void *)&gInstructions[ 2011] // RCL Bb,Eb,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_02_l_00_nd_01_nf = @@ -10306,13 +10473,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_02_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_02_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1998] // RCL Eb,1 + (const void *)&gInstructions[ 2002] // RCL Eb,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_02_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1989] // RCL Eb,1 + (const void *)&gInstructions[ 1993] // RCL Eb,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_02_l_00_nd_00_nf = @@ -10347,13 +10514,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_02_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_01_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2168] // ROR Bb,Eb,1 + (const void *)&gInstructions[ 2174] // ROR Bb,Eb,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_01_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2159] // ROR Bb,Eb,1 + (const void *)&gInstructions[ 2165] // ROR Bb,Eb,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_01_l_00_nd_01_nf = @@ -10368,13 +10535,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_01_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_01_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2150] // ROR Eb,1 + (const void *)&gInstructions[ 2156] // ROR Eb,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_01_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2141] // ROR Eb,1 + (const void *)&gInstructions[ 2147] // ROR Eb,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_01_l_00_nd_00_nf = @@ -10409,13 +10576,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_00_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2126] // ROL Bb,Eb,1 + (const void *)&gInstructions[ 2132] // ROL Bb,Eb,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_00_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2117] // ROL Bb,Eb,1 + (const void *)&gInstructions[ 2123] // ROL Bb,Eb,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_00_l_00_nd_01_nf = @@ -10430,13 +10597,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_00_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_00_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2108] // ROL Eb,1 + (const void *)&gInstructions[ 2114] // ROL Eb,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2099] // ROL Eb,1 + (const void *)&gInstructions[ 2105] // ROL Eb,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_00_l_00_nd_00_nf = @@ -10497,13 +10664,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_d0_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_07_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2263] // SAR Bv,Ev,Ib + (const void *)&gInstructions[ 2269] // SAR Bv,Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_07_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2254] // SAR Bv,Ev,Ib + (const void *)&gInstructions[ 2260] // SAR Bv,Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_07_l_00_nd_01_nf = @@ -10518,13 +10685,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_07_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_07_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2245] // SAR Ev,Ib + (const void *)&gInstructions[ 2251] // SAR Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_07_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2236] // SAR Ev,Ib + (const void *)&gInstructions[ 2242] // SAR Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_07_l_00_nd_00_nf = @@ -10559,13 +10726,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_07_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_06_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2220] // SAL Bv,Ev,Ib + (const void *)&gInstructions[ 2226] // SAL Bv,Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_06_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2211] // SAL Bv,Ev,Ib + (const void *)&gInstructions[ 2217] // SAL Bv,Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_06_l_00_nd_01_nf = @@ -10580,13 +10747,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_06_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_06_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2202] // SAL Ev,Ib + (const void *)&gInstructions[ 2208] // SAL Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_06_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2193] // SAL Ev,Ib + (const void *)&gInstructions[ 2199] // SAL Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_06_l_00_nd_00_nf = @@ -10621,13 +10788,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_06_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_05_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2457] // SHR Bv,Ev,Ib + (const void *)&gInstructions[ 2463] // SHR Bv,Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_05_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2448] // SHR Bv,Ev,Ib + (const void *)&gInstructions[ 2454] // SHR Bv,Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_05_l_00_nd_01_nf = @@ -10642,13 +10809,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_05_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_05_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2439] // SHR Ev,Ib + (const void *)&gInstructions[ 2445] // SHR Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_05_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2430] // SHR Ev,Ib + (const void *)&gInstructions[ 2436] // SHR Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_05_l_00_nd_00_nf = @@ -10683,13 +10850,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_05_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_04_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2395] // SHL Bv,Ev,Ib + (const void *)&gInstructions[ 2401] // SHL Bv,Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_04_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2386] // SHL Bv,Ev,Ib + (const void *)&gInstructions[ 2392] // SHL Bv,Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_04_l_00_nd_01_nf = @@ -10704,13 +10871,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_04_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_04_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2377] // SHL Ev,Ib + (const void *)&gInstructions[ 2383] // SHL Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_04_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2368] // SHL Ev,Ib + (const void *)&gInstructions[ 2374] // SHL Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_04_l_00_nd_00_nf = @@ -10745,13 +10912,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_04_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_03_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2059] // RCR Bv,Ev,Ib + (const void *)&gInstructions[ 2063] // RCR Bv,Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_03_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2050] // RCR Bv,Ev,Ib + (const void *)&gInstructions[ 2054] // RCR Bv,Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_03_l_00_nd_01_nf = @@ -10766,13 +10933,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_03_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_03_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2041] // RCR Ev,Ib + (const void *)&gInstructions[ 2045] // RCR Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_03_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2032] // RCR Ev,Ib + (const void *)&gInstructions[ 2036] // RCR Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_03_l_00_nd_00_nf = @@ -10807,13 +10974,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_03_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_02_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2015] // RCL Bv,Ev,Ib + (const void *)&gInstructions[ 2019] // RCL Bv,Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_02_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2006] // RCL Bv,Ev,Ib + (const void *)&gInstructions[ 2010] // RCL Bv,Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_02_l_00_nd_01_nf = @@ -10828,13 +10995,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_02_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_02_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1997] // RCL Ev,Ib + (const void *)&gInstructions[ 2001] // RCL Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_02_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1988] // RCL Ev,Ib + (const void *)&gInstructions[ 1992] // RCL Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_02_l_00_nd_00_nf = @@ -10869,13 +11036,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_02_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_01_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2167] // ROR Bv,Ev,Ib + (const void *)&gInstructions[ 2173] // ROR Bv,Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_01_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2158] // ROR Bv,Ev,Ib + (const void *)&gInstructions[ 2164] // ROR Bv,Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_01_l_00_nd_01_nf = @@ -10890,13 +11057,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_01_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_01_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2149] // ROR Ev,Ib + (const void *)&gInstructions[ 2155] // ROR Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_01_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2140] // ROR Ev,Ib + (const void *)&gInstructions[ 2146] // ROR Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_01_l_00_nd_00_nf = @@ -10931,13 +11098,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_00_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2125] // ROL Bv,Ev,Ib + (const void *)&gInstructions[ 2131] // ROL Bv,Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_00_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2116] // ROL Bv,Ev,Ib + (const void *)&gInstructions[ 2122] // ROL Bv,Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_00_l_00_nd_01_nf = @@ -10952,13 +11119,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_00_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_00_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2107] // ROL Ev,Ib + (const void *)&gInstructions[ 2113] // ROL Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2098] // ROL Ev,Ib + (const void *)&gInstructions[ 2104] // ROL Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_00_l_00_nd_00_nf = @@ -11008,13 +11175,13 @@ const ND_TABLE_MODRM_REG gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_07_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2262] // SAR Bv,Ev,Ib + (const void *)&gInstructions[ 2268] // SAR Bv,Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_07_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2253] // SAR Bv,Ev,Ib + (const void *)&gInstructions[ 2259] // SAR Bv,Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_07_l_00_nd_01_nf = @@ -11029,13 +11196,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_07_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_07_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2244] // SAR Ev,Ib + (const void *)&gInstructions[ 2250] // SAR Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_07_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2235] // SAR Ev,Ib + (const void *)&gInstructions[ 2241] // SAR Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_07_l_00_nd_00_nf = @@ -11070,13 +11237,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_07_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_06_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2219] // SAL Bv,Ev,Ib + (const void *)&gInstructions[ 2225] // SAL Bv,Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_06_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2210] // SAL Bv,Ev,Ib + (const void *)&gInstructions[ 2216] // SAL Bv,Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_06_l_00_nd_01_nf = @@ -11091,13 +11258,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_06_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_06_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2201] // SAL Ev,Ib + (const void *)&gInstructions[ 2207] // SAL Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_06_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2192] // SAL Ev,Ib + (const void *)&gInstructions[ 2198] // SAL Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_06_l_00_nd_00_nf = @@ -11132,13 +11299,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_06_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_05_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2456] // SHR Bv,Ev,Ib + (const void *)&gInstructions[ 2462] // SHR Bv,Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_05_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2447] // SHR Bv,Ev,Ib + (const void *)&gInstructions[ 2453] // SHR Bv,Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_05_l_00_nd_01_nf = @@ -11153,13 +11320,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_05_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_05_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2438] // SHR Ev,Ib + (const void *)&gInstructions[ 2444] // SHR Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_05_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2429] // SHR Ev,Ib + (const void *)&gInstructions[ 2435] // SHR Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_05_l_00_nd_00_nf = @@ -11194,13 +11361,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_05_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_04_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2394] // SHL Bv,Ev,Ib + (const void *)&gInstructions[ 2400] // SHL Bv,Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_04_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2385] // SHL Bv,Ev,Ib + (const void *)&gInstructions[ 2391] // SHL Bv,Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_04_l_00_nd_01_nf = @@ -11215,13 +11382,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_04_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_04_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2376] // SHL Ev,Ib + (const void *)&gInstructions[ 2382] // SHL Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_04_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2367] // SHL Ev,Ib + (const void *)&gInstructions[ 2373] // SHL Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_04_l_00_nd_00_nf = @@ -11256,13 +11423,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_04_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_03_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2058] // RCR Bv,Ev,Ib + (const void *)&gInstructions[ 2062] // RCR Bv,Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_03_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2049] // RCR Bv,Ev,Ib + (const void *)&gInstructions[ 2053] // RCR Bv,Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_03_l_00_nd_01_nf = @@ -11277,13 +11444,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_03_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_03_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2040] // RCR Ev,Ib + (const void *)&gInstructions[ 2044] // RCR Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_03_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2031] // RCR Ev,Ib + (const void *)&gInstructions[ 2035] // RCR Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_03_l_00_nd_00_nf = @@ -11318,13 +11485,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_03_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_02_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2014] // RCL Bv,Ev,Ib + (const void *)&gInstructions[ 2018] // RCL Bv,Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_02_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2005] // RCL Bv,Ev,Ib + (const void *)&gInstructions[ 2009] // RCL Bv,Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_02_l_00_nd_01_nf = @@ -11339,13 +11506,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_02_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_02_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1996] // RCL Ev,Ib + (const void *)&gInstructions[ 2000] // RCL Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_02_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1987] // RCL Ev,Ib + (const void *)&gInstructions[ 1991] // RCL Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_02_l_00_nd_00_nf = @@ -11380,13 +11547,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_02_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_01_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2166] // ROR Bv,Ev,Ib + (const void *)&gInstructions[ 2172] // ROR Bv,Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_01_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2157] // ROR Bv,Ev,Ib + (const void *)&gInstructions[ 2163] // ROR Bv,Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_01_l_00_nd_01_nf = @@ -11401,13 +11568,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_01_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_01_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2148] // ROR Ev,Ib + (const void *)&gInstructions[ 2154] // ROR Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_01_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2139] // ROR Ev,Ib + (const void *)&gInstructions[ 2145] // ROR Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_01_l_00_nd_00_nf = @@ -11442,13 +11609,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_00_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2124] // ROL Bv,Ev,Ib + (const void *)&gInstructions[ 2130] // ROL Bv,Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_00_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2115] // ROL Bv,Ev,Ib + (const void *)&gInstructions[ 2121] // ROL Bv,Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_00_l_00_nd_01_nf = @@ -11463,13 +11630,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_00_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_00_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2106] // ROL Ev,Ib + (const void *)&gInstructions[ 2112] // ROL Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2097] // ROL Ev,Ib + (const void *)&gInstructions[ 2103] // ROL Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_00_l_00_nd_00_nf = @@ -11530,13 +11697,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_c1_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_07_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2261] // SAR Bb,Eb,Ib + (const void *)&gInstructions[ 2267] // SAR Bb,Eb,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_07_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2252] // SAR Bb,Eb,Ib + (const void *)&gInstructions[ 2258] // SAR Bb,Eb,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_07_l_00_nd_01_nf = @@ -11551,13 +11718,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_07_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_07_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2243] // SAR Eb,Ib + (const void *)&gInstructions[ 2249] // SAR Eb,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_07_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2234] // SAR Eb,Ib + (const void *)&gInstructions[ 2240] // SAR Eb,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_07_l_00_nd_00_nf = @@ -11592,13 +11759,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_07_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_06_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2218] // SAL Bb,Eb,Ib + (const void *)&gInstructions[ 2224] // SAL Bb,Eb,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_06_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2209] // SAL Bb,Eb,Ib + (const void *)&gInstructions[ 2215] // SAL Bb,Eb,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_06_l_00_nd_01_nf = @@ -11613,13 +11780,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_06_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_06_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2200] // SAL Eb,Ib + (const void *)&gInstructions[ 2206] // SAL Eb,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_06_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2191] // SAL Eb,Ib + (const void *)&gInstructions[ 2197] // SAL Eb,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_06_l_00_nd_00_nf = @@ -11654,13 +11821,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_06_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_05_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2455] // SHR Bb,Eb,Ib + (const void *)&gInstructions[ 2461] // SHR Bb,Eb,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_05_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2446] // SHR Bb,Eb,Ib + (const void *)&gInstructions[ 2452] // SHR Bb,Eb,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_05_l_00_nd_01_nf = @@ -11675,13 +11842,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_05_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_05_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2437] // SHR Eb,Ib + (const void *)&gInstructions[ 2443] // SHR Eb,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_05_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2428] // SHR Eb,Ib + (const void *)&gInstructions[ 2434] // SHR Eb,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_05_l_00_nd_00_nf = @@ -11716,13 +11883,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_05_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_04_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2393] // SHL Bb,Eb,Ib + (const void *)&gInstructions[ 2399] // SHL Bb,Eb,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_04_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2384] // SHL Bb,Eb,Ib + (const void *)&gInstructions[ 2390] // SHL Bb,Eb,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_04_l_00_nd_01_nf = @@ -11737,13 +11904,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_04_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_04_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2375] // SHL Eb,Ib + (const void *)&gInstructions[ 2381] // SHL Eb,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_04_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2366] // SHL Eb,Ib + (const void *)&gInstructions[ 2372] // SHL Eb,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_04_l_00_nd_00_nf = @@ -11778,13 +11945,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_04_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_03_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2057] // RCR Bb,Eb,Ib + (const void *)&gInstructions[ 2061] // RCR Bb,Eb,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_03_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2048] // RCR Bb,Eb,Ib + (const void *)&gInstructions[ 2052] // RCR Bb,Eb,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_03_l_00_nd_01_nf = @@ -11799,13 +11966,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_03_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_03_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2039] // RCR Eb,Ib + (const void *)&gInstructions[ 2043] // RCR Eb,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_03_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2030] // RCR Eb,Ib + (const void *)&gInstructions[ 2034] // RCR Eb,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_03_l_00_nd_00_nf = @@ -11840,13 +12007,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_03_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_02_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2013] // RCL Bb,Eb,Ib + (const void *)&gInstructions[ 2017] // RCL Bb,Eb,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_02_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2004] // RCL Bb,Eb,Ib + (const void *)&gInstructions[ 2008] // RCL Bb,Eb,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_02_l_00_nd_01_nf = @@ -11861,13 +12028,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_02_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_02_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1995] // RCL Eb,Ib + (const void *)&gInstructions[ 1999] // RCL Eb,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_02_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1986] // RCL Eb,Ib + (const void *)&gInstructions[ 1990] // RCL Eb,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_02_l_00_nd_00_nf = @@ -11902,13 +12069,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_02_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_01_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2165] // ROR Bb,Eb,Ib + (const void *)&gInstructions[ 2171] // ROR Bb,Eb,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_01_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2156] // ROR Bb,Eb,Ib + (const void *)&gInstructions[ 2162] // ROR Bb,Eb,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_01_l_00_nd_01_nf = @@ -11923,13 +12090,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_01_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_01_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2147] // ROR Eb,Ib + (const void *)&gInstructions[ 2153] // ROR Eb,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_01_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2138] // ROR Eb,Ib + (const void *)&gInstructions[ 2144] // ROR Eb,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_01_l_00_nd_00_nf = @@ -11964,13 +12131,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_00_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2123] // ROL Bb,Eb,Ib + (const void *)&gInstructions[ 2129] // ROL Bb,Eb,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_00_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2114] // ROL Bb,Eb,Ib + (const void *)&gInstructions[ 2120] // ROL Bb,Eb,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_00_l_00_nd_01_nf = @@ -11985,13 +12152,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_00_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_00_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2105] // ROL Eb,Ib + (const void *)&gInstructions[ 2111] // ROL Eb,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2096] // ROL Eb,Ib + (const void *)&gInstructions[ 2102] // ROL Eb,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_00_l_00_nd_00_nf = @@ -12187,13 +12354,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_af_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_ad_pp_01_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2485] // SHRD Bv,Ev,Gv,CL + (const void *)&gInstructions[ 2491] // SHRD Bv,Ev,Gv,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_ad_pp_01_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2481] // SHRD Bv,Ev,Gv,CL + (const void *)&gInstructions[ 2487] // SHRD Bv,Ev,Gv,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_ad_pp_01_l_00_nd_01_nf = @@ -12208,13 +12375,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_ad_pp_01_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_ad_pp_01_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2477] // SHRD Ev,Gv,CL + (const void *)&gInstructions[ 2483] // SHRD Ev,Gv,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_ad_pp_01_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2473] // SHRD Ev,Gv,CL + (const void *)&gInstructions[ 2479] // SHRD Ev,Gv,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_ad_pp_01_l_00_nd_00_nf = @@ -12249,13 +12416,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_ad_pp_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_ad_pp_00_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2483] // SHRD Bv,Ev,Gv,CL + (const void *)&gInstructions[ 2489] // SHRD Bv,Ev,Gv,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_ad_pp_00_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2479] // SHRD Bv,Ev,Gv,CL + (const void *)&gInstructions[ 2485] // SHRD Bv,Ev,Gv,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_ad_pp_00_l_00_nd_01_nf = @@ -12270,13 +12437,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_ad_pp_00_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_ad_pp_00_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2475] // SHRD Ev,Gv,CL + (const void *)&gInstructions[ 2481] // SHRD Ev,Gv,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_ad_pp_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2471] // SHRD Ev,Gv,CL + (const void *)&gInstructions[ 2477] // SHRD Ev,Gv,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_ad_pp_00_l_00_nd_00_nf = @@ -12322,13 +12489,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_ad_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_a5_pp_01_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2423] // SHLD Bv,Ev,Gv,CL + (const void *)&gInstructions[ 2429] // SHLD Bv,Ev,Gv,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_a5_pp_01_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2419] // SHLD Bv,Ev,Gv,CL + (const void *)&gInstructions[ 2425] // SHLD Bv,Ev,Gv,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_a5_pp_01_l_00_nd_01_nf = @@ -12343,13 +12510,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_a5_pp_01_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_a5_pp_01_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2415] // SHLD Ev,Gv,CL + (const void *)&gInstructions[ 2421] // SHLD Ev,Gv,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_a5_pp_01_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2411] // SHLD Ev,Gv,CL + (const void *)&gInstructions[ 2417] // SHLD Ev,Gv,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_a5_pp_01_l_00_nd_00_nf = @@ -12384,13 +12551,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_a5_pp_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_a5_pp_00_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2421] // SHLD Bv,Ev,Gv,CL + (const void *)&gInstructions[ 2427] // SHLD Bv,Ev,Gv,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_a5_pp_00_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2417] // SHLD Bv,Ev,Gv,CL + (const void *)&gInstructions[ 2423] // SHLD Bv,Ev,Gv,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_a5_pp_00_l_00_nd_01_nf = @@ -12405,13 +12572,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_a5_pp_00_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_a5_pp_00_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2413] // SHLD Ev,Gv,CL + (const void *)&gInstructions[ 2419] // SHLD Ev,Gv,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_a5_pp_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2409] // SHLD Ev,Gv,CL + (const void *)&gInstructions[ 2415] // SHLD Ev,Gv,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_a5_pp_00_l_00_nd_00_nf = @@ -12457,7 +12624,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_a5_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_8f_pp_00_modrmreg_00_modrmmod_01_l_00_w_01_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1830] // POP2P Bv,Rv + (const void *)&gInstructions[ 1832] // POP2P Bv,Rv }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_8f_pp_00_modrmreg_00_modrmmod_01_l_00_w_01_nd_01_nf = @@ -12481,7 +12648,7 @@ const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_8f_pp_00_modrmreg_00_modrmmod_01_l const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_8f_pp_00_modrmreg_00_modrmmod_01_l_00_w_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1829] // POP2 Bv,Rv + (const void *)&gInstructions[ 1831] // POP2 Bv,Rv }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_8f_pp_00_modrmreg_00_modrmmod_01_l_00_w_00_nd_01_nf = @@ -12560,13 +12727,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_8f_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_88_pp_01_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1836] // POPCNT Gv,Ev + (const void *)&gInstructions[ 1838] // POPCNT Gv,Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_88_pp_01_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1834] // POPCNT Gv,Ev + (const void *)&gInstructions[ 1836] // POPCNT Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_88_pp_01_l_00_nd_00_nf = @@ -12601,13 +12768,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_88_pp_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_88_pp_00_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1835] // POPCNT Gv,Ev + (const void *)&gInstructions[ 1837] // POPCNT Gv,Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_88_pp_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1833] // POPCNT Gv,Ev + (const void *)&gInstructions[ 1835] // POPCNT Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_88_pp_00_l_00_nd_00_nf = @@ -13231,13 +13398,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_06_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4128] // XOR Bv,Ev,Ib + (const void *)&gInstructions[ 4177] // XOR Bv,Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_06_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4117] // XOR Bv,Ev,Ib + (const void *)&gInstructions[ 4166] // XOR Bv,Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_06_l_00_nd_01_nf = @@ -13252,13 +13419,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_06_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_06_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4106] // XOR Ev,Ib + (const void *)&gInstructions[ 4155] // XOR Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_06_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4095] // XOR Ev,Ib + (const void *)&gInstructions[ 4144] // XOR Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_06_l_00_nd_00_nf = @@ -13293,13 +13460,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_06_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_05_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2566] // SUB Bv,Ev,Ib + (const void *)&gInstructions[ 2572] // SUB Bv,Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_05_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2555] // SUB Bv,Ev,Ib + (const void *)&gInstructions[ 2561] // SUB Bv,Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_05_l_00_nd_01_nf = @@ -13314,13 +13481,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_05_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_05_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2544] // SUB Ev,Ib + (const void *)&gInstructions[ 2550] // SUB Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_05_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2533] // SUB Ev,Ib + (const void *)&gInstructions[ 2539] // SUB Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_05_l_00_nd_00_nf = @@ -13417,7 +13584,7 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_04_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_03_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2300] // SBB Bv,Ev,Ib + (const void *)&gInstructions[ 2306] // SBB Bv,Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_03_l_00_nd_01_nf = @@ -13432,7 +13599,7 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_03_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_03_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2289] // SBB Ev,Ib + (const void *)&gInstructions[ 2295] // SBB Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_03_l_00_nd_00_nf = @@ -13517,13 +13684,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_02_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_01_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1623] // OR Bv,Ev,Ib + (const void *)&gInstructions[ 1625] // OR Bv,Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_01_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1612] // OR Bv,Ev,Ib + (const void *)&gInstructions[ 1614] // OR Bv,Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_01_l_00_nd_01_nf = @@ -13538,13 +13705,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_01_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_01_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1601] // OR Ev,Ib + (const void *)&gInstructions[ 1603] // OR Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_01_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1590] // OR Ev,Ib + (const void *)&gInstructions[ 1592] // OR Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_01_l_00_nd_00_nf = @@ -13795,13 +13962,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_06_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4127] // XOR Bv,Ev,Ib + (const void *)&gInstructions[ 4176] // XOR Bv,Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_06_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4116] // XOR Bv,Ev,Ib + (const void *)&gInstructions[ 4165] // XOR Bv,Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_06_l_00_nd_01_nf = @@ -13816,13 +13983,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_06_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_06_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4105] // XOR Ev,Ib + (const void *)&gInstructions[ 4154] // XOR Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_06_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4094] // XOR Ev,Ib + (const void *)&gInstructions[ 4143] // XOR Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_06_l_00_nd_00_nf = @@ -13857,13 +14024,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_06_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_05_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2565] // SUB Bv,Ev,Ib + (const void *)&gInstructions[ 2571] // SUB Bv,Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_05_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2554] // SUB Bv,Ev,Ib + (const void *)&gInstructions[ 2560] // SUB Bv,Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_05_l_00_nd_01_nf = @@ -13878,13 +14045,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_05_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_05_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2543] // SUB Ev,Ib + (const void *)&gInstructions[ 2549] // SUB Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_05_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2532] // SUB Ev,Ib + (const void *)&gInstructions[ 2538] // SUB Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_05_l_00_nd_00_nf = @@ -13981,7 +14148,7 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_04_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_03_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2299] // SBB Bv,Ev,Ib + (const void *)&gInstructions[ 2305] // SBB Bv,Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_03_l_00_nd_01_nf = @@ -13996,7 +14163,7 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_03_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_03_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2288] // SBB Ev,Ib + (const void *)&gInstructions[ 2294] // SBB Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_03_l_00_nd_00_nf = @@ -14081,13 +14248,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_02_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_01_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1622] // OR Bv,Ev,Ib + (const void *)&gInstructions[ 1624] // OR Bv,Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_01_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1611] // OR Bv,Ev,Ib + (const void *)&gInstructions[ 1613] // OR Bv,Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_01_l_00_nd_01_nf = @@ -14102,13 +14269,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_01_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_01_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1600] // OR Ev,Ib + (const void *)&gInstructions[ 1602] // OR Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_01_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1589] // OR Ev,Ib + (const void *)&gInstructions[ 1591] // OR Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_01_l_00_nd_00_nf = @@ -14370,13 +14537,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_06_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4126] // XOR Bv,Ev,Iz + (const void *)&gInstructions[ 4175] // XOR Bv,Ev,Iz }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_06_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4115] // XOR Bv,Ev,Iz + (const void *)&gInstructions[ 4164] // XOR Bv,Ev,Iz }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_06_l_00_nd_01_nf = @@ -14391,13 +14558,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_06_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_06_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4104] // XOR Ev,Iz + (const void *)&gInstructions[ 4153] // XOR Ev,Iz }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_06_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4093] // XOR Ev,Iz + (const void *)&gInstructions[ 4142] // XOR Ev,Iz }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_06_l_00_nd_00_nf = @@ -14432,13 +14599,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_06_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_05_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2564] // SUB Bv,Ev,Iz + (const void *)&gInstructions[ 2570] // SUB Bv,Ev,Iz }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_05_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2553] // SUB Bv,Ev,Iz + (const void *)&gInstructions[ 2559] // SUB Bv,Ev,Iz }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_05_l_00_nd_01_nf = @@ -14453,13 +14620,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_05_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_05_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2542] // SUB Ev,Iz + (const void *)&gInstructions[ 2548] // SUB Ev,Iz }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_05_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2531] // SUB Ev,Iz + (const void *)&gInstructions[ 2537] // SUB Ev,Iz }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_05_l_00_nd_00_nf = @@ -14556,7 +14723,7 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_04_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_03_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2298] // SBB Bv,Ev,Iz + (const void *)&gInstructions[ 2304] // SBB Bv,Ev,Iz }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_03_l_00_nd_01_nf = @@ -14571,7 +14738,7 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_03_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_03_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2287] // SBB Ev,Iz + (const void *)&gInstructions[ 2293] // SBB Ev,Iz }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_03_l_00_nd_00_nf = @@ -14656,13 +14823,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_02_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_01_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1621] // OR Bv,Ev,Iz + (const void *)&gInstructions[ 1623] // OR Bv,Ev,Iz }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_01_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1610] // OR Bv,Ev,Iz + (const void *)&gInstructions[ 1612] // OR Bv,Ev,Iz }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_01_l_00_nd_01_nf = @@ -14677,13 +14844,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_01_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_01_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1599] // OR Ev,Iz + (const void *)&gInstructions[ 1601] // OR Ev,Iz }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_01_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1588] // OR Ev,Iz + (const void *)&gInstructions[ 1590] // OR Ev,Iz }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_01_l_00_nd_00_nf = @@ -14934,13 +15101,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_06_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4125] // XOR Bv,Ev,Iz + (const void *)&gInstructions[ 4174] // XOR Bv,Ev,Iz }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_06_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4114] // XOR Bv,Ev,Iz + (const void *)&gInstructions[ 4163] // XOR Bv,Ev,Iz }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_06_l_00_nd_01_nf = @@ -14955,13 +15122,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_06_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_06_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4103] // XOR Ev,Iz + (const void *)&gInstructions[ 4152] // XOR Ev,Iz }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_06_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4092] // XOR Ev,Iz + (const void *)&gInstructions[ 4141] // XOR Ev,Iz }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_06_l_00_nd_00_nf = @@ -14996,13 +15163,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_06_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_05_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2563] // SUB Bv,Ev,Iz + (const void *)&gInstructions[ 2569] // SUB Bv,Ev,Iz }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_05_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2552] // SUB Bv,Ev,Iz + (const void *)&gInstructions[ 2558] // SUB Bv,Ev,Iz }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_05_l_00_nd_01_nf = @@ -15017,13 +15184,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_05_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_05_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2541] // SUB Ev,Iz + (const void *)&gInstructions[ 2547] // SUB Ev,Iz }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_05_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2530] // SUB Ev,Iz + (const void *)&gInstructions[ 2536] // SUB Ev,Iz }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_05_l_00_nd_00_nf = @@ -15120,7 +15287,7 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_04_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_03_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2297] // SBB Bv,Ev,Iz + (const void *)&gInstructions[ 2303] // SBB Bv,Ev,Iz }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_03_l_00_nd_01_nf = @@ -15135,7 +15302,7 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_03_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_03_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2286] // SBB Ev,Iz + (const void *)&gInstructions[ 2292] // SBB Ev,Iz }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_03_l_00_nd_00_nf = @@ -15220,13 +15387,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_02_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_01_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1620] // OR Bv,Ev,Iz + (const void *)&gInstructions[ 1622] // OR Bv,Ev,Iz }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_01_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1609] // OR Bv,Ev,Iz + (const void *)&gInstructions[ 1611] // OR Bv,Ev,Iz }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_01_l_00_nd_01_nf = @@ -15241,13 +15408,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_01_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_01_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1598] // OR Ev,Iz + (const void *)&gInstructions[ 1600] // OR Ev,Iz }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_01_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1587] // OR Ev,Iz + (const void *)&gInstructions[ 1589] // OR Ev,Iz }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_01_l_00_nd_00_nf = @@ -15509,13 +15676,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_06_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4124] // XOR Bb,Eb,Ib + (const void *)&gInstructions[ 4173] // XOR Bb,Eb,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_06_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4113] // XOR Bb,Eb,Ib + (const void *)&gInstructions[ 4162] // XOR Bb,Eb,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_06_l_00_nd_01_nf = @@ -15530,13 +15697,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_06_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_06_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4102] // XOR Eb,Ib + (const void *)&gInstructions[ 4151] // XOR Eb,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_06_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4091] // XOR Eb,Ib + (const void *)&gInstructions[ 4140] // XOR Eb,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_06_l_00_nd_00_nf = @@ -15571,13 +15738,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_06_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_05_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2562] // SUB Bb,Eb,Ib + (const void *)&gInstructions[ 2568] // SUB Bb,Eb,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_05_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2551] // SUB Bb,Eb,Ib + (const void *)&gInstructions[ 2557] // SUB Bb,Eb,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_05_l_00_nd_01_nf = @@ -15592,13 +15759,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_05_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_05_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2540] // SUB Eb,Ib + (const void *)&gInstructions[ 2546] // SUB Eb,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_05_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2529] // SUB Eb,Ib + (const void *)&gInstructions[ 2535] // SUB Eb,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_05_l_00_nd_00_nf = @@ -15695,7 +15862,7 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_04_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_03_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2296] // SBB Bb,Eb,Ib + (const void *)&gInstructions[ 2302] // SBB Bb,Eb,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_03_l_00_nd_01_nf = @@ -15710,7 +15877,7 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_03_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_03_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2285] // SBB Eb,Ib + (const void *)&gInstructions[ 2291] // SBB Eb,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_03_l_00_nd_00_nf = @@ -15795,13 +15962,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_02_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_01_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1619] // OR Bb,Eb,Ib + (const void *)&gInstructions[ 1621] // OR Bb,Eb,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_01_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1608] // OR Bb,Eb,Ib + (const void *)&gInstructions[ 1610] // OR Bb,Eb,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_01_l_00_nd_01_nf = @@ -15816,13 +15983,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_01_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_01_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1597] // OR Eb,Ib + (const void *)&gInstructions[ 1599] // OR Eb,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_01_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1586] // OR Eb,Ib + (const void *)&gInstructions[ 1588] // OR Eb,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_01_l_00_nd_00_nf = @@ -16315,7 +16482,7 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_66_pp_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_66_pp_00_modrmmod_00_l_00_w_01_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4062] // WRSSQ My,Gy + (const void *)&gInstructions[ 4111] // WRSSQ My,Gy }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_66_pp_00_modrmmod_00_l_00_w_01_nd_00_nf = @@ -16339,7 +16506,7 @@ const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_66_pp_00_modrmmod_00_l_00_w_01_nd const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_66_pp_00_modrmmod_00_l_00_w_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4060] // WRSSD My,Gy + (const void *)&gInstructions[ 4109] // WRSSD My,Gy }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_66_pp_00_modrmmod_00_l_00_w_00_nd_00_nf = @@ -16403,7 +16570,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_66_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_65_pp_01_modrmmod_00_l_00_w_01_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4066] // WRUSSQ My,Gy + (const void *)&gInstructions[ 4115] // WRUSSQ My,Gy }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_65_pp_01_modrmmod_00_l_00_w_01_nd_00_nf = @@ -16427,7 +16594,7 @@ const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_65_pp_01_modrmmod_00_l_00_w_01_nd const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_65_pp_01_modrmmod_00_l_00_w_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4064] // WRUSSD My,Gy + (const void *)&gInstructions[ 4113] // WRUSSD My,Gy }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_65_pp_01_modrmmod_00_l_00_w_00_nd_00_nf = @@ -16653,7 +16820,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_60_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4f_pp_03_l_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2338] // SETNLE Eb + (const void *)&gInstructions[ 2344] // SETNLE Eb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4f_pp_03_l_00_nf = @@ -16844,7 +17011,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_4f_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4e_pp_03_l_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2330] // SETLE Eb + (const void *)&gInstructions[ 2336] // SETLE Eb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4e_pp_03_l_00_nf = @@ -17035,7 +17202,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_4e_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4d_pp_03_l_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2336] // SETNL Eb + (const void *)&gInstructions[ 2342] // SETNL Eb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4d_pp_03_l_00_nf = @@ -17226,7 +17393,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_4d_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4c_pp_03_l_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2328] // SETL Eb + (const void *)&gInstructions[ 2334] // SETL Eb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4c_pp_03_l_00_nf = @@ -17417,7 +17584,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_4c_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4b_pp_03_l_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2342] // SETNP Eb + (const void *)&gInstructions[ 2348] // SETNP Eb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4b_pp_03_l_00_nf = @@ -17608,7 +17775,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_4b_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4a_pp_03_l_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2350] // SETP Eb + (const void *)&gInstructions[ 2356] // SETP Eb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4a_pp_03_l_00_nf = @@ -17799,7 +17966,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_4a_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_49_pp_03_l_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2344] // SETNS Eb + (const void *)&gInstructions[ 2350] // SETNS Eb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_49_pp_03_l_00_nf = @@ -17990,7 +18157,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_49_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_48_pp_03_l_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2352] // SETS Eb + (const void *)&gInstructions[ 2358] // SETS Eb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_48_pp_03_l_00_nf = @@ -18181,7 +18348,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_48_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_47_pp_03_l_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2332] // SETNBE Eb + (const void *)&gInstructions[ 2338] // SETNBE Eb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_47_pp_03_l_00_nf = @@ -18372,7 +18539,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_47_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_46_pp_03_l_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2324] // SETBE Eb + (const void *)&gInstructions[ 2330] // SETBE Eb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_46_pp_03_l_00_nf = @@ -18563,7 +18730,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_46_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_45_pp_03_l_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2346] // SETNZ Eb + (const void *)&gInstructions[ 2352] // SETNZ Eb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_45_pp_03_l_00_nf = @@ -18754,7 +18921,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_45_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_44_pp_03_l_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2355] // SETZ Eb + (const void *)&gInstructions[ 2361] // SETZ Eb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_44_pp_03_l_00_nf = @@ -18945,7 +19112,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_44_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_43_pp_03_l_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2334] // SETNC Eb + (const void *)&gInstructions[ 2340] // SETNC Eb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_43_pp_03_l_00_nf = @@ -19136,7 +19303,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_43_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_42_pp_03_l_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2326] // SETC Eb + (const void *)&gInstructions[ 2332] // SETC Eb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_42_pp_03_l_00_nf = @@ -19327,7 +19494,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_42_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_41_pp_03_l_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2340] // SETNO Eb + (const void *)&gInstructions[ 2346] // SETNO Eb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_41_pp_03_l_00_nf = @@ -19518,7 +19685,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_41_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_40_pp_03_l_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2348] // SETO Eb + (const void *)&gInstructions[ 2354] // SETO Eb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_40_pp_03_l_00_nf = @@ -20587,13 +20754,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_38_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_33_pp_01_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4123] // XOR Bv,Gv,Ev + (const void *)&gInstructions[ 4172] // XOR Bv,Gv,Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_33_pp_01_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4112] // XOR Bv,Gv,Ev + (const void *)&gInstructions[ 4161] // XOR Bv,Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_33_pp_01_l_00_nd_01_nf = @@ -20608,13 +20775,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_33_pp_01_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_33_pp_01_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4101] // XOR Gv,Ev + (const void *)&gInstructions[ 4150] // XOR Gv,Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_33_pp_01_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4090] // XOR Gv,Ev + (const void *)&gInstructions[ 4139] // XOR Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_33_pp_01_l_00_nd_00_nf = @@ -20649,13 +20816,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_33_pp_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_33_pp_00_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4122] // XOR Bv,Gv,Ev + (const void *)&gInstructions[ 4171] // XOR Bv,Gv,Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_33_pp_00_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4111] // XOR Bv,Gv,Ev + (const void *)&gInstructions[ 4160] // XOR Bv,Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_33_pp_00_l_00_nd_01_nf = @@ -20670,13 +20837,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_33_pp_00_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_33_pp_00_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4100] // XOR Gv,Ev + (const void *)&gInstructions[ 4149] // XOR Gv,Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_33_pp_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4089] // XOR Gv,Ev + (const void *)&gInstructions[ 4138] // XOR Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_33_pp_00_l_00_nd_00_nf = @@ -20722,13 +20889,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_33_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_32_pp_00_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4121] // XOR Bb,Gb,Eb + (const void *)&gInstructions[ 4170] // XOR Bb,Gb,Eb }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_32_pp_00_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4110] // XOR Bb,Gb,Eb + (const void *)&gInstructions[ 4159] // XOR Bb,Gb,Eb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_32_pp_00_l_00_nd_01_nf = @@ -20743,13 +20910,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_32_pp_00_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_32_pp_00_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4099] // XOR Gb,Eb + (const void *)&gInstructions[ 4148] // XOR Gb,Eb }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_32_pp_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4088] // XOR Gb,Eb + (const void *)&gInstructions[ 4137] // XOR Gb,Eb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_32_pp_00_l_00_nd_00_nf = @@ -20795,13 +20962,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_32_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_31_pp_01_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4120] // XOR Bv,Ev,Gv + (const void *)&gInstructions[ 4169] // XOR Bv,Ev,Gv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_31_pp_01_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4109] // XOR Bv,Ev,Gv + (const void *)&gInstructions[ 4158] // XOR Bv,Ev,Gv }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_31_pp_01_l_00_nd_01_nf = @@ -20816,13 +20983,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_31_pp_01_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_31_pp_01_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4098] // XOR Ev,Gv + (const void *)&gInstructions[ 4147] // XOR Ev,Gv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_31_pp_01_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4087] // XOR Ev,Gv + (const void *)&gInstructions[ 4136] // XOR Ev,Gv }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_31_pp_01_l_00_nd_00_nf = @@ -20857,13 +21024,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_31_pp_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_31_pp_00_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4119] // XOR Bv,Ev,Gv + (const void *)&gInstructions[ 4168] // XOR Bv,Ev,Gv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_31_pp_00_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4108] // XOR Bv,Ev,Gv + (const void *)&gInstructions[ 4157] // XOR Bv,Ev,Gv }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_31_pp_00_l_00_nd_01_nf = @@ -20878,13 +21045,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_31_pp_00_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_31_pp_00_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4097] // XOR Ev,Gv + (const void *)&gInstructions[ 4146] // XOR Ev,Gv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_31_pp_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4086] // XOR Ev,Gv + (const void *)&gInstructions[ 4135] // XOR Ev,Gv }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_31_pp_00_l_00_nd_00_nf = @@ -20930,13 +21097,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_31_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_30_pp_00_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4118] // XOR Bb,Eb,Gb + (const void *)&gInstructions[ 4167] // XOR Bb,Eb,Gb }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_30_pp_00_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4107] // XOR Bb,Eb,Gb + (const void *)&gInstructions[ 4156] // XOR Bb,Eb,Gb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_30_pp_00_l_00_nd_01_nf = @@ -20951,13 +21118,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_30_pp_00_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_30_pp_00_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4096] // XOR Eb,Gb + (const void *)&gInstructions[ 4145] // XOR Eb,Gb }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_30_pp_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4085] // XOR Eb,Gb + (const void *)&gInstructions[ 4134] // XOR Eb,Gb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_30_pp_00_l_00_nd_00_nf = @@ -21003,13 +21170,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_30_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_2c_pp_01_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2484] // SHRD Bv,Ev,Gv,Ib + (const void *)&gInstructions[ 2490] // SHRD Bv,Ev,Gv,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_2c_pp_01_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2480] // SHRD Bv,Ev,Gv,Ib + (const void *)&gInstructions[ 2486] // SHRD Bv,Ev,Gv,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_2c_pp_01_l_00_nd_01_nf = @@ -21024,13 +21191,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_2c_pp_01_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_2c_pp_01_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2476] // SHRD Ev,Gv,Ib + (const void *)&gInstructions[ 2482] // SHRD Ev,Gv,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_2c_pp_01_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2472] // SHRD Ev,Gv,Ib + (const void *)&gInstructions[ 2478] // SHRD Ev,Gv,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_2c_pp_01_l_00_nd_00_nf = @@ -21065,13 +21232,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_2c_pp_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_2c_pp_00_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2482] // SHRD Bv,Ev,Gv,Ib + (const void *)&gInstructions[ 2488] // SHRD Bv,Ev,Gv,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_2c_pp_00_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2478] // SHRD Bv,Ev,Gv,Ib + (const void *)&gInstructions[ 2484] // SHRD Bv,Ev,Gv,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_2c_pp_00_l_00_nd_01_nf = @@ -21086,13 +21253,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_2c_pp_00_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_2c_pp_00_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2474] // SHRD Ev,Gv,Ib + (const void *)&gInstructions[ 2480] // SHRD Ev,Gv,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_2c_pp_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2470] // SHRD Ev,Gv,Ib + (const void *)&gInstructions[ 2476] // SHRD Ev,Gv,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_2c_pp_00_l_00_nd_00_nf = @@ -21138,13 +21305,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_2c_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_2b_pp_01_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2561] // SUB Bv,Gv,Ev + (const void *)&gInstructions[ 2567] // SUB Bv,Gv,Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_2b_pp_01_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2550] // SUB Bv,Gv,Ev + (const void *)&gInstructions[ 2556] // SUB Bv,Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_2b_pp_01_l_00_nd_01_nf = @@ -21159,13 +21326,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_2b_pp_01_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_2b_pp_01_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2539] // SUB Gv,Ev + (const void *)&gInstructions[ 2545] // SUB Gv,Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_2b_pp_01_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2528] // SUB Gv,Ev + (const void *)&gInstructions[ 2534] // SUB Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_2b_pp_01_l_00_nd_00_nf = @@ -21200,13 +21367,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_2b_pp_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_2b_pp_00_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2560] // SUB Bv,Gv,Ev + (const void *)&gInstructions[ 2566] // SUB Bv,Gv,Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_2b_pp_00_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2549] // SUB Bv,Gv,Ev + (const void *)&gInstructions[ 2555] // SUB Bv,Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_2b_pp_00_l_00_nd_01_nf = @@ -21221,13 +21388,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_2b_pp_00_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_2b_pp_00_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2538] // SUB Gv,Ev + (const void *)&gInstructions[ 2544] // SUB Gv,Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_2b_pp_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2527] // SUB Gv,Ev + (const void *)&gInstructions[ 2533] // SUB Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_2b_pp_00_l_00_nd_00_nf = @@ -21273,13 +21440,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_2b_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_2a_pp_00_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2559] // SUB Bb,Gb,Eb + (const void *)&gInstructions[ 2565] // SUB Bb,Gb,Eb }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_2a_pp_00_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2548] // SUB Bb,Gb,Eb + (const void *)&gInstructions[ 2554] // SUB Bb,Gb,Eb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_2a_pp_00_l_00_nd_01_nf = @@ -21294,13 +21461,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_2a_pp_00_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_2a_pp_00_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2537] // SUB Gb,Eb + (const void *)&gInstructions[ 2543] // SUB Gb,Eb }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_2a_pp_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2526] // SUB Gb,Eb + (const void *)&gInstructions[ 2532] // SUB Gb,Eb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_2a_pp_00_l_00_nd_00_nf = @@ -21346,13 +21513,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_2a_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_29_pp_01_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2558] // SUB Bv,Ev,Gv + (const void *)&gInstructions[ 2564] // SUB Bv,Ev,Gv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_29_pp_01_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2547] // SUB Bv,Ev,Gv + (const void *)&gInstructions[ 2553] // SUB Bv,Ev,Gv }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_29_pp_01_l_00_nd_01_nf = @@ -21367,13 +21534,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_29_pp_01_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_29_pp_01_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2536] // SUB Ev,Gv + (const void *)&gInstructions[ 2542] // SUB Ev,Gv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_29_pp_01_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2525] // SUB Ev,Gv + (const void *)&gInstructions[ 2531] // SUB Ev,Gv }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_29_pp_01_l_00_nd_00_nf = @@ -21408,13 +21575,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_29_pp_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_29_pp_00_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2557] // SUB Bv,Ev,Gv + (const void *)&gInstructions[ 2563] // SUB Bv,Ev,Gv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_29_pp_00_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2546] // SUB Bv,Ev,Gv + (const void *)&gInstructions[ 2552] // SUB Bv,Ev,Gv }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_29_pp_00_l_00_nd_01_nf = @@ -21429,13 +21596,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_29_pp_00_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_29_pp_00_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2535] // SUB Ev,Gv + (const void *)&gInstructions[ 2541] // SUB Ev,Gv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_29_pp_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2524] // SUB Ev,Gv + (const void *)&gInstructions[ 2530] // SUB Ev,Gv }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_29_pp_00_l_00_nd_00_nf = @@ -21481,13 +21648,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_29_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_28_pp_00_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2556] // SUB Bb,Eb,Gb + (const void *)&gInstructions[ 2562] // SUB Bb,Eb,Gb }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_28_pp_00_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2545] // SUB Bb,Eb,Gb + (const void *)&gInstructions[ 2551] // SUB Bb,Eb,Gb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_28_pp_00_l_00_nd_01_nf = @@ -21502,13 +21669,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_28_pp_00_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_28_pp_00_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2534] // SUB Eb,Gb + (const void *)&gInstructions[ 2540] // SUB Eb,Gb }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_28_pp_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2523] // SUB Eb,Gb + (const void *)&gInstructions[ 2529] // SUB Eb,Gb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_28_pp_00_l_00_nd_00_nf = @@ -21554,13 +21721,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_28_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_24_pp_01_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2422] // SHLD Bv,Ev,Gv,Ib + (const void *)&gInstructions[ 2428] // SHLD Bv,Ev,Gv,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_24_pp_01_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2418] // SHLD Bv,Ev,Gv,Ib + (const void *)&gInstructions[ 2424] // SHLD Bv,Ev,Gv,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_24_pp_01_l_00_nd_01_nf = @@ -21575,13 +21742,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_24_pp_01_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_24_pp_01_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2414] // SHLD Ev,Gv,Ib + (const void *)&gInstructions[ 2420] // SHLD Ev,Gv,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_24_pp_01_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2410] // SHLD Ev,Gv,Ib + (const void *)&gInstructions[ 2416] // SHLD Ev,Gv,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_24_pp_01_l_00_nd_00_nf = @@ -21616,13 +21783,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_24_pp_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_24_pp_00_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2420] // SHLD Bv,Ev,Gv,Ib + (const void *)&gInstructions[ 2426] // SHLD Bv,Ev,Gv,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_24_pp_00_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2416] // SHLD Bv,Ev,Gv,Ib + (const void *)&gInstructions[ 2422] // SHLD Bv,Ev,Gv,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_24_pp_00_l_00_nd_01_nf = @@ -21637,13 +21804,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_24_pp_00_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_24_pp_00_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2412] // SHLD Ev,Gv,Ib + (const void *)&gInstructions[ 2418] // SHLD Ev,Gv,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_24_pp_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2408] // SHLD Ev,Gv,Ib + (const void *)&gInstructions[ 2414] // SHLD Ev,Gv,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_24_pp_00_l_00_nd_00_nf = @@ -22105,7 +22272,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_20_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_1b_pp_01_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2295] // SBB Bv,Gv,Ev + (const void *)&gInstructions[ 2301] // SBB Bv,Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_1b_pp_01_l_00_nd_01_nf = @@ -22120,7 +22287,7 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_1b_pp_01_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_1b_pp_01_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2284] // SBB Gv,Ev + (const void *)&gInstructions[ 2290] // SBB Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_1b_pp_01_l_00_nd_00_nf = @@ -22155,7 +22322,7 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_1b_pp_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_1b_pp_00_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2294] // SBB Bv,Gv,Ev + (const void *)&gInstructions[ 2300] // SBB Bv,Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_1b_pp_00_l_00_nd_01_nf = @@ -22170,7 +22337,7 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_1b_pp_00_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_1b_pp_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2283] // SBB Gv,Ev + (const void *)&gInstructions[ 2289] // SBB Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_1b_pp_00_l_00_nd_00_nf = @@ -22216,7 +22383,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_1b_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_1a_pp_00_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2293] // SBB Bb,Gb,Eb + (const void *)&gInstructions[ 2299] // SBB Bb,Gb,Eb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_1a_pp_00_l_00_nd_01_nf = @@ -22231,7 +22398,7 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_1a_pp_00_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_1a_pp_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2282] // SBB Gb,Eb + (const void *)&gInstructions[ 2288] // SBB Gb,Eb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_1a_pp_00_l_00_nd_00_nf = @@ -22277,7 +22444,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_1a_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_19_pp_01_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2292] // SBB Bv,Ev,Gv + (const void *)&gInstructions[ 2298] // SBB Bv,Ev,Gv }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_19_pp_01_l_00_nd_01_nf = @@ -22292,7 +22459,7 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_19_pp_01_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_19_pp_01_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2281] // SBB Ev,Gv + (const void *)&gInstructions[ 2287] // SBB Ev,Gv }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_19_pp_01_l_00_nd_00_nf = @@ -22327,7 +22494,7 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_19_pp_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_19_pp_00_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2291] // SBB Bv,Ev,Gv + (const void *)&gInstructions[ 2297] // SBB Bv,Ev,Gv }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_19_pp_00_l_00_nd_01_nf = @@ -22342,7 +22509,7 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_19_pp_00_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_19_pp_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2280] // SBB Ev,Gv + (const void *)&gInstructions[ 2286] // SBB Ev,Gv }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_19_pp_00_l_00_nd_00_nf = @@ -22388,7 +22555,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_19_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_18_pp_00_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2290] // SBB Bb,Eb,Gb + (const void *)&gInstructions[ 2296] // SBB Bb,Eb,Gb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_18_pp_00_l_00_nd_01_nf = @@ -22403,7 +22570,7 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_18_pp_00_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_18_pp_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2279] // SBB Eb,Gb + (const void *)&gInstructions[ 2285] // SBB Eb,Gb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_18_pp_00_l_00_nd_00_nf = @@ -22793,13 +22960,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_10_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_0b_pp_01_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1618] // OR Bv,Gv,Ev + (const void *)&gInstructions[ 1620] // OR Bv,Gv,Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_0b_pp_01_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1607] // OR Bv,Gv,Ev + (const void *)&gInstructions[ 1609] // OR Bv,Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_0b_pp_01_l_00_nd_01_nf = @@ -22814,13 +22981,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_0b_pp_01_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_0b_pp_01_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1596] // OR Gv,Ev + (const void *)&gInstructions[ 1598] // OR Gv,Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_0b_pp_01_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1585] // OR Gv,Ev + (const void *)&gInstructions[ 1587] // OR Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_0b_pp_01_l_00_nd_00_nf = @@ -22855,13 +23022,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_0b_pp_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_0b_pp_00_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1617] // OR Bv,Gv,Ev + (const void *)&gInstructions[ 1619] // OR Bv,Gv,Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_0b_pp_00_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1606] // OR Bv,Gv,Ev + (const void *)&gInstructions[ 1608] // OR Bv,Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_0b_pp_00_l_00_nd_01_nf = @@ -22876,13 +23043,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_0b_pp_00_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_0b_pp_00_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1595] // OR Gv,Ev + (const void *)&gInstructions[ 1597] // OR Gv,Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_0b_pp_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1584] // OR Gv,Ev + (const void *)&gInstructions[ 1586] // OR Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_0b_pp_00_l_00_nd_00_nf = @@ -22928,13 +23095,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_0b_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_0a_pp_00_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1616] // OR Bb,Gb,Eb + (const void *)&gInstructions[ 1618] // OR Bb,Gb,Eb }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_0a_pp_00_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1605] // OR Bb,Gb,Eb + (const void *)&gInstructions[ 1607] // OR Bb,Gb,Eb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_0a_pp_00_l_00_nd_01_nf = @@ -22949,13 +23116,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_0a_pp_00_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_0a_pp_00_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1594] // OR Gb,Eb + (const void *)&gInstructions[ 1596] // OR Gb,Eb }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_0a_pp_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1583] // OR Gb,Eb + (const void *)&gInstructions[ 1585] // OR Gb,Eb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_0a_pp_00_l_00_nd_00_nf = @@ -23001,13 +23168,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_0a_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_09_pp_01_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1615] // OR Bv,Ev,Gv + (const void *)&gInstructions[ 1617] // OR Bv,Ev,Gv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_09_pp_01_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1604] // OR Bv,Ev,Gv + (const void *)&gInstructions[ 1606] // OR Bv,Ev,Gv }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_09_pp_01_l_00_nd_01_nf = @@ -23022,13 +23189,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_09_pp_01_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_09_pp_01_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1593] // OR Ev,Gv + (const void *)&gInstructions[ 1595] // OR Ev,Gv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_09_pp_01_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1582] // OR Ev,Gv + (const void *)&gInstructions[ 1584] // OR Ev,Gv }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_09_pp_01_l_00_nd_00_nf = @@ -23063,13 +23230,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_09_pp_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_09_pp_00_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1614] // OR Bv,Ev,Gv + (const void *)&gInstructions[ 1616] // OR Bv,Ev,Gv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_09_pp_00_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1603] // OR Bv,Ev,Gv + (const void *)&gInstructions[ 1605] // OR Bv,Ev,Gv }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_09_pp_00_l_00_nd_01_nf = @@ -23084,13 +23251,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_09_pp_00_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_09_pp_00_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1592] // OR Ev,Gv + (const void *)&gInstructions[ 1594] // OR Ev,Gv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_09_pp_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1581] // OR Ev,Gv + (const void *)&gInstructions[ 1583] // OR Ev,Gv }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_09_pp_00_l_00_nd_00_nf = @@ -23136,13 +23303,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_09_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_08_pp_00_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1613] // OR Bb,Eb,Gb + (const void *)&gInstructions[ 1615] // OR Bb,Eb,Gb }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_08_pp_00_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1602] // OR Bb,Eb,Gb + (const void *)&gInstructions[ 1604] // OR Bb,Eb,Gb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_08_pp_00_l_00_nd_01_nf = @@ -23157,13 +23324,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_08_pp_00_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_08_pp_00_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1591] // OR Eb,Gb + (const void *)&gInstructions[ 1593] // OR Eb,Gb }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_08_pp_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1580] // OR Eb,Gb + (const void *)&gInstructions[ 1582] // OR Eb,Gb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_08_pp_00_l_00_nd_00_nf = @@ -23888,7 +24055,7 @@ const ND_TABLE_OPCODE gEvexMap_mmmmm_04_opcode = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_f0_pp_03_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2180] // RORX Gy,Ey,Ib + (const void *)&gInstructions[ 2186] // RORX Gy,Ey,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_03_opcode_f0_pp_03_l_00_nd_00_nf = @@ -23934,7 +24101,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_f0_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_cf_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3159] // VGF2P8AFFINEINVQB Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib + (const void *)&gInstructions[ 3200] // VGF2P8AFFINEINVQB Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_cf_pp_01_w = @@ -23960,7 +24127,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_cf_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_ce_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3161] // VGF2P8AFFINEQB Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib + (const void *)&gInstructions[ 3202] // VGF2P8AFFINEQB Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_ce_pp_01_w = @@ -23986,7 +24153,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_ce_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_c2_pp_03_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2702] // VCMPPBF16 rK{K},aKq,Hfv,Wfv|B16,Ib + (const void *)&gInstructions[ 2743] // VCMPPBF16 rK{K},aKq,Hfv,Wfv|B16,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_c2_pp_03_w = @@ -24001,7 +24168,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_c2_pp_03_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_c2_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2710] // VCMPSH rK{K},aKq,Hfv,Wsh{sae},Ib + (const void *)&gInstructions[ 2751] // VCMPSH rK{K},aKq,Hfv,Wsh{sae},Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_c2_pp_02_w = @@ -24016,7 +24183,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_c2_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_c2_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2705] // VCMPPH rK{K},aKq,Hfv,Wfv|B16{sae},Ib + (const void *)&gInstructions[ 2746] // VCMPPH rK{K},aKq,Hfv,Wfv|B16{sae},Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_c2_pp_00_w = @@ -24039,16 +24206,97 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_c2_pp = } }; +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_77_pp_03_modrmmod_01_l_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2614] // TCVTROWPS2PHL Voq,mTt,Ib +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_77_pp_03_modrmmod_01_l_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_77_pp_03_modrmmod_01_l_02_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_03_opcode_77_pp_03_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gEvexMap_mmmmm_03_opcode_77_pp_03_modrmmod_01_l_02_w, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_03_opcode_77_pp_03_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_77_pp_03_modrmmod_01_l, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_77_pp_02_modrmmod_01_l_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2610] // TCVTROWPS2PBF16L Voq,mTt,Ib +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_77_pp_02_modrmmod_01_l_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_77_pp_02_modrmmod_01_l_02_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_03_opcode_77_pp_02_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gEvexMap_mmmmm_03_opcode_77_pp_02_modrmmod_01_l_02_w, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_03_opcode_77_pp_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_77_pp_02_modrmmod_01_l, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_77_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gEvexMap_mmmmm_03_opcode_77_pp_02_modrmmod, + /* 03 */ (const void *)&gEvexMap_mmmmm_03_opcode_77_pp_03_modrmmod, + } +}; + const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_73_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3806] // VPSHRDQ Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib + (const void *)&gInstructions[ 3851] // VPSHRDQ Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_73_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3805] // VPSHRDD Vfv{K}{z},aKq,Hfv,Wfv|B32,Ib + (const void *)&gInstructions[ 3850] // VPSHRDD Vfv{K}{z},aKq,Hfv,Wfv|B32,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_73_pp_01_w = @@ -24074,7 +24322,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_73_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_72_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3810] // VPSHRDW Vfv{K}{z},aKq,Hfv,Wfv,Ib + (const void *)&gInstructions[ 3855] // VPSHRDW Vfv{K}{z},aKq,Hfv,Wfv,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_72_pp_01_w = @@ -24100,13 +24348,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_72_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_71_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3797] // VPSHLDQ Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib + (const void *)&gInstructions[ 3842] // VPSHLDQ Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_71_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3796] // VPSHLDD Vfv{K}{z},aKq,Hfv,Wfv|B32,Ib + (const void *)&gInstructions[ 3841] // VPSHLDD Vfv{K}{z},aKq,Hfv,Wfv|B32,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_71_pp_01_w = @@ -24132,7 +24380,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_71_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_70_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3801] // VPSHLDW Vfv{K}{z},aKq,Hfv,Wfv,Ib + (const void *)&gInstructions[ 3846] // VPSHLDW Vfv{K}{z},aKq,Hfv,Wfv,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_70_pp_01_w = @@ -24158,13 +24406,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_70_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_67_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3122] // VFPCLASSSD rKq{K},aKq,Wsd,Ib + (const void *)&gInstructions[ 3163] // VFPCLASSSD rKq{K},aKq,Wsd,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_67_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3124] // VFPCLASSSS rKq{K},aKq,Wss,Ib + (const void *)&gInstructions[ 3165] // VFPCLASSSS rKq{K},aKq,Wss,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_67_pp_01_w = @@ -24179,7 +24427,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_67_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_67_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3123] // VFPCLASSSH rKq{K},aKq,Wsh,Ib + (const void *)&gInstructions[ 3164] // VFPCLASSSH rKq{K},aKq,Wsh,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_67_pp_00_w = @@ -24205,7 +24453,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_67_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_66_pp_03_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3118] // VFPCLASSPBF16 rKq{K},aKq,Wfv|B16,Ib + (const void *)&gInstructions[ 3159] // VFPCLASSPBF16 rKq{K},aKq,Wfv|B16,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_66_pp_03_w = @@ -24220,13 +24468,13 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_66_pp_03_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_66_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3119] // VFPCLASSPD rKq{K},aKq,Wfv|B64,Ib + (const void *)&gInstructions[ 3160] // VFPCLASSPD rKq{K},aKq,Wfv|B64,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_66_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3121] // VFPCLASSPS rKq{K},aKq,Wfv|B32,Ib + (const void *)&gInstructions[ 3162] // VFPCLASSPS rKq{K},aKq,Wfv|B32,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_66_pp_01_w = @@ -24241,7 +24489,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_66_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_66_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3120] // VFPCLASSPH rKq{K},aKq,Wfv|B16,Ib + (const void *)&gInstructions[ 3161] // VFPCLASSPH rKq{K},aKq,Wfv|B16,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_66_pp_00_w = @@ -24267,13 +24515,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_66_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_57_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3942] // VREDUCESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib + (const void *)&gInstructions[ 3987] // VREDUCESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_57_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3944] // VREDUCESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib + (const void *)&gInstructions[ 3989] // VREDUCESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_57_pp_01_w = @@ -24288,7 +24536,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_57_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_57_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3943] // VREDUCESH Vdq{K}{z},aKq,Hdq,Wsh{sae},Ib + (const void *)&gInstructions[ 3988] // VREDUCESH Vdq{K}{z},aKq,Hdq,Wsh{sae},Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_57_pp_00_w = @@ -24314,7 +24562,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_57_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_56_pp_03_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3938] // VREDUCENEPBF16 Vfv{K}{z},aKq,Wfv|B16,Ib + (const void *)&gInstructions[ 3983] // VREDUCENEPBF16 Vfv{K}{z},aKq,Wfv|B16,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_56_pp_03_w = @@ -24329,13 +24577,13 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_56_pp_03_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_56_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3939] // VREDUCEPD Vfv{K}{z},aKq,Wfv|B64{sae},Ib + (const void *)&gInstructions[ 3984] // VREDUCEPD Vfv{K}{z},aKq,Wfv|B64{sae},Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_56_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3941] // VREDUCEPS Vfv{K}{z},aKq,Wfv|B32{sae},Ib + (const void *)&gInstructions[ 3986] // VREDUCEPS Vfv{K}{z},aKq,Wfv|B32{sae},Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_56_pp_01_w = @@ -24350,7 +24598,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_56_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_56_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3940] // VREDUCEPH Vfv{K}{z},aKq,Wfv|B16{sae},Ib + (const void *)&gInstructions[ 3985] // VREDUCEPH Vfv{K}{z},aKq,Wfv|B16{sae},Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_56_pp_00_w = @@ -24376,13 +24624,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_56_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_55_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2910] // VFIXUPIMMSD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib + (const void *)&gInstructions[ 2951] // VFIXUPIMMSD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_55_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2911] // VFIXUPIMMSS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib + (const void *)&gInstructions[ 2952] // VFIXUPIMMSS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_55_pp_01_w = @@ -24408,13 +24656,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_55_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_54_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2908] // VFIXUPIMMPD Vfv{K}{z},aKq,Hfv,Wfv|B64{sae},Ib + (const void *)&gInstructions[ 2949] // VFIXUPIMMPD Vfv{K}{z},aKq,Hfv,Wfv|B64{sae},Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_54_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2909] // VFIXUPIMMPS Vfv{K}{z},aKq,Hfv,Wfv|B32{sae},Ib + (const void *)&gInstructions[ 2950] // VFIXUPIMMPS Vfv{K}{z},aKq,Hfv,Wfv|B32{sae},Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_54_pp_01_w = @@ -24440,13 +24688,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_54_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_53_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3210] // VMINMAXSD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib + (const void *)&gInstructions[ 3251] // VMINMAXSD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_53_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3212] // VMINMAXSS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib + (const void *)&gInstructions[ 3253] // VMINMAXSS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_53_pp_01_w = @@ -24461,7 +24709,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_53_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_53_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3211] // VMINMAXSH Vdq{K}{z},aKq,Hdq,Wsh{sae},Ib + (const void *)&gInstructions[ 3252] // VMINMAXSH Vdq{K}{z},aKq,Hdq,Wsh{sae},Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_53_pp_00_w = @@ -24487,7 +24735,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_53_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_52_pp_03_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3206] // VMINMAXNEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16,Ib + (const void *)&gInstructions[ 3247] // VMINMAXNEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_52_pp_03_w = @@ -24502,13 +24750,13 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_52_pp_03_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_52_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3207] // VMINMAXPD Vfv{K}{z},aKq,Hfv,Wfv|B64{sae},Ib + (const void *)&gInstructions[ 3248] // VMINMAXPD Vfv{K}{z},aKq,Hfv,Wfv|B64{sae},Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_52_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3209] // VMINMAXPS Vfv{K}{z},aKq,Hfv,Wfv|B32{sae},Ib + (const void *)&gInstructions[ 3250] // VMINMAXPS Vfv{K}{z},aKq,Hfv,Wfv|B32{sae},Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_52_pp_01_w = @@ -24523,7 +24771,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_52_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_52_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3208] // VMINMAXPH Vfv{K}{z},aKq,Hfv,Wfv|B16{sae},Ib + (const void *)&gInstructions[ 3249] // VMINMAXPH Vfv{K}{z},aKq,Hfv,Wfv|B16{sae},Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_52_pp_00_w = @@ -24549,13 +24797,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_52_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_51_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3923] // VRANGESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib + (const void *)&gInstructions[ 3968] // VRANGESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_51_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3924] // VRANGESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib + (const void *)&gInstructions[ 3969] // VRANGESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_51_pp_01_w = @@ -24581,13 +24829,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_51_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_50_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3921] // VRANGEPD Vfv{K}{z},aKq,Hfv,Wfv|B64{sae},Ib + (const void *)&gInstructions[ 3966] // VRANGEPD Vfv{K}{z},aKq,Hfv,Wfv|B64{sae},Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_50_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3922] // VRANGEPS Vfv{K}{z},aKq,Hfv,Wfv|B32{sae},Ib + (const void *)&gInstructions[ 3967] // VRANGEPS Vfv{K}{z},aKq,Hfv,Wfv|B32{sae},Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_50_pp_01_w = @@ -24613,7 +24861,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_50_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_44_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3433] // VPCLMULQDQ Vfv,Hfv,Wfv,Ib + (const void *)&gInstructions[ 3478] // VPCLMULQDQ Vfv,Hfv,Wfv,Ib }; const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_44_pp = @@ -24630,13 +24878,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_44_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_43_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3994] // VSHUFI64X2 Vuv{K}{z},aKq,Huv,Wuv|B64,Ib + (const void *)&gInstructions[ 4039] // VSHUFI64X2 Vuv{K}{z},aKq,Huv,Wuv|B64,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_43_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3993] // VSHUFI32X4 Vuv{K}{z},aKq,Huv,Wuv|B32,Ib + (const void *)&gInstructions[ 4038] // VSHUFI32X4 Vuv{K}{z},aKq,Huv,Wuv|B32,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_43_pp_01_w = @@ -24662,7 +24910,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_43_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_42_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3339] // VMPSADBW Vfv{K}{z},aKq,Hfv,Wfv,Ib + (const void *)&gInstructions[ 3384] // VMPSADBW Vfv{K}{z},aKq,Hfv,Wfv,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_42_pp_02_w = @@ -24677,7 +24925,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_42_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_42_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2868] // VDBPSADBW Vfv{K}{z},aKq,Hfv,Wfv,Ib + (const void *)&gInstructions[ 2909] // VDBPSADBW Vfv{K}{z},aKq,Hfv,Wfv,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_42_pp_01_w = @@ -24703,13 +24951,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_42_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_3f_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3464] // VPCMPW rKq{K},aKq,Hfv,Wfv,Ib + (const void *)&gInstructions[ 3509] // VPCMPW rKq{K},aKq,Hfv,Wfv,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_3f_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3437] // VPCMPB rKq{K},aKq,Hfv,Wfv,Ib + (const void *)&gInstructions[ 3482] // VPCMPB rKq{K},aKq,Hfv,Wfv,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_3f_pp_01_w = @@ -24735,13 +24983,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_3f_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_3e_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3463] // VPCMPUW rKq{K},aKq,Hfv,Wfv,Ib + (const void *)&gInstructions[ 3508] // VPCMPUW rKq{K},aKq,Hfv,Wfv,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_3e_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3460] // VPCMPUB rKq{K},aKq,Hfv,Wfv,Ib + (const void *)&gInstructions[ 3505] // VPCMPUB rKq{K},aKq,Hfv,Wfv,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_3e_pp_01_w = @@ -24767,13 +25015,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_3e_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_3b_pp_01_l_02_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2899] // VEXTRACTI64X4 Wqq{K}{z},aKq,Voq,Ib + (const void *)&gInstructions[ 2940] // VEXTRACTI64X4 Wqq{K}{z},aKq,Voq,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_3b_pp_01_l_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2897] // VEXTRACTI32X8 Wqq{K}{z},aKq,Voq,Ib + (const void *)&gInstructions[ 2938] // VEXTRACTI32X8 Wqq{K}{z},aKq,Voq,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_3b_pp_01_l_02_w = @@ -24810,13 +25058,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_3b_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_3a_pp_01_l_02_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3178] // VINSERTI64X4 Voq{K}{z},aKq,Hoq,Wqq,Ib + (const void *)&gInstructions[ 3219] // VINSERTI64X4 Voq{K}{z},aKq,Hoq,Wqq,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_3a_pp_01_l_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3176] // VINSERTI32X8 Voq{K}{z},aKq,Hoq,Wqq,Ib + (const void *)&gInstructions[ 3217] // VINSERTI32X8 Voq{K}{z},aKq,Hoq,Wqq,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_3a_pp_01_l_02_w = @@ -24853,13 +25101,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_3a_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_39_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2898] // VEXTRACTI64X2 Wdq{K}{z},aKq,Vuv,Ib + (const void *)&gInstructions[ 2939] // VEXTRACTI64X2 Wdq{K}{z},aKq,Vuv,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_39_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2896] // VEXTRACTI32X4 Wdq{K}{z},aKq,Vuv,Ib + (const void *)&gInstructions[ 2937] // VEXTRACTI32X4 Wdq{K}{z},aKq,Vuv,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_39_pp_01_w = @@ -24885,13 +25133,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_39_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_38_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3177] // VINSERTI64X2 Vuv{K}{z},aKq,Huv,Wdq,Ib + (const void *)&gInstructions[ 3218] // VINSERTI64X2 Vuv{K}{z},aKq,Huv,Wdq,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_38_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3175] // VINSERTI32X4 Vuv{K}{z},aKq,Huv,Wdq,Ib + (const void *)&gInstructions[ 3216] // VINSERTI32X4 Vuv{K}{z},aKq,Huv,Wdq,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_38_pp_01_w = @@ -24917,13 +25165,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_38_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_27_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3156] // VGETMANTSD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib + (const void *)&gInstructions[ 3197] // VGETMANTSD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_27_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3158] // VGETMANTSS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib + (const void *)&gInstructions[ 3199] // VGETMANTSS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_27_pp_01_w = @@ -24938,7 +25186,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_27_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_27_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3157] // VGETMANTSH Vdq{K}{z},aKq,Hdq,Wsh{sae},Ib + (const void *)&gInstructions[ 3198] // VGETMANTSH Vdq{K}{z},aKq,Hdq,Wsh{sae},Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_27_pp_00_w = @@ -24964,7 +25212,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_27_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_26_pp_03_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3152] // VGETMANTPBF16 Vfv{K}{z},aKq,Wfv|B16,Ib + (const void *)&gInstructions[ 3193] // VGETMANTPBF16 Vfv{K}{z},aKq,Wfv|B16,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_26_pp_03_w = @@ -24979,13 +25227,13 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_26_pp_03_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_26_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3153] // VGETMANTPD Vfv{K}{z},aKq,Wfv|B64{sae},Ib + (const void *)&gInstructions[ 3194] // VGETMANTPD Vfv{K}{z},aKq,Wfv|B64{sae},Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_26_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3155] // VGETMANTPS Vfv{K}{z},aKq,Wfv|B32{sae},Ib + (const void *)&gInstructions[ 3196] // VGETMANTPS Vfv{K}{z},aKq,Wfv|B32{sae},Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_26_pp_01_w = @@ -25000,7 +25248,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_26_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_26_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3154] // VGETMANTPH Vfv{K}{z},aKq,Wfv|B16{sae},Ib + (const void *)&gInstructions[ 3195] // VGETMANTPH Vfv{K}{z},aKq,Wfv|B16{sae},Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_26_pp_00_w = @@ -25026,13 +25274,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_26_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_25_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3892] // VPTERNLOGQ Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib + (const void *)&gInstructions[ 3937] // VPTERNLOGQ Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_25_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3891] // VPTERNLOGD Vfv{K}{z},aKq,Hfv,Wfv|B32,Ib + (const void *)&gInstructions[ 3936] // VPTERNLOGD Vfv{K}{z},aKq,Hfv,Wfv|B32,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_25_pp_01_w = @@ -25058,13 +25306,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_25_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_23_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3992] // VSHUFF64X2 Vuv{K}{z},aKq,Huv,Wuv|B64,Ib + (const void *)&gInstructions[ 4037] // VSHUFF64X2 Vuv{K}{z},aKq,Huv,Wuv|B64,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_23_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3991] // VSHUFF32X4 Vuv{K}{z},aKq,Huv,Wuv|B32,Ib + (const void *)&gInstructions[ 4036] // VSHUFF32X4 Vuv{K}{z},aKq,Huv,Wuv|B32,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_23_pp_01_w = @@ -25090,13 +25338,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_23_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_22_pp_01_l_00_wi_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3609] // VPINSRQ Vdq,Hdq,Eq,Ib + (const void *)&gInstructions[ 3654] // VPINSRQ Vdq,Hdq,Eq,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_22_pp_01_l_00_wi_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3607] // VPINSRD Vdq,Hdq,Ed,Ib + (const void *)&gInstructions[ 3652] // VPINSRD Vdq,Hdq,Ed,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_22_pp_01_l_00_wi = @@ -25133,7 +25381,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_22_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_21_pp_01_modrmmod_01_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3180] // VINSERTPS Vdq,Hdq,Udq,Ib + (const void *)&gInstructions[ 3221] // VINSERTPS Vdq,Hdq,Udq,Ib }; const ND_TABLE_EX_L gEvexMap_mmmmm_03_opcode_21_pp_01_modrmmod_01_l = @@ -25150,7 +25398,7 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_03_opcode_21_pp_01_modrmmod_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_21_pp_01_modrmmod_00_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3179] // VINSERTPS Vdq,Hdq,Md,Ib + (const void *)&gInstructions[ 3220] // VINSERTPS Vdq,Hdq,Md,Ib }; const ND_TABLE_EX_L gEvexMap_mmmmm_03_opcode_21_pp_01_modrmmod_00_l = @@ -25187,7 +25435,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_21_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_20_pp_01_modrmmod_01_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3604] // VPINSRB Vdq,Hdq,Rd,Ib + (const void *)&gInstructions[ 3649] // VPINSRB Vdq,Hdq,Rd,Ib }; const ND_TABLE_EX_L gEvexMap_mmmmm_03_opcode_20_pp_01_modrmmod_01_l = @@ -25204,7 +25452,7 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_03_opcode_20_pp_01_modrmmod_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_20_pp_01_modrmmod_00_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3603] // VPINSRB Vdq,Hdq,Mb,Ib + (const void *)&gInstructions[ 3648] // VPINSRB Vdq,Hdq,Mb,Ib }; const ND_TABLE_EX_L gEvexMap_mmmmm_03_opcode_20_pp_01_modrmmod_00_l = @@ -25241,13 +25489,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_20_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_1f_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3459] // VPCMPQ rKq{K},aKq,Hfv,Wfv|B64,Ib + (const void *)&gInstructions[ 3504] // VPCMPQ rKq{K},aKq,Hfv,Wfv|B64,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_1f_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3438] // VPCMPD rKq{K},aKq,Hfv,Wfv|B32,Ib + (const void *)&gInstructions[ 3483] // VPCMPD rKq{K},aKq,Hfv,Wfv|B32,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_1f_pp_01_w = @@ -25273,13 +25521,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_1f_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_1e_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3462] // VPCMPUQ rKq{K},aKq,Hfv,Wfv|B64,Ib + (const void *)&gInstructions[ 3507] // VPCMPUQ rKq{K},aKq,Hfv,Wfv|B64,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_1e_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3461] // VPCMPUD rKq{K},aKq,Hfv,Wfv|B32,Ib + (const void *)&gInstructions[ 3506] // VPCMPUD rKq{K},aKq,Hfv,Wfv|B32,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_1e_pp_01_w = @@ -25305,7 +25553,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_1e_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_1d_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2782] // VCVTPS2PH Whv{K}{z},aKq,Vfv{sae},Ib + (const void *)&gInstructions[ 2823] // VCVTPS2PH Whv{K}{z},aKq,Vfv{sae},Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_1d_pp_01_w = @@ -25331,13 +25579,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_1d_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_1b_pp_01_l_02_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2894] // VEXTRACTF64X4 Wqq{K}{z},aKq,Voq,Ib + (const void *)&gInstructions[ 2935] // VEXTRACTF64X4 Wqq{K}{z},aKq,Voq,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_1b_pp_01_l_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2892] // VEXTRACTF32X8 Wqq{K}{z},aKq,Voq,Ib + (const void *)&gInstructions[ 2933] // VEXTRACTF32X8 Wqq{K}{z},aKq,Voq,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_1b_pp_01_l_02_w = @@ -25374,13 +25622,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_1b_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_1a_pp_01_l_02_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3173] // VINSERTF64X4 Voq{K}{z},aKq,Hoq,Wqq,Ib + (const void *)&gInstructions[ 3214] // VINSERTF64X4 Voq{K}{z},aKq,Hoq,Wqq,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_1a_pp_01_l_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3171] // VINSERTF32X8 Voq{K}{z},aKq,Hoq,Wqq,Ib + (const void *)&gInstructions[ 3212] // VINSERTF32X8 Voq{K}{z},aKq,Hoq,Wqq,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_1a_pp_01_l_02_w = @@ -25417,13 +25665,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_1a_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_19_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2893] // VEXTRACTF64X2 Wdq{K}{z},aKq,Vuv,Ib + (const void *)&gInstructions[ 2934] // VEXTRACTF64X2 Wdq{K}{z},aKq,Vuv,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_19_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2891] // VEXTRACTF32X4 Wdq{K}{z},aKq,Vuv,Ib + (const void *)&gInstructions[ 2932] // VEXTRACTF32X4 Wdq{K}{z},aKq,Vuv,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_19_pp_01_w = @@ -25449,13 +25697,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_19_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_18_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3172] // VINSERTF64X2 Vuv{K}{z},aKq,Huv,Wdq,Ib + (const void *)&gInstructions[ 3213] // VINSERTF64X2 Vuv{K}{z},aKq,Huv,Wdq,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_18_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3170] // VINSERTF32X4 Vuv{K}{z},aKq,Huv,Wdq,Ib + (const void *)&gInstructions[ 3211] // VINSERTF32X4 Vuv{K}{z},aKq,Huv,Wdq,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_18_pp_01_w = @@ -25481,7 +25729,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_18_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_17_pp_01_modrmmod_01_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2901] // VEXTRACTPS Ry,Vdq,Ib + (const void *)&gInstructions[ 2942] // VEXTRACTPS Ry,Vdq,Ib }; const ND_TABLE_EX_L gEvexMap_mmmmm_03_opcode_17_pp_01_modrmmod_01_l = @@ -25498,7 +25746,7 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_03_opcode_17_pp_01_modrmmod_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_17_pp_01_modrmmod_00_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2900] // VEXTRACTPS Md,Vdq,Ib + (const void *)&gInstructions[ 2941] // VEXTRACTPS Md,Vdq,Ib }; const ND_TABLE_EX_L gEvexMap_mmmmm_03_opcode_17_pp_01_modrmmod_00_l = @@ -25535,13 +25783,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_17_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_16_pp_01_modrmmod_01_l_00_wi_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3564] // VPEXTRQ Ry,Vdq,Ib + (const void *)&gInstructions[ 3609] // VPEXTRQ Ry,Vdq,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_16_pp_01_modrmmod_01_l_00_wi_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3560] // VPEXTRD Ry,Vdq,Ib + (const void *)&gInstructions[ 3605] // VPEXTRD Ry,Vdq,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_16_pp_01_modrmmod_01_l_00_wi = @@ -25567,13 +25815,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_03_opcode_16_pp_01_modrmmod_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_16_pp_01_modrmmod_00_l_00_wi_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3563] // VPEXTRQ Mq,Vdq,Ib + (const void *)&gInstructions[ 3608] // VPEXTRQ Mq,Vdq,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_16_pp_01_modrmmod_00_l_00_wi_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3559] // VPEXTRD Md,Vdq,Ib + (const void *)&gInstructions[ 3604] // VPEXTRD Md,Vdq,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_16_pp_01_modrmmod_00_l_00_wi = @@ -25619,7 +25867,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_16_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_15_pp_01_modrmmod_01_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3569] // VPEXTRW Ry,Vdq,Ib + (const void *)&gInstructions[ 3614] // VPEXTRW Ry,Vdq,Ib }; const ND_TABLE_EX_L gEvexMap_mmmmm_03_opcode_15_pp_01_modrmmod_01_l = @@ -25636,7 +25884,7 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_03_opcode_15_pp_01_modrmmod_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_15_pp_01_modrmmod_00_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3568] // VPEXTRW Mw,Vdq,Ib + (const void *)&gInstructions[ 3613] // VPEXTRW Mw,Vdq,Ib }; const ND_TABLE_EX_L gEvexMap_mmmmm_03_opcode_15_pp_01_modrmmod_00_l = @@ -25673,7 +25921,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_15_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_14_pp_01_modrmmod_01_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3556] // VPEXTRB Ry,Vdq,Ib + (const void *)&gInstructions[ 3601] // VPEXTRB Ry,Vdq,Ib }; const ND_TABLE_EX_L gEvexMap_mmmmm_03_opcode_14_pp_01_modrmmod_01_l = @@ -25690,7 +25938,7 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_03_opcode_14_pp_01_modrmmod_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_14_pp_01_modrmmod_00_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3555] // VPEXTRB Mb,Vdq,Ib + (const void *)&gInstructions[ 3600] // VPEXTRB Mb,Vdq,Ib }; const ND_TABLE_EX_L gEvexMap_mmmmm_03_opcode_14_pp_01_modrmmod_00_l = @@ -25727,7 +25975,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_14_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_0f_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3400] // VPALIGNR Vfv{K}{z},aKq,Hfv,Wfv,Ib + (const void *)&gInstructions[ 3445] // VPALIGNR Vfv{K}{z},aKq,Hfv,Wfv,Ib }; const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_0f_pp = @@ -25744,7 +25992,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_0f_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_0b_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3949] // VRNDSCALESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib + (const void *)&gInstructions[ 3994] // VRNDSCALESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_0b_pp_01_w = @@ -25770,7 +26018,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_0b_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_0a_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3951] // VRNDSCALESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib + (const void *)&gInstructions[ 3996] // VRNDSCALESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_0a_pp_01_w = @@ -25785,7 +26033,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_0a_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_0a_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3950] // VRNDSCALESH Vdq{K}{z},aKq,Hdq,Wsh{sae},Ib + (const void *)&gInstructions[ 3995] // VRNDSCALESH Vdq{K}{z},aKq,Hdq,Wsh{sae},Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_0a_pp_00_w = @@ -25811,7 +26059,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_0a_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_09_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3946] // VRNDSCALEPD Vfv{K}{z},aKq,Wfv|B64{sae},Ib + (const void *)&gInstructions[ 3991] // VRNDSCALEPD Vfv{K}{z},aKq,Wfv|B64{sae},Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_09_pp_01_w = @@ -25837,7 +26085,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_09_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_08_pp_03_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3945] // VRNDSCALENEPBF16 Vfv{K}{z},aKq,Wfv|B16,Ib + (const void *)&gInstructions[ 3990] // VRNDSCALENEPBF16 Vfv{K}{z},aKq,Wfv|B16,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_08_pp_03_w = @@ -25852,7 +26100,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_08_pp_03_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_08_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3948] // VRNDSCALEPS Vfv{K}{z},aKq,Wfv|B32{sae},Ib + (const void *)&gInstructions[ 3993] // VRNDSCALEPS Vfv{K}{z},aKq,Wfv|B32{sae},Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_08_pp_01_w = @@ -25867,7 +26115,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_08_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_08_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3947] // VRNDSCALEPH Vfv{K}{z},aKq,Wfv|B16{sae},Ib + (const void *)&gInstructions[ 3992] // VRNDSCALEPH Vfv{K}{z},aKq,Wfv|B16{sae},Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_08_pp_00_w = @@ -25890,10 +26138,161 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_08_pp = } }; +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_07_pp_03_modrmmod_01_l_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2608] // TCVTROWPS2PBF16H Voq,mTt,Ib +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_07_pp_03_modrmmod_01_l_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_07_pp_03_modrmmod_01_l_02_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_03_opcode_07_pp_03_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gEvexMap_mmmmm_03_opcode_07_pp_03_modrmmod_01_l_02_w, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_03_opcode_07_pp_03_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_07_pp_03_modrmmod_01_l, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_07_pp_02_modrmmod_01_l_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2606] // TCVTROWD2PS Voq,mTt,Ib +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_07_pp_02_modrmmod_01_l_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_07_pp_02_modrmmod_01_l_02_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_03_opcode_07_pp_02_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gEvexMap_mmmmm_03_opcode_07_pp_02_modrmmod_01_l_02_w, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_03_opcode_07_pp_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_07_pp_02_modrmmod_01_l, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_07_pp_01_modrmmod_01_l_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2642] // TILEMOVROW Voq,mTt,Ib +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_07_pp_01_modrmmod_01_l_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_07_pp_01_modrmmod_01_l_02_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_03_opcode_07_pp_01_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gEvexMap_mmmmm_03_opcode_07_pp_01_modrmmod_01_l_02_w, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_03_opcode_07_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_07_pp_01_modrmmod_01_l, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_07_pp_00_modrmmod_01_l_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2612] // TCVTROWPS2PHH Voq,mTt,Ib +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_07_pp_00_modrmmod_01_l_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_07_pp_00_modrmmod_01_l_02_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_03_opcode_07_pp_00_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gEvexMap_mmmmm_03_opcode_07_pp_00_modrmmod_01_l_02_w, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_03_opcode_07_pp_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_07_pp_00_modrmmod_01_l, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_07_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_07_pp_00_modrmmod, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_07_pp_01_modrmmod, + /* 02 */ (const void *)&gEvexMap_mmmmm_03_opcode_07_pp_02_modrmmod, + /* 03 */ (const void *)&gEvexMap_mmmmm_03_opcode_07_pp_03_modrmmod, + } +}; + const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_05_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3527] // VPERMILPD Vfv{K}{z},aKq,Wfv|B64,Ib + (const void *)&gInstructions[ 3572] // VPERMILPD Vfv{K}{z},aKq,Wfv|B64,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_05_pp_01_w = @@ -25919,7 +26318,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_05_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_04_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3531] // VPERMILPS Vfv{K}{z},aKq,Wfv|B32,Ib + (const void *)&gInstructions[ 3576] // VPERMILPS Vfv{K}{z},aKq,Wfv|B32,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_04_pp_01_w = @@ -25945,13 +26344,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_04_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_03_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2669] // VALIGNQ Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib + (const void *)&gInstructions[ 2710] // VALIGNQ Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_03_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2668] // VALIGND Vfv{K}{z},aKq,Hfv,Wfv|B32,Ib + (const void *)&gInstructions[ 2709] // VALIGND Vfv{K}{z},aKq,Hfv,Wfv|B32,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_03_pp_01_w = @@ -25977,7 +26376,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_03_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_01_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3536] // VPERMPD Vuv{K}{z},aKq,Wuv|B64,Ib + (const void *)&gInstructions[ 3581] // VPERMPD Vuv{K}{z},aKq,Wuv|B64,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_01_pp_01_w = @@ -26003,7 +26402,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_01_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_00_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3542] // VPERMQ Vuv{K}{z},aKq,Wuv|B64,Ib + (const void *)&gInstructions[ 3587] // VPERMQ Vuv{K}{z},aKq,Wuv|B64,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_00_pp_01_w = @@ -26037,7 +26436,7 @@ const ND_TABLE_OPCODE gEvexMap_mmmmm_03_opcode = /* 04 */ (const void *)&gEvexMap_mmmmm_03_opcode_04_pp, /* 05 */ (const void *)&gEvexMap_mmmmm_03_opcode_05_pp, /* 06 */ (const void *)ND_NULL, - /* 07 */ (const void *)ND_NULL, + /* 07 */ (const void *)&gEvexMap_mmmmm_03_opcode_07_pp, /* 08 */ (const void *)&gEvexMap_mmmmm_03_opcode_08_pp, /* 09 */ (const void *)&gEvexMap_mmmmm_03_opcode_09_pp, /* 0a */ (const void *)&gEvexMap_mmmmm_03_opcode_0a_pp, @@ -26149,7 +26548,7 @@ const ND_TABLE_OPCODE gEvexMap_mmmmm_03_opcode = /* 74 */ (const void *)ND_NULL, /* 75 */ (const void *)ND_NULL, /* 76 */ (const void *)ND_NULL, - /* 77 */ (const void *)ND_NULL, + /* 77 */ (const void *)&gEvexMap_mmmmm_03_opcode_77_pp, /* 78 */ (const void *)ND_NULL, /* 79 */ (const void *)ND_NULL, /* 7a */ (const void *)ND_NULL, @@ -26292,7 +26691,7 @@ const ND_TABLE_OPCODE gEvexMap_mmmmm_03_opcode = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_f7_pp_03_l_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2488] // SHRX Gy,Ey,By + (const void *)&gInstructions[ 2494] // SHRX Gy,Ey,By }; const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_f7_pp_03_l_00_nf = @@ -26318,7 +26717,7 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_f7_pp_03_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_f7_pp_02_l_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2276] // SARX Gy,Ey,By + (const void *)&gInstructions[ 2282] // SARX Gy,Ey,By }; const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_f7_pp_02_l_00_nf = @@ -26344,7 +26743,7 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_f7_pp_02_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_f7_pp_01_l_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2426] // SHLX Gy,Ey,By + (const void *)&gInstructions[ 2432] // SHLX Gy,Ey,By }; const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_f7_pp_01_l_00_nf = @@ -26413,7 +26812,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_f7_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_f6_pp_03_l_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1483] // MULX Gy,By,Ey + (const void *)&gInstructions[ 1485] // MULX Gy,By,Ey }; const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_f6_pp_03_l_00_nf = @@ -26450,7 +26849,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_f6_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_f5_pp_03_l_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1710] // PDEP Gy,By,Ey + (const void *)&gInstructions[ 1712] // PDEP Gy,By,Ey }; const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_f5_pp_03_l_00_nf = @@ -26476,7 +26875,7 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_f5_pp_03_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_f5_pp_02_l_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1712] // PEXT Gy,By,Ey + (const void *)&gInstructions[ 1714] // PEXT Gy,By,Ey }; const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_f5_pp_02_l_00_nf = @@ -27446,7 +27845,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_e0_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_df_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2660] // VAESDECLAST Vfv,Hfv,Wfv + (const void *)&gInstructions[ 2701] // VAESDECLAST Vfv,Hfv,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_df_pp = @@ -27463,7 +27862,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_df_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_de_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2658] // VAESDEC Vfv,Hfv,Wfv + (const void *)&gInstructions[ 2699] // VAESDEC Vfv,Hfv,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_de_pp = @@ -27480,7 +27879,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_de_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_dd_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2664] // VAESENCLAST Vfv,Hfv,Wfv + (const void *)&gInstructions[ 2705] // VAESENCLAST Vfv,Hfv,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_dd_pp = @@ -27497,7 +27896,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_dd_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_dc_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2662] // VAESENC Vfv,Hfv,Wfv + (const void *)&gInstructions[ 2703] // VAESENC Vfv,Hfv,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_dc_pp = @@ -27511,10 +27910,51 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_dc_pp = } }; +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_da_pp_03_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 4049] // VSM4RNDS4 Vfv,Hfv,Wfv +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_da_pp_03_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_da_pp_03_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_da_pp_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 4047] // VSM4KEY4 Vfv,Hfv,Wfv +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_da_pp_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_da_pp_02_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_da_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_da_pp_02_w, + /* 03 */ (const void *)&gEvexMap_mmmmm_02_opcode_da_pp_03_w, + } +}; + const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_d3_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3501] // VPDPWSUDS Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 3546] // VPDPWSUDS Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_d3_pp_02_w = @@ -27529,7 +27969,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_d3_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_d3_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3505] // VPDPWUSDS Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 3550] // VPDPWUSDS Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_d3_pp_01_w = @@ -27544,7 +27984,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_d3_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_d3_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3509] // VPDPWUUDS Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 3554] // VPDPWUUDS Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_d3_pp_00_w = @@ -27570,7 +28010,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_d3_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_d2_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3499] // VPDPWSUD Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 3544] // VPDPWSUD Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_d2_pp_02_w = @@ -27585,7 +28025,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_d2_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_d2_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3503] // VPDPWUSD Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 3548] // VPDPWUSD Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_d2_pp_01_w = @@ -27600,7 +28040,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_d2_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_d2_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3507] // VPDPWUUD Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 3552] // VPDPWUUD Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_d2_pp_00_w = @@ -27626,7 +28066,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_d2_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_cf_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3163] // VGF2P8MULB Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3204] // VGF2P8MULB Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_cf_pp_01_w = @@ -27652,13 +28092,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_cf_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_cd_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3962] // VRSQRT28SD Vdq{K}{z},aKq,Hdq,Wsd{sae} + (const void *)&gInstructions[ 4007] // VRSQRT28SD Vdq{K}{z},aKq,Hdq,Wsd{sae} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_cd_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3963] // VRSQRT28SS Vdq{K}{z},aKq,Hdq,Wss{sae} + (const void *)&gInstructions[ 4008] // VRSQRT28SS Vdq{K}{z},aKq,Hdq,Wss{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_cd_pp_01_w = @@ -27684,13 +28124,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_cd_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_cc_pp_01_l_02_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3960] // VRSQRT28PD Voq{K}{z},aKq,Woq|B64{sae} + (const void *)&gInstructions[ 4005] // VRSQRT28PD Voq{K}{z},aKq,Woq|B64{sae} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_cc_pp_01_l_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3961] // VRSQRT28PS Voq{K}{z},aKq,Woq|B32{sae} + (const void *)&gInstructions[ 4006] // VRSQRT28PS Voq{K}{z},aKq,Woq|B32{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_cc_pp_01_l_02_w = @@ -27727,13 +28167,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_cc_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_cb_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3931] // VRCP28SD Vdq{K}{z},aKq,Hdq,Wsd{sae} + (const void *)&gInstructions[ 3976] // VRCP28SD Vdq{K}{z},aKq,Hdq,Wsd{sae} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_cb_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3932] // VRCP28SS Vdq{K}{z},aKq,Hdq,Wss{sae} + (const void *)&gInstructions[ 3977] // VRCP28SS Vdq{K}{z},aKq,Hdq,Wss{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_cb_pp_01_w = @@ -27759,13 +28199,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_cb_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_ca_pp_01_l_02_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3929] // VRCP28PD Voq{K}{z},aKq,Woq|B64{sae} + (const void *)&gInstructions[ 3974] // VRCP28PD Voq{K}{z},aKq,Woq|B64{sae} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_ca_pp_01_l_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3930] // VRCP28PS Voq{K}{z},aKq,Woq|B32{sae} + (const void *)&gInstructions[ 3975] // VRCP28PS Voq{K}{z},aKq,Woq|B32{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_ca_pp_01_l_02_w = @@ -27802,13 +28242,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_ca_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_c8_pp_01_l_02_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2886] // VEXP2PD Voq{K}{z},aKq,Woq|B64{sae} + (const void *)&gInstructions[ 2927] // VEXP2PD Voq{K}{z},aKq,Woq|B64{sae} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_c8_pp_01_l_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2887] // VEXP2PS Voq{K}{z},aKq,Woq|B32{sae} + (const void *)&gInstructions[ 2928] // VEXP2PS Voq{K}{z},aKq,Woq|B32{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_c8_pp_01_l_02_w = @@ -27845,13 +28285,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_c8_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_06_modrmmod_00_l_02_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3984] // VSCATTERPF1QPD Mvm64n{K},aKq + (const void *)&gInstructions[ 4029] // VSCATTERPF1QPD Mvm64n{K},aKq }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_06_modrmmod_00_l_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3985] // VSCATTERPF1QPS Mvm64n{K},aKq + (const void *)&gInstructions[ 4030] // VSCATTERPF1QPS Mvm64n{K},aKq }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_06_modrmmod_00_l_02_w = @@ -27886,13 +28326,13 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_06_modrmmod const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_05_modrmmod_00_l_02_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3980] // VSCATTERPF0QPD Mvm64n{K},aKq + (const void *)&gInstructions[ 4025] // VSCATTERPF0QPD Mvm64n{K},aKq }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_05_modrmmod_00_l_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3981] // VSCATTERPF0QPS Mvm64n{K},aKq + (const void *)&gInstructions[ 4026] // VSCATTERPF0QPS Mvm64n{K},aKq }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_05_modrmmod_00_l_02_w = @@ -27927,13 +28367,13 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_05_modrmmod const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_02_modrmmod_00_l_02_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3139] // VGATHERPF1QPD Mvm64n{K},aKq + (const void *)&gInstructions[ 3180] // VGATHERPF1QPD Mvm64n{K},aKq }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_02_modrmmod_00_l_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3140] // VGATHERPF1QPS Mvm64n{K},aKq + (const void *)&gInstructions[ 3181] // VGATHERPF1QPS Mvm64n{K},aKq }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_02_modrmmod_00_l_02_w = @@ -27968,13 +28408,13 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_02_modrmmod const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_01_modrmmod_00_l_02_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3135] // VGATHERPF0QPD Mvm64n{K},aKq + (const void *)&gInstructions[ 3176] // VGATHERPF0QPD Mvm64n{K},aKq }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_01_modrmmod_00_l_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3136] // VGATHERPF0QPS Mvm64n{K},aKq + (const void *)&gInstructions[ 3177] // VGATHERPF0QPS Mvm64n{K},aKq }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_01_modrmmod_00_l_02_w = @@ -28035,13 +28475,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_c7_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_06_modrmmod_00_l_02_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3982] // VSCATTERPF1DPD Mvm32h{K},aKq + (const void *)&gInstructions[ 4027] // VSCATTERPF1DPD Mvm32h{K},aKq }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_06_modrmmod_00_l_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3983] // VSCATTERPF1DPS Mvm32n{K},aKq + (const void *)&gInstructions[ 4028] // VSCATTERPF1DPS Mvm32n{K},aKq }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_06_modrmmod_00_l_02_w = @@ -28076,13 +28516,13 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_06_modrmmod const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_05_modrmmod_00_l_02_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3978] // VSCATTERPF0DPD Mvm32h{K},aKq + (const void *)&gInstructions[ 4023] // VSCATTERPF0DPD Mvm32h{K},aKq }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_05_modrmmod_00_l_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3979] // VSCATTERPF0DPS Mvm32n{K},aKq + (const void *)&gInstructions[ 4024] // VSCATTERPF0DPS Mvm32n{K},aKq }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_05_modrmmod_00_l_02_w = @@ -28117,13 +28557,13 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_05_modrmmod const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_02_modrmmod_00_l_02_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3137] // VGATHERPF1DPD Mvm32h{K},aKq + (const void *)&gInstructions[ 3178] // VGATHERPF1DPD Mvm32h{K},aKq }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_02_modrmmod_00_l_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3138] // VGATHERPF1DPS Mvm32n{K},aKq + (const void *)&gInstructions[ 3179] // VGATHERPF1DPS Mvm32n{K},aKq }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_02_modrmmod_00_l_02_w = @@ -28158,13 +28598,13 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_02_modrmmod const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_01_modrmmod_00_l_02_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3133] // VGATHERPF0DPD Mvm32h{K},aKq + (const void *)&gInstructions[ 3174] // VGATHERPF0DPD Mvm32h{K},aKq }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_01_modrmmod_00_l_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3134] // VGATHERPF0DPS Mvm32n{K},aKq + (const void *)&gInstructions[ 3175] // VGATHERPF0DPS Mvm32n{K},aKq }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_01_modrmmod_00_l_02_w = @@ -28225,13 +28665,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_c6_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_c4_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3478] // VPCONFLICTQ Vfv{K}{z},aKq,Wfv|B64 + (const void *)&gInstructions[ 3523] // VPCONFLICTQ Vfv{K}{z},aKq,Wfv|B64 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_c4_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3477] // VPCONFLICTD Vfv{K}{z},aKq,Wfv|B32 + (const void *)&gInstructions[ 3522] // VPCONFLICTD Vfv{K}{z},aKq,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_c4_pp_01_w = @@ -28257,13 +28697,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_c4_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_bf_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3105] // VFNMSUB231SD Vdq{K}{z},aKq,Hdq,Wsd{er} + (const void *)&gInstructions[ 3146] // VFNMSUB231SD Vdq{K}{z},aKq,Hdq,Wsd{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_bf_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3108] // VFNMSUB231SS Vdq{K}{z},aKq,Hdq,Wss{er} + (const void *)&gInstructions[ 3149] // VFNMSUB231SS Vdq{K}{z},aKq,Hdq,Wss{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_bf_pp_01_w = @@ -28289,13 +28729,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_bf_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_be_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3100] // VFNMSUB231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} + (const void *)&gInstructions[ 3141] // VFNMSUB231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_be_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3103] // VFNMSUB231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} + (const void *)&gInstructions[ 3144] // VFNMSUB231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_be_pp_01_w = @@ -28321,13 +28761,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_be_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_bd_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3064] // VFNMADD231SD Vdq{K}{z},aKq,Hdq,Wsd{er} + (const void *)&gInstructions[ 3105] // VFNMADD231SD Vdq{K}{z},aKq,Hdq,Wsd{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_bd_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3067] // VFNMADD231SS Vdq{K}{z},aKq,Hdq,Wss{er} + (const void *)&gInstructions[ 3108] // VFNMADD231SS Vdq{K}{z},aKq,Hdq,Wss{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_bd_pp_01_w = @@ -28353,13 +28793,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_bd_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_bc_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3059] // VFNMADD231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} + (const void *)&gInstructions[ 3100] // VFNMADD231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_bc_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3062] // VFNMADD231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} + (const void *)&gInstructions[ 3103] // VFNMADD231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_bc_pp_01_w = @@ -28385,13 +28825,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_bc_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_bb_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3002] // VFMSUB231SD Vdq{K}{z},aKq,Hdq,Wsd{er} + (const void *)&gInstructions[ 3043] // VFMSUB231SD Vdq{K}{z},aKq,Hdq,Wsd{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_bb_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3005] // VFMSUB231SS Vdq{K}{z},aKq,Hdq,Wss{er} + (const void *)&gInstructions[ 3046] // VFMSUB231SS Vdq{K}{z},aKq,Hdq,Wss{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_bb_pp_01_w = @@ -28417,13 +28857,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_bb_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_ba_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2997] // VFMSUB231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} + (const void *)&gInstructions[ 3038] // VFMSUB231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_ba_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3000] // VFMSUB231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} + (const void *)&gInstructions[ 3041] // VFMSUB231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_ba_pp_01_w = @@ -28449,13 +28889,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_ba_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_b9_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2940] // VFMADD231SD Vdq{K}{z},aKq,Hdq,Wsd{er} + (const void *)&gInstructions[ 2981] // VFMADD231SD Vdq{K}{z},aKq,Hdq,Wsd{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_b9_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2943] // VFMADD231SS Vdq{K}{z},aKq,Hdq,Wss{er} + (const void *)&gInstructions[ 2984] // VFMADD231SS Vdq{K}{z},aKq,Hdq,Wss{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_b9_pp_01_w = @@ -28481,13 +28921,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_b9_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_b8_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2935] // VFMADD231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} + (const void *)&gInstructions[ 2976] // VFMADD231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_b8_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2938] // VFMADD231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} + (const void *)&gInstructions[ 2979] // VFMADD231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_b8_pp_01_w = @@ -28513,13 +28953,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_b8_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_b7_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3017] // VFMSUBADD231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} + (const void *)&gInstructions[ 3058] // VFMSUBADD231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_b7_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3020] // VFMSUBADD231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} + (const void *)&gInstructions[ 3061] // VFMSUBADD231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_b7_pp_01_w = @@ -28545,13 +28985,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_b7_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_b6_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2965] // VFMADDSUB231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} + (const void *)&gInstructions[ 3006] // VFMADDSUB231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_b6_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2968] // VFMADDSUB231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} + (const void *)&gInstructions[ 3009] // VFMADDSUB231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_b6_pp_01_w = @@ -28577,7 +29017,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_b6_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_b5_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3629] // VPMADD52HUQ Vfv{K}{z},aKq,Hfv,Wfv|B64 + (const void *)&gInstructions[ 3674] // VPMADD52HUQ Vfv{K}{z},aKq,Hfv,Wfv|B64 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_b5_pp_01_w = @@ -28603,7 +29043,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_b5_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_b4_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3631] // VPMADD52LUQ Vfv{K}{z},aKq,Hfv,Wfv|B64 + (const void *)&gInstructions[ 3676] // VPMADD52LUQ Vfv{K}{z},aKq,Hfv,Wfv|B64 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_b4_pp_01_w = @@ -28629,13 +29069,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_b4_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_af_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3094] // VFNMSUB213SD Vdq{K}{z},aKq,Hdq,Wsd{er} + (const void *)&gInstructions[ 3135] // VFNMSUB213SD Vdq{K}{z},aKq,Hdq,Wsd{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_af_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3097] // VFNMSUB213SS Vdq{K}{z},aKq,Hdq,Wss{er} + (const void *)&gInstructions[ 3138] // VFNMSUB213SS Vdq{K}{z},aKq,Hdq,Wss{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_af_pp_01_w = @@ -28661,13 +29101,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_af_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_ae_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3089] // VFNMSUB213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} + (const void *)&gInstructions[ 3130] // VFNMSUB213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_ae_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3092] // VFNMSUB213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} + (const void *)&gInstructions[ 3133] // VFNMSUB213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_ae_pp_01_w = @@ -28693,13 +29133,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_ae_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_ad_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3053] // VFNMADD213SD Vdq{K}{z},aKq,Hdq,Wsd{er} + (const void *)&gInstructions[ 3094] // VFNMADD213SD Vdq{K}{z},aKq,Hdq,Wsd{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_ad_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3056] // VFNMADD213SS Vdq{K}{z},aKq,Hdq,Wss{er} + (const void *)&gInstructions[ 3097] // VFNMADD213SS Vdq{K}{z},aKq,Hdq,Wss{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_ad_pp_01_w = @@ -28725,13 +29165,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_ad_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_ac_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3048] // VFNMADD213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} + (const void *)&gInstructions[ 3089] // VFNMADD213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_ac_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3051] // VFNMADD213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} + (const void *)&gInstructions[ 3092] // VFNMADD213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_ac_pp_01_w = @@ -28757,7 +29197,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_ac_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_ab_pp_03_modrmmod_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2644] // V4FNMADDSS Vdq{K}{z},aKq,Hdq+3,Mdq + (const void *)&gInstructions[ 2685] // V4FNMADDSS Vdq{K}{z},aKq,Hdq+3,Mdq }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_ab_pp_03_modrmmod_00_w = @@ -28781,13 +29221,13 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_ab_pp_03_modrmmod = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_ab_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2991] // VFMSUB213SD Vdq{K}{z},aKq,Hdq,Wsd{er} + (const void *)&gInstructions[ 3032] // VFMSUB213SD Vdq{K}{z},aKq,Hdq,Wsd{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_ab_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2994] // VFMSUB213SS Vdq{K}{z},aKq,Hdq,Wss{er} + (const void *)&gInstructions[ 3035] // VFMSUB213SS Vdq{K}{z},aKq,Hdq,Wss{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_ab_pp_01_w = @@ -28813,7 +29253,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_ab_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_aa_pp_03_modrmmod_00_l_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2643] // V4FNMADDPS Voq{K}{z},aKq,Hoq+3,Mdq + (const void *)&gInstructions[ 2684] // V4FNMADDPS Voq{K}{z},aKq,Hoq+3,Mdq }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_aa_pp_03_modrmmod_00_l_02_w = @@ -28848,13 +29288,13 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_aa_pp_03_modrmmod = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_aa_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2986] // VFMSUB213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} + (const void *)&gInstructions[ 3027] // VFMSUB213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_aa_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2989] // VFMSUB213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} + (const void *)&gInstructions[ 3030] // VFMSUB213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_aa_pp_01_w = @@ -28880,13 +29320,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_aa_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_a9_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2929] // VFMADD213SD Vdq{K}{z},aKq,Hdq,Wsd{er} + (const void *)&gInstructions[ 2970] // VFMADD213SD Vdq{K}{z},aKq,Hdq,Wsd{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_a9_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2932] // VFMADD213SS Vdq{K}{z},aKq,Hdq,Wss{er} + (const void *)&gInstructions[ 2973] // VFMADD213SS Vdq{K}{z},aKq,Hdq,Wss{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_a9_pp_01_w = @@ -28912,13 +29352,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_a9_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_a8_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2924] // VFMADD213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} + (const void *)&gInstructions[ 2965] // VFMADD213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_a8_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2927] // VFMADD213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} + (const void *)&gInstructions[ 2968] // VFMADD213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_a8_pp_01_w = @@ -28944,13 +29384,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_a8_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_a7_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3012] // VFMSUBADD213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} + (const void *)&gInstructions[ 3053] // VFMSUBADD213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_a7_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3015] // VFMSUBADD213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} + (const void *)&gInstructions[ 3056] // VFMSUBADD213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_a7_pp_01_w = @@ -28976,13 +29416,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_a7_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_a6_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2960] // VFMADDSUB213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} + (const void *)&gInstructions[ 3001] // VFMADDSUB213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_a6_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2963] // VFMADDSUB213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} + (const void *)&gInstructions[ 3004] // VFMADDSUB213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_a6_pp_01_w = @@ -29008,13 +29448,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_a6_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_a3_pp_01_modrmmod_00_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3986] // VSCATTERQPD Mvm64n{K},aKq,Vfv + (const void *)&gInstructions[ 4031] // VSCATTERQPD Mvm64n{K},aKq,Vfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_a3_pp_01_modrmmod_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3987] // VSCATTERQPS Mvm64n{K},aKq,Vhv + (const void *)&gInstructions[ 4032] // VSCATTERQPS Mvm64n{K},aKq,Vhv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_a3_pp_01_modrmmod_00_w = @@ -29049,13 +29489,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_a3_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_a2_pp_01_modrmmod_00_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3976] // VSCATTERDPD Mvm32h{K},aKq,Vfv + (const void *)&gInstructions[ 4021] // VSCATTERDPD Mvm32h{K},aKq,Vfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_a2_pp_01_modrmmod_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3977] // VSCATTERDPS Mvm32n{K},aKq,Vfv + (const void *)&gInstructions[ 4022] // VSCATTERDPS Mvm32n{K},aKq,Vfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_a2_pp_01_modrmmod_00_w = @@ -29090,13 +29530,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_a2_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_a1_pp_01_modrmmod_00_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3782] // VPSCATTERQQ Mvm64n{K},aKq,Vfv + (const void *)&gInstructions[ 3827] // VPSCATTERQQ Mvm64n{K},aKq,Vfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_a1_pp_01_modrmmod_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3781] // VPSCATTERQD Mvm64n{K},aKq,Vhv + (const void *)&gInstructions[ 3826] // VPSCATTERQD Mvm64n{K},aKq,Vhv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_a1_pp_01_modrmmod_00_w = @@ -29131,13 +29571,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_a1_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_a0_pp_01_modrmmod_00_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3780] // VPSCATTERDQ Mvm32h{K},aKq,Vfv + (const void *)&gInstructions[ 3825] // VPSCATTERDQ Mvm32h{K},aKq,Vfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_a0_pp_01_modrmmod_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3779] // VPSCATTERDD Mvm32n{K},aKq,Vfv + (const void *)&gInstructions[ 3824] // VPSCATTERDD Mvm32n{K},aKq,Vfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_a0_pp_01_modrmmod_00_w = @@ -29172,13 +29612,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_a0_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_9f_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3083] // VFNMSUB132SD Vdq{K}{z},aKq,Hdq,Wsd{er} + (const void *)&gInstructions[ 3124] // VFNMSUB132SD Vdq{K}{z},aKq,Hdq,Wsd{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_9f_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3086] // VFNMSUB132SS Vdq{K}{z},aKq,Hdq,Wss{er} + (const void *)&gInstructions[ 3127] // VFNMSUB132SS Vdq{K}{z},aKq,Hdq,Wss{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_9f_pp_01_w = @@ -29204,13 +29644,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_9f_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_9e_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3078] // VFNMSUB132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} + (const void *)&gInstructions[ 3119] // VFNMSUB132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_9e_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3081] // VFNMSUB132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} + (const void *)&gInstructions[ 3122] // VFNMSUB132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_9e_pp_01_w = @@ -29236,13 +29676,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_9e_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_9d_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3042] // VFNMADD132SD Vdq{K}{z},aKq,Hdq,Wsd{er} + (const void *)&gInstructions[ 3083] // VFNMADD132SD Vdq{K}{z},aKq,Hdq,Wsd{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_9d_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3045] // VFNMADD132SS Vdq{K}{z},aKq,Hdq,Wss{er} + (const void *)&gInstructions[ 3086] // VFNMADD132SS Vdq{K}{z},aKq,Hdq,Wss{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_9d_pp_01_w = @@ -29268,13 +29708,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_9d_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_9c_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3037] // VFNMADD132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} + (const void *)&gInstructions[ 3078] // VFNMADD132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_9c_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3040] // VFNMADD132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} + (const void *)&gInstructions[ 3081] // VFNMADD132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_9c_pp_01_w = @@ -29300,7 +29740,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_9c_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_9b_pp_03_modrmmod_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2642] // V4FMADDSS Vdq{K}{z},aKq,Hdq+3,Mdq + (const void *)&gInstructions[ 2683] // V4FMADDSS Vdq{K}{z},aKq,Hdq+3,Mdq }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_9b_pp_03_modrmmod_00_w = @@ -29324,13 +29764,13 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_9b_pp_03_modrmmod = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_9b_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2980] // VFMSUB132SD Vdq{K}{z},aKq,Hdq,Wsd{er} + (const void *)&gInstructions[ 3021] // VFMSUB132SD Vdq{K}{z},aKq,Hdq,Wsd{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_9b_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2983] // VFMSUB132SS Vdq{K}{z},aKq,Hdq,Wss{er} + (const void *)&gInstructions[ 3024] // VFMSUB132SS Vdq{K}{z},aKq,Hdq,Wss{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_9b_pp_01_w = @@ -29356,7 +29796,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_9b_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_9a_pp_03_modrmmod_00_l_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2641] // V4FMADDPS Voq{K}{z},aKq,Hoq+3,Mdq + (const void *)&gInstructions[ 2682] // V4FMADDPS Voq{K}{z},aKq,Hoq+3,Mdq }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_9a_pp_03_modrmmod_00_l_02_w = @@ -29391,13 +29831,13 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_9a_pp_03_modrmmod = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_9a_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2975] // VFMSUB132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} + (const void *)&gInstructions[ 3016] // VFMSUB132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_9a_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2978] // VFMSUB132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} + (const void *)&gInstructions[ 3019] // VFMSUB132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_9a_pp_01_w = @@ -29423,13 +29863,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_9a_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_99_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2918] // VFMADD132SD Vdq{K}{z},aKq,Hdq,Wsd{er} + (const void *)&gInstructions[ 2959] // VFMADD132SD Vdq{K}{z},aKq,Hdq,Wsd{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_99_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2921] // VFMADD132SS Vdq{K}{z},aKq,Hdq,Wss{er} + (const void *)&gInstructions[ 2962] // VFMADD132SS Vdq{K}{z},aKq,Hdq,Wss{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_99_pp_01_w = @@ -29455,13 +29895,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_99_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_98_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2913] // VFMADD132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} + (const void *)&gInstructions[ 2954] // VFMADD132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_98_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2916] // VFMADD132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} + (const void *)&gInstructions[ 2957] // VFMADD132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_98_pp_01_w = @@ -29487,13 +29927,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_98_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_97_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3007] // VFMSUBADD132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} + (const void *)&gInstructions[ 3048] // VFMSUBADD132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_97_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3010] // VFMSUBADD132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} + (const void *)&gInstructions[ 3051] // VFMSUBADD132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_97_pp_01_w = @@ -29519,13 +29959,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_97_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_96_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2955] // VFMADDSUB132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} + (const void *)&gInstructions[ 2996] // VFMADDSUB132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_96_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2958] // VFMADDSUB132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} + (const void *)&gInstructions[ 2999] // VFMADDSUB132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_96_pp_01_w = @@ -29551,13 +29991,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_96_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_93_pp_01_modrmmod_00_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3141] // VGATHERQPD Vfv{K},aKq,Mvm64n + (const void *)&gInstructions[ 3182] // VGATHERQPD Vfv{K},aKq,Mvm64n }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_93_pp_01_modrmmod_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3143] // VGATHERQPS Vhv{K},aKq,Mvm64n + (const void *)&gInstructions[ 3184] // VGATHERQPS Vhv{K},aKq,Mvm64n }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_93_pp_01_modrmmod_00_w = @@ -29592,13 +30032,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_93_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_92_pp_01_modrmmod_00_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3129] // VGATHERDPD Vfv{K},aKq,Mvm32h + (const void *)&gInstructions[ 3170] // VGATHERDPD Vfv{K},aKq,Mvm32h }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_92_pp_01_modrmmod_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3131] // VGATHERDPS Vfv{K},aKq,Mvm32n + (const void *)&gInstructions[ 3172] // VGATHERDPS Vfv{K},aKq,Mvm32n }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_92_pp_01_modrmmod_00_w = @@ -29633,13 +30073,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_92_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_91_pp_01_modrmmod_00_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3579] // VPGATHERQQ Vfv{K},aKq,Mvm64n + (const void *)&gInstructions[ 3624] // VPGATHERQQ Vfv{K},aKq,Mvm64n }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_91_pp_01_modrmmod_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3577] // VPGATHERQD Vhv{K},aKq,Mvm64n + (const void *)&gInstructions[ 3622] // VPGATHERQD Vhv{K},aKq,Mvm64n }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_91_pp_01_modrmmod_00_w = @@ -29674,13 +30114,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_91_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_90_pp_01_modrmmod_00_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3575] // VPGATHERDQ Vfv{K},aKq,Mvm32h + (const void *)&gInstructions[ 3620] // VPGATHERDQ Vfv{K},aKq,Mvm32h }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_90_pp_01_modrmmod_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3573] // VPGATHERDD Vfv{K},aKq,Mvm32n + (const void *)&gInstructions[ 3618] // VPGATHERDD Vfv{K},aKq,Mvm32n }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_90_pp_01_modrmmod_00_w = @@ -29715,7 +30155,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_90_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_8f_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3813] // VPSHUFBITQMB rK{K},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3858] // VPSHUFBITQMB rK{K},aKq,Hfv,Wfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_8f_pp_01_w = @@ -29741,13 +30181,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_8f_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_8d_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3550] // VPERMW Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3595] // VPERMW Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_8d_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3513] // VPERMB Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3558] // VPERMB Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_8d_pp_01_w = @@ -29773,13 +30213,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_8d_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_8b_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3469] // VPCOMPRESSQ Wfv{K}{z},aKq,Vfv + (const void *)&gInstructions[ 3514] // VPCOMPRESSQ Wfv{K}{z},aKq,Vfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_8b_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3468] // VPCOMPRESSD Wfv{K}{z},aKq,Vfv + (const void *)&gInstructions[ 3513] // VPCOMPRESSD Wfv{K}{z},aKq,Vfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_8b_pp_01_w = @@ -29805,13 +30245,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_8b_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_8a_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2718] // VCOMPRESSPD Wfv{K}{z},aKq,Vfv + (const void *)&gInstructions[ 2759] // VCOMPRESSPD Wfv{K}{z},aKq,Vfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_8a_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2719] // VCOMPRESSPS Wfv{K}{z},aKq,Vfv + (const void *)&gInstructions[ 2760] // VCOMPRESSPS Wfv{K}{z},aKq,Vfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_8a_pp_01_w = @@ -29837,13 +30277,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_8a_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_89_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3553] // VPEXPANDQ Vfv{K}{z},aKq,Wfv + (const void *)&gInstructions[ 3598] // VPEXPANDQ Vfv{K}{z},aKq,Wfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_89_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3552] // VPEXPANDD Vfv{K}{z},aKq,Wfv + (const void *)&gInstructions[ 3597] // VPEXPANDD Vfv{K}{z},aKq,Wfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_89_pp_01_w = @@ -29869,13 +30309,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_89_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_88_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2888] // VEXPANDPD Vfv{K}{z},aKq,Wfv + (const void *)&gInstructions[ 2929] // VEXPANDPD Vfv{K}{z},aKq,Wfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_88_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2889] // VEXPANDPS Vfv{K}{z},aKq,Wfv + (const void *)&gInstructions[ 2930] // VEXPANDPS Vfv{K}{z},aKq,Wfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_88_pp_01_w = @@ -29901,7 +30341,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_88_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_83_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3745] // VPMULTISHIFTQB Vfv{K}{z},aKq,Hfv,Wfv|B64 + (const void *)&gInstructions[ 3790] // VPMULTISHIFTQB Vfv{K}{z},aKq,Hfv,Wfv|B64 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_83_pp_01_w = @@ -29927,13 +30367,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_83_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_7f_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3546] // VPERMT2PD Vfv{K}{z},aKq,Hfv,Wfv|B64 + (const void *)&gInstructions[ 3591] // VPERMT2PD Vfv{K}{z},aKq,Hfv,Wfv|B64 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_7f_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3547] // VPERMT2PS Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 3592] // VPERMT2PS Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_7f_pp_01_w = @@ -29959,13 +30399,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_7f_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_7e_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3548] // VPERMT2Q Vfv{K}{z},aKq,Hfv,Wfv|B64 + (const void *)&gInstructions[ 3593] // VPERMT2Q Vfv{K}{z},aKq,Hfv,Wfv|B64 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_7e_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3545] // VPERMT2D Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 3590] // VPERMT2D Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_7e_pp_01_w = @@ -29991,13 +30431,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_7e_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_7d_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3549] // VPERMT2W Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3594] // VPERMT2W Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_7d_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3544] // VPERMT2B Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3589] // VPERMT2B Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_7d_pp_01_w = @@ -30023,13 +30463,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_7d_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_7c_pp_01_modrmmod_01_wi_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3428] // VPBROADCASTQ Vfv{K}{z},aKq,Rq + (const void *)&gInstructions[ 3473] // VPBROADCASTQ Vfv{K}{z},aKq,Rq }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_7c_pp_01_modrmmod_01_wi_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3423] // VPBROADCASTD Vfv{K}{z},aKq,Rd + (const void *)&gInstructions[ 3468] // VPBROADCASTD Vfv{K}{z},aKq,Rd }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_7c_pp_01_modrmmod_01_wi = @@ -30064,7 +30504,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_7c_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_7b_pp_01_modrmmod_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3431] // VPBROADCASTW Vfv{K}{z},aKq,Rw + (const void *)&gInstructions[ 3476] // VPBROADCASTW Vfv{K}{z},aKq,Rw }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_7b_pp_01_modrmmod_01_w = @@ -30099,7 +30539,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_7b_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_7a_pp_01_modrmmod_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3420] // VPBROADCASTB Vfv{K}{z},aKq,Rb + (const void *)&gInstructions[ 3465] // VPBROADCASTB Vfv{K}{z},aKq,Rb }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_7a_pp_01_modrmmod_01_w = @@ -30134,7 +30574,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_7a_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_79_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3430] // VPBROADCASTW Vfv{K}{z},aKq,Ww + (const void *)&gInstructions[ 3475] // VPBROADCASTW Vfv{K}{z},aKq,Ww }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_79_pp_01_w = @@ -30160,7 +30600,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_79_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_78_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3419] // VPBROADCASTB Vfv{K}{z},aKq,Wb + (const void *)&gInstructions[ 3464] // VPBROADCASTB Vfv{K}{z},aKq,Wb }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_78_pp_01_w = @@ -30186,13 +30626,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_78_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_77_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3518] // VPERMI2PD Vfv{K}{z},aKq,Hfv,Wfv|B64 + (const void *)&gInstructions[ 3563] // VPERMI2PD Vfv{K}{z},aKq,Hfv,Wfv|B64 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_77_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3519] // VPERMI2PS Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 3564] // VPERMI2PS Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_77_pp_01_w = @@ -30218,13 +30658,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_77_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_76_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3520] // VPERMI2Q Vfv{K}{z},aKq,Hfv,Wfv|B64 + (const void *)&gInstructions[ 3565] // VPERMI2Q Vfv{K}{z},aKq,Hfv,Wfv|B64 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_76_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3517] // VPERMI2D Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 3562] // VPERMI2D Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_76_pp_01_w = @@ -30250,13 +30690,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_76_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_75_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3521] // VPERMI2W Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3566] // VPERMI2W Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_75_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3516] // VPERMI2B Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3561] // VPERMI2B Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_75_pp_01_w = @@ -30279,10 +30719,40 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_75_pp = } }; +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_74_pp_03_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2777] // VCVTNE2PH2BF8 Vfv{K}{z},aKq,Hfv,Wfv|B16 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_74_pp_03_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_74_pp_03_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_74_pp_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2788] // VCVTNEPH2BF8 Vhv{K}{z},aKq,Wfv|B16 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_74_pp_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_74_pp_02_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_74_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2725] // VCVTBIASPH2BF8 Vhv{K}{z},aKq,Hfv,Wfv|B16 + (const void *)&gInstructions[ 2766] // VCVTBIASPH2BF8 Vhv{K}{z},aKq,Hfv,Wfv|B16 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_74_pp_00_w = @@ -30300,21 +30770,21 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_74_pp = { /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_74_pp_00_w, /* 01 */ (const void *)ND_NULL, - /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_74_pp_02_w, + /* 03 */ (const void *)&gEvexMap_mmmmm_02_opcode_74_pp_03_w, } }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_73_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3808] // VPSHRDVQ Vfv{K}{z},aKq,Hfv,Wfv|B64 + (const void *)&gInstructions[ 3853] // VPSHRDVQ Vfv{K}{z},aKq,Hfv,Wfv|B64 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_73_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3807] // VPSHRDVD Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 3852] // VPSHRDVD Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_73_pp_01_w = @@ -30340,7 +30810,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_73_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_72_pp_03_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2740] // VCVTNE2PS2BF16 Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 2781] // VCVTNE2PS2BF16 Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_72_pp_03_w = @@ -30355,7 +30825,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_72_pp_03_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_72_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2751] // VCVTNEPS2BF16 Vhv{K}{z},aKq,Wfv|B32 + (const void *)&gInstructions[ 2792] // VCVTNEPS2BF16 Vhv{K}{z},aKq,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_72_pp_02_w = @@ -30370,7 +30840,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_72_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_72_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3809] // VPSHRDVW Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3854] // VPSHRDVW Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_72_pp_01_w = @@ -30396,13 +30866,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_72_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_71_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3799] // VPSHLDVQ Vfv{K}{z},aKq,Hfv,Wfv|B64 + (const void *)&gInstructions[ 3844] // VPSHLDVQ Vfv{K}{z},aKq,Hfv,Wfv|B64 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_71_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3798] // VPSHLDVD Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 3843] // VPSHLDVD Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_71_pp_01_w = @@ -30428,7 +30898,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_71_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_70_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3800] // VPSHLDVW Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3845] // VPSHLDVW Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_70_pp_01_w = @@ -30451,16 +30921,167 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_70_pp = } }; +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_6d_pp_03_modrmmod_01_l_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2607] // TCVTROWPS2PBF16H Voq,mTt,Bd +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_6d_pp_03_modrmmod_01_l_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_6d_pp_03_modrmmod_01_l_02_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_6d_pp_03_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_6d_pp_03_modrmmod_01_l_02_w, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_6d_pp_03_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_6d_pp_03_modrmmod_01_l, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_6d_pp_02_modrmmod_01_l_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2609] // TCVTROWPS2PBF16L Voq,mTt,Bd +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_6d_pp_02_modrmmod_01_l_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_6d_pp_02_modrmmod_01_l_02_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_6d_pp_02_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_6d_pp_02_modrmmod_01_l_02_w, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_6d_pp_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_6d_pp_02_modrmmod_01_l, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_6d_pp_01_modrmmod_01_l_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2613] // TCVTROWPS2PHL Voq,mTt,Bd +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_6d_pp_01_modrmmod_01_l_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_6d_pp_01_modrmmod_01_l_02_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_6d_pp_01_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_6d_pp_01_modrmmod_01_l_02_w, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_6d_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_6d_pp_01_modrmmod_01_l, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_6d_pp_00_modrmmod_01_l_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2611] // TCVTROWPS2PHH Voq,mTt,Bd +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_6d_pp_00_modrmmod_01_l_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_6d_pp_00_modrmmod_01_l_02_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_6d_pp_00_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_6d_pp_00_modrmmod_01_l_02_w, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_6d_pp_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_6d_pp_00_modrmmod_01_l, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_6d_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_6d_pp_00_modrmmod, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_6d_pp_01_modrmmod, + /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_6d_pp_02_modrmmod, + /* 03 */ (const void *)&gEvexMap_mmmmm_02_opcode_6d_pp_03_modrmmod, + } +}; + const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_68_pp_03_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3366] // VP2INTERSECTQ rKq+1,Hfv,Wfv|B64 + (const void *)&gInstructions[ 3411] // VP2INTERSECTQ rKq+1,Hfv,Wfv|B64 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_68_pp_03_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3365] // VP2INTERSECTD rKq+1,Hfv,Wfv|B32 + (const void *)&gInstructions[ 3410] // VP2INTERSECTD rKq+1,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_68_pp_03_w = @@ -30486,7 +31107,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_68_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_67_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2724] // VCVT2PS2PHX Vfv{K}{z},aKq,Hfv,Wfv|B32{er} + (const void *)&gInstructions[ 2765] // VCVT2PS2PHX Vfv{K}{z},aKq,Hfv,Wfv|B32{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_67_pp_01_w = @@ -30512,13 +31133,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_67_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_66_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3416] // VPBLENDMW Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3461] // VPBLENDMW Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_66_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3413] // VPBLENDMB Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3458] // VPBLENDMB Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_66_pp_01_w = @@ -30544,13 +31165,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_66_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_65_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2680] // VBLENDMPD Vfv{K}{z},aKq,Hfv,Wfv|B64 + (const void *)&gInstructions[ 2721] // VBLENDMPD Vfv{K}{z},aKq,Hfv,Wfv|B64 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_65_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2681] // VBLENDMPS Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 2722] // VBLENDMPS Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_65_pp_01_w = @@ -30576,13 +31197,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_65_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_64_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3415] // VPBLENDMQ Vfv{K}{z},aKq,Hfv,Wfv|B64 + (const void *)&gInstructions[ 3460] // VPBLENDMQ Vfv{K}{z},aKq,Hfv,Wfv|B64 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_64_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3414] // VPBLENDMD Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 3459] // VPBLENDMD Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_64_pp_01_w = @@ -30608,13 +31229,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_64_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_63_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3470] // VPCOMPRESSW Wfv{K}{z},aKq,Vfv + (const void *)&gInstructions[ 3515] // VPCOMPRESSW Wfv{K}{z},aKq,Vfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_63_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3467] // VPCOMPRESSB Wfv{K}{z},aKq,Vfv + (const void *)&gInstructions[ 3512] // VPCOMPRESSB Wfv{K}{z},aKq,Vfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_63_pp_01_w = @@ -30640,13 +31261,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_63_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_62_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3554] // VPEXPANDW Vfv{K}{z},aKq,Wfv + (const void *)&gInstructions[ 3599] // VPEXPANDW Vfv{K}{z},aKq,Wfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_62_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3551] // VPEXPANDB Vfv{K}{z},aKq,Wfv + (const void *)&gInstructions[ 3596] // VPEXPANDB Vfv{K}{z},aKq,Wfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_62_pp_01_w = @@ -30672,13 +31293,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_62_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_5b_pp_01_modrmmod_00_l_02_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2697] // VBROADCASTI64X4 Voq{K}{z},aKq,Mqq + (const void *)&gInstructions[ 2738] // VBROADCASTI64X4 Voq{K}{z},aKq,Mqq }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_5b_pp_01_modrmmod_00_l_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2695] // VBROADCASTI32X8 Voq{K}{z},aKq,Mqq + (const void *)&gInstructions[ 2736] // VBROADCASTI32X8 Voq{K}{z},aKq,Mqq }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_5b_pp_01_modrmmod_00_l_02_w = @@ -30724,13 +31345,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_5b_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_5a_pp_01_modrmmod_00_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2696] // VBROADCASTI64X2 Vuv{K}{z},aKq,Mdq + (const void *)&gInstructions[ 2737] // VBROADCASTI64X2 Vuv{K}{z},aKq,Mdq }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_5a_pp_01_modrmmod_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2694] // VBROADCASTI32X4 Vuv{K}{z},aKq,Mdq + (const void *)&gInstructions[ 2735] // VBROADCASTI32X4 Vuv{K}{z},aKq,Mdq }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_5a_pp_01_modrmmod_00_w = @@ -30765,13 +31386,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_5a_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_59_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3427] // VPBROADCASTQ Vfv{K}{z},aKq,Wq + (const void *)&gInstructions[ 3472] // VPBROADCASTQ Vfv{K}{z},aKq,Wq }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_59_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2693] // VBROADCASTI32X2 Vfv{K}{z},aKq,Wq + (const void *)&gInstructions[ 2734] // VBROADCASTI32X2 Vfv{K}{z},aKq,Wq }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_59_pp_01_w = @@ -30797,7 +31418,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_59_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_58_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3422] // VPBROADCASTD Vfv{K}{z},aKq,Wd + (const void *)&gInstructions[ 3467] // VPBROADCASTD Vfv{K}{z},aKq,Wd }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_58_pp_01_w = @@ -30823,13 +31444,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_58_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_55_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3750] // VPOPCNTQ Vfv{K}{z},aKq,Wfv|B64 + (const void *)&gInstructions[ 3795] // VPOPCNTQ Vfv{K}{z},aKq,Wfv|B64 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_55_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3749] // VPOPCNTD Vfv{K}{z},aKq,Wfv|B32 + (const void *)&gInstructions[ 3794] // VPOPCNTD Vfv{K}{z},aKq,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_55_pp_01_w = @@ -30855,13 +31476,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_55_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_54_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3751] // VPOPCNTW Vfv{K}{z},aKq,Wfv + (const void *)&gInstructions[ 3796] // VPOPCNTW Vfv{K}{z},aKq,Wfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_54_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3748] // VPOPCNTB Vfv{K}{z},aKq,Wfv + (const void *)&gInstructions[ 3793] // VPOPCNTB Vfv{K}{z},aKq,Wfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_54_pp_01_w = @@ -30887,7 +31508,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_54_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_53_pp_03_modrmmod_00_l_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3368] // VP4DPWSSDS Voq{K}{z},aKq,Hoq+3,Mdq + (const void *)&gInstructions[ 3413] // VP4DPWSSDS Voq{K}{z},aKq,Hoq+3,Mdq }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_53_pp_03_modrmmod_00_l_02_w = @@ -30922,7 +31543,7 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_53_pp_03_modrmmod = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_53_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3497] // VPDPWSSDS Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 3542] // VPDPWSSDS Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_53_pp_01_w = @@ -30948,7 +31569,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_53_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_52_pp_03_modrmmod_00_l_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3367] // VP4DPWSSD Voq{K}{z},aKq,Hoq+3,Mdq + (const void *)&gInstructions[ 3412] // VP4DPWSSD Voq{K}{z},aKq,Hoq+3,Mdq }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_52_pp_03_modrmmod_00_l_02_w = @@ -30983,7 +31604,7 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_52_pp_03_modrmmod = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_52_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2880] // VDPBF16PS Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 2921] // VDPBF16PS Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_52_pp_02_w = @@ -30998,7 +31619,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_52_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_52_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3495] // VPDPWSSD Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 3540] // VPDPWSSD Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_52_pp_01_w = @@ -31013,7 +31634,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_52_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_52_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2882] // VDPPHPS Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 2923] // VDPPHPS Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_52_pp_00_w = @@ -31039,7 +31660,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_52_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_51_pp_03_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3481] // VPDPBSSDS Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 3526] // VPDPBSSDS Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_51_pp_03_w = @@ -31054,7 +31675,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_51_pp_03_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_51_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3485] // VPDPBSUDS Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 3530] // VPDPBSUDS Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_51_pp_02_w = @@ -31069,7 +31690,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_51_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_51_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3489] // VPDPBUSDS Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 3534] // VPDPBUSDS Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_51_pp_01_w = @@ -31084,7 +31705,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_51_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_51_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3493] // VPDPBUUDS Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 3538] // VPDPBUUDS Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_51_pp_00_w = @@ -31110,7 +31731,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_51_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_50_pp_03_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3479] // VPDPBSSD Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 3524] // VPDPBSSD Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_50_pp_03_w = @@ -31125,7 +31746,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_50_pp_03_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_50_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3483] // VPDPBSUD Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 3528] // VPDPBSUD Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_50_pp_02_w = @@ -31140,7 +31761,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_50_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_50_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3487] // VPDPBUSD Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 3532] // VPDPBUSD Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_50_pp_01_w = @@ -31155,7 +31776,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_50_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_50_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3491] // VPDPBUUD Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 3536] // VPDPBUUD Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_50_pp_00_w = @@ -31181,13 +31802,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_50_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_4f_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3958] // VRSQRT14SD Vdq{K}{z},aKq,Hdq,Wsd + (const void *)&gInstructions[ 4003] // VRSQRT14SD Vdq{K}{z},aKq,Hdq,Wsd }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_4f_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3959] // VRSQRT14SS Vdq{K}{z},aKq,Hdq,Wss + (const void *)&gInstructions[ 4004] // VRSQRT14SS Vdq{K}{z},aKq,Hdq,Wss }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_4f_pp_01_w = @@ -31213,13 +31834,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_4f_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_4e_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3956] // VRSQRT14PD Vfv{K}{z},aKq,Wfv|B64 + (const void *)&gInstructions[ 4001] // VRSQRT14PD Vfv{K}{z},aKq,Wfv|B64 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_4e_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3957] // VRSQRT14PS Vfv{K}{z},aKq,Wfv|B32 + (const void *)&gInstructions[ 4002] // VRSQRT14PS Vfv{K}{z},aKq,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_4e_pp_01_w = @@ -31245,13 +31866,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_4e_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_4d_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3927] // VRCP14SD Vdq{K}{z},aKq,Hdq,Wsd + (const void *)&gInstructions[ 3972] // VRCP14SD Vdq{K}{z},aKq,Hdq,Wsd }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_4d_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3928] // VRCP14SS Vdq{K}{z},aKq,Hdq,Wss + (const void *)&gInstructions[ 3973] // VRCP14SS Vdq{K}{z},aKq,Hdq,Wss }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_4d_pp_01_w = @@ -31277,13 +31898,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_4d_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_4c_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3925] // VRCP14PD Vfv{K}{z},aKq,Wfv|B64 + (const void *)&gInstructions[ 3970] // VRCP14PD Vfv{K}{z},aKq,Wfv|B64 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_4c_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3926] // VRCP14PS Vfv{K}{z},aKq,Wfv|B32 + (const void *)&gInstructions[ 3971] // VRCP14PS Vfv{K}{z},aKq,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_4c_pp_01_w = @@ -31309,7 +31930,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_4c_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_4b_pp_03_modrmmod_00_modrmrm_04_l_00_w_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2605] // TILELOADD rTt,Mt + (const void *)&gInstructions[ 2635] // TILELOADD rTt,Mt }; const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_4b_pp_03_modrmmod_00_modrmrm_04_l_00_w_00_nf = @@ -31368,7 +31989,7 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_4b_pp_03_modrmmod = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_4b_pp_02_modrmmod_00_modrmrm_04_l_00_w_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2610] // TILESTORED Mt,rTt + (const void *)&gInstructions[ 2644] // TILESTORED Mt,rTt }; const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_4b_pp_02_modrmmod_00_modrmrm_04_l_00_w_00_nf = @@ -31427,7 +32048,7 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_4b_pp_02_modrmmod = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_4b_pp_01_modrmmod_00_modrmrm_04_l_00_w_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2607] // TILELOADDT1 rTt,Mt + (const void *)&gInstructions[ 2639] // TILELOADDT1 rTt,Mt }; const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_4b_pp_01_modrmmod_00_modrmrm_04_l_00_w_00_nf = @@ -31494,10 +32115,91 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_4b_pp = } }; +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_4a_pp_02_modrmmod_01_l_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2605] // TCVTROWD2PS Voq,mTt,Bd +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_4a_pp_02_modrmmod_01_l_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_4a_pp_02_modrmmod_01_l_02_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_4a_pp_02_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_4a_pp_02_modrmmod_01_l_02_w, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_4a_pp_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_4a_pp_02_modrmmod_01_l, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_4a_pp_01_modrmmod_01_l_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2641] // TILEMOVROW Voq,mTt,Bd +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_4a_pp_01_modrmmod_01_l_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_4a_pp_01_modrmmod_01_l_02_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_4a_pp_01_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_4a_pp_01_modrmmod_01_l_02_w, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_4a_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_4a_pp_01_modrmmod_01_l, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_4a_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_4a_pp_01_modrmmod, + /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_4a_pp_02_modrmmod, + /* 03 */ (const void *)ND_NULL, + } +}; + const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_49_pp_01_modrmreg_00_modrmmod_00_l_00_w_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2520] // STTILECFG Moq + (const void *)&gInstructions[ 2526] // STTILECFG Moq }; const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_49_pp_01_modrmreg_00_modrmmod_00_l_00_w_00_nf = @@ -31626,13 +32328,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_49_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_47_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3835] // VPSLLVQ Vfv{K}{z},aKq,Hfv,Wfv|B64 + (const void *)&gInstructions[ 3880] // VPSLLVQ Vfv{K}{z},aKq,Hfv,Wfv|B64 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_47_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3833] // VPSLLVD Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 3878] // VPSLLVD Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_47_pp_01_w = @@ -31658,13 +32360,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_47_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_46_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3850] // VPSRAVQ Vfv{K}{z},aKq,Hfv,Wfv|B64 + (const void *)&gInstructions[ 3895] // VPSRAVQ Vfv{K}{z},aKq,Hfv,Wfv|B64 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_46_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3848] // VPSRAVD Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 3893] // VPSRAVD Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_46_pp_01_w = @@ -31690,13 +32392,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_46_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_45_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3868] // VPSRLVQ Vfv{K}{z},aKq,Hfv,Wfv|B64 + (const void *)&gInstructions[ 3913] // VPSRLVQ Vfv{K}{z},aKq,Hfv,Wfv|B64 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_45_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3866] // VPSRLVD Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 3911] // VPSRLVD Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_45_pp_01_w = @@ -31722,13 +32424,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_45_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_44_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3616] // VPLZCNTQ Vfv{K}{z},aKq,Wfv|B64 + (const void *)&gInstructions[ 3661] // VPLZCNTQ Vfv{K}{z},aKq,Wfv|B64 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_44_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3615] // VPLZCNTD Vfv{K}{z},aKq,Wfv|B32 + (const void *)&gInstructions[ 3660] // VPLZCNTD Vfv{K}{z},aKq,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_44_pp_01_w = @@ -31754,13 +32456,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_44_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_43_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3149] // VGETEXPSD Vdq{K}{z},aKq,Hdq,Wsd{sae} + (const void *)&gInstructions[ 3190] // VGETEXPSD Vdq{K}{z},aKq,Hdq,Wsd{sae} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_43_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3151] // VGETEXPSS Vdq{K}{z},aKq,Hdq,Wss{sae} + (const void *)&gInstructions[ 3192] // VGETEXPSS Vdq{K}{z},aKq,Hdq,Wss{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_43_pp_01_w = @@ -31786,13 +32488,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_43_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_42_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3146] // VGETEXPPD Vfv{K}{z},aKq,Wfv|B64{sae} + (const void *)&gInstructions[ 3187] // VGETEXPPD Vfv{K}{z},aKq,Wfv|B64{sae} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_42_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3148] // VGETEXPPS Vfv{K}{z},aKq,Wfv|B32{sae} + (const void *)&gInstructions[ 3189] // VGETEXPPS Vfv{K}{z},aKq,Wfv|B32{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_42_pp_01_w = @@ -31818,13 +32520,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_42_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_40_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3742] // VPMULLQ Vfv{K}{z},aKq,Hfv,Wfv|B64 + (const void *)&gInstructions[ 3787] // VPMULLQ Vfv{K}{z},aKq,Hfv,Wfv|B64 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_40_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3740] // VPMULLD Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 3785] // VPMULLD Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_40_pp_01_w = @@ -31850,13 +32552,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_40_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_3f_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3652] // VPMAXUQ Vfv{K}{z},aKq,Hfv,Wfv|B64 + (const void *)&gInstructions[ 3697] // VPMAXUQ Vfv{K}{z},aKq,Hfv,Wfv|B64 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_3f_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3650] // VPMAXUD Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 3695] // VPMAXUD Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_3f_pp_01_w = @@ -31882,7 +32584,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_3f_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_3e_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3653] // VPMAXUW Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3698] // VPMAXUW Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_3e_pp = @@ -31899,13 +32601,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_3e_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_3d_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3645] // VPMAXSQ Vfv{K}{z},aKq,Hfv,Wfv|B64 + (const void *)&gInstructions[ 3690] // VPMAXSQ Vfv{K}{z},aKq,Hfv,Wfv|B64 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_3d_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3643] // VPMAXSD Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 3688] // VPMAXSD Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_3d_pp_01_w = @@ -31931,7 +32633,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_3d_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_3c_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3641] // VPMAXSB Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3686] // VPMAXSB Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_3c_pp = @@ -31948,13 +32650,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_3c_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_3b_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3666] // VPMINUQ Vfv{K}{z},aKq,Hfv,Wfv|B64 + (const void *)&gInstructions[ 3711] // VPMINUQ Vfv{K}{z},aKq,Hfv,Wfv|B64 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_3b_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3664] // VPMINUD Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 3709] // VPMINUD Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_3b_pp_01_w = @@ -31980,7 +32682,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_3b_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_3a_pp_02_modrmmod_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3426] // VPBROADCASTMW2D Vfv,mKq + (const void *)&gInstructions[ 3471] // VPBROADCASTMW2D Vfv,mKq }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_3a_pp_02_modrmmod_01_w = @@ -32004,7 +32706,7 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_3a_pp_02_modrmmod = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_3a_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3667] // VPMINUW Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3712] // VPMINUW Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_3a_pp = @@ -32021,13 +32723,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_3a_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_39_pp_02_modrmmod_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3678] // VPMOVQ2M rKq,Ufv + (const void *)&gInstructions[ 3723] // VPMOVQ2M rKq,Ufv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_39_pp_02_modrmmod_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3670] // VPMOVD2M rKq,Ufv + (const void *)&gInstructions[ 3715] // VPMOVD2M rKq,Ufv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_39_pp_02_modrmmod_01_w = @@ -32051,13 +32753,13 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_39_pp_02_modrmmod = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_39_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3659] // VPMINSQ Vfv{K}{z},aKq,Hfv,Wfv|B64 + (const void *)&gInstructions[ 3704] // VPMINSQ Vfv{K}{z},aKq,Hfv,Wfv|B64 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_39_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3657] // VPMINSD Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 3702] // VPMINSD Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_39_pp_01_w = @@ -32083,13 +32785,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_39_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_38_pp_02_modrmmod_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3675] // VPMOVM2Q Vfv,mKq + (const void *)&gInstructions[ 3720] // VPMOVM2Q Vfv,mKq }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_38_pp_02_modrmmod_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3674] // VPMOVM2D Vfv,mKq + (const void *)&gInstructions[ 3719] // VPMOVM2D Vfv,mKq }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_38_pp_02_modrmmod_01_w = @@ -32113,7 +32815,7 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_38_pp_02_modrmmod = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_38_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3655] // VPMINSB Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3700] // VPMINSB Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_38_pp = @@ -32130,7 +32832,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_38_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_37_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3453] // VPCMPGTQ rKq{K},aKq,Hfv,Wfv|B64 + (const void *)&gInstructions[ 3498] // VPCMPGTQ rKq{K},aKq,Hfv,Wfv|B64 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_37_pp_01_w = @@ -32156,13 +32858,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_37_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_36_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3541] // VPERMQ Vuv{K}{z},aKq,Huv,Wuv|B64 + (const void *)&gInstructions[ 3586] // VPERMQ Vuv{K}{z},aKq,Huv,Wuv|B64 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_36_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3514] // VPERMD Vuv{K}{z},aKq,Huv,Wuv|B32 + (const void *)&gInstructions[ 3559] // VPERMD Vuv{K}{z},aKq,Huv,Wuv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_36_pp_01_w = @@ -32188,7 +32890,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_36_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_35_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3680] // VPMOVQD Whv{K}{z},aKq,Vfv + (const void *)&gInstructions[ 3725] // VPMOVQD Whv{K}{z},aKq,Vfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_35_pp_02_w = @@ -32203,7 +32905,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_35_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_35_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3723] // VPMOVZXDQ Vfv{K}{z},aKq,Whv + (const void *)&gInstructions[ 3768] // VPMOVZXDQ Vfv{K}{z},aKq,Whv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_35_pp_01_w = @@ -32229,7 +32931,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_35_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_34_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3681] // VPMOVQW Wqv{K}{z},aKq,Vfv + (const void *)&gInstructions[ 3726] // VPMOVQW Wqv{K}{z},aKq,Vfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_34_pp_02_w = @@ -32244,7 +32946,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_34_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_34_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3729] // VPMOVZXWQ Vfv{K}{z},aKq,Wqv + (const void *)&gInstructions[ 3774] // VPMOVZXWQ Vfv{K}{z},aKq,Wqv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_34_pp = @@ -32261,7 +32963,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_34_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_33_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3672] // VPMOVDW Whv{K}{z},aKq,Vfv + (const void *)&gInstructions[ 3717] // VPMOVDW Whv{K}{z},aKq,Vfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_33_pp_02_w = @@ -32276,7 +32978,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_33_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_33_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3726] // VPMOVZXWD Vfv{K}{z},aKq,Whv + (const void *)&gInstructions[ 3771] // VPMOVZXWD Vfv{K}{z},aKq,Whv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_33_pp = @@ -32293,7 +32995,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_33_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_32_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3679] // VPMOVQB Wev{K}{z},aKq,Vfv + (const void *)&gInstructions[ 3724] // VPMOVQB Wev{K}{z},aKq,Vfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_32_pp_02_w = @@ -32308,7 +33010,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_32_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_32_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3717] // VPMOVZXBQ Vfv{K}{z},aKq,Wev + (const void *)&gInstructions[ 3762] // VPMOVZXBQ Vfv{K}{z},aKq,Wev }; const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_32_pp = @@ -32325,7 +33027,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_32_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_31_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3671] // VPMOVDB Wqv{K}{z},aKq,Vfv + (const void *)&gInstructions[ 3716] // VPMOVDB Wqv{K}{z},aKq,Vfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_31_pp_02_w = @@ -32340,7 +33042,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_31_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_31_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3714] // VPMOVZXBD Vfv{K}{z},aKq,Wqv + (const void *)&gInstructions[ 3759] // VPMOVZXBD Vfv{K}{z},aKq,Wqv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_31_pp = @@ -32357,7 +33059,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_31_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_30_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3713] // VPMOVWB Whv{K}{z},aKq,Vfv + (const void *)&gInstructions[ 3758] // VPMOVWB Whv{K}{z},aKq,Vfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_30_pp_02_w = @@ -32372,7 +33074,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_30_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_30_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3720] // VPMOVZXBW Vfv{K}{z},aKq,Whv + (const void *)&gInstructions[ 3765] // VPMOVZXBW Vfv{K}{z},aKq,Whv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_30_pp = @@ -32389,13 +33091,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_30_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_2d_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3973] // VSCALEFSD Vsd{K}{z},aKq,Hsd,Wsd{er} + (const void *)&gInstructions[ 4018] // VSCALEFSD Vsd{K}{z},aKq,Hsd,Wsd{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_2d_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3975] // VSCALEFSS Vss{K}{z},aKq,Hss,Wss{er} + (const void *)&gInstructions[ 4020] // VSCALEFSS Vss{K}{z},aKq,Hss,Wss{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_2d_pp_01_w = @@ -32421,13 +33123,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_2d_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_2c_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3970] // VSCALEFPD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} + (const void *)&gInstructions[ 4015] // VSCALEFPD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_2c_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3972] // VSCALEFPS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} + (const void *)&gInstructions[ 4017] // VSCALEFPS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_2c_pp_01_w = @@ -32453,7 +33155,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_2c_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_2b_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3380] // VPACKUSDW Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 3425] // VPACKUSDW Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_2b_pp_01_w = @@ -32479,7 +33181,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_2b_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_2a_pp_02_modrmmod_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3425] // VPBROADCASTMB2Q Vfv,mKq + (const void *)&gInstructions[ 3470] // VPBROADCASTMB2Q Vfv,mKq }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_2a_pp_02_modrmmod_01_w = @@ -32503,7 +33205,7 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_2a_pp_02_modrmmod = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_2a_pp_01_modrmmod_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3287] // VMOVNTDQA Vfv,Mfv + (const void *)&gInstructions[ 3328] // VMOVNTDQA Vfv,Mfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_2a_pp_01_modrmmod_00_w = @@ -32538,13 +33240,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_2a_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_29_pp_02_modrmmod_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3712] // VPMOVW2M rKq,Ufv + (const void *)&gInstructions[ 3757] // VPMOVW2M rKq,Ufv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_29_pp_02_modrmmod_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3669] // VPMOVB2M rKq,Ufv + (const void *)&gInstructions[ 3714] // VPMOVB2M rKq,Ufv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_29_pp_02_modrmmod_01_w = @@ -32568,7 +33270,7 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_29_pp_02_modrmmod = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_29_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3443] // VPCMPEQQ rKq{K},aKq,Hfv,Wfv|B64 + (const void *)&gInstructions[ 3488] // VPCMPEQQ rKq{K},aKq,Hfv,Wfv|B64 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_29_pp_01_w = @@ -32594,13 +33296,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_29_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_28_pp_02_modrmmod_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3676] // VPMOVM2W Vfv,mKq + (const void *)&gInstructions[ 3721] // VPMOVM2W Vfv,mKq }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_28_pp_02_modrmmod_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3673] // VPMOVM2B Vfv,mKq + (const void *)&gInstructions[ 3718] // VPMOVM2B Vfv,mKq }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_28_pp_02_modrmmod_01_w = @@ -32624,7 +33326,7 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_28_pp_02_modrmmod = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_28_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3732] // VPMULDQ Vfv{K}{z},aKq,Hfv,Wfv|B64 + (const void *)&gInstructions[ 3777] // VPMULDQ Vfv{K}{z},aKq,Hfv,Wfv|B64 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_28_pp_01_w = @@ -32650,13 +33352,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_28_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_27_pp_02_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3900] // VPTESTNMQ rKq{K},aKq,Hfv,Wfv|B64 + (const void *)&gInstructions[ 3945] // VPTESTNMQ rKq{K},aKq,Hfv,Wfv|B64 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_27_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3899] // VPTESTNMD rKq{K},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 3944] // VPTESTNMD rKq{K},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_27_pp_02_w = @@ -32671,13 +33373,13 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_27_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_27_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3896] // VPTESTMQ rKq{K},aKq,Hfv,Wfv|B64 + (const void *)&gInstructions[ 3941] // VPTESTMQ rKq{K},aKq,Hfv,Wfv|B64 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_27_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3895] // VPTESTMD rKq{K},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 3940] // VPTESTMD rKq{K},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_27_pp_01_w = @@ -32703,13 +33405,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_27_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_26_pp_02_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3901] // VPTESTNMW rKq{K},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3946] // VPTESTNMW rKq{K},aKq,Hfv,Wfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_26_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3898] // VPTESTNMB rKq{K},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3943] // VPTESTNMB rKq{K},aKq,Hfv,Wfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_26_pp_02_w = @@ -32724,13 +33426,13 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_26_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_26_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3897] // VPTESTMW rKq{K},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3942] // VPTESTMW rKq{K},aKq,Hfv,Wfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_26_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3894] // VPTESTMB rKq{K},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3939] // VPTESTMB rKq{K},aKq,Hfv,Wfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_26_pp_01_w = @@ -32756,7 +33458,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_26_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_25_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3685] // VPMOVSQD Whv{K}{z},aKq,Vfv + (const void *)&gInstructions[ 3730] // VPMOVSQD Whv{K}{z},aKq,Vfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_25_pp_02_w = @@ -32771,7 +33473,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_25_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_25_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3697] // VPMOVSXDQ Vfv{K}{z},aKq,Whv + (const void *)&gInstructions[ 3742] // VPMOVSXDQ Vfv{K}{z},aKq,Whv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_25_pp_01_w = @@ -32797,7 +33499,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_25_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_24_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3686] // VPMOVSQW Wqv{K}{z},aKq,Vfv + (const void *)&gInstructions[ 3731] // VPMOVSQW Wqv{K}{z},aKq,Vfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_24_pp_02_w = @@ -32812,7 +33514,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_24_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_24_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3703] // VPMOVSXWQ Vfv{K}{z},aKq,Wqv + (const void *)&gInstructions[ 3748] // VPMOVSXWQ Vfv{K}{z},aKq,Wqv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_24_pp = @@ -32829,7 +33531,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_24_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_23_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3683] // VPMOVSDW Whv{K}{z},aKq,Vfv + (const void *)&gInstructions[ 3728] // VPMOVSDW Whv{K}{z},aKq,Vfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_23_pp_02_w = @@ -32844,7 +33546,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_23_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_23_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3700] // VPMOVSXWD Vfv{K}{z},aKq,Whv + (const void *)&gInstructions[ 3745] // VPMOVSXWD Vfv{K}{z},aKq,Whv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_23_pp = @@ -32861,7 +33563,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_23_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_22_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3684] // VPMOVSQB Wev{K}{z},aKq,Vfv + (const void *)&gInstructions[ 3729] // VPMOVSQB Wev{K}{z},aKq,Vfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_22_pp_02_w = @@ -32876,7 +33578,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_22_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_22_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3691] // VPMOVSXBQ Vfv{K}{z},aKq,Wev + (const void *)&gInstructions[ 3736] // VPMOVSXBQ Vfv{K}{z},aKq,Wev }; const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_22_pp = @@ -32893,7 +33595,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_22_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_21_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3682] // VPMOVSDB Wqv{K}{z},aKq,Vfv + (const void *)&gInstructions[ 3727] // VPMOVSDB Wqv{K}{z},aKq,Vfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_21_pp_02_w = @@ -32908,7 +33610,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_21_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_21_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3688] // VPMOVSXBD Vfv{K}{z},aKq,Wqv + (const void *)&gInstructions[ 3733] // VPMOVSXBD Vfv{K}{z},aKq,Wqv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_21_pp = @@ -32925,7 +33627,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_21_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_20_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3687] // VPMOVSWB Whv{K}{z},aKq,Vfv + (const void *)&gInstructions[ 3732] // VPMOVSWB Whv{K}{z},aKq,Vfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_20_pp_02_w = @@ -32940,7 +33642,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_20_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_20_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3694] // VPMOVSXBW Vfv{K}{z},aKq,Whv + (const void *)&gInstructions[ 3739] // VPMOVSXBW Vfv{K}{z},aKq,Whv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_20_pp = @@ -32957,7 +33659,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_20_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_1f_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3373] // VPABSQ Vfv{K}{z},aKq,Wfv|B64 + (const void *)&gInstructions[ 3418] // VPABSQ Vfv{K}{z},aKq,Wfv|B64 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_1f_pp_01_w = @@ -32983,7 +33685,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_1f_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_1e_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3371] // VPABSD Vfv{K}{z},aKq,Wfv|B32 + (const void *)&gInstructions[ 3416] // VPABSD Vfv{K}{z},aKq,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_1e_pp_01_w = @@ -33009,7 +33711,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_1e_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_1d_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3374] // VPABSW Vfv{K}{z},aKq,Wfv + (const void *)&gInstructions[ 3419] // VPABSW Vfv{K}{z},aKq,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_1d_pp = @@ -33026,7 +33728,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_1d_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_1c_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3369] // VPABSB Vfv{K}{z},aKq,Wfv + (const void *)&gInstructions[ 3414] // VPABSB Vfv{K}{z},aKq,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_1c_pp = @@ -33043,13 +33745,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_1c_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_1b_pp_01_modrmmod_00_l_02_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2691] // VBROADCASTF64X4 Voq{K}{z},aKq,Mqq + (const void *)&gInstructions[ 2732] // VBROADCASTF64X4 Voq{K}{z},aKq,Mqq }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_1b_pp_01_modrmmod_00_l_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2689] // VBROADCASTF32X8 Voq{K}{z},aKq,Mqq + (const void *)&gInstructions[ 2730] // VBROADCASTF32X8 Voq{K}{z},aKq,Mqq }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_1b_pp_01_modrmmod_00_l_02_w = @@ -33095,13 +33797,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_1b_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_1a_pp_01_modrmmod_00_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2690] // VBROADCASTF64X2 Vuv{K}{z},aKq,Mdq + (const void *)&gInstructions[ 2731] // VBROADCASTF64X2 Vuv{K}{z},aKq,Mdq }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_1a_pp_01_modrmmod_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2688] // VBROADCASTF32X4 Vuv{K}{z},aKq,Mdq + (const void *)&gInstructions[ 2729] // VBROADCASTF32X4 Vuv{K}{z},aKq,Mdq }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_1a_pp_01_modrmmod_00_w = @@ -33136,13 +33838,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_1a_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_19_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2698] // VBROADCASTSD Vuv{K}{z},aKq,Wsd + (const void *)&gInstructions[ 2739] // VBROADCASTSD Vuv{K}{z},aKq,Wsd }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_19_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2687] // VBROADCASTF32X2 Vuv{K}{z},aKq,Wq + (const void *)&gInstructions[ 2728] // VBROADCASTF32X2 Vuv{K}{z},aKq,Wq }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_19_pp_01_w = @@ -33168,7 +33870,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_19_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_18_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2700] // VBROADCASTSS Vfv{K}{z},aKq,Wss + (const void *)&gInstructions[ 2741] // VBROADCASTSS Vfv{K}{z},aKq,Wss }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_18_pp_01_w = @@ -33194,13 +33896,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_18_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_16_pp_01_l_02_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3535] // VPERMPD Vuv{K}{z},aKq,Huv,Wuv|B64 + (const void *)&gInstructions[ 3580] // VPERMPD Vuv{K}{z},aKq,Huv,Wuv|B64 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_16_pp_01_l_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3539] // VPERMPS Vuv{K}{z},aKq,Huv,Wuv|B32 + (const void *)&gInstructions[ 3584] // VPERMPS Vuv{K}{z},aKq,Huv,Wuv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_16_pp_01_l_02_w = @@ -33215,13 +33917,13 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_16_pp_01_l_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_16_pp_01_l_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3534] // VPERMPD Vuv{K}{z},aKq,Huv,Wuv|B64 + (const void *)&gInstructions[ 3579] // VPERMPD Vuv{K}{z},aKq,Huv,Wuv|B64 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_16_pp_01_l_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3538] // VPERMPS Vuv{K}{z},aKq,Huv,Wuv|B32 + (const void *)&gInstructions[ 3583] // VPERMPS Vuv{K}{z},aKq,Huv,Wuv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_16_pp_01_l_01_w = @@ -33258,7 +33960,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_16_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_15_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3709] // VPMOVUSQD Whv{K}{z},aKq,Vfv + (const void *)&gInstructions[ 3754] // VPMOVUSQD Whv{K}{z},aKq,Vfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_15_pp_02_w = @@ -33273,13 +33975,13 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_15_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_15_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3760] // VPROLVQ Vfv{K}{z},aKq,Hfv,Wfv|B64 + (const void *)&gInstructions[ 3805] // VPROLVQ Vfv{K}{z},aKq,Hfv,Wfv|B64 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_15_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3759] // VPROLVD Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 3804] // VPROLVD Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_15_pp_01_w = @@ -33305,7 +34007,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_15_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_14_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3710] // VPMOVUSQW Wqv{K}{z},aKq,Vfv + (const void *)&gInstructions[ 3755] // VPMOVUSQW Wqv{K}{z},aKq,Vfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_14_pp_02_w = @@ -33320,13 +34022,13 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_14_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_14_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3764] // VPRORVQ Vfv{K}{z},aKq,Hfv,Wfv|B64 + (const void *)&gInstructions[ 3809] // VPRORVQ Vfv{K}{z},aKq,Hfv,Wfv|B64 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_14_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3763] // VPRORVD Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 3808] // VPRORVD Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_14_pp_01_w = @@ -33352,7 +34054,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_14_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_13_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3707] // VPMOVUSDW Whv{K}{z},aKq,Vfv + (const void *)&gInstructions[ 3752] // VPMOVUSDW Whv{K}{z},aKq,Vfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_13_pp_02_w = @@ -33367,7 +34069,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_13_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_13_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2766] // VCVTPH2PS Vfv{K}{z},aKq,Whv{sae} + (const void *)&gInstructions[ 2807] // VCVTPH2PS Vfv{K}{z},aKq,Whv{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_13_pp_01_w = @@ -33393,7 +34095,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_13_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_12_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3708] // VPMOVUSQB Wev{K}{z},aKq,Vfv + (const void *)&gInstructions[ 3753] // VPMOVUSQB Wev{K}{z},aKq,Vfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_12_pp_02_w = @@ -33408,7 +34110,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_12_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_12_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3837] // VPSLLVW Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3882] // VPSLLVW Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_12_pp_01_w = @@ -33434,7 +34136,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_12_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_11_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3706] // VPMOVUSDB Wqv{K}{z},aKq,Vfv + (const void *)&gInstructions[ 3751] // VPMOVUSDB Wqv{K}{z},aKq,Vfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_11_pp_02_w = @@ -33449,7 +34151,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_11_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_11_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3851] // VPSRAVW Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3896] // VPSRAVW Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_11_pp_01_w = @@ -33475,7 +34177,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_11_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_10_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3711] // VPMOVUSWB Whv{K}{z},aKq,Vfv + (const void *)&gInstructions[ 3756] // VPMOVUSWB Whv{K}{z},aKq,Vfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_10_pp_02_w = @@ -33490,7 +34192,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_10_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_10_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3870] // VPSRLVW Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3915] // VPSRLVW Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_10_pp_01_w = @@ -33516,7 +34218,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_10_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_0d_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3526] // VPERMILPD Vfv{K}{z},aKq,Hfv,Wfv|B64 + (const void *)&gInstructions[ 3571] // VPERMILPD Vfv{K}{z},aKq,Hfv,Wfv|B64 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_0d_pp_01_w = @@ -33542,7 +34244,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_0d_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_0c_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3530] // VPERMILPS Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 3575] // VPERMILPS Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_0c_pp_01_w = @@ -33568,7 +34270,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_0c_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_0b_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3734] // VPMULHRSW Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3779] // VPMULHRSW Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_0b_pp = @@ -33585,7 +34287,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_0b_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_04_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3633] // VPMADDUBSW Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3678] // VPMADDUBSW Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_04_pp = @@ -33602,7 +34304,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_04_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_00_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3811] // VPSHUFB Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3856] // VPSHUFB Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_00_pp = @@ -33694,7 +34396,7 @@ const ND_TABLE_OPCODE gEvexMap_mmmmm_02_opcode = /* 47 */ (const void *)&gEvexMap_mmmmm_02_opcode_47_pp, /* 48 */ (const void *)ND_NULL, /* 49 */ (const void *)&gEvexMap_mmmmm_02_opcode_49_pp, - /* 4a */ (const void *)ND_NULL, + /* 4a */ (const void *)&gEvexMap_mmmmm_02_opcode_4a_pp, /* 4b */ (const void *)&gEvexMap_mmmmm_02_opcode_4b_pp, /* 4c */ (const void *)&gEvexMap_mmmmm_02_opcode_4c_pp, /* 4d */ (const void *)&gEvexMap_mmmmm_02_opcode_4d_pp, @@ -33729,7 +34431,7 @@ const ND_TABLE_OPCODE gEvexMap_mmmmm_02_opcode = /* 6a */ (const void *)ND_NULL, /* 6b */ (const void *)ND_NULL, /* 6c */ (const void *)ND_NULL, - /* 6d */ (const void *)ND_NULL, + /* 6d */ (const void *)&gEvexMap_mmmmm_02_opcode_6d_pp, /* 6e */ (const void *)ND_NULL, /* 6f */ (const void *)ND_NULL, /* 70 */ (const void *)&gEvexMap_mmmmm_02_opcode_70_pp, @@ -33838,7 +34540,7 @@ const ND_TABLE_OPCODE gEvexMap_mmmmm_02_opcode = /* d7 */ (const void *)ND_NULL, /* d8 */ (const void *)ND_NULL, /* d9 */ (const void *)ND_NULL, - /* da */ (const void *)ND_NULL, + /* da */ (const void *)&gEvexMap_mmmmm_02_opcode_da_pp, /* db */ (const void *)ND_NULL, /* dc */ (const void *)&gEvexMap_mmmmm_02_opcode_dc_pp, /* dd */ (const void *)&gEvexMap_mmmmm_02_opcode_dd_pp, @@ -33882,7 +34584,7 @@ const ND_TABLE_OPCODE gEvexMap_mmmmm_02_opcode = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_fe_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3386] // VPADDD Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 3431] // VPADDD Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_fe_pp_01_w = @@ -33908,7 +34610,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_fe_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_fd_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3398] // VPADDW Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3443] // VPADDW Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_fd_pp = @@ -33925,7 +34627,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_fd_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_fc_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3384] // VPADDB Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3429] // VPADDB Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_fc_pp = @@ -33942,7 +34644,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_fc_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_fb_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3879] // VPSUBQ Vfv{K}{z},aKq,Hfv,Wfv|B64 + (const void *)&gInstructions[ 3924] // VPSUBQ Vfv{K}{z},aKq,Hfv,Wfv|B64 }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_fb_pp_01_w = @@ -33968,7 +34670,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_fb_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_fa_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3877] // VPSUBD Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 3922] // VPSUBD Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_fa_pp_01_w = @@ -33994,7 +34696,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_fa_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_f9_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3889] // VPSUBW Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3934] // VPSUBW Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_f9_pp = @@ -34011,7 +34713,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_f9_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_f8_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3875] // VPSUBB Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3920] // VPSUBB Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_f8_pp = @@ -34028,7 +34730,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_f8_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_f6_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3777] // VPSADBW Vfv,Hfv,Wfv + (const void *)&gInstructions[ 3822] // VPSADBW Vfv,Hfv,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_f6_pp = @@ -34045,7 +34747,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_f6_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_f5_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3635] // VPMADDWD Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3680] // VPMADDWD Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_f5_pp = @@ -34062,7 +34764,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_f5_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_f4_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3746] // VPMULUDQ Vfv{K}{z},aKq,Hfv,Wfv|B64 + (const void *)&gInstructions[ 3791] // VPMULUDQ Vfv{K}{z},aKq,Hfv,Wfv|B64 }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_f4_pp_01_w = @@ -34088,7 +34790,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_f4_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_f3_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3830] // VPSLLQ Vfv{K}{z},aKq,Hfv,Wdq + (const void *)&gInstructions[ 3875] // VPSLLQ Vfv{K}{z},aKq,Hfv,Wdq }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_f3_pp_01_w = @@ -34114,7 +34816,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_f3_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_f2_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3824] // VPSLLD Vfv{K}{z},aKq,Hfv,Wdq + (const void *)&gInstructions[ 3869] // VPSLLD Vfv{K}{z},aKq,Hfv,Wdq }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_f2_pp_01_w = @@ -34140,7 +34842,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_f2_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_f1_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3839] // VPSLLW Vfv{K}{z},aKq,Hfv,Wdq + (const void *)&gInstructions[ 3884] // VPSLLW Vfv{K}{z},aKq,Hfv,Wdq }; const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_f1_pp = @@ -34157,13 +34859,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_f1_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_ef_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3920] // VPXORQ Vfv{K}{z},aKq,Hfv,Wfv|B64 + (const void *)&gInstructions[ 3965] // VPXORQ Vfv{K}{z},aKq,Hfv,Wfv|B64 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_ef_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3919] // VPXORD Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 3964] // VPXORD Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_ef_pp_01_w = @@ -34189,7 +34891,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_ef_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_ee_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3646] // VPMAXSW Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3691] // VPMAXSW Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_ee_pp = @@ -34206,7 +34908,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_ee_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_ed_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3392] // VPADDSW Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3437] // VPADDSW Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_ed_pp = @@ -34223,7 +34925,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_ed_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_ec_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3390] // VPADDSB Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3435] // VPADDSB Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_ec_pp = @@ -34240,13 +34942,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_ec_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_eb_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3754] // VPORQ Vfv{K}{z},aKq,Hfv,Wfv|B64 + (const void *)&gInstructions[ 3799] // VPORQ Vfv{K}{z},aKq,Hfv,Wfv|B64 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_eb_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3753] // VPORD Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 3798] // VPORD Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_eb_pp_01_w = @@ -34272,7 +34974,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_eb_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_ea_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3660] // VPMINSW Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3705] // VPMINSW Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_ea_pp = @@ -34289,7 +34991,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_ea_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_e9_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3883] // VPSUBSW Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3928] // VPSUBSW Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_e9_pp = @@ -34306,7 +35008,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_e9_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_e8_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3881] // VPSUBSB Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3926] // VPSUBSB Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_e8_pp = @@ -34323,7 +35025,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_e8_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_e7_pp_01_modrmmod_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3285] // VMOVNTDQ Mfv,Vfv + (const void *)&gInstructions[ 3326] // VMOVNTDQ Mfv,Vfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_e7_pp_01_modrmmod_00_w = @@ -34358,7 +35060,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_e7_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_e6_pp_03_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2753] // VCVTPD2DQ Vhv{K}{z},aKq,Wfv|B64{er} + (const void *)&gInstructions[ 2794] // VCVTPD2DQ Vhv{K}{z},aKq,Wfv|B64{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_e6_pp_03_w = @@ -34373,13 +35075,13 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_e6_pp_03_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_e6_pp_02_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2789] // VCVTQQ2PD Vfv{K}{z},aKq,Wfv|B64{er} + (const void *)&gInstructions[ 2830] // VCVTQQ2PD Vfv{K}{z},aKq,Wfv|B64{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_e6_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2729] // VCVTDQ2PD Vfv{K}{z},aKq,Whv|B32 + (const void *)&gInstructions[ 2770] // VCVTDQ2PD Vfv{K}{z},aKq,Whv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_e6_pp_02_w = @@ -34394,7 +35096,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_e6_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_e6_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2816] // VCVTTPD2DQ Vhv{K}{z},aKq,Wfv|B64{sae} + (const void *)&gInstructions[ 2857] // VCVTTPD2DQ Vhv{K}{z},aKq,Wfv|B64{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_e6_pp_01_w = @@ -34420,7 +35122,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_e6_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_e5_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3738] // VPMULHW Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3783] // VPMULHW Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_e5_pp = @@ -34437,7 +35139,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_e5_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_e4_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3736] // VPMULHUW Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3781] // VPMULHUW Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_e4_pp = @@ -34454,7 +35156,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_e4_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_e3_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3410] // VPAVGW Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3455] // VPAVGW Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_e3_pp = @@ -34471,13 +35173,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_e3_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_e2_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3847] // VPSRAQ Vfv{K}{z},aKq,Hfv,Wdq + (const void *)&gInstructions[ 3892] // VPSRAQ Vfv{K}{z},aKq,Hfv,Wdq }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_e2_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3843] // VPSRAD Vfv{K}{z},aKq,Hfv,Wdq + (const void *)&gInstructions[ 3888] // VPSRAD Vfv{K}{z},aKq,Hfv,Wdq }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_e2_pp_01_w = @@ -34503,7 +35205,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_e2_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_e1_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3853] // VPSRAW Vfv{K}{z},aKq,Hfv,Wdq + (const void *)&gInstructions[ 3898] // VPSRAW Vfv{K}{z},aKq,Hfv,Wdq }; const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_e1_pp = @@ -34520,7 +35222,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_e1_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_e0_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3408] // VPAVGB Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3453] // VPAVGB Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_e0_pp = @@ -34537,13 +35239,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_e0_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_df_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3406] // VPANDNQ Vfv{K}{z},aKq,Hfv,Wfv|B64 + (const void *)&gInstructions[ 3451] // VPANDNQ Vfv{K}{z},aKq,Hfv,Wfv|B64 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_df_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3405] // VPANDND Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 3450] // VPANDND Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_df_pp_01_w = @@ -34569,7 +35271,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_df_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_de_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3648] // VPMAXUB Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3693] // VPMAXUB Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_de_pp = @@ -34586,7 +35288,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_de_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_dd_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3396] // VPADDUSW Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3441] // VPADDUSW Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_dd_pp = @@ -34603,7 +35305,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_dd_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_dc_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3394] // VPADDUSB Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3439] // VPADDUSB Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_dc_pp = @@ -34620,13 +35322,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_dc_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_db_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3407] // VPANDQ Vfv{K}{z},aKq,Hfv,Wfv|B64 + (const void *)&gInstructions[ 3452] // VPANDQ Vfv{K}{z},aKq,Hfv,Wfv|B64 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_db_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3403] // VPANDD Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 3448] // VPANDD Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_db_pp_01_w = @@ -34652,7 +35354,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_db_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_da_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3662] // VPMINUB Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3707] // VPMINUB Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_da_pp = @@ -34669,7 +35371,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_da_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_d9_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3887] // VPSUBUSW Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3932] // VPSUBUSW Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_d9_pp = @@ -34686,7 +35388,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_d9_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_d8_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3885] // VPSUBUSB Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3930] // VPSUBUSB Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_d8_pp = @@ -34703,13 +35405,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_d8_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_d6_pp_01_l_00_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3296] // VMOVQ Wq,Vdq + (const void *)&gInstructions[ 3337] // VMOVQ Wq,Vdq }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_d6_pp_01_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3239] // VMOVD Wd,Vdq + (const void *)&gInstructions[ 3280] // VMOVD Wd,Vdq }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_d6_pp_01_l_00_w = @@ -34746,7 +35448,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_d6_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_d5_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3743] // VPMULLW Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3788] // VPMULLW Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_d5_pp = @@ -34763,7 +35465,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_d5_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_d4_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3388] // VPADDQ Vfv{K}{z},aKq,Hfv,Wfv|B64 + (const void *)&gInstructions[ 3433] // VPADDQ Vfv{K}{z},aKq,Hfv,Wfv|B64 }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_d4_pp_01_w = @@ -34789,7 +35491,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_d4_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_d3_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3863] // VPSRLQ Vfv{K}{z},aKq,Hfv,Wdq + (const void *)&gInstructions[ 3908] // VPSRLQ Vfv{K}{z},aKq,Hfv,Wdq }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_d3_pp_01_w = @@ -34815,7 +35517,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_d3_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_d2_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3857] // VPSRLD Vfv{K}{z},aKq,Hfv,Wdq + (const void *)&gInstructions[ 3902] // VPSRLD Vfv{K}{z},aKq,Hfv,Wdq }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_d2_pp_01_w = @@ -34841,7 +35543,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_d2_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_d1_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3872] // VPSRLW Vfv{K}{z},aKq,Hfv,Wdq + (const void *)&gInstructions[ 3917] // VPSRLW Vfv{K}{z},aKq,Hfv,Wdq }; const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_d1_pp = @@ -34858,7 +35560,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_d1_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_c6_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3995] // VSHUFPD Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib + (const void *)&gInstructions[ 4040] // VSHUFPD Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_c6_pp_01_w = @@ -34873,7 +35575,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_c6_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_c6_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3997] // VSHUFPS Vfv{K}{z},aKq,Hfv,Wfv|B32,Ib + (const void *)&gInstructions[ 4042] // VSHUFPS Vfv{K}{z},aKq,Hfv,Wfv|B32,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_c6_pp_00_w = @@ -34899,7 +35601,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_c6_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_c5_pp_01_modrmmod_01_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3567] // VPEXTRW Gy,Udq,Ib + (const void *)&gInstructions[ 3612] // VPEXTRW Gy,Udq,Ib }; const ND_TABLE_EX_L gEvexMap_mmmmm_01_opcode_c5_pp_01_modrmmod_01_l = @@ -34936,7 +35638,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_c5_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_c4_pp_01_modrmmod_01_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3612] // VPINSRW Vdq,Hdq,Rv,Ib + (const void *)&gInstructions[ 3657] // VPINSRW Vdq,Hdq,Rv,Ib }; const ND_TABLE_EX_L gEvexMap_mmmmm_01_opcode_c4_pp_01_modrmmod_01_l = @@ -34953,7 +35655,7 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_01_opcode_c4_pp_01_modrmmod_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_c4_pp_01_modrmmod_00_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3611] // VPINSRW Vdq,Hdq,Mw,Ib + (const void *)&gInstructions[ 3656] // VPINSRW Vdq,Hdq,Mw,Ib }; const ND_TABLE_EX_L gEvexMap_mmmmm_01_opcode_c4_pp_01_modrmmod_00_l = @@ -34990,7 +35692,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_c4_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_c2_pp_03_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2708] // VCMPSD rKq{K},aKq,Hdq,Wsd{sae},Ib + (const void *)&gInstructions[ 2749] // VCMPSD rKq{K},aKq,Hdq,Wsd{sae},Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_c2_pp_03_w = @@ -35005,7 +35707,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_c2_pp_03_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_c2_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2711] // VCMPSS rKq{K},aKq,Hdq,Wss{sae},Ib + (const void *)&gInstructions[ 2752] // VCMPSS rKq{K},aKq,Hdq,Wss{sae},Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_c2_pp_02_w = @@ -35020,7 +35722,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_c2_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_c2_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2703] // VCMPPD rKq{K},aKq,Hfv,Wfv|B64{sae},Ib + (const void *)&gInstructions[ 2744] // VCMPPD rKq{K},aKq,Hfv,Wfv|B64{sae},Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_c2_pp_01_w = @@ -35035,7 +35737,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_c2_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_c2_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2706] // VCMPPS rKq{K},aKq,Hfv,Wfv|B32{sae},Ib + (const void *)&gInstructions[ 2747] // VCMPPS rKq{K},aKq,Hfv,Wfv|B32{sae},Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_c2_pp_00_w = @@ -35735,13 +36437,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_90_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_7f_pp_03_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3256] // VMOVDQU16 Wfv{K}{z},aKq,Vfv + (const void *)&gInstructions[ 3297] // VMOVDQU16 Wfv{K}{z},aKq,Vfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_7f_pp_03_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3262] // VMOVDQU8 Wfv{K}{z},aKq,Vfv + (const void *)&gInstructions[ 3303] // VMOVDQU8 Wfv{K}{z},aKq,Vfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_7f_pp_03_w = @@ -35756,13 +36458,13 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_7f_pp_03_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_7f_pp_02_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3260] // VMOVDQU64 Wfv{K}{z},aKq,Vfv + (const void *)&gInstructions[ 3301] // VMOVDQU64 Wfv{K}{z},aKq,Vfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_7f_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3258] // VMOVDQU32 Wfv{K}{z},aKq,Vfv + (const void *)&gInstructions[ 3299] // VMOVDQU32 Wfv{K}{z},aKq,Vfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_7f_pp_02_w = @@ -35777,13 +36479,13 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_7f_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_7f_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3252] // VMOVDQA64 Wfv{K}{z},aKq,Vfv + (const void *)&gInstructions[ 3293] // VMOVDQA64 Wfv{K}{z},aKq,Vfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_7f_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3250] // VMOVDQA32 Wfv{K}{z},aKq,Vfv + (const void *)&gInstructions[ 3291] // VMOVDQA32 Wfv{K}{z},aKq,Vfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_7f_pp_01_w = @@ -35809,13 +36511,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_7f_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_7e_pp_02_l_00_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3295] // VMOVQ Vdq,Wq + (const void *)&gInstructions[ 3336] // VMOVQ Vdq,Wq }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_7e_pp_02_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3238] // VMOVD Vdq,Wd + (const void *)&gInstructions[ 3279] // VMOVD Vdq,Wd }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_7e_pp_02_l_00_w = @@ -35841,13 +36543,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_01_opcode_7e_pp_02_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_7e_pp_01_l_00_wi_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3294] // VMOVQ Ey,Vdq + (const void *)&gInstructions[ 3335] // VMOVQ Ey,Vdq }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_7e_pp_01_l_00_wi_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3237] // VMOVD Ey,Vdq + (const void *)&gInstructions[ 3278] // VMOVD Ey,Vdq }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_7e_pp_01_l_00_wi = @@ -35884,13 +36586,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_7e_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_7b_pp_03_wi_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2863] // VCVTUSI2SD Vdq,Hdq{er},Ey + (const void *)&gInstructions[ 2904] // VCVTUSI2SD Vdq,Hdq{er},Ey }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_7b_pp_03_wi_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2862] // VCVTUSI2SD Vdq,Hdq,Ey + (const void *)&gInstructions[ 2903] // VCVTUSI2SD Vdq,Hdq,Ey }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_7b_pp_03_wi = @@ -35905,19 +36607,19 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_7b_pp_03_wi = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_7b_pp_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2865] // VCVTUSI2SS Vss,Hss{er},Ey + (const void *)&gInstructions[ 2906] // VCVTUSI2SS Vss,Hss{er},Ey }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_7b_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2759] // VCVTPD2QQ Vfv{K}{z},aKq,Wfv|B64{er} + (const void *)&gInstructions[ 2800] // VCVTPD2QQ Vfv{K}{z},aKq,Wfv|B64{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_7b_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2786] // VCVTPS2QQ Vfv{K}{z},aKq,Whv|B32{er} + (const void *)&gInstructions[ 2827] // VCVTPS2QQ Vfv{K}{z},aKq,Whv|B32{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_7b_pp_01_w = @@ -35943,13 +36645,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_7b_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_7a_pp_03_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2861] // VCVTUQQ2PS Vhv{K}{z},aKq,Wfv|B64{er} + (const void *)&gInstructions[ 2902] // VCVTUQQ2PS Vhv{K}{z},aKq,Wfv|B64{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_7a_pp_03_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2858] // VCVTUDQ2PS Vfv{K}{z},aKq,Wfv|B32{er} + (const void *)&gInstructions[ 2899] // VCVTUDQ2PS Vfv{K}{z},aKq,Wfv|B32{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_7a_pp_03_w = @@ -35964,13 +36666,13 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_7a_pp_03_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_7a_pp_02_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2859] // VCVTUQQ2PD Vfv{K}{z},aKq,Wfv|B64{er} + (const void *)&gInstructions[ 2900] // VCVTUQQ2PD Vfv{K}{z},aKq,Wfv|B64{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_7a_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2856] // VCVTUDQ2PD Vfv{K}{z},aKq,Whv|B32 + (const void *)&gInstructions[ 2897] // VCVTUDQ2PD Vfv{K}{z},aKq,Whv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_7a_pp_02_w = @@ -35985,13 +36687,13 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_7a_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_7a_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2819] // VCVTTPD2QQ Vfv{K}{z},aKq,Wfv|B64{sae} + (const void *)&gInstructions[ 2860] // VCVTTPD2QQ Vfv{K}{z},aKq,Wfv|B64{sae} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_7a_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2838] // VCVTTPS2QQ Vfv{K}{z},aKq,Whv|B32{sae} + (const void *)&gInstructions[ 2879] // VCVTTPS2QQ Vfv{K}{z},aKq,Whv|B32{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_7a_pp_01_w = @@ -36017,25 +36719,25 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_7a_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_79_pp_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2797] // VCVTSD2USI Gy,Wsd{er} + (const void *)&gInstructions[ 2838] // VCVTSD2USI Gy,Wsd{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_79_pp_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2813] // VCVTSS2USI Gy,Wss{er} + (const void *)&gInstructions[ 2854] // VCVTSS2USI Gy,Wss{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_79_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2761] // VCVTPD2UQQ Vfv{K}{z},aKq,Wfv|B64{er} + (const void *)&gInstructions[ 2802] // VCVTPD2UQQ Vfv{K}{z},aKq,Wfv|B64{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_79_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2788] // VCVTPS2UQQ Vfv{K}{z},aKq,Whv|B32{er} + (const void *)&gInstructions[ 2829] // VCVTPS2UQQ Vfv{K}{z},aKq,Whv|B32{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_79_pp_01_w = @@ -36050,13 +36752,13 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_79_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_79_pp_00_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2760] // VCVTPD2UDQ Vhv{K}{z},aKq,Wfv|B64{er} + (const void *)&gInstructions[ 2801] // VCVTPD2UDQ Vhv{K}{z},aKq,Wfv|B64{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_79_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2787] // VCVTPS2UDQ Vfv{K}{z},aKq,Wfv|B32{er} + (const void *)&gInstructions[ 2828] // VCVTPS2UDQ Vfv{K}{z},aKq,Wfv|B32{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_79_pp_00_w = @@ -36082,25 +36784,25 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_79_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_78_pp_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2847] // VCVTTSD2USI Gy,Wsd{sae} + (const void *)&gInstructions[ 2888] // VCVTTSD2USI Gy,Wsd{sae} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_78_pp_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2854] // VCVTTSS2USI Gy,Wss{sae} + (const void *)&gInstructions[ 2895] // VCVTTSS2USI Gy,Wss{sae} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_78_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2823] // VCVTTPD2UQQ Vfv{K}{z},aKq,Wfv|B64{sae} + (const void *)&gInstructions[ 2864] // VCVTTPD2UQQ Vfv{K}{z},aKq,Wfv|B64{sae} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_78_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2842] // VCVTTPS2UQQ Vfv{K}{z},aKq,Whv|B32{sae} + (const void *)&gInstructions[ 2883] // VCVTTPS2UQQ Vfv{K}{z},aKq,Whv|B32{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_78_pp_01_w = @@ -36115,13 +36817,13 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_78_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_78_pp_00_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2821] // VCVTTPD2UDQ Vhv{K}{z},aKq,Wfv|B64{sae} + (const void *)&gInstructions[ 2862] // VCVTTPD2UDQ Vhv{K}{z},aKq,Wfv|B64{sae} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_78_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2840] // VCVTTPS2UDQ Vfv{K}{z},aKq,Wfv|B32{sae} + (const void *)&gInstructions[ 2881] // VCVTTPS2UDQ Vfv{K}{z},aKq,Wfv|B32{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_78_pp_00_w = @@ -36147,7 +36849,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_78_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_76_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3441] // VPCMPEQD rKq{K},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 3486] // VPCMPEQD rKq{K},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_76_pp = @@ -36164,7 +36866,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_76_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_75_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3445] // VPCMPEQW rKq{K},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3490] // VPCMPEQW rKq{K},aKq,Hfv,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_75_pp = @@ -36178,40 +36880,10 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_75_pp = } }; -const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_74_pp_03_w_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2736] // VCVTNE2PH2BF8 Vfv{K}{z},aKq,Hfv,Wfv|B16 -}; - -const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_74_pp_03_w = -{ - ND_ILUT_EX_W, - { - /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_74_pp_03_w_00_leaf, - /* 01 */ (const void *)ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_74_pp_02_w_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2747] // VCVTNEPH2BF8 Vhv{K}{z},aKq,Wfv|B16 -}; - -const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_74_pp_02_w = -{ - ND_ILUT_EX_W, - { - /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_74_pp_02_w_00_leaf, - /* 01 */ (const void *)ND_NULL, - } -}; - const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_74_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3439] // VPCMPEQB rKq{K},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3484] // VPCMPEQB rKq{K},aKq,Hfv,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_74_pp = @@ -36220,21 +36892,21 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_74_pp = { /* 00 */ (const void *)ND_NULL, /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_74_pp_01_leaf, - /* 02 */ (const void *)&gEvexMap_mmmmm_01_opcode_74_pp_02_w, - /* 03 */ (const void *)&gEvexMap_mmmmm_01_opcode_74_pp_03_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, } }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_73_pp_01_modrmreg_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3827] // VPSLLDQ Hfv,Wfv,Ib + (const void *)&gInstructions[ 3872] // VPSLLDQ Hfv,Wfv,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_73_pp_01_modrmreg_06_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3829] // VPSLLQ Hfv{K}{z},aKq,Wfv|B64,Ib + (const void *)&gInstructions[ 3874] // VPSLLQ Hfv{K}{z},aKq,Wfv|B64,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_73_pp_01_modrmreg_06_w = @@ -36249,13 +36921,13 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_73_pp_01_modrmreg_06_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_73_pp_01_modrmreg_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3860] // VPSRLDQ Hfv,Wfv,Ib + (const void *)&gInstructions[ 3905] // VPSRLDQ Hfv,Wfv,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_73_pp_01_modrmreg_02_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3862] // VPSRLQ Hfv{K}{z},aKq,Wfv|B64,Ib + (const void *)&gInstructions[ 3907] // VPSRLQ Hfv{K}{z},aKq,Wfv|B64,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_73_pp_01_modrmreg_02_w = @@ -36296,7 +36968,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_73_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg_06_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3823] // VPSLLD Hfv{K}{z},aKq,Wfv|B32,Ib + (const void *)&gInstructions[ 3868] // VPSLLD Hfv{K}{z},aKq,Wfv|B32,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg_06_w = @@ -36311,13 +36983,13 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg_06_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg_04_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3846] // VPSRAQ Hfv{K}{z},aKq,Wfv|B64,Ib + (const void *)&gInstructions[ 3891] // VPSRAQ Hfv{K}{z},aKq,Wfv|B64,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg_04_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3842] // VPSRAD Hfv{K}{z},aKq,Wfv|B32,Ib + (const void *)&gInstructions[ 3887] // VPSRAD Hfv{K}{z},aKq,Wfv|B32,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg_04_w = @@ -36332,7 +37004,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg_04_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3856] // VPSRLD Hfv{K}{z},aKq,Wfv|B32,Ib + (const void *)&gInstructions[ 3901] // VPSRLD Hfv{K}{z},aKq,Wfv|B32,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg_02_w = @@ -36347,13 +37019,13 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3758] // VPROLQ Hfv{K}{z},aKq,Wfv|B64,Ib + (const void *)&gInstructions[ 3803] // VPROLQ Hfv{K}{z},aKq,Wfv|B64,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3757] // VPROLD Hfv{K}{z},aKq,Wfv|B32,Ib + (const void *)&gInstructions[ 3802] // VPROLD Hfv{K}{z},aKq,Wfv|B32,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg_01_w = @@ -36368,13 +37040,13 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg_00_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3762] // VPRORQ Hfv{K}{z},aKq,Wfv|B64,Ib + (const void *)&gInstructions[ 3807] // VPRORQ Hfv{K}{z},aKq,Wfv|B64,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3761] // VPRORD Hfv{K}{z},aKq,Wfv|B32,Ib + (const void *)&gInstructions[ 3806] // VPRORD Hfv{K}{z},aKq,Wfv|B32,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg_00_w = @@ -36415,19 +37087,19 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_72_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_71_pp_01_modrmreg_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3838] // VPSLLW Hfv{K}{z},aKq,Wfv,Ib + (const void *)&gInstructions[ 3883] // VPSLLW Hfv{K}{z},aKq,Wfv,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_71_pp_01_modrmreg_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3852] // VPSRAW Hfv{K}{z},aKq,Wfv,Ib + (const void *)&gInstructions[ 3897] // VPSRAW Hfv{K}{z},aKq,Wfv,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_71_pp_01_modrmreg_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3871] // VPSRLW Hfv{K}{z},aKq,Wfv,Ib + (const void *)&gInstructions[ 3916] // VPSRLW Hfv{K}{z},aKq,Wfv,Ib }; const ND_TABLE_MODRM_REG gEvexMap_mmmmm_01_opcode_71_pp_01_modrmreg = @@ -36459,19 +37131,19 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_71_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_70_pp_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3818] // VPSHUFLW Vfv{K}{z},aKq,Wfv,Ib + (const void *)&gInstructions[ 3863] // VPSHUFLW Vfv{K}{z},aKq,Wfv,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_70_pp_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3816] // VPSHUFHW Vfv{K}{z},aKq,Wfv,Ib + (const void *)&gInstructions[ 3861] // VPSHUFHW Vfv{K}{z},aKq,Wfv,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_70_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3814] // VPSHUFD Vfv{K}{z},aKq,Wfv|B32,Ib + (const void *)&gInstructions[ 3859] // VPSHUFD Vfv{K}{z},aKq,Wfv|B32,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_70_pp_01_w = @@ -36497,13 +37169,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_70_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_6f_pp_03_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3255] // VMOVDQU16 Vfv{K}{z},aKq,Wfv + (const void *)&gInstructions[ 3296] // VMOVDQU16 Vfv{K}{z},aKq,Wfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_6f_pp_03_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3261] // VMOVDQU8 Vfv{K}{z},aKq,Wfv + (const void *)&gInstructions[ 3302] // VMOVDQU8 Vfv{K}{z},aKq,Wfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_6f_pp_03_w = @@ -36518,13 +37190,13 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_6f_pp_03_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_6f_pp_02_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3259] // VMOVDQU64 Vfv{K}{z},aKq,Wfv + (const void *)&gInstructions[ 3300] // VMOVDQU64 Vfv{K}{z},aKq,Wfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_6f_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3257] // VMOVDQU32 Vfv{K}{z},aKq,Wfv + (const void *)&gInstructions[ 3298] // VMOVDQU32 Vfv{K}{z},aKq,Wfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_6f_pp_02_w = @@ -36539,13 +37211,13 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_6f_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_6f_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3251] // VMOVDQA64 Vfv{K}{z},aKq,Wfv + (const void *)&gInstructions[ 3292] // VMOVDQA64 Vfv{K}{z},aKq,Wfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_6f_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3249] // VMOVDQA32 Vfv{K}{z},aKq,Wfv + (const void *)&gInstructions[ 3290] // VMOVDQA32 Vfv{K}{z},aKq,Wfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_6f_pp_01_w = @@ -36571,13 +37243,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_6f_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_6e_pp_01_l_00_wi_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3293] // VMOVQ Vdq,Eq + (const void *)&gInstructions[ 3334] // VMOVQ Vdq,Eq }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_6e_pp_01_l_00_wi_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3236] // VMOVD Vdq,Ed + (const void *)&gInstructions[ 3277] // VMOVD Vdq,Ed }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_6e_pp_01_l_00_wi = @@ -36614,7 +37286,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_6e_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_6d_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3906] // VPUNPCKHQDQ Vfv{K}{z},aKq,Hfv,Wfv|B64 + (const void *)&gInstructions[ 3951] // VPUNPCKHQDQ Vfv{K}{z},aKq,Hfv,Wfv|B64 }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_6d_pp_01_w = @@ -36640,7 +37312,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_6d_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_6c_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3914] // VPUNPCKLQDQ Vfv{K}{z},aKq,Hfv,Wfv|B64 + (const void *)&gInstructions[ 3959] // VPUNPCKLQDQ Vfv{K}{z},aKq,Hfv,Wfv|B64 }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_6c_pp_01_w = @@ -36666,7 +37338,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_6c_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_6b_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3376] // VPACKSSDW Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 3421] // VPACKSSDW Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_6b_pp_01_w = @@ -36692,7 +37364,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_6b_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_6a_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3904] // VPUNPCKHDQ Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 3949] // VPUNPCKHDQ Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_6a_pp_01_w = @@ -36718,7 +37390,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_6a_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_69_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3908] // VPUNPCKHWD Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3953] // VPUNPCKHWD Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_69_pp = @@ -36735,7 +37407,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_69_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_68_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3902] // VPUNPCKHBW Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3947] // VPUNPCKHBW Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_68_pp = @@ -36752,7 +37424,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_68_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_67_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3382] // VPACKUSWB Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3427] // VPACKUSWB Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_67_pp = @@ -36769,7 +37441,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_67_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_66_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3451] // VPCMPGTD rKq{K},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 3496] // VPCMPGTD rKq{K},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_66_pp_01_w = @@ -36795,7 +37467,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_66_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_65_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3455] // VPCMPGTW rKq{K},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3500] // VPCMPGTW rKq{K},aKq,Hfv,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_65_pp = @@ -36812,7 +37484,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_65_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_64_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3449] // VPCMPGTB rKq{K},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3494] // VPCMPGTB rKq{K},aKq,Hfv,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_64_pp = @@ -36829,7 +37501,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_64_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_63_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3378] // VPACKSSWB Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3423] // VPACKSSWB Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_63_pp = @@ -36846,7 +37518,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_63_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_62_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3912] // VPUNPCKLDQ Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 3957] // VPUNPCKLDQ Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_62_pp_01_w = @@ -36872,7 +37544,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_62_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_61_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3916] // VPUNPCKLWD Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3961] // VPUNPCKLWD Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_61_pp = @@ -36889,7 +37561,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_61_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_60_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3910] // VPUNPCKLBW Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3955] // VPUNPCKLBW Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_60_pp = @@ -36906,7 +37578,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_60_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5f_pp_03_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3196] // VMAXSD Vdq{K}{z},aKq,Hdq,Wsd{sae} + (const void *)&gInstructions[ 3237] // VMAXSD Vdq{K}{z},aKq,Hdq,Wsd{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5f_pp_03_w = @@ -36921,7 +37593,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5f_pp_03_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5f_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3199] // VMAXSS Vdq{K}{z},aKq,Hdq,Wss{sae} + (const void *)&gInstructions[ 3240] // VMAXSS Vdq{K}{z},aKq,Hdq,Wss{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5f_pp_02_w = @@ -36936,7 +37608,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5f_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5f_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3191] // VMAXPD Vfv{K}{z},aKq,Hfv,Wfv|B64{sae} + (const void *)&gInstructions[ 3232] // VMAXPD Vfv{K}{z},aKq,Hfv,Wfv|B64{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5f_pp_01_w = @@ -36951,7 +37623,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5f_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5f_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3194] // VMAXPS Vfv{K}{z},aKq,Hfv,Wfv|B32{sae} + (const void *)&gInstructions[ 3235] // VMAXPS Vfv{K}{z},aKq,Hfv,Wfv|B32{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5f_pp_00_w = @@ -36977,7 +37649,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_5f_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5e_pp_03_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2875] // VDIVSD Vdq{K}{z},aKq,Hdq,Wsd{er} + (const void *)&gInstructions[ 2916] // VDIVSD Vdq{K}{z},aKq,Hdq,Wsd{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5e_pp_03_w = @@ -36992,7 +37664,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5e_pp_03_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5e_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2878] // VDIVSS Vdq{K}{z},aKq,Hdq,Wss{er} + (const void *)&gInstructions[ 2919] // VDIVSS Vdq{K}{z},aKq,Hdq,Wss{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5e_pp_02_w = @@ -37007,7 +37679,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5e_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5e_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2870] // VDIVPD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} + (const void *)&gInstructions[ 2911] // VDIVPD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5e_pp_01_w = @@ -37022,7 +37694,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5e_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5e_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2873] // VDIVPS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} + (const void *)&gInstructions[ 2914] // VDIVPS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5e_pp_00_w = @@ -37048,7 +37720,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_5e_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5d_pp_03_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3219] // VMINSD Vdq{K}{z},aKq,Hdq,Wsd{sae} + (const void *)&gInstructions[ 3260] // VMINSD Vdq{K}{z},aKq,Hdq,Wsd{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5d_pp_03_w = @@ -37063,7 +37735,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5d_pp_03_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5d_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3222] // VMINSS Vdq{K}{z},aKq,Hdq,Wss{sae} + (const void *)&gInstructions[ 3263] // VMINSS Vdq{K}{z},aKq,Hdq,Wss{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5d_pp_02_w = @@ -37078,7 +37750,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5d_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5d_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3214] // VMINPD Vfv{K}{z},aKq,Hfv,Wfv|B64{sae} + (const void *)&gInstructions[ 3255] // VMINPD Vfv{K}{z},aKq,Hfv,Wfv|B64{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5d_pp_01_w = @@ -37093,7 +37765,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5d_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5d_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3217] // VMINPS Vfv{K}{z},aKq,Hfv,Wfv|B32{sae} + (const void *)&gInstructions[ 3258] // VMINPS Vfv{K}{z},aKq,Hfv,Wfv|B32{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5d_pp_00_w = @@ -37119,7 +37791,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_5d_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5c_pp_03_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4022] // VSUBSD Vdq{K}{z},aKq,Hdq,Wsd{er} + (const void *)&gInstructions[ 4069] // VSUBSD Vdq{K}{z},aKq,Hdq,Wsd{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5c_pp_03_w = @@ -37134,7 +37806,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5c_pp_03_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5c_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4025] // VSUBSS Vdq{K}{z},aKq,Hdq,Wss{er} + (const void *)&gInstructions[ 4072] // VSUBSS Vdq{K}{z},aKq,Hdq,Wss{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5c_pp_02_w = @@ -37149,7 +37821,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5c_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5c_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4017] // VSUBPD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} + (const void *)&gInstructions[ 4064] // VSUBPD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5c_pp_01_w = @@ -37164,7 +37836,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5c_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5c_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4020] // VSUBPS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} + (const void *)&gInstructions[ 4067] // VSUBPS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5c_pp_00_w = @@ -37190,7 +37862,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_5c_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5b_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2833] // VCVTTPS2DQ Vfv{K}{z},aKq,Wfv|B32{sae} + (const void *)&gInstructions[ 2874] // VCVTTPS2DQ Vfv{K}{z},aKq,Wfv|B32{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5b_pp_02_w = @@ -37205,7 +37877,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5b_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5b_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2775] // VCVTPS2DQ Vfv{K}{z},aKq,Wfv|B32{er} + (const void *)&gInstructions[ 2816] // VCVTPS2DQ Vfv{K}{z},aKq,Wfv|B32{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5b_pp_01_w = @@ -37220,13 +37892,13 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5b_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5b_pp_00_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2791] // VCVTQQ2PS Vhv{K}{z},aKq,Wfv|B64{er} + (const void *)&gInstructions[ 2832] // VCVTQQ2PS Vhv{K}{z},aKq,Wfv|B64{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5b_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2733] // VCVTDQ2PS Vfv{K}{z},aKq,Wfv|B32{er} + (const void *)&gInstructions[ 2774] // VCVTDQ2PS Vfv{K}{z},aKq,Wfv|B32{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5b_pp_00_w = @@ -37252,7 +37924,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_5b_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5a_pp_03_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2795] // VCVTSD2SS Vdq{K}{z},aKq,Hdq,Wsd{er} + (const void *)&gInstructions[ 2836] // VCVTSD2SS Vdq{K}{z},aKq,Hdq,Wsd{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5a_pp_03_w = @@ -37267,7 +37939,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5a_pp_03_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5a_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2808] // VCVTSS2SD Vdq{K}{z},aKq,Hdq,Wss{sae} + (const void *)&gInstructions[ 2849] // VCVTSS2SD Vdq{K}{z},aKq,Hdq,Wss{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5a_pp_02_w = @@ -37282,7 +37954,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5a_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5a_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2756] // VCVTPD2PS Vhv{K}{z},aKq,Wfv|B64{er} + (const void *)&gInstructions[ 2797] // VCVTPD2PS Vhv{K}{z},aKq,Wfv|B64{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5a_pp_01_w = @@ -37297,7 +37969,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5a_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5a_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2779] // VCVTPS2PD Vfv{K}{z},aKq,Whv|B32{sae} + (const void *)&gInstructions[ 2820] // VCVTPS2PD Vfv{K}{z},aKq,Whv|B32{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5a_pp_00_w = @@ -37323,7 +37995,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_5a_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_59_pp_03_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3353] // VMULSD Vdq{K}{z},aKq,Hdq,Wsd{er} + (const void *)&gInstructions[ 3398] // VMULSD Vdq{K}{z},aKq,Hdq,Wsd{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_59_pp_03_w = @@ -37338,7 +38010,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_59_pp_03_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_59_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3356] // VMULSS Vdq{K}{z},aKq,Hdq,Wss{er} + (const void *)&gInstructions[ 3401] // VMULSS Vdq{K}{z},aKq,Hdq,Wss{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_59_pp_02_w = @@ -37353,7 +38025,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_59_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_59_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3348] // VMULPD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} + (const void *)&gInstructions[ 3393] // VMULPD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_59_pp_01_w = @@ -37368,7 +38040,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_59_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_59_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3351] // VMULPS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} + (const void *)&gInstructions[ 3396] // VMULPS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_59_pp_00_w = @@ -37394,7 +38066,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_59_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_58_pp_03_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2651] // VADDSD Vdq{K}{z},aKq,Hdq,Wsd{er} + (const void *)&gInstructions[ 2692] // VADDSD Vdq{K}{z},aKq,Hdq,Wsd{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_58_pp_03_w = @@ -37409,7 +38081,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_58_pp_03_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_58_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2654] // VADDSS Vdq{K}{z},aKq,Hdq,Wss{er} + (const void *)&gInstructions[ 2695] // VADDSS Vdq{K}{z},aKq,Hdq,Wss{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_58_pp_02_w = @@ -37424,7 +38096,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_58_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_58_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2646] // VADDPD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} + (const void *)&gInstructions[ 2687] // VADDPD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_58_pp_01_w = @@ -37439,7 +38111,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_58_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_58_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2649] // VADDPS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} + (const void *)&gInstructions[ 2690] // VADDPS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_58_pp_00_w = @@ -37465,7 +38137,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_58_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_57_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4045] // VXORPD Vfv{K}{z},aKq,Hfv,Wfv|B64 + (const void *)&gInstructions[ 4092] // VXORPD Vfv{K}{z},aKq,Hfv,Wfv|B64 }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_57_pp_01_w = @@ -37480,7 +38152,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_57_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_57_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4047] // VXORPS Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 4094] // VXORPS Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_57_pp_00_w = @@ -37506,7 +38178,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_57_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_56_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3361] // VORPD Vfv{K}{z},aKq,Hfv,Wfv|B64 + (const void *)&gInstructions[ 3406] // VORPD Vfv{K}{z},aKq,Hfv,Wfv|B64 }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_56_pp_01_w = @@ -37521,7 +38193,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_56_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_56_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3363] // VORPS Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 3408] // VORPS Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_56_pp_00_w = @@ -37547,7 +38219,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_56_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_55_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2670] // VANDNPD Vfv{K}{z},aKq,Hfv,Wfv|B64 + (const void *)&gInstructions[ 2711] // VANDNPD Vfv{K}{z},aKq,Hfv,Wfv|B64 }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_55_pp_01_w = @@ -37562,7 +38234,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_55_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_55_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2672] // VANDNPS Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 2713] // VANDNPS Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_55_pp_00_w = @@ -37588,7 +38260,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_55_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_54_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2674] // VANDPD Vfv{K}{z},aKq,Hfv,Wfv|B64 + (const void *)&gInstructions[ 2715] // VANDPD Vfv{K}{z},aKq,Hfv,Wfv|B64 }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_54_pp_01_w = @@ -37603,7 +38275,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_54_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_54_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2676] // VANDPS Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 2717] // VANDPS Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_54_pp_00_w = @@ -37629,7 +38301,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_54_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_51_pp_03_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4010] // VSQRTSD Vdq{K}{z},aKq,Hdq,Wsd{er} + (const void *)&gInstructions[ 4057] // VSQRTSD Vdq{K}{z},aKq,Hdq,Wsd{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_51_pp_03_w = @@ -37644,7 +38316,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_51_pp_03_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_51_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4013] // VSQRTSS Vdq{K}{z},aKq,Hdq,Wss{er} + (const void *)&gInstructions[ 4060] // VSQRTSS Vdq{K}{z},aKq,Hdq,Wss{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_51_pp_02_w = @@ -37659,7 +38331,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_51_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_51_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4005] // VSQRTPD Vfv{K}{z},aKq,Wfv|B64{er} + (const void *)&gInstructions[ 4052] // VSQRTPD Vfv{K}{z},aKq,Wfv|B64{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_51_pp_01_w = @@ -37674,7 +38346,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_51_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_51_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4008] // VSQRTPS Vfv{K}{z},aKq,Wfv|B32{er} + (const void *)&gInstructions[ 4055] // VSQRTPS Vfv{K}{z},aKq,Wfv|B32{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_51_pp_00_w = @@ -37697,62 +38369,40 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_51_pp = } }; -const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_2f_pp_03_l_00_w_00_leaf = +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_2f_pp_03_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2723] // VCOMXSS Vdq,Wss{sae} + (const void *)&gInstructions[ 2762] // VCOMXSD Vdq,Wsd{sae} }; -const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_2f_pp_03_l_00_w = +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_2f_pp_03_w = { ND_ILUT_EX_W, { - /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_2f_pp_03_l_00_w_00_leaf, - /* 01 */ (const void *)ND_NULL, - } -}; - -const ND_TABLE_EX_L gEvexMap_mmmmm_01_opcode_2f_pp_03_l = -{ - ND_ILUT_EX_L, - { - /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_2f_pp_03_l_00_w, - /* 01 */ (const void *)ND_NULL, - /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)ND_NULL, + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_2f_pp_03_w_01_leaf, } }; -const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_2f_pp_02_l_00_w_01_leaf = +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_2f_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2721] // VCOMXSD Vdq,Wsd{sae} + (const void *)&gInstructions[ 2764] // VCOMXSS Vdq,Wss{sae} }; -const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_2f_pp_02_l_00_w = +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_2f_pp_02_w = { ND_ILUT_EX_W, { - /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_2f_pp_02_l_00_w_01_leaf, - } -}; - -const ND_TABLE_EX_L gEvexMap_mmmmm_01_opcode_2f_pp_02_l = -{ - ND_ILUT_EX_L, - { - /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_2f_pp_02_l_00_w, + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_2f_pp_02_w_00_leaf, /* 01 */ (const void *)ND_NULL, - /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)ND_NULL, } }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_2f_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2713] // VCOMISD Vdq,Wsd{sae} + (const void *)&gInstructions[ 2754] // VCOMISD Vdq,Wsd{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_2f_pp_01_w = @@ -37767,7 +38417,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_2f_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_2f_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2716] // VCOMISS Vdq,Wss{sae} + (const void *)&gInstructions[ 2757] // VCOMISS Vdq,Wss{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_2f_pp_00_w = @@ -37785,67 +38435,45 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_2f_pp = { /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_2f_pp_00_w, /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_2f_pp_01_w, - /* 02 */ (const void *)&gEvexMap_mmmmm_01_opcode_2f_pp_02_l, - /* 03 */ (const void *)&gEvexMap_mmmmm_01_opcode_2f_pp_03_l, + /* 02 */ (const void *)&gEvexMap_mmmmm_01_opcode_2f_pp_02_w, + /* 03 */ (const void *)&gEvexMap_mmmmm_01_opcode_2f_pp_03_w, } }; -const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_2e_pp_03_l_00_w_00_leaf = +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_2e_pp_03_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4036] // VUCOMXSS Vdq,Wss{sae} + (const void *)&gInstructions[ 4081] // VUCOMXSD Vdq,Wsd{sae} }; -const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_2e_pp_03_l_00_w = +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_2e_pp_03_w = { ND_ILUT_EX_W, { - /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_2e_pp_03_l_00_w_00_leaf, - /* 01 */ (const void *)ND_NULL, - } -}; - -const ND_TABLE_EX_L gEvexMap_mmmmm_01_opcode_2e_pp_03_l = -{ - ND_ILUT_EX_L, - { - /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_2e_pp_03_l_00_w, - /* 01 */ (const void *)ND_NULL, - /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)ND_NULL, + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_2e_pp_03_w_01_leaf, } }; -const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_2e_pp_02_l_00_w_01_leaf = +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_2e_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4034] // VUCOMXSD Vdq,Wsd{sae} + (const void *)&gInstructions[ 4083] // VUCOMXSS Vdq,Wss{sae} }; -const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_2e_pp_02_l_00_w = +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_2e_pp_02_w = { ND_ILUT_EX_W, { - /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_2e_pp_02_l_00_w_01_leaf, - } -}; - -const ND_TABLE_EX_L gEvexMap_mmmmm_01_opcode_2e_pp_02_l = -{ - ND_ILUT_EX_L, - { - /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_2e_pp_02_l_00_w, + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_2e_pp_02_w_00_leaf, /* 01 */ (const void *)ND_NULL, - /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)ND_NULL, } }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_2e_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4029] // VUCOMISD Vdq,Wsd{sae} + (const void *)&gInstructions[ 4076] // VUCOMISD Vdq,Wsd{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_2e_pp_01_w = @@ -37860,7 +38488,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_2e_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_2e_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4032] // VUCOMISS Vdq,Wss{sae} + (const void *)&gInstructions[ 4079] // VUCOMISS Vdq,Wss{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_2e_pp_00_w = @@ -37878,21 +38506,21 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_2e_pp = { /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_2e_pp_00_w, /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_2e_pp_01_w, - /* 02 */ (const void *)&gEvexMap_mmmmm_01_opcode_2e_pp_02_l, - /* 03 */ (const void *)&gEvexMap_mmmmm_01_opcode_2e_pp_03_l, + /* 02 */ (const void *)&gEvexMap_mmmmm_01_opcode_2e_pp_02_w, + /* 03 */ (const void *)&gEvexMap_mmmmm_01_opcode_2e_pp_03_w, } }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_2d_pp_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2793] // VCVTSD2SI Gy,Wsd{er} + (const void *)&gInstructions[ 2834] // VCVTSD2SI Gy,Wsd{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_2d_pp_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2811] // VCVTSS2SI Gy,Wss{er} + (const void *)&gInstructions[ 2852] // VCVTSS2SI Gy,Wss{er} }; const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_2d_pp = @@ -37909,13 +38537,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_2d_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_2c_pp_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2844] // VCVTTSD2SI Gy,Wsd{sae} + (const void *)&gInstructions[ 2885] // VCVTTSD2SI Gy,Wsd{sae} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_2c_pp_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2851] // VCVTTSS2SI Gy,Wss{sae} + (const void *)&gInstructions[ 2892] // VCVTTSS2SI Gy,Wss{sae} }; const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_2c_pp = @@ -37932,7 +38560,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_2c_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_2b_pp_01_modrmmod_00_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3289] // VMOVNTPD Mfv,Vfv + (const void *)&gInstructions[ 3330] // VMOVNTPD Mfv,Vfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_2b_pp_01_modrmmod_00_w = @@ -37956,7 +38584,7 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_01_opcode_2b_pp_01_modrmmod = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_2b_pp_00_modrmmod_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3291] // VMOVNTPS Mfv,Vfv + (const void *)&gInstructions[ 3332] // VMOVNTPS Mfv,Vfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_2b_pp_00_modrmmod_00_w = @@ -37991,13 +38619,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_2b_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_2a_pp_03_wi_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2803] // VCVTSI2SD Vdq,Hdq{er},Ey + (const void *)&gInstructions[ 2844] // VCVTSI2SD Vdq,Hdq{er},Ey }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_2a_pp_03_wi_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2802] // VCVTSI2SD Vdq,Hdq,Ey + (const void *)&gInstructions[ 2843] // VCVTSI2SD Vdq,Hdq,Ey }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_2a_pp_03_wi = @@ -38012,7 +38640,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_2a_pp_03_wi = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_2a_pp_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2806] // VCVTSI2SS Vdq,Hdq{er},Ey + (const void *)&gInstructions[ 2847] // VCVTSI2SS Vdq,Hdq{er},Ey }; const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_2a_pp = @@ -38029,7 +38657,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_2a_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_29_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3229] // VMOVAPD Wfv{K}{z},aKq,Vfv + (const void *)&gInstructions[ 3270] // VMOVAPD Wfv{K}{z},aKq,Vfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_29_pp_01_w = @@ -38044,7 +38672,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_29_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_29_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3233] // VMOVAPS Wfv{K}{z},aKq,Vfv + (const void *)&gInstructions[ 3274] // VMOVAPS Wfv{K}{z},aKq,Vfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_29_pp_00_w = @@ -38070,7 +38698,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_29_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_28_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3228] // VMOVAPD Vfv{K}{z},aKq,Wfv + (const void *)&gInstructions[ 3269] // VMOVAPD Vfv{K}{z},aKq,Wfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_28_pp_01_w = @@ -38085,7 +38713,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_28_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_28_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3232] // VMOVAPS Vfv{K}{z},aKq,Wfv + (const void *)&gInstructions[ 3273] // VMOVAPS Vfv{K}{z},aKq,Wfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_28_pp_00_w = @@ -38111,7 +38739,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_28_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_17_pp_01_modrmmod_00_l_00_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3266] // VMOVHPD Mq,Vdq + (const void *)&gInstructions[ 3307] // VMOVHPD Mq,Vdq }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_17_pp_01_modrmmod_00_l_00_w = @@ -38146,7 +38774,7 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_01_opcode_17_pp_01_modrmmod = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_17_pp_00_modrmmod_00_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3270] // VMOVHPS Mq,Vdq + (const void *)&gInstructions[ 3311] // VMOVHPS Mq,Vdq }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_17_pp_00_modrmmod_00_l_00_w = @@ -38192,7 +38820,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_17_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_16_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3313] // VMOVSHDUP Vfv{K}{z},aKq,Wfv + (const void *)&gInstructions[ 3358] // VMOVSHDUP Vfv{K}{z},aKq,Wfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_16_pp_02_w = @@ -38207,7 +38835,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_16_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_16_pp_01_modrmmod_00_l_00_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3265] // VMOVHPD Vdq,Hdq,Mq + (const void *)&gInstructions[ 3306] // VMOVHPD Vdq,Hdq,Mq }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_16_pp_01_modrmmod_00_l_00_w = @@ -38242,7 +38870,7 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_01_opcode_16_pp_01_modrmmod = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_16_pp_00_modrmmod_01_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3273] // VMOVLHPS Vdq,Hdq,Udq + (const void *)&gInstructions[ 3314] // VMOVLHPS Vdq,Hdq,Udq }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_16_pp_00_modrmmod_01_l_00_w = @@ -38268,7 +38896,7 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_01_opcode_16_pp_00_modrmmod_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_16_pp_00_modrmmod_00_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3269] // VMOVHPS Vdq,Hdq,Mq + (const void *)&gInstructions[ 3310] // VMOVHPS Vdq,Hdq,Mq }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_16_pp_00_modrmmod_00_l_00_w = @@ -38314,7 +38942,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_16_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_15_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4037] // VUNPCKHPD Vfv{K}{z},aKq,Hfv,Wfv|B64 + (const void *)&gInstructions[ 4084] // VUNPCKHPD Vfv{K}{z},aKq,Hfv,Wfv|B64 }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_15_pp_01_w = @@ -38329,7 +38957,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_15_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_15_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4039] // VUNPCKHPS Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 4086] // VUNPCKHPS Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_15_pp_00_w = @@ -38355,7 +38983,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_15_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_14_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4041] // VUNPCKLPD Vfv{K}{z},aKq,Hfv,Wfv|B64 + (const void *)&gInstructions[ 4088] // VUNPCKLPD Vfv{K}{z},aKq,Hfv,Wfv|B64 }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_14_pp_01_w = @@ -38370,7 +38998,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_14_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_14_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4043] // VUNPCKLPS Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 4090] // VUNPCKLPS Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_14_pp_00_w = @@ -38396,7 +39024,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_14_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_13_pp_01_modrmmod_00_l_00_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3276] // VMOVLPD Mq,Vdq + (const void *)&gInstructions[ 3317] // VMOVLPD Mq,Vdq }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_13_pp_01_modrmmod_00_l_00_w = @@ -38431,7 +39059,7 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_01_opcode_13_pp_01_modrmmod = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_13_pp_00_modrmmod_00_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3280] // VMOVLPS Mq,Vdq + (const void *)&gInstructions[ 3321] // VMOVLPS Mq,Vdq }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_13_pp_00_modrmmod_00_l_00_w = @@ -38477,7 +39105,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_13_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_12_pp_03_l_02_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3244] // VMOVDDUP Voq{K}{z},aKq,Woq + (const void *)&gInstructions[ 3285] // VMOVDDUP Voq{K}{z},aKq,Woq }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_12_pp_03_l_02_w = @@ -38492,7 +39120,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_12_pp_03_l_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_12_pp_03_l_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3243] // VMOVDDUP Vqq{K}{z},aKq,Wqq + (const void *)&gInstructions[ 3284] // VMOVDDUP Vqq{K}{z},aKq,Wqq }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_12_pp_03_l_01_w = @@ -38507,7 +39135,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_12_pp_03_l_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_12_pp_03_l_00_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3242] // VMOVDDUP Vdq{K}{z},aKq,Wq + (const void *)&gInstructions[ 3283] // VMOVDDUP Vdq{K}{z},aKq,Wq }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_12_pp_03_l_00_w = @@ -38533,7 +39161,7 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_01_opcode_12_pp_03_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_12_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3315] // VMOVSLDUP Vfv{K}{z},aKq,Wfv + (const void *)&gInstructions[ 3360] // VMOVSLDUP Vfv{K}{z},aKq,Wfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_12_pp_02_w = @@ -38548,7 +39176,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_12_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_12_pp_01_modrmmod_00_l_00_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3275] // VMOVLPD Vdq,Hdq,Mq + (const void *)&gInstructions[ 3316] // VMOVLPD Vdq,Hdq,Mq }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_12_pp_01_modrmmod_00_l_00_w = @@ -38583,7 +39211,7 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_01_opcode_12_pp_01_modrmmod = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_12_pp_00_modrmmod_01_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3263] // VMOVHLPS Vdq,Hdq,Udq + (const void *)&gInstructions[ 3304] // VMOVHLPS Vdq,Hdq,Udq }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_12_pp_00_modrmmod_01_l_00_w = @@ -38609,7 +39237,7 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_01_opcode_12_pp_00_modrmmod_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_12_pp_00_modrmmod_00_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3279] // VMOVLPS Vdq,Hdq,Mq + (const void *)&gInstructions[ 3320] // VMOVLPS Vdq,Hdq,Mq }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_12_pp_00_modrmmod_00_l_00_w = @@ -38655,7 +39283,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_12_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_11_pp_03_modrmmod_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3304] // VMOVSD Udq{K}{z},aKq,Hdq,Vdq + (const void *)&gInstructions[ 3349] // VMOVSD Udq{K}{z},aKq,Hdq,Vdq }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_11_pp_03_modrmmod_01_w = @@ -38670,7 +39298,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_11_pp_03_modrmmod_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_11_pp_03_modrmmod_00_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3303] // VMOVSD Msd{K},aKq,Vdq + (const void *)&gInstructions[ 3348] // VMOVSD Msd{K},aKq,Vdq }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_11_pp_03_modrmmod_00_w = @@ -38694,7 +39322,7 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_01_opcode_11_pp_03_modrmmod = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_11_pp_02_modrmmod_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3320] // VMOVSS Udq{K}{z},aKq,Hdq,Vdq + (const void *)&gInstructions[ 3365] // VMOVSS Udq{K}{z},aKq,Hdq,Vdq }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_11_pp_02_modrmmod_01_w = @@ -38709,7 +39337,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_11_pp_02_modrmmod_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_11_pp_02_modrmmod_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3319] // VMOVSS Mss{K},aKq,Vdq + (const void *)&gInstructions[ 3364] // VMOVSS Mss{K},aKq,Vdq }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_11_pp_02_modrmmod_00_w = @@ -38733,7 +39361,7 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_01_opcode_11_pp_02_modrmmod = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_11_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3326] // VMOVUPD Wfv{K}{z},aKq,Vfv + (const void *)&gInstructions[ 3371] // VMOVUPD Wfv{K}{z},aKq,Vfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_11_pp_01_w = @@ -38748,7 +39376,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_11_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_11_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3330] // VMOVUPS Wfv{K}{z},aKq,Vfv + (const void *)&gInstructions[ 3375] // VMOVUPS Wfv{K}{z},aKq,Vfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_11_pp_00_w = @@ -38774,7 +39402,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_11_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_10_pp_03_modrmmod_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3302] // VMOVSD Vdq{K}{z},aKq,Hdq,Udq + (const void *)&gInstructions[ 3347] // VMOVSD Vdq{K}{z},aKq,Hdq,Udq }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_10_pp_03_modrmmod_01_w = @@ -38789,7 +39417,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_10_pp_03_modrmmod_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_10_pp_03_modrmmod_00_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3301] // VMOVSD Vdq{K}{z},aKq,Msd + (const void *)&gInstructions[ 3346] // VMOVSD Vdq{K}{z},aKq,Msd }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_10_pp_03_modrmmod_00_w = @@ -38813,7 +39441,7 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_01_opcode_10_pp_03_modrmmod = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_10_pp_02_modrmmod_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3318] // VMOVSS Vdq{K}{z},aKq,Hdq,Udq + (const void *)&gInstructions[ 3363] // VMOVSS Vdq{K}{z},aKq,Hdq,Udq }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_10_pp_02_modrmmod_01_w = @@ -38828,7 +39456,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_10_pp_02_modrmmod_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_10_pp_02_modrmmod_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3317] // VMOVSS Vdq{K}{z},aKq,Mss + (const void *)&gInstructions[ 3362] // VMOVSS Vdq{K}{z},aKq,Mss }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_10_pp_02_modrmmod_00_w = @@ -38852,7 +39480,7 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_01_opcode_10_pp_02_modrmmod = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_10_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3325] // VMOVUPD Vfv{K}{z},aKq,Wfv + (const void *)&gInstructions[ 3370] // VMOVUPD Vfv{K}{z},aKq,Wfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_10_pp_01_w = @@ -38867,7 +39495,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_10_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_10_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3329] // VMOVUPS Vfv{K}{z},aKq,Wfv + (const void *)&gInstructions[ 3374] // VMOVUPS Vfv{K}{z},aKq,Wfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_10_pp_00_w = diff --git a/bddisasm/include/bdx86_table_root.h b/bddisasm/include/bdx86_table_root.h index 2c356a9..8e70711 100644 --- a/bddisasm/include/bdx86_table_root.h +++ b/bddisasm/include/bdx86_table_root.h @@ -13,7 +13,7 @@ const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ff_modrmreg_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1965] // PUSH Ev + (const void *)&gInstructions[ 1969] // PUSH Ev }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ff_modrmreg_05_modrmmod_00_leaf = @@ -115,7 +115,7 @@ const ND_TABLE_MODRM_REG gLegacyMap_opcode_fe_modrmreg = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_fd_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2506] // STD + (const void *)&gInstructions[ 2512] // STD }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_fc_leaf = @@ -127,7 +127,7 @@ const ND_TABLE_INSTRUCTION gLegacyMap_opcode_fc_leaf = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_fb_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2508] // STI + (const void *)&gInstructions[ 2514] // STI }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_fa_leaf = @@ -139,7 +139,7 @@ const ND_TABLE_INSTRUCTION gLegacyMap_opcode_fa_leaf = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_f9_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2505] // STC + (const void *)&gInstructions[ 2511] // STC }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_f8_leaf = @@ -169,31 +169,31 @@ const ND_TABLE_INSTRUCTION gLegacyMap_opcode_f7_modrmreg_05_leaf = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_f7_modrmreg_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1478] // MUL Ev + (const void *)&gInstructions[ 1480] // MUL Ev }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_f7_modrmreg_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1500] // NEG Ev + (const void *)&gInstructions[ 1502] // NEG Ev }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_f7_modrmreg_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1579] // NOT Ev + (const void *)&gInstructions[ 1581] // NOT Ev }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_f7_modrmreg_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2603] // TEST Ev,Iz + (const void *)&gInstructions[ 2633] // TEST Ev,Iz }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_f7_modrmreg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2602] // TEST Ev,Iz + (const void *)&gInstructions[ 2632] // TEST Ev,Iz }; const ND_TABLE_MODRM_REG gLegacyMap_opcode_f7_modrmreg = @@ -232,31 +232,31 @@ const ND_TABLE_INSTRUCTION gLegacyMap_opcode_f6_modrmreg_05_leaf = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_f6_modrmreg_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1477] // MUL Eb + (const void *)&gInstructions[ 1479] // MUL Eb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_f6_modrmreg_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1499] // NEG Eb + (const void *)&gInstructions[ 1501] // NEG Eb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_f6_modrmreg_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1578] // NOT Eb + (const void *)&gInstructions[ 1580] // NOT Eb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_f6_modrmreg_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2601] // TEST Eb,Ib + (const void *)&gInstructions[ 2631] // TEST Eb,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_f6_modrmreg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2600] // TEST Eb,Ib + (const void *)&gInstructions[ 2630] // TEST Eb,Ib }; const ND_TABLE_MODRM_REG gLegacyMap_opcode_f6_modrmreg = @@ -295,13 +295,13 @@ const ND_TABLE_INSTRUCTION gLegacyMap_opcode_f1_leaf = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ef_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1639] // OUT DX,eAX + (const void *)&gInstructions[ 1641] // OUT DX,eAX }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ee_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1638] // OUT DX,AL + (const void *)&gInstructions[ 1640] // OUT DX,AL }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ed_leaf = @@ -343,13 +343,13 @@ const ND_TABLE_INSTRUCTION gLegacyMap_opcode_e8_leaf = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_e7_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1637] // OUT Ib,eAX + (const void *)&gInstructions[ 1639] // OUT Ib,eAX }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_e6_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1636] // OUT Ib,AL + (const void *)&gInstructions[ 1638] // OUT Ib,AL }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_e5_leaf = @@ -2142,13 +2142,13 @@ const ND_TABLE_MODRM_REG gLegacyMap_opcode_d8_modrmreg = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d7_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4084] // XLATB + (const void *)&gInstructions[ 4133] // XLATB }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d6_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2233] // SALC + (const void *)&gInstructions[ 2239] // SALC }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d5_leaf = @@ -2166,49 +2166,49 @@ const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d4_leaf = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d3_modrmreg_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2275] // SAR Ev,CL + (const void *)&gInstructions[ 2281] // SAR Ev,CL }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d3_modrmreg_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2232] // SAL Ev,CL + (const void *)&gInstructions[ 2238] // SAL Ev,CL }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d3_modrmreg_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2469] // SHR Ev,CL + (const void *)&gInstructions[ 2475] // SHR Ev,CL }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d3_modrmreg_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2407] // SHL Ev,CL + (const void *)&gInstructions[ 2413] // SHL Ev,CL }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d3_modrmreg_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2071] // RCR Ev,CL + (const void *)&gInstructions[ 2075] // RCR Ev,CL }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d3_modrmreg_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2027] // RCL Ev,CL + (const void *)&gInstructions[ 2031] // RCL Ev,CL }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d3_modrmreg_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2179] // ROR Ev,CL + (const void *)&gInstructions[ 2185] // ROR Ev,CL }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d3_modrmreg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2137] // ROL Ev,CL + (const void *)&gInstructions[ 2143] // ROL Ev,CL }; const ND_TABLE_MODRM_REG gLegacyMap_opcode_d3_modrmreg = @@ -2229,49 +2229,49 @@ const ND_TABLE_MODRM_REG gLegacyMap_opcode_d3_modrmreg = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d2_modrmreg_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2274] // SAR Eb,CL + (const void *)&gInstructions[ 2280] // SAR Eb,CL }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d2_modrmreg_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2231] // SAL Eb,CL + (const void *)&gInstructions[ 2237] // SAL Eb,CL }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d2_modrmreg_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2468] // SHR Eb,CL + (const void *)&gInstructions[ 2474] // SHR Eb,CL }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d2_modrmreg_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2406] // SHL Eb,CL + (const void *)&gInstructions[ 2412] // SHL Eb,CL }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d2_modrmreg_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2070] // RCR Eb,CL + (const void *)&gInstructions[ 2074] // RCR Eb,CL }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d2_modrmreg_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2026] // RCL Eb,CL + (const void *)&gInstructions[ 2030] // RCL Eb,CL }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d2_modrmreg_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2178] // ROR Eb,CL + (const void *)&gInstructions[ 2184] // ROR Eb,CL }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d2_modrmreg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2136] // ROL Eb,CL + (const void *)&gInstructions[ 2142] // ROL Eb,CL }; const ND_TABLE_MODRM_REG gLegacyMap_opcode_d2_modrmreg = @@ -2292,49 +2292,49 @@ const ND_TABLE_MODRM_REG gLegacyMap_opcode_d2_modrmreg = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d1_modrmreg_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2273] // SAR Ev,1 + (const void *)&gInstructions[ 2279] // SAR Ev,1 }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d1_modrmreg_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2230] // SAL Ev,1 + (const void *)&gInstructions[ 2236] // SAL Ev,1 }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d1_modrmreg_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2467] // SHR Ev,1 + (const void *)&gInstructions[ 2473] // SHR Ev,1 }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d1_modrmreg_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2405] // SHL Ev,1 + (const void *)&gInstructions[ 2411] // SHL Ev,1 }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d1_modrmreg_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2069] // RCR Ev,1 + (const void *)&gInstructions[ 2073] // RCR Ev,1 }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d1_modrmreg_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2025] // RCL Ev,1 + (const void *)&gInstructions[ 2029] // RCL Ev,1 }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d1_modrmreg_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2177] // ROR Ev,1 + (const void *)&gInstructions[ 2183] // ROR Ev,1 }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d1_modrmreg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2135] // ROL Ev,1 + (const void *)&gInstructions[ 2141] // ROL Ev,1 }; const ND_TABLE_MODRM_REG gLegacyMap_opcode_d1_modrmreg = @@ -2355,49 +2355,49 @@ const ND_TABLE_MODRM_REG gLegacyMap_opcode_d1_modrmreg = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d0_modrmreg_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2272] // SAR Eb,1 + (const void *)&gInstructions[ 2278] // SAR Eb,1 }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d0_modrmreg_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2229] // SAL Eb,1 + (const void *)&gInstructions[ 2235] // SAL Eb,1 }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d0_modrmreg_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2466] // SHR Eb,1 + (const void *)&gInstructions[ 2472] // SHR Eb,1 }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d0_modrmreg_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2404] // SHL Eb,1 + (const void *)&gInstructions[ 2410] // SHL Eb,1 }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d0_modrmreg_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2068] // RCR Eb,1 + (const void *)&gInstructions[ 2072] // RCR Eb,1 }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d0_modrmreg_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2024] // RCL Eb,1 + (const void *)&gInstructions[ 2028] // RCL Eb,1 }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d0_modrmreg_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2176] // ROR Eb,1 + (const void *)&gInstructions[ 2182] // ROR Eb,1 }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d0_modrmreg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2134] // ROL Eb,1 + (const void *)&gInstructions[ 2140] // ROL Eb,1 }; const ND_TABLE_MODRM_REG gLegacyMap_opcode_d0_modrmreg = @@ -2467,13 +2467,13 @@ const ND_TABLE_INSTRUCTION gLegacyMap_opcode_cc_leaf = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_cb_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2089] // RETF + (const void *)&gInstructions[ 2095] // RETF }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ca_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2088] // RETF Iw + (const void *)&gInstructions[ 2094] // RETF Iw }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c9_leaf = @@ -2491,7 +2491,7 @@ const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c8_leaf = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c7_modrmreg_07_modrmmod_01_modrmrm_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4071] // XBEGIN Jz + (const void *)&gInstructions[ 4120] // XBEGIN Jz }; const ND_TABLE_MODRM_RM gLegacyMap_opcode_c7_modrmreg_07_modrmmod_01_modrmrm = @@ -2542,7 +2542,7 @@ const ND_TABLE_MODRM_REG gLegacyMap_opcode_c7_modrmreg = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c6_modrmreg_07_modrmmod_01_modrmrm_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4068] // XABORT Ib + (const void *)&gInstructions[ 4117] // XABORT Ib }; const ND_TABLE_MODRM_RM gLegacyMap_opcode_c6_modrmreg_07_modrmmod_01_modrmrm = @@ -2623,61 +2623,61 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_c4_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2091] // RETN + (const void *)&gInstructions[ 2097] // RETN }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2090] // RETN Iw + (const void *)&gInstructions[ 2096] // RETN Iw }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c1_modrmreg_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2271] // SAR Ev,Ib + (const void *)&gInstructions[ 2277] // SAR Ev,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c1_modrmreg_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2228] // SAL Ev,Ib + (const void *)&gInstructions[ 2234] // SAL Ev,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c1_modrmreg_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2465] // SHR Ev,Ib + (const void *)&gInstructions[ 2471] // SHR Ev,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c1_modrmreg_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2403] // SHL Ev,Ib + (const void *)&gInstructions[ 2409] // SHL Ev,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c1_modrmreg_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2067] // RCR Ev,Ib + (const void *)&gInstructions[ 2071] // RCR Ev,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c1_modrmreg_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2023] // RCL Ev,Ib + (const void *)&gInstructions[ 2027] // RCL Ev,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c1_modrmreg_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2175] // ROR Ev,Ib + (const void *)&gInstructions[ 2181] // ROR Ev,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c1_modrmreg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2133] // ROL Ev,Ib + (const void *)&gInstructions[ 2139] // ROL Ev,Ib }; const ND_TABLE_MODRM_REG gLegacyMap_opcode_c1_modrmreg = @@ -2698,49 +2698,49 @@ const ND_TABLE_MODRM_REG gLegacyMap_opcode_c1_modrmreg = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c0_modrmreg_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2270] // SAR Eb,Ib + (const void *)&gInstructions[ 2276] // SAR Eb,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c0_modrmreg_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2227] // SAL Eb,Ib + (const void *)&gInstructions[ 2233] // SAL Eb,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c0_modrmreg_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2464] // SHR Eb,Ib + (const void *)&gInstructions[ 2470] // SHR Eb,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c0_modrmreg_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2402] // SHL Eb,Ib + (const void *)&gInstructions[ 2408] // SHL Eb,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c0_modrmreg_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2066] // RCR Eb,Ib + (const void *)&gInstructions[ 2070] // RCR Eb,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c0_modrmreg_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2022] // RCL Eb,Ib + (const void *)&gInstructions[ 2026] // RCL Eb,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c0_modrmreg_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2174] // ROR Eb,Ib + (const void *)&gInstructions[ 2180] // ROR Eb,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c0_modrmreg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2132] // ROL Eb,Ib + (const void *)&gInstructions[ 2138] // ROL Eb,Ib }; const ND_TABLE_MODRM_REG gLegacyMap_opcode_c0_modrmreg = @@ -2857,13 +2857,13 @@ const ND_TABLE_INSTRUCTION gLegacyMap_opcode_b0_leaf = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_af_dsize_03_auxiliary_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2316] // SCASQ RAX,Yv + (const void *)&gInstructions[ 2322] // SCASQ RAX,Yv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_af_dsize_03_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2315] // SCASQ RAX,Yv + (const void *)&gInstructions[ 2321] // SCASQ RAX,Yv }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_af_dsize_03_auxiliary = @@ -2886,13 +2886,13 @@ const ND_TABLE_AUXILIARY gLegacyMap_opcode_af_dsize_03_auxiliary = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_af_dsize_02_auxiliary_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2314] // SCASD EAX,Yv + (const void *)&gInstructions[ 2320] // SCASD EAX,Yv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_af_dsize_02_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2313] // SCASD EAX,Yv + (const void *)&gInstructions[ 2319] // SCASD EAX,Yv }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_af_dsize_02_auxiliary = @@ -2915,13 +2915,13 @@ const ND_TABLE_AUXILIARY gLegacyMap_opcode_af_dsize_02_auxiliary = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_af_dsize_01_auxiliary_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2318] // SCASW AX,Yv + (const void *)&gInstructions[ 2324] // SCASW AX,Yv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_af_dsize_01_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2317] // SCASW AX,Yv + (const void *)&gInstructions[ 2323] // SCASW AX,Yv }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_af_dsize_01_auxiliary = @@ -2957,13 +2957,13 @@ const ND_TABLE_DSIZE gLegacyMap_opcode_af_dsize = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ae_auxiliary_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2312] // SCASB AL,Yb + (const void *)&gInstructions[ 2318] // SCASB AL,Yb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ae_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2311] // SCASB AL,Yb + (const void *)&gInstructions[ 2317] // SCASB AL,Yb }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_ae_auxiliary = @@ -3115,13 +3115,13 @@ const ND_TABLE_AUXILIARY gLegacyMap_opcode_ac_auxiliary = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ab_dsize_03_auxiliary_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2515] // STOSQ Yv,RAX + (const void *)&gInstructions[ 2521] // STOSQ Yv,RAX }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ab_dsize_03_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2514] // STOSQ Yv,RAX + (const void *)&gInstructions[ 2520] // STOSQ Yv,RAX }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_ab_dsize_03_auxiliary = @@ -3144,13 +3144,13 @@ const ND_TABLE_AUXILIARY gLegacyMap_opcode_ab_dsize_03_auxiliary = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ab_dsize_02_auxiliary_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2513] // STOSD Yv,EAX + (const void *)&gInstructions[ 2519] // STOSD Yv,EAX }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ab_dsize_02_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2512] // STOSD Yv,EAX + (const void *)&gInstructions[ 2518] // STOSD Yv,EAX }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_ab_dsize_02_auxiliary = @@ -3173,13 +3173,13 @@ const ND_TABLE_AUXILIARY gLegacyMap_opcode_ab_dsize_02_auxiliary = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ab_dsize_01_auxiliary_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2517] // STOSW Yv,AX + (const void *)&gInstructions[ 2523] // STOSW Yv,AX }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ab_dsize_01_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2516] // STOSW Yv,AX + (const void *)&gInstructions[ 2522] // STOSW Yv,AX }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_ab_dsize_01_auxiliary = @@ -3215,13 +3215,13 @@ const ND_TABLE_DSIZE gLegacyMap_opcode_ab_dsize = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_aa_auxiliary_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2511] // STOSB Yb,AL + (const void *)&gInstructions[ 2517] // STOSB Yb,AL }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_aa_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2510] // STOSB Yb,AL + (const void *)&gInstructions[ 2516] // STOSB Yb,AL }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_aa_auxiliary = @@ -3244,13 +3244,13 @@ const ND_TABLE_AUXILIARY gLegacyMap_opcode_aa_auxiliary = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_a9_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2599] // TEST rAX,Iz + (const void *)&gInstructions[ 2629] // TEST rAX,Iz }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_a8_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2598] // TEST AL,Ib + (const void *)&gInstructions[ 2628] // TEST AL,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_a7_dsize_03_auxiliary_05_leaf = @@ -3385,13 +3385,13 @@ const ND_TABLE_AUXILIARY gLegacyMap_opcode_a6_auxiliary = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_a5_dsize_03_auxiliary_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1456] // MOVSQ Yv,Xv + (const void *)&gInstructions[ 1458] // MOVSQ Yv,Xv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_a5_dsize_03_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1455] // MOVSQ Yv,Xv + (const void *)&gInstructions[ 1457] // MOVSQ Yv,Xv }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_a5_dsize_03_auxiliary = @@ -3414,13 +3414,13 @@ const ND_TABLE_AUXILIARY gLegacyMap_opcode_a5_dsize_03_auxiliary = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_a5_dsize_02_auxiliary_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1450] // MOVSD Yv,Xv + (const void *)&gInstructions[ 1452] // MOVSD Yv,Xv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_a5_dsize_02_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1449] // MOVSD Yv,Xv + (const void *)&gInstructions[ 1451] // MOVSD Yv,Xv }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_a5_dsize_02_auxiliary = @@ -3443,13 +3443,13 @@ const ND_TABLE_AUXILIARY gLegacyMap_opcode_a5_dsize_02_auxiliary = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_a5_dsize_01_auxiliary_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1460] // MOVSW Yv,Xv + (const void *)&gInstructions[ 1462] // MOVSW Yv,Xv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_a5_dsize_01_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1459] // MOVSW Yv,Xv + (const void *)&gInstructions[ 1461] // MOVSW Yv,Xv }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_a5_dsize_01_auxiliary = @@ -3485,13 +3485,13 @@ const ND_TABLE_DSIZE gLegacyMap_opcode_a5_dsize = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_a4_auxiliary_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1448] // MOVSB Yb,Xb + (const void *)&gInstructions[ 1450] // MOVSB Yb,Xb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_a4_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1447] // MOVSB Yb,Xb + (const void *)&gInstructions[ 1449] // MOVSB Yb,Xb }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_a4_auxiliary = @@ -3576,25 +3576,25 @@ const ND_TABLE_INSTRUCTION gLegacyMap_opcode_9f_leaf = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_9e_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2190] // SAHF + (const void *)&gInstructions[ 2196] // SAHF }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_9d_dsize_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1839] // POPFQ Fv + (const void *)&gInstructions[ 1841] // POPFQ Fv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_9d_dsize_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1838] // POPFD Fv + (const void *)&gInstructions[ 1840] // POPFD Fv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_9d_dsize_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1840] // POPFW Fv + (const void *)&gInstructions[ 1842] // POPFW Fv }; const ND_TABLE_DSIZE gLegacyMap_opcode_9d_dsize = @@ -3613,19 +3613,19 @@ const ND_TABLE_DSIZE gLegacyMap_opcode_9d_dsize = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_9c_dsize_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1973] // PUSHFQ Fv + (const void *)&gInstructions[ 1977] // PUSHFQ Fv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_9c_dsize_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1972] // PUSHFD Fv + (const void *)&gInstructions[ 1976] // PUSHFD Fv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_9c_dsize_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1974] // PUSHFW Fv + (const void *)&gInstructions[ 1978] // PUSHFW Fv }; const ND_TABLE_DSIZE gLegacyMap_opcode_9c_dsize = @@ -3644,7 +3644,7 @@ const ND_TABLE_DSIZE gLegacyMap_opcode_9c_dsize = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_9b_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4051] // WAIT + (const void *)&gInstructions[ 4098] // WAIT }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_9a_leaf = @@ -3718,61 +3718,61 @@ const ND_TABLE_DSIZE gLegacyMap_opcode_98_dsize = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_97_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4081] // XCHG Zv,rAX + (const void *)&gInstructions[ 4130] // XCHG Zv,rAX }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_96_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4080] // XCHG Zv,rAX + (const void *)&gInstructions[ 4129] // XCHG Zv,rAX }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_95_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4079] // XCHG Zv,rAX + (const void *)&gInstructions[ 4128] // XCHG Zv,rAX }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_94_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4078] // XCHG Zv,rAX + (const void *)&gInstructions[ 4127] // XCHG Zv,rAX }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_93_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4077] // XCHG Zv,rAX + (const void *)&gInstructions[ 4126] // XCHG Zv,rAX }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_92_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4076] // XCHG Zv,rAX + (const void *)&gInstructions[ 4125] // XCHG Zv,rAX }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_91_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4075] // XCHG Zv,rAX + (const void *)&gInstructions[ 4124] // XCHG Zv,rAX }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_90_auxiliary_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1681] // PAUSE + (const void *)&gInstructions[ 1683] // PAUSE }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_90_auxiliary_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4074] // XCHG Zv,rAX + (const void *)&gInstructions[ 4123] // XCHG Zv,rAX }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_90_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1501] // NOP + (const void *)&gInstructions[ 1503] // NOP }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_90_auxiliary = @@ -3795,7 +3795,7 @@ const ND_TABLE_AUXILIARY gLegacyMap_opcode_90_auxiliary = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_8f_modrmreg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1826] // POP Ev + (const void *)&gInstructions[ 1828] // POP Ev }; const ND_TABLE_MODRM_REG gLegacyMap_opcode_8f_modrmreg = @@ -3897,25 +3897,25 @@ const ND_TABLE_INSTRUCTION gLegacyMap_opcode_88_leaf = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_87_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4073] // XCHG Ev,Gv + (const void *)&gInstructions[ 4122] // XCHG Ev,Gv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_86_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4072] // XCHG Eb,Gb + (const void *)&gInstructions[ 4121] // XCHG Eb,Gb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_85_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2597] // TEST Ev,Gv + (const void *)&gInstructions[ 2627] // TEST Ev,Gv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_84_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2596] // TEST Eb,Gb + (const void *)&gInstructions[ 2626] // TEST Eb,Gb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_83_modrmreg_07_leaf = @@ -3927,13 +3927,13 @@ const ND_TABLE_INSTRUCTION gLegacyMap_opcode_83_modrmreg_07_leaf = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_83_modrmreg_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4138] // XOR Ev,Ib + (const void *)&gInstructions[ 4187] // XOR Ev,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_83_modrmreg_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2576] // SUB Ev,Ib + (const void *)&gInstructions[ 2582] // SUB Ev,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_83_modrmreg_04_leaf = @@ -3945,7 +3945,7 @@ const ND_TABLE_INSTRUCTION gLegacyMap_opcode_83_modrmreg_04_leaf = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_83_modrmreg_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2310] // SBB Ev,Ib + (const void *)&gInstructions[ 2316] // SBB Ev,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_83_modrmreg_02_leaf = @@ -3957,7 +3957,7 @@ const ND_TABLE_INSTRUCTION gLegacyMap_opcode_83_modrmreg_02_leaf = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_83_modrmreg_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1633] // OR Ev,Ib + (const void *)&gInstructions[ 1635] // OR Ev,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_83_modrmreg_00_leaf = @@ -3990,13 +3990,13 @@ const ND_TABLE_INSTRUCTION gLegacyMap_opcode_82_modrmreg_07_leaf = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_82_modrmreg_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4137] // XOR Eb,Ib + (const void *)&gInstructions[ 4186] // XOR Eb,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_82_modrmreg_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2575] // SUB Eb,Ib + (const void *)&gInstructions[ 2581] // SUB Eb,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_82_modrmreg_04_leaf = @@ -4008,7 +4008,7 @@ const ND_TABLE_INSTRUCTION gLegacyMap_opcode_82_modrmreg_04_leaf = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_82_modrmreg_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2309] // SBB Eb,Ib + (const void *)&gInstructions[ 2315] // SBB Eb,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_82_modrmreg_02_leaf = @@ -4020,7 +4020,7 @@ const ND_TABLE_INSTRUCTION gLegacyMap_opcode_82_modrmreg_02_leaf = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_82_modrmreg_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1632] // OR Eb,Ib + (const void *)&gInstructions[ 1634] // OR Eb,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_82_modrmreg_00_leaf = @@ -4053,13 +4053,13 @@ const ND_TABLE_INSTRUCTION gLegacyMap_opcode_81_modrmreg_07_leaf = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_81_modrmreg_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4136] // XOR Ev,Iz + (const void *)&gInstructions[ 4185] // XOR Ev,Iz }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_81_modrmreg_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2574] // SUB Ev,Iz + (const void *)&gInstructions[ 2580] // SUB Ev,Iz }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_81_modrmreg_04_leaf = @@ -4071,7 +4071,7 @@ const ND_TABLE_INSTRUCTION gLegacyMap_opcode_81_modrmreg_04_leaf = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_81_modrmreg_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2308] // SBB Ev,Iz + (const void *)&gInstructions[ 2314] // SBB Ev,Iz }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_81_modrmreg_02_leaf = @@ -4083,7 +4083,7 @@ const ND_TABLE_INSTRUCTION gLegacyMap_opcode_81_modrmreg_02_leaf = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_81_modrmreg_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1631] // OR Ev,Iz + (const void *)&gInstructions[ 1633] // OR Ev,Iz }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_81_modrmreg_00_leaf = @@ -4116,13 +4116,13 @@ const ND_TABLE_INSTRUCTION gLegacyMap_opcode_80_modrmreg_07_leaf = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_80_modrmreg_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4135] // XOR Eb,Ib + (const void *)&gInstructions[ 4184] // XOR Eb,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_80_modrmreg_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2573] // SUB Eb,Ib + (const void *)&gInstructions[ 2579] // SUB Eb,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_80_modrmreg_04_leaf = @@ -4134,7 +4134,7 @@ const ND_TABLE_INSTRUCTION gLegacyMap_opcode_80_modrmreg_04_leaf = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_80_modrmreg_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2307] // SBB Eb,Ib + (const void *)&gInstructions[ 2313] // SBB Eb,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_80_modrmreg_02_leaf = @@ -4146,7 +4146,7 @@ const ND_TABLE_INSTRUCTION gLegacyMap_opcode_80_modrmreg_02_leaf = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_80_modrmreg_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1630] // OR Eb,Ib + (const void *)&gInstructions[ 1632] // OR Eb,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_80_modrmreg_00_leaf = @@ -4269,13 +4269,13 @@ const ND_TABLE_INSTRUCTION gLegacyMap_opcode_70_leaf = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_6f_dsize_01_auxiliary_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1645] // OUTSW DX,Xz + (const void *)&gInstructions[ 1647] // OUTSW DX,Xz }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_6f_dsize_01_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1644] // OUTSW DX,Xz + (const void *)&gInstructions[ 1646] // OUTSW DX,Xz }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_6f_dsize_01_auxiliary = @@ -4298,13 +4298,13 @@ const ND_TABLE_AUXILIARY gLegacyMap_opcode_6f_dsize_01_auxiliary = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_6f_dsize_00_auxiliary_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1643] // OUTSD DX,Xz + (const void *)&gInstructions[ 1645] // OUTSD DX,Xz }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_6f_dsize_00_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1642] // OUTSD DX,Xz + (const void *)&gInstructions[ 1644] // OUTSD DX,Xz }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_6f_dsize_00_auxiliary = @@ -4340,13 +4340,13 @@ const ND_TABLE_DSIZE gLegacyMap_opcode_6f_dsize = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_6e_auxiliary_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1641] // OUTSB DX,Xb + (const void *)&gInstructions[ 1643] // OUTSB DX,Xb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_6e_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1640] // OUTSB DX,Xb + (const void *)&gInstructions[ 1642] // OUTSB DX,Xb }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_6e_auxiliary = @@ -4475,7 +4475,7 @@ const ND_TABLE_INSTRUCTION gLegacyMap_opcode_6b_leaf = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_6a_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1964] // PUSH Ib + (const void *)&gInstructions[ 1968] // PUSH Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_69_leaf = @@ -4487,13 +4487,13 @@ const ND_TABLE_INSTRUCTION gLegacyMap_opcode_69_leaf = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_68_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1963] // PUSH Iz + (const void *)&gInstructions[ 1967] // PUSH Iz }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_63_auxiliary_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1463] // MOVSXD Gv,Ez + (const void *)&gInstructions[ 1465] // MOVSXD Gv,Ez }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_63_auxiliary_00_leaf = @@ -4537,13 +4537,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_62_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_61_dsize_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1832] // POPAD + (const void *)&gInstructions[ 1834] // POPAD }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_61_dsize_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1831] // POPA + (const void *)&gInstructions[ 1833] // POPA }; const ND_TABLE_DSIZE gLegacyMap_opcode_61_dsize = @@ -4562,13 +4562,13 @@ const ND_TABLE_DSIZE gLegacyMap_opcode_61_dsize = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_60_dsize_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1971] // PUSHAD + (const void *)&gInstructions[ 1975] // PUSHAD }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_60_dsize_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1970] // PUSHA + (const void *)&gInstructions[ 1974] // PUSHA }; const ND_TABLE_DSIZE gLegacyMap_opcode_60_dsize = @@ -4587,13 +4587,13 @@ const ND_TABLE_DSIZE gLegacyMap_opcode_60_dsize = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_5f_auxiliary_08_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1848] // POPP Zv + (const void *)&gInstructions[ 1850] // POPP Zv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_5f_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1825] // POP Zv + (const void *)&gInstructions[ 1827] // POP Zv }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_5f_auxiliary = @@ -4616,13 +4616,13 @@ const ND_TABLE_AUXILIARY gLegacyMap_opcode_5f_auxiliary = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_5e_auxiliary_08_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1847] // POPP Zv + (const void *)&gInstructions[ 1849] // POPP Zv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_5e_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1824] // POP Zv + (const void *)&gInstructions[ 1826] // POP Zv }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_5e_auxiliary = @@ -4645,13 +4645,13 @@ const ND_TABLE_AUXILIARY gLegacyMap_opcode_5e_auxiliary = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_5d_auxiliary_08_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1846] // POPP Zv + (const void *)&gInstructions[ 1848] // POPP Zv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_5d_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1823] // POP Zv + (const void *)&gInstructions[ 1825] // POP Zv }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_5d_auxiliary = @@ -4674,13 +4674,13 @@ const ND_TABLE_AUXILIARY gLegacyMap_opcode_5d_auxiliary = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_5c_auxiliary_08_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1845] // POPP Zv + (const void *)&gInstructions[ 1847] // POPP Zv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_5c_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1822] // POP Zv + (const void *)&gInstructions[ 1824] // POP Zv }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_5c_auxiliary = @@ -4703,13 +4703,13 @@ const ND_TABLE_AUXILIARY gLegacyMap_opcode_5c_auxiliary = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_5b_auxiliary_08_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1844] // POPP Zv + (const void *)&gInstructions[ 1846] // POPP Zv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_5b_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1821] // POP Zv + (const void *)&gInstructions[ 1823] // POP Zv }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_5b_auxiliary = @@ -4732,13 +4732,13 @@ const ND_TABLE_AUXILIARY gLegacyMap_opcode_5b_auxiliary = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_5a_auxiliary_08_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1843] // POPP Zv + (const void *)&gInstructions[ 1845] // POPP Zv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_5a_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1820] // POP Zv + (const void *)&gInstructions[ 1822] // POP Zv }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_5a_auxiliary = @@ -4761,13 +4761,13 @@ const ND_TABLE_AUXILIARY gLegacyMap_opcode_5a_auxiliary = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_59_auxiliary_08_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1842] // POPP Zv + (const void *)&gInstructions[ 1844] // POPP Zv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_59_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1819] // POP Zv + (const void *)&gInstructions[ 1821] // POP Zv }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_59_auxiliary = @@ -4790,13 +4790,13 @@ const ND_TABLE_AUXILIARY gLegacyMap_opcode_59_auxiliary = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_58_auxiliary_08_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1841] // POPP Zv + (const void *)&gInstructions[ 1843] // POPP Zv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_58_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1818] // POP Zv + (const void *)&gInstructions[ 1820] // POP Zv }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_58_auxiliary = @@ -4819,13 +4819,13 @@ const ND_TABLE_AUXILIARY gLegacyMap_opcode_58_auxiliary = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_57_auxiliary_08_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1982] // PUSHP Zv + (const void *)&gInstructions[ 1986] // PUSHP Zv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_57_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1962] // PUSH Zv + (const void *)&gInstructions[ 1966] // PUSH Zv }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_57_auxiliary = @@ -4848,13 +4848,13 @@ const ND_TABLE_AUXILIARY gLegacyMap_opcode_57_auxiliary = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_56_auxiliary_08_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1981] // PUSHP Zv + (const void *)&gInstructions[ 1985] // PUSHP Zv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_56_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1961] // PUSH Zv + (const void *)&gInstructions[ 1965] // PUSH Zv }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_56_auxiliary = @@ -4877,13 +4877,13 @@ const ND_TABLE_AUXILIARY gLegacyMap_opcode_56_auxiliary = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_55_auxiliary_08_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1980] // PUSHP Zv + (const void *)&gInstructions[ 1984] // PUSHP Zv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_55_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1960] // PUSH Zv + (const void *)&gInstructions[ 1964] // PUSH Zv }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_55_auxiliary = @@ -4906,13 +4906,13 @@ const ND_TABLE_AUXILIARY gLegacyMap_opcode_55_auxiliary = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_54_auxiliary_08_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1979] // PUSHP Zv + (const void *)&gInstructions[ 1983] // PUSHP Zv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_54_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1959] // PUSH Zv + (const void *)&gInstructions[ 1963] // PUSH Zv }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_54_auxiliary = @@ -4935,13 +4935,13 @@ const ND_TABLE_AUXILIARY gLegacyMap_opcode_54_auxiliary = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_53_auxiliary_08_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1978] // PUSHP Zv + (const void *)&gInstructions[ 1982] // PUSHP Zv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_53_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1958] // PUSH Zv + (const void *)&gInstructions[ 1962] // PUSH Zv }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_53_auxiliary = @@ -4964,13 +4964,13 @@ const ND_TABLE_AUXILIARY gLegacyMap_opcode_53_auxiliary = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_52_auxiliary_08_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1977] // PUSHP Zv + (const void *)&gInstructions[ 1981] // PUSHP Zv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_52_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1957] // PUSH Zv + (const void *)&gInstructions[ 1961] // PUSH Zv }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_52_auxiliary = @@ -4993,13 +4993,13 @@ const ND_TABLE_AUXILIARY gLegacyMap_opcode_52_auxiliary = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_51_auxiliary_08_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1976] // PUSHP Zv + (const void *)&gInstructions[ 1980] // PUSHP Zv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_51_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1956] // PUSH Zv + (const void *)&gInstructions[ 1960] // PUSH Zv }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_51_auxiliary = @@ -5022,13 +5022,13 @@ const ND_TABLE_AUXILIARY gLegacyMap_opcode_51_auxiliary = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_50_auxiliary_08_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1975] // PUSHP Zv + (const void *)&gInstructions[ 1979] // PUSHP Zv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_50_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1955] // PUSH Zv + (const void *)&gInstructions[ 1959] // PUSH Zv }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_50_auxiliary = @@ -5195,37 +5195,37 @@ const ND_TABLE_INSTRUCTION gLegacyMap_opcode_37_leaf = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_35_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4134] // XOR rAX,Iz + (const void *)&gInstructions[ 4183] // XOR rAX,Iz }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_34_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4133] // XOR AL,Ib + (const void *)&gInstructions[ 4182] // XOR AL,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_33_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4132] // XOR Gv,Ev + (const void *)&gInstructions[ 4181] // XOR Gv,Ev }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_32_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4131] // XOR Gb,Eb + (const void *)&gInstructions[ 4180] // XOR Gb,Eb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_31_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4130] // XOR Ev,Gv + (const void *)&gInstructions[ 4179] // XOR Ev,Gv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_30_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4129] // XOR Eb,Gb + (const void *)&gInstructions[ 4178] // XOR Eb,Gb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_2f_leaf = @@ -5237,37 +5237,37 @@ const ND_TABLE_INSTRUCTION gLegacyMap_opcode_2f_leaf = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_2d_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2572] // SUB rAX,Iz + (const void *)&gInstructions[ 2578] // SUB rAX,Iz }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_2c_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2571] // SUB AL,Ib + (const void *)&gInstructions[ 2577] // SUB AL,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_2b_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2570] // SUB Gv,Ev + (const void *)&gInstructions[ 2576] // SUB Gv,Ev }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_2a_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2569] // SUB Gb,Eb + (const void *)&gInstructions[ 2575] // SUB Gb,Eb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_29_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2568] // SUB Ev,Gv + (const void *)&gInstructions[ 2574] // SUB Ev,Gv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_28_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2567] // SUB Eb,Gb + (const void *)&gInstructions[ 2573] // SUB Eb,Gb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_27_leaf = @@ -5315,61 +5315,61 @@ const ND_TABLE_INSTRUCTION gLegacyMap_opcode_20_leaf = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_1f_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1817] // POP DS + (const void *)&gInstructions[ 1819] // POP DS }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_1e_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1954] // PUSH DS + (const void *)&gInstructions[ 1958] // PUSH DS }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_1d_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2306] // SBB rAX,Iz + (const void *)&gInstructions[ 2312] // SBB rAX,Iz }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_1c_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2305] // SBB AL,Ib + (const void *)&gInstructions[ 2311] // SBB AL,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_1b_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2304] // SBB Gv,Ev + (const void *)&gInstructions[ 2310] // SBB Gv,Ev }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_1a_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2303] // SBB Gb,Eb + (const void *)&gInstructions[ 2309] // SBB Gb,Eb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_19_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2302] // SBB Ev,Gv + (const void *)&gInstructions[ 2308] // SBB Ev,Gv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_18_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2301] // SBB Eb,Gb + (const void *)&gInstructions[ 2307] // SBB Eb,Gb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_17_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1816] // POP SS + (const void *)&gInstructions[ 1818] // POP SS }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_16_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1953] // PUSH SS + (const void *)&gInstructions[ 1957] // PUSH SS }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_15_leaf = @@ -5411,19 +5411,19 @@ const ND_TABLE_INSTRUCTION gLegacyMap_opcode_10_leaf = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ff_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2623] // UD0 Gd,Ed + (const void *)&gInstructions[ 2664] // UD0 Gd,Ed }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_fe_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1662] // PADDD Vx,Wx + (const void *)&gInstructions[ 1664] // PADDD Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_fe_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1661] // PADDD Pq,Qq + (const void *)&gInstructions[ 1663] // PADDD Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_fe_prefix = @@ -5440,13 +5440,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_fe_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_fd_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1674] // PADDW Vx,Wx + (const void *)&gInstructions[ 1676] // PADDW Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_fd_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1673] // PADDW Pq,Qq + (const void *)&gInstructions[ 1675] // PADDW Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_fd_prefix = @@ -5463,13 +5463,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_fd_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_fc_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1660] // PADDB Vx,Wx + (const void *)&gInstructions[ 1662] // PADDB Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_fc_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1659] // PADDB Pq,Qq + (const void *)&gInstructions[ 1661] // PADDB Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_fc_prefix = @@ -5486,13 +5486,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_fc_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_fb_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1923] // PSUBQ Vx,Wx + (const void *)&gInstructions[ 1927] // PSUBQ Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_fb_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1922] // PSUBQ Pq,Qq + (const void *)&gInstructions[ 1926] // PSUBQ Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_fb_prefix = @@ -5509,13 +5509,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_fb_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_fa_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1921] // PSUBD Vx,Wx + (const void *)&gInstructions[ 1925] // PSUBD Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_fa_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1920] // PSUBD Pq,Qq + (const void *)&gInstructions[ 1924] // PSUBD Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_fa_prefix = @@ -5532,13 +5532,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_fa_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_f9_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1933] // PSUBW Vx,Wx + (const void *)&gInstructions[ 1937] // PSUBW Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_f9_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1932] // PSUBW Pq,Qq + (const void *)&gInstructions[ 1936] // PSUBW Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_f9_prefix = @@ -5555,13 +5555,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_f9_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_f8_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1919] // PSUBB Vx,Wx + (const void *)&gInstructions[ 1923] // PSUBB Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_f8_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1918] // PSUBB Pq,Qq + (const void *)&gInstructions[ 1922] // PSUBB Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_f8_prefix = @@ -5619,13 +5619,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_f7_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_f6_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1870] // PSADBW Vx,Wx + (const void *)&gInstructions[ 1874] // PSADBW Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_f6_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1869] // PSADBW Pq,Qq + (const void *)&gInstructions[ 1873] // PSADBW Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_f6_prefix = @@ -5642,13 +5642,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_f6_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_f5_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1771] // PMADDWD Vx,Wx + (const void *)&gInstructions[ 1773] // PMADDWD Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_f5_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1770] // PMADDWD Pq,Qq + (const void *)&gInstructions[ 1772] // PMADDWD Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_f5_prefix = @@ -5665,13 +5665,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_f5_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_f4_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1814] // PMULUDQ Vx,Wx + (const void *)&gInstructions[ 1816] // PMULUDQ Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_f4_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1813] // PMULUDQ Pq,Qq + (const void *)&gInstructions[ 1815] // PMULUDQ Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_f4_prefix = @@ -5688,13 +5688,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_f4_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_f3_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1891] // PSLLQ Vx,Wx + (const void *)&gInstructions[ 1895] // PSLLQ Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_f3_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1890] // PSLLQ Pq,Qq + (const void *)&gInstructions[ 1894] // PSLLQ Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_f3_prefix = @@ -5711,13 +5711,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_f3_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_f2_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1886] // PSLLD Vx,Wx + (const void *)&gInstructions[ 1890] // PSLLD Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_f2_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1885] // PSLLD Pq,Qq + (const void *)&gInstructions[ 1889] // PSLLD Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_f2_prefix = @@ -5734,13 +5734,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_f2_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_f1_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1895] // PSLLW Vx,Wx + (const void *)&gInstructions[ 1899] // PSLLW Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_f1_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1894] // PSLLW Pq,Qq + (const void *)&gInstructions[ 1898] // PSLLW Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_f1_prefix = @@ -5783,13 +5783,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_f0_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ef_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1985] // PXOR Vx,Wx + (const void *)&gInstructions[ 1989] // PXOR Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ef_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1984] // PXOR Pq,Qq + (const void *)&gInstructions[ 1988] // PXOR Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_ef_prefix = @@ -5806,13 +5806,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_ef_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ee_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1775] // PMAXSW Vx,Wx + (const void *)&gInstructions[ 1777] // PMAXSW Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ee_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1774] // PMAXSW Pq,Qq + (const void *)&gInstructions[ 1776] // PMAXSW Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_ee_prefix = @@ -5829,13 +5829,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_ee_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ed_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1668] // PADDSW Vx,Wx + (const void *)&gInstructions[ 1670] // PADDSW Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ed_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1667] // PADDSW Pq,Qq + (const void *)&gInstructions[ 1669] // PADDSW Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_ed_prefix = @@ -5852,13 +5852,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_ed_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ec_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1666] // PADDSB Vx,Wx + (const void *)&gInstructions[ 1668] // PADDSB Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ec_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1665] // PADDSB Pq,Qq + (const void *)&gInstructions[ 1667] // PADDSB Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_ec_prefix = @@ -5875,13 +5875,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_ec_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_eb_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1850] // POR Vx,Wx + (const void *)&gInstructions[ 1852] // POR Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_eb_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1849] // POR Pq,Qq + (const void *)&gInstructions[ 1851] // POR Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_eb_prefix = @@ -5898,13 +5898,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_eb_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ea_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1783] // PMINSW Vx,Wx + (const void *)&gInstructions[ 1785] // PMINSW Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ea_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1782] // PMINSW Pq,Qq + (const void *)&gInstructions[ 1784] // PMINSW Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_ea_prefix = @@ -5921,13 +5921,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_ea_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_e9_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1927] // PSUBSW Vx,Wx + (const void *)&gInstructions[ 1931] // PSUBSW Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_e9_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1926] // PSUBSW Pq,Qq + (const void *)&gInstructions[ 1930] // PSUBSW Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_e9_prefix = @@ -5944,13 +5944,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_e9_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_e8_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1925] // PSUBSB Vx,Wx + (const void *)&gInstructions[ 1929] // PSUBSB Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_e8_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1924] // PSUBSB Pq,Qq + (const void *)&gInstructions[ 1928] // PSUBSB Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_e8_prefix = @@ -6037,13 +6037,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_e6_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_e5_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1809] // PMULHW Vx,Wx + (const void *)&gInstructions[ 1811] // PMULHW Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_e5_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1808] // PMULHW Pq,Qq + (const void *)&gInstructions[ 1810] // PMULHW Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_e5_prefix = @@ -6060,13 +6060,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_e5_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_e4_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1807] // PMULHUW Vx,Wx + (const void *)&gInstructions[ 1809] // PMULHUW Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_e4_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1806] // PMULHUW Pq,Qq + (const void *)&gInstructions[ 1808] // PMULHUW Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_e4_prefix = @@ -6083,13 +6083,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_e4_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_e3_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1686] // PAVGW Vx,Wx + (const void *)&gInstructions[ 1688] // PAVGW Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_e3_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1685] // PAVGW Pq,Qq + (const void *)&gInstructions[ 1687] // PAVGW Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_e3_prefix = @@ -6106,13 +6106,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_e3_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_e2_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1900] // PSRAD Vx,Wx + (const void *)&gInstructions[ 1904] // PSRAD Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_e2_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1899] // PSRAD Pq,Qq + (const void *)&gInstructions[ 1903] // PSRAD Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_e2_prefix = @@ -6129,13 +6129,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_e2_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_e1_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1904] // PSRAW Vx,Wx + (const void *)&gInstructions[ 1908] // PSRAW Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_e1_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1903] // PSRAW Pq,Qq + (const void *)&gInstructions[ 1907] // PSRAW Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_e1_prefix = @@ -6152,13 +6152,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_e1_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_e0_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1683] // PAVGB Vx,Wx + (const void *)&gInstructions[ 1685] // PAVGB Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_e0_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1682] // PAVGB Pq,Qq + (const void *)&gInstructions[ 1684] // PAVGB Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_e0_prefix = @@ -6175,13 +6175,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_e0_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_df_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1680] // PANDN Vx,Wx + (const void *)&gInstructions[ 1682] // PANDN Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_df_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1679] // PANDN Pq,Qq + (const void *)&gInstructions[ 1681] // PANDN Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_df_prefix = @@ -6198,13 +6198,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_df_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_de_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1777] // PMAXUB Vx,Wx + (const void *)&gInstructions[ 1779] // PMAXUB Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_de_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1776] // PMAXUB Pq,Qq + (const void *)&gInstructions[ 1778] // PMAXUB Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_de_prefix = @@ -6221,13 +6221,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_de_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_dd_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1672] // PADDUSW Vx,Wx + (const void *)&gInstructions[ 1674] // PADDUSW Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_dd_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1671] // PADDUSW Pq,Qq + (const void *)&gInstructions[ 1673] // PADDUSW Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_dd_prefix = @@ -6244,13 +6244,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_dd_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_dc_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1670] // PADDUSB Vx,Wx + (const void *)&gInstructions[ 1672] // PADDUSB Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_dc_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1669] // PADDUSB Pq,Qq + (const void *)&gInstructions[ 1671] // PADDUSB Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_dc_prefix = @@ -6267,13 +6267,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_dc_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_db_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1678] // PAND Vx,Wx + (const void *)&gInstructions[ 1680] // PAND Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_db_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1677] // PAND Pq,Qq + (const void *)&gInstructions[ 1679] // PAND Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_db_prefix = @@ -6290,13 +6290,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_db_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_da_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1785] // PMINUB Vx,Wx + (const void *)&gInstructions[ 1787] // PMINUB Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_da_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1784] // PMINUB Pq,Qq + (const void *)&gInstructions[ 1786] // PMINUB Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_da_prefix = @@ -6313,13 +6313,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_da_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_d9_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1931] // PSUBUSW Vx,Wx + (const void *)&gInstructions[ 1935] // PSUBUSW Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_d9_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1930] // PSUBUSW Pq,Qq + (const void *)&gInstructions[ 1934] // PSUBUSW Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_d9_prefix = @@ -6336,13 +6336,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_d9_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_d8_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1929] // PSUBUSB Vx,Wx + (const void *)&gInstructions[ 1933] // PSUBUSB Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_d8_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1928] // PSUBUSB Pq,Qq + (const void *)&gInstructions[ 1932] // PSUBUSB Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_d8_prefix = @@ -6359,7 +6359,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_d8_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_d7_prefix_01_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1789] // PMOVMSKB Gy,Ux + (const void *)&gInstructions[ 1791] // PMOVMSKB Gy,Ux }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_d7_prefix_01_modrmmod = @@ -6374,7 +6374,7 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_d7_prefix_01_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_d7_prefix_00_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1788] // PMOVMSKB Gy,Nq + (const void *)&gInstructions[ 1790] // PMOVMSKB Gy,Nq }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_d7_prefix_00_modrmmod = @@ -6447,13 +6447,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_d6_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_d5_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1812] // PMULLW Vx,Wx + (const void *)&gInstructions[ 1814] // PMULLW Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_d5_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1811] // PMULLW Pq,Qq + (const void *)&gInstructions[ 1813] // PMULLW Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_d5_prefix = @@ -6470,13 +6470,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_d5_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_d4_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1664] // PADDQ Vx,Wx + (const void *)&gInstructions[ 1666] // PADDQ Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_d4_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1663] // PADDQ Pq,Qq + (const void *)&gInstructions[ 1665] // PADDQ Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_d4_prefix = @@ -6493,13 +6493,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_d4_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_d3_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1913] // PSRLQ Vx,Wx + (const void *)&gInstructions[ 1917] // PSRLQ Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_d3_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1912] // PSRLQ Pq,Qq + (const void *)&gInstructions[ 1916] // PSRLQ Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_d3_prefix = @@ -6516,13 +6516,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_d3_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_d2_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1908] // PSRLD Vx,Wx + (const void *)&gInstructions[ 1912] // PSRLD Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_d2_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1907] // PSRLD Pq,Qq + (const void *)&gInstructions[ 1911] // PSRLD Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_d2_prefix = @@ -6539,13 +6539,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_d2_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_d1_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1917] // PSRLW Vx,Wx + (const void *)&gInstructions[ 1921] // PSRLW Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_d1_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1916] // PSRLW Pq,Qq + (const void *)&gInstructions[ 1920] // PSRLW Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_d1_prefix = @@ -6633,7 +6633,7 @@ const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c8_leaf = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c7_modrmreg_07_prefix_02_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2076] // RDPID Ryf + (const void *)&gInstructions[ 2082] // RDPID Ryf }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_c7_modrmreg_07_prefix_02_modrmmod = @@ -6648,7 +6648,7 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_c7_modrmreg_07_prefix_02_mo const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c7_modrmreg_07_prefix_01_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2083] // RDSEED Rv + (const void *)&gInstructions[ 2089] // RDSEED Rv }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_c7_modrmreg_07_prefix_01_modrmmod = @@ -6663,13 +6663,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_c7_modrmreg_07_prefix_01_mo const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c7_modrmreg_07_prefix_00_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2082] // RDSEED Rv + (const void *)&gInstructions[ 2088] // RDSEED Rv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c7_modrmreg_07_prefix_00_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3342] // VMPTRST Mq + (const void *)&gInstructions[ 3387] // VMPTRST Mq }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_c7_modrmreg_07_prefix_00_modrmmod = @@ -6695,13 +6695,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_c7_modrmreg_07_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c7_modrmreg_06_prefix_02_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2322] // SENDUIPI Rq + (const void *)&gInstructions[ 2328] // SENDUIPI Rq }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c7_modrmreg_06_prefix_02_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3360] // VMXON Mq + (const void *)&gInstructions[ 3405] // VMXON Mq }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_c7_modrmreg_06_prefix_02_modrmmod = @@ -6716,13 +6716,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_c7_modrmreg_06_prefix_02_mo const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c7_modrmreg_06_prefix_01_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2081] // RDRAND Rv + (const void *)&gInstructions[ 2087] // RDRAND Rv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c7_modrmreg_06_prefix_01_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3202] // VMCLEAR Mq + (const void *)&gInstructions[ 3243] // VMCLEAR Mq }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_c7_modrmreg_06_prefix_01_modrmmod = @@ -6737,13 +6737,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_c7_modrmreg_06_prefix_01_mo const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c7_modrmreg_06_prefix_00_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2080] // RDRAND Rv + (const void *)&gInstructions[ 2086] // RDRAND Rv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c7_modrmreg_06_prefix_00_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3341] // VMPTRLD Mq + (const void *)&gInstructions[ 3386] // VMPTRLD Mq }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_c7_modrmreg_06_prefix_00_modrmmod = @@ -6769,13 +6769,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_c7_modrmreg_06_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c7_modrmreg_05_prefix_00_modrmmod_00_auxiliary_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4153] // XSAVES64 M? + (const void *)&gInstructions[ 4202] // XSAVES64 M? }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c7_modrmreg_05_prefix_00_modrmmod_00_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4152] // XSAVES M? + (const void *)&gInstructions[ 4201] // XSAVES M? }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_c7_modrmreg_05_prefix_00_modrmmod_00_auxiliary = @@ -6818,13 +6818,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_c7_modrmreg_05_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c7_modrmreg_04_prefix_00_modrmmod_00_auxiliary_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4149] // XSAVEC64 M? + (const void *)&gInstructions[ 4198] // XSAVEC64 M? }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c7_modrmreg_04_prefix_00_modrmmod_00_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4148] // XSAVEC M? + (const void *)&gInstructions[ 4197] // XSAVEC M? }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_c7_modrmreg_04_prefix_00_modrmmod_00_auxiliary = @@ -6867,13 +6867,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_c7_modrmreg_04_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c7_modrmreg_03_prefix_00_modrmmod_00_auxiliary_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4145] // XRSTORS64 M? + (const void *)&gInstructions[ 4194] // XRSTORS64 M? }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c7_modrmreg_03_prefix_00_modrmmod_00_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4144] // XRSTORS M? + (const void *)&gInstructions[ 4193] // XRSTORS M? }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_c7_modrmreg_03_prefix_00_modrmmod_00_auxiliary = @@ -6969,13 +6969,13 @@ const ND_TABLE_MODRM_REG gLegacyMap_opcode_0f_opcode_c7_modrmreg = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c6_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2490] // SHUFPD Vpd,Wpd,Ib + (const void *)&gInstructions[ 2496] // SHUFPD Vpd,Wpd,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c6_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2491] // SHUFPS Vps,Wps,Ib + (const void *)&gInstructions[ 2497] // SHUFPS Vps,Wps,Ib }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_c6_prefix = @@ -6992,7 +6992,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_c6_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c5_prefix_01_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1721] // PEXTRW Gy,Udq,Ib + (const void *)&gInstructions[ 1723] // PEXTRW Gy,Udq,Ib }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_c5_prefix_01_modrmmod = @@ -7007,7 +7007,7 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_c5_prefix_01_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c5_prefix_00_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1720] // PEXTRW Gy,Nq,Ib + (const void *)&gInstructions[ 1722] // PEXTRW Gy,Nq,Ib }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_c5_prefix_00_modrmmod = @@ -7033,13 +7033,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_c5_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c4_prefix_01_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1766] // PINSRW Vdq,Rd,Ib + (const void *)&gInstructions[ 1768] // PINSRW Vdq,Rd,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c4_prefix_01_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1767] // PINSRW Vdq,Mw,Ib + (const void *)&gInstructions[ 1769] // PINSRW Vdq,Mw,Ib }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_c4_prefix_01_modrmmod = @@ -7054,13 +7054,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_c4_prefix_01_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c4_prefix_00_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1764] // PINSRW Pq,Rd,Ib + (const void *)&gInstructions[ 1766] // PINSRW Pq,Rd,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c4_prefix_00_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1765] // PINSRW Pq,Mw,Ib + (const void *)&gInstructions[ 1767] // PINSRW Pq,Mw,Ib }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_c4_prefix_00_modrmmod = @@ -7147,25 +7147,25 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_c2_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c1_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4070] // XADD Ev,Gv + (const void *)&gInstructions[ 4119] // XADD Ev,Gv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c0_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4069] // XADD Eb,Gb + (const void *)&gInstructions[ 4118] // XADD Eb,Gb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_bf_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1462] // MOVSX Gv,Ew + (const void *)&gInstructions[ 1464] // MOVSX Gv,Ew }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_be_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1461] // MOVSX Gv,Eb + (const void *)&gInstructions[ 1463] // MOVSX Gv,Eb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_bd_auxiliary_04_leaf = @@ -7200,7 +7200,7 @@ const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_bd_auxiliary = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_bc_auxiliary_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2619] // TZCNT Gv,Ev + (const void *)&gInstructions[ 2660] // TZCNT Gv,Ev }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_bc_auxiliary_00_leaf = @@ -7274,13 +7274,13 @@ const ND_TABLE_MODRM_REG gLegacyMap_opcode_0f_opcode_ba_modrmreg = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_b9_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2624] // UD1 Gd,Ed + (const void *)&gInstructions[ 2665] // UD1 Gd,Ed }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_b8_auxiliary_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1837] // POPCNT Gv,Ev + (const void *)&gInstructions[ 1839] // POPCNT Gv,Ev }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_b8_auxiliary_00_leaf = @@ -7309,13 +7309,13 @@ const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_b8_auxiliary = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_b7_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1469] // MOVZX Gv,Ew + (const void *)&gInstructions[ 1471] // MOVZX Gv,Ew }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_b6_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1468] // MOVZX Gv,Eb + (const void *)&gInstructions[ 1470] // MOVZX Gv,Eb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_b5_modrmmod_00_leaf = @@ -7390,7 +7390,7 @@ const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_af_leaf = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_03_modrmreg_06_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2628] // UMWAIT Ry + (const void *)&gInstructions[ 2669] // UMWAIT Ry }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_ae_prefix_03_modrmreg_06_modrmmod = @@ -7420,7 +7420,7 @@ const ND_TABLE_MODRM_REG gLegacyMap_opcode_0f_opcode_ae_prefix_03_modrmreg = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_06_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2627] // UMONITOR mMb + (const void *)&gInstructions[ 2668] // UMONITOR mMb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_06_modrmmod_00_leaf = @@ -7479,13 +7479,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_05_mo const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1936] // PTWRITE Ey + (const void *)&gInstructions[ 1940] // PTWRITE Ey }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_03_modrmmod_01_auxiliary_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4055] // WRGSBASE Ry + (const void *)&gInstructions[ 4102] // WRGSBASE Ry }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_03_modrmmod_01_auxiliary = @@ -7517,7 +7517,7 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_03_mo const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_02_modrmmod_01_auxiliary_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4054] // WRFSBASE Ry + (const void *)&gInstructions[ 4101] // WRFSBASE Ry }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_02_modrmmod_01_auxiliary = @@ -7549,7 +7549,7 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_02_mo const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_01_modrmmod_01_auxiliary_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2073] // RDGSBASE Ry + (const void *)&gInstructions[ 2077] // RDGSBASE Ry }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_01_modrmmod_01_auxiliary = @@ -7581,7 +7581,7 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_01_mo const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_00_modrmmod_01_auxiliary_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2072] // RDFSBASE Ry + (const void *)&gInstructions[ 2076] // RDFSBASE Ry }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_00_modrmmod_01_auxiliary = @@ -7643,7 +7643,7 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_ae_prefix_01_modrmreg_07_mo const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_01_modrmreg_06_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2614] // TPAUSE Ry + (const void *)&gInstructions[ 2649] // TPAUSE Ry }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_01_modrmreg_06_modrmmod_00_leaf = @@ -7679,7 +7679,7 @@ const ND_TABLE_MODRM_REG gLegacyMap_opcode_0f_opcode_ae_prefix_01_modrmreg = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_07_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2357] // SFENCE + (const void *)&gInstructions[ 2363] // SFENCE }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_07_modrmmod_00_leaf = @@ -7706,13 +7706,13 @@ const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_06_ const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_06_modrmmod_00_auxiliary_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4151] // XSAVEOPT64 M? + (const void *)&gInstructions[ 4200] // XSAVEOPT64 M? }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_06_modrmmod_00_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4150] // XSAVEOPT M? + (const void *)&gInstructions[ 4199] // XSAVEOPT M? }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_06_modrmmod_00_auxiliary = @@ -7750,13 +7750,13 @@ const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_05_ const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_05_modrmmod_00_auxiliary_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4143] // XRSTOR64 M? + (const void *)&gInstructions[ 4192] // XRSTOR64 M? }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_05_modrmmod_00_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4142] // XRSTOR M? + (const void *)&gInstructions[ 4191] // XRSTOR M? }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_05_modrmmod_00_auxiliary = @@ -7788,13 +7788,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_05_mo const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_04_modrmmod_00_auxiliary_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4147] // XSAVE64 M? + (const void *)&gInstructions[ 4196] // XSAVE64 M? }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_04_modrmmod_00_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4146] // XSAVE M? + (const void *)&gInstructions[ 4195] // XSAVE M? }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_04_modrmmod_00_auxiliary = @@ -7826,7 +7826,7 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_04_mo const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_03_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2509] // STMXCSR Md + (const void *)&gInstructions[ 2515] // STMXCSR Md }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_03_modrmmod = @@ -7958,13 +7958,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_ae_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ad_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2487] // SHRD Ev,Gv,CL + (const void *)&gInstructions[ 2493] // SHRD Ev,Gv,CL }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ac_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2486] // SHRD Ev,Gv,Ib + (const void *)&gInstructions[ 2492] // SHRD Ev,Gv,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ab_leaf = @@ -7976,31 +7976,31 @@ const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ab_leaf = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_aa_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2186] // RSM + (const void *)&gInstructions[ 2192] // RSM }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_a9_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1828] // POP GS + (const void *)&gInstructions[ 1830] // POP GS }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_a8_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1967] // PUSH GS + (const void *)&gInstructions[ 1971] // PUSH GS }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_a5_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2425] // SHLD Ev,Gv,CL + (const void *)&gInstructions[ 2431] // SHLD Ev,Gv,CL }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_a4_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2424] // SHLD Ev,Gv,Ib + (const void *)&gInstructions[ 2430] // SHLD Ev,Gv,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_a3_leaf = @@ -8018,109 +8018,109 @@ const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_a2_leaf = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_a1_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1827] // POP FS + (const void *)&gInstructions[ 1829] // POP FS }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_a0_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1966] // PUSH FS + (const void *)&gInstructions[ 1970] // PUSH FS }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_9f_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2339] // SETNLE Eb + (const void *)&gInstructions[ 2345] // SETNLE Eb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_9e_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2331] // SETLE Eb + (const void *)&gInstructions[ 2337] // SETLE Eb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_9d_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2337] // SETNL Eb + (const void *)&gInstructions[ 2343] // SETNL Eb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_9c_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2329] // SETL Eb + (const void *)&gInstructions[ 2335] // SETL Eb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_9b_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2343] // SETNP Eb + (const void *)&gInstructions[ 2349] // SETNP Eb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_9a_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2351] // SETP Eb + (const void *)&gInstructions[ 2357] // SETP Eb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_99_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2345] // SETNS Eb + (const void *)&gInstructions[ 2351] // SETNS Eb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_98_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2353] // SETS Eb + (const void *)&gInstructions[ 2359] // SETS Eb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_97_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2333] // SETNBE Eb + (const void *)&gInstructions[ 2339] // SETNBE Eb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_96_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2325] // SETBE Eb + (const void *)&gInstructions[ 2331] // SETBE Eb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_95_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2347] // SETNZ Eb + (const void *)&gInstructions[ 2353] // SETNZ Eb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_94_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2356] // SETZ Eb + (const void *)&gInstructions[ 2362] // SETZ Eb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_93_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2335] // SETNC Eb + (const void *)&gInstructions[ 2341] // SETNC Eb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_92_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2327] // SETC Eb + (const void *)&gInstructions[ 2333] // SETC Eb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_91_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2341] // SETNO Eb + (const void *)&gInstructions[ 2347] // SETNO Eb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_90_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2349] // SETO Eb + (const void *)&gInstructions[ 2355] // SETO Eb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_8f_leaf = @@ -8402,7 +8402,7 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_79_prefix_01_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_79_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3358] // VMWRITE Gy,Ey + (const void *)&gInstructions[ 3403] // VMWRITE Gy,Ey }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_79_prefix = @@ -8446,7 +8446,7 @@ const ND_TABLE_MODRM_REG gLegacyMap_opcode_0f_opcode_78_prefix_01_modrmreg = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_78_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3343] // VMREAD Ey,Gy + (const void *)&gInstructions[ 3388] // VMREAD Ey,Gy }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_78_prefix = @@ -8480,13 +8480,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_77_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_76_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1694] // PCMPEQD Vx,Wx + (const void *)&gInstructions[ 1696] // PCMPEQD Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_76_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1693] // PCMPEQD Pq,Qq + (const void *)&gInstructions[ 1695] // PCMPEQD Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_76_prefix = @@ -8503,13 +8503,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_76_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_75_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1697] // PCMPEQW Vx,Wx + (const void *)&gInstructions[ 1699] // PCMPEQW Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_75_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1696] // PCMPEQW Pq,Qq + (const void *)&gInstructions[ 1698] // PCMPEQW Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_75_prefix = @@ -8526,13 +8526,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_75_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_74_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1692] // PCMPEQB Vx,Wx + (const void *)&gInstructions[ 1694] // PCMPEQB Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_74_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1691] // PCMPEQB Pq,Qq + (const void *)&gInstructions[ 1693] // PCMPEQB Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_74_prefix = @@ -8549,7 +8549,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_74_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_73_prefix_01_modrmreg_07_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1887] // PSLLDQ Ux,Ib + (const void *)&gInstructions[ 1891] // PSLLDQ Ux,Ib }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_73_prefix_01_modrmreg_07_modrmmod = @@ -8564,7 +8564,7 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_73_prefix_01_modrmreg_07_mo const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_73_prefix_01_modrmreg_06_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1889] // PSLLQ Ux,Ib + (const void *)&gInstructions[ 1893] // PSLLQ Ux,Ib }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_73_prefix_01_modrmreg_06_modrmmod = @@ -8579,7 +8579,7 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_73_prefix_01_modrmreg_06_mo const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_73_prefix_01_modrmreg_03_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1909] // PSRLDQ Ux,Ib + (const void *)&gInstructions[ 1913] // PSRLDQ Ux,Ib }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_73_prefix_01_modrmreg_03_modrmmod = @@ -8594,7 +8594,7 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_73_prefix_01_modrmreg_03_mo const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_73_prefix_01_modrmreg_02_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1911] // PSRLQ Ux,Ib + (const void *)&gInstructions[ 1915] // PSRLQ Ux,Ib }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_73_prefix_01_modrmreg_02_modrmmod = @@ -8624,7 +8624,7 @@ const ND_TABLE_MODRM_REG gLegacyMap_opcode_0f_opcode_73_prefix_01_modrmreg = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_73_prefix_00_modrmreg_06_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1888] // PSLLQ Nq,Ib + (const void *)&gInstructions[ 1892] // PSLLQ Nq,Ib }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_73_prefix_00_modrmreg_06_modrmmod = @@ -8639,7 +8639,7 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_73_prefix_00_modrmreg_06_mo const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_73_prefix_00_modrmreg_02_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1910] // PSRLQ Nq,Ib + (const void *)&gInstructions[ 1914] // PSRLQ Nq,Ib }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_73_prefix_00_modrmreg_02_modrmmod = @@ -8680,7 +8680,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_73_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_72_prefix_01_modrmreg_06_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1884] // PSLLD Ux,Ib + (const void *)&gInstructions[ 1888] // PSLLD Ux,Ib }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_72_prefix_01_modrmreg_06_modrmmod = @@ -8695,7 +8695,7 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_72_prefix_01_modrmreg_06_mo const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_72_prefix_01_modrmreg_04_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1898] // PSRAD Ux,Ib + (const void *)&gInstructions[ 1902] // PSRAD Ux,Ib }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_72_prefix_01_modrmreg_04_modrmmod = @@ -8710,7 +8710,7 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_72_prefix_01_modrmreg_04_mo const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_72_prefix_01_modrmreg_02_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1906] // PSRLD Ux,Ib + (const void *)&gInstructions[ 1910] // PSRLD Ux,Ib }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_72_prefix_01_modrmreg_02_modrmmod = @@ -8740,7 +8740,7 @@ const ND_TABLE_MODRM_REG gLegacyMap_opcode_0f_opcode_72_prefix_01_modrmreg = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_72_prefix_00_modrmreg_06_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1883] // PSLLD Nq,Ib + (const void *)&gInstructions[ 1887] // PSLLD Nq,Ib }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_72_prefix_00_modrmreg_06_modrmmod = @@ -8755,7 +8755,7 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_72_prefix_00_modrmreg_06_mo const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_72_prefix_00_modrmreg_04_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1897] // PSRAD Nq,Ib + (const void *)&gInstructions[ 1901] // PSRAD Nq,Ib }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_72_prefix_00_modrmreg_04_modrmmod = @@ -8770,7 +8770,7 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_72_prefix_00_modrmreg_04_mo const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_72_prefix_00_modrmreg_02_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1905] // PSRLD Nq,Ib + (const void *)&gInstructions[ 1909] // PSRLD Nq,Ib }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_72_prefix_00_modrmreg_02_modrmmod = @@ -8811,7 +8811,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_72_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_71_prefix_01_modrmreg_06_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1893] // PSLLW Ux,Ib + (const void *)&gInstructions[ 1897] // PSLLW Ux,Ib }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_71_prefix_01_modrmreg_06_modrmmod = @@ -8826,7 +8826,7 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_71_prefix_01_modrmreg_06_mo const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_71_prefix_01_modrmreg_04_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1902] // PSRAW Ux,Ib + (const void *)&gInstructions[ 1906] // PSRAW Ux,Ib }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_71_prefix_01_modrmreg_04_modrmmod = @@ -8841,7 +8841,7 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_71_prefix_01_modrmreg_04_mo const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_71_prefix_01_modrmreg_02_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1915] // PSRLW Ux,Ib + (const void *)&gInstructions[ 1919] // PSRLW Ux,Ib }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_71_prefix_01_modrmreg_02_modrmmod = @@ -8871,7 +8871,7 @@ const ND_TABLE_MODRM_REG gLegacyMap_opcode_0f_opcode_71_prefix_01_modrmreg = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_71_prefix_00_modrmreg_06_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1892] // PSLLW Nq,Ib + (const void *)&gInstructions[ 1896] // PSLLW Nq,Ib }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_71_prefix_00_modrmreg_06_modrmmod = @@ -8886,7 +8886,7 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_71_prefix_00_modrmreg_06_mo const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_71_prefix_00_modrmreg_04_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1901] // PSRAW Nq,Ib + (const void *)&gInstructions[ 1905] // PSRAW Nq,Ib }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_71_prefix_00_modrmreg_04_modrmmod = @@ -8901,7 +8901,7 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_71_prefix_00_modrmreg_04_mo const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_71_prefix_00_modrmreg_02_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1914] // PSRLW Nq,Ib + (const void *)&gInstructions[ 1918] // PSRLW Nq,Ib }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_71_prefix_00_modrmreg_02_modrmmod = @@ -8942,25 +8942,25 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_71_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_70_prefix_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1875] // PSHUFLW Vx,Wx,Ib + (const void *)&gInstructions[ 1879] // PSHUFLW Vx,Wx,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_70_prefix_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1874] // PSHUFHW Vx,Wx,Ib + (const void *)&gInstructions[ 1878] // PSHUFHW Vx,Wx,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_70_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1873] // PSHUFD Vx,Wx,Ib + (const void *)&gInstructions[ 1877] // PSHUFD Vx,Wx,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_70_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1876] // PSHUFW Pq,Qq,Ib + (const void *)&gInstructions[ 1880] // PSHUFW Pq,Qq,Ib }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_70_prefix = @@ -9075,7 +9075,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_6e_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_6d_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1941] // PUNPCKHQDQ Vx,Wx + (const void *)&gInstructions[ 1945] // PUNPCKHQDQ Vx,Wx }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_6d_prefix = @@ -9092,7 +9092,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_6d_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_6c_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1948] // PUNPCKLQDQ Vx,Wx + (const void *)&gInstructions[ 1952] // PUNPCKLQDQ Vx,Wx }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_6c_prefix = @@ -9109,13 +9109,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_6c_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_6b_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1653] // PACKSSDW Vx,Wx + (const void *)&gInstructions[ 1655] // PACKSSDW Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_6b_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1652] // PACKSSDW Pq,Qq + (const void *)&gInstructions[ 1654] // PACKSSDW Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_6b_prefix = @@ -9132,13 +9132,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_6b_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_6a_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1940] // PUNPCKHDQ Vx,Wx + (const void *)&gInstructions[ 1944] // PUNPCKHDQ Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_6a_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1939] // PUNPCKHDQ Pq,Qq + (const void *)&gInstructions[ 1943] // PUNPCKHDQ Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_6a_prefix = @@ -9155,13 +9155,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_6a_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_69_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1943] // PUNPCKHWD Vx,Wx + (const void *)&gInstructions[ 1947] // PUNPCKHWD Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_69_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1942] // PUNPCKHWD Pq,Qq + (const void *)&gInstructions[ 1946] // PUNPCKHWD Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_69_prefix = @@ -9178,13 +9178,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_69_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_68_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1938] // PUNPCKHBW Vx,Wx + (const void *)&gInstructions[ 1942] // PUNPCKHBW Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_68_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1937] // PUNPCKHBW Pq,Qq + (const void *)&gInstructions[ 1941] // PUNPCKHBW Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_68_prefix = @@ -9201,13 +9201,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_68_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_67_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1658] // PACKUSWB Vx,Wx + (const void *)&gInstructions[ 1660] // PACKUSWB Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_67_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1657] // PACKUSWB Pq,Qq + (const void *)&gInstructions[ 1659] // PACKUSWB Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_67_prefix = @@ -9224,13 +9224,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_67_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_66_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1703] // PCMPGTD Vx,Wx + (const void *)&gInstructions[ 1705] // PCMPGTD Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_66_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1702] // PCMPGTD Pq,Qq + (const void *)&gInstructions[ 1704] // PCMPGTD Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_66_prefix = @@ -9247,13 +9247,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_66_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_65_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1706] // PCMPGTW Vx,Wx + (const void *)&gInstructions[ 1708] // PCMPGTW Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_65_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1705] // PCMPGTW Pq,Qq + (const void *)&gInstructions[ 1707] // PCMPGTW Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_65_prefix = @@ -9270,13 +9270,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_65_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_64_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1701] // PCMPGTB Vx,Wx + (const void *)&gInstructions[ 1703] // PCMPGTB Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_64_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1700] // PCMPGTB Pq,Qq + (const void *)&gInstructions[ 1702] // PCMPGTB Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_64_prefix = @@ -9293,13 +9293,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_64_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_63_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1655] // PACKSSWB Vx,Wx + (const void *)&gInstructions[ 1657] // PACKSSWB Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_63_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1654] // PACKSSWB Pq,Qq + (const void *)&gInstructions[ 1656] // PACKSSWB Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_63_prefix = @@ -9316,13 +9316,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_63_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_62_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1947] // PUNPCKLDQ Vx,Wx + (const void *)&gInstructions[ 1951] // PUNPCKLDQ Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_62_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1946] // PUNPCKLDQ Pq,Qd + (const void *)&gInstructions[ 1950] // PUNPCKLDQ Pq,Qd }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_62_prefix = @@ -9339,13 +9339,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_62_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_61_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1950] // PUNPCKLWD Vx,Wx + (const void *)&gInstructions[ 1954] // PUNPCKLWD Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_61_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1949] // PUNPCKLWD Pq,Qd + (const void *)&gInstructions[ 1953] // PUNPCKLWD Pq,Qd }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_61_prefix = @@ -9362,13 +9362,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_61_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_60_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1945] // PUNPCKLBW Vx,Wx + (const void *)&gInstructions[ 1949] // PUNPCKLBW Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_60_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1944] // PUNPCKLBW Pq,Qd + (const void *)&gInstructions[ 1948] // PUNPCKLBW Pq,Qd }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_60_prefix = @@ -9490,25 +9490,25 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_5d_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_5c_prefix_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2579] // SUBSD Vsd,Wsd + (const void *)&gInstructions[ 2585] // SUBSD Vsd,Wsd }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_5c_prefix_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2580] // SUBSS Vss,Wss + (const void *)&gInstructions[ 2586] // SUBSS Vss,Wss }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_5c_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2577] // SUBPD Vpd,Wpd + (const void *)&gInstructions[ 2583] // SUBPD Vpd,Wpd }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_5c_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2578] // SUBPS Vps,Wps + (const void *)&gInstructions[ 2584] // SUBPS Vps,Wps }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_5c_prefix = @@ -9589,25 +9589,25 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_5a_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_59_prefix_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1481] // MULSD Vsd,Wsd + (const void *)&gInstructions[ 1483] // MULSD Vsd,Wsd }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_59_prefix_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1482] // MULSS Vss,Wss + (const void *)&gInstructions[ 1484] // MULSS Vss,Wss }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_59_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1479] // MULPD Vpd,Wpd + (const void *)&gInstructions[ 1481] // MULPD Vpd,Wpd }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_59_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1480] // MULPS Vps,Wps + (const void *)&gInstructions[ 1482] // MULPS Vps,Wps }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_59_prefix = @@ -9659,13 +9659,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_58_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_57_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4139] // XORPD Vpd,Wpd + (const void *)&gInstructions[ 4188] // XORPD Vpd,Wpd }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_57_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4140] // XORPS Vps,Wps + (const void *)&gInstructions[ 4189] // XORPS Vps,Wps }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_57_prefix = @@ -9682,13 +9682,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_57_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_56_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1634] // ORPD Vpd,Wpd + (const void *)&gInstructions[ 1636] // ORPD Vpd,Wpd }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_56_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1635] // ORPS Vps,Wps + (const void *)&gInstructions[ 1637] // ORPS Vps,Wps }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_56_prefix = @@ -9751,13 +9751,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_54_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_53_prefix_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2029] // RCPSS Vss,Wss + (const void *)&gInstructions[ 2033] // RCPSS Vss,Wss }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_53_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2028] // RCPPS Vps,Wps + (const void *)&gInstructions[ 2032] // RCPPS Vps,Wps }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_53_prefix = @@ -9774,13 +9774,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_53_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_52_prefix_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2188] // RSQRTSS Vss,Wss + (const void *)&gInstructions[ 2194] // RSQRTSS Vss,Wss }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_52_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2187] // RSQRTPS Vps,Wps + (const void *)&gInstructions[ 2193] // RSQRTPS Vps,Wps }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_52_prefix = @@ -9797,25 +9797,25 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_52_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_51_prefix_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2502] // SQRTSD Vsd,Wsd + (const void *)&gInstructions[ 2508] // SQRTSD Vsd,Wsd }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_51_prefix_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2503] // SQRTSS Vss,Wss + (const void *)&gInstructions[ 2509] // SQRTSS Vss,Wss }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_51_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2500] // SQRTPD Vpd,Wpd + (const void *)&gInstructions[ 2506] // SQRTPD Vpd,Wpd }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_51_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2501] // SQRTPS Vps,Wps + (const void *)&gInstructions[ 2507] // SQRTPS Vps,Wps }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_51_prefix = @@ -10076,7 +10076,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_ce_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_cc_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2362] // SHA1RNDS4 Vdq,Wdq,Ib + (const void *)&gInstructions[ 2368] // SHA1RNDS4 Vdq,Wdq,Ib }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_cc_prefix = @@ -10093,7 +10093,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_cc_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_63_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1707] // PCMPISTRI Vdq,Wdq,Ib + (const void *)&gInstructions[ 1709] // PCMPISTRI Vdq,Wdq,Ib }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_63_prefix = @@ -10110,7 +10110,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_63_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_62_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1708] // PCMPISTRM Vdq,Wdq,Ib + (const void *)&gInstructions[ 1710] // PCMPISTRM Vdq,Wdq,Ib }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_62_prefix = @@ -10127,7 +10127,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_62_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_61_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1698] // PCMPESTRI Vdq,Wdq,Ib + (const void *)&gInstructions[ 1700] // PCMPESTRI Vdq,Wdq,Ib }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_61_prefix = @@ -10144,7 +10144,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_61_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_60_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1699] // PCMPESTRM Vdq,Wdq,Ib + (const void *)&gInstructions[ 1701] // PCMPESTRM Vdq,Wdq,Ib }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_60_prefix = @@ -10161,7 +10161,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_60_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_44_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1690] // PCLMULQDQ Vdq,Wdq,Ib + (const void *)&gInstructions[ 1692] // PCLMULQDQ Vdq,Wdq,Ib }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_44_prefix = @@ -10178,7 +10178,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_44_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_42_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1470] // MPSADBW Vdq,Wdq,Ib + (const void *)&gInstructions[ 1472] // MPSADBW Vdq,Wdq,Ib }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_42_prefix = @@ -10229,13 +10229,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_40_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_22_prefix_01_auxiliary_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1763] // PINSRQ Vdq,Eq,Ib + (const void *)&gInstructions[ 1765] // PINSRQ Vdq,Eq,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_22_prefix_01_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1762] // PINSRD Vdq,Ed,Ib + (const void *)&gInstructions[ 1764] // PINSRD Vdq,Ed,Ib }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_3a_opcode_22_prefix_01_auxiliary = @@ -10301,13 +10301,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_21_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_20_prefix_01_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1761] // PINSRB Vdq,Ry,Ib + (const void *)&gInstructions[ 1763] // PINSRB Vdq,Ry,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_20_prefix_01_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1760] // PINSRB Vdq,Mb,Ib + (const void *)&gInstructions[ 1762] // PINSRB Vdq,Mb,Ib }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_3a_opcode_20_prefix_01_modrmmod = @@ -10350,13 +10350,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_17_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_16_prefix_01_modrmmod_01_auxiliary_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1719] // PEXTRQ Ry,Vdq,Ib + (const void *)&gInstructions[ 1721] // PEXTRQ Ry,Vdq,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_16_prefix_01_modrmmod_01_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1717] // PEXTRD Ry,Vdq,Ib + (const void *)&gInstructions[ 1719] // PEXTRD Ry,Vdq,Ib }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_3a_opcode_16_prefix_01_modrmmod_01_auxiliary = @@ -10379,13 +10379,13 @@ const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_3a_opcode_16_prefix_01_modr const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_16_prefix_01_modrmmod_00_auxiliary_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1718] // PEXTRQ Mq,Vdq,Ib + (const void *)&gInstructions[ 1720] // PEXTRQ Mq,Vdq,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_16_prefix_01_modrmmod_00_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1716] // PEXTRD Md,Vdq,Ib + (const void *)&gInstructions[ 1718] // PEXTRD Md,Vdq,Ib }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_3a_opcode_16_prefix_01_modrmmod_00_auxiliary = @@ -10428,13 +10428,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_16_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_15_prefix_01_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1723] // PEXTRW Ry,Vdq,Ib + (const void *)&gInstructions[ 1725] // PEXTRW Ry,Vdq,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_15_prefix_01_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1722] // PEXTRW Mw,Vdq,Ib + (const void *)&gInstructions[ 1724] // PEXTRW Mw,Vdq,Ib }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_3a_opcode_15_prefix_01_modrmmod = @@ -10460,13 +10460,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_15_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_14_prefix_01_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1715] // PEXTRB Ry,Vdq,Ib + (const void *)&gInstructions[ 1717] // PEXTRB Ry,Vdq,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_14_prefix_01_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1714] // PEXTRB Mb,Vdq,Ib + (const void *)&gInstructions[ 1716] // PEXTRB Mb,Vdq,Ib }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_3a_opcode_14_prefix_01_modrmmod = @@ -10492,13 +10492,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_14_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_0f_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1676] // PALIGNR Vx,Wx,Ib + (const void *)&gInstructions[ 1678] // PALIGNR Vx,Wx,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_0f_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1675] // PALIGNR Pq,Qq,Ib + (const void *)&gInstructions[ 1677] // PALIGNR Pq,Qq,Ib }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_0f_prefix = @@ -10515,7 +10515,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_0f_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_0e_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1688] // PBLENDW Vx,Wx,Ib + (const void *)&gInstructions[ 1690] // PBLENDW Vx,Wx,Ib }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_0e_prefix = @@ -10566,7 +10566,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_0c_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_0b_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2184] // ROUNDSD Vsd,Wsd,Ib + (const void *)&gInstructions[ 2190] // ROUNDSD Vsd,Wsd,Ib }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_0b_prefix = @@ -10583,7 +10583,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_0b_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_0a_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2185] // ROUNDSS Vss,Wss,Ib + (const void *)&gInstructions[ 2191] // ROUNDSS Vss,Wss,Ib }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_0a_prefix = @@ -10600,7 +10600,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_0a_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_09_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2182] // ROUNDPD Vx,Wx,Ib + (const void *)&gInstructions[ 2188] // ROUNDPD Vx,Wx,Ib }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_09_prefix = @@ -10617,7 +10617,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_09_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_08_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2183] // ROUNDPS Vx,Wx,Ib + (const void *)&gInstructions[ 2189] // ROUNDPS Vx,Wx,Ib }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_08_prefix = @@ -11046,7 +11046,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_f9_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_f8_prefix_03_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2635] // URDMSR Rq,Gq + (const void *)&gInstructions[ 2676] // URDMSR Rq,Gq }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_f8_prefix_03_modrmmod_00_leaf = @@ -11067,7 +11067,7 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_f8_prefix_03_modr const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_f8_prefix_02_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2639] // UWRMSR Gq,Rq + (const void *)&gInstructions[ 2680] // UWRMSR Gq,Rq }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_f8_prefix_02_modrmmod_00_leaf = @@ -11126,13 +11126,13 @@ const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_f6_prefix_01_le const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_f6_prefix_00_modrmmod_00_auxiliary_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4063] // WRSSQ My,Gy + (const void *)&gInstructions[ 4112] // WRSSQ My,Gy }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_f6_prefix_00_modrmmod_00_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4061] // WRSSD My,Gy + (const void *)&gInstructions[ 4110] // WRSSD My,Gy }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_38_opcode_f6_prefix_00_modrmmod_00_auxiliary = @@ -11175,13 +11175,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_f6_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_f5_prefix_01_modrmmod_00_auxiliary_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4067] // WRUSSQ My,Gy + (const void *)&gInstructions[ 4116] // WRUSSQ My,Gy }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_f5_prefix_01_modrmmod_00_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4065] // WRUSSD My,Gy + (const void *)&gInstructions[ 4114] // WRUSSD My,Gy }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_38_opcode_f5_prefix_01_modrmmod_00_auxiliary = @@ -11572,7 +11572,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_cf_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_cd_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2364] // SHA256MSG2 Vdq,Wdq + (const void *)&gInstructions[ 2370] // SHA256MSG2 Vdq,Wdq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_cd_prefix = @@ -11589,7 +11589,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_cd_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_cc_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2363] // SHA256MSG1 Vdq,Wdq + (const void *)&gInstructions[ 2369] // SHA256MSG1 Vdq,Wdq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_cc_prefix = @@ -11606,7 +11606,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_cc_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_cb_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2365] // SHA256RNDS2 Vdq,Wdq + (const void *)&gInstructions[ 2371] // SHA256RNDS2 Vdq,Wdq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_cb_prefix = @@ -11623,7 +11623,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_cb_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_ca_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2360] // SHA1MSG2 Vdq,Wdq + (const void *)&gInstructions[ 2366] // SHA1MSG2 Vdq,Wdq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_ca_prefix = @@ -11640,7 +11640,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_ca_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_c9_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2359] // SHA1MSG1 Vdq,Wdq + (const void *)&gInstructions[ 2365] // SHA1MSG1 Vdq,Wdq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_c9_prefix = @@ -11657,7 +11657,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_c9_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_c8_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2361] // SHA1NEXTE Vdq,Wdq + (const void *)&gInstructions[ 2367] // SHA1NEXTE Vdq,Wdq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_c8_prefix = @@ -11671,6 +11671,36 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_c8_prefix = } }; +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_8b_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1448] // MOVRS Gv,Mv +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_8b_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_8b_modrmmod_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_8a_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1447] // MOVRS Gb,Mb +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_8a_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_8a_modrmmod_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_82_prefix_01_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, @@ -11752,7 +11782,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_80_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_41_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1751] // PHMINPOSUW Vdq,Wdq + (const void *)&gInstructions[ 1753] // PHMINPOSUW Vdq,Wdq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_41_prefix = @@ -11769,7 +11799,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_41_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_40_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1810] // PMULLD Vx,Wx + (const void *)&gInstructions[ 1812] // PMULLD Vx,Wx }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_40_prefix = @@ -11786,7 +11816,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_40_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_3f_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1778] // PMAXUD Vx,Wx + (const void *)&gInstructions[ 1780] // PMAXUD Vx,Wx }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_3f_prefix = @@ -11803,7 +11833,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_3f_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_3e_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1779] // PMAXUW Vx,Wx + (const void *)&gInstructions[ 1781] // PMAXUW Vx,Wx }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_3e_prefix = @@ -11820,7 +11850,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_3e_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_3d_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1773] // PMAXSD Vx,Wx + (const void *)&gInstructions[ 1775] // PMAXSD Vx,Wx }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_3d_prefix = @@ -11837,7 +11867,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_3d_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_3c_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1772] // PMAXSB Vx,Wx + (const void *)&gInstructions[ 1774] // PMAXSB Vx,Wx }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_3c_prefix = @@ -11854,7 +11884,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_3c_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_3b_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1786] // PMINUD Vx,Wx + (const void *)&gInstructions[ 1788] // PMINUD Vx,Wx }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_3b_prefix = @@ -11871,7 +11901,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_3b_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_3a_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1787] // PMINUW Vx,Wx + (const void *)&gInstructions[ 1789] // PMINUW Vx,Wx }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_3a_prefix = @@ -11888,7 +11918,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_3a_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_39_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1781] // PMINSD Vx,Wx + (const void *)&gInstructions[ 1783] // PMINSD Vx,Wx }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_39_prefix = @@ -11905,7 +11935,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_39_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_38_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1780] // PMINSB Vx,Wx + (const void *)&gInstructions[ 1782] // PMINSB Vx,Wx }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_38_prefix = @@ -11922,7 +11952,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_38_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_37_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1704] // PCMPGTQ Vx,Wx + (const void *)&gInstructions[ 1706] // PCMPGTQ Vx,Wx }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_37_prefix = @@ -11939,7 +11969,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_37_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_35_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1799] // PMOVZXDQ Vdq,Wq + (const void *)&gInstructions[ 1801] // PMOVZXDQ Vdq,Wq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_35_prefix = @@ -11956,7 +11986,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_35_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_34_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1801] // PMOVZXWQ Vdq,Wd + (const void *)&gInstructions[ 1803] // PMOVZXWQ Vdq,Wd }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_34_prefix = @@ -11973,7 +12003,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_34_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_33_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1800] // PMOVZXWD Vdq,Wq + (const void *)&gInstructions[ 1802] // PMOVZXWD Vdq,Wq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_33_prefix = @@ -11990,7 +12020,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_33_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_32_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1797] // PMOVZXBQ Vdq,Ww + (const void *)&gInstructions[ 1799] // PMOVZXBQ Vdq,Ww }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_32_prefix = @@ -12007,7 +12037,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_32_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_31_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1796] // PMOVZXBD Vdq,Wd + (const void *)&gInstructions[ 1798] // PMOVZXBD Vdq,Wd }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_31_prefix = @@ -12024,7 +12054,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_31_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_30_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1798] // PMOVZXBW Vdq,Wq + (const void *)&gInstructions[ 1800] // PMOVZXBW Vdq,Wq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_30_prefix = @@ -12041,7 +12071,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_30_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_2b_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1656] // PACKUSDW Vx,Wx + (const void *)&gInstructions[ 1658] // PACKUSDW Vx,Wx }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_2b_prefix = @@ -12084,7 +12114,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_2a_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_29_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1695] // PCMPEQQ Vx,Wx + (const void *)&gInstructions[ 1697] // PCMPEQQ Vx,Wx }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_29_prefix = @@ -12101,7 +12131,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_29_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_28_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1802] // PMULDQ Vx,Wx + (const void *)&gInstructions[ 1804] // PMULDQ Vx,Wx }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_28_prefix = @@ -12118,7 +12148,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_28_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_25_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1793] // PMOVSXDQ Vdq,Wq + (const void *)&gInstructions[ 1795] // PMOVSXDQ Vdq,Wq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_25_prefix = @@ -12135,7 +12165,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_25_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_24_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1795] // PMOVSXWQ Vdq,Wd + (const void *)&gInstructions[ 1797] // PMOVSXWQ Vdq,Wd }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_24_prefix = @@ -12152,7 +12182,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_24_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_23_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1794] // PMOVSXWD Vdq,Wq + (const void *)&gInstructions[ 1796] // PMOVSXWD Vdq,Wq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_23_prefix = @@ -12169,7 +12199,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_23_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_22_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1791] // PMOVSXBQ Vdq,Ww + (const void *)&gInstructions[ 1793] // PMOVSXBQ Vdq,Ww }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_22_prefix = @@ -12186,7 +12216,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_22_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_21_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1790] // PMOVSXBD Vdq,Wd + (const void *)&gInstructions[ 1792] // PMOVSXBD Vdq,Wd }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_21_prefix = @@ -12203,7 +12233,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_21_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_20_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1792] // PMOVSXBW Vdq,Wq + (const void *)&gInstructions[ 1794] // PMOVSXBW Vdq,Wq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_20_prefix = @@ -12220,13 +12250,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_20_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_1e_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1649] // PABSD Vx,Wx + (const void *)&gInstructions[ 1651] // PABSD Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_1e_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1648] // PABSD Pq,Qq + (const void *)&gInstructions[ 1650] // PABSD Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_1e_prefix = @@ -12243,13 +12273,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_1e_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_1d_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1651] // PABSW Vx,Wx + (const void *)&gInstructions[ 1653] // PABSW Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_1d_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1650] // PABSW Pq,Qq + (const void *)&gInstructions[ 1652] // PABSW Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_1d_prefix = @@ -12266,13 +12296,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_1d_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_1c_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1647] // PABSB Vx,Wx + (const void *)&gInstructions[ 1649] // PABSB Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_1c_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1646] // PABSB Pq,Qq + (const void *)&gInstructions[ 1648] // PABSB Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_1c_prefix = @@ -12289,7 +12319,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_1c_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_17_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1935] // PTEST Vdq,Wdq + (const void *)&gInstructions[ 1939] // PTEST Vdq,Wdq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_17_prefix = @@ -12340,7 +12370,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_14_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_10_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1687] // PBLENDVB Vdq,Wdq + (const void *)&gInstructions[ 1689] // PBLENDVB Vdq,Wdq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_10_prefix = @@ -12357,13 +12387,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_10_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_0b_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1804] // PMULHRSW Vx,Wx + (const void *)&gInstructions[ 1806] // PMULHRSW Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_0b_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1803] // PMULHRSW Pq,Qq + (const void *)&gInstructions[ 1805] // PMULHRSW Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_0b_prefix = @@ -12380,13 +12410,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_0b_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_0a_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1880] // PSIGND Vx,Wx + (const void *)&gInstructions[ 1884] // PSIGND Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_0a_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1879] // PSIGND Pq,Qq + (const void *)&gInstructions[ 1883] // PSIGND Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_0a_prefix = @@ -12403,13 +12433,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_0a_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_09_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1882] // PSIGNW Vx,Wx + (const void *)&gInstructions[ 1886] // PSIGNW Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_09_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1881] // PSIGNW Pq,Qq + (const void *)&gInstructions[ 1885] // PSIGNW Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_09_prefix = @@ -12426,13 +12456,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_09_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_08_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1878] // PSIGNB Vx,Wx + (const void *)&gInstructions[ 1882] // PSIGNB Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_08_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1877] // PSIGNB Pq,Qq + (const void *)&gInstructions[ 1881] // PSIGNB Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_08_prefix = @@ -12449,13 +12479,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_08_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_07_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1755] // PHSUBSW Vx,Wx + (const void *)&gInstructions[ 1757] // PHSUBSW Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_07_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1754] // PHSUBSW Pq,Qq + (const void *)&gInstructions[ 1756] // PHSUBSW Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_07_prefix = @@ -12472,13 +12502,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_07_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_06_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1753] // PHSUBD Vx,Wx + (const void *)&gInstructions[ 1755] // PHSUBD Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_06_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1752] // PHSUBD Pq,Qq + (const void *)&gInstructions[ 1754] // PHSUBD Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_06_prefix = @@ -12495,13 +12525,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_06_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_05_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1757] // PHSUBW Vx,Wx + (const void *)&gInstructions[ 1759] // PHSUBW Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_05_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1756] // PHSUBW Pq,Qq + (const void *)&gInstructions[ 1758] // PHSUBW Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_05_prefix = @@ -12518,13 +12548,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_05_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_04_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1769] // PMADDUBSW Vx,Wx + (const void *)&gInstructions[ 1771] // PMADDUBSW Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_04_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1768] // PMADDUBSW Pq,Qq + (const void *)&gInstructions[ 1770] // PMADDUBSW Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_04_prefix = @@ -12541,13 +12571,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_04_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_03_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1748] // PHADDSW Vx,Wx + (const void *)&gInstructions[ 1750] // PHADDSW Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_03_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1747] // PHADDSW Pq,Qq + (const void *)&gInstructions[ 1749] // PHADDSW Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_03_prefix = @@ -12564,13 +12594,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_03_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_02_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1746] // PHADDD Vx,Wx + (const void *)&gInstructions[ 1748] // PHADDD Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_02_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1745] // PHADDD Pq,Qq + (const void *)&gInstructions[ 1747] // PHADDD Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_02_prefix = @@ -12587,13 +12617,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_02_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_01_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1750] // PHADDW Vx,Wx + (const void *)&gInstructions[ 1752] // PHADDW Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_01_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1749] // PHADDW Pq,Qq + (const void *)&gInstructions[ 1751] // PHADDW Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_01_prefix = @@ -12610,13 +12640,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_01_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_00_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1872] // PSHUFB Vx,Wx + (const void *)&gInstructions[ 1876] // PSHUFB Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_00_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1871] // PSHUFB Pq,Qq + (const void *)&gInstructions[ 1875] // PSHUFB Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_00_prefix = @@ -12772,8 +12802,8 @@ const ND_TABLE_OPCODE gLegacyMap_opcode_0f_opcode_38_opcode = /* 87 */ (const void *)ND_NULL, /* 88 */ (const void *)ND_NULL, /* 89 */ (const void *)ND_NULL, - /* 8a */ (const void *)ND_NULL, - /* 8b */ (const void *)ND_NULL, + /* 8a */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_8a_modrmmod, + /* 8b */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_8b_modrmmod, /* 8c */ (const void *)ND_NULL, /* 8d */ (const void *)ND_NULL, /* 8e */ (const void *)ND_NULL, @@ -12913,37 +12943,37 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_37_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_35_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2584] // SYSEXIT + (const void *)&gInstructions[ 2590] // SYSEXIT }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_34_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2583] // SYSENTER + (const void *)&gInstructions[ 2589] // SYSENTER }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_33_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2078] // RDPMC + (const void *)&gInstructions[ 2084] // RDPMC }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_32_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2074] // RDMSR + (const void *)&gInstructions[ 2079] // RDMSR }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_31_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2086] // RDTSC + (const void *)&gInstructions[ 2092] // RDTSC }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_30_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4056] // WRMSR + (const void *)&gInstructions[ 4103] // WRMSR }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_2f_prefix_01_leaf = @@ -12972,13 +13002,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_2f_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_2e_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2621] // UCOMISD Vsd,Wsd + (const void *)&gInstructions[ 2662] // UCOMISD Vsd,Wsd }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_2e_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2622] // UCOMISS Vss,Wss + (const void *)&gInstructions[ 2663] // UCOMISS Vss,Wss }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_2e_prefix = @@ -13253,31 +13283,31 @@ const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_20_leaf = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1f_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1534] // NOP Ev,Gv + (const void *)&gInstructions[ 1536] // NOP Ev,Gv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_modrmmod_01_modrmrm_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1571] // NOP Rv,Gv + (const void *)&gInstructions[ 1573] // NOP Rv,Gv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_modrmmod_01_modrmrm_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1570] // NOP Rv,Gv + (const void *)&gInstructions[ 1572] // NOP Rv,Gv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_modrmmod_01_modrmrm_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1569] // NOP Rv,Gv + (const void *)&gInstructions[ 1571] // NOP Rv,Gv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_modrmmod_01_modrmrm_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1568] // NOP Rv,Gv + (const void *)&gInstructions[ 1570] // NOP Rv,Gv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_modrmmod_01_modrmrm_03_auxiliary_04_leaf = @@ -13289,7 +13319,7 @@ const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07 const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_modrmmod_01_modrmrm_03_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1567] // NOP Rv,Gv + (const void *)&gInstructions[ 1569] // NOP Rv,Gv }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_modrmmod_01_modrmrm_03_auxiliary = @@ -13318,7 +13348,7 @@ const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07 const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_modrmmod_01_modrmrm_02_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1566] // NOP Rv,Gv + (const void *)&gInstructions[ 1568] // NOP Rv,Gv }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_modrmmod_01_modrmrm_02_auxiliary = @@ -13341,13 +13371,13 @@ const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_m const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_modrmmod_01_modrmrm_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1565] // NOP Rv,Gv + (const void *)&gInstructions[ 1567] // NOP Rv,Gv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_modrmmod_01_modrmrm_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1564] // NOP Rv,Gv + (const void *)&gInstructions[ 1566] // NOP Rv,Gv }; const ND_TABLE_MODRM_RM gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_modrmmod_01_modrmrm = @@ -13368,7 +13398,7 @@ const ND_TABLE_MODRM_RM gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_mo const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1563] // NOP Mv,Gv + (const void *)&gInstructions[ 1565] // NOP Mv,Gv }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_modrmmod = @@ -13383,13 +13413,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_m const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_06_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1562] // NOP Rv,Gv + (const void *)&gInstructions[ 1564] // NOP Rv,Gv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_06_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1561] // NOP Mv,Gv + (const void *)&gInstructions[ 1563] // NOP Mv,Gv }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_06_modrmmod = @@ -13404,13 +13434,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_06_m const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_05_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1560] // NOP Rv,Gv + (const void *)&gInstructions[ 1562] // NOP Rv,Gv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_05_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1559] // NOP Mv,Gv + (const void *)&gInstructions[ 1561] // NOP Mv,Gv }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_05_modrmmod = @@ -13425,13 +13455,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_05_m const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_04_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1558] // NOP Rv,Gv + (const void *)&gInstructions[ 1560] // NOP Rv,Gv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_04_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1557] // NOP Mv,Gv + (const void *)&gInstructions[ 1559] // NOP Mv,Gv }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_04_modrmmod = @@ -13446,13 +13476,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_04_m const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_03_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1556] // NOP Rv,Gv + (const void *)&gInstructions[ 1558] // NOP Rv,Gv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_03_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1555] // NOP Mv,Gv + (const void *)&gInstructions[ 1557] // NOP Mv,Gv }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_03_modrmmod = @@ -13467,13 +13497,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_03_m const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_02_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1554] // NOP Rv,Gv + (const void *)&gInstructions[ 1556] // NOP Rv,Gv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_02_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1553] // NOP Mv,Gv + (const void *)&gInstructions[ 1555] // NOP Mv,Gv }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_02_modrmmod = @@ -13488,13 +13518,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_02_m const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_01_modrmmod_01_auxiliary_04_auxiliary_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2085] // RDSSPQ Rq + (const void *)&gInstructions[ 2091] // RDSSPQ Rq }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_01_modrmmod_01_auxiliary_04_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2084] // RDSSPD Rd + (const void *)&gInstructions[ 2090] // RDSSPD Rd }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_01_modrmmod_01_auxiliary_04_auxiliary = @@ -13517,7 +13547,7 @@ const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_01_m const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_01_modrmmod_01_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1552] // NOP Rv,Gv + (const void *)&gInstructions[ 1554] // NOP Rv,Gv }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_01_modrmmod_01_auxiliary = @@ -13540,7 +13570,7 @@ const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_01_m const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_01_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1551] // NOP Mv,Gv + (const void *)&gInstructions[ 1553] // NOP Mv,Gv }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_01_modrmmod = @@ -13555,13 +13585,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_01_m const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_00_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1550] // NOP Rv,Gv + (const void *)&gInstructions[ 1552] // NOP Rv,Gv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_00_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1549] // NOP Mv,Gv + (const void *)&gInstructions[ 1551] // NOP Mv,Gv }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_00_modrmmod = @@ -13591,7 +13621,7 @@ const ND_TABLE_MODRM_REG gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1533] // NOP Ev,Gv + (const void *)&gInstructions[ 1535] // NOP Ev,Gv }; const ND_TABLE_FEATURE gLegacyMap_opcode_0f_opcode_1e_feature = @@ -13612,73 +13642,73 @@ const ND_TABLE_FEATURE gLegacyMap_opcode_0f_opcode_1e_feature = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1d_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1532] // NOP Ev,Gv + (const void *)&gInstructions[ 1534] // NOP Ev,Gv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1c_feature_03_modrmreg_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1548] // NOP Ev,Gv + (const void *)&gInstructions[ 1550] // NOP Ev,Gv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1c_feature_03_modrmreg_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1547] // NOP Ev,Gv + (const void *)&gInstructions[ 1549] // NOP Ev,Gv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1c_feature_03_modrmreg_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1546] // NOP Ev,Gv + (const void *)&gInstructions[ 1548] // NOP Ev,Gv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1c_feature_03_modrmreg_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1545] // NOP Ev,Gv + (const void *)&gInstructions[ 1547] // NOP Ev,Gv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1c_feature_03_modrmreg_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1544] // NOP Ev,Gv + (const void *)&gInstructions[ 1546] // NOP Ev,Gv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1c_feature_03_modrmreg_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1543] // NOP Ev,Gv + (const void *)&gInstructions[ 1545] // NOP Ev,Gv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1c_feature_03_modrmreg_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1542] // NOP Ev,Gv + (const void *)&gInstructions[ 1544] // NOP Ev,Gv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1c_feature_03_modrmreg_00_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1541] // NOP Ev,Gv + (const void *)&gInstructions[ 1543] // NOP Ev,Gv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1c_feature_03_modrmreg_00_modrmmod_00_prefix_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1540] // NOP Ev,Gv + (const void *)&gInstructions[ 1542] // NOP Ev,Gv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1c_feature_03_modrmreg_00_modrmmod_00_prefix_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1539] // NOP Ev,Gv + (const void *)&gInstructions[ 1541] // NOP Ev,Gv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1c_feature_03_modrmreg_00_modrmmod_00_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1538] // NOP Ev,Gv + (const void *)&gInstructions[ 1540] // NOP Ev,Gv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1c_feature_03_modrmreg_00_modrmmod_00_prefix_00_leaf = @@ -13725,7 +13755,7 @@ const ND_TABLE_MODRM_REG gLegacyMap_opcode_0f_opcode_1c_feature_03_modrmreg = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1c_feature_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1531] // NOP Ev,Gv + (const void *)&gInstructions[ 1533] // NOP Ev,Gv }; const ND_TABLE_FEATURE gLegacyMap_opcode_0f_opcode_1c_feature = @@ -13752,7 +13782,7 @@ const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1b_feature_01_prefix_03_l const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1b_feature_01_prefix_02_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1537] // NOP Gv,Ev + (const void *)&gInstructions[ 1539] // NOP Gv,Ev }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1b_feature_01_prefix_02_modrmmod_00_leaf = @@ -13779,7 +13809,7 @@ const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1b_feature_01_prefix_01_l const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1b_feature_01_prefix_00_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1536] // NOP Gv,Ev + (const void *)&gInstructions[ 1538] // NOP Gv,Ev }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1b_feature_01_prefix_00_modrmmod_00_leaf = @@ -13811,7 +13841,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_1b_feature_01_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1b_feature_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1530] // NOP Gv,Ev + (const void *)&gInstructions[ 1532] // NOP Gv,Ev }; const ND_TABLE_FEATURE gLegacyMap_opcode_0f_opcode_1b_feature = @@ -13850,7 +13880,7 @@ const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1a_feature_01_prefix_01_l const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1a_feature_01_prefix_00_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1535] // NOP Gv,Ev + (const void *)&gInstructions[ 1537] // NOP Gv,Ev }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1a_feature_01_prefix_00_modrmmod_00_leaf = @@ -13882,7 +13912,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_1a_feature_01_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1a_feature_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1529] // NOP Ev,Gv + (const void *)&gInstructions[ 1531] // NOP Ev,Gv }; const ND_TABLE_FEATURE gLegacyMap_opcode_0f_opcode_1a_feature = @@ -13903,25 +13933,25 @@ const ND_TABLE_FEATURE gLegacyMap_opcode_0f_opcode_1a_feature = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_19_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1518] // NOP Ev + (const void *)&gInstructions[ 1520] // NOP Ev }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_07_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1528] // NOP Ev + (const void *)&gInstructions[ 1530] // NOP Ev }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_07_modrmmod_00_auxiliary_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1856] // PREFETCHIT0 Mb + (const void *)&gInstructions[ 1858] // PREFETCHIT0 Mb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_07_modrmmod_00_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1527] // NOP Ev + (const void *)&gInstructions[ 1529] // NOP Ev }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_07_modrmmod_00_auxiliary = @@ -13953,19 +13983,19 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_07_m const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_06_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1526] // NOP Ev + (const void *)&gInstructions[ 1528] // NOP Ev }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_06_modrmmod_00_auxiliary_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1857] // PREFETCHIT1 Mb + (const void *)&gInstructions[ 1859] // PREFETCHIT1 Mb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_06_modrmmod_00_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1525] // NOP Ev + (const void *)&gInstructions[ 1527] // NOP Ev }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_06_modrmmod_00_auxiliary = @@ -13997,25 +14027,40 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_06_m const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1524] // NOP Ev + (const void *)&gInstructions[ 1526] // NOP Ev }; -const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_04_leaf = +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_04_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1523] // NOP Ev + (const void *)&gInstructions[ 1525] // NOP Ev +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_04_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1864] // PREFETCHRST2 Mb +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_04_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_04_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_04_modrmmod_01_leaf, + } }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_03_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1522] // NOP Ev + (const void *)&gInstructions[ 1524] // NOP Ev }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_03_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1866] // PREFETCHT2 Mb + (const void *)&gInstructions[ 1870] // PREFETCHT2 Mb }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_03_modrmmod = @@ -14030,13 +14075,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_03_m const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_02_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1521] // NOP Ev + (const void *)&gInstructions[ 1523] // NOP Ev }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_02_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1864] // PREFETCHT1 Mb + (const void *)&gInstructions[ 1868] // PREFETCHT1 Mb }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_02_modrmmod = @@ -14051,13 +14096,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_02_m const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_01_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1520] // NOP Ev + (const void *)&gInstructions[ 1522] // NOP Ev }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_01_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1862] // PREFETCHT0 Mb + (const void *)&gInstructions[ 1866] // PREFETCHT0 Mb }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_01_modrmmod = @@ -14072,13 +14117,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_01_m const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_00_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1519] // NOP Ev + (const void *)&gInstructions[ 1521] // NOP Ev }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_00_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1860] // PREFETCHNTA Mb + (const void *)&gInstructions[ 1862] // PREFETCHNTA Mb }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_00_modrmmod = @@ -14098,7 +14143,7 @@ const ND_TABLE_MODRM_REG gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg = /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_01_modrmmod, /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_02_modrmmod, /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_03_modrmmod, - /* 04 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_04_leaf, + /* 04 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_04_modrmmod, /* 05 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_05_leaf, /* 06 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_06_modrmmod, /* 07 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_07_modrmmod, @@ -14108,37 +14153,52 @@ const ND_TABLE_MODRM_REG gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1517] // NOP Ev + (const void *)&gInstructions[ 1519] // NOP Ev }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1516] // NOP Ev + (const void *)&gInstructions[ 1518] // NOP Ev }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1515] // NOP Ev + (const void *)&gInstructions[ 1517] // NOP Ev }; -const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_04_leaf = +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_04_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1514] // NOP Ev + (const void *)&gInstructions[ 1516] // NOP Ev +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_04_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1863] // PREFETCHRST2 Mb +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_04_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_04_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_04_modrmmod_01_leaf, + } }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_03_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1513] // NOP Ev + (const void *)&gInstructions[ 1515] // NOP Ev }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_03_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1865] // PREFETCHT2 Mb + (const void *)&gInstructions[ 1869] // PREFETCHT2 Mb }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_03_modrmmod = @@ -14153,13 +14213,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_03_m const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_02_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1512] // NOP Ev + (const void *)&gInstructions[ 1514] // NOP Ev }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_02_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1863] // PREFETCHT1 Mb + (const void *)&gInstructions[ 1867] // PREFETCHT1 Mb }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_02_modrmmod = @@ -14174,13 +14234,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_02_m const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_01_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1511] // NOP Ev + (const void *)&gInstructions[ 1513] // NOP Ev }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_01_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1861] // PREFETCHT0 Mb + (const void *)&gInstructions[ 1865] // PREFETCHT0 Mb }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_01_modrmmod = @@ -14195,13 +14255,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_01_m const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_00_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1510] // NOP Ev + (const void *)&gInstructions[ 1512] // NOP Ev }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_00_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1859] // PREFETCHNTA Mb + (const void *)&gInstructions[ 1861] // PREFETCHNTA Mb }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_00_modrmmod = @@ -14221,7 +14281,7 @@ const ND_TABLE_MODRM_REG gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg = /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_01_modrmmod, /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_02_modrmmod, /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_03_modrmmod, - /* 04 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_04_leaf, + /* 04 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_04_modrmmod, /* 05 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_05_leaf, /* 06 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_06_leaf, /* 07 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_07_leaf, @@ -14287,7 +14347,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_17_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_16_prefix_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1453] // MOVSHDUP Vx,Wx + (const void *)&gInstructions[ 1455] // MOVSHDUP Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_16_prefix_01_modrmmod_00_leaf = @@ -14340,13 +14400,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_16_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_15_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2629] // UNPCKHPD Vx,Wx + (const void *)&gInstructions[ 2670] // UNPCKHPD Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_15_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2630] // UNPCKHPS Vx,Wx + (const void *)&gInstructions[ 2671] // UNPCKHPS Vx,Wx }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_15_prefix = @@ -14363,13 +14423,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_15_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_14_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2631] // UNPCKLPD Vx,Wx + (const void *)&gInstructions[ 2672] // UNPCKLPD Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_14_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2632] // UNPCKLPS Vx,Wx + (const void *)&gInstructions[ 2673] // UNPCKLPS Vx,Wx }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_14_prefix = @@ -14433,7 +14493,7 @@ const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_12_prefix_03_leaf = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_12_prefix_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1454] // MOVSLDUP Vx,Wx + (const void *)&gInstructions[ 1456] // MOVSLDUP Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_12_prefix_01_modrmmod_00_leaf = @@ -14471,25 +14531,25 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_12_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_11_prefix_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1452] // MOVSD Wsd,Vsd + (const void *)&gInstructions[ 1454] // MOVSD Wsd,Vsd }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_11_prefix_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1458] // MOVSS Wss,Vss + (const void *)&gInstructions[ 1460] // MOVSS Wss,Vss }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_11_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1465] // MOVUPD Wpd,Vpd + (const void *)&gInstructions[ 1467] // MOVUPD Wpd,Vpd }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_11_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1467] // MOVUPS Wps,Vps + (const void *)&gInstructions[ 1469] // MOVUPS Wps,Vps }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_11_prefix = @@ -14506,25 +14566,25 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_11_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_10_prefix_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1451] // MOVSD Vsd,Wsd + (const void *)&gInstructions[ 1453] // MOVSD Vsd,Wsd }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_10_prefix_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1457] // MOVSS Vss,Wss + (const void *)&gInstructions[ 1459] // MOVSS Vss,Wss }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_10_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1464] // MOVUPD Vpd,Wpd + (const void *)&gInstructions[ 1466] // MOVUPD Vpd,Wpd }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_10_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1466] // MOVUPS Vps,Wps + (const void *)&gInstructions[ 1468] // MOVUPS Vps,Wps }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_10_prefix = @@ -14541,157 +14601,157 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_10_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_bf_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1684] // PAVGUSB Pq,Qq + (const void *)&gInstructions[ 1686] // PAVGUSB Pq,Qq }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_bb_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1934] // PSWAPD Pq,Qq + (const void *)&gInstructions[ 1938] // PSWAPD Pq,Qq }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_b7_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1805] // PMULHRW Pq,Qq + (const void *)&gInstructions[ 1807] // PMULHRW Pq,Qq }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_b6_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1738] // PFRCPIT2 Pq,Qq + (const void *)&gInstructions[ 1740] // PFRCPIT2 Pq,Qq }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_b4_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1733] // PFMUL Pq,Qq + (const void *)&gInstructions[ 1735] // PFMUL Pq,Qq }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_b0_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1728] // PFCMPEQ Pq,Qq + (const void *)&gInstructions[ 1730] // PFCMPEQ Pq,Qq }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_ae_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1726] // PFACC Pq,Qq + (const void *)&gInstructions[ 1728] // PFACC Pq,Qq }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_aa_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1744] // PFSUBR Pq,Qq + (const void *)&gInstructions[ 1746] // PFSUBR Pq,Qq }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_a7_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1740] // PFRSQIT1 Pq,Qq + (const void *)&gInstructions[ 1742] // PFRSQIT1 Pq,Qq }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_a6_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1737] // PFRCPIT1 Pq,Qq + (const void *)&gInstructions[ 1739] // PFRCPIT1 Pq,Qq }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_a4_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1731] // PFMAX Pq,Qq + (const void *)&gInstructions[ 1733] // PFMAX Pq,Qq }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_a0_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1730] // PFCMPGT Pq,Qq + (const void *)&gInstructions[ 1732] // PFCMPGT Pq,Qq }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_9e_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1727] // PFADD Pq,Qq + (const void *)&gInstructions[ 1729] // PFADD Pq,Qq }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_9a_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1743] // PFSUB Pq,Qq + (const void *)&gInstructions[ 1745] // PFSUB Pq,Qq }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_97_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1741] // PFRSQRT Pq,Qq + (const void *)&gInstructions[ 1743] // PFRSQRT Pq,Qq }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_96_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1736] // PFRCP Pq,Qq + (const void *)&gInstructions[ 1738] // PFRCP Pq,Qq }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_94_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1732] // PFMIN Pq,Qq + (const void *)&gInstructions[ 1734] // PFMIN Pq,Qq }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_90_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1729] // PFCMPGE Pq,Qq + (const void *)&gInstructions[ 1731] // PFCMPGE Pq,Qq }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_8e_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1735] // PFPNACC Pq,Qq + (const void *)&gInstructions[ 1737] // PFPNACC Pq,Qq }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_8a_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1734] // PFNACC Pq,Qq + (const void *)&gInstructions[ 1736] // PFNACC Pq,Qq }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_87_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1742] // PFRSQRTV Pq,Qq + (const void *)&gInstructions[ 1744] // PFRSQRTV Pq,Qq }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_86_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1739] // PFRCPV Pq,Qq + (const void *)&gInstructions[ 1741] // PFRCPV Pq,Qq }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_1d_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1724] // PF2ID Pq,Qq + (const void *)&gInstructions[ 1726] // PF2ID Pq,Qq }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_1c_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1725] // PF2IW Pq,Qq + (const void *)&gInstructions[ 1727] // PF2IW Pq,Qq }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_0d_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1758] // PI2FD Pq,Qq + (const void *)&gInstructions[ 1760] // PI2FD Pq,Qq }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_0c_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1759] // PI2FW Pq,Qq + (const void *)&gInstructions[ 1761] // PI2FW Pq,Qq }; const ND_TABLE_OPCODE gLegacyMap_opcode_0f_opcode_0f_opcode_last = @@ -14966,13 +15026,13 @@ const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0e_leaf = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0d_modrmreg_07_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1509] // NOP Ev,Gv + (const void *)&gInstructions[ 1511] // NOP Ev,Gv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0d_modrmreg_07_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1854] // PREFETCH Mb + (const void *)&gInstructions[ 1856] // PREFETCH Mb }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_0d_modrmreg_07_modrmmod = @@ -14987,13 +15047,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_0d_modrmreg_07_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0d_modrmreg_06_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1508] // NOP Ev,Gv + (const void *)&gInstructions[ 1510] // NOP Ev,Gv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0d_modrmreg_06_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1853] // PREFETCH Mb + (const void *)&gInstructions[ 1855] // PREFETCH Mb }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_0d_modrmreg_06_modrmmod = @@ -15008,13 +15068,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_0d_modrmreg_06_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0d_modrmreg_05_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1507] // NOP Ev,Gv + (const void *)&gInstructions[ 1509] // NOP Ev,Gv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0d_modrmreg_05_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1852] // PREFETCH Mb + (const void *)&gInstructions[ 1854] // PREFETCH Mb }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_0d_modrmreg_05_modrmmod = @@ -15029,13 +15089,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_0d_modrmreg_05_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0d_modrmreg_04_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1506] // NOP Ev,Gv + (const void *)&gInstructions[ 1508] // NOP Ev,Gv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0d_modrmreg_04_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1851] // PREFETCH Mb + (const void *)&gInstructions[ 1853] // PREFETCH Mb }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_0d_modrmreg_04_modrmmod = @@ -15050,13 +15110,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_0d_modrmreg_04_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0d_modrmreg_03_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1505] // NOP Ev,Gv + (const void *)&gInstructions[ 1507] // NOP Ev,Gv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0d_modrmreg_03_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1858] // PREFETCHM Mb + (const void *)&gInstructions[ 1860] // PREFETCHM Mb }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_0d_modrmreg_03_modrmmod = @@ -15071,13 +15131,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_0d_modrmreg_03_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0d_modrmreg_02_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1504] // NOP Ev,Gv + (const void *)&gInstructions[ 1506] // NOP Ev,Gv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0d_modrmreg_02_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1868] // PREFETCHWT1 Mb + (const void *)&gInstructions[ 1872] // PREFETCHWT1 Mb }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_0d_modrmreg_02_modrmmod = @@ -15092,13 +15152,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_0d_modrmreg_02_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0d_modrmreg_01_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1503] // NOP Ev,Gv + (const void *)&gInstructions[ 1505] // NOP Ev,Gv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0d_modrmreg_01_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1867] // PREFETCHW Mb + (const void *)&gInstructions[ 1871] // PREFETCHW Mb }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_0d_modrmreg_01_modrmmod = @@ -15113,13 +15173,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_0d_modrmreg_01_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0d_modrmreg_00_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1502] // NOP Ev,Gv + (const void *)&gInstructions[ 1504] // NOP Ev,Gv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0d_modrmreg_00_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1855] // PREFETCHE Mb + (const void *)&gInstructions[ 1857] // PREFETCHE Mb }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_0d_modrmreg_00_modrmmod = @@ -15149,19 +15209,19 @@ const ND_TABLE_MODRM_REG gLegacyMap_opcode_0f_opcode_0d_modrmreg = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0b_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2625] // UD2 + (const void *)&gInstructions[ 2666] // UD2 }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_09_auxiliary_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4053] // WBNOINVD + (const void *)&gInstructions[ 4100] // WBNOINVD }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_09_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4052] // WBINVD + (const void *)&gInstructions[ 4099] // WBINVD }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_09_auxiliary = @@ -15190,7 +15250,7 @@ const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_08_leaf = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2585] // SYSRET + (const void *)&gInstructions[ 2591] // SYSRET }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_06_leaf = @@ -15202,7 +15262,7 @@ const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_06_leaf = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2582] // SYSCALL + (const void *)&gInstructions[ 2588] // SYSCALL }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_03_modrmmod_01_leaf = @@ -15250,19 +15310,19 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_02_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_07_prefix_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1983] // PVALIDATE + (const void *)&gInstructions[ 1987] // PVALIDATE }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_07_prefix_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1896] // PSMASH + (const void *)&gInstructions[ 1900] // PSMASH }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_07_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2613] // TLBSYNC + (const void *)&gInstructions[ 2647] // TLBSYNC }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_07_prefix = @@ -15279,13 +15339,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_mo const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_06_prefix_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2095] // RMPUPDATE + (const void *)&gInstructions[ 2101] // RMPUPDATE }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_06_prefix_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2092] // RMPADJUST + (const void *)&gInstructions[ 2098] // RMPADJUST }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_06_prefix_00_leaf = @@ -15308,19 +15368,19 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_mo const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_05_prefix_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2094] // RMPREAD + (const void *)&gInstructions[ 2100] // RMPREAD }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_05_prefix_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2093] // RMPQUERY + (const void *)&gInstructions[ 2099] // RMPQUERY }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_05_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2079] // RDPRU + (const void *)&gInstructions[ 2085] // RDPRU }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_05_prefix = @@ -15343,7 +15403,7 @@ const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_0 const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_03_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1486] // MWAITX + (const void *)&gInstructions[ 1488] // MWAITX }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_03_prefix = @@ -15383,13 +15443,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_mo const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2087] // RDTSCP + (const void *)&gInstructions[ 2093] // RDTSCP }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2581] // SWAPGS + (const void *)&gInstructions[ 2587] // SWAPGS }; const ND_TABLE_MODRM_RM gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm = @@ -15431,13 +15491,13 @@ const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_06_leaf = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_03_modrmmod_01_modrmrm_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4141] // XRESLDTRK + (const void *)&gInstructions[ 4190] // XRESLDTRK }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_03_modrmmod_01_modrmrm_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4155] // XSUSLDTRK + (const void *)&gInstructions[ 4204] // XSUSLDTRK }; const ND_TABLE_MODRM_RM gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_03_modrmmod_01_modrmrm = @@ -15467,7 +15527,7 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_03_mo const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_02_modrmmod_01_modrmrm_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2522] // STUI + (const void *)&gInstructions[ 2528] // STUI }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_02_modrmmod_01_modrmrm_06_leaf = @@ -15479,25 +15539,25 @@ const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_02_ const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_02_modrmmod_01_modrmrm_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2604] // TESTUI + (const void *)&gInstructions[ 2634] // TESTUI }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_02_modrmmod_01_modrmrm_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2626] // UIRET + (const void *)&gInstructions[ 2667] // UIRET }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_02_modrmmod_01_modrmrm_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2278] // SAVEPREVSSP + (const void *)&gInstructions[ 2284] // SAVEPREVSSP }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_02_modrmmod_01_modrmrm_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2354] // SETSSBSY + (const void *)&gInstructions[ 2360] // SETSSBSY }; const ND_TABLE_MODRM_RM gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_02_modrmmod_01_modrmrm = @@ -15518,7 +15578,7 @@ const ND_TABLE_MODRM_RM gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_02_mod const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_02_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2189] // RSTORSSP Mq + (const void *)&gInstructions[ 2195] // RSTORSSP Mq }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_02_modrmmod = @@ -15533,19 +15593,19 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_02_mo const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_00_modrmmod_01_modrmrm_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4059] // WRPKRU + (const void *)&gInstructions[ 4108] // WRPKRU }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_00_modrmmod_01_modrmrm_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2077] // RDPKRU + (const void *)&gInstructions[ 2083] // RDPKRU }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_00_modrmmod_01_modrmrm_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2323] // SERIALIZE + (const void *)&gInstructions[ 2329] // SERIALIZE }; const ND_TABLE_MODRM_RM gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_00_modrmmod_01_modrmrm = @@ -15586,13 +15646,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_04_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2498] // SMSW Rv + (const void *)&gInstructions[ 2504] // SMSW Rv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_04_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2497] // SMSW Mw + (const void *)&gInstructions[ 2503] // SMSW Mw }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_01_modrmreg_04_modrmmod = @@ -15613,7 +15673,7 @@ const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod_0 const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod_01_modrmrm_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2493] // SKINIT + (const void *)&gInstructions[ 2499] // SKINIT }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod_01_modrmrm_05_leaf = @@ -15625,43 +15685,43 @@ const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod_0 const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod_01_modrmrm_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2507] // STGI + (const void *)&gInstructions[ 2513] // STGI }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod_01_modrmrm_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3346] // VMSAVE + (const void *)&gInstructions[ 3391] // VMSAVE }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod_01_modrmrm_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3225] // VMLOAD + (const void *)&gInstructions[ 3266] // VMLOAD }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod_01_modrmrm_01_prefix_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3205] // VMGEXIT + (const void *)&gInstructions[ 3246] // VMGEXIT }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod_01_modrmrm_01_prefix_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3204] // VMGEXIT + (const void *)&gInstructions[ 3245] // VMGEXIT }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod_01_modrmrm_01_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3227] // VMMCALL + (const void *)&gInstructions[ 3268] // VMMCALL }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod_01_modrmrm_01_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3226] // VMMCALL + (const void *)&gInstructions[ 3267] // VMMCALL }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod_01_modrmrm_01_prefix = @@ -15678,7 +15738,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod_01_mo const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod_01_modrmrm_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3345] // VMRUN + (const void *)&gInstructions[ 3390] // VMRUN }; const ND_TABLE_MODRM_RM gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod_01_modrmrm = @@ -15720,31 +15780,31 @@ const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_02_modrmmod_0 const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_02_modrmmod_01_prefix_00_modrmrm_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4156] // XTEST + (const void *)&gInstructions[ 4205] // XTEST }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_02_modrmmod_01_prefix_00_modrmrm_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4082] // XEND + (const void *)&gInstructions[ 4131] // XEND }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_02_modrmmod_01_prefix_00_modrmrm_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3203] // VMFUNC + (const void *)&gInstructions[ 3244] // VMFUNC }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_02_modrmmod_01_prefix_00_modrmrm_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4154] // XSETBV + (const void *)&gInstructions[ 4203] // XSETBV }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_02_modrmmod_01_prefix_00_modrmrm_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4083] // XGETBV + (const void *)&gInstructions[ 4132] // XGETBV }; const ND_TABLE_MODRM_RM gLegacyMap_opcode_0f_opcode_01_modrmreg_02_modrmmod_01_prefix_00_modrmrm = @@ -15833,25 +15893,25 @@ const ND_TABLE_MODRM_RM gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_p const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_prefix_01_modrmrm_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2319] // SEAMCALL + (const void *)&gInstructions[ 2325] // SEAMCALL }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_prefix_01_modrmrm_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2320] // SEAMOPS + (const void *)&gInstructions[ 2326] // SEAMOPS }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_prefix_01_modrmrm_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2321] // SEAMRET + (const void *)&gInstructions[ 2327] // SEAMRET }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_prefix_01_modrmrm_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2589] // TDCALL + (const void *)&gInstructions[ 2615] // TDCALL }; const ND_TABLE_MODRM_RM gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_prefix_01_modrmrm = @@ -15878,7 +15938,7 @@ const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_0 const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_prefix_00_modrmrm_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2504] // STAC + (const void *)&gInstructions[ 2510] // STAC }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_prefix_00_modrmrm_02_leaf = @@ -15890,7 +15950,7 @@ const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_0 const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_prefix_00_modrmrm_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1485] // MWAIT + (const void *)&gInstructions[ 1487] // MWAIT }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_prefix_00_modrmrm_00_leaf = @@ -15928,7 +15988,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_pr const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2492] // SIDT Ms + (const void *)&gInstructions[ 2498] // SIDT Ms }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod = @@ -15943,7 +16003,7 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_01_prefix_03_modrmrm_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2075] // RDMSRLIST + (const void *)&gInstructions[ 2081] // RDMSRLIST }; const ND_TABLE_MODRM_RM gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_01_prefix_03_modrmrm = @@ -15964,7 +16024,7 @@ const ND_TABLE_MODRM_RM gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_01_p const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_01_prefix_02_modrmrm_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4057] // WRMSRLIST + (const void *)&gInstructions[ 4104] // WRMSRLIST }; const ND_TABLE_MODRM_RM gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_01_prefix_02_modrmrm = @@ -15985,43 +16045,43 @@ const ND_TABLE_MODRM_RM gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_01_p const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_01_prefix_00_modrmrm_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1689] // PBNDKB + (const void *)&gInstructions[ 1691] // PBNDKB }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_01_prefix_00_modrmrm_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4058] // WRMSRNS + (const void *)&gInstructions[ 4106] // WRMSRNS }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_01_prefix_00_modrmrm_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1709] // PCONFIG + (const void *)&gInstructions[ 1711] // PCONFIG }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_01_prefix_00_modrmrm_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3359] // VMXOFF + (const void *)&gInstructions[ 3404] // VMXOFF }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_01_prefix_00_modrmrm_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3344] // VMRESUME + (const void *)&gInstructions[ 3389] // VMRESUME }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_01_prefix_00_modrmrm_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3224] // VMLAUNCH + (const void *)&gInstructions[ 3265] // VMLAUNCH }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_01_prefix_00_modrmrm_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3201] // VMCALL + (const void *)&gInstructions[ 3242] // VMCALL }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_01_prefix_00_modrmrm_00_leaf = @@ -16059,7 +16119,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_01_pr const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2358] // SGDT Ms + (const void *)&gInstructions[ 2364] // SGDT Ms }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod = @@ -16127,13 +16187,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_00_modrmreg_06_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_00_modrmreg_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2885] // VERW Ew + (const void *)&gInstructions[ 2926] // VERW Ew }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_00_modrmreg_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2884] // VERR Ew + (const void *)&gInstructions[ 2925] // VERR Ew }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_00_modrmreg_03_leaf = @@ -16151,13 +16211,13 @@ const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_00_modrmreg_02_leaf = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_00_modrmreg_01_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2519] // STR Rv + (const void *)&gInstructions[ 2525] // STR Rv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_00_modrmreg_01_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2518] // STR Mw + (const void *)&gInstructions[ 2524] // STR Mw }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_00_modrmreg_01_modrmmod = @@ -16172,13 +16232,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_00_modrmreg_01_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_00_modrmreg_00_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2495] // SLDT Rv + (const void *)&gInstructions[ 2501] // SLDT Rv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_00_modrmreg_00_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2494] // SLDT Mw + (const void *)&gInstructions[ 2500] // SLDT Mw }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_00_modrmreg_00_modrmmod = @@ -16471,55 +16531,55 @@ const ND_TABLE_OPCODE gLegacyMap_opcode_0f_opcode = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0e_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1952] // PUSH CS + (const void *)&gInstructions[ 1956] // PUSH CS }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0d_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1629] // OR rAX,Iz + (const void *)&gInstructions[ 1631] // OR rAX,Iz }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0c_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1628] // OR AL,Ib + (const void *)&gInstructions[ 1630] // OR AL,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0b_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1627] // OR Gv,Ev + (const void *)&gInstructions[ 1629] // OR Gv,Ev }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0a_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1626] // OR Gb,Eb + (const void *)&gInstructions[ 1628] // OR Gb,Eb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_09_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1625] // OR Ev,Gv + (const void *)&gInstructions[ 1627] // OR Ev,Gv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_08_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1624] // OR Eb,Gb + (const void *)&gInstructions[ 1626] // OR Eb,Gb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1815] // POP ES + (const void *)&gInstructions[ 1817] // POP ES }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1951] // PUSH ES + (const void *)&gInstructions[ 1955] // PUSH ES }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_05_leaf = diff --git a/bddisasm/include/bdx86_table_vex.h b/bddisasm/include/bdx86_table_vex.h index bd13233..f1be108 100644 --- a/bddisasm/include/bdx86_table_vex.h +++ b/bddisasm/include/bdx86_table_vex.h @@ -13,7 +13,7 @@ const ND_TABLE_INSTRUCTION gVexMap_mmmmm_07_opcode_f8_pp_03_modrmreg_00_modrmmod_01_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2636] // URDMSR Rq,Id + (const void *)&gInstructions[ 2677] // URDMSR Rq,Id }; const ND_TABLE_EX_W gVexMap_mmmmm_07_opcode_f8_pp_03_modrmreg_00_modrmmod_01_l_00_w = @@ -63,7 +63,7 @@ const ND_TABLE_MODRM_REG gVexMap_mmmmm_07_opcode_f8_pp_03_modrmreg = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_07_opcode_f8_pp_02_modrmreg_00_modrmmod_01_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2640] // UWRMSR Id,Rq + (const void *)&gInstructions[ 2681] // UWRMSR Id,Rq }; const ND_TABLE_EX_W gVexMap_mmmmm_07_opcode_f8_pp_02_modrmreg_00_modrmmod_01_l_00_w = @@ -121,6 +121,117 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_07_opcode_f8_pp = } }; +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_07_opcode_f6_pp_03_modrmreg_00_modrmmod_01_l_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2080] // RDMSR Rq,Id +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_07_opcode_f6_pp_03_modrmreg_00_modrmmod_01_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_07_opcode_f6_pp_03_modrmreg_00_modrmmod_01_l_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_07_opcode_f6_pp_03_modrmreg_00_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_07_opcode_f6_pp_03_modrmreg_00_modrmmod_01_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_07_opcode_f6_pp_03_modrmreg_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_07_opcode_f6_pp_03_modrmreg_00_modrmmod_01_l, + } +}; + +const ND_TABLE_MODRM_REG gVexMap_mmmmm_07_opcode_f6_pp_03_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gVexMap_mmmmm_07_opcode_f6_pp_03_modrmreg_00_modrmmod, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_07_opcode_f6_pp_02_modrmreg_00_modrmmod_01_l_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 4107] // WRMSRNS Id,Rq +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_07_opcode_f6_pp_02_modrmreg_00_modrmmod_01_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_07_opcode_f6_pp_02_modrmreg_00_modrmmod_01_l_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_07_opcode_f6_pp_02_modrmreg_00_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_07_opcode_f6_pp_02_modrmreg_00_modrmmod_01_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_07_opcode_f6_pp_02_modrmreg_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_07_opcode_f6_pp_02_modrmreg_00_modrmmod_01_l, + } +}; + +const ND_TABLE_MODRM_REG gVexMap_mmmmm_07_opcode_f6_pp_02_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gVexMap_mmmmm_07_opcode_f6_pp_02_modrmreg_00_modrmmod, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_07_opcode_f6_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gVexMap_mmmmm_07_opcode_f6_pp_02_modrmreg, + /* 03 */ (const void *)&gVexMap_mmmmm_07_opcode_f6_pp_03_modrmreg, + } +}; + const ND_TABLE_OPCODE gVexMap_mmmmm_07_opcode = { ND_ILUT_OPCODE, @@ -371,7 +482,7 @@ const ND_TABLE_OPCODE gVexMap_mmmmm_07_opcode = /* f3 */ (const void *)ND_NULL, /* f4 */ (const void *)ND_NULL, /* f5 */ (const void *)ND_NULL, - /* f6 */ (const void *)ND_NULL, + /* f6 */ (const void *)&gVexMap_mmmmm_07_opcode_f6_pp, /* f7 */ (const void *)ND_NULL, /* f8 */ (const void *)&gVexMap_mmmmm_07_opcode_f8_pp, /* f9 */ (const void *)ND_NULL, @@ -384,2397 +495,2973 @@ const ND_TABLE_OPCODE gVexMap_mmmmm_07_opcode = } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_f0_pp_03_l_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_05_opcode_fd_pp_03_modrmmod_01_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2181] // RORX Gy,Ey,Ib + (const void *)&gInstructions[ 2618] // TDPBHF8PS rTt,mTt,vTt }; -const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_f0_pp_03_l = +const ND_TABLE_EX_W gVexMap_mmmmm_05_opcode_fd_pp_03_modrmmod_01_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_05_opcode_fd_pp_03_modrmmod_01_l_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_05_opcode_fd_pp_03_modrmmod_01_l = { ND_ILUT_EX_L, { - /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_f0_pp_03_l_00_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_05_opcode_fd_pp_03_modrmmod_01_l_00_w, /* 01 */ (const void *)ND_NULL, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_f0_pp = +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_05_opcode_fd_pp_03_modrmmod = { - ND_ILUT_EX_PP, + ND_ILUT_MODRM_MOD, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)ND_NULL, - /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)&gVexMap_mmmmm_03_opcode_f0_pp_03_l, + /* 01 */ (const void *)&gVexMap_mmmmm_05_opcode_fd_pp_03_modrmmod_01_l, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_df_pp_01_l_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_05_opcode_fd_pp_02_modrmmod_01_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2667] // VAESKEYGENASSIST Vdq,Wdq,Ib + (const void *)&gInstructions[ 2624] // TDPHBF8PS rTt,mTt,vTt }; -const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_df_pp_01_l = +const ND_TABLE_EX_W gVexMap_mmmmm_05_opcode_fd_pp_02_modrmmod_01_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_05_opcode_fd_pp_02_modrmmod_01_l_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_05_opcode_fd_pp_02_modrmmod_01_l = { ND_ILUT_EX_L, { - /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_df_pp_01_l_00_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_05_opcode_fd_pp_02_modrmmod_01_l_00_w, /* 01 */ (const void *)ND_NULL, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_df_pp = +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_05_opcode_fd_pp_02_modrmmod = { - ND_ILUT_EX_PP, + ND_ILUT_MODRM_MOD, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_df_pp_01_l, - /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_05_opcode_fd_pp_02_modrmmod_01_l, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_de_pp_01_l_00_w_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_05_opcode_fd_pp_01_modrmmod_01_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4001] // VSM3RNDS2 Vdq,Hdq,Wdq,Ib + (const void *)&gInstructions[ 2625] // TDPHF8PS rTt,mTt,vTt }; -const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_de_pp_01_l_00_w = +const ND_TABLE_EX_W gVexMap_mmmmm_05_opcode_fd_pp_01_modrmmod_01_l_00_w = { ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_de_pp_01_l_00_w_00_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_05_opcode_fd_pp_01_modrmmod_01_l_00_w_00_leaf, /* 01 */ (const void *)ND_NULL, } }; -const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_de_pp_01_l = +const ND_TABLE_EX_L gVexMap_mmmmm_05_opcode_fd_pp_01_modrmmod_01_l = { ND_ILUT_EX_L, { - /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_de_pp_01_l_00_w, + /* 00 */ (const void *)&gVexMap_mmmmm_05_opcode_fd_pp_01_modrmmod_01_l_00_w, /* 01 */ (const void *)ND_NULL, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_de_pp = +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_05_opcode_fd_pp_01_modrmmod = { - ND_ILUT_EX_PP, + ND_ILUT_MODRM_MOD, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_de_pp_01_l, - /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_05_opcode_fd_pp_01_modrmmod_01_l, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_cf_pp_01_w_01_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_05_opcode_fd_pp_00_modrmmod_01_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3160] // VGF2P8AFFINEINVQB Vx,Hx,Wx,Ib + (const void *)&gInstructions[ 2617] // TDPBF8PS rTt,mTt,vTt }; -const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_cf_pp_01_w = +const ND_TABLE_EX_W gVexMap_mmmmm_05_opcode_fd_pp_00_modrmmod_01_l_00_w = { ND_ILUT_EX_W, { - /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_cf_pp_01_w_01_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_05_opcode_fd_pp_00_modrmmod_01_l_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_cf_pp = +const ND_TABLE_EX_L gVexMap_mmmmm_05_opcode_fd_pp_00_modrmmod_01_l = { - ND_ILUT_EX_PP, + ND_ILUT_EX_L, { - /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_cf_pp_01_w, + /* 00 */ (const void *)&gVexMap_mmmmm_05_opcode_fd_pp_00_modrmmod_01_l_00_w, + /* 01 */ (const void *)ND_NULL, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_ce_pp_01_w_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3162] // VGF2P8AFFINEQB Vx,Hx,Wx,Ib -}; - -const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_ce_pp_01_w = +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_05_opcode_fd_pp_00_modrmmod = { - ND_ILUT_EX_W, + ND_ILUT_MODRM_MOD, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_ce_pp_01_w_01_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_05_opcode_fd_pp_00_modrmmod_01_l, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_ce_pp = +const ND_TABLE_EX_PP gVexMap_mmmmm_05_opcode_fd_pp = { ND_ILUT_EX_PP, { - /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_ce_pp_01_w, - /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)ND_NULL, + /* 00 */ (const void *)&gVexMap_mmmmm_05_opcode_fd_pp_00_modrmmod, + /* 01 */ (const void *)&gVexMap_mmmmm_05_opcode_fd_pp_01_modrmmod, + /* 02 */ (const void *)&gVexMap_mmmmm_05_opcode_fd_pp_02_modrmmod, + /* 03 */ (const void *)&gVexMap_mmmmm_05_opcode_fd_pp_03_modrmmod, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_7f_pp_01_w_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3115] // VFNMSUBSD Vdq,Hdq,Ldq,Wsd -}; - -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_7f_pp_01_w_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_05_opcode_f9_pp_01_modrmmod_00_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3114] // VFNMSUBSD Vdq,Hdq,Wsd,Ldq + (const void *)&gInstructions[ 2599] // T2RPNTLVWZ1RST1 rTt+1,Mt }; -const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_7f_pp_01_w = +const ND_TABLE_EX_W gVexMap_mmmmm_05_opcode_f9_pp_01_modrmmod_00_l_00_w = { ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_7f_pp_01_w_00_leaf, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_7f_pp_01_w_01_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_05_opcode_f9_pp_01_modrmmod_00_l_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_7f_pp = +const ND_TABLE_EX_L gVexMap_mmmmm_05_opcode_f9_pp_01_modrmmod_00_l = { - ND_ILUT_EX_PP, + ND_ILUT_EX_L, { - /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_7f_pp_01_w, + /* 00 */ (const void *)&gVexMap_mmmmm_05_opcode_f9_pp_01_modrmmod_00_l_00_w, + /* 01 */ (const void *)ND_NULL, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_7e_pp_01_w_01_leaf = +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_05_opcode_f9_pp_01_modrmmod = { - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3117] // VFNMSUBSS Vdq,Hdq,Ldq,Wss + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_05_opcode_f9_pp_01_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_7e_pp_01_w_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_05_opcode_f9_pp_00_modrmmod_00_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3116] // VFNMSUBSS Vdq,Hdq,Wss,Ldq + (const void *)&gInstructions[ 2595] // T2RPNTLVWZ0RST1 rTt+1,Mt }; -const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_7e_pp_01_w = +const ND_TABLE_EX_W gVexMap_mmmmm_05_opcode_f9_pp_00_modrmmod_00_l_00_w = { ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_7e_pp_01_w_00_leaf, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_7e_pp_01_w_01_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_05_opcode_f9_pp_00_modrmmod_00_l_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_7e_pp = +const ND_TABLE_EX_L gVexMap_mmmmm_05_opcode_f9_pp_00_modrmmod_00_l = { - ND_ILUT_EX_PP, + ND_ILUT_EX_L, { - /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_7e_pp_01_w, + /* 00 */ (const void *)&gVexMap_mmmmm_05_opcode_f9_pp_00_modrmmod_00_l_00_w, + /* 01 */ (const void *)ND_NULL, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_7d_pp_01_w_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3111] // VFNMSUBPD Vx,Hx,Lx,Wx -}; - -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_7d_pp_01_w_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3110] // VFNMSUBPD Vx,Hx,Wx,Lx -}; - -const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_7d_pp_01_w = +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_05_opcode_f9_pp_00_modrmmod = { - ND_ILUT_EX_W, + ND_ILUT_MODRM_MOD, { - /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_7d_pp_01_w_00_leaf, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_7d_pp_01_w_01_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_05_opcode_f9_pp_00_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_7d_pp = +const ND_TABLE_EX_PP gVexMap_mmmmm_05_opcode_f9_pp = { ND_ILUT_EX_PP, { - /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_7d_pp_01_w, + /* 00 */ (const void *)&gVexMap_mmmmm_05_opcode_f9_pp_00_modrmmod, + /* 01 */ (const void *)&gVexMap_mmmmm_05_opcode_f9_pp_01_modrmmod, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_7c_pp_01_w_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3113] // VFNMSUBPS Vx,Hx,Lx,Wx -}; - -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_7c_pp_01_w_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_05_opcode_f8_pp_01_modrmmod_00_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3112] // VFNMSUBPS Vx,Hx,Wx,Lx + (const void *)&gInstructions[ 2598] // T2RPNTLVWZ1RS rTt+1,Mt }; -const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_7c_pp_01_w = +const ND_TABLE_EX_W gVexMap_mmmmm_05_opcode_f8_pp_01_modrmmod_00_l_00_w = { ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_7c_pp_01_w_00_leaf, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_7c_pp_01_w_01_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_05_opcode_f8_pp_01_modrmmod_00_l_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_7c_pp = +const ND_TABLE_EX_L gVexMap_mmmmm_05_opcode_f8_pp_01_modrmmod_00_l = { - ND_ILUT_EX_PP, + ND_ILUT_EX_L, { - /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_7c_pp_01_w, + /* 00 */ (const void *)&gVexMap_mmmmm_05_opcode_f8_pp_01_modrmmod_00_l_00_w, + /* 01 */ (const void *)ND_NULL, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_7b_pp_01_w_01_leaf = +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_05_opcode_f8_pp_01_modrmmod = { - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3074] // VFNMADDSD Vdq,Hdq,Ldq,Wsd + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_05_opcode_f8_pp_01_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_7b_pp_01_w_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_05_opcode_f8_pp_00_modrmmod_00_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3073] // VFNMADDSD Vdq,Hdq,Wsd,Ldq + (const void *)&gInstructions[ 2594] // T2RPNTLVWZ0RS rTt+1,Mt }; -const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_7b_pp_01_w = +const ND_TABLE_EX_W gVexMap_mmmmm_05_opcode_f8_pp_00_modrmmod_00_l_00_w = { ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_7b_pp_01_w_00_leaf, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_7b_pp_01_w_01_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_05_opcode_f8_pp_00_modrmmod_00_l_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_7b_pp = +const ND_TABLE_EX_L gVexMap_mmmmm_05_opcode_f8_pp_00_modrmmod_00_l = { - ND_ILUT_EX_PP, + ND_ILUT_EX_L, { - /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_7b_pp_01_w, + /* 00 */ (const void *)&gVexMap_mmmmm_05_opcode_f8_pp_00_modrmmod_00_l_00_w, + /* 01 */ (const void *)ND_NULL, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_7a_pp_01_w_01_leaf = +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_05_opcode_f8_pp_00_modrmmod = { - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3076] // VFNMADDSS Vdq,Hdq,Ldq,Wss + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_05_opcode_f8_pp_00_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_7a_pp_01_w_00_leaf = +const ND_TABLE_EX_PP gVexMap_mmmmm_05_opcode_f8_pp = { - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3075] // VFNMADDSS Vdq,Hdq,Wss,Ldq + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gVexMap_mmmmm_05_opcode_f8_pp_00_modrmmod, + /* 01 */ (const void *)&gVexMap_mmmmm_05_opcode_f8_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } }; -const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_7a_pp_01_w = +const ND_TABLE_OPCODE gVexMap_mmmmm_05_opcode = { - ND_ILUT_EX_W, - { - /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_7a_pp_01_w_00_leaf, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_7a_pp_01_w_01_leaf, - } -}; - -const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_7a_pp = -{ - ND_ILUT_EX_PP, - { - /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_7a_pp_01_w, - /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_79_pp_01_w_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3070] // VFNMADDPD Vx,Hx,Lx,Wx -}; - -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_79_pp_01_w_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3069] // VFNMADDPD Vx,Hx,Wx,Lx -}; - -const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_79_pp_01_w = -{ - ND_ILUT_EX_W, - { - /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_79_pp_01_w_00_leaf, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_79_pp_01_w_01_leaf, - } -}; - -const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_79_pp = -{ - ND_ILUT_EX_PP, - { - /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_79_pp_01_w, - /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_78_pp_01_w_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3072] // VFNMADDPS Vx,Hx,Lx,Wx -}; - -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_78_pp_01_w_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3071] // VFNMADDPS Vx,Hx,Wx,Lx -}; - -const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_78_pp_01_w = -{ - ND_ILUT_EX_W, - { - /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_78_pp_01_w_00_leaf, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_78_pp_01_w_01_leaf, - } -}; - -const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_78_pp = -{ - ND_ILUT_EX_PP, - { - /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_78_pp_01_w, - /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_6f_pp_01_w_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3031] // VFMSUBSD Vdq,Hdq,Ldq,Wsd -}; - -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_6f_pp_01_w_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3030] // VFMSUBSD Vdq,Hdq,Wsd,Ldq -}; - -const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_6f_pp_01_w = -{ - ND_ILUT_EX_W, - { - /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_6f_pp_01_w_00_leaf, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_6f_pp_01_w_01_leaf, - } -}; - -const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_6f_pp = -{ - ND_ILUT_EX_PP, - { - /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_6f_pp_01_w, - /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_6e_pp_01_w_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3033] // VFMSUBSS Vdq,Hdq,Ldq,Wss -}; - -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_6e_pp_01_w_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3032] // VFMSUBSS Vdq,Hdq,Wss,Ldq -}; - -const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_6e_pp_01_w = -{ - ND_ILUT_EX_W, - { - /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_6e_pp_01_w_00_leaf, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_6e_pp_01_w_01_leaf, - } -}; - -const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_6e_pp = -{ - ND_ILUT_EX_PP, - { - /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_6e_pp_01_w, - /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_6d_pp_01_w_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3027] // VFMSUBPD Vx,Hx,Lx,Wx -}; - -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_6d_pp_01_w_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3026] // VFMSUBPD Vx,Hx,Wx,Lx -}; - -const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_6d_pp_01_w = -{ - ND_ILUT_EX_W, - { - /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_6d_pp_01_w_00_leaf, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_6d_pp_01_w_01_leaf, - } -}; - -const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_6d_pp = -{ - ND_ILUT_EX_PP, - { - /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_6d_pp_01_w, - /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_6c_pp_01_w_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3029] // VFMSUBPS Vx,Hx,Lx,Wx -}; - -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_6c_pp_01_w_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3028] // VFMSUBPS Vx,Hx,Wx,Lx -}; - -const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_6c_pp_01_w = -{ - ND_ILUT_EX_W, - { - /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_6c_pp_01_w_00_leaf, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_6c_pp_01_w_01_leaf, - } -}; - -const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_6c_pp = -{ - ND_ILUT_EX_PP, - { - /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_6c_pp_01_w, - /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_6b_pp_01_w_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2952] // VFMADDSD Vdq,Hdq,Ldq,Wsd -}; - -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_6b_pp_01_w_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2951] // VFMADDSD Vdq,Hdq,Wsd,Ldq -}; - -const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_6b_pp_01_w = -{ - ND_ILUT_EX_W, - { - /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_6b_pp_01_w_00_leaf, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_6b_pp_01_w_01_leaf, - } -}; - -const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_6b_pp = -{ - ND_ILUT_EX_PP, - { - /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_6b_pp_01_w, - /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_6a_pp_01_w_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2954] // VFMADDSS Vdq,Hdq,Ldq,Wss -}; - -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_6a_pp_01_w_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2953] // VFMADDSS Vdq,Hdq,Wss,Ldq -}; - -const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_6a_pp_01_w = -{ - ND_ILUT_EX_W, - { - /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_6a_pp_01_w_00_leaf, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_6a_pp_01_w_01_leaf, - } -}; - -const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_6a_pp = -{ - ND_ILUT_EX_PP, + ND_ILUT_OPCODE, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_6a_pp_01_w, + /* 01 */ (const void *)ND_NULL, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_69_pp_01_w_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2948] // VFMADDPD Vx,Hx,Lx,Wx + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)ND_NULL, + /* 09 */ (const void *)ND_NULL, + /* 0a */ (const void *)ND_NULL, + /* 0b */ (const void *)ND_NULL, + /* 0c */ (const void *)ND_NULL, + /* 0d */ (const void *)ND_NULL, + /* 0e */ (const void *)ND_NULL, + /* 0f */ (const void *)ND_NULL, + /* 10 */ (const void *)ND_NULL, + /* 11 */ (const void *)ND_NULL, + /* 12 */ (const void *)ND_NULL, + /* 13 */ (const void *)ND_NULL, + /* 14 */ (const void *)ND_NULL, + /* 15 */ (const void *)ND_NULL, + /* 16 */ (const void *)ND_NULL, + /* 17 */ (const void *)ND_NULL, + /* 18 */ (const void *)ND_NULL, + /* 19 */ (const void *)ND_NULL, + /* 1a */ (const void *)ND_NULL, + /* 1b */ (const void *)ND_NULL, + /* 1c */ (const void *)ND_NULL, + /* 1d */ (const void *)ND_NULL, + /* 1e */ (const void *)ND_NULL, + /* 1f */ (const void *)ND_NULL, + /* 20 */ (const void *)ND_NULL, + /* 21 */ (const void *)ND_NULL, + /* 22 */ (const void *)ND_NULL, + /* 23 */ (const void *)ND_NULL, + /* 24 */ (const void *)ND_NULL, + /* 25 */ (const void *)ND_NULL, + /* 26 */ (const void *)ND_NULL, + /* 27 */ (const void *)ND_NULL, + /* 28 */ (const void *)ND_NULL, + /* 29 */ (const void *)ND_NULL, + /* 2a */ (const void *)ND_NULL, + /* 2b */ (const void *)ND_NULL, + /* 2c */ (const void *)ND_NULL, + /* 2d */ (const void *)ND_NULL, + /* 2e */ (const void *)ND_NULL, + /* 2f */ (const void *)ND_NULL, + /* 30 */ (const void *)ND_NULL, + /* 31 */ (const void *)ND_NULL, + /* 32 */ (const void *)ND_NULL, + /* 33 */ (const void *)ND_NULL, + /* 34 */ (const void *)ND_NULL, + /* 35 */ (const void *)ND_NULL, + /* 36 */ (const void *)ND_NULL, + /* 37 */ (const void *)ND_NULL, + /* 38 */ (const void *)ND_NULL, + /* 39 */ (const void *)ND_NULL, + /* 3a */ (const void *)ND_NULL, + /* 3b */ (const void *)ND_NULL, + /* 3c */ (const void *)ND_NULL, + /* 3d */ (const void *)ND_NULL, + /* 3e */ (const void *)ND_NULL, + /* 3f */ (const void *)ND_NULL, + /* 40 */ (const void *)ND_NULL, + /* 41 */ (const void *)ND_NULL, + /* 42 */ (const void *)ND_NULL, + /* 43 */ (const void *)ND_NULL, + /* 44 */ (const void *)ND_NULL, + /* 45 */ (const void *)ND_NULL, + /* 46 */ (const void *)ND_NULL, + /* 47 */ (const void *)ND_NULL, + /* 48 */ (const void *)ND_NULL, + /* 49 */ (const void *)ND_NULL, + /* 4a */ (const void *)ND_NULL, + /* 4b */ (const void *)ND_NULL, + /* 4c */ (const void *)ND_NULL, + /* 4d */ (const void *)ND_NULL, + /* 4e */ (const void *)ND_NULL, + /* 4f */ (const void *)ND_NULL, + /* 50 */ (const void *)ND_NULL, + /* 51 */ (const void *)ND_NULL, + /* 52 */ (const void *)ND_NULL, + /* 53 */ (const void *)ND_NULL, + /* 54 */ (const void *)ND_NULL, + /* 55 */ (const void *)ND_NULL, + /* 56 */ (const void *)ND_NULL, + /* 57 */ (const void *)ND_NULL, + /* 58 */ (const void *)ND_NULL, + /* 59 */ (const void *)ND_NULL, + /* 5a */ (const void *)ND_NULL, + /* 5b */ (const void *)ND_NULL, + /* 5c */ (const void *)ND_NULL, + /* 5d */ (const void *)ND_NULL, + /* 5e */ (const void *)ND_NULL, + /* 5f */ (const void *)ND_NULL, + /* 60 */ (const void *)ND_NULL, + /* 61 */ (const void *)ND_NULL, + /* 62 */ (const void *)ND_NULL, + /* 63 */ (const void *)ND_NULL, + /* 64 */ (const void *)ND_NULL, + /* 65 */ (const void *)ND_NULL, + /* 66 */ (const void *)ND_NULL, + /* 67 */ (const void *)ND_NULL, + /* 68 */ (const void *)ND_NULL, + /* 69 */ (const void *)ND_NULL, + /* 6a */ (const void *)ND_NULL, + /* 6b */ (const void *)ND_NULL, + /* 6c */ (const void *)ND_NULL, + /* 6d */ (const void *)ND_NULL, + /* 6e */ (const void *)ND_NULL, + /* 6f */ (const void *)ND_NULL, + /* 70 */ (const void *)ND_NULL, + /* 71 */ (const void *)ND_NULL, + /* 72 */ (const void *)ND_NULL, + /* 73 */ (const void *)ND_NULL, + /* 74 */ (const void *)ND_NULL, + /* 75 */ (const void *)ND_NULL, + /* 76 */ (const void *)ND_NULL, + /* 77 */ (const void *)ND_NULL, + /* 78 */ (const void *)ND_NULL, + /* 79 */ (const void *)ND_NULL, + /* 7a */ (const void *)ND_NULL, + /* 7b */ (const void *)ND_NULL, + /* 7c */ (const void *)ND_NULL, + /* 7d */ (const void *)ND_NULL, + /* 7e */ (const void *)ND_NULL, + /* 7f */ (const void *)ND_NULL, + /* 80 */ (const void *)ND_NULL, + /* 81 */ (const void *)ND_NULL, + /* 82 */ (const void *)ND_NULL, + /* 83 */ (const void *)ND_NULL, + /* 84 */ (const void *)ND_NULL, + /* 85 */ (const void *)ND_NULL, + /* 86 */ (const void *)ND_NULL, + /* 87 */ (const void *)ND_NULL, + /* 88 */ (const void *)ND_NULL, + /* 89 */ (const void *)ND_NULL, + /* 8a */ (const void *)ND_NULL, + /* 8b */ (const void *)ND_NULL, + /* 8c */ (const void *)ND_NULL, + /* 8d */ (const void *)ND_NULL, + /* 8e */ (const void *)ND_NULL, + /* 8f */ (const void *)ND_NULL, + /* 90 */ (const void *)ND_NULL, + /* 91 */ (const void *)ND_NULL, + /* 92 */ (const void *)ND_NULL, + /* 93 */ (const void *)ND_NULL, + /* 94 */ (const void *)ND_NULL, + /* 95 */ (const void *)ND_NULL, + /* 96 */ (const void *)ND_NULL, + /* 97 */ (const void *)ND_NULL, + /* 98 */ (const void *)ND_NULL, + /* 99 */ (const void *)ND_NULL, + /* 9a */ (const void *)ND_NULL, + /* 9b */ (const void *)ND_NULL, + /* 9c */ (const void *)ND_NULL, + /* 9d */ (const void *)ND_NULL, + /* 9e */ (const void *)ND_NULL, + /* 9f */ (const void *)ND_NULL, + /* a0 */ (const void *)ND_NULL, + /* a1 */ (const void *)ND_NULL, + /* a2 */ (const void *)ND_NULL, + /* a3 */ (const void *)ND_NULL, + /* a4 */ (const void *)ND_NULL, + /* a5 */ (const void *)ND_NULL, + /* a6 */ (const void *)ND_NULL, + /* a7 */ (const void *)ND_NULL, + /* a8 */ (const void *)ND_NULL, + /* a9 */ (const void *)ND_NULL, + /* aa */ (const void *)ND_NULL, + /* ab */ (const void *)ND_NULL, + /* ac */ (const void *)ND_NULL, + /* ad */ (const void *)ND_NULL, + /* ae */ (const void *)ND_NULL, + /* af */ (const void *)ND_NULL, + /* b0 */ (const void *)ND_NULL, + /* b1 */ (const void *)ND_NULL, + /* b2 */ (const void *)ND_NULL, + /* b3 */ (const void *)ND_NULL, + /* b4 */ (const void *)ND_NULL, + /* b5 */ (const void *)ND_NULL, + /* b6 */ (const void *)ND_NULL, + /* b7 */ (const void *)ND_NULL, + /* b8 */ (const void *)ND_NULL, + /* b9 */ (const void *)ND_NULL, + /* ba */ (const void *)ND_NULL, + /* bb */ (const void *)ND_NULL, + /* bc */ (const void *)ND_NULL, + /* bd */ (const void *)ND_NULL, + /* be */ (const void *)ND_NULL, + /* bf */ (const void *)ND_NULL, + /* c0 */ (const void *)ND_NULL, + /* c1 */ (const void *)ND_NULL, + /* c2 */ (const void *)ND_NULL, + /* c3 */ (const void *)ND_NULL, + /* c4 */ (const void *)ND_NULL, + /* c5 */ (const void *)ND_NULL, + /* c6 */ (const void *)ND_NULL, + /* c7 */ (const void *)ND_NULL, + /* c8 */ (const void *)ND_NULL, + /* c9 */ (const void *)ND_NULL, + /* ca */ (const void *)ND_NULL, + /* cb */ (const void *)ND_NULL, + /* cc */ (const void *)ND_NULL, + /* cd */ (const void *)ND_NULL, + /* ce */ (const void *)ND_NULL, + /* cf */ (const void *)ND_NULL, + /* d0 */ (const void *)ND_NULL, + /* d1 */ (const void *)ND_NULL, + /* d2 */ (const void *)ND_NULL, + /* d3 */ (const void *)ND_NULL, + /* d4 */ (const void *)ND_NULL, + /* d5 */ (const void *)ND_NULL, + /* d6 */ (const void *)ND_NULL, + /* d7 */ (const void *)ND_NULL, + /* d8 */ (const void *)ND_NULL, + /* d9 */ (const void *)ND_NULL, + /* da */ (const void *)ND_NULL, + /* db */ (const void *)ND_NULL, + /* dc */ (const void *)ND_NULL, + /* dd */ (const void *)ND_NULL, + /* de */ (const void *)ND_NULL, + /* df */ (const void *)ND_NULL, + /* e0 */ (const void *)ND_NULL, + /* e1 */ (const void *)ND_NULL, + /* e2 */ (const void *)ND_NULL, + /* e3 */ (const void *)ND_NULL, + /* e4 */ (const void *)ND_NULL, + /* e5 */ (const void *)ND_NULL, + /* e6 */ (const void *)ND_NULL, + /* e7 */ (const void *)ND_NULL, + /* e8 */ (const void *)ND_NULL, + /* e9 */ (const void *)ND_NULL, + /* ea */ (const void *)ND_NULL, + /* eb */ (const void *)ND_NULL, + /* ec */ (const void *)ND_NULL, + /* ed */ (const void *)ND_NULL, + /* ee */ (const void *)ND_NULL, + /* ef */ (const void *)ND_NULL, + /* f0 */ (const void *)ND_NULL, + /* f1 */ (const void *)ND_NULL, + /* f2 */ (const void *)ND_NULL, + /* f3 */ (const void *)ND_NULL, + /* f4 */ (const void *)ND_NULL, + /* f5 */ (const void *)ND_NULL, + /* f6 */ (const void *)ND_NULL, + /* f7 */ (const void *)ND_NULL, + /* f8 */ (const void *)&gVexMap_mmmmm_05_opcode_f8_pp, + /* f9 */ (const void *)&gVexMap_mmmmm_05_opcode_f9_pp, + /* fa */ (const void *)ND_NULL, + /* fb */ (const void *)ND_NULL, + /* fc */ (const void *)ND_NULL, + /* fd */ (const void *)&gVexMap_mmmmm_05_opcode_fd_pp, + /* fe */ (const void *)ND_NULL, + /* ff */ (const void *)ND_NULL, + } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_69_pp_01_w_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_f0_pp_03_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2947] // VFMADDPD Vx,Hx,Wx,Lx + (const void *)&gInstructions[ 2187] // RORX Gy,Ey,Ib }; -const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_69_pp_01_w = +const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_f0_pp_03_l = { - ND_ILUT_EX_W, + ND_ILUT_EX_L, { - /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_69_pp_01_w_00_leaf, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_69_pp_01_w_01_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_f0_pp_03_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_69_pp = +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_f0_pp = { ND_ILUT_EX_PP, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_69_pp_01_w, + /* 01 */ (const void *)ND_NULL, /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)ND_NULL, + /* 03 */ (const void *)&gVexMap_mmmmm_03_opcode_f0_pp_03_l, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_68_pp_01_w_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2950] // VFMADDPS Vx,Hx,Lx,Wx -}; - -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_68_pp_01_w_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_df_pp_01_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2949] // VFMADDPS Vx,Hx,Wx,Lx + (const void *)&gInstructions[ 2708] // VAESKEYGENASSIST Vdq,Wdq,Ib }; -const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_68_pp_01_w = +const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_df_pp_01_l = { - ND_ILUT_EX_W, + ND_ILUT_EX_L, { - /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_68_pp_01_w_00_leaf, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_68_pp_01_w_01_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_df_pp_01_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_68_pp = +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_df_pp = { ND_ILUT_EX_PP, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_68_pp_01_w, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_df_pp_01_l, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_63_pp_01_l_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_de_pp_01_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3457] // VPCMPISTRI Vdq,Wdq,Ib + (const void *)&gInstructions[ 4046] // VSM3RNDS2 Vdq,Hdq,Wdq,Ib }; -const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_63_pp_01_l = +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_de_pp_01_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_de_pp_01_l_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_de_pp_01_l = { ND_ILUT_EX_L, { - /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_63_pp_01_l_00_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_de_pp_01_l_00_w, /* 01 */ (const void *)ND_NULL, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_63_pp = +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_de_pp = { ND_ILUT_EX_PP, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_63_pp_01_l, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_de_pp_01_l, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_62_pp_01_l_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_cf_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3458] // VPCMPISTRM Vdq,Wdq,Ib + (const void *)&gInstructions[ 3201] // VGF2P8AFFINEINVQB Vx,Hx,Wx,Ib }; -const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_62_pp_01_l = +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_cf_pp_01_w = { - ND_ILUT_EX_L, + ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_62_pp_01_l_00_leaf, - /* 01 */ (const void *)ND_NULL, - /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)ND_NULL, + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_cf_pp_01_w_01_leaf, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_62_pp = +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_cf_pp = { ND_ILUT_EX_PP, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_62_pp_01_l, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_cf_pp_01_w, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_61_pp_01_l_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_ce_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3447] // VPCMPESTRI Vdq,Wdq,Ib + (const void *)&gInstructions[ 3203] // VGF2P8AFFINEQB Vx,Hx,Wx,Ib }; -const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_61_pp_01_l = +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_ce_pp_01_w = { - ND_ILUT_EX_L, + ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_61_pp_01_l_00_leaf, - /* 01 */ (const void *)ND_NULL, - /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)ND_NULL, + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_ce_pp_01_w_01_leaf, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_61_pp = +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_ce_pp = { ND_ILUT_EX_PP, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_61_pp_01_l, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_ce_pp_01_w, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_60_pp_01_l_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_7f_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3448] // VPCMPESTRM Vdq,Wdq,Ib + (const void *)&gInstructions[ 3156] // VFNMSUBSD Vdq,Hdq,Ldq,Wsd }; -const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_60_pp_01_l = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_7f_pp_01_w_00_leaf = { - ND_ILUT_EX_L, + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3155] // VFNMSUBSD Vdq,Hdq,Wsd,Ldq +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_7f_pp_01_w = +{ + ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_60_pp_01_l_00_leaf, - /* 01 */ (const void *)ND_NULL, - /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)ND_NULL, + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_7f_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_7f_pp_01_w_01_leaf, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_60_pp = +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_7f_pp = { ND_ILUT_EX_PP, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_60_pp_01_l, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_7f_pp_01_w, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_5f_pp_01_w_01_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_7e_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3023] // VFMSUBADDPD Vx,Hx,Lx,Wx + (const void *)&gInstructions[ 3158] // VFNMSUBSS Vdq,Hdq,Ldq,Wss }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_5f_pp_01_w_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_7e_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3022] // VFMSUBADDPD Vx,Hx,Wx,Lx + (const void *)&gInstructions[ 3157] // VFNMSUBSS Vdq,Hdq,Wss,Ldq }; -const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_5f_pp_01_w = +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_7e_pp_01_w = { ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_5f_pp_01_w_00_leaf, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_5f_pp_01_w_01_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_7e_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_7e_pp_01_w_01_leaf, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_5f_pp = +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_7e_pp = { ND_ILUT_EX_PP, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_5f_pp_01_w, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_7e_pp_01_w, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_5e_pp_01_w_01_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_7d_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3025] // VFMSUBADDPS Vx,Hx,Lx,Wx + (const void *)&gInstructions[ 3152] // VFNMSUBPD Vx,Hx,Lx,Wx }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_5e_pp_01_w_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_7d_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3024] // VFMSUBADDPS Vx,Hx,Wx,Lx + (const void *)&gInstructions[ 3151] // VFNMSUBPD Vx,Hx,Wx,Lx }; -const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_5e_pp_01_w = +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_7d_pp_01_w = { ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_5e_pp_01_w_00_leaf, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_5e_pp_01_w_01_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_7d_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_7d_pp_01_w_01_leaf, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_5e_pp = +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_7d_pp = { ND_ILUT_EX_PP, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_5e_pp_01_w, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_7d_pp_01_w, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_5d_pp_01_w_01_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_7c_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2971] // VFMADDSUBPD Vx,Hx,Lx,Wx + (const void *)&gInstructions[ 3154] // VFNMSUBPS Vx,Hx,Lx,Wx }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_5d_pp_01_w_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_7c_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2970] // VFMADDSUBPD Vx,Hx,Wx,Lx + (const void *)&gInstructions[ 3153] // VFNMSUBPS Vx,Hx,Wx,Lx }; -const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_5d_pp_01_w = +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_7c_pp_01_w = { ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_5d_pp_01_w_00_leaf, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_5d_pp_01_w_01_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_7c_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_7c_pp_01_w_01_leaf, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_5d_pp = +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_7c_pp = { ND_ILUT_EX_PP, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_5d_pp_01_w, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_7c_pp_01_w, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_5c_pp_01_w_01_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_7b_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2973] // VFMADDSUBPS Vx,Hx,Lx,Wx + (const void *)&gInstructions[ 3115] // VFNMADDSD Vdq,Hdq,Ldq,Wsd }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_5c_pp_01_w_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_7b_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2972] // VFMADDSUBPS Vx,Hx,Wx,Lx + (const void *)&gInstructions[ 3114] // VFNMADDSD Vdq,Hdq,Wsd,Ldq }; -const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_5c_pp_01_w = +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_7b_pp_01_w = { ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_5c_pp_01_w_00_leaf, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_5c_pp_01_w_01_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_7b_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_7b_pp_01_w_01_leaf, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_5c_pp = +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_7b_pp = { ND_ILUT_EX_PP, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_5c_pp_01_w, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_7b_pp_01_w, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_4c_pp_01_w_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_7a_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3417] // VPBLENDVB Vx,Hx,Wx,Lx + (const void *)&gInstructions[ 3117] // VFNMADDSS Vdq,Hdq,Ldq,Wss }; -const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_4c_pp_01_w = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_7a_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3116] // VFNMADDSS Vdq,Hdq,Wss,Ldq +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_7a_pp_01_w = { ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_4c_pp_01_w_00_leaf, - /* 01 */ (const void *)ND_NULL, + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_7a_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_7a_pp_01_w_01_leaf, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_4c_pp = +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_7a_pp = { ND_ILUT_EX_PP, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_4c_pp_01_w, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_7a_pp_01_w, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_4b_pp_01_w_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_79_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2684] // VBLENDVPD Vx,Hx,Wx,Lx + (const void *)&gInstructions[ 3111] // VFNMADDPD Vx,Hx,Lx,Wx }; -const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_4b_pp_01_w = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_79_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3110] // VFNMADDPD Vx,Hx,Wx,Lx +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_79_pp_01_w = { ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_4b_pp_01_w_00_leaf, - /* 01 */ (const void *)ND_NULL, + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_79_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_79_pp_01_w_01_leaf, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_4b_pp = +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_79_pp = { ND_ILUT_EX_PP, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_4b_pp_01_w, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_79_pp_01_w, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_4a_pp_01_w_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_78_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2685] // VBLENDVPS Vx,Hx,Wx,Lx + (const void *)&gInstructions[ 3113] // VFNMADDPS Vx,Hx,Lx,Wx }; -const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_4a_pp_01_w = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_78_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3112] // VFNMADDPS Vx,Hx,Wx,Lx +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_78_pp_01_w = { ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_4a_pp_01_w_00_leaf, - /* 01 */ (const void *)ND_NULL, + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_78_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_78_pp_01_w_01_leaf, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_4a_pp = +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_78_pp = { ND_ILUT_EX_PP, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_4a_pp_01_w, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_78_pp_01_w, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_49_pp_01_w_01_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_6f_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3523] // VPERMIL2PD Vx,Hx,Lx,Wx,m2zIb + (const void *)&gInstructions[ 3072] // VFMSUBSD Vdq,Hdq,Ldq,Wsd }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_49_pp_01_w_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_6f_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3522] // VPERMIL2PD Vx,Hx,Wx,Lx,m2zIb + (const void *)&gInstructions[ 3071] // VFMSUBSD Vdq,Hdq,Wsd,Ldq }; -const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_49_pp_01_w = +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_6f_pp_01_w = { ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_49_pp_01_w_00_leaf, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_49_pp_01_w_01_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_6f_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_6f_pp_01_w_01_leaf, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_49_pp = +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_6f_pp = { ND_ILUT_EX_PP, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_49_pp_01_w, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_6f_pp_01_w, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_48_pp_01_w_01_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_6e_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3525] // VPERMIL2PS Vx,Hx,Lx,Wx,m2zIb + (const void *)&gInstructions[ 3074] // VFMSUBSS Vdq,Hdq,Ldq,Wss }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_48_pp_01_w_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_6e_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3524] // VPERMIL2PS Vx,Hx,Wx,Lx,m2zIb + (const void *)&gInstructions[ 3073] // VFMSUBSS Vdq,Hdq,Wss,Ldq }; -const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_48_pp_01_w = +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_6e_pp_01_w = { ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_48_pp_01_w_00_leaf, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_48_pp_01_w_01_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_6e_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_6e_pp_01_w_01_leaf, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_48_pp = +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_6e_pp = { ND_ILUT_EX_PP, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_48_pp_01_w, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_6e_pp_01_w, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_46_pp_01_l_01_w_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_6d_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3512] // VPERM2I128 Vqq,Hqq,Wqq,Ib + (const void *)&gInstructions[ 3068] // VFMSUBPD Vx,Hx,Lx,Wx }; -const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_46_pp_01_l_01_w = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_6d_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3067] // VFMSUBPD Vx,Hx,Wx,Lx +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_6d_pp_01_w = { ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_46_pp_01_l_01_w_00_leaf, - /* 01 */ (const void *)ND_NULL, + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_6d_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_6d_pp_01_w_01_leaf, } }; -const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_46_pp_01_l = +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_6d_pp = { - ND_ILUT_EX_L, + ND_ILUT_EX_PP, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_46_pp_01_l_01_w, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_6d_pp_01_w, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_46_pp = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_6c_pp_01_w_01_leaf = { - ND_ILUT_EX_PP, - { - /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_46_pp_01_l, - /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)ND_NULL, - } + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3070] // VFMSUBPS Vx,Hx,Lx,Wx }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_44_pp_01_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_6c_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3434] // VPCLMULQDQ Vx,Hx,Wx,Ib + (const void *)&gInstructions[ 3069] // VFMSUBPS Vx,Hx,Wx,Lx }; -const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_44_pp = +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_6c_pp_01_w = { - ND_ILUT_EX_PP, + ND_ILUT_EX_W, { - /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_44_pp_01_leaf, - /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)ND_NULL, + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_6c_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_6c_pp_01_w_01_leaf, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_42_pp_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3340] // VMPSADBW Vx,Hx,Wx,Ib -}; - -const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_42_pp = +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_6c_pp = { ND_ILUT_EX_PP, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_42_pp_01_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_6c_pp_01_w, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_41_pp_01_l_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_6b_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2881] // VDPPD Vdq,Hdq,Wdq,Ib + (const void *)&gInstructions[ 2993] // VFMADDSD Vdq,Hdq,Ldq,Wsd }; -const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_41_pp_01_l = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_6b_pp_01_w_00_leaf = { - ND_ILUT_EX_L, - { - /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_41_pp_01_l_00_leaf, - /* 01 */ (const void *)ND_NULL, - /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)ND_NULL, - } + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2992] // VFMADDSD Vdq,Hdq,Wsd,Ldq }; -const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_41_pp = +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_6b_pp_01_w = { - ND_ILUT_EX_PP, + ND_ILUT_EX_W, { - /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_41_pp_01_l, - /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)ND_NULL, + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_6b_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_6b_pp_01_w_01_leaf, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_40_pp_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2883] // VDPPS Vx,Hx,Wx,Ib -}; - -const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_40_pp = +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_6b_pp = { ND_ILUT_EX_PP, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_40_pp_01_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_6b_pp_01_w, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_39_pp_01_l_01_w_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_6a_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2895] // VEXTRACTI128 Wdq,Vqq,Ib + (const void *)&gInstructions[ 2995] // VFMADDSS Vdq,Hdq,Ldq,Wss }; -const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_39_pp_01_l_01_w = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_6a_pp_01_w_00_leaf = { - ND_ILUT_EX_W, - { - /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_39_pp_01_l_01_w_00_leaf, - /* 01 */ (const void *)ND_NULL, - } + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2994] // VFMADDSS Vdq,Hdq,Wss,Ldq }; -const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_39_pp_01_l = +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_6a_pp_01_w = { - ND_ILUT_EX_L, + ND_ILUT_EX_W, { - /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_39_pp_01_l_01_w, - /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)ND_NULL, + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_6a_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_6a_pp_01_w_01_leaf, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_39_pp = +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_6a_pp = { ND_ILUT_EX_PP, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_39_pp_01_l, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_6a_pp_01_w, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_38_pp_01_l_01_w_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_69_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3174] // VINSERTI128 Vqq,Hqq,Wdq,Ib + (const void *)&gInstructions[ 2989] // VFMADDPD Vx,Hx,Lx,Wx }; -const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_38_pp_01_l_01_w = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_69_pp_01_w_00_leaf = { - ND_ILUT_EX_W, - { - /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_38_pp_01_l_01_w_00_leaf, - /* 01 */ (const void *)ND_NULL, - } + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2988] // VFMADDPD Vx,Hx,Wx,Lx }; -const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_38_pp_01_l = +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_69_pp_01_w = { - ND_ILUT_EX_L, + ND_ILUT_EX_W, { - /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_38_pp_01_l_01_w, - /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)ND_NULL, + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_69_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_69_pp_01_w_01_leaf, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_38_pp = +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_69_pp = { ND_ILUT_EX_PP, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_38_pp_01_l, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_69_pp_01_w, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_33_pp_01_modrmmod_01_l_00_w_01_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_68_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1278] // KSHIFTLQ rKq,mKq,Ib + (const void *)&gInstructions[ 2991] // VFMADDPS Vx,Hx,Lx,Wx }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_33_pp_01_modrmmod_01_l_00_w_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_68_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1277] // KSHIFTLD rKd,mKd,Ib + (const void *)&gInstructions[ 2990] // VFMADDPS Vx,Hx,Wx,Lx }; -const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_33_pp_01_modrmmod_01_l_00_w = +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_68_pp_01_w = { ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_33_pp_01_modrmmod_01_l_00_w_00_leaf, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_33_pp_01_modrmmod_01_l_00_w_01_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_68_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_68_pp_01_w_01_leaf, } }; -const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_33_pp_01_modrmmod_01_l = +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_68_pp = { - ND_ILUT_EX_L, + ND_ILUT_EX_PP, { - /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_33_pp_01_modrmmod_01_l_00_w, - /* 01 */ (const void *)ND_NULL, + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_68_pp_01_w, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_MODRM_MOD gVexMap_mmmmm_03_opcode_33_pp_01_modrmmod = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_63_pp_01_l_00_leaf = { - ND_ILUT_MODRM_MOD, + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3502] // VPCMPISTRI Vdq,Wdq,Ib +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_63_pp_01_l = +{ + ND_ILUT_EX_L, { - /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_33_pp_01_modrmmod_01_l, + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_63_pp_01_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_33_pp = +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_63_pp = { ND_ILUT_EX_PP, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_33_pp_01_modrmmod, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_63_pp_01_l, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_32_pp_01_modrmmod_01_l_00_w_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1279] // KSHIFTLW rKw,mKw,Ib -}; - -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_32_pp_01_modrmmod_01_l_00_w_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_62_pp_01_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1276] // KSHIFTLB rKb,mKb,Ib -}; - -const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_32_pp_01_modrmmod_01_l_00_w = -{ - ND_ILUT_EX_W, - { - /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_32_pp_01_modrmmod_01_l_00_w_00_leaf, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_32_pp_01_modrmmod_01_l_00_w_01_leaf, - } + (const void *)&gInstructions[ 3503] // VPCMPISTRM Vdq,Wdq,Ib }; -const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_32_pp_01_modrmmod_01_l = +const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_62_pp_01_l = { ND_ILUT_EX_L, { - /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_32_pp_01_modrmmod_01_l_00_w, + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_62_pp_01_l_00_leaf, /* 01 */ (const void *)ND_NULL, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_MODRM_MOD gVexMap_mmmmm_03_opcode_32_pp_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_32_pp_01_modrmmod_01_l, - } -}; - -const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_32_pp = +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_62_pp = { ND_ILUT_EX_PP, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_32_pp_01_modrmmod, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_62_pp_01_l, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_31_pp_01_modrmmod_01_l_00_w_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1282] // KSHIFTRQ rKq,mKq,Ib -}; - -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_31_pp_01_modrmmod_01_l_00_w_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_61_pp_01_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1281] // KSHIFTRD rKd,mKd,Ib + (const void *)&gInstructions[ 3492] // VPCMPESTRI Vdq,Wdq,Ib }; -const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_31_pp_01_modrmmod_01_l_00_w = +const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_61_pp_01_l = { - ND_ILUT_EX_W, + ND_ILUT_EX_L, { - /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_31_pp_01_modrmmod_01_l_00_w_00_leaf, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_31_pp_01_modrmmod_01_l_00_w_01_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_61_pp_01_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_31_pp_01_modrmmod_01_l = +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_61_pp = { - ND_ILUT_EX_L, + ND_ILUT_EX_PP, { - /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_31_pp_01_modrmmod_01_l_00_w, - /* 01 */ (const void *)ND_NULL, + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_61_pp_01_l, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_MODRM_MOD gVexMap_mmmmm_03_opcode_31_pp_01_modrmmod = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_60_pp_01_l_00_leaf = { - ND_ILUT_MODRM_MOD, + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3493] // VPCMPESTRM Vdq,Wdq,Ib +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_60_pp_01_l = +{ + ND_ILUT_EX_L, { - /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_31_pp_01_modrmmod_01_l, + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_60_pp_01_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_31_pp = +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_60_pp = { ND_ILUT_EX_PP, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_31_pp_01_modrmmod, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_60_pp_01_l, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_30_pp_01_modrmmod_01_l_00_w_01_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_5f_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1283] // KSHIFTRW rKw,mKw,Ib + (const void *)&gInstructions[ 3064] // VFMSUBADDPD Vx,Hx,Lx,Wx }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_30_pp_01_modrmmod_01_l_00_w_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_5f_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1280] // KSHIFTRB rKb,mKb,Ib + (const void *)&gInstructions[ 3063] // VFMSUBADDPD Vx,Hx,Wx,Lx }; -const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_30_pp_01_modrmmod_01_l_00_w = +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_5f_pp_01_w = { ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_30_pp_01_modrmmod_01_l_00_w_00_leaf, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_30_pp_01_modrmmod_01_l_00_w_01_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_5f_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_5f_pp_01_w_01_leaf, } }; -const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_30_pp_01_modrmmod_01_l = +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_5f_pp = { - ND_ILUT_EX_L, + ND_ILUT_EX_PP, { - /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_30_pp_01_modrmmod_01_l_00_w, - /* 01 */ (const void *)ND_NULL, + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_5f_pp_01_w, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_MODRM_MOD gVexMap_mmmmm_03_opcode_30_pp_01_modrmmod = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_5e_pp_01_w_01_leaf = { - ND_ILUT_MODRM_MOD, + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3066] // VFMSUBADDPS Vx,Hx,Lx,Wx +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_5e_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3065] // VFMSUBADDPS Vx,Hx,Wx,Lx +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_5e_pp_01_w = +{ + ND_ILUT_EX_W, { - /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_30_pp_01_modrmmod_01_l, + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_5e_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_5e_pp_01_w_01_leaf, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_30_pp = +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_5e_pp = { ND_ILUT_EX_PP, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_30_pp_01_modrmmod, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_5e_pp_01_w, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_22_pp_01_l_00_wi_01_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_5d_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3610] // VPINSRQ Vdq,Hdq,Ey,Ib + (const void *)&gInstructions[ 3012] // VFMADDSUBPD Vx,Hx,Lx,Wx }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_22_pp_01_l_00_wi_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_5d_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3608] // VPINSRD Vdq,Hdq,Ey,Ib + (const void *)&gInstructions[ 3011] // VFMADDSUBPD Vx,Hx,Wx,Lx }; -const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_22_pp_01_l_00_wi = +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_5d_pp_01_w = { - ND_ILUT_EX_WI, + ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_22_pp_01_l_00_wi_00_leaf, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_22_pp_01_l_00_wi_01_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_5d_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_5d_pp_01_w_01_leaf, } }; -const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_22_pp_01_l = +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_5d_pp = { - ND_ILUT_EX_L, + ND_ILUT_EX_PP, { - /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_22_pp_01_l_00_wi, - /* 01 */ (const void *)ND_NULL, + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_5d_pp_01_w, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_22_pp = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_5c_pp_01_w_01_leaf = { - ND_ILUT_EX_PP, - { - /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_22_pp_01_l, - /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)ND_NULL, - } + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3014] // VFMADDSUBPS Vx,Hx,Lx,Wx }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_21_pp_01_modrmmod_01_l_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_5c_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3182] // VINSERTPS Vdq,Hdq,Udq,Ib + (const void *)&gInstructions[ 3013] // VFMADDSUBPS Vx,Hx,Wx,Lx }; -const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_21_pp_01_modrmmod_01_l = +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_5c_pp_01_w = { - ND_ILUT_EX_L, + ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_21_pp_01_modrmmod_01_l_00_leaf, - /* 01 */ (const void *)ND_NULL, + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_5c_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_5c_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_5c_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_5c_pp_01_w, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_21_pp_01_modrmmod_00_l_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_4c_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3181] // VINSERTPS Vdq,Hdq,Md,Ib + (const void *)&gInstructions[ 3462] // VPBLENDVB Vx,Hx,Wx,Lx }; -const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_21_pp_01_modrmmod_00_l = +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_4c_pp_01_w = { - ND_ILUT_EX_L, + ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_21_pp_01_modrmmod_00_l_00_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_4c_pp_01_w_00_leaf, /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_4c_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_4c_pp_01_w, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_MODRM_MOD gVexMap_mmmmm_03_opcode_21_pp_01_modrmmod = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_4b_pp_01_w_00_leaf = { - ND_ILUT_MODRM_MOD, + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2725] // VBLENDVPD Vx,Hx,Wx,Lx +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_4b_pp_01_w = +{ + ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_21_pp_01_modrmmod_00_l, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_21_pp_01_modrmmod_01_l, + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_4b_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_21_pp = +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_4b_pp = { ND_ILUT_EX_PP, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_21_pp_01_modrmmod, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_4b_pp_01_w, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_20_pp_01_modrmmod_01_l_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_4a_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3606] // VPINSRB Vdq,Hdq,Rd,Ib + (const void *)&gInstructions[ 2726] // VBLENDVPS Vx,Hx,Wx,Lx }; -const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_20_pp_01_modrmmod_01_l = +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_4a_pp_01_w = { - ND_ILUT_EX_L, + ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_20_pp_01_modrmmod_01_l_00_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_4a_pp_01_w_00_leaf, /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_4a_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_4a_pp_01_w, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_20_pp_01_modrmmod_00_l_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_49_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3605] // VPINSRB Vdq,Hdq,Mb,Ib + (const void *)&gInstructions[ 3568] // VPERMIL2PD Vx,Hx,Lx,Wx,m2zIb }; -const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_20_pp_01_modrmmod_00_l = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_49_pp_01_w_00_leaf = { - ND_ILUT_EX_L, - { - /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_20_pp_01_modrmmod_00_l_00_leaf, - /* 01 */ (const void *)ND_NULL, - /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)ND_NULL, - } + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3567] // VPERMIL2PD Vx,Hx,Wx,Lx,m2zIb }; -const ND_TABLE_MODRM_MOD gVexMap_mmmmm_03_opcode_20_pp_01_modrmmod = +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_49_pp_01_w = { - ND_ILUT_MODRM_MOD, + ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_20_pp_01_modrmmod_00_l, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_20_pp_01_modrmmod_01_l, + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_49_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_49_pp_01_w_01_leaf, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_20_pp = +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_49_pp = { ND_ILUT_EX_PP, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_20_pp_01_modrmmod, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_49_pp_01_w, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_1d_pp_01_l_01_w_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_48_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2784] // VCVTPS2PH Wdq,Vqq,Ib -}; - -const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_1d_pp_01_l_01_w = -{ - ND_ILUT_EX_W, - { - /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_1d_pp_01_l_01_w_00_leaf, - /* 01 */ (const void *)ND_NULL, - } + (const void *)&gInstructions[ 3570] // VPERMIL2PS Vx,Hx,Lx,Wx,m2zIb }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_1d_pp_01_l_00_w_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_48_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2783] // VCVTPS2PH Wq,Vdq,Ib + (const void *)&gInstructions[ 3569] // VPERMIL2PS Vx,Hx,Wx,Lx,m2zIb }; -const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_1d_pp_01_l_00_w = +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_48_pp_01_w = { ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_1d_pp_01_l_00_w_00_leaf, - /* 01 */ (const void *)ND_NULL, - } -}; - -const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_1d_pp_01_l = -{ - ND_ILUT_EX_L, - { - /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_1d_pp_01_l_00_w, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_1d_pp_01_l_01_w, - /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)ND_NULL, + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_48_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_48_pp_01_w_01_leaf, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_1d_pp = +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_48_pp = { ND_ILUT_EX_PP, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_1d_pp_01_l, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_48_pp_01_w, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_19_pp_01_l_01_w_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_46_pp_01_l_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2890] // VEXTRACTF128 Wdq,Vqq,Ib + (const void *)&gInstructions[ 3557] // VPERM2I128 Vqq,Hqq,Wqq,Ib }; -const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_19_pp_01_l_01_w = +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_46_pp_01_l_01_w = { ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_19_pp_01_l_01_w_00_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_46_pp_01_l_01_w_00_leaf, /* 01 */ (const void *)ND_NULL, } }; -const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_19_pp_01_l = +const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_46_pp_01_l = { ND_ILUT_EX_L, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_19_pp_01_l_01_w, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_46_pp_01_l_01_w, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_19_pp = +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_46_pp = { ND_ILUT_EX_PP, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_19_pp_01_l, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_46_pp_01_l, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_18_pp_01_l_01_w_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_44_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3169] // VINSERTF128 Vqq,Hqq,Wdq,Ib -}; - -const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_18_pp_01_l_01_w = -{ - ND_ILUT_EX_W, - { - /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_18_pp_01_l_01_w_00_leaf, - /* 01 */ (const void *)ND_NULL, - } + (const void *)&gInstructions[ 3479] // VPCLMULQDQ Vx,Hx,Wx,Ib }; -const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_18_pp_01_l = +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_44_pp = { - ND_ILUT_EX_L, + ND_ILUT_EX_PP, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_18_pp_01_l_01_w, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_44_pp_01_leaf, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_18_pp = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_42_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3385] // VMPSADBW Vx,Hx,Wx,Ib +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_42_pp = { ND_ILUT_EX_PP, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_18_pp_01_l, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_42_pp_01_leaf, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_17_pp_01_modrmmod_01_l_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_41_pp_01_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2903] // VEXTRACTPS Ry,Vdq,Ib + (const void *)&gInstructions[ 2922] // VDPPD Vdq,Hdq,Wdq,Ib }; -const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_17_pp_01_modrmmod_01_l = +const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_41_pp_01_l = { ND_ILUT_EX_L, { - /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_17_pp_01_modrmmod_01_l_00_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_41_pp_01_l_00_leaf, /* 01 */ (const void *)ND_NULL, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_17_pp_01_modrmmod_00_l_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2902] // VEXTRACTPS Md,Vdq,Ib -}; - -const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_17_pp_01_modrmmod_00_l = +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_41_pp = { - ND_ILUT_EX_L, + ND_ILUT_EX_PP, { - /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_17_pp_01_modrmmod_00_l_00_leaf, - /* 01 */ (const void *)ND_NULL, + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_41_pp_01_l, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_MODRM_MOD gVexMap_mmmmm_03_opcode_17_pp_01_modrmmod = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_40_pp_01_leaf = { - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_17_pp_01_modrmmod_00_l, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_17_pp_01_modrmmod_01_l, - } + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2924] // VDPPS Vx,Hx,Wx,Ib }; -const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_17_pp = +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_40_pp = { ND_ILUT_EX_PP, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_17_pp_01_modrmmod, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_40_pp_01_leaf, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_16_pp_01_modrmmod_01_l_00_wi_01_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_39_pp_01_l_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3566] // VPEXTRQ Ry,Vdq,Ib + (const void *)&gInstructions[ 2936] // VEXTRACTI128 Wdq,Vqq,Ib }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_16_pp_01_modrmmod_01_l_00_wi_00_leaf = +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_39_pp_01_l_01_w = { - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3562] // VPEXTRD Ry,Vdq,Ib -}; - -const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_16_pp_01_modrmmod_01_l_00_wi = -{ - ND_ILUT_EX_WI, + ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_16_pp_01_modrmmod_01_l_00_wi_00_leaf, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_16_pp_01_modrmmod_01_l_00_wi_01_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_39_pp_01_l_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, } }; -const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_16_pp_01_modrmmod_01_l = +const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_39_pp_01_l = { ND_ILUT_EX_L, { - /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_16_pp_01_modrmmod_01_l_00_wi, - /* 01 */ (const void *)ND_NULL, + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_39_pp_01_l_01_w, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_16_pp_01_modrmmod_00_l_00_wi_01_leaf = +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_39_pp = { - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3565] // VPEXTRQ Mq,Vdq,Ib + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_39_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_16_pp_01_modrmmod_00_l_00_wi_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_38_pp_01_l_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3561] // VPEXTRD Md,Vdq,Ib + (const void *)&gInstructions[ 3215] // VINSERTI128 Vqq,Hqq,Wdq,Ib }; -const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_16_pp_01_modrmmod_00_l_00_wi = +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_38_pp_01_l_01_w = { - ND_ILUT_EX_WI, + ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_16_pp_01_modrmmod_00_l_00_wi_00_leaf, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_16_pp_01_modrmmod_00_l_00_wi_01_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_38_pp_01_l_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, } }; -const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_16_pp_01_modrmmod_00_l = +const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_38_pp_01_l = { ND_ILUT_EX_L, { - /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_16_pp_01_modrmmod_00_l_00_wi, - /* 01 */ (const void *)ND_NULL, + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_38_pp_01_l_01_w, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_MODRM_MOD gVexMap_mmmmm_03_opcode_16_pp_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_16_pp_01_modrmmod_00_l, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_16_pp_01_modrmmod_01_l, - } -}; - -const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_16_pp = +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_38_pp = { ND_ILUT_EX_PP, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_16_pp_01_modrmmod, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_38_pp_01_l, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_15_pp_01_modrmmod_01_l_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_33_pp_01_modrmmod_01_l_00_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3572] // VPEXTRW Ry,Vdq,Ib + (const void *)&gInstructions[ 1278] // KSHIFTLQ rKq,mKq,Ib }; -const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_15_pp_01_modrmmod_01_l = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_33_pp_01_modrmmod_01_l_00_w_00_leaf = { - ND_ILUT_EX_L, - { - /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_15_pp_01_modrmmod_01_l_00_leaf, - /* 01 */ (const void *)ND_NULL, - /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)ND_NULL, - } + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1277] // KSHIFTLD rKd,mKd,Ib }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_15_pp_01_modrmmod_00_l_00_leaf = +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_33_pp_01_modrmmod_01_l_00_w = { - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3571] // VPEXTRW Mw,Vdq,Ib + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_33_pp_01_modrmmod_01_l_00_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_33_pp_01_modrmmod_01_l_00_w_01_leaf, + } }; -const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_15_pp_01_modrmmod_00_l = +const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_33_pp_01_modrmmod_01_l = { ND_ILUT_EX_L, { - /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_15_pp_01_modrmmod_00_l_00_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_33_pp_01_modrmmod_01_l_00_w, /* 01 */ (const void *)ND_NULL, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_MODRM_MOD gVexMap_mmmmm_03_opcode_15_pp_01_modrmmod = +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_03_opcode_33_pp_01_modrmmod = { ND_ILUT_MODRM_MOD, { - /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_15_pp_01_modrmmod_00_l, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_15_pp_01_modrmmod_01_l, + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_33_pp_01_modrmmod_01_l, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_15_pp = +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_33_pp = { ND_ILUT_EX_PP, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_15_pp_01_modrmmod, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_33_pp_01_modrmmod, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_14_pp_01_modrmmod_01_l_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_32_pp_01_modrmmod_01_l_00_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3558] // VPEXTRB Ry,Vdq,Ib + (const void *)&gInstructions[ 1279] // KSHIFTLW rKw,mKw,Ib }; -const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_14_pp_01_modrmmod_01_l = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_32_pp_01_modrmmod_01_l_00_w_00_leaf = { - ND_ILUT_EX_L, - { - /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_14_pp_01_modrmmod_01_l_00_leaf, - /* 01 */ (const void *)ND_NULL, - /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)ND_NULL, - } + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1276] // KSHIFTLB rKb,mKb,Ib }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_14_pp_01_modrmmod_00_l_00_leaf = +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_32_pp_01_modrmmod_01_l_00_w = { - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3557] // VPEXTRB Mb,Vdq,Ib + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_32_pp_01_modrmmod_01_l_00_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_32_pp_01_modrmmod_01_l_00_w_01_leaf, + } }; -const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_14_pp_01_modrmmod_00_l = +const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_32_pp_01_modrmmod_01_l = { ND_ILUT_EX_L, { - /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_14_pp_01_modrmmod_00_l_00_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_32_pp_01_modrmmod_01_l_00_w, /* 01 */ (const void *)ND_NULL, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_MODRM_MOD gVexMap_mmmmm_03_opcode_14_pp_01_modrmmod = +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_03_opcode_32_pp_01_modrmmod = { ND_ILUT_MODRM_MOD, { - /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_14_pp_01_modrmmod_00_l, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_14_pp_01_modrmmod_01_l, + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_32_pp_01_modrmmod_01_l, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_14_pp = +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_32_pp = { ND_ILUT_EX_PP, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_14_pp_01_modrmmod, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_32_pp_01_modrmmod, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_0f_pp_01_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_31_pp_01_modrmmod_01_l_00_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3401] // VPALIGNR Vx,Hx,Wx,Ib -}; - -const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_0f_pp = -{ - ND_ILUT_EX_PP, - { - /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_0f_pp_01_leaf, - /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)ND_NULL, - } + (const void *)&gInstructions[ 1282] // KSHIFTRQ rKq,mKq,Ib }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_0e_pp_01_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_31_pp_01_modrmmod_01_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3418] // VPBLENDW Vx,Hx,Wx,Ib + (const void *)&gInstructions[ 1281] // KSHIFTRD rKd,mKd,Ib }; -const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_0e_pp = +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_31_pp_01_modrmmod_01_l_00_w = { - ND_ILUT_EX_PP, + ND_ILUT_EX_W, { - /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_0e_pp_01_leaf, - /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)ND_NULL, + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_31_pp_01_modrmmod_01_l_00_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_31_pp_01_modrmmod_01_l_00_w_01_leaf, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_0d_pp_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2682] // VBLENDPD Vx,Hx,Wx,Ib -}; - -const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_0d_pp = +const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_31_pp_01_modrmmod_01_l = { - ND_ILUT_EX_PP, + ND_ILUT_EX_L, { - /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_0d_pp_01_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_31_pp_01_modrmmod_01_l_00_w, + /* 01 */ (const void *)ND_NULL, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_0c_pp_01_leaf = +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_03_opcode_31_pp_01_modrmmod = { - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2683] // VBLENDPS Vx,Hx,Wx,Ib + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_31_pp_01_modrmmod_01_l, + } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_0c_pp = +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_31_pp = { ND_ILUT_EX_PP, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_0c_pp_01_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_31_pp_01_modrmmod, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_0b_pp_01_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_30_pp_01_modrmmod_01_l_00_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3954] // VROUNDSD Vsd,Hsd,Wsd,Ib + (const void *)&gInstructions[ 1283] // KSHIFTRW rKw,mKw,Ib }; -const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_0b_pp = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_30_pp_01_modrmmod_01_l_00_w_00_leaf = { - ND_ILUT_EX_PP, - { - /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_0b_pp_01_leaf, - /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)ND_NULL, - } + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1280] // KSHIFTRB rKb,mKb,Ib }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_0a_pp_01_leaf = +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_30_pp_01_modrmmod_01_l_00_w = { - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3955] // VROUNDSS Vss,Hss,Wss,Ib + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_30_pp_01_modrmmod_01_l_00_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_30_pp_01_modrmmod_01_l_00_w_01_leaf, + } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_0a_pp = +const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_30_pp_01_modrmmod_01_l = { - ND_ILUT_EX_PP, + ND_ILUT_EX_L, { - /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_0a_pp_01_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_30_pp_01_modrmmod_01_l_00_w, + /* 01 */ (const void *)ND_NULL, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_09_pp_01_leaf = +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_03_opcode_30_pp_01_modrmmod = { - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3952] // VROUNDPD Vx,Wx,Ib + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_30_pp_01_modrmmod_01_l, + } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_09_pp = +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_30_pp = { ND_ILUT_EX_PP, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_09_pp_01_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_30_pp_01_modrmmod, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_08_pp_01_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_22_pp_01_l_00_wi_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3953] // VROUNDPS Vx,Wx,Ib -}; - -const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_08_pp = -{ - ND_ILUT_EX_PP, - { - /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_08_pp_01_leaf, - /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)ND_NULL, - } + (const void *)&gInstructions[ 3655] // VPINSRQ Vdq,Hdq,Ey,Ib }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_06_pp_01_l_01_w_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_22_pp_01_l_00_wi_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3511] // VPERM2F128 Vqq,Hqq,Wqq,Ib + (const void *)&gInstructions[ 3653] // VPINSRD Vdq,Hdq,Ey,Ib }; -const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_06_pp_01_l_01_w = +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_22_pp_01_l_00_wi = { - ND_ILUT_EX_W, + ND_ILUT_EX_WI, { - /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_06_pp_01_l_01_w_00_leaf, - /* 01 */ (const void *)ND_NULL, + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_22_pp_01_l_00_wi_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_22_pp_01_l_00_wi_01_leaf, } }; -const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_06_pp_01_l = +const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_22_pp_01_l = { ND_ILUT_EX_L, { - /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_06_pp_01_l_01_w, + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_22_pp_01_l_00_wi, + /* 01 */ (const void *)ND_NULL, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_06_pp = +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_22_pp = { ND_ILUT_EX_PP, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_06_pp_01_l, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_22_pp_01_l, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_05_pp_01_w_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_21_pp_01_modrmmod_01_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3529] // VPERMILPD Vx,Wx,Ib + (const void *)&gInstructions[ 3223] // VINSERTPS Vdq,Hdq,Udq,Ib }; -const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_05_pp_01_w = +const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_21_pp_01_modrmmod_01_l = { - ND_ILUT_EX_W, + ND_ILUT_EX_L, { - /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_05_pp_01_w_00_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_21_pp_01_modrmmod_01_l_00_leaf, /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_05_pp = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_21_pp_01_modrmmod_00_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3222] // VINSERTPS Vdq,Hdq,Md,Ib +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_21_pp_01_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_21_pp_01_modrmmod_00_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_03_opcode_21_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_21_pp_01_modrmmod_00_l, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_21_pp_01_modrmmod_01_l, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_21_pp = { ND_ILUT_EX_PP, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_05_pp_01_w, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_21_pp_01_modrmmod, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_04_pp_01_w_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_20_pp_01_modrmmod_01_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3533] // VPERMILPS Vx,Wx,Ib + (const void *)&gInstructions[ 3651] // VPINSRB Vdq,Hdq,Rd,Ib }; -const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_04_pp_01_w = +const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_20_pp_01_modrmmod_01_l = { - ND_ILUT_EX_W, + ND_ILUT_EX_L, { - /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_04_pp_01_w_00_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_20_pp_01_modrmmod_01_l_00_leaf, /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_04_pp = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_20_pp_01_modrmmod_00_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3650] // VPINSRB Vdq,Hdq,Mb,Ib +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_20_pp_01_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_20_pp_01_modrmmod_00_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_03_opcode_20_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_20_pp_01_modrmmod_00_l, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_20_pp_01_modrmmod_01_l, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_20_pp = { ND_ILUT_EX_PP, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_04_pp_01_w, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_20_pp_01_modrmmod, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_02_pp_01_w_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_1d_pp_01_l_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3412] // VPBLENDD Vx,Hx,Wx,Ib + (const void *)&gInstructions[ 2825] // VCVTPS2PH Wdq,Vqq,Ib }; -const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_02_pp_01_w = +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_1d_pp_01_l_01_w = { ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_02_pp_01_w_00_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_1d_pp_01_l_01_w_00_leaf, /* 01 */ (const void *)ND_NULL, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_02_pp = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_1d_pp_01_l_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2824] // VCVTPS2PH Wq,Vdq,Ib +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_1d_pp_01_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_1d_pp_01_l_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_1d_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_1d_pp_01_l_00_w, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_1d_pp_01_l_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_1d_pp = { ND_ILUT_EX_PP, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_02_pp_01_w, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_1d_pp_01_l, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_01_pp_01_l_01_w_01_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_19_pp_01_l_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3537] // VPERMPD Vqq,Wqq,Ib + (const void *)&gInstructions[ 2931] // VEXTRACTF128 Wdq,Vqq,Ib }; -const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_01_pp_01_l_01_w = +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_19_pp_01_l_01_w = { ND_ILUT_EX_W, { - /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_01_pp_01_l_01_w_01_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_19_pp_01_l_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, } }; -const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_01_pp_01_l = +const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_19_pp_01_l = { ND_ILUT_EX_L, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_01_pp_01_l_01_w, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_19_pp_01_l_01_w, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_01_pp = +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_19_pp = { ND_ILUT_EX_PP, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_01_pp_01_l, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_19_pp_01_l, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_00_pp_01_l_01_w_01_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_18_pp_01_l_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3543] // VPERMQ Vqq,Wqq,Ib + (const void *)&gInstructions[ 3210] // VINSERTF128 Vqq,Hqq,Wdq,Ib }; -const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_00_pp_01_l_01_w = +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_18_pp_01_l_01_w = { ND_ILUT_EX_W, { - /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_00_pp_01_l_01_w_01_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_18_pp_01_l_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, } }; -const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_00_pp_01_l = +const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_18_pp_01_l = { ND_ILUT_EX_L, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_00_pp_01_l_01_w, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_18_pp_01_l_01_w, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_00_pp = +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_18_pp = { ND_ILUT_EX_PP, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_00_pp_01_l, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_18_pp_01_l, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_OPCODE gVexMap_mmmmm_03_opcode = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_17_pp_01_modrmmod_01_l_00_leaf = { - ND_ILUT_OPCODE, + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2944] // VEXTRACTPS Ry,Vdq,Ib +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_17_pp_01_modrmmod_01_l = +{ + ND_ILUT_EX_L, { - /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_00_pp, - /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_01_pp, - /* 02 */ (const void *)&gVexMap_mmmmm_03_opcode_02_pp, + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_17_pp_01_modrmmod_01_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, - /* 04 */ (const void *)&gVexMap_mmmmm_03_opcode_04_pp, - /* 05 */ (const void *)&gVexMap_mmmmm_03_opcode_05_pp, - /* 06 */ (const void *)&gVexMap_mmmmm_03_opcode_06_pp, - /* 07 */ (const void *)ND_NULL, - /* 08 */ (const void *)&gVexMap_mmmmm_03_opcode_08_pp, - /* 09 */ (const void *)&gVexMap_mmmmm_03_opcode_09_pp, - /* 0a */ (const void *)&gVexMap_mmmmm_03_opcode_0a_pp, - /* 0b */ (const void *)&gVexMap_mmmmm_03_opcode_0b_pp, - /* 0c */ (const void *)&gVexMap_mmmmm_03_opcode_0c_pp, - /* 0d */ (const void *)&gVexMap_mmmmm_03_opcode_0d_pp, - /* 0e */ (const void *)&gVexMap_mmmmm_03_opcode_0e_pp, - /* 0f */ (const void *)&gVexMap_mmmmm_03_opcode_0f_pp, - /* 10 */ (const void *)ND_NULL, - /* 11 */ (const void *)ND_NULL, - /* 12 */ (const void *)ND_NULL, - /* 13 */ (const void *)ND_NULL, - /* 14 */ (const void *)&gVexMap_mmmmm_03_opcode_14_pp, - /* 15 */ (const void *)&gVexMap_mmmmm_03_opcode_15_pp, - /* 16 */ (const void *)&gVexMap_mmmmm_03_opcode_16_pp, - /* 17 */ (const void *)&gVexMap_mmmmm_03_opcode_17_pp, - /* 18 */ (const void *)&gVexMap_mmmmm_03_opcode_18_pp, - /* 19 */ (const void *)&gVexMap_mmmmm_03_opcode_19_pp, - /* 1a */ (const void *)ND_NULL, - /* 1b */ (const void *)ND_NULL, - /* 1c */ (const void *)ND_NULL, - /* 1d */ (const void *)&gVexMap_mmmmm_03_opcode_1d_pp, - /* 1e */ (const void *)ND_NULL, - /* 1f */ (const void *)ND_NULL, - /* 20 */ (const void *)&gVexMap_mmmmm_03_opcode_20_pp, - /* 21 */ (const void *)&gVexMap_mmmmm_03_opcode_21_pp, - /* 22 */ (const void *)&gVexMap_mmmmm_03_opcode_22_pp, - /* 23 */ (const void *)ND_NULL, - /* 24 */ (const void *)ND_NULL, - /* 25 */ (const void *)ND_NULL, - /* 26 */ (const void *)ND_NULL, - /* 27 */ (const void *)ND_NULL, - /* 28 */ (const void *)ND_NULL, - /* 29 */ (const void *)ND_NULL, - /* 2a */ (const void *)ND_NULL, - /* 2b */ (const void *)ND_NULL, - /* 2c */ (const void *)ND_NULL, - /* 2d */ (const void *)ND_NULL, - /* 2e */ (const void *)ND_NULL, - /* 2f */ (const void *)ND_NULL, - /* 30 */ (const void *)&gVexMap_mmmmm_03_opcode_30_pp, - /* 31 */ (const void *)&gVexMap_mmmmm_03_opcode_31_pp, - /* 32 */ (const void *)&gVexMap_mmmmm_03_opcode_32_pp, - /* 33 */ (const void *)&gVexMap_mmmmm_03_opcode_33_pp, - /* 34 */ (const void *)ND_NULL, - /* 35 */ (const void *)ND_NULL, - /* 36 */ (const void *)ND_NULL, - /* 37 */ (const void *)ND_NULL, - /* 38 */ (const void *)&gVexMap_mmmmm_03_opcode_38_pp, - /* 39 */ (const void *)&gVexMap_mmmmm_03_opcode_39_pp, - /* 3a */ (const void *)ND_NULL, - /* 3b */ (const void *)ND_NULL, - /* 3c */ (const void *)ND_NULL, - /* 3d */ (const void *)ND_NULL, - /* 3e */ (const void *)ND_NULL, - /* 3f */ (const void *)ND_NULL, - /* 40 */ (const void *)&gVexMap_mmmmm_03_opcode_40_pp, - /* 41 */ (const void *)&gVexMap_mmmmm_03_opcode_41_pp, - /* 42 */ (const void *)&gVexMap_mmmmm_03_opcode_42_pp, - /* 43 */ (const void *)ND_NULL, - /* 44 */ (const void *)&gVexMap_mmmmm_03_opcode_44_pp, - /* 45 */ (const void *)ND_NULL, - /* 46 */ (const void *)&gVexMap_mmmmm_03_opcode_46_pp, - /* 47 */ (const void *)ND_NULL, - /* 48 */ (const void *)&gVexMap_mmmmm_03_opcode_48_pp, - /* 49 */ (const void *)&gVexMap_mmmmm_03_opcode_49_pp, - /* 4a */ (const void *)&gVexMap_mmmmm_03_opcode_4a_pp, - /* 4b */ (const void *)&gVexMap_mmmmm_03_opcode_4b_pp, - /* 4c */ (const void *)&gVexMap_mmmmm_03_opcode_4c_pp, - /* 4d */ (const void *)ND_NULL, - /* 4e */ (const void *)ND_NULL, - /* 4f */ (const void *)ND_NULL, - /* 50 */ (const void *)ND_NULL, - /* 51 */ (const void *)ND_NULL, - /* 52 */ (const void *)ND_NULL, - /* 53 */ (const void *)ND_NULL, - /* 54 */ (const void *)ND_NULL, - /* 55 */ (const void *)ND_NULL, - /* 56 */ (const void *)ND_NULL, - /* 57 */ (const void *)ND_NULL, - /* 58 */ (const void *)ND_NULL, - /* 59 */ (const void *)ND_NULL, - /* 5a */ (const void *)ND_NULL, - /* 5b */ (const void *)ND_NULL, - /* 5c */ (const void *)&gVexMap_mmmmm_03_opcode_5c_pp, - /* 5d */ (const void *)&gVexMap_mmmmm_03_opcode_5d_pp, - /* 5e */ (const void *)&gVexMap_mmmmm_03_opcode_5e_pp, - /* 5f */ (const void *)&gVexMap_mmmmm_03_opcode_5f_pp, - /* 60 */ (const void *)&gVexMap_mmmmm_03_opcode_60_pp, - /* 61 */ (const void *)&gVexMap_mmmmm_03_opcode_61_pp, - /* 62 */ (const void *)&gVexMap_mmmmm_03_opcode_62_pp, - /* 63 */ (const void *)&gVexMap_mmmmm_03_opcode_63_pp, - /* 64 */ (const void *)ND_NULL, - /* 65 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_17_pp_01_modrmmod_00_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2943] // VEXTRACTPS Md,Vdq,Ib +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_17_pp_01_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_17_pp_01_modrmmod_00_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_03_opcode_17_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_17_pp_01_modrmmod_00_l, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_17_pp_01_modrmmod_01_l, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_17_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_17_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_16_pp_01_modrmmod_01_l_00_wi_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3611] // VPEXTRQ Ry,Vdq,Ib +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_16_pp_01_modrmmod_01_l_00_wi_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3607] // VPEXTRD Ry,Vdq,Ib +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_16_pp_01_modrmmod_01_l_00_wi = +{ + ND_ILUT_EX_WI, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_16_pp_01_modrmmod_01_l_00_wi_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_16_pp_01_modrmmod_01_l_00_wi_01_leaf, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_16_pp_01_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_16_pp_01_modrmmod_01_l_00_wi, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_16_pp_01_modrmmod_00_l_00_wi_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3610] // VPEXTRQ Mq,Vdq,Ib +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_16_pp_01_modrmmod_00_l_00_wi_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3606] // VPEXTRD Md,Vdq,Ib +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_16_pp_01_modrmmod_00_l_00_wi = +{ + ND_ILUT_EX_WI, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_16_pp_01_modrmmod_00_l_00_wi_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_16_pp_01_modrmmod_00_l_00_wi_01_leaf, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_16_pp_01_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_16_pp_01_modrmmod_00_l_00_wi, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_03_opcode_16_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_16_pp_01_modrmmod_00_l, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_16_pp_01_modrmmod_01_l, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_16_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_16_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_15_pp_01_modrmmod_01_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3617] // VPEXTRW Ry,Vdq,Ib +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_15_pp_01_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_15_pp_01_modrmmod_01_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_15_pp_01_modrmmod_00_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3616] // VPEXTRW Mw,Vdq,Ib +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_15_pp_01_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_15_pp_01_modrmmod_00_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_03_opcode_15_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_15_pp_01_modrmmod_00_l, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_15_pp_01_modrmmod_01_l, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_15_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_15_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_14_pp_01_modrmmod_01_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3603] // VPEXTRB Ry,Vdq,Ib +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_14_pp_01_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_14_pp_01_modrmmod_01_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_14_pp_01_modrmmod_00_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3602] // VPEXTRB Mb,Vdq,Ib +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_14_pp_01_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_14_pp_01_modrmmod_00_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_03_opcode_14_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_14_pp_01_modrmmod_00_l, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_14_pp_01_modrmmod_01_l, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_14_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_14_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_0f_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3446] // VPALIGNR Vx,Hx,Wx,Ib +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_0f_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_0f_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_0e_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3463] // VPBLENDW Vx,Hx,Wx,Ib +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_0e_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_0e_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_0d_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2723] // VBLENDPD Vx,Hx,Wx,Ib +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_0d_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_0d_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_0c_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2724] // VBLENDPS Vx,Hx,Wx,Ib +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_0c_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_0c_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_0b_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3999] // VROUNDSD Vsd,Hsd,Wsd,Ib +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_0b_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_0b_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_0a_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 4000] // VROUNDSS Vss,Hss,Wss,Ib +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_0a_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_0a_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_09_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3997] // VROUNDPD Vx,Wx,Ib +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_09_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_09_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_08_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3998] // VROUNDPS Vx,Wx,Ib +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_08_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_08_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_06_pp_01_l_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3556] // VPERM2F128 Vqq,Hqq,Wqq,Ib +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_06_pp_01_l_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_06_pp_01_l_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_06_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_06_pp_01_l_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_06_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_06_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_05_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3574] // VPERMILPD Vx,Wx,Ib +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_05_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_05_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_05_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_05_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_04_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3578] // VPERMILPS Vx,Wx,Ib +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_04_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_04_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_04_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_04_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_02_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3457] // VPBLENDD Vx,Hx,Wx,Ib +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_02_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_02_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_02_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_02_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_01_pp_01_l_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3582] // VPERMPD Vqq,Wqq,Ib +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_01_pp_01_l_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_01_pp_01_l_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_01_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_01_pp_01_l_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_01_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_01_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_00_pp_01_l_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3588] // VPERMQ Vqq,Wqq,Ib +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_00_pp_01_l_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_00_pp_01_l_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_00_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_00_pp_01_l_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_00_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_00_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_OPCODE gVexMap_mmmmm_03_opcode = +{ + ND_ILUT_OPCODE, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_00_pp, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_01_pp, + /* 02 */ (const void *)&gVexMap_mmmmm_03_opcode_02_pp, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)&gVexMap_mmmmm_03_opcode_04_pp, + /* 05 */ (const void *)&gVexMap_mmmmm_03_opcode_05_pp, + /* 06 */ (const void *)&gVexMap_mmmmm_03_opcode_06_pp, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)&gVexMap_mmmmm_03_opcode_08_pp, + /* 09 */ (const void *)&gVexMap_mmmmm_03_opcode_09_pp, + /* 0a */ (const void *)&gVexMap_mmmmm_03_opcode_0a_pp, + /* 0b */ (const void *)&gVexMap_mmmmm_03_opcode_0b_pp, + /* 0c */ (const void *)&gVexMap_mmmmm_03_opcode_0c_pp, + /* 0d */ (const void *)&gVexMap_mmmmm_03_opcode_0d_pp, + /* 0e */ (const void *)&gVexMap_mmmmm_03_opcode_0e_pp, + /* 0f */ (const void *)&gVexMap_mmmmm_03_opcode_0f_pp, + /* 10 */ (const void *)ND_NULL, + /* 11 */ (const void *)ND_NULL, + /* 12 */ (const void *)ND_NULL, + /* 13 */ (const void *)ND_NULL, + /* 14 */ (const void *)&gVexMap_mmmmm_03_opcode_14_pp, + /* 15 */ (const void *)&gVexMap_mmmmm_03_opcode_15_pp, + /* 16 */ (const void *)&gVexMap_mmmmm_03_opcode_16_pp, + /* 17 */ (const void *)&gVexMap_mmmmm_03_opcode_17_pp, + /* 18 */ (const void *)&gVexMap_mmmmm_03_opcode_18_pp, + /* 19 */ (const void *)&gVexMap_mmmmm_03_opcode_19_pp, + /* 1a */ (const void *)ND_NULL, + /* 1b */ (const void *)ND_NULL, + /* 1c */ (const void *)ND_NULL, + /* 1d */ (const void *)&gVexMap_mmmmm_03_opcode_1d_pp, + /* 1e */ (const void *)ND_NULL, + /* 1f */ (const void *)ND_NULL, + /* 20 */ (const void *)&gVexMap_mmmmm_03_opcode_20_pp, + /* 21 */ (const void *)&gVexMap_mmmmm_03_opcode_21_pp, + /* 22 */ (const void *)&gVexMap_mmmmm_03_opcode_22_pp, + /* 23 */ (const void *)ND_NULL, + /* 24 */ (const void *)ND_NULL, + /* 25 */ (const void *)ND_NULL, + /* 26 */ (const void *)ND_NULL, + /* 27 */ (const void *)ND_NULL, + /* 28 */ (const void *)ND_NULL, + /* 29 */ (const void *)ND_NULL, + /* 2a */ (const void *)ND_NULL, + /* 2b */ (const void *)ND_NULL, + /* 2c */ (const void *)ND_NULL, + /* 2d */ (const void *)ND_NULL, + /* 2e */ (const void *)ND_NULL, + /* 2f */ (const void *)ND_NULL, + /* 30 */ (const void *)&gVexMap_mmmmm_03_opcode_30_pp, + /* 31 */ (const void *)&gVexMap_mmmmm_03_opcode_31_pp, + /* 32 */ (const void *)&gVexMap_mmmmm_03_opcode_32_pp, + /* 33 */ (const void *)&gVexMap_mmmmm_03_opcode_33_pp, + /* 34 */ (const void *)ND_NULL, + /* 35 */ (const void *)ND_NULL, + /* 36 */ (const void *)ND_NULL, + /* 37 */ (const void *)ND_NULL, + /* 38 */ (const void *)&gVexMap_mmmmm_03_opcode_38_pp, + /* 39 */ (const void *)&gVexMap_mmmmm_03_opcode_39_pp, + /* 3a */ (const void *)ND_NULL, + /* 3b */ (const void *)ND_NULL, + /* 3c */ (const void *)ND_NULL, + /* 3d */ (const void *)ND_NULL, + /* 3e */ (const void *)ND_NULL, + /* 3f */ (const void *)ND_NULL, + /* 40 */ (const void *)&gVexMap_mmmmm_03_opcode_40_pp, + /* 41 */ (const void *)&gVexMap_mmmmm_03_opcode_41_pp, + /* 42 */ (const void *)&gVexMap_mmmmm_03_opcode_42_pp, + /* 43 */ (const void *)ND_NULL, + /* 44 */ (const void *)&gVexMap_mmmmm_03_opcode_44_pp, + /* 45 */ (const void *)ND_NULL, + /* 46 */ (const void *)&gVexMap_mmmmm_03_opcode_46_pp, + /* 47 */ (const void *)ND_NULL, + /* 48 */ (const void *)&gVexMap_mmmmm_03_opcode_48_pp, + /* 49 */ (const void *)&gVexMap_mmmmm_03_opcode_49_pp, + /* 4a */ (const void *)&gVexMap_mmmmm_03_opcode_4a_pp, + /* 4b */ (const void *)&gVexMap_mmmmm_03_opcode_4b_pp, + /* 4c */ (const void *)&gVexMap_mmmmm_03_opcode_4c_pp, + /* 4d */ (const void *)ND_NULL, + /* 4e */ (const void *)ND_NULL, + /* 4f */ (const void *)ND_NULL, + /* 50 */ (const void *)ND_NULL, + /* 51 */ (const void *)ND_NULL, + /* 52 */ (const void *)ND_NULL, + /* 53 */ (const void *)ND_NULL, + /* 54 */ (const void *)ND_NULL, + /* 55 */ (const void *)ND_NULL, + /* 56 */ (const void *)ND_NULL, + /* 57 */ (const void *)ND_NULL, + /* 58 */ (const void *)ND_NULL, + /* 59 */ (const void *)ND_NULL, + /* 5a */ (const void *)ND_NULL, + /* 5b */ (const void *)ND_NULL, + /* 5c */ (const void *)&gVexMap_mmmmm_03_opcode_5c_pp, + /* 5d */ (const void *)&gVexMap_mmmmm_03_opcode_5d_pp, + /* 5e */ (const void *)&gVexMap_mmmmm_03_opcode_5e_pp, + /* 5f */ (const void *)&gVexMap_mmmmm_03_opcode_5f_pp, + /* 60 */ (const void *)&gVexMap_mmmmm_03_opcode_60_pp, + /* 61 */ (const void *)&gVexMap_mmmmm_03_opcode_61_pp, + /* 62 */ (const void *)&gVexMap_mmmmm_03_opcode_62_pp, + /* 63 */ (const void *)&gVexMap_mmmmm_03_opcode_63_pp, + /* 64 */ (const void *)ND_NULL, + /* 65 */ (const void *)ND_NULL, /* 66 */ (const void *)ND_NULL, /* 67 */ (const void *)ND_NULL, /* 68 */ (const void *)&gVexMap_mmmmm_03_opcode_68_pp, @@ -2932,2916 +3619,3345 @@ const ND_TABLE_OPCODE gVexMap_mmmmm_03_opcode = } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_f7_pp_03_l_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_f7_pp_03_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2495] // SHRX Gy,Ey,By +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_f7_pp_03_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_f7_pp_03_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_f7_pp_02_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2283] // SARX Gy,Ey,By +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_f7_pp_02_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_f7_pp_02_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_f7_pp_01_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2433] // SHLX Gy,Ey,By +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_f7_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_f7_pp_01_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_f7_pp_00_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 188] // BEXTR Gy,Ey,By +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_f7_pp_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_f7_pp_00_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_f7_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_f7_pp_00_l, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_f7_pp_01_l, + /* 02 */ (const void *)&gVexMap_mmmmm_02_opcode_f7_pp_02_l, + /* 03 */ (const void *)&gVexMap_mmmmm_02_opcode_f7_pp_03_l, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_f6_pp_03_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1486] // MULX Gy,By,Ey +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_f6_pp_03_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_f6_pp_03_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_f6_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)&gVexMap_mmmmm_02_opcode_f6_pp_03_l, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_f5_pp_03_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1713] // PDEP Gy,By,Ey +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_f5_pp_03_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_f5_pp_03_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_f5_pp_02_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1715] // PEXT Gy,By,Ey +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_f5_pp_02_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_f5_pp_02_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_f5_pp_00_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 239] // BZHI Gy,Ey,By +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_f5_pp_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_f5_pp_00_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_f5_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_f5_pp_00_l, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gVexMap_mmmmm_02_opcode_f5_pp_02_l, + /* 03 */ (const void *)&gVexMap_mmmmm_02_opcode_f5_pp_03_l, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_03_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 202] // BLSI By,Ey +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_03_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_03_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_02_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 206] // BLSMSK By,Ey +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_02_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_02_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_01_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 209] // BLSR By,Ey +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_01_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_REG gVexMap_mmmmm_02_opcode_f3_pp_00_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_01_l, + /* 02 */ (const void *)&gVexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_02_l, + /* 03 */ (const void *)&gVexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_03_l, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_f3_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_f3_pp_00_modrmreg, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_f2_pp_00_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 176] // ANDN Gy,By,Ey +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_f2_pp_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_f2_pp_00_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_f2_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_f2_pp_00_l, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_ef_pp_01_modrmmod_00_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2489] // SHRX Gy,Ey,By + (const void *)&gInstructions[ 638] // CMPNLEXADD My,Gy,By }; -const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_f7_pp_03_l = +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_ef_pp_01_modrmmod_00_l = { ND_ILUT_EX_L, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_f7_pp_03_l_00_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_ef_pp_01_modrmmod_00_l_00_leaf, /* 01 */ (const void *)ND_NULL, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_f7_pp_02_l_00_leaf = +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_ef_pp_01_modrmmod = { - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2277] // SARX Gy,Ey,By + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_ef_pp_01_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } }; -const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_f7_pp_02_l = +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_ef_pp = { - ND_ILUT_EX_L, + ND_ILUT_EX_PP, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_f7_pp_02_l_00_leaf, - /* 01 */ (const void *)ND_NULL, + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_ef_pp_01_modrmmod, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_f7_pp_01_l_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_ee_pp_01_modrmmod_00_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2427] // SHLX Gy,Ey,By + (const void *)&gInstructions[ 630] // CMPLEXADD My,Gy,By }; -const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_f7_pp_01_l = +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_ee_pp_01_modrmmod_00_l = { ND_ILUT_EX_L, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_f7_pp_01_l_00_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_ee_pp_01_modrmmod_00_l_00_leaf, /* 01 */ (const void *)ND_NULL, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_f7_pp_00_l_00_leaf = +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_ee_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_ee_pp_01_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_ee_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_ee_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_ed_pp_01_modrmmod_00_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 188] // BEXTR Gy,Ey,By + (const void *)&gInstructions[ 640] // CMPNLXADD My,Gy,By }; -const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_f7_pp_00_l = +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_ed_pp_01_modrmmod_00_l = { ND_ILUT_EX_L, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_f7_pp_00_l_00_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_ed_pp_01_modrmmod_00_l_00_leaf, /* 01 */ (const void *)ND_NULL, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_f7_pp = +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_ed_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_ed_pp_01_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_ed_pp = { ND_ILUT_EX_PP, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_f7_pp_00_l, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_f7_pp_01_l, - /* 02 */ (const void *)&gVexMap_mmmmm_02_opcode_f7_pp_02_l, - /* 03 */ (const void *)&gVexMap_mmmmm_02_opcode_f7_pp_03_l, + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_ed_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_f6_pp_03_l_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_ec_pp_01_modrmmod_00_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1484] // MULX Gy,By,Ey + (const void *)&gInstructions[ 632] // CMPLXADD My,Gy,By }; -const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_f6_pp_03_l = +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_ec_pp_01_modrmmod_00_l = { ND_ILUT_EX_L, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_f6_pp_03_l_00_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_ec_pp_01_modrmmod_00_l_00_leaf, /* 01 */ (const void *)ND_NULL, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_f6_pp = +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_ec_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_ec_pp_01_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_ec_pp = { ND_ILUT_EX_PP, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_ec_pp_01_modrmmod, /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)&gVexMap_mmmmm_02_opcode_f6_pp_03_l, + /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_f5_pp_03_l_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_eb_pp_01_modrmmod_00_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1711] // PDEP Gy,By,Ey + (const void *)&gInstructions[ 644] // CMPNPXADD My,Gy,By }; -const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_f5_pp_03_l = +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_eb_pp_01_modrmmod_00_l = { ND_ILUT_EX_L, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_f5_pp_03_l_00_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_eb_pp_01_modrmmod_00_l_00_leaf, /* 01 */ (const void *)ND_NULL, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_f5_pp_02_l_00_leaf = +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_eb_pp_01_modrmmod = { - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1713] // PEXT Gy,By,Ey + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_eb_pp_01_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } }; -const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_f5_pp_02_l = +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_eb_pp = { - ND_ILUT_EX_L, + ND_ILUT_EX_PP, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_f5_pp_02_l_00_leaf, - /* 01 */ (const void *)ND_NULL, + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_eb_pp_01_modrmmod, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_f5_pp_00_l_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_ea_pp_01_modrmmod_00_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 239] // BZHI Gy,Ey,By + (const void *)&gInstructions[ 654] // CMPPXADD My,Gy,By }; -const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_f5_pp_00_l = +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_ea_pp_01_modrmmod_00_l = { ND_ILUT_EX_L, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_f5_pp_00_l_00_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_ea_pp_01_modrmmod_00_l_00_leaf, /* 01 */ (const void *)ND_NULL, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_f5_pp = +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_ea_pp_01_modrmmod = { - ND_ILUT_EX_PP, + ND_ILUT_MODRM_MOD, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_f5_pp_00_l, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_ea_pp_01_modrmmod_00_l, /* 01 */ (const void *)ND_NULL, - /* 02 */ (const void *)&gVexMap_mmmmm_02_opcode_f5_pp_02_l, - /* 03 */ (const void *)&gVexMap_mmmmm_02_opcode_f5_pp_03_l, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_03_l_00_leaf = +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_ea_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_ea_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_e9_pp_01_modrmmod_00_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 202] // BLSI By,Ey + (const void *)&gInstructions[ 646] // CMPNSXADD My,Gy,By }; -const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_03_l = +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_e9_pp_01_modrmmod_00_l = { ND_ILUT_EX_L, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_03_l_00_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_e9_pp_01_modrmmod_00_l_00_leaf, /* 01 */ (const void *)ND_NULL, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_02_l_00_leaf = +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_e9_pp_01_modrmmod = { - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 206] // BLSMSK By,Ey + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_e9_pp_01_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } }; -const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_02_l = +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_e9_pp = { - ND_ILUT_EX_L, + ND_ILUT_EX_PP, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_02_l_00_leaf, - /* 01 */ (const void *)ND_NULL, + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_e9_pp_01_modrmmod, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_01_l_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_e8_pp_01_modrmmod_00_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 209] // BLSR By,Ey + (const void *)&gInstructions[ 666] // CMPSXADD My,Gy,By }; -const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_01_l = +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_e8_pp_01_modrmmod_00_l = { ND_ILUT_EX_L, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_01_l_00_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_e8_pp_01_modrmmod_00_l_00_leaf, /* 01 */ (const void *)ND_NULL, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_MODRM_REG gVexMap_mmmmm_02_opcode_f3_pp_00_modrmreg = +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_e8_pp_01_modrmmod = { - ND_ILUT_MODRM_REG, + ND_ILUT_MODRM_MOD, { - /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_01_l, - /* 02 */ (const void *)&gVexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_02_l, - /* 03 */ (const void *)&gVexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_03_l, - /* 04 */ (const void *)ND_NULL, - /* 05 */ (const void *)ND_NULL, - /* 06 */ (const void *)ND_NULL, - /* 07 */ (const void *)ND_NULL, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_e8_pp_01_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_f3_pp = +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_e8_pp = { ND_ILUT_EX_PP, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_f3_pp_00_modrmreg, - /* 01 */ (const void *)ND_NULL, + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_e8_pp_01_modrmmod, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_f2_pp_00_l_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_e7_pp_01_modrmmod_00_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 176] // ANDN Gy,By,Ey + (const void *)&gInstructions[ 634] // CMPNBEXADD My,Gy,By }; -const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_f2_pp_00_l = +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_e7_pp_01_modrmmod_00_l = { ND_ILUT_EX_L, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_f2_pp_00_l_00_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_e7_pp_01_modrmmod_00_l_00_leaf, /* 01 */ (const void *)ND_NULL, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_f2_pp = +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_e7_pp_01_modrmmod = { - ND_ILUT_EX_PP, + ND_ILUT_MODRM_MOD, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_f2_pp_00_l, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_e7_pp_01_modrmmod_00_l, /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_e7_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_e7_pp_01_modrmmod, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_ef_pp_01_modrmmod_00_l_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_e6_pp_01_modrmmod_00_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 638] // CMPNLEXADD My,Gy,By + (const void *)&gInstructions[ 626] // CMPBEXADD My,Gy,By }; -const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_ef_pp_01_modrmmod_00_l = +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_e6_pp_01_modrmmod_00_l = { ND_ILUT_EX_L, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_ef_pp_01_modrmmod_00_l_00_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_e6_pp_01_modrmmod_00_l_00_leaf, /* 01 */ (const void *)ND_NULL, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_ef_pp_01_modrmmod = +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_e6_pp_01_modrmmod = { ND_ILUT_MODRM_MOD, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_ef_pp_01_modrmmod_00_l, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_e6_pp_01_modrmmod_00_l, /* 01 */ (const void *)ND_NULL, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_ef_pp = +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_e6_pp = { ND_ILUT_EX_PP, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_ef_pp_01_modrmmod, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_e6_pp_01_modrmmod, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_ee_pp_01_modrmmod_00_l_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_e5_pp_01_modrmmod_00_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 630] // CMPLEXADD My,Gy,By + (const void *)&gInstructions[ 648] // CMPNZXADD My,Gy,By }; -const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_ee_pp_01_modrmmod_00_l = +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_e5_pp_01_modrmmod_00_l = { ND_ILUT_EX_L, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_ee_pp_01_modrmmod_00_l_00_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_e5_pp_01_modrmmod_00_l_00_leaf, /* 01 */ (const void *)ND_NULL, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_ee_pp_01_modrmmod = +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_e5_pp_01_modrmmod = { ND_ILUT_MODRM_MOD, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_ee_pp_01_modrmmod_00_l, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_e5_pp_01_modrmmod_00_l, /* 01 */ (const void *)ND_NULL, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_ee_pp = +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_e5_pp = { ND_ILUT_EX_PP, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_ee_pp_01_modrmmod, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_e5_pp_01_modrmmod, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_ed_pp_01_modrmmod_00_l_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_e4_pp_01_modrmmod_00_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 640] // CMPNLXADD My,Gy,By + (const void *)&gInstructions[ 672] // CMPZXADD My,Gy,By }; -const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_ed_pp_01_modrmmod_00_l = +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_e4_pp_01_modrmmod_00_l = { ND_ILUT_EX_L, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_ed_pp_01_modrmmod_00_l_00_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_e4_pp_01_modrmmod_00_l_00_leaf, /* 01 */ (const void *)ND_NULL, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_ed_pp_01_modrmmod = +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_e4_pp_01_modrmmod = { ND_ILUT_MODRM_MOD, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_ed_pp_01_modrmmod_00_l, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_e4_pp_01_modrmmod_00_l, /* 01 */ (const void *)ND_NULL, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_ed_pp = +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_e4_pp = { ND_ILUT_EX_PP, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_ed_pp_01_modrmmod, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_e4_pp_01_modrmmod, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_ec_pp_01_modrmmod_00_l_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_e3_pp_01_modrmmod_00_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 632] // CMPLXADD My,Gy,By + (const void *)&gInstructions[ 636] // CMPNCXADD My,Gy,By }; -const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_ec_pp_01_modrmmod_00_l = +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_e3_pp_01_modrmmod_00_l = { ND_ILUT_EX_L, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_ec_pp_01_modrmmod_00_l_00_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_e3_pp_01_modrmmod_00_l_00_leaf, /* 01 */ (const void *)ND_NULL, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_ec_pp_01_modrmmod = +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_e3_pp_01_modrmmod = { ND_ILUT_MODRM_MOD, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_ec_pp_01_modrmmod_00_l, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_e3_pp_01_modrmmod_00_l, /* 01 */ (const void *)ND_NULL, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_ec_pp = +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_e3_pp = { ND_ILUT_EX_PP, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_ec_pp_01_modrmmod, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_e3_pp_01_modrmmod, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_eb_pp_01_modrmmod_00_l_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_e2_pp_01_modrmmod_00_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 644] // CMPNPXADD My,Gy,By + (const void *)&gInstructions[ 628] // CMPCXADD My,Gy,By }; -const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_eb_pp_01_modrmmod_00_l = +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_e2_pp_01_modrmmod_00_l = { ND_ILUT_EX_L, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_eb_pp_01_modrmmod_00_l_00_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_e2_pp_01_modrmmod_00_l_00_leaf, /* 01 */ (const void *)ND_NULL, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_eb_pp_01_modrmmod = +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_e2_pp_01_modrmmod = { ND_ILUT_MODRM_MOD, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_eb_pp_01_modrmmod_00_l, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_e2_pp_01_modrmmod_00_l, /* 01 */ (const void *)ND_NULL, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_eb_pp = +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_e2_pp = { ND_ILUT_EX_PP, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_eb_pp_01_modrmmod, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_e2_pp_01_modrmmod, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_ea_pp_01_modrmmod_00_l_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_e1_pp_01_modrmmod_00_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 654] // CMPPXADD My,Gy,By + (const void *)&gInstructions[ 642] // CMPNOXADD My,Gy,By }; -const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_ea_pp_01_modrmmod_00_l = +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_e1_pp_01_modrmmod_00_l = { ND_ILUT_EX_L, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_ea_pp_01_modrmmod_00_l_00_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_e1_pp_01_modrmmod_00_l_00_leaf, /* 01 */ (const void *)ND_NULL, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_ea_pp_01_modrmmod = +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_e1_pp_01_modrmmod = { ND_ILUT_MODRM_MOD, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_ea_pp_01_modrmmod_00_l, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_e1_pp_01_modrmmod_00_l, /* 01 */ (const void *)ND_NULL, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_ea_pp = +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_e1_pp = { ND_ILUT_EX_PP, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_ea_pp_01_modrmmod, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_e1_pp_01_modrmmod, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_e9_pp_01_modrmmod_00_l_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_e0_pp_01_modrmmod_00_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 646] // CMPNSXADD My,Gy,By + (const void *)&gInstructions[ 650] // CMPOXADD My,Gy,By }; -const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_e9_pp_01_modrmmod_00_l = +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_e0_pp_01_modrmmod_00_l = { ND_ILUT_EX_L, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_e9_pp_01_modrmmod_00_l_00_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_e0_pp_01_modrmmod_00_l_00_leaf, /* 01 */ (const void *)ND_NULL, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_e9_pp_01_modrmmod = +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_e0_pp_01_modrmmod = { ND_ILUT_MODRM_MOD, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_e9_pp_01_modrmmod_00_l, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_e0_pp_01_modrmmod_00_l, /* 01 */ (const void *)ND_NULL, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_e9_pp = +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_e0_pp = { ND_ILUT_EX_PP, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_e9_pp_01_modrmmod, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_e0_pp_01_modrmmod, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_e8_pp_01_modrmmod_00_l_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_df_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 666] // CMPSXADD My,Gy,By + (const void *)&gInstructions[ 2702] // VAESDECLAST Vx,Hx,Wx }; -const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_e8_pp_01_modrmmod_00_l = +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_df_pp = { - ND_ILUT_EX_L, + ND_ILUT_EX_PP, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_e8_pp_01_modrmmod_00_l_00_leaf, - /* 01 */ (const void *)ND_NULL, + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_df_pp_01_leaf, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_e8_pp_01_modrmmod = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_de_pp_01_leaf = { - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_e8_pp_01_modrmmod_00_l, - /* 01 */ (const void *)ND_NULL, - } + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2700] // VAESDEC Vx,Hx,Wx }; -const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_e8_pp = +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_de_pp = { ND_ILUT_EX_PP, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_e8_pp_01_modrmmod, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_de_pp_01_leaf, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_e7_pp_01_modrmmod_00_l_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_dd_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 634] // CMPNBEXADD My,Gy,By + (const void *)&gInstructions[ 2706] // VAESENCLAST Vx,Hx,Wx }; -const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_e7_pp_01_modrmmod_00_l = +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_dd_pp = { - ND_ILUT_EX_L, + ND_ILUT_EX_PP, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_e7_pp_01_modrmmod_00_l_00_leaf, - /* 01 */ (const void *)ND_NULL, + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_dd_pp_01_leaf, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_e7_pp_01_modrmmod = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_dc_pp_01_leaf = { - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_e7_pp_01_modrmmod_00_l, - /* 01 */ (const void *)ND_NULL, - } + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2704] // VAESENC Vx,Hx,Wx }; -const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_e7_pp = +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_dc_pp = { ND_ILUT_EX_PP, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_e7_pp_01_modrmmod, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_dc_pp_01_leaf, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_e6_pp_01_modrmmod_00_l_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_db_pp_01_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 626] // CMPBEXADD My,Gy,By + (const void *)&gInstructions[ 2707] // VAESIMC Vdq,Wdq }; -const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_e6_pp_01_modrmmod_00_l = +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_db_pp_01_l = { ND_ILUT_EX_L, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_e6_pp_01_modrmmod_00_l_00_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_db_pp_01_l_00_leaf, /* 01 */ (const void *)ND_NULL, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_e6_pp_01_modrmmod = +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_db_pp = { - ND_ILUT_MODRM_MOD, + ND_ILUT_EX_PP, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_e6_pp_01_modrmmod_00_l, - /* 01 */ (const void *)ND_NULL, + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_db_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_e6_pp = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_da_pp_03_w_00_leaf = { - ND_ILUT_EX_PP, + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 4050] // VSM4RNDS4 Vx,Hx,Wx +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_da_pp_03_w = +{ + ND_ILUT_EX_W, { - /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_e6_pp_01_modrmmod, - /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)ND_NULL, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_da_pp_03_w_00_leaf, + /* 01 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_e5_pp_01_modrmmod_00_l_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_da_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 648] // CMPNZXADD My,Gy,By + (const void *)&gInstructions[ 4048] // VSM4KEY4 Vx,Hx,Wx }; -const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_e5_pp_01_modrmmod_00_l = +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_da_pp_02_w = { - ND_ILUT_EX_L, + ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_e5_pp_01_modrmmod_00_l_00_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_da_pp_02_w_00_leaf, /* 01 */ (const void *)ND_NULL, - /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_e5_pp_01_modrmmod = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_da_pp_01_l_00_w_00_leaf = { - ND_ILUT_MODRM_MOD, + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 4045] // VSM3MSG2 Vdq,Hdq,Wdq +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_da_pp_01_l_00_w = +{ + ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_e5_pp_01_modrmmod_00_l, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_da_pp_01_l_00_w_00_leaf, /* 01 */ (const void *)ND_NULL, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_e5_pp = +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_da_pp_01_l = { - ND_ILUT_EX_PP, + ND_ILUT_EX_L, { - /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_e5_pp_01_modrmmod, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_da_pp_01_l_00_w, + /* 01 */ (const void *)ND_NULL, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_e4_pp_01_modrmmod_00_l_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_da_pp_00_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 672] // CMPZXADD My,Gy,By + (const void *)&gInstructions[ 4044] // VSM3MSG1 Vdq,Hdq,Wdq }; -const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_e4_pp_01_modrmmod_00_l = +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_da_pp_00_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_da_pp_00_l_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_da_pp_00_l = { ND_ILUT_EX_L, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_e4_pp_01_modrmmod_00_l_00_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_da_pp_00_l_00_w, /* 01 */ (const void *)ND_NULL, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_e4_pp_01_modrmmod = +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_da_pp = { - ND_ILUT_MODRM_MOD, + ND_ILUT_EX_PP, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_e4_pp_01_modrmmod_00_l, - /* 01 */ (const void *)ND_NULL, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_da_pp_00_l, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_da_pp_01_l, + /* 02 */ (const void *)&gVexMap_mmmmm_02_opcode_da_pp_02_w, + /* 03 */ (const void *)&gVexMap_mmmmm_02_opcode_da_pp_03_w, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_e4_pp = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_d3_pp_02_w_00_leaf = { - ND_ILUT_EX_PP, + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3547] // VPDPWSUDS Vx,Hx,Wx +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_d3_pp_02_w = +{ + ND_ILUT_EX_W, { - /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_e4_pp_01_modrmmod, - /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)ND_NULL, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_d3_pp_02_w_00_leaf, + /* 01 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_e3_pp_01_modrmmod_00_l_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_d3_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 636] // CMPNCXADD My,Gy,By + (const void *)&gInstructions[ 3551] // VPDPWUSDS Vx,Hx,Wx }; -const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_e3_pp_01_modrmmod_00_l = +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_d3_pp_01_w = { - ND_ILUT_EX_L, + ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_e3_pp_01_modrmmod_00_l_00_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_d3_pp_01_w_00_leaf, /* 01 */ (const void *)ND_NULL, - /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_e3_pp_01_modrmmod = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_d3_pp_00_w_00_leaf = { - ND_ILUT_MODRM_MOD, + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3555] // VPDPWUUDS Vx,Hx,Wx +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_d3_pp_00_w = +{ + ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_e3_pp_01_modrmmod_00_l, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_d3_pp_00_w_00_leaf, /* 01 */ (const void *)ND_NULL, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_e3_pp = +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_d3_pp = { ND_ILUT_EX_PP, { - /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_e3_pp_01_modrmmod, - /* 02 */ (const void *)ND_NULL, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_d3_pp_00_w, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_d3_pp_01_w, + /* 02 */ (const void *)&gVexMap_mmmmm_02_opcode_d3_pp_02_w, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_e2_pp_01_modrmmod_00_l_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_d2_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 628] // CMPCXADD My,Gy,By + (const void *)&gInstructions[ 3545] // VPDPWSUD Vx,Hx,Wx }; -const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_e2_pp_01_modrmmod_00_l = +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_d2_pp_02_w = { - ND_ILUT_EX_L, + ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_e2_pp_01_modrmmod_00_l_00_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_d2_pp_02_w_00_leaf, /* 01 */ (const void *)ND_NULL, - /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_e2_pp_01_modrmmod = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_d2_pp_01_w_00_leaf = { - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_e2_pp_01_modrmmod_00_l, - /* 01 */ (const void *)ND_NULL, - } + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3549] // VPDPWUSD Vx,Hx,Wx }; -const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_e2_pp = +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_d2_pp_01_w = { - ND_ILUT_EX_PP, + ND_ILUT_EX_W, { - /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_e2_pp_01_modrmmod, - /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)ND_NULL, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_d2_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_e1_pp_01_modrmmod_00_l_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_d2_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 642] // CMPNOXADD My,Gy,By + (const void *)&gInstructions[ 3553] // VPDPWUUD Vx,Hx,Wx }; -const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_e1_pp_01_modrmmod_00_l = +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_d2_pp_00_w = { - ND_ILUT_EX_L, + ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_e1_pp_01_modrmmod_00_l_00_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_d2_pp_00_w_00_leaf, /* 01 */ (const void *)ND_NULL, - /* 02 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_d2_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_d2_pp_00_w, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_d2_pp_01_w, + /* 02 */ (const void *)&gVexMap_mmmmm_02_opcode_d2_pp_02_w, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_e1_pp_01_modrmmod = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_cf_pp_01_w_00_leaf = { - ND_ILUT_MODRM_MOD, + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3205] // VGF2P8MULB Vx,Hx,Wx +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_cf_pp_01_w = +{ + ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_e1_pp_01_modrmmod_00_l, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_cf_pp_01_w_00_leaf, /* 01 */ (const void *)ND_NULL, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_e1_pp = +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_cf_pp = { ND_ILUT_EX_PP, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_e1_pp_01_modrmmod, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_cf_pp_01_w, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_e0_pp_01_modrmmod_00_l_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_cd_pp_03_modrmmod_01_l_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 650] // CMPOXADD My,Gy,By -}; - -const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_e0_pp_01_modrmmod_00_l = -{ - ND_ILUT_EX_L, - { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_e0_pp_01_modrmmod_00_l_00_leaf, - /* 01 */ (const void *)ND_NULL, - /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)ND_NULL, - } + (const void *)&gInstructions[ 4034] // VSHA512MSG2 Vqq,Uqq }; -const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_e0_pp_01_modrmmod = +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_cd_pp_03_modrmmod_01_l_01_w = { - ND_ILUT_MODRM_MOD, + ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_e0_pp_01_modrmmod_00_l, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_cd_pp_03_modrmmod_01_l_01_w_00_leaf, /* 01 */ (const void *)ND_NULL, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_e0_pp = +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_cd_pp_03_modrmmod_01_l = { - ND_ILUT_EX_PP, + ND_ILUT_EX_L, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_e0_pp_01_modrmmod, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_cd_pp_03_modrmmod_01_l_01_w, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_df_pp_01_leaf = +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_cd_pp_03_modrmmod = { - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2661] // VAESDECLAST Vx,Hx,Wx + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_cd_pp_03_modrmmod_01_l, + } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_df_pp = +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_cd_pp = { ND_ILUT_EX_PP, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_df_pp_01_leaf, + /* 01 */ (const void *)ND_NULL, /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)ND_NULL, + /* 03 */ (const void *)&gVexMap_mmmmm_02_opcode_cd_pp_03_modrmmod, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_de_pp_01_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_cc_pp_03_modrmmod_01_l_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2659] // VAESDEC Vx,Hx,Wx + (const void *)&gInstructions[ 4033] // VSHA512MSG1 Vqq,Udq }; -const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_de_pp = +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_cc_pp_03_modrmmod_01_l_01_w = { - ND_ILUT_EX_PP, + ND_ILUT_EX_W, { - /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_de_pp_01_leaf, - /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)ND_NULL, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_cc_pp_03_modrmmod_01_l_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_dd_pp_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2665] // VAESENCLAST Vx,Hx,Wx -}; - -const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_dd_pp = +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_cc_pp_03_modrmmod_01_l = { - ND_ILUT_EX_PP, + ND_ILUT_EX_L, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_dd_pp_01_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_cc_pp_03_modrmmod_01_l_01_w, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_dc_pp_01_leaf = +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_cc_pp_03_modrmmod = { - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2663] // VAESENC Vx,Hx,Wx + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_cc_pp_03_modrmmod_01_l, + } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_dc_pp = +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_cc_pp = { ND_ILUT_EX_PP, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_dc_pp_01_leaf, + /* 01 */ (const void *)ND_NULL, /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)ND_NULL, + /* 03 */ (const void *)&gVexMap_mmmmm_02_opcode_cc_pp_03_modrmmod, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_db_pp_01_l_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_cb_pp_03_modrmmod_01_l_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2666] // VAESIMC Vdq,Wdq + (const void *)&gInstructions[ 4035] // VSHA512RNDS2 Vqq,Hqq,Udq }; -const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_db_pp_01_l = +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_cb_pp_03_modrmmod_01_l_01_w = { - ND_ILUT_EX_L, + ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_db_pp_01_l_00_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_cb_pp_03_modrmmod_01_l_01_w_00_leaf, /* 01 */ (const void *)ND_NULL, - /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_db_pp = +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_cb_pp_03_modrmmod_01_l = { - ND_ILUT_EX_PP, + ND_ILUT_EX_L, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_db_pp_01_l, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_cb_pp_03_modrmmod_01_l_01_w, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_da_pp_03_w_00_leaf = +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_cb_pp_03_modrmmod = { - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4003] // VSM4RNDS4 Vx,Hx,Wx + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_cb_pp_03_modrmmod_01_l, + } }; -const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_da_pp_03_w = +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_cb_pp = { - ND_ILUT_EX_W, + ND_ILUT_EX_PP, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_da_pp_03_w_00_leaf, + /* 00 */ (const void *)ND_NULL, /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)&gVexMap_mmmmm_02_opcode_cb_pp_03_modrmmod, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_da_pp_02_w_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_bf_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4002] // VSM4KEY4 Vx,Hx,Wx -}; - -const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_da_pp_02_w = -{ - ND_ILUT_EX_W, - { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_da_pp_02_w_00_leaf, - /* 01 */ (const void *)ND_NULL, - } + (const void *)&gInstructions[ 3147] // VFNMSUB231SD Vdq,Hdq,Wsd }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_da_pp_01_l_00_w_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_bf_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4000] // VSM3MSG2 Vdq,Hdq,Wdq + (const void *)&gInstructions[ 3150] // VFNMSUB231SS Vdq,Hdq,Wss }; -const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_da_pp_01_l_00_w = +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_bf_pp_01_w = { ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_da_pp_01_l_00_w_00_leaf, - /* 01 */ (const void *)ND_NULL, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_bf_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_bf_pp_01_w_01_leaf, } }; -const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_da_pp_01_l = +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_bf_pp = { - ND_ILUT_EX_L, + ND_ILUT_EX_PP, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_da_pp_01_l_00_w, - /* 01 */ (const void *)ND_NULL, + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_bf_pp_01_w, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_da_pp_00_l_00_w_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_be_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3999] // VSM3MSG1 Vdq,Hdq,Wdq + (const void *)&gInstructions[ 3142] // VFNMSUB231PD Vx,Hx,Wx }; -const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_da_pp_00_l_00_w = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_be_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3145] // VFNMSUB231PS Vx,Hx,Wx +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_be_pp_01_w = { ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_da_pp_00_l_00_w_00_leaf, - /* 01 */ (const void *)ND_NULL, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_be_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_be_pp_01_w_01_leaf, } }; -const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_da_pp_00_l = +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_be_pp = { - ND_ILUT_EX_L, + ND_ILUT_EX_PP, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_da_pp_00_l_00_w, - /* 01 */ (const void *)ND_NULL, + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_be_pp_01_w, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_da_pp = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_bd_pp_01_w_01_leaf = { - ND_ILUT_EX_PP, - { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_da_pp_00_l, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_da_pp_01_l, - /* 02 */ (const void *)&gVexMap_mmmmm_02_opcode_da_pp_02_w, - /* 03 */ (const void *)&gVexMap_mmmmm_02_opcode_da_pp_03_w, - } + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3106] // VFNMADD231SD Vdq,Hdq,Wsd }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_d3_pp_02_w_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_bd_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3502] // VPDPWSUDS Vx,Hx,Wx + (const void *)&gInstructions[ 3109] // VFNMADD231SS Vdq,Hdq,Wss }; -const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_d3_pp_02_w = +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_bd_pp_01_w = { ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_d3_pp_02_w_00_leaf, - /* 01 */ (const void *)ND_NULL, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_bd_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_bd_pp_01_w_01_leaf, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_d3_pp_01_w_00_leaf = +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_bd_pp = { - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3506] // VPDPWUSDS Vx,Hx,Wx + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_bd_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } }; -const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_d3_pp_01_w = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_bc_pp_01_w_01_leaf = { - ND_ILUT_EX_W, - { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_d3_pp_01_w_00_leaf, - /* 01 */ (const void *)ND_NULL, - } + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3101] // VFNMADD231PD Vx,Hx,Wx }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_d3_pp_00_w_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_bc_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3510] // VPDPWUUDS Vx,Hx,Wx + (const void *)&gInstructions[ 3104] // VFNMADD231PS Vx,Hx,Wx }; -const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_d3_pp_00_w = +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_bc_pp_01_w = { ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_d3_pp_00_w_00_leaf, - /* 01 */ (const void *)ND_NULL, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_bc_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_bc_pp_01_w_01_leaf, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_d3_pp = +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_bc_pp = { ND_ILUT_EX_PP, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_d3_pp_00_w, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_d3_pp_01_w, - /* 02 */ (const void *)&gVexMap_mmmmm_02_opcode_d3_pp_02_w, + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_bc_pp_01_w, + /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_d2_pp_02_w_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_bb_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3500] // VPDPWSUD Vx,Hx,Wx + (const void *)&gInstructions[ 3044] // VFMSUB231SD Vdq,Hdq,Wsd }; -const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_d2_pp_02_w = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_bb_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3047] // VFMSUB231SS Vdq,Hdq,Wss +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_bb_pp_01_w = { ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_d2_pp_02_w_00_leaf, - /* 01 */ (const void *)ND_NULL, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_bb_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_bb_pp_01_w_01_leaf, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_d2_pp_01_w_00_leaf = +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_bb_pp = { - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3504] // VPDPWUSD Vx,Hx,Wx + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_bb_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } }; -const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_d2_pp_01_w = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_ba_pp_01_w_01_leaf = { - ND_ILUT_EX_W, - { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_d2_pp_01_w_00_leaf, - /* 01 */ (const void *)ND_NULL, - } + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3039] // VFMSUB231PD Vx,Hx,Wx }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_d2_pp_00_w_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_ba_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3508] // VPDPWUUD Vx,Hx,Wx + (const void *)&gInstructions[ 3042] // VFMSUB231PS Vx,Hx,Wx }; -const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_d2_pp_00_w = +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_ba_pp_01_w = { ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_d2_pp_00_w_00_leaf, - /* 01 */ (const void *)ND_NULL, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_ba_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_ba_pp_01_w_01_leaf, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_d2_pp = +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_ba_pp = { ND_ILUT_EX_PP, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_d2_pp_00_w, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_d2_pp_01_w, - /* 02 */ (const void *)&gVexMap_mmmmm_02_opcode_d2_pp_02_w, + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_ba_pp_01_w, + /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_cf_pp_01_w_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_b9_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3164] // VGF2P8MULB Vx,Hx,Wx + (const void *)&gInstructions[ 2982] // VFMADD231SD Vdq,Hdq,Wsd }; -const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_cf_pp_01_w = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_b9_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2985] // VFMADD231SS Vdq,Hdq,Wss +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_b9_pp_01_w = { ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_cf_pp_01_w_00_leaf, - /* 01 */ (const void *)ND_NULL, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_b9_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_b9_pp_01_w_01_leaf, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_cf_pp = +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_b9_pp = { ND_ILUT_EX_PP, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_cf_pp_01_w, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_b9_pp_01_w, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_cd_pp_03_modrmmod_01_l_01_w_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_b8_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3989] // VSHA512MSG2 Vqq,Uqq + (const void *)&gInstructions[ 2977] // VFMADD231PD Vx,Hx,Wx }; -const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_cd_pp_03_modrmmod_01_l_01_w = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_b8_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2980] // VFMADD231PS Vx,Hx,Wx +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_b8_pp_01_w = { ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_cd_pp_03_modrmmod_01_l_01_w_00_leaf, - /* 01 */ (const void *)ND_NULL, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_b8_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_b8_pp_01_w_01_leaf, } }; -const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_cd_pp_03_modrmmod_01_l = +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_b8_pp = { - ND_ILUT_EX_L, + ND_ILUT_EX_PP, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_cd_pp_03_modrmmod_01_l_01_w, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_b8_pp_01_w, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_cd_pp_03_modrmmod = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_b7_pp_01_w_01_leaf = { - ND_ILUT_MODRM_MOD, + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3059] // VFMSUBADD231PD Vx,Hx,Wx +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_b7_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3062] // VFMSUBADD231PS Vx,Hx,Wx +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_b7_pp_01_w = +{ + ND_ILUT_EX_W, { - /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_cd_pp_03_modrmmod_01_l, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_b7_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_b7_pp_01_w_01_leaf, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_cd_pp = +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_b7_pp = { ND_ILUT_EX_PP, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_b7_pp_01_w, /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)&gVexMap_mmmmm_02_opcode_cd_pp_03_modrmmod, + /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_cc_pp_03_modrmmod_01_l_01_w_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_b6_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3988] // VSHA512MSG1 Vqq,Udq + (const void *)&gInstructions[ 3007] // VFMADDSUB231PD Vx,Hx,Wx }; -const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_cc_pp_03_modrmmod_01_l_01_w = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_b6_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3010] // VFMADDSUB231PS Vx,Hx,Wx +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_b6_pp_01_w = { ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_cc_pp_03_modrmmod_01_l_01_w_00_leaf, - /* 01 */ (const void *)ND_NULL, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_b6_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_b6_pp_01_w_01_leaf, } }; -const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_cc_pp_03_modrmmod_01_l = +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_b6_pp = { - ND_ILUT_EX_L, + ND_ILUT_EX_PP, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_cc_pp_03_modrmmod_01_l_01_w, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_b6_pp_01_w, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_cc_pp_03_modrmmod = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_b5_pp_01_w_01_leaf = { - ND_ILUT_MODRM_MOD, + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3675] // VPMADD52HUQ Vx,Hx,Wx +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_b5_pp_01_w = +{ + ND_ILUT_EX_W, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_cc_pp_03_modrmmod_01_l, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_b5_pp_01_w_01_leaf, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_cc_pp = +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_b5_pp = { ND_ILUT_EX_PP, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_b5_pp_01_w, /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)&gVexMap_mmmmm_02_opcode_cc_pp_03_modrmmod, + /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_cb_pp_03_modrmmod_01_l_01_w_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_b4_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3990] // VSHA512RNDS2 Vqq,Hqq,Udq + (const void *)&gInstructions[ 3677] // VPMADD52LUQ Vx,Hx,Wx }; -const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_cb_pp_03_modrmmod_01_l_01_w = +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_b4_pp_01_w = { ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_cb_pp_03_modrmmod_01_l_01_w_00_leaf, - /* 01 */ (const void *)ND_NULL, + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_b4_pp_01_w_01_leaf, } }; -const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_cb_pp_03_modrmmod_01_l = +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_b4_pp = { - ND_ILUT_EX_L, + ND_ILUT_EX_PP, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_cb_pp_03_modrmmod_01_l_01_w, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_b4_pp_01_w, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_cb_pp_03_modrmmod = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_b1_pp_02_modrmmod_00_w_00_leaf = { - ND_ILUT_MODRM_MOD, + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2719] // VBCSTNEBF162PS Vx,Mw +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_b1_pp_02_modrmmod_00_w = +{ + ND_ILUT_EX_W, { - /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_cb_pp_03_modrmmod_01_l, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_b1_pp_02_modrmmod_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_cb_pp = +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_b1_pp_02_modrmmod = { - ND_ILUT_EX_PP, + ND_ILUT_MODRM_MOD, { - /* 00 */ (const void *)ND_NULL, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_b1_pp_02_modrmmod_00_w, /* 01 */ (const void *)ND_NULL, - /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)&gVexMap_mmmmm_02_opcode_cb_pp_03_modrmmod, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_bf_pp_01_w_01_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_b1_pp_01_modrmmod_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3106] // VFNMSUB231SD Vdq,Hdq,Wsd + (const void *)&gInstructions[ 2720] // VBCSTNESH2PS Vx,Mw }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_bf_pp_01_w_00_leaf = +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_b1_pp_01_modrmmod_00_w = { - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3109] // VFNMSUB231SS Vdq,Hdq,Wss + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_b1_pp_01_modrmmod_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } }; -const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_bf_pp_01_w = +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_b1_pp_01_modrmmod = { - ND_ILUT_EX_W, + ND_ILUT_MODRM_MOD, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_bf_pp_01_w_00_leaf, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_bf_pp_01_w_01_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_b1_pp_01_modrmmod_00_w, + /* 01 */ (const void *)ND_NULL, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_bf_pp = +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_b1_pp = { ND_ILUT_EX_PP, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_bf_pp_01_w, - /* 02 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_b1_pp_01_modrmmod, + /* 02 */ (const void *)&gVexMap_mmmmm_02_opcode_b1_pp_02_modrmmod, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_be_pp_01_w_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3101] // VFNMSUB231PD Vx,Hx,Wx -}; - -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_be_pp_01_w_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_b0_pp_03_modrmmod_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3104] // VFNMSUB231PS Vx,Hx,Wx + (const void *)&gInstructions[ 2786] // VCVTNEOBF162PS Vx,Mx }; -const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_be_pp_01_w = +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_b0_pp_03_modrmmod_00_w = { ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_be_pp_01_w_00_leaf, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_be_pp_01_w_01_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_b0_pp_03_modrmmod_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_be_pp = +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_b0_pp_03_modrmmod = { - ND_ILUT_EX_PP, + ND_ILUT_MODRM_MOD, { - /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_be_pp_01_w, - /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)ND_NULL, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_b0_pp_03_modrmmod_00_w, + /* 01 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_bd_pp_01_w_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3065] // VFNMADD231SD Vdq,Hdq,Wsd -}; - -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_bd_pp_01_w_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_b0_pp_02_modrmmod_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3068] // VFNMADD231SS Vdq,Hdq,Wss + (const void *)&gInstructions[ 2784] // VCVTNEEBF162PS Vx,Mx }; -const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_bd_pp_01_w = +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_b0_pp_02_modrmmod_00_w = { ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_bd_pp_01_w_00_leaf, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_bd_pp_01_w_01_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_b0_pp_02_modrmmod_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_bd_pp = +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_b0_pp_02_modrmmod = { - ND_ILUT_EX_PP, + ND_ILUT_MODRM_MOD, { - /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_bd_pp_01_w, - /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)ND_NULL, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_b0_pp_02_modrmmod_00_w, + /* 01 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_bc_pp_01_w_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3060] // VFNMADD231PD Vx,Hx,Wx -}; - -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_bc_pp_01_w_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_b0_pp_01_modrmmod_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3063] // VFNMADD231PS Vx,Hx,Wx + (const void *)&gInstructions[ 2785] // VCVTNEEPH2PS Vx,Mx }; -const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_bc_pp_01_w = +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_b0_pp_01_modrmmod_00_w = { ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_bc_pp_01_w_00_leaf, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_bc_pp_01_w_01_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_b0_pp_01_modrmmod_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_bc_pp = +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_b0_pp_01_modrmmod = { - ND_ILUT_EX_PP, + ND_ILUT_MODRM_MOD, { - /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_bc_pp_01_w, - /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)ND_NULL, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_b0_pp_01_modrmmod_00_w, + /* 01 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_bb_pp_01_w_01_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_b0_pp_00_modrmmod_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3003] // VFMSUB231SD Vdq,Hdq,Wsd + (const void *)&gInstructions[ 2787] // VCVTNEOPH2PS Vx,Mx }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_bb_pp_01_w_00_leaf = +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_b0_pp_00_modrmmod_00_w = { - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3006] // VFMSUB231SS Vdq,Hdq,Wss + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_b0_pp_00_modrmmod_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } }; -const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_bb_pp_01_w = +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_b0_pp_00_modrmmod = { - ND_ILUT_EX_W, + ND_ILUT_MODRM_MOD, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_bb_pp_01_w_00_leaf, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_bb_pp_01_w_01_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_b0_pp_00_modrmmod_00_w, + /* 01 */ (const void *)ND_NULL, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_bb_pp = +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_b0_pp = { ND_ILUT_EX_PP, { - /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_bb_pp_01_w, - /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)ND_NULL, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_b0_pp_00_modrmmod, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_b0_pp_01_modrmmod, + /* 02 */ (const void *)&gVexMap_mmmmm_02_opcode_b0_pp_02_modrmmod, + /* 03 */ (const void *)&gVexMap_mmmmm_02_opcode_b0_pp_03_modrmmod, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_ba_pp_01_w_01_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_af_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2998] // VFMSUB231PD Vx,Hx,Wx + (const void *)&gInstructions[ 3136] // VFNMSUB213SD Vdq,Hdq,Wsd }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_ba_pp_01_w_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_af_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3001] // VFMSUB231PS Vx,Hx,Wx + (const void *)&gInstructions[ 3139] // VFNMSUB213SS Vdq,Hdq,Wss }; -const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_ba_pp_01_w = +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_af_pp_01_w = { ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_ba_pp_01_w_00_leaf, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_ba_pp_01_w_01_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_af_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_af_pp_01_w_01_leaf, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_ba_pp = +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_af_pp = { ND_ILUT_EX_PP, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_ba_pp_01_w, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_af_pp_01_w, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_b9_pp_01_w_01_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_ae_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2941] // VFMADD231SD Vdq,Hdq,Wsd + (const void *)&gInstructions[ 3131] // VFNMSUB213PD Vx,Hx,Wx }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_b9_pp_01_w_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_ae_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2944] // VFMADD231SS Vdq,Hdq,Wss + (const void *)&gInstructions[ 3134] // VFNMSUB213PS Vx,Hx,Wx }; -const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_b9_pp_01_w = +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_ae_pp_01_w = { ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_b9_pp_01_w_00_leaf, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_b9_pp_01_w_01_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_ae_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_ae_pp_01_w_01_leaf, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_b9_pp = +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_ae_pp = { ND_ILUT_EX_PP, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_b9_pp_01_w, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_ae_pp_01_w, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_b8_pp_01_w_01_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_ad_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2936] // VFMADD231PD Vx,Hx,Wx + (const void *)&gInstructions[ 3095] // VFNMADD213SD Vdq,Hdq,Wsd }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_b8_pp_01_w_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_ad_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2939] // VFMADD231PS Vx,Hx,Wx + (const void *)&gInstructions[ 3098] // VFNMADD213SS Vdq,Hdq,Wss }; -const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_b8_pp_01_w = +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_ad_pp_01_w = { ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_b8_pp_01_w_00_leaf, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_b8_pp_01_w_01_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_ad_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_ad_pp_01_w_01_leaf, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_b8_pp = +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_ad_pp = { ND_ILUT_EX_PP, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_b8_pp_01_w, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_ad_pp_01_w, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_b7_pp_01_w_01_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_ac_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3018] // VFMSUBADD231PD Vx,Hx,Wx + (const void *)&gInstructions[ 3090] // VFNMADD213PD Vx,Hx,Wx }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_b7_pp_01_w_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_ac_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3021] // VFMSUBADD231PS Vx,Hx,Wx + (const void *)&gInstructions[ 3093] // VFNMADD213PS Vx,Hx,Wx }; -const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_b7_pp_01_w = +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_ac_pp_01_w = { ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_b7_pp_01_w_00_leaf, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_b7_pp_01_w_01_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_ac_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_ac_pp_01_w_01_leaf, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_b7_pp = +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_ac_pp = { ND_ILUT_EX_PP, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_b7_pp_01_w, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_ac_pp_01_w, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_b6_pp_01_w_01_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_ab_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2966] // VFMADDSUB231PD Vx,Hx,Wx + (const void *)&gInstructions[ 3033] // VFMSUB213SD Vdq,Hdq,Wsd }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_b6_pp_01_w_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_ab_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2969] // VFMADDSUB231PS Vx,Hx,Wx + (const void *)&gInstructions[ 3036] // VFMSUB213SS Vdq,Hdq,Wss }; -const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_b6_pp_01_w = +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_ab_pp_01_w = { ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_b6_pp_01_w_00_leaf, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_b6_pp_01_w_01_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_ab_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_ab_pp_01_w_01_leaf, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_b6_pp = +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_ab_pp = { ND_ILUT_EX_PP, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_b6_pp_01_w, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_ab_pp_01_w, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_b5_pp_01_w_01_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_aa_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3630] // VPMADD52HUQ Vx,Hx,Wx -}; - -const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_b5_pp_01_w = -{ - ND_ILUT_EX_W, - { - /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_b5_pp_01_w_01_leaf, - } -}; - -const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_b5_pp = -{ - ND_ILUT_EX_PP, - { - /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_b5_pp_01_w, - /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)ND_NULL, - } + (const void *)&gInstructions[ 3028] // VFMSUB213PD Vx,Hx,Wx }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_b4_pp_01_w_01_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_aa_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3632] // VPMADD52LUQ Vx,Hx,Wx + (const void *)&gInstructions[ 3031] // VFMSUB213PS Vx,Hx,Wx }; -const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_b4_pp_01_w = +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_aa_pp_01_w = { ND_ILUT_EX_W, { - /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_b4_pp_01_w_01_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_aa_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_aa_pp_01_w_01_leaf, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_b4_pp = +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_aa_pp = { ND_ILUT_EX_PP, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_b4_pp_01_w, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_aa_pp_01_w, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_b1_pp_02_modrmmod_00_w_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_a9_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2678] // VBCSTNEBF162PS Vx,Mw -}; - -const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_b1_pp_02_modrmmod_00_w = -{ - ND_ILUT_EX_W, - { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_b1_pp_02_modrmmod_00_w_00_leaf, - /* 01 */ (const void *)ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_b1_pp_02_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_b1_pp_02_modrmmod_00_w, - /* 01 */ (const void *)ND_NULL, - } + (const void *)&gInstructions[ 2971] // VFMADD213SD Vdq,Hdq,Wsd }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_b1_pp_01_modrmmod_00_w_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_a9_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2679] // VBCSTNESH2PS Vx,Mw + (const void *)&gInstructions[ 2974] // VFMADD213SS Vdq,Hdq,Wss }; -const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_b1_pp_01_modrmmod_00_w = +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_a9_pp_01_w = { ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_b1_pp_01_modrmmod_00_w_00_leaf, - /* 01 */ (const void *)ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_b1_pp_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_b1_pp_01_modrmmod_00_w, - /* 01 */ (const void *)ND_NULL, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_a9_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_a9_pp_01_w_01_leaf, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_b1_pp = +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_a9_pp = { ND_ILUT_EX_PP, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_b1_pp_01_modrmmod, - /* 02 */ (const void *)&gVexMap_mmmmm_02_opcode_b1_pp_02_modrmmod, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_a9_pp_01_w, + /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_b0_pp_03_modrmmod_00_w_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_a8_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2745] // VCVTNEOBF162PS Vx,Mx -}; - -const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_b0_pp_03_modrmmod_00_w = -{ - ND_ILUT_EX_W, - { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_b0_pp_03_modrmmod_00_w_00_leaf, - /* 01 */ (const void *)ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_b0_pp_03_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_b0_pp_03_modrmmod_00_w, - /* 01 */ (const void *)ND_NULL, - } + (const void *)&gInstructions[ 2966] // VFMADD213PD Vx,Hx,Wx }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_b0_pp_02_modrmmod_00_w_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_a8_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2743] // VCVTNEEBF162PS Vx,Mx + (const void *)&gInstructions[ 2969] // VFMADD213PS Vx,Hx,Wx }; -const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_b0_pp_02_modrmmod_00_w = +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_a8_pp_01_w = { ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_b0_pp_02_modrmmod_00_w_00_leaf, - /* 01 */ (const void *)ND_NULL, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_a8_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_a8_pp_01_w_01_leaf, } }; -const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_b0_pp_02_modrmmod = +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_a8_pp = { - ND_ILUT_MODRM_MOD, + ND_ILUT_EX_PP, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_b0_pp_02_modrmmod_00_w, - /* 01 */ (const void *)ND_NULL, + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_a8_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_b0_pp_01_modrmmod_00_w_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_a7_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3054] // VFMSUBADD213PD Vx,Hx,Wx +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_a7_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2744] // VCVTNEEPH2PS Vx,Mx + (const void *)&gInstructions[ 3057] // VFMSUBADD213PS Vx,Hx,Wx }; -const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_b0_pp_01_modrmmod_00_w = +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_a7_pp_01_w = { ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_b0_pp_01_modrmmod_00_w_00_leaf, - /* 01 */ (const void *)ND_NULL, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_a7_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_a7_pp_01_w_01_leaf, } }; -const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_b0_pp_01_modrmmod = +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_a7_pp = { - ND_ILUT_MODRM_MOD, + ND_ILUT_EX_PP, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_b0_pp_01_modrmmod_00_w, - /* 01 */ (const void *)ND_NULL, + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_a7_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_b0_pp_00_modrmmod_00_w_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_a6_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2746] // VCVTNEOPH2PS Vx,Mx + (const void *)&gInstructions[ 3002] // VFMADDSUB213PD Vx,Hx,Wx }; -const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_b0_pp_00_modrmmod_00_w = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_a6_pp_01_w_00_leaf = { - ND_ILUT_EX_W, - { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_b0_pp_00_modrmmod_00_w_00_leaf, - /* 01 */ (const void *)ND_NULL, - } + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3005] // VFMADDSUB213PS Vx,Hx,Wx }; -const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_b0_pp_00_modrmmod = +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_a6_pp_01_w = { - ND_ILUT_MODRM_MOD, + ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_b0_pp_00_modrmmod_00_w, - /* 01 */ (const void *)ND_NULL, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_a6_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_a6_pp_01_w_01_leaf, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_b0_pp = +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_a6_pp = { ND_ILUT_EX_PP, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_b0_pp_00_modrmmod, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_b0_pp_01_modrmmod, - /* 02 */ (const void *)&gVexMap_mmmmm_02_opcode_b0_pp_02_modrmmod, - /* 03 */ (const void *)&gVexMap_mmmmm_02_opcode_b0_pp_03_modrmmod, + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_a6_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_af_pp_01_w_01_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_9f_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3095] // VFNMSUB213SD Vdq,Hdq,Wsd + (const void *)&gInstructions[ 3125] // VFNMSUB132SD Vdq,Hdq,Wsd }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_af_pp_01_w_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_9f_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3098] // VFNMSUB213SS Vdq,Hdq,Wss + (const void *)&gInstructions[ 3128] // VFNMSUB132SS Vdq,Hdq,Wss }; -const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_af_pp_01_w = +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_9f_pp_01_w = { ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_af_pp_01_w_00_leaf, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_af_pp_01_w_01_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_9f_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_9f_pp_01_w_01_leaf, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_af_pp = +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_9f_pp = { ND_ILUT_EX_PP, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_af_pp_01_w, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_9f_pp_01_w, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_ae_pp_01_w_01_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_9e_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3090] // VFNMSUB213PD Vx,Hx,Wx + (const void *)&gInstructions[ 3120] // VFNMSUB132PD Vx,Hx,Wx }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_ae_pp_01_w_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_9e_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3093] // VFNMSUB213PS Vx,Hx,Wx + (const void *)&gInstructions[ 3123] // VFNMSUB132PS Vx,Hx,Wx }; -const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_ae_pp_01_w = +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_9e_pp_01_w = { ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_ae_pp_01_w_00_leaf, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_ae_pp_01_w_01_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_9e_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_9e_pp_01_w_01_leaf, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_ae_pp = +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_9e_pp = { ND_ILUT_EX_PP, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_ae_pp_01_w, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_9e_pp_01_w, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_ad_pp_01_w_01_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_9d_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3054] // VFNMADD213SD Vdq,Hdq,Wsd + (const void *)&gInstructions[ 3084] // VFNMADD132SD Vdq,Hdq,Wsd }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_ad_pp_01_w_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_9d_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3057] // VFNMADD213SS Vdq,Hdq,Wss + (const void *)&gInstructions[ 3087] // VFNMADD132SS Vdq,Hdq,Wss }; -const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_ad_pp_01_w = +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_9d_pp_01_w = { ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_ad_pp_01_w_00_leaf, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_ad_pp_01_w_01_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_9d_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_9d_pp_01_w_01_leaf, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_ad_pp = +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_9d_pp = { ND_ILUT_EX_PP, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_ad_pp_01_w, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_9d_pp_01_w, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_ac_pp_01_w_01_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_9c_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3049] // VFNMADD213PD Vx,Hx,Wx + (const void *)&gInstructions[ 3079] // VFNMADD132PD Vx,Hx,Wx }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_ac_pp_01_w_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_9c_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3052] // VFNMADD213PS Vx,Hx,Wx + (const void *)&gInstructions[ 3082] // VFNMADD132PS Vx,Hx,Wx }; -const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_ac_pp_01_w = +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_9c_pp_01_w = { ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_ac_pp_01_w_00_leaf, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_ac_pp_01_w_01_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_9c_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_9c_pp_01_w_01_leaf, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_ac_pp = +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_9c_pp = { ND_ILUT_EX_PP, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_ac_pp_01_w, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_9c_pp_01_w, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_ab_pp_01_w_01_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_9b_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2992] // VFMSUB213SD Vdq,Hdq,Wsd + (const void *)&gInstructions[ 3022] // VFMSUB132SD Vdq,Hdq,Wsd }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_ab_pp_01_w_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_9b_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2995] // VFMSUB213SS Vdq,Hdq,Wss + (const void *)&gInstructions[ 3025] // VFMSUB132SS Vdq,Hdq,Wss }; -const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_ab_pp_01_w = +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_9b_pp_01_w = { ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_ab_pp_01_w_00_leaf, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_ab_pp_01_w_01_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_9b_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_9b_pp_01_w_01_leaf, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_ab_pp = +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_9b_pp = { ND_ILUT_EX_PP, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_ab_pp_01_w, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_9b_pp_01_w, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_aa_pp_01_w_01_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_9a_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2987] // VFMSUB213PD Vx,Hx,Wx + (const void *)&gInstructions[ 3017] // VFMSUB132PD Vx,Hx,Wx }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_aa_pp_01_w_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_9a_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2990] // VFMSUB213PS Vx,Hx,Wx + (const void *)&gInstructions[ 3020] // VFMSUB132PS Vx,Hx,Wx }; -const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_aa_pp_01_w = +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_9a_pp_01_w = { ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_aa_pp_01_w_00_leaf, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_aa_pp_01_w_01_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_9a_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_9a_pp_01_w_01_leaf, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_aa_pp = +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_9a_pp = { ND_ILUT_EX_PP, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_aa_pp_01_w, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_9a_pp_01_w, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_a9_pp_01_w_01_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_99_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2930] // VFMADD213SD Vdq,Hdq,Wsd + (const void *)&gInstructions[ 2960] // VFMADD132SD Vdq,Hdq,Wsd }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_a9_pp_01_w_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_99_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2933] // VFMADD213SS Vdq,Hdq,Wss + (const void *)&gInstructions[ 2963] // VFMADD132SS Vdq,Hdq,Wss }; -const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_a9_pp_01_w = +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_99_pp_01_w = { ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_a9_pp_01_w_00_leaf, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_a9_pp_01_w_01_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_99_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_99_pp_01_w_01_leaf, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_a9_pp = +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_99_pp = { ND_ILUT_EX_PP, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_a9_pp_01_w, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_99_pp_01_w, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_a8_pp_01_w_01_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_98_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2925] // VFMADD213PD Vx,Hx,Wx + (const void *)&gInstructions[ 2955] // VFMADD132PD Vx,Hx,Wx }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_a8_pp_01_w_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_98_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2928] // VFMADD213PS Vx,Hx,Wx + (const void *)&gInstructions[ 2958] // VFMADD132PS Vx,Hx,Wx }; -const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_a8_pp_01_w = +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_98_pp_01_w = { ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_a8_pp_01_w_00_leaf, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_a8_pp_01_w_01_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_98_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_98_pp_01_w_01_leaf, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_a8_pp = +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_98_pp = { ND_ILUT_EX_PP, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_a8_pp_01_w, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_98_pp_01_w, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_a7_pp_01_w_01_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_97_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3013] // VFMSUBADD213PD Vx,Hx,Wx + (const void *)&gInstructions[ 3049] // VFMSUBADD132PD Vx,Hx,Wx }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_a7_pp_01_w_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_97_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3016] // VFMSUBADD213PS Vx,Hx,Wx + (const void *)&gInstructions[ 3052] // VFMSUBADD132PS Vx,Hx,Wx }; -const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_a7_pp_01_w = +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_97_pp_01_w = { ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_a7_pp_01_w_00_leaf, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_a7_pp_01_w_01_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_97_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_97_pp_01_w_01_leaf, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_a7_pp = +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_97_pp = { ND_ILUT_EX_PP, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_a7_pp_01_w, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_97_pp_01_w, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_a6_pp_01_w_01_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_96_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2961] // VFMADDSUB213PD Vx,Hx,Wx + (const void *)&gInstructions[ 2997] // VFMADDSUB132PD Vx,Hx,Wx }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_a6_pp_01_w_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_96_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2964] // VFMADDSUB213PS Vx,Hx,Wx + (const void *)&gInstructions[ 3000] // VFMADDSUB132PS Vx,Hx,Wx }; -const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_a6_pp_01_w = +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_96_pp_01_w = { ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_a6_pp_01_w_00_leaf, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_a6_pp_01_w_01_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_96_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_96_pp_01_w_01_leaf, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_a6_pp = +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_96_pp = { ND_ILUT_EX_PP, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_a6_pp_01_w, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_96_pp_01_w, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_9f_pp_01_w_01_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_93_pp_01_modrmmod_00_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3084] // VFNMSUB132SD Vdq,Hdq,Wsd + (const void *)&gInstructions[ 3183] // VGATHERQPD Vx,Mvm64n,Hx }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_9f_pp_01_w_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_93_pp_01_modrmmod_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3087] // VFNMSUB132SS Vdq,Hdq,Wss + (const void *)&gInstructions[ 3185] // VGATHERQPS Vdq,Mvm64n,Hdq }; -const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_9f_pp_01_w = +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_93_pp_01_modrmmod_00_w = { ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_9f_pp_01_w_00_leaf, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_9f_pp_01_w_01_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_93_pp_01_modrmmod_00_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_93_pp_01_modrmmod_00_w_01_leaf, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_9f_pp = +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_93_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_93_pp_01_modrmmod_00_w, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_93_pp = { ND_ILUT_EX_PP, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_9f_pp_01_w, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_93_pp_01_modrmmod, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_9e_pp_01_w_01_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_92_pp_01_modrmmod_00_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3079] // VFNMSUB132PD Vx,Hx,Wx + (const void *)&gInstructions[ 3171] // VGATHERDPD Vx,Mvm32h,Hx }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_9e_pp_01_w_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_92_pp_01_modrmmod_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3082] // VFNMSUB132PS Vx,Hx,Wx + (const void *)&gInstructions[ 3173] // VGATHERDPS Vx,Mvm32n,Hx }; -const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_9e_pp_01_w = +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_92_pp_01_modrmmod_00_w = { ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_9e_pp_01_w_00_leaf, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_9e_pp_01_w_01_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_92_pp_01_modrmmod_00_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_92_pp_01_modrmmod_00_w_01_leaf, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_9e_pp = +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_92_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_92_pp_01_modrmmod_00_w, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_92_pp = { ND_ILUT_EX_PP, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_9e_pp_01_w, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_92_pp_01_modrmmod, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_9d_pp_01_w_01_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_91_pp_01_modrmmod_00_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3043] // VFNMADD132SD Vdq,Hdq,Wsd + (const void *)&gInstructions[ 3625] // VPGATHERQQ Vx,Mvm64n,Hx }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_9d_pp_01_w_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_91_pp_01_modrmmod_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3046] // VFNMADD132SS Vdq,Hdq,Wss + (const void *)&gInstructions[ 3623] // VPGATHERQD Vdq,Mvm64n,Hdq }; -const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_9d_pp_01_w = +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_91_pp_01_modrmmod_00_w = { ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_9d_pp_01_w_00_leaf, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_9d_pp_01_w_01_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_91_pp_01_modrmmod_00_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_91_pp_01_modrmmod_00_w_01_leaf, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_9d_pp = +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_91_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_91_pp_01_modrmmod_00_w, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_91_pp = { ND_ILUT_EX_PP, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_9d_pp_01_w, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_91_pp_01_modrmmod, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_9c_pp_01_w_01_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_90_pp_01_modrmmod_00_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3038] // VFNMADD132PD Vx,Hx,Wx + (const void *)&gInstructions[ 3621] // VPGATHERDQ Vx,Mvm32h,Hx }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_9c_pp_01_w_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_90_pp_01_modrmmod_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3041] // VFNMADD132PS Vx,Hx,Wx + (const void *)&gInstructions[ 3619] // VPGATHERDD Vx,Mvm32n,Hx }; -const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_9c_pp_01_w = +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_90_pp_01_modrmmod_00_w = { ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_9c_pp_01_w_00_leaf, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_9c_pp_01_w_01_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_90_pp_01_modrmmod_00_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_90_pp_01_modrmmod_00_w_01_leaf, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_9c_pp = +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_90_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_90_pp_01_modrmmod_00_w, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_90_pp = { ND_ILUT_EX_PP, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_9c_pp_01_w, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_90_pp_01_modrmmod, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_9b_pp_01_w_01_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_8e_pp_01_modrmmod_00_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2981] // VFMSUB132SD Vdq,Hdq,Wsd + (const void *)&gInstructions[ 3685] // VPMASKMOVQ Mx,Hx,Vx }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_9b_pp_01_w_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_8e_pp_01_modrmmod_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2984] // VFMSUB132SS Vdq,Hdq,Wss + (const void *)&gInstructions[ 3683] // VPMASKMOVD Mx,Hx,Vx }; -const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_9b_pp_01_w = +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_8e_pp_01_modrmmod_00_w = { ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_9b_pp_01_w_00_leaf, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_9b_pp_01_w_01_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_8e_pp_01_modrmmod_00_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_8e_pp_01_modrmmod_00_w_01_leaf, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_9b_pp = +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_8e_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_8e_pp_01_modrmmod_00_w, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_8e_pp = { ND_ILUT_EX_PP, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_9b_pp_01_w, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_8e_pp_01_modrmmod, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_9a_pp_01_w_01_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_8c_pp_01_modrmmod_00_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2976] // VFMSUB132PD Vx,Hx,Wx + (const void *)&gInstructions[ 3684] // VPMASKMOVQ Vx,Hx,Mx }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_9a_pp_01_w_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_8c_pp_01_modrmmod_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2979] // VFMSUB132PS Vx,Hx,Wx + (const void *)&gInstructions[ 3682] // VPMASKMOVD Vx,Hx,Mx }; -const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_9a_pp_01_w = +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_8c_pp_01_modrmmod_00_w = { ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_9a_pp_01_w_00_leaf, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_9a_pp_01_w_01_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_8c_pp_01_modrmmod_00_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_8c_pp_01_modrmmod_00_w_01_leaf, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_9a_pp = +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_8c_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_8c_pp_01_modrmmod_00_w, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_8c_pp = { ND_ILUT_EX_PP, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_9a_pp_01_w, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_8c_pp_01_modrmmod, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_99_pp_01_w_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2919] // VFMADD132SD Vdq,Hdq,Wsd -}; - -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_99_pp_01_w_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_79_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2922] // VFMADD132SS Vdq,Hdq,Wss + (const void *)&gInstructions[ 3477] // VPBROADCASTW Vx,Ww }; -const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_99_pp_01_w = +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_79_pp_01_w = { ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_99_pp_01_w_00_leaf, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_99_pp_01_w_01_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_79_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_99_pp = +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_79_pp = { ND_ILUT_EX_PP, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_99_pp_01_w, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_79_pp_01_w, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_98_pp_01_w_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2914] // VFMADD132PD Vx,Hx,Wx -}; - -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_98_pp_01_w_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_78_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2917] // VFMADD132PS Vx,Hx,Wx + (const void *)&gInstructions[ 3466] // VPBROADCASTB Vx,Wb }; -const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_98_pp_01_w = +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_78_pp_01_w = { ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_98_pp_01_w_00_leaf, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_98_pp_01_w_01_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_78_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_98_pp = +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_78_pp = { ND_ILUT_EX_PP, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_98_pp_01_w, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_78_pp_01_w, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_97_pp_01_w_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3008] // VFMSUBADD132PD Vx,Hx,Wx -}; - -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_97_pp_01_w_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_72_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3011] // VFMSUBADD132PS Vx,Hx,Wx + (const void *)&gInstructions[ 2793] // VCVTNEPS2BF16 Vx,Wx }; -const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_97_pp_01_w = +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_72_pp_02_w = { ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_97_pp_01_w_00_leaf, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_97_pp_01_w_01_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_72_pp_02_w_00_leaf, + /* 01 */ (const void *)ND_NULL, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_97_pp = +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_72_pp = { ND_ILUT_EX_PP, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_97_pp_01_w, - /* 02 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gVexMap_mmmmm_02_opcode_72_pp_02_w, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_96_pp_01_w_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2956] // VFMADDSUB132PD Vx,Hx,Wx -}; - -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_96_pp_01_w_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_6f_pp_01_modrmmod_00_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2959] // VFMADDSUB132PS Vx,Hx,Wx + (const void *)&gInstructions[ 2600] // T2RPNTLVWZ1T1 rTt+1,Mt }; -const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_96_pp_01_w = +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_6f_pp_01_modrmmod_00_l_00_w = { ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_96_pp_01_w_00_leaf, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_96_pp_01_w_01_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_6f_pp_01_modrmmod_00_l_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_96_pp = +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_6f_pp_01_modrmmod_00_l = { - ND_ILUT_EX_PP, + ND_ILUT_EX_L, { - /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_96_pp_01_w, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_6f_pp_01_modrmmod_00_l_00_w, + /* 01 */ (const void *)ND_NULL, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_93_pp_01_modrmmod_00_w_01_leaf = +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_6f_pp_01_modrmmod = { - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3142] // VGATHERQPD Vx,Mvm64n,Hx + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_6f_pp_01_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_93_pp_01_modrmmod_00_w_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_6f_pp_00_modrmmod_00_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3144] // VGATHERQPS Vdq,Mvm64n,Hdq + (const void *)&gInstructions[ 2596] // T2RPNTLVWZ0T1 rTt+1,Mt }; -const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_93_pp_01_modrmmod_00_w = +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_6f_pp_00_modrmmod_00_l_00_w = { ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_93_pp_01_modrmmod_00_w_00_leaf, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_93_pp_01_modrmmod_00_w_01_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_6f_pp_00_modrmmod_00_l_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, } }; -const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_93_pp_01_modrmmod = +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_6f_pp_00_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_6f_pp_00_modrmmod_00_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_6f_pp_00_modrmmod = { ND_ILUT_MODRM_MOD, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_93_pp_01_modrmmod_00_w, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_6f_pp_00_modrmmod_00_l, /* 01 */ (const void *)ND_NULL, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_93_pp = +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_6f_pp = { ND_ILUT_EX_PP, { - /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_93_pp_01_modrmmod, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_6f_pp_00_modrmmod, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_6f_pp_01_modrmmod, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_92_pp_01_modrmmod_00_w_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3130] // VGATHERDPD Vx,Mvm32h,Hx -}; - -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_92_pp_01_modrmmod_00_w_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_6e_pp_01_modrmmod_00_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3132] // VGATHERDPS Vx,Mvm32n,Hx + (const void *)&gInstructions[ 2597] // T2RPNTLVWZ1 rTt+1,Mt }; -const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_92_pp_01_modrmmod_00_w = +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_6e_pp_01_modrmmod_00_l_00_w = { ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_92_pp_01_modrmmod_00_w_00_leaf, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_92_pp_01_modrmmod_00_w_01_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_6e_pp_01_modrmmod_00_l_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, } }; -const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_92_pp_01_modrmmod = +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_6e_pp_01_modrmmod_00_l = { - ND_ILUT_MODRM_MOD, + ND_ILUT_EX_L, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_92_pp_01_modrmmod_00_w, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_6e_pp_01_modrmmod_00_l_00_w, /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_92_pp = +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_6e_pp_01_modrmmod = { - ND_ILUT_EX_PP, + ND_ILUT_MODRM_MOD, { - /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_92_pp_01_modrmmod, - /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)ND_NULL, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_6e_pp_01_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_91_pp_01_modrmmod_00_w_01_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_6e_pp_00_modrmmod_00_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3580] // VPGATHERQQ Vx,Mvm64n,Hx + (const void *)&gInstructions[ 2593] // T2RPNTLVWZ0 rTt+1,Mt }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_91_pp_01_modrmmod_00_w_00_leaf = +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_6e_pp_00_modrmmod_00_l_00_w = { - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3578] // VPGATHERQD Vdq,Mvm64n,Hdq + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_6e_pp_00_modrmmod_00_l_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } }; -const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_91_pp_01_modrmmod_00_w = +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_6e_pp_00_modrmmod_00_l = { - ND_ILUT_EX_W, + ND_ILUT_EX_L, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_91_pp_01_modrmmod_00_w_00_leaf, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_91_pp_01_modrmmod_00_w_01_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_6e_pp_00_modrmmod_00_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_91_pp_01_modrmmod = +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_6e_pp_00_modrmmod = { ND_ILUT_MODRM_MOD, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_91_pp_01_modrmmod_00_w, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_6e_pp_00_modrmmod_00_l, /* 01 */ (const void *)ND_NULL, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_91_pp = +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_6e_pp = { ND_ILUT_EX_PP, { - /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_91_pp_01_modrmmod, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_6e_pp_00_modrmmod, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_6e_pp_01_modrmmod, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_90_pp_01_modrmmod_00_w_01_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_6c_pp_03_modrmmod_01_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3576] // VPGATHERDQ Vx,Mvm32h,Hx + (const void *)&gInstructions[ 2653] // TTDPFP16PS rTt,mTt,vTt }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_90_pp_01_modrmmod_00_w_00_leaf = +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_6c_pp_03_modrmmod_01_l_00_w = { - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3574] // VPGATHERDD Vx,Mvm32n,Hx + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_6c_pp_03_modrmmod_01_l_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } }; -const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_90_pp_01_modrmmod_00_w = +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_6c_pp_03_modrmmod_01_l = { - ND_ILUT_EX_W, + ND_ILUT_EX_L, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_90_pp_01_modrmmod_00_w_00_leaf, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_90_pp_01_modrmmod_00_w_01_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_6c_pp_03_modrmmod_01_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_90_pp_01_modrmmod = +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_6c_pp_03_modrmmod = { ND_ILUT_MODRM_MOD, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_90_pp_01_modrmmod_00_w, + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_6c_pp_03_modrmmod_01_l, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_6c_pp_02_modrmmod_01_l_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2652] // TTDPBF16PS rTt,mTt,vTt +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_6c_pp_02_modrmmod_01_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_6c_pp_02_modrmmod_01_l_00_w_00_leaf, /* 01 */ (const void *)ND_NULL, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_90_pp = +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_6c_pp_02_modrmmod_01_l = { - ND_ILUT_EX_PP, + ND_ILUT_EX_L, { - /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_90_pp_01_modrmmod, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_6c_pp_02_modrmmod_01_l_00_w, + /* 01 */ (const void *)ND_NULL, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_8e_pp_01_modrmmod_00_w_01_leaf = +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_6c_pp_02_modrmmod = { - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3640] // VPMASKMOVQ Mx,Hx,Vx + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_6c_pp_02_modrmmod_01_l, + } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_8e_pp_01_modrmmod_00_w_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_6c_pp_01_modrmmod_01_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3638] // VPMASKMOVD Mx,Hx,Vx + (const void *)&gInstructions[ 2601] // TCMMIMFP16PS rTt,mTt,vTt }; -const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_8e_pp_01_modrmmod_00_w = +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_6c_pp_01_modrmmod_01_l_00_w = { ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_8e_pp_01_modrmmod_00_w_00_leaf, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_8e_pp_01_modrmmod_00_w_01_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_6c_pp_01_modrmmod_01_l_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, } }; -const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_8e_pp_01_modrmmod = +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_6c_pp_01_modrmmod_01_l = { - ND_ILUT_MODRM_MOD, + ND_ILUT_EX_L, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_8e_pp_01_modrmmod_00_w, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_6c_pp_01_modrmmod_01_l_00_w, /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_8e_pp = +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_6c_pp_01_modrmmod = { - ND_ILUT_EX_PP, + ND_ILUT_MODRM_MOD, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_8e_pp_01_modrmmod, - /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_6c_pp_01_modrmmod_01_l, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_8c_pp_01_modrmmod_00_w_01_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_6c_pp_00_modrmmod_01_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3639] // VPMASKMOVQ Vx,Hx,Mx + (const void *)&gInstructions[ 2602] // TCMMRLFP16PS rTt,mTt,vTt }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_8c_pp_01_modrmmod_00_w_00_leaf = +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_6c_pp_00_modrmmod_01_l_00_w = { - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3637] // VPMASKMOVD Vx,Hx,Mx + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_6c_pp_00_modrmmod_01_l_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } }; -const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_8c_pp_01_modrmmod_00_w = +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_6c_pp_00_modrmmod_01_l = { - ND_ILUT_EX_W, + ND_ILUT_EX_L, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_8c_pp_01_modrmmod_00_w_00_leaf, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_8c_pp_01_modrmmod_00_w_01_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_6c_pp_00_modrmmod_01_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_8c_pp_01_modrmmod = +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_6c_pp_00_modrmmod = { ND_ILUT_MODRM_MOD, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_8c_pp_01_modrmmod_00_w, - /* 01 */ (const void *)ND_NULL, + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_6c_pp_00_modrmmod_01_l, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_8c_pp = +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_6c_pp = { ND_ILUT_EX_PP, { - /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_8c_pp_01_modrmmod, - /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)ND_NULL, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_6c_pp_00_modrmmod, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_6c_pp_01_modrmmod, + /* 02 */ (const void *)&gVexMap_mmmmm_02_opcode_6c_pp_02_modrmmod, + /* 03 */ (const void *)&gVexMap_mmmmm_02_opcode_6c_pp_03_modrmmod, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_79_pp_01_w_00_leaf = +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_6b_pp_03_modrmmod_01_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3432] // VPBROADCASTW Vx,Ww + (const void *)&gInstructions[ 2650] // TTCMMIMFP16PS rTt,mTt,vTt }; -const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_79_pp_01_w = +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_6b_pp_03_modrmmod_01_l_00_w = { ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_79_pp_01_w_00_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_6b_pp_03_modrmmod_01_l_00_w_00_leaf, /* 01 */ (const void *)ND_NULL, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_79_pp = +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_6b_pp_03_modrmmod_01_l = { - ND_ILUT_EX_PP, + ND_ILUT_EX_L, { - /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_79_pp_01_w, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_6b_pp_03_modrmmod_01_l_00_w, + /* 01 */ (const void *)ND_NULL, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_78_pp_01_w_00_leaf = +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_6b_pp_03_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_6b_pp_03_modrmmod_01_l, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_6b_pp_02_modrmmod_01_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3421] // VPBROADCASTB Vx,Wb + (const void *)&gInstructions[ 2651] // TTCMMRLFP16PS rTt,mTt,vTt }; -const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_78_pp_01_w = +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_6b_pp_02_modrmmod_01_l_00_w = { ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_78_pp_01_w_00_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_6b_pp_02_modrmmod_01_l_00_w_00_leaf, /* 01 */ (const void *)ND_NULL, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_78_pp = +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_6b_pp_02_modrmmod_01_l = { - ND_ILUT_EX_PP, + ND_ILUT_EX_L, { - /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_78_pp_01_w, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_6b_pp_02_modrmmod_01_l_00_w, + /* 01 */ (const void *)ND_NULL, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_72_pp_02_w_00_leaf = +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_6b_pp_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_6b_pp_02_modrmmod_01_l, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_6b_pp_01_modrmmod_01_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2752] // VCVTNEPS2BF16 Vx,Wx + (const void *)&gInstructions[ 2604] // TCONJTFP16 rTt,mTt }; -const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_72_pp_02_w = +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_6b_pp_01_modrmmod_01_l_00_w = { ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_72_pp_02_w_00_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_6b_pp_01_modrmmod_01_l_00_w_00_leaf, /* 01 */ (const void *)ND_NULL, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_72_pp = +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_6b_pp_01_modrmmod_01_l = { - ND_ILUT_EX_PP, + ND_ILUT_EX_L, { - /* 00 */ (const void *)ND_NULL, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_6b_pp_01_modrmmod_01_l_00_w, /* 01 */ (const void *)ND_NULL, - /* 02 */ (const void *)&gVexMap_mmmmm_02_opcode_72_pp_02_w, + /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_6c_pp_01_modrmmod_01_l_00_w_00_leaf = +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_6b_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_6b_pp_01_modrmmod_01_l, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_6b_pp_00_modrmmod_01_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2587] // TCMMIMFP16PS rTt,mTt,vTt + (const void *)&gInstructions[ 2603] // TCONJTCMMIMFP16PS rTt,mTt,vTt }; -const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_6c_pp_01_modrmmod_01_l_00_w = +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_6b_pp_00_modrmmod_01_l_00_w = { ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_6c_pp_01_modrmmod_01_l_00_w_00_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_6b_pp_00_modrmmod_01_l_00_w_00_leaf, /* 01 */ (const void *)ND_NULL, } }; -const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_6c_pp_01_modrmmod_01_l = +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_6b_pp_00_modrmmod_01_l = { ND_ILUT_EX_L, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_6c_pp_01_modrmmod_01_l_00_w, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_6b_pp_00_modrmmod_01_l_00_w, /* 01 */ (const void *)ND_NULL, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_6c_pp_01_modrmmod = +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_6b_pp_00_modrmmod = { ND_ILUT_MODRM_MOD, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_6c_pp_01_modrmmod_01_l, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_6b_pp_00_modrmmod_01_l, } }; -const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_6c_pp_00_modrmmod_01_l_00_w_00_leaf = +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_6b_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_6b_pp_00_modrmmod, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_6b_pp_01_modrmmod, + /* 02 */ (const void *)&gVexMap_mmmmm_02_opcode_6b_pp_02_modrmmod, + /* 03 */ (const void *)&gVexMap_mmmmm_02_opcode_6b_pp_03_modrmmod, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_5f_pp_02_modrmmod_01_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2588] // TCMMRLFP16PS rTt,mTt,vTt + (const void *)&gInstructions[ 2655] // TTRANSPOSED rTt,mTt }; -const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_6c_pp_00_modrmmod_01_l_00_w = +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_5f_pp_02_modrmmod_01_l_00_w = { ND_ILUT_EX_W, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_6c_pp_00_modrmmod_01_l_00_w_00_leaf, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_5f_pp_02_modrmmod_01_l_00_w_00_leaf, /* 01 */ (const void *)ND_NULL, } }; -const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_6c_pp_00_modrmmod_01_l = +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_5f_pp_02_modrmmod_01_l = { ND_ILUT_EX_L, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_6c_pp_00_modrmmod_01_l_00_w, + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_5f_pp_02_modrmmod_01_l_00_w, /* 01 */ (const void *)ND_NULL, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } }; -const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_6c_pp_00_modrmmod = +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_5f_pp_02_modrmmod = { ND_ILUT_MODRM_MOD, { /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_6c_pp_00_modrmmod_01_l, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_5f_pp_02_modrmmod_01_l, } }; -const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_6c_pp = +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_5f_pp = { ND_ILUT_EX_PP, { - /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_6c_pp_00_modrmmod, - /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_6c_pp_01_modrmmod, - /* 02 */ (const void *)ND_NULL, + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gVexMap_mmmmm_02_opcode_5f_pp_02_modrmmod, /* 03 */ (const void *)ND_NULL, } }; @@ -5849,7 +6965,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_6c_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_5e_pp_03_modrmmod_01_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2591] // TDPBSSD rTt,mTt,vTt + (const void *)&gInstructions[ 2619] // TDPBSSD rTt,mTt,vTt }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_5e_pp_03_modrmmod_01_l_00_w = @@ -5884,7 +7000,7 @@ const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_5e_pp_03_modrmmod = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_5e_pp_02_modrmmod_01_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2592] // TDPBSUD rTt,mTt,vTt + (const void *)&gInstructions[ 2620] // TDPBSUD rTt,mTt,vTt }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_5e_pp_02_modrmmod_01_l_00_w = @@ -5919,7 +7035,7 @@ const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_5e_pp_02_modrmmod = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_5e_pp_01_modrmmod_01_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2593] // TDPBUSD rTt,mTt,vTt + (const void *)&gInstructions[ 2621] // TDPBUSD rTt,mTt,vTt }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_5e_pp_01_modrmmod_01_l_00_w = @@ -5954,7 +7070,7 @@ const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_5e_pp_01_modrmmod = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_5e_pp_00_modrmmod_01_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2594] // TDPBUUD rTt,mTt,vTt + (const void *)&gInstructions[ 2622] // TDPBUUD rTt,mTt,vTt }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_5e_pp_00_modrmmod_01_l_00_w = @@ -6000,7 +7116,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_5e_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_5c_pp_03_modrmmod_01_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2595] // TDPFP16PS rTt,mTt,vTt + (const void *)&gInstructions[ 2623] // TDPFP16PS rTt,mTt,vTt }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_5c_pp_03_modrmmod_01_l_00_w = @@ -6035,7 +7151,7 @@ const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_5c_pp_03_modrmmod = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_5c_pp_02_modrmmod_01_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2590] // TDPBF16PS rTt,mTt,vTt + (const void *)&gInstructions[ 2616] // TDPBF16PS rTt,mTt,vTt }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_5c_pp_02_modrmmod_01_l_00_w = @@ -6081,7 +7197,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_5c_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_5a_pp_01_modrmmod_00_l_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2692] // VBROADCASTI128 Vqq,Mdq + (const void *)&gInstructions[ 2733] // VBROADCASTI128 Vqq,Mdq }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_5a_pp_01_modrmmod_00_l_01_w = @@ -6127,7 +7243,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_5a_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_59_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3429] // VPBROADCASTQ Vx,Wq + (const void *)&gInstructions[ 3474] // VPBROADCASTQ Vx,Wq }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_59_pp_01_w = @@ -6153,7 +7269,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_59_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_58_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3424] // VPBROADCASTD Vx,Wd + (const void *)&gInstructions[ 3469] // VPBROADCASTD Vx,Wd }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_58_pp_01_w = @@ -6179,7 +7295,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_58_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_53_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3498] // VPDPWSSDS Vx,Hx,Wx + (const void *)&gInstructions[ 3543] // VPDPWSSDS Vx,Hx,Wx }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_53_pp_01_w = @@ -6205,7 +7321,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_53_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_52_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3496] // VPDPWSSD Vx,Hx,Wx + (const void *)&gInstructions[ 3541] // VPDPWSSD Vx,Hx,Wx }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_52_pp_01_w = @@ -6231,7 +7347,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_52_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_51_pp_03_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3482] // VPDPBSSDS Vx,Hx,Wx + (const void *)&gInstructions[ 3527] // VPDPBSSDS Vx,Hx,Wx }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_51_pp_03_w = @@ -6246,7 +7362,7 @@ const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_51_pp_03_w = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_51_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3486] // VPDPBSUDS Vx,Hx,Wx + (const void *)&gInstructions[ 3531] // VPDPBSUDS Vx,Hx,Wx }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_51_pp_02_w = @@ -6261,7 +7377,7 @@ const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_51_pp_02_w = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_51_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3490] // VPDPBUSDS Vx,Hx,Wx + (const void *)&gInstructions[ 3535] // VPDPBUSDS Vx,Hx,Wx }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_51_pp_01_w = @@ -6276,7 +7392,7 @@ const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_51_pp_01_w = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_51_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3494] // VPDPBUUDS Vx,Hx,Wx + (const void *)&gInstructions[ 3539] // VPDPBUUDS Vx,Hx,Wx }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_51_pp_00_w = @@ -6302,7 +7418,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_51_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_50_pp_03_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3480] // VPDPBSSD Vx,Hx,Wx + (const void *)&gInstructions[ 3525] // VPDPBSSD Vx,Hx,Wx }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_50_pp_03_w = @@ -6317,7 +7433,7 @@ const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_50_pp_03_w = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_50_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3484] // VPDPBSUD Vx,Hx,Wx + (const void *)&gInstructions[ 3529] // VPDPBSUD Vx,Hx,Wx }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_50_pp_02_w = @@ -6332,7 +7448,7 @@ const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_50_pp_02_w = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_50_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3488] // VPDPBUSD Vx,Hx,Wx + (const void *)&gInstructions[ 3533] // VPDPBUSD Vx,Hx,Wx }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_50_pp_01_w = @@ -6347,7 +7463,7 @@ const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_50_pp_01_w = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_50_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3492] // VPDPBUUD Vx,Hx,Wx + (const void *)&gInstructions[ 3537] // VPDPBUUD Vx,Hx,Wx }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_50_pp_00_w = @@ -6373,7 +7489,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_50_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_4b_pp_03_modrmmod_00_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2606] // TILELOADD rTt,Mt + (const void *)&gInstructions[ 2636] // TILELOADD rTt,Mt }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_4b_pp_03_modrmmod_00_l_00_w = @@ -6408,7 +7524,7 @@ const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_4b_pp_03_modrmmod = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_4b_pp_02_modrmmod_00_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2611] // TILESTORED Mt,rTt + (const void *)&gInstructions[ 2645] // TILESTORED Mt,rTt }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_4b_pp_02_modrmmod_00_l_00_w = @@ -6443,7 +7559,7 @@ const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_4b_pp_02_modrmmod = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_4b_pp_01_modrmmod_00_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2608] // TILELOADDT1 rTt,Mt + (const void *)&gInstructions[ 2640] // TILELOADDT1 rTt,Mt }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_4b_pp_01_modrmmod_00_l_00_w = @@ -6486,10 +7602,91 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_4b_pp = } }; +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_4a_pp_03_modrmmod_00_l_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2637] // TILELOADDRS rTt,Mt +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_4a_pp_03_modrmmod_00_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_4a_pp_03_modrmmod_00_l_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_4a_pp_03_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_4a_pp_03_modrmmod_00_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_4a_pp_03_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_4a_pp_03_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_4a_pp_01_modrmmod_00_l_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2638] // TILELOADDRST1 rTt,Mt +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_4a_pp_01_modrmmod_00_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_4a_pp_01_modrmmod_00_l_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_4a_pp_01_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_4a_pp_01_modrmmod_00_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_4a_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_4a_pp_01_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_4a_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_4a_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)&gVexMap_mmmmm_02_opcode_4a_pp_03_modrmmod, + } +}; + const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_49_pp_03_modrmmod_01_modrmrm_00_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2612] // TILEZERO rTt + (const void *)&gInstructions[ 2646] // TILEZERO rTt }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_49_pp_03_modrmmod_01_modrmrm_00_l_00_w = @@ -6539,7 +7736,7 @@ const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_49_pp_03_modrmmod = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_49_pp_01_modrmreg_00_modrmmod_00_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2521] // STTILECFG Moq + (const void *)&gInstructions[ 2527] // STTILECFG Moq }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_49_pp_01_modrmreg_00_modrmmod_00_l_00_w = @@ -6589,7 +7786,7 @@ const ND_TABLE_MODRM_REG gVexMap_mmmmm_02_opcode_49_pp_01_modrmreg = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_49_pp_00_modrmreg_00_modrmmod_01_modrmrm_00_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2609] // TILERELEASE + (const void *)&gInstructions[ 2643] // TILERELEASE }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_49_pp_00_modrmreg_00_modrmmod_01_modrmrm_00_l_00_w = @@ -6688,16 +7885,97 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_49_pp = } }; +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_48_pp_01_modrmmod_01_l_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2648] // TMMULTF32PS rTt,mTt,vTt +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_48_pp_01_modrmmod_01_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_48_pp_01_modrmmod_01_l_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_48_pp_01_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_48_pp_01_modrmmod_01_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_48_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_48_pp_01_modrmmod_01_l, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_48_pp_00_modrmmod_01_l_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2654] // TTMMULTF32PS rTt,mTt,vTt +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_48_pp_00_modrmmod_01_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_48_pp_00_modrmmod_01_l_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_48_pp_00_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_48_pp_00_modrmmod_01_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_48_pp_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_48_pp_00_modrmmod_01_l, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_48_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_48_pp_00_modrmmod, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_48_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_47_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3836] // VPSLLVQ Vx,Hx,Wx + (const void *)&gInstructions[ 3881] // VPSLLVQ Vx,Hx,Wx }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_47_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3834] // VPSLLVD Vx,Hx,Wx + (const void *)&gInstructions[ 3879] // VPSLLVD Vx,Hx,Wx }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_47_pp_01_w = @@ -6723,7 +8001,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_47_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_46_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3849] // VPSRAVD Vx,Hx,Wx + (const void *)&gInstructions[ 3894] // VPSRAVD Vx,Hx,Wx }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_46_pp_01_w = @@ -6749,13 +8027,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_46_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_45_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3869] // VPSRLVQ Vx,Hx,Wx + (const void *)&gInstructions[ 3914] // VPSRLVQ Vx,Hx,Wx }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_45_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3867] // VPSRLVD Vx,Hx,Wx + (const void *)&gInstructions[ 3912] // VPSRLVD Vx,Hx,Wx }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_45_pp_01_w = @@ -6781,7 +8059,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_45_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_41_pp_01_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3596] // VPHMINPOSUW Vdq,Wdq + (const void *)&gInstructions[ 3641] // VPHMINPOSUW Vdq,Wdq }; const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_41_pp_01_l = @@ -6809,7 +8087,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_41_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_40_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3741] // VPMULLD Vx,Hx,Wx + (const void *)&gInstructions[ 3786] // VPMULLD Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_40_pp = @@ -6826,7 +8104,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_40_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_3f_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3651] // VPMAXUD Vx,Hx,Wx + (const void *)&gInstructions[ 3696] // VPMAXUD Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_3f_pp = @@ -6843,7 +8121,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_3f_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_3e_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3654] // VPMAXUW Vx,Hx,Wx + (const void *)&gInstructions[ 3699] // VPMAXUW Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_3e_pp = @@ -6860,7 +8138,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_3e_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_3d_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3644] // VPMAXSD Vx,Hx,Wx + (const void *)&gInstructions[ 3689] // VPMAXSD Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_3d_pp = @@ -6877,7 +8155,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_3d_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_3c_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3642] // VPMAXSB Vx,Hx,Wx + (const void *)&gInstructions[ 3687] // VPMAXSB Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_3c_pp = @@ -6894,7 +8172,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_3c_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_3b_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3665] // VPMINUD Vx,Hx,Wx + (const void *)&gInstructions[ 3710] // VPMINUD Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_3b_pp = @@ -6911,7 +8189,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_3b_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_3a_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3668] // VPMINUW Vx,Hx,Wx + (const void *)&gInstructions[ 3713] // VPMINUW Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_3a_pp = @@ -6928,7 +8206,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_3a_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_39_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3658] // VPMINSD Vx,Hx,Wx + (const void *)&gInstructions[ 3703] // VPMINSD Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_39_pp = @@ -6945,7 +8223,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_39_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_38_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3656] // VPMINSB Vx,Hx,Wx + (const void *)&gInstructions[ 3701] // VPMINSB Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_38_pp = @@ -6962,7 +8240,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_38_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_37_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3454] // VPCMPGTQ Vx,Hx,Wx + (const void *)&gInstructions[ 3499] // VPCMPGTQ Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_37_pp = @@ -6979,7 +8257,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_37_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_36_pp_01_l_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3515] // VPERMD Vqq,Hqq,Wqq + (const void *)&gInstructions[ 3560] // VPERMD Vqq,Hqq,Wqq }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_36_pp_01_l_01_w = @@ -7016,13 +8294,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_36_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_35_pp_01_l_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3725] // VPMOVZXDQ Vqq,Wdq + (const void *)&gInstructions[ 3770] // VPMOVZXDQ Vqq,Wdq }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_35_pp_01_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3724] // VPMOVZXDQ Vdq,Wq + (const void *)&gInstructions[ 3769] // VPMOVZXDQ Vdq,Wq }; const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_35_pp_01_l = @@ -7050,13 +8328,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_35_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_34_pp_01_l_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3731] // VPMOVZXWQ Vqq,Wq + (const void *)&gInstructions[ 3776] // VPMOVZXWQ Vqq,Wq }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_34_pp_01_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3730] // VPMOVZXWQ Vdq,Wd + (const void *)&gInstructions[ 3775] // VPMOVZXWQ Vdq,Wd }; const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_34_pp_01_l = @@ -7084,13 +8362,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_34_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_33_pp_01_l_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3728] // VPMOVZXWD Vqq,Wdq + (const void *)&gInstructions[ 3773] // VPMOVZXWD Vqq,Wdq }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_33_pp_01_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3727] // VPMOVZXWD Vdq,Wq + (const void *)&gInstructions[ 3772] // VPMOVZXWD Vdq,Wq }; const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_33_pp_01_l = @@ -7118,13 +8396,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_33_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_32_pp_01_l_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3719] // VPMOVZXBQ Vqq,Wd + (const void *)&gInstructions[ 3764] // VPMOVZXBQ Vqq,Wd }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_32_pp_01_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3718] // VPMOVZXBQ Vdq,Ww + (const void *)&gInstructions[ 3763] // VPMOVZXBQ Vdq,Ww }; const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_32_pp_01_l = @@ -7152,13 +8430,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_32_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_31_pp_01_l_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3716] // VPMOVZXBD Vqq,Wq + (const void *)&gInstructions[ 3761] // VPMOVZXBD Vqq,Wq }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_31_pp_01_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3715] // VPMOVZXBD Vdq,Wd + (const void *)&gInstructions[ 3760] // VPMOVZXBD Vdq,Wd }; const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_31_pp_01_l = @@ -7186,13 +8464,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_31_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_30_pp_01_l_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3722] // VPMOVZXBW Vqq,Wdq + (const void *)&gInstructions[ 3767] // VPMOVZXBW Vqq,Wdq }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_30_pp_01_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3721] // VPMOVZXBW Vdq,Wq + (const void *)&gInstructions[ 3766] // VPMOVZXBW Vdq,Wq }; const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_30_pp_01_l = @@ -7220,7 +8498,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_30_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_2f_pp_01_modrmmod_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3187] // VMASKMOVPD Mx,Hx,Vx + (const void *)&gInstructions[ 3228] // VMASKMOVPD Mx,Hx,Vx }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_2f_pp_01_modrmmod_00_w = @@ -7255,7 +8533,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_2f_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_2e_pp_01_modrmmod_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3189] // VMASKMOVPS Mx,Hx,Vx + (const void *)&gInstructions[ 3230] // VMASKMOVPS Mx,Hx,Vx }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_2e_pp_01_modrmmod_00_w = @@ -7290,7 +8568,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_2e_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_2d_pp_01_modrmmod_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3186] // VMASKMOVPD Vx,Hx,Mx + (const void *)&gInstructions[ 3227] // VMASKMOVPD Vx,Hx,Mx }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_2d_pp_01_modrmmod_00_w = @@ -7325,7 +8603,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_2d_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_2c_pp_01_modrmmod_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3188] // VMASKMOVPS Vx,Hx,Mx + (const void *)&gInstructions[ 3229] // VMASKMOVPS Vx,Hx,Mx }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_2c_pp_01_modrmmod_00_w = @@ -7360,7 +8638,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_2c_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_2b_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3381] // VPACKUSDW Vx,Hx,Wx + (const void *)&gInstructions[ 3426] // VPACKUSDW Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_2b_pp = @@ -7377,7 +8655,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_2b_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_2a_pp_01_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3288] // VMOVNTDQA Vx,Mx + (const void *)&gInstructions[ 3329] // VMOVNTDQA Vx,Mx }; const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_2a_pp_01_modrmmod = @@ -7403,7 +8681,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_2a_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_29_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3444] // VPCMPEQQ Vx,Hx,Wx + (const void *)&gInstructions[ 3489] // VPCMPEQQ Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_29_pp = @@ -7420,7 +8698,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_29_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_28_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3733] // VPMULDQ Vx,Hx,Wx + (const void *)&gInstructions[ 3778] // VPMULDQ Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_28_pp = @@ -7437,13 +8715,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_28_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_25_pp_01_l_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3699] // VPMOVSXDQ Vqq,Wdq + (const void *)&gInstructions[ 3744] // VPMOVSXDQ Vqq,Wdq }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_25_pp_01_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3698] // VPMOVSXDQ Vdq,Wq + (const void *)&gInstructions[ 3743] // VPMOVSXDQ Vdq,Wq }; const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_25_pp_01_l = @@ -7471,13 +8749,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_25_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_24_pp_01_l_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3705] // VPMOVSXWQ Vqq,Wq + (const void *)&gInstructions[ 3750] // VPMOVSXWQ Vqq,Wq }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_24_pp_01_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3704] // VPMOVSXWQ Vdq,Wd + (const void *)&gInstructions[ 3749] // VPMOVSXWQ Vdq,Wd }; const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_24_pp_01_l = @@ -7505,13 +8783,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_24_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_23_pp_01_l_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3702] // VPMOVSXWD Vqq,Wdq + (const void *)&gInstructions[ 3747] // VPMOVSXWD Vqq,Wdq }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_23_pp_01_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3701] // VPMOVSXWD Vdq,Wq + (const void *)&gInstructions[ 3746] // VPMOVSXWD Vdq,Wq }; const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_23_pp_01_l = @@ -7539,13 +8817,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_23_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_22_pp_01_l_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3693] // VPMOVSXBQ Vqq,Wd + (const void *)&gInstructions[ 3738] // VPMOVSXBQ Vqq,Wd }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_22_pp_01_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3692] // VPMOVSXBQ Vdq,Ww + (const void *)&gInstructions[ 3737] // VPMOVSXBQ Vdq,Ww }; const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_22_pp_01_l = @@ -7573,13 +8851,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_22_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_21_pp_01_l_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3690] // VPMOVSXBD Vqq,Wq + (const void *)&gInstructions[ 3735] // VPMOVSXBD Vqq,Wq }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_21_pp_01_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3689] // VPMOVSXBD Vdq,Wd + (const void *)&gInstructions[ 3734] // VPMOVSXBD Vdq,Wd }; const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_21_pp_01_l = @@ -7607,13 +8885,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_21_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_20_pp_01_l_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3696] // VPMOVSXBW Vqq,Wdq + (const void *)&gInstructions[ 3741] // VPMOVSXBW Vqq,Wdq }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_20_pp_01_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3695] // VPMOVSXBW Vdq,Wq + (const void *)&gInstructions[ 3740] // VPMOVSXBW Vdq,Wq }; const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_20_pp_01_l = @@ -7641,7 +8919,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_20_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_1e_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3372] // VPABSD Vx,Wx + (const void *)&gInstructions[ 3417] // VPABSD Vx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_1e_pp = @@ -7658,7 +8936,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_1e_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_1d_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3375] // VPABSW Vx,Wx + (const void *)&gInstructions[ 3420] // VPABSW Vx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_1d_pp = @@ -7675,7 +8953,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_1d_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_1c_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3370] // VPABSB Vx,Wx + (const void *)&gInstructions[ 3415] // VPABSB Vx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_1c_pp = @@ -7692,7 +8970,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_1c_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_1a_pp_01_modrmmod_00_l_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2686] // VBROADCASTF128 Vqq,Mdq + (const void *)&gInstructions[ 2727] // VBROADCASTF128 Vqq,Mdq }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_1a_pp_01_modrmmod_00_l_01_w = @@ -7738,7 +9016,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_1a_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_19_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2699] // VBROADCASTSD Vqq,Wsd + (const void *)&gInstructions[ 2740] // VBROADCASTSD Vqq,Wsd }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_19_pp_01_w = @@ -7764,7 +9042,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_19_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_18_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2701] // VBROADCASTSS Vx,Wss + (const void *)&gInstructions[ 2742] // VBROADCASTSS Vx,Wss }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_18_pp_01_w = @@ -7790,7 +9068,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_18_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_17_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3893] // VPTEST Vx,Wx + (const void *)&gInstructions[ 3938] // VPTEST Vx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_17_pp = @@ -7807,7 +9085,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_17_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_16_pp_01_l_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3540] // VPERMPS Vqq,Hqq,Wqq + (const void *)&gInstructions[ 3585] // VPERMPS Vqq,Hqq,Wqq }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_16_pp_01_l_01_w = @@ -7844,7 +9122,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_16_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_13_pp_01_l_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2768] // VCVTPH2PS Vqq,Wdq + (const void *)&gInstructions[ 2809] // VCVTPH2PS Vqq,Wdq }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_13_pp_01_l_01_w = @@ -7859,7 +9137,7 @@ const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_13_pp_01_l_01_w = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_13_pp_01_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2767] // VCVTPH2PS Vdq,Wq + (const void *)&gInstructions[ 2808] // VCVTPH2PS Vdq,Wq }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_13_pp_01_l_00_w = @@ -7896,7 +9174,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_13_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_0f_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4027] // VTESTPD Vx,Wx + (const void *)&gInstructions[ 4074] // VTESTPD Vx,Wx }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_0f_pp_01_w = @@ -7922,7 +9200,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_0f_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_0e_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4028] // VTESTPS Vx,Wx + (const void *)&gInstructions[ 4075] // VTESTPS Vx,Wx }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_0e_pp_01_w = @@ -7948,7 +9226,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_0e_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_0d_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3528] // VPERMILPD Vx,Hx,Wx + (const void *)&gInstructions[ 3573] // VPERMILPD Vx,Hx,Wx }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_0d_pp_01_w = @@ -7974,7 +9252,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_0d_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_0c_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3532] // VPERMILPS Vx,Hx,Wx + (const void *)&gInstructions[ 3577] // VPERMILPS Vx,Hx,Wx }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_0c_pp_01_w = @@ -8000,7 +9278,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_0c_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_0b_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3735] // VPMULHRSW Vx,Hx,Wx + (const void *)&gInstructions[ 3780] // VPMULHRSW Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_0b_pp = @@ -8017,7 +9295,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_0b_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_0a_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3821] // VPSIGND Vx,Hx,Wx + (const void *)&gInstructions[ 3866] // VPSIGND Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_0a_pp = @@ -8034,7 +9312,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_0a_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_09_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3822] // VPSIGNW Vx,Hx,Wx + (const void *)&gInstructions[ 3867] // VPSIGNW Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_09_pp = @@ -8051,7 +9329,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_09_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_08_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3820] // VPSIGNB Vx,Hx,Wx + (const void *)&gInstructions[ 3865] // VPSIGNB Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_08_pp = @@ -8068,7 +9346,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_08_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_07_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3600] // VPHSUBSW Vx,Hx,Wx + (const void *)&gInstructions[ 3645] // VPHSUBSW Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_07_pp = @@ -8085,7 +9363,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_07_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_06_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3598] // VPHSUBD Vx,Hx,Wx + (const void *)&gInstructions[ 3643] // VPHSUBD Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_06_pp = @@ -8102,7 +9380,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_06_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_05_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3601] // VPHSUBW Vx,Hx,Wx + (const void *)&gInstructions[ 3646] // VPHSUBW Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_05_pp = @@ -8119,7 +9397,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_05_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_04_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3634] // VPMADDUBSW Vx,Hx,Wx + (const void *)&gInstructions[ 3679] // VPMADDUBSW Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_04_pp = @@ -8136,7 +9414,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_04_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_03_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3586] // VPHADDSW Vx,Hx,Wx + (const void *)&gInstructions[ 3631] // VPHADDSW Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_03_pp = @@ -8153,7 +9431,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_03_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_02_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3584] // VPHADDD Vx,Hx,Wx + (const void *)&gInstructions[ 3629] // VPHADDD Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_02_pp = @@ -8170,7 +9448,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_02_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_01_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3593] // VPHADDW Vx,Hx,Wx + (const void *)&gInstructions[ 3638] // VPHADDW Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_01_pp = @@ -8187,7 +9465,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_01_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_00_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3812] // VPSHUFB Vx,Hx,Wx + (const void *)&gInstructions[ 3857] // VPSHUFB Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_00_pp = @@ -8277,9 +9555,9 @@ const ND_TABLE_OPCODE gVexMap_mmmmm_02_opcode = /* 45 */ (const void *)&gVexMap_mmmmm_02_opcode_45_pp, /* 46 */ (const void *)&gVexMap_mmmmm_02_opcode_46_pp, /* 47 */ (const void *)&gVexMap_mmmmm_02_opcode_47_pp, - /* 48 */ (const void *)ND_NULL, + /* 48 */ (const void *)&gVexMap_mmmmm_02_opcode_48_pp, /* 49 */ (const void *)&gVexMap_mmmmm_02_opcode_49_pp, - /* 4a */ (const void *)ND_NULL, + /* 4a */ (const void *)&gVexMap_mmmmm_02_opcode_4a_pp, /* 4b */ (const void *)&gVexMap_mmmmm_02_opcode_4b_pp, /* 4c */ (const void *)ND_NULL, /* 4d */ (const void *)ND_NULL, @@ -8300,7 +9578,7 @@ const ND_TABLE_OPCODE gVexMap_mmmmm_02_opcode = /* 5c */ (const void *)&gVexMap_mmmmm_02_opcode_5c_pp, /* 5d */ (const void *)ND_NULL, /* 5e */ (const void *)&gVexMap_mmmmm_02_opcode_5e_pp, - /* 5f */ (const void *)ND_NULL, + /* 5f */ (const void *)&gVexMap_mmmmm_02_opcode_5f_pp, /* 60 */ (const void *)ND_NULL, /* 61 */ (const void *)ND_NULL, /* 62 */ (const void *)ND_NULL, @@ -8312,11 +9590,11 @@ const ND_TABLE_OPCODE gVexMap_mmmmm_02_opcode = /* 68 */ (const void *)ND_NULL, /* 69 */ (const void *)ND_NULL, /* 6a */ (const void *)ND_NULL, - /* 6b */ (const void *)ND_NULL, + /* 6b */ (const void *)&gVexMap_mmmmm_02_opcode_6b_pp, /* 6c */ (const void *)&gVexMap_mmmmm_02_opcode_6c_pp, /* 6d */ (const void *)ND_NULL, - /* 6e */ (const void *)ND_NULL, - /* 6f */ (const void *)ND_NULL, + /* 6e */ (const void *)&gVexMap_mmmmm_02_opcode_6e_pp, + /* 6f */ (const void *)&gVexMap_mmmmm_02_opcode_6f_pp, /* 70 */ (const void *)ND_NULL, /* 71 */ (const void *)ND_NULL, /* 72 */ (const void *)&gVexMap_mmmmm_02_opcode_72_pp, @@ -8467,7 +9745,7 @@ const ND_TABLE_OPCODE gVexMap_mmmmm_02_opcode = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_fe_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3387] // VPADDD Vx,Hx,Wx + (const void *)&gInstructions[ 3432] // VPADDD Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_fe_pp = @@ -8484,7 +9762,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_fe_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_fd_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3399] // VPADDW Vx,Hx,Wx + (const void *)&gInstructions[ 3444] // VPADDW Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_fd_pp = @@ -8501,7 +9779,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_fd_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_fc_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3385] // VPADDB Vx,Hx,Wx + (const void *)&gInstructions[ 3430] // VPADDB Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_fc_pp = @@ -8518,7 +9796,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_fc_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_fb_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3880] // VPSUBQ Vx,Hx,Wx + (const void *)&gInstructions[ 3925] // VPSUBQ Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_fb_pp = @@ -8535,7 +9813,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_fb_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_fa_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3878] // VPSUBD Vx,Hx,Wx + (const void *)&gInstructions[ 3923] // VPSUBD Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_fa_pp = @@ -8552,7 +9830,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_fa_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_f9_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3890] // VPSUBW Vx,Hx,Wx + (const void *)&gInstructions[ 3935] // VPSUBW Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_f9_pp = @@ -8569,7 +9847,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_f9_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_f8_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3876] // VPSUBB Vx,Hx,Wx + (const void *)&gInstructions[ 3921] // VPSUBB Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_f8_pp = @@ -8586,7 +9864,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_f8_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_f7_pp_01_modrmmod_01_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3185] // VMASKMOVDQU Vdq,Udq + (const void *)&gInstructions[ 3226] // VMASKMOVDQU Vdq,Udq }; const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_f7_pp_01_modrmmod_01_l = @@ -8623,7 +9901,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_f7_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_f6_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3778] // VPSADBW Vx,Hx,Wx + (const void *)&gInstructions[ 3823] // VPSADBW Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_f6_pp = @@ -8640,7 +9918,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_f6_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_f5_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3636] // VPMADDWD Vx,Hx,Wx + (const void *)&gInstructions[ 3681] // VPMADDWD Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_f5_pp = @@ -8657,7 +9935,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_f5_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_f4_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3747] // VPMULUDQ Vx,Hx,Wx + (const void *)&gInstructions[ 3792] // VPMULUDQ Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_f4_pp = @@ -8674,7 +9952,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_f4_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_f3_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3832] // VPSLLQ Vx,Hx,Wdq + (const void *)&gInstructions[ 3877] // VPSLLQ Vx,Hx,Wdq }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_f3_pp = @@ -8691,7 +9969,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_f3_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_f2_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3826] // VPSLLD Vx,Hx,Wdq + (const void *)&gInstructions[ 3871] // VPSLLD Vx,Hx,Wdq }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_f2_pp = @@ -8708,7 +9986,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_f2_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_f1_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3841] // VPSLLW Vx,Hx,Wdq + (const void *)&gInstructions[ 3886] // VPSLLW Vx,Hx,Wdq }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_f1_pp = @@ -8725,7 +10003,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_f1_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_f0_pp_03_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3183] // VLDDQU Vx,Mx + (const void *)&gInstructions[ 3224] // VLDDQU Vx,Mx }; const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_f0_pp_03_modrmmod = @@ -8751,7 +10029,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_f0_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_ef_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3918] // VPXOR Vx,Hx,Wx + (const void *)&gInstructions[ 3963] // VPXOR Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_ef_pp = @@ -8768,7 +10046,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_ef_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_ee_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3647] // VPMAXSW Vx,Hx,Wx + (const void *)&gInstructions[ 3692] // VPMAXSW Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_ee_pp = @@ -8785,7 +10063,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_ee_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_ed_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3393] // VPADDSW Vx,Hx,Wx + (const void *)&gInstructions[ 3438] // VPADDSW Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_ed_pp = @@ -8802,7 +10080,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_ed_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_ec_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3391] // VPADDSB Vx,Hx,Wx + (const void *)&gInstructions[ 3436] // VPADDSB Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_ec_pp = @@ -8819,7 +10097,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_ec_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_eb_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3752] // VPOR Vx,Hx,Wx + (const void *)&gInstructions[ 3797] // VPOR Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_eb_pp = @@ -8836,7 +10114,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_eb_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_ea_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3661] // VPMINSW Vx,Hx,Wx + (const void *)&gInstructions[ 3706] // VPMINSW Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_ea_pp = @@ -8853,7 +10131,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_ea_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_e9_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3884] // VPSUBSW Vx,Hx,Wx + (const void *)&gInstructions[ 3929] // VPSUBSW Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_e9_pp = @@ -8870,7 +10148,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_e9_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_e8_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3882] // VPSUBSB Vx,Hx,Wx + (const void *)&gInstructions[ 3927] // VPSUBSB Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_e8_pp = @@ -8887,7 +10165,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_e8_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_e7_pp_01_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3286] // VMOVNTDQ Mx,Vx + (const void *)&gInstructions[ 3327] // VMOVNTDQ Mx,Vx }; const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_e7_pp_01_modrmmod = @@ -8913,19 +10191,19 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_e7_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_e6_pp_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2754] // VCVTPD2DQ Vdq,Wx + (const void *)&gInstructions[ 2795] // VCVTPD2DQ Vdq,Wx }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_e6_pp_02_l_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2731] // VCVTDQ2PD Vqq,Wdq + (const void *)&gInstructions[ 2772] // VCVTDQ2PD Vqq,Wdq }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_e6_pp_02_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2730] // VCVTDQ2PD Vdq,Wq + (const void *)&gInstructions[ 2771] // VCVTDQ2PD Vdq,Wq }; const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_e6_pp_02_l = @@ -8942,7 +10220,7 @@ const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_e6_pp_02_l = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_e6_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2817] // VCVTTPD2DQ Vdq,Wx + (const void *)&gInstructions[ 2858] // VCVTTPD2DQ Vdq,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_e6_pp = @@ -8959,7 +10237,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_e6_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_e5_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3739] // VPMULHW Vx,Hx,Wx + (const void *)&gInstructions[ 3784] // VPMULHW Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_e5_pp = @@ -8976,7 +10254,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_e5_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_e4_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3737] // VPMULHUW Vx,Hx,Wx + (const void *)&gInstructions[ 3782] // VPMULHUW Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_e4_pp = @@ -8993,7 +10271,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_e4_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_e3_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3411] // VPAVGW Vx,Hx,Wx + (const void *)&gInstructions[ 3456] // VPAVGW Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_e3_pp = @@ -9010,7 +10288,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_e3_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_e2_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3845] // VPSRAD Vx,Hx,Wdq + (const void *)&gInstructions[ 3890] // VPSRAD Vx,Hx,Wdq }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_e2_pp = @@ -9027,7 +10305,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_e2_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_e1_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3855] // VPSRAW Vx,Hx,Wdq + (const void *)&gInstructions[ 3900] // VPSRAW Vx,Hx,Wdq }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_e1_pp = @@ -9044,7 +10322,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_e1_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_e0_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3409] // VPAVGB Vx,Hx,Wx + (const void *)&gInstructions[ 3454] // VPAVGB Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_e0_pp = @@ -9061,7 +10339,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_e0_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_df_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3404] // VPANDN Vx,Hx,Wx + (const void *)&gInstructions[ 3449] // VPANDN Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_df_pp = @@ -9078,7 +10356,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_df_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_de_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3649] // VPMAXUB Vx,Hx,Wx + (const void *)&gInstructions[ 3694] // VPMAXUB Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_de_pp = @@ -9095,7 +10373,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_de_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_dd_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3397] // VPADDUSW Vx,Hx,Wx + (const void *)&gInstructions[ 3442] // VPADDUSW Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_dd_pp = @@ -9112,7 +10390,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_dd_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_dc_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3395] // VPADDUSB Vx,Hx,Wx + (const void *)&gInstructions[ 3440] // VPADDUSB Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_dc_pp = @@ -9129,7 +10407,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_dc_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_db_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3402] // VPAND Vx,Hx,Wx + (const void *)&gInstructions[ 3447] // VPAND Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_db_pp = @@ -9146,7 +10424,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_db_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_da_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3663] // VPMINUB Vx,Hx,Wx + (const void *)&gInstructions[ 3708] // VPMINUB Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_da_pp = @@ -9163,7 +10441,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_da_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_d9_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3888] // VPSUBUSW Vx,Hx,Wx + (const void *)&gInstructions[ 3933] // VPSUBUSW Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_d9_pp = @@ -9180,7 +10458,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_d9_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_d8_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3886] // VPSUBUSB Vx,Hx,Wx + (const void *)&gInstructions[ 3931] // VPSUBUSB Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_d8_pp = @@ -9197,7 +10475,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_d8_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_d7_pp_01_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3677] // VPMOVMSKB Gy,Ux + (const void *)&gInstructions[ 3722] // VPMOVMSKB Gy,Ux }; const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_d7_pp_01_modrmmod = @@ -9223,7 +10501,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_d7_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_d6_pp_01_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3300] // VMOVQ Wq,Vdq + (const void *)&gInstructions[ 3341] // VMOVQ Wq,Vdq }; const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_d6_pp_01_l = @@ -9251,7 +10529,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_d6_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_d5_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3744] // VPMULLW Vx,Hx,Wx + (const void *)&gInstructions[ 3789] // VPMULLW Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_d5_pp = @@ -9268,7 +10546,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_d5_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_d4_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3389] // VPADDQ Vx,Hx,Wx + (const void *)&gInstructions[ 3434] // VPADDQ Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_d4_pp = @@ -9285,7 +10563,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_d4_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_d3_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3865] // VPSRLQ Vx,Hx,Wdq + (const void *)&gInstructions[ 3910] // VPSRLQ Vx,Hx,Wdq }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_d3_pp = @@ -9302,7 +10580,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_d3_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_d2_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3859] // VPSRLD Vx,Hx,Wdq + (const void *)&gInstructions[ 3904] // VPSRLD Vx,Hx,Wdq }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_d2_pp = @@ -9319,7 +10597,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_d2_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_d1_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3874] // VPSRLW Vx,Hx,Wdq + (const void *)&gInstructions[ 3919] // VPSRLW Vx,Hx,Wdq }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_d1_pp = @@ -9336,13 +10614,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_d1_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_d0_pp_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2657] // VADDSUBPS Vps,Hps,Wps + (const void *)&gInstructions[ 2698] // VADDSUBPS Vps,Hps,Wps }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_d0_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2656] // VADDSUBPD Vpd,Hpd,Wpd + (const void *)&gInstructions[ 2697] // VADDSUBPD Vpd,Hpd,Wpd }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_d0_pp = @@ -9359,13 +10637,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_d0_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_c6_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3996] // VSHUFPD Vpd,Hpd,Wpd,Ib + (const void *)&gInstructions[ 4041] // VSHUFPD Vpd,Hpd,Wpd,Ib }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_c6_pp_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3998] // VSHUFPS Vps,Hps,Wps,Ib + (const void *)&gInstructions[ 4043] // VSHUFPS Vps,Hps,Wps,Ib }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_c6_pp = @@ -9382,7 +10660,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_c6_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_c5_pp_01_modrmmod_01_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3570] // VPEXTRW Gy,Udq,Ib + (const void *)&gInstructions[ 3615] // VPEXTRW Gy,Udq,Ib }; const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_c5_pp_01_modrmmod_01_l = @@ -9419,7 +10697,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_c5_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_c4_pp_01_modrmmod_01_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3614] // VPINSRW Vdq,Hdq,Rd,Ib + (const void *)&gInstructions[ 3659] // VPINSRW Vdq,Hdq,Rd,Ib }; const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_c4_pp_01_modrmmod_01_l = @@ -9436,7 +10714,7 @@ const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_c4_pp_01_modrmmod_01_l = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_c4_pp_01_modrmmod_00_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3613] // VPINSRW Vdq,Hdq,Mw,Ib + (const void *)&gInstructions[ 3658] // VPINSRW Vdq,Hdq,Mw,Ib }; const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_c4_pp_01_modrmmod_00_l = @@ -9473,25 +10751,25 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_c4_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_c2_pp_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2709] // VCMPSD Vsd,Hsd,Wsd,Ib + (const void *)&gInstructions[ 2750] // VCMPSD Vsd,Hsd,Wsd,Ib }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_c2_pp_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2712] // VCMPSS Vss,Hss,Wss,Ib + (const void *)&gInstructions[ 2753] // VCMPSS Vss,Hss,Wss,Ib }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_c2_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2704] // VCMPPD Vpd,Hpd,Wpd,Ib + (const void *)&gInstructions[ 2745] // VCMPPD Vpd,Hpd,Wpd,Ib }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_c2_pp_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2707] // VCMPPS Vss,Hss,Wss,Ib + (const void *)&gInstructions[ 2748] // VCMPPS Vss,Hss,Wss,Ib }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_c2_pp = @@ -9523,7 +10801,7 @@ const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_ae_pp_03_modrmreg_07_modrmmod = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_ae_pp_03_modrmreg_06_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2499] // SPFLT Ry + (const void *)&gInstructions[ 2505] // SPFLT Ry }; const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_ae_pp_03_modrmreg_06_modrmmod = @@ -9598,7 +10876,7 @@ const ND_TABLE_MODRM_REG gVexMap_mmmmm_01_opcode_ae_pp_02_modrmreg = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_ae_pp_00_modrmreg_03_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4015] // VSTMXCSR Md + (const void *)&gInstructions[ 4062] // VSTMXCSR Md }; const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_ae_pp_00_modrmreg_03_modrmmod = @@ -9613,7 +10891,7 @@ const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_ae_pp_00_modrmreg_03_modrmmod = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_ae_pp_00_modrmreg_02_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3184] // VLDMXCSR Md + (const void *)&gInstructions[ 3225] // VLDMXCSR Md }; const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_ae_pp_00_modrmreg_02_modrmmod = @@ -10334,13 +11612,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_90_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_7f_pp_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3254] // VMOVDQU Wx,Vx + (const void *)&gInstructions[ 3295] // VMOVDQU Wx,Vx }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_7f_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3248] // VMOVDQA Wx,Vx + (const void *)&gInstructions[ 3289] // VMOVDQA Wx,Vx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_7f_pp = @@ -10357,7 +11635,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_7f_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_7e_pp_02_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3299] // VMOVQ Vdq,Wq + (const void *)&gInstructions[ 3340] // VMOVQ Vdq,Wq }; const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_7e_pp_02_l = @@ -10374,13 +11652,13 @@ const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_7e_pp_02_l = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_7e_pp_01_l_00_wi_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3298] // VMOVQ Ey,Vq + (const void *)&gInstructions[ 3339] // VMOVQ Ey,Vq }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_7e_pp_01_l_00_wi_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3241] // VMOVD Ey,Vd + (const void *)&gInstructions[ 3282] // VMOVD Ey,Vd }; const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_7e_pp_01_l_00_wi = @@ -10417,13 +11695,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_7e_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_7d_pp_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3168] // VHSUBPS Vps,Hps,Wps + (const void *)&gInstructions[ 3209] // VHSUBPS Vps,Hps,Wps }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_7d_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3167] // VHSUBPD Vpd,Hpd,Wpd + (const void *)&gInstructions[ 3208] // VHSUBPD Vpd,Hpd,Wpd }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_7d_pp = @@ -10440,13 +11718,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_7d_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_7c_pp_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3166] // VHADDPS Vps,Hps,Wps + (const void *)&gInstructions[ 3207] // VHADDPS Vps,Hps,Wps }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_7c_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3165] // VHADDPD Vpd,Hpd,Wpd + (const void *)&gInstructions[ 3206] // VHADDPD Vpd,Hpd,Wpd }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_7c_pp = @@ -10463,13 +11741,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_7c_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_77_pp_00_l_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4049] // VZEROALL + (const void *)&gInstructions[ 4096] // VZEROALL }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_77_pp_00_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4050] // VZEROUPPER + (const void *)&gInstructions[ 4097] // VZEROUPPER }; const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_77_pp_00_l = @@ -10497,7 +11775,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_77_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_76_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3442] // VPCMPEQD Vx,Hx,Wx + (const void *)&gInstructions[ 3487] // VPCMPEQD Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_76_pp = @@ -10514,7 +11792,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_76_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_75_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3446] // VPCMPEQW Vx,Hx,Wx + (const void *)&gInstructions[ 3491] // VPCMPEQW Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_75_pp = @@ -10531,7 +11809,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_75_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_74_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3440] // VPCMPEQB Vx,Hx,Wx + (const void *)&gInstructions[ 3485] // VPCMPEQB Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_74_pp = @@ -10548,7 +11826,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_74_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_73_pp_01_modrmreg_07_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3828] // VPSLLDQ Hx,Ux,Ib + (const void *)&gInstructions[ 3873] // VPSLLDQ Hx,Ux,Ib }; const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_73_pp_01_modrmreg_07_modrmmod = @@ -10563,7 +11841,7 @@ const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_73_pp_01_modrmreg_07_modrmmod = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_73_pp_01_modrmreg_06_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3831] // VPSLLQ Hx,Ux,Ib + (const void *)&gInstructions[ 3876] // VPSLLQ Hx,Ux,Ib }; const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_73_pp_01_modrmreg_06_modrmmod = @@ -10578,7 +11856,7 @@ const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_73_pp_01_modrmreg_06_modrmmod = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_73_pp_01_modrmreg_03_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3861] // VPSRLDQ Hx,Ux,Ib + (const void *)&gInstructions[ 3906] // VPSRLDQ Hx,Ux,Ib }; const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_73_pp_01_modrmreg_03_modrmmod = @@ -10593,7 +11871,7 @@ const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_73_pp_01_modrmreg_03_modrmmod = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_73_pp_01_modrmreg_02_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3864] // VPSRLQ Hx,Ux,Ib + (const void *)&gInstructions[ 3909] // VPSRLQ Hx,Ux,Ib }; const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_73_pp_01_modrmreg_02_modrmmod = @@ -10634,7 +11912,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_73_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_72_pp_01_modrmreg_06_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3825] // VPSLLD Hx,Ux,Ib + (const void *)&gInstructions[ 3870] // VPSLLD Hx,Ux,Ib }; const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_72_pp_01_modrmreg_06_modrmmod = @@ -10649,7 +11927,7 @@ const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_72_pp_01_modrmreg_06_modrmmod = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_72_pp_01_modrmreg_04_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3844] // VPSRAD Hx,Ux,Ib + (const void *)&gInstructions[ 3889] // VPSRAD Hx,Ux,Ib }; const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_72_pp_01_modrmreg_04_modrmmod = @@ -10664,7 +11942,7 @@ const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_72_pp_01_modrmreg_04_modrmmod = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_72_pp_01_modrmreg_02_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3858] // VPSRLD Hx,Ux,Ib + (const void *)&gInstructions[ 3903] // VPSRLD Hx,Ux,Ib }; const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_72_pp_01_modrmreg_02_modrmmod = @@ -10705,7 +11983,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_72_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_71_pp_01_modrmreg_06_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3840] // VPSLLW Hx,Ux,Ib + (const void *)&gInstructions[ 3885] // VPSLLW Hx,Ux,Ib }; const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_71_pp_01_modrmreg_06_modrmmod = @@ -10720,7 +11998,7 @@ const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_71_pp_01_modrmreg_06_modrmmod = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_71_pp_01_modrmreg_04_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3854] // VPSRAW Hx,Ux,Ib + (const void *)&gInstructions[ 3899] // VPSRAW Hx,Ux,Ib }; const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_71_pp_01_modrmreg_04_modrmmod = @@ -10735,7 +12013,7 @@ const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_71_pp_01_modrmreg_04_modrmmod = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_71_pp_01_modrmreg_02_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3873] // VPSRLW Hx,Ux,Ib + (const void *)&gInstructions[ 3918] // VPSRLW Hx,Ux,Ib }; const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_71_pp_01_modrmreg_02_modrmmod = @@ -10776,19 +12054,19 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_71_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_70_pp_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3819] // VPSHUFLW Vx,Wx,Ib + (const void *)&gInstructions[ 3864] // VPSHUFLW Vx,Wx,Ib }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_70_pp_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3817] // VPSHUFHW Vx,Wx,Ib + (const void *)&gInstructions[ 3862] // VPSHUFHW Vx,Wx,Ib }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_70_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3815] // VPSHUFD Vx,Wx,Ib + (const void *)&gInstructions[ 3860] // VPSHUFD Vx,Wx,Ib }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_70_pp = @@ -10805,13 +12083,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_70_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_6f_pp_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3253] // VMOVDQU Vx,Wx + (const void *)&gInstructions[ 3294] // VMOVDQU Vx,Wx }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_6f_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3247] // VMOVDQA Vx,Wx + (const void *)&gInstructions[ 3288] // VMOVDQA Vx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_6f_pp = @@ -10828,13 +12106,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_6f_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_6e_pp_01_l_00_wi_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3297] // VMOVQ Vdq,Ey + (const void *)&gInstructions[ 3338] // VMOVQ Vdq,Ey }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_6e_pp_01_l_00_wi_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3240] // VMOVD Vdq,Ey + (const void *)&gInstructions[ 3281] // VMOVD Vdq,Ey }; const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_6e_pp_01_l_00_wi = @@ -10871,7 +12149,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_6e_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_6d_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3907] // VPUNPCKHQDQ Vx,Hx,Wx + (const void *)&gInstructions[ 3952] // VPUNPCKHQDQ Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_6d_pp = @@ -10888,7 +12166,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_6d_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_6c_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3915] // VPUNPCKLQDQ Vx,Hx,Wx + (const void *)&gInstructions[ 3960] // VPUNPCKLQDQ Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_6c_pp = @@ -10905,7 +12183,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_6c_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_6b_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3377] // VPACKSSDW Vx,Hx,Wx + (const void *)&gInstructions[ 3422] // VPACKSSDW Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_6b_pp = @@ -10922,7 +12200,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_6b_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_6a_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3905] // VPUNPCKHDQ Vx,Hx,Wx + (const void *)&gInstructions[ 3950] // VPUNPCKHDQ Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_6a_pp = @@ -10939,7 +12217,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_6a_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_69_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3909] // VPUNPCKHWD Vx,Hx,Wx + (const void *)&gInstructions[ 3954] // VPUNPCKHWD Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_69_pp = @@ -10956,7 +12234,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_69_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_68_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3903] // VPUNPCKHBW Vx,Hx,Wx + (const void *)&gInstructions[ 3948] // VPUNPCKHBW Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_68_pp = @@ -10973,7 +12251,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_68_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_67_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3383] // VPACKUSWB Vx,Hx,Wx + (const void *)&gInstructions[ 3428] // VPACKUSWB Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_67_pp = @@ -10990,7 +12268,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_67_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_66_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3452] // VPCMPGTD Vx,Hx,Wx + (const void *)&gInstructions[ 3497] // VPCMPGTD Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_66_pp = @@ -11007,7 +12285,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_66_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_65_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3456] // VPCMPGTW Vx,Hx,Wx + (const void *)&gInstructions[ 3501] // VPCMPGTW Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_65_pp = @@ -11024,7 +12302,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_65_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_64_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3450] // VPCMPGTB Vx,Hx,Wx + (const void *)&gInstructions[ 3495] // VPCMPGTB Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_64_pp = @@ -11041,7 +12319,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_64_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_63_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3379] // VPACKSSWB Vx,Hx,Wx + (const void *)&gInstructions[ 3424] // VPACKSSWB Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_63_pp = @@ -11058,7 +12336,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_63_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_62_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3913] // VPUNPCKLDQ Vx,Hx,Wx + (const void *)&gInstructions[ 3958] // VPUNPCKLDQ Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_62_pp = @@ -11075,7 +12353,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_62_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_61_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3917] // VPUNPCKLWD Vx,Hx,Wx + (const void *)&gInstructions[ 3962] // VPUNPCKLWD Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_61_pp = @@ -11092,7 +12370,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_61_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_60_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3911] // VPUNPCKLBW Vx,Hx,Wx + (const void *)&gInstructions[ 3956] // VPUNPCKLBW Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_60_pp = @@ -11109,25 +12387,25 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_60_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5f_pp_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3197] // VMAXSD Vsd,Hsd,Wsd + (const void *)&gInstructions[ 3238] // VMAXSD Vsd,Hsd,Wsd }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5f_pp_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3200] // VMAXSS Vss,Hss,Wss + (const void *)&gInstructions[ 3241] // VMAXSS Vss,Hss,Wss }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5f_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3192] // VMAXPD Vpd,Hpd,Wpd + (const void *)&gInstructions[ 3233] // VMAXPD Vpd,Hpd,Wpd }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5f_pp_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3195] // VMAXPS Vps,Hps,Wps + (const void *)&gInstructions[ 3236] // VMAXPS Vps,Hps,Wps }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_5f_pp = @@ -11144,25 +12422,25 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_5f_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5e_pp_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2876] // VDIVSD Vsd,Hsd,Wsd + (const void *)&gInstructions[ 2917] // VDIVSD Vsd,Hsd,Wsd }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5e_pp_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2879] // VDIVSS Vss,Hss,Wss + (const void *)&gInstructions[ 2920] // VDIVSS Vss,Hss,Wss }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5e_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2871] // VDIVPD Vpd,Hpd,Wpd + (const void *)&gInstructions[ 2912] // VDIVPD Vpd,Hpd,Wpd }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5e_pp_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2874] // VDIVPS Vps,Hps,Wps + (const void *)&gInstructions[ 2915] // VDIVPS Vps,Hps,Wps }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_5e_pp = @@ -11179,25 +12457,25 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_5e_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5d_pp_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3220] // VMINSD Vsd,Hsd,Wsd + (const void *)&gInstructions[ 3261] // VMINSD Vsd,Hsd,Wsd }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5d_pp_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3223] // VMINSS Vss,Hss,Wss + (const void *)&gInstructions[ 3264] // VMINSS Vss,Hss,Wss }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5d_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3215] // VMINPD Vpd,Hpd,Wpd + (const void *)&gInstructions[ 3256] // VMINPD Vpd,Hpd,Wpd }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5d_pp_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3218] // VMINPS Vps,Hps,Wps + (const void *)&gInstructions[ 3259] // VMINPS Vps,Hps,Wps }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_5d_pp = @@ -11214,25 +12492,25 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_5d_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5c_pp_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4023] // VSUBSD Vsd,Hsd,Wsd + (const void *)&gInstructions[ 4070] // VSUBSD Vsd,Hsd,Wsd }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5c_pp_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4026] // VSUBSS Vss,Hss,Wss + (const void *)&gInstructions[ 4073] // VSUBSS Vss,Hss,Wss }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5c_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4018] // VSUBPD Vpd,Hpd,Wpd + (const void *)&gInstructions[ 4065] // VSUBPD Vpd,Hpd,Wpd }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5c_pp_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4021] // VSUBPS Vps,Hps,Wps + (const void *)&gInstructions[ 4068] // VSUBPS Vps,Hps,Wps }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_5c_pp = @@ -11249,19 +12527,19 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_5c_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5b_pp_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2834] // VCVTTPS2DQ Vps,Wps + (const void *)&gInstructions[ 2875] // VCVTTPS2DQ Vps,Wps }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5b_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2776] // VCVTPS2DQ Vps,Wps + (const void *)&gInstructions[ 2817] // VCVTPS2DQ Vps,Wps }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5b_pp_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2734] // VCVTDQ2PS Vps,Wps + (const void *)&gInstructions[ 2775] // VCVTDQ2PS Vps,Wps }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_5b_pp = @@ -11278,25 +12556,25 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_5b_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5a_pp_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2796] // VCVTSD2SS Vss,Hx,Wsd + (const void *)&gInstructions[ 2837] // VCVTSD2SS Vss,Hx,Wsd }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5a_pp_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2809] // VCVTSS2SD Vsd,Hx,Wss + (const void *)&gInstructions[ 2850] // VCVTSS2SD Vsd,Hx,Wss }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5a_pp_01_l_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2758] // VCVTPD2PS Vdq,Wqq + (const void *)&gInstructions[ 2799] // VCVTPD2PS Vdq,Wqq }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5a_pp_01_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2757] // VCVTPD2PS Vdq,Wdq + (const void *)&gInstructions[ 2798] // VCVTPD2PS Vdq,Wdq }; const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_5a_pp_01_l = @@ -11313,13 +12591,13 @@ const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_5a_pp_01_l = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5a_pp_00_l_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2781] // VCVTPS2PD Vqq,Wdq + (const void *)&gInstructions[ 2822] // VCVTPS2PD Vqq,Wdq }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5a_pp_00_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2780] // VCVTPS2PD Vpd,Wq + (const void *)&gInstructions[ 2821] // VCVTPS2PD Vpd,Wq }; const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_5a_pp_00_l = @@ -11347,25 +12625,25 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_5a_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_59_pp_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3354] // VMULSD Vsd,Hsd,Wsd + (const void *)&gInstructions[ 3399] // VMULSD Vsd,Hsd,Wsd }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_59_pp_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3357] // VMULSS Vss,Hss,Wss + (const void *)&gInstructions[ 3402] // VMULSS Vss,Hss,Wss }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_59_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3349] // VMULPD Vpd,Hpd,Wpd + (const void *)&gInstructions[ 3394] // VMULPD Vpd,Hpd,Wpd }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_59_pp_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3352] // VMULPS Vps,Hps,Wps + (const void *)&gInstructions[ 3397] // VMULPS Vps,Hps,Wps }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_59_pp = @@ -11382,25 +12660,25 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_59_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_58_pp_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2652] // VADDSD Vsd,Hsd,Wsd + (const void *)&gInstructions[ 2693] // VADDSD Vsd,Hsd,Wsd }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_58_pp_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2655] // VADDSS Vss,Hss,Wss + (const void *)&gInstructions[ 2696] // VADDSS Vss,Hss,Wss }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_58_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2647] // VADDPD Vpd,Hpd,Wpd + (const void *)&gInstructions[ 2688] // VADDPD Vpd,Hpd,Wpd }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_58_pp_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2650] // VADDPS Vps,Hps,Wps + (const void *)&gInstructions[ 2691] // VADDPS Vps,Hps,Wps }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_58_pp = @@ -11417,13 +12695,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_58_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_57_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4046] // VXORPD Vpd,Hpd,Wpd + (const void *)&gInstructions[ 4093] // VXORPD Vpd,Hpd,Wpd }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_57_pp_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4048] // VXORPS Vps,Hps,Wps + (const void *)&gInstructions[ 4095] // VXORPS Vps,Hps,Wps }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_57_pp = @@ -11440,13 +12718,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_57_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_56_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3362] // VORPD Vpd,Hpd,Wpd + (const void *)&gInstructions[ 3407] // VORPD Vpd,Hpd,Wpd }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_56_pp_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3364] // VORPS Vps,Hps,Wps + (const void *)&gInstructions[ 3409] // VORPS Vps,Hps,Wps }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_56_pp = @@ -11463,13 +12741,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_56_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_55_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2671] // VANDNPD Vpd,Hpd,Wpd + (const void *)&gInstructions[ 2712] // VANDNPD Vpd,Hpd,Wpd }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_55_pp_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2673] // VANDNPS Vps,Hps,Wps + (const void *)&gInstructions[ 2714] // VANDNPS Vps,Hps,Wps }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_55_pp = @@ -11486,13 +12764,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_55_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_54_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2675] // VANDPD Vpd,Hpd,Wpd + (const void *)&gInstructions[ 2716] // VANDPD Vpd,Hpd,Wpd }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_54_pp_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2677] // VANDPS Vps,Hps,Wps + (const void *)&gInstructions[ 2718] // VANDPS Vps,Hps,Wps }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_54_pp = @@ -11509,13 +12787,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_54_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_53_pp_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3937] // VRCPSS Vss,Hss,Wss + (const void *)&gInstructions[ 3982] // VRCPSS Vss,Hss,Wss }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_53_pp_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3935] // VRCPPS Vps,Wps + (const void *)&gInstructions[ 3980] // VRCPPS Vps,Wps }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_53_pp = @@ -11532,13 +12810,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_53_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_52_pp_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3968] // VRSQRTSS Vss,Hss,Wss + (const void *)&gInstructions[ 4013] // VRSQRTSS Vss,Hss,Wss }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_52_pp_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3966] // VRSQRTPS Vx,Wx + (const void *)&gInstructions[ 4011] // VRSQRTPS Vx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_52_pp = @@ -11555,25 +12833,25 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_52_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_51_pp_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4011] // VSQRTSD Vsd,Hsd,Wsd + (const void *)&gInstructions[ 4058] // VSQRTSD Vsd,Hsd,Wsd }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_51_pp_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4014] // VSQRTSS Vss,Hss,Wss + (const void *)&gInstructions[ 4061] // VSQRTSS Vss,Hss,Wss }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_51_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4006] // VSQRTPD Vx,Wx + (const void *)&gInstructions[ 4053] // VSQRTPD Vx,Wx }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_51_pp_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4009] // VSQRTPS Vx,Wx + (const void *)&gInstructions[ 4056] // VSQRTPS Vx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_51_pp = @@ -11590,7 +12868,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_51_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_50_pp_01_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3283] // VMOVMSKPD Gy,Ux + (const void *)&gInstructions[ 3324] // VMOVMSKPD Gy,Ux }; const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_50_pp_01_modrmmod = @@ -11605,7 +12883,7 @@ const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_50_pp_01_modrmmod = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_50_pp_00_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3284] // VMOVMSKPS Gy,Ux + (const void *)&gInstructions[ 3325] // VMOVMSKPS Gy,Ux }; const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_50_pp_00_modrmmod = @@ -12461,13 +13739,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_41_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_2f_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2714] // VCOMISD Vsd,Wsd + (const void *)&gInstructions[ 2755] // VCOMISD Vsd,Wsd }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_2f_pp_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2717] // VCOMISS Vss,Wss + (const void *)&gInstructions[ 2758] // VCOMISS Vss,Wss }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_2f_pp = @@ -12484,13 +13762,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_2f_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_2e_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4030] // VUCOMISD Vsd,Wsd + (const void *)&gInstructions[ 4077] // VUCOMISD Vsd,Wsd }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_2e_pp_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4033] // VUCOMISS Vss,Wss + (const void *)&gInstructions[ 4080] // VUCOMISS Vss,Wss }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_2e_pp = @@ -12507,13 +13785,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_2e_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_2d_pp_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2794] // VCVTSD2SI Gy,Wsd + (const void *)&gInstructions[ 2835] // VCVTSD2SI Gy,Wsd }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_2d_pp_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2812] // VCVTSS2SI Gy,Wss + (const void *)&gInstructions[ 2853] // VCVTSS2SI Gy,Wss }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_2d_pp = @@ -12530,13 +13808,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_2d_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_2c_pp_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2845] // VCVTTSD2SI Gy,Wsd + (const void *)&gInstructions[ 2886] // VCVTTSD2SI Gy,Wsd }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_2c_pp_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2852] // VCVTTSS2SI Gy,Wss + (const void *)&gInstructions[ 2893] // VCVTTSS2SI Gy,Wss }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_2c_pp = @@ -12553,7 +13831,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_2c_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_2b_pp_01_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3290] // VMOVNTPD Mx,Vx + (const void *)&gInstructions[ 3331] // VMOVNTPD Mx,Vx }; const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_2b_pp_01_modrmmod = @@ -12568,7 +13846,7 @@ const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_2b_pp_01_modrmmod = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_2b_pp_00_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3292] // VMOVNTPS Mx,Vx + (const void *)&gInstructions[ 3333] // VMOVNTPS Mx,Vx }; const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_2b_pp_00_modrmmod = @@ -12594,13 +13872,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_2b_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_2a_pp_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2804] // VCVTSI2SD Vsd,Hsd,Ey + (const void *)&gInstructions[ 2845] // VCVTSI2SD Vsd,Hsd,Ey }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_2a_pp_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2807] // VCVTSI2SS Vss,Hss,Ey + (const void *)&gInstructions[ 2848] // VCVTSI2SS Vss,Hss,Ey }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_2a_pp = @@ -12617,13 +13895,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_2a_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_29_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3231] // VMOVAPD Wx,Vx + (const void *)&gInstructions[ 3272] // VMOVAPD Wx,Vx }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_29_pp_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3235] // VMOVAPS Wx,Vx + (const void *)&gInstructions[ 3276] // VMOVAPS Wx,Vx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_29_pp = @@ -12640,13 +13918,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_29_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_28_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3230] // VMOVAPD Vx,Wx + (const void *)&gInstructions[ 3271] // VMOVAPD Vx,Wx }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_28_pp_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3234] // VMOVAPS Vx,Wx + (const void *)&gInstructions[ 3275] // VMOVAPS Vx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_28_pp = @@ -12663,7 +13941,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_28_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_17_pp_01_modrmmod_00_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3268] // VMOVHPD Mq,Vdq + (const void *)&gInstructions[ 3309] // VMOVHPD Mq,Vdq }; const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_17_pp_01_modrmmod_00_l = @@ -12689,7 +13967,7 @@ const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_17_pp_01_modrmmod = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_17_pp_00_modrmmod_00_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3272] // VMOVHPS Mq,Vdq + (const void *)&gInstructions[ 3313] // VMOVHPS Mq,Vdq }; const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_17_pp_00_modrmmod_00_l = @@ -12726,13 +14004,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_17_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_16_pp_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3314] // VMOVSHDUP Vx,Wx + (const void *)&gInstructions[ 3359] // VMOVSHDUP Vx,Wx }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_16_pp_01_modrmmod_00_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3267] // VMOVHPD Vdq,Hdq,Mq + (const void *)&gInstructions[ 3308] // VMOVHPD Vdq,Hdq,Mq }; const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_16_pp_01_modrmmod_00_l = @@ -12758,7 +14036,7 @@ const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_16_pp_01_modrmmod = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_16_pp_00_modrmmod_01_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3274] // VMOVLHPS Vdq,Hdq,Udq + (const void *)&gInstructions[ 3315] // VMOVLHPS Vdq,Hdq,Udq }; const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_16_pp_00_modrmmod_01_l = @@ -12775,7 +14053,7 @@ const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_16_pp_00_modrmmod_01_l = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_16_pp_00_modrmmod_00_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3271] // VMOVHPS Vdq,Hdq,Mq + (const void *)&gInstructions[ 3312] // VMOVHPS Vdq,Hdq,Mq }; const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_16_pp_00_modrmmod_00_l = @@ -12812,13 +14090,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_16_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_15_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4038] // VUNPCKHPD Vx,Hx,Wx + (const void *)&gInstructions[ 4085] // VUNPCKHPD Vx,Hx,Wx }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_15_pp_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4040] // VUNPCKHPS Vx,Hx,Wx + (const void *)&gInstructions[ 4087] // VUNPCKHPS Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_15_pp = @@ -12835,13 +14113,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_15_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_14_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4042] // VUNPCKLPD Vx,Hx,Wx + (const void *)&gInstructions[ 4089] // VUNPCKLPD Vx,Hx,Wx }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_14_pp_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4044] // VUNPCKLPS Vx,Hx,Wx + (const void *)&gInstructions[ 4091] // VUNPCKLPS Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_14_pp = @@ -12858,7 +14136,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_14_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_13_pp_01_modrmmod_00_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3278] // VMOVLPD Mq,Vdq + (const void *)&gInstructions[ 3319] // VMOVLPD Mq,Vdq }; const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_13_pp_01_modrmmod_00_l = @@ -12884,7 +14162,7 @@ const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_13_pp_01_modrmmod = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_13_pp_00_modrmmod_00_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3282] // VMOVLPS Mq,Vdq + (const void *)&gInstructions[ 3323] // VMOVLPS Mq,Vdq }; const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_13_pp_00_modrmmod_00_l = @@ -12921,13 +14199,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_13_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_12_pp_03_l_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3246] // VMOVDDUP Vqq,Wqq + (const void *)&gInstructions[ 3287] // VMOVDDUP Vqq,Wqq }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_12_pp_03_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3245] // VMOVDDUP Vdq,Wq + (const void *)&gInstructions[ 3286] // VMOVDDUP Vdq,Wq }; const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_12_pp_03_l = @@ -12944,13 +14222,13 @@ const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_12_pp_03_l = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_12_pp_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3316] // VMOVSLDUP Vx,Wx + (const void *)&gInstructions[ 3361] // VMOVSLDUP Vx,Wx }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_12_pp_01_modrmmod_00_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3277] // VMOVLPD Vdq,Hdq,Mq + (const void *)&gInstructions[ 3318] // VMOVLPD Vdq,Hdq,Mq }; const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_12_pp_01_modrmmod_00_l = @@ -12976,7 +14254,7 @@ const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_12_pp_01_modrmmod = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_12_pp_00_modrmmod_01_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3264] // VMOVHLPS Vdq,Hdq,Udq + (const void *)&gInstructions[ 3305] // VMOVHLPS Vdq,Hdq,Udq }; const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_12_pp_00_modrmmod_01_l = @@ -12993,7 +14271,7 @@ const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_12_pp_00_modrmmod_01_l = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_12_pp_00_modrmmod_00_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3281] // VMOVLPS Vdq,Hdq,Mq + (const void *)&gInstructions[ 3322] // VMOVLPS Vdq,Hdq,Mq }; const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_12_pp_00_modrmmod_00_l = @@ -13030,13 +14308,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_12_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_11_pp_03_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3307] // VMOVSD Usd,Hsd,Vsd + (const void *)&gInstructions[ 3352] // VMOVSD Usd,Hsd,Vsd }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_11_pp_03_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3308] // VMOVSD Mq,Vsd + (const void *)&gInstructions[ 3353] // VMOVSD Mq,Vsd }; const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_11_pp_03_modrmmod = @@ -13051,13 +14329,13 @@ const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_11_pp_03_modrmmod = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_11_pp_02_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3323] // VMOVSS Uss,Hss,Vss + (const void *)&gInstructions[ 3368] // VMOVSS Uss,Hss,Vss }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_11_pp_02_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3324] // VMOVSS Md,Vss + (const void *)&gInstructions[ 3369] // VMOVSS Md,Vss }; const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_11_pp_02_modrmmod = @@ -13072,13 +14350,13 @@ const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_11_pp_02_modrmmod = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_11_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3328] // VMOVUPD Wx,Vx + (const void *)&gInstructions[ 3373] // VMOVUPD Wx,Vx }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_11_pp_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3332] // VMOVUPS Wx,Vx + (const void *)&gInstructions[ 3377] // VMOVUPS Wx,Vx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_11_pp = @@ -13095,13 +14373,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_11_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_10_pp_03_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3305] // VMOVSD Vdq,Hdq,Usd + (const void *)&gInstructions[ 3350] // VMOVSD Vdq,Hdq,Usd }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_10_pp_03_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3306] // VMOVSD Vdq,Mq + (const void *)&gInstructions[ 3351] // VMOVSD Vdq,Mq }; const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_10_pp_03_modrmmod = @@ -13116,13 +14394,13 @@ const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_10_pp_03_modrmmod = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_10_pp_02_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3321] // VMOVSS Vdq,Hdq,Uss + (const void *)&gInstructions[ 3366] // VMOVSS Vdq,Hdq,Uss }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_10_pp_02_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3322] // VMOVSS Vdq,Md + (const void *)&gInstructions[ 3367] // VMOVSS Vdq,Md }; const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_10_pp_02_modrmmod = @@ -13137,13 +14415,13 @@ const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_10_pp_02_modrmmod = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_10_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3327] // VMOVUPD Vx,Wx + (const void *)&gInstructions[ 3372] // VMOVUPD Vx,Wx }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_10_pp_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3331] // VMOVUPS Vx,Wx + (const void *)&gInstructions[ 3376] // VMOVUPS Vx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_10_pp = @@ -13429,7 +14707,7 @@ const ND_TABLE_EX_M gVexMap_mmmmm = /* 02 */ (const void *)&gVexMap_mmmmm_02_opcode, /* 03 */ (const void *)&gVexMap_mmmmm_03_opcode, /* 04 */ (const void *)ND_NULL, - /* 05 */ (const void *)ND_NULL, + /* 05 */ (const void *)&gVexMap_mmmmm_05_opcode, /* 06 */ (const void *)ND_NULL, /* 07 */ (const void *)&gVexMap_mmmmm_07_opcode, /* 08 */ (const void *)ND_NULL, diff --git a/bddisasm/include/bdx86_table_xop.h b/bddisasm/include/bdx86_table_xop.h index ba3e011..80445c8 100644 --- a/bddisasm/include/bdx86_table_xop.h +++ b/bddisasm/include/bdx86_table_xop.h @@ -309,103 +309,103 @@ const ND_TABLE_OPCODE gXopMap_mmmmm_0a_opcode = const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_e3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3599] // VPHSUBDQ Vdq,Wdq + (const void *)&gInstructions[ 3644] // VPHSUBDQ Vdq,Wdq }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_e2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3602] // VPHSUBWD Vdq,Wdq + (const void *)&gInstructions[ 3647] // VPHSUBWD Vdq,Wdq }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_e1_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3597] // VPHSUBBW Vdq,Wdq + (const void *)&gInstructions[ 3642] // VPHSUBBW Vdq,Wdq }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_db_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3590] // VPHADDUDQ Vdq,Wdq + (const void *)&gInstructions[ 3635] // VPHADDUDQ Vdq,Wdq }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_d7_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3592] // VPHADDUWQ Vdq,Wdq + (const void *)&gInstructions[ 3637] // VPHADDUWQ Vdq,Wdq }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_d6_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3591] // VPHADDUWD Vdq,Wdq + (const void *)&gInstructions[ 3636] // VPHADDUWD Vdq,Wdq }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_d3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3588] // VPHADDUBQ Vdq,Wdq + (const void *)&gInstructions[ 3633] // VPHADDUBQ Vdq,Wdq }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_d2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3587] // VPHADDUBD Vdq,Wdq + (const void *)&gInstructions[ 3632] // VPHADDUBD Vdq,Wdq }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_d1_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3589] // VPHADDUBW Vdq,Wdq + (const void *)&gInstructions[ 3634] // VPHADDUBW Vdq,Wdq }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_cb_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3585] // VPHADDDQ Vdq,Wdq + (const void *)&gInstructions[ 3630] // VPHADDDQ Vdq,Wdq }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_c7_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3595] // VPHADDWQ Vdq,Wdq + (const void *)&gInstructions[ 3640] // VPHADDWQ Vdq,Wdq }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_c6_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3594] // VPHADDWD Vdq,Wdq + (const void *)&gInstructions[ 3639] // VPHADDWD Vdq,Wdq }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_c3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3582] // VPHADDBQ Vdq,Wdq + (const void *)&gInstructions[ 3627] // VPHADDBQ Vdq,Wdq }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_c2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3581] // VPHADDBD Vdq,Wdq + (const void *)&gInstructions[ 3626] // VPHADDBD Vdq,Wdq }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_c1_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3583] // VPHADDBW Vdq,Wdq + (const void *)&gInstructions[ 3628] // VPHADDBW Vdq,Wdq }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_9b_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3788] // VPSHAQ Vdq,Hdq,Wdq + (const void *)&gInstructions[ 3833] // VPSHAQ Vdq,Hdq,Wdq }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_9b_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3787] // VPSHAQ Vdq,Wdq,Hdq + (const void *)&gInstructions[ 3832] // VPSHAQ Vdq,Wdq,Hdq }; const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_9b_w = @@ -420,13 +420,13 @@ const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_9b_w = const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_9a_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3786] // VPSHAD Vdq,Hdq,Wdq + (const void *)&gInstructions[ 3831] // VPSHAD Vdq,Hdq,Wdq }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_9a_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3785] // VPSHAD Vdq,Wdq,Hdq + (const void *)&gInstructions[ 3830] // VPSHAD Vdq,Wdq,Hdq }; const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_9a_w = @@ -441,13 +441,13 @@ const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_9a_w = const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_99_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3790] // VPSHAW Vdq,Hdq,Wdq + (const void *)&gInstructions[ 3835] // VPSHAW Vdq,Hdq,Wdq }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_99_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3789] // VPSHAW Vdq,Wdq,Hdq + (const void *)&gInstructions[ 3834] // VPSHAW Vdq,Wdq,Hdq }; const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_99_w = @@ -462,13 +462,13 @@ const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_99_w = const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_98_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3784] // VPSHAB Vdq,Hdq,Wdq + (const void *)&gInstructions[ 3829] // VPSHAB Vdq,Hdq,Wdq }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_98_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3783] // VPSHAB Vdq,Wdq,Hdq + (const void *)&gInstructions[ 3828] // VPSHAB Vdq,Wdq,Hdq }; const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_98_w = @@ -483,13 +483,13 @@ const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_98_w = const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_97_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3803] // VPSHLQ Vdq,Hdq,Wdq + (const void *)&gInstructions[ 3848] // VPSHLQ Vdq,Hdq,Wdq }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_97_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3802] // VPSHLQ Vdq,Wdq,Hdq + (const void *)&gInstructions[ 3847] // VPSHLQ Vdq,Wdq,Hdq }; const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_97_w = @@ -504,13 +504,13 @@ const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_97_w = const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_96_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3794] // VPSHLB Vdq,Hdq,Wdq + (const void *)&gInstructions[ 3839] // VPSHLB Vdq,Hdq,Wdq }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_96_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3795] // VPSHLD Vdq,Wdq,Hdq + (const void *)&gInstructions[ 3840] // VPSHLD Vdq,Wdq,Hdq }; const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_96_w = @@ -525,13 +525,13 @@ const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_96_w = const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_95_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3793] // VPSHLB Vdq,Hdq,Wdq + (const void *)&gInstructions[ 3838] // VPSHLB Vdq,Hdq,Wdq }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_95_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3804] // VPSHLW Vdq,Wdq,Hdq + (const void *)&gInstructions[ 3849] // VPSHLW Vdq,Wdq,Hdq }; const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_95_w = @@ -546,13 +546,13 @@ const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_95_w = const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_94_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3792] // VPSHLB Vdq,Hdq,Wdq + (const void *)&gInstructions[ 3837] // VPSHLB Vdq,Hdq,Wdq }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_94_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3791] // VPSHLB Vdq,Wdq,Hdq + (const void *)&gInstructions[ 3836] // VPSHLB Vdq,Wdq,Hdq }; const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_94_w = @@ -567,13 +567,13 @@ const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_94_w = const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_93_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3773] // VPROTQ Vdq,Hdq,Wdq + (const void *)&gInstructions[ 3818] // VPROTQ Vdq,Hdq,Wdq }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_93_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3772] // VPROTQ Vdq,Wdq,Hdq + (const void *)&gInstructions[ 3817] // VPROTQ Vdq,Wdq,Hdq }; const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_93_w = @@ -588,13 +588,13 @@ const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_93_w = const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_92_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3770] // VPROTD Vdq,Hdq,Wdq + (const void *)&gInstructions[ 3815] // VPROTD Vdq,Hdq,Wdq }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_92_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3769] // VPROTD Vdq,Wdq,Hdq + (const void *)&gInstructions[ 3814] // VPROTD Vdq,Wdq,Hdq }; const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_92_w = @@ -609,13 +609,13 @@ const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_92_w = const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_91_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3776] // VPROTW Vdq,Hdq,Wdq + (const void *)&gInstructions[ 3821] // VPROTW Vdq,Hdq,Wdq }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_91_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3775] // VPROTW Vdq,Wdq,Hdq + (const void *)&gInstructions[ 3820] // VPROTW Vdq,Wdq,Hdq }; const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_91_w = @@ -630,13 +630,13 @@ const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_91_w = const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_90_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3767] // VPROTB Vdq,Hdq,Wdq + (const void *)&gInstructions[ 3812] // VPROTB Vdq,Hdq,Wdq }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_90_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3766] // VPROTB Vdq,Wdq,Hdq + (const void *)&gInstructions[ 3811] // VPROTB Vdq,Wdq,Hdq }; const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_90_w = @@ -651,31 +651,31 @@ const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_90_w = const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_83_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3127] // VFRCZSD Vdq,Wsd + (const void *)&gInstructions[ 3168] // VFRCZSD Vdq,Wsd }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_82_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3128] // VFRCZSS Vdq,Wss + (const void *)&gInstructions[ 3169] // VFRCZSS Vdq,Wss }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_81_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3125] // VFRCZPD Vx,Wx + (const void *)&gInstructions[ 3166] // VFRCZPD Vx,Wx }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_80_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3126] // VFRCZPS Vx,Wx + (const void *)&gInstructions[ 3167] // VFRCZPS Vx,Wx }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_12_modrmreg_01_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2496] // SLWPCB Ry + (const void *)&gInstructions[ 2502] // SLWPCB Ry }; const ND_TABLE_MODRM_MOD gXopMap_mmmmm_09_opcode_12_modrmreg_01_modrmmod = @@ -747,7 +747,7 @@ const ND_TABLE_MODRM_REG gXopMap_mmmmm_09_opcode_02_modrmreg = const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_01_modrmreg_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2586] // T1MSKC By,Ey + (const void *)&gInstructions[ 2592] // T1MSKC By,Ey }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_01_modrmreg_06_leaf = @@ -765,7 +765,7 @@ const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_01_modrmreg_05_leaf = const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_01_modrmreg_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2620] // TZMSK By,Ey + (const void *)&gInstructions[ 2661] // TZMSK By,Ey }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_01_modrmreg_03_leaf = @@ -1067,97 +1067,97 @@ const ND_TABLE_OPCODE gXopMap_mmmmm_09_opcode = const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_ef_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3474] // VPCOMUQ Vdq,Hdq,Wdq,Ib + (const void *)&gInstructions[ 3519] // VPCOMUQ Vdq,Hdq,Wdq,Ib }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_ee_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3473] // VPCOMUD Vdq,Hdq,Wdq,Ib + (const void *)&gInstructions[ 3518] // VPCOMUD Vdq,Hdq,Wdq,Ib }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_ed_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3475] // VPCOMUW Vdq,Hdq,Wdq,Ib + (const void *)&gInstructions[ 3520] // VPCOMUW Vdq,Hdq,Wdq,Ib }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_ec_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3472] // VPCOMUB Vdq,Hdq,Wdq,Ib + (const void *)&gInstructions[ 3517] // VPCOMUB Vdq,Hdq,Wdq,Ib }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_cf_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3471] // VPCOMQ Vdq,Hdq,Wdq,Ib + (const void *)&gInstructions[ 3516] // VPCOMQ Vdq,Hdq,Wdq,Ib }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_ce_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3466] // VPCOMD Vdq,Hdq,Wdq,Ib + (const void *)&gInstructions[ 3511] // VPCOMD Vdq,Hdq,Wdq,Ib }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_cd_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3476] // VPCOMW Vdq,Hdq,Wdq,Ib + (const void *)&gInstructions[ 3521] // VPCOMW Vdq,Hdq,Wdq,Ib }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_cc_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3465] // VPCOMB Vdq,Hdq,Wdq,Ib + (const void *)&gInstructions[ 3510] // VPCOMB Vdq,Hdq,Wdq,Ib }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_c3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3771] // VPROTQ Vdq,Wdq,Ib + (const void *)&gInstructions[ 3816] // VPROTQ Vdq,Wdq,Ib }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_c2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3768] // VPROTD Vdq,Wdq,Ib + (const void *)&gInstructions[ 3813] // VPROTD Vdq,Wdq,Ib }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_c1_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3774] // VPROTW Vdq,Wdq,Ib + (const void *)&gInstructions[ 3819] // VPROTW Vdq,Wdq,Ib }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_c0_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3765] // VPROTB Vdq,Wdq,Ib + (const void *)&gInstructions[ 3810] // VPROTB Vdq,Wdq,Ib }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_b6_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3628] // VPMADCSWD Vdq,Hdq,Wdq,Ldq + (const void *)&gInstructions[ 3673] // VPMADCSWD Vdq,Hdq,Wdq,Ldq }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_a6_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3627] // VPMADCSSWD Vdq,Hdq,Wdq,Ldq + (const void *)&gInstructions[ 3672] // VPMADCSSWD Vdq,Hdq,Wdq,Ldq }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_a3_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3756] // VPPERM Vx,Hx,Lx,Wx + (const void *)&gInstructions[ 3801] // VPPERM Vx,Hx,Lx,Wx }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_a3_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3755] // VPPERM Vx,Hx,Wx,Lx + (const void *)&gInstructions[ 3800] // VPPERM Vx,Hx,Wx,Lx }; const ND_TABLE_EX_W gXopMap_mmmmm_08_opcode_a3_w = @@ -1172,13 +1172,13 @@ const ND_TABLE_EX_W gXopMap_mmmmm_08_opcode_a3_w = const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_a2_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3436] // VPCMOV Vx,Hx,Lx,Wx + (const void *)&gInstructions[ 3481] // VPCMOV Vx,Hx,Lx,Wx }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_a2_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3435] // VPCMOV Vx,Hx,Wx,Lx + (const void *)&gInstructions[ 3480] // VPCMOV Vx,Hx,Wx,Lx }; const ND_TABLE_EX_W gXopMap_mmmmm_08_opcode_a2_w = @@ -1193,61 +1193,61 @@ const ND_TABLE_EX_W gXopMap_mmmmm_08_opcode_a2_w = const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_9f_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3618] // VPMACSDQH Vdq,Hdq,Wdq,Ldq + (const void *)&gInstructions[ 3663] // VPMACSDQH Vdq,Hdq,Wdq,Ldq }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_9e_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3617] // VPMACSDD Vdq,Hdq,Wdq,Ldq + (const void *)&gInstructions[ 3662] // VPMACSDD Vdq,Hdq,Wdq,Ldq }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_97_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3619] // VPMACSDQL Vdq,Hdq,Wdq,Ldq + (const void *)&gInstructions[ 3664] // VPMACSDQL Vdq,Hdq,Wdq,Ldq }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_96_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3625] // VPMACSWD Vdq,Hdq,Wdq,Ldq + (const void *)&gInstructions[ 3670] // VPMACSWD Vdq,Hdq,Wdq,Ldq }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_95_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3626] // VPMACSWW Vdq,Hdq,Wdq,Ldq + (const void *)&gInstructions[ 3671] // VPMACSWW Vdq,Hdq,Wdq,Ldq }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_8f_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3621] // VPMACSSDQH Vdq,Hdq,Wdq,Ldq + (const void *)&gInstructions[ 3666] // VPMACSSDQH Vdq,Hdq,Wdq,Ldq }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_8e_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3620] // VPMACSSDD Vdq,Hdq,Wdq,Ldq + (const void *)&gInstructions[ 3665] // VPMACSSDD Vdq,Hdq,Wdq,Ldq }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_87_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3622] // VPMACSSDQL Vdq,Hdq,Wdq,Ldq + (const void *)&gInstructions[ 3667] // VPMACSSDQL Vdq,Hdq,Wdq,Ldq }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_86_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3623] // VPMACSSWD Vdq,Hdq,Wdq,Ldq + (const void *)&gInstructions[ 3668] // VPMACSSWD Vdq,Hdq,Wdq,Ldq }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_85_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3624] // VPMACSSWW Vdq,Hdq,Wdq,Ldq + (const void *)&gInstructions[ 3669] // VPMACSSWW Vdq,Hdq,Wdq,Ldq }; const ND_TABLE_OPCODE gXopMap_mmmmm_08_opcode = diff --git a/bddisasm/include/bdx86_tabledefs.h b/bddisasm/include/bdx86_tabledefs.h index c1612ab..513b4c6 100644 --- a/bddisasm/include/bdx86_tabledefs.h +++ b/bddisasm/include/bdx86_tabledefs.h @@ -227,6 +227,7 @@ typedef struct _ND_IDBE ND_UINT8 ExcType; // SSE/VEX/EVEX/OPMASK/AMX/APX exception type. ND_UINT8 FpuFlags; // FPU status word C0, C1, C2 & C3 access type. ND_UINT8 EvexMode; // EVEX prefix extension type. + ND_UINT8 SimdExc; // SIMD Floating-Point Exceptions. // Per-flag access. Undefined flags will have their bit set in both the "Set" and "Cleared" mask, since a flag // cannot be both cleared and set. diff --git a/bddisasm_test/conf-x86.json b/bddisasm_test/conf-x86.json index f8df8f8..c92280b 100644 --- a/bddisasm_test/conf-x86.json +++ b/bddisasm_test/conf-x86.json @@ -705,5 +705,33 @@ "f_test": "x86/avx10/avx102_64.test", "options": "-b64", "command": "decode" + }, + { + "f_source": "x86/movrs/movrs_64.asm", + "f_result": "x86/movrs/movrs_64.result", + "f_test": "x86/movrs/movrs_64.test", + "options": "-b64", + "command": "decode" + }, + { + "f_source": "x86/movrs/vmovrs_64.asm", + "f_result": "x86/movrs/vmovrs_64.result", + "f_test": "x86/movrs/vmovrs_64.test", + "options": "-b64", + "command": "decode" + }, + { + "f_source": "x86/sm/sm4_evex_64.asm", + "f_result": "x86/sm/sm4_evex_64.result", + "f_test": "x86/sm/sm4_evex_64.test", + "options": "-b64", + "command": "decode" + }, + { + "f_source": "x86/amx/amx_evex_64.asm", + "f_result": "x86/amx/amx_evex_64.result", + "f_test": "x86/amx/amx_evex_64.test", + "options": "-b64", + "command": "decode" } ] \ No newline at end of file diff --git a/bddisasm_test/x86/amx/amx1_64.asm b/bddisasm_test/x86/amx/amx1_64.asm index 8a34afa..c650820 100644 --- a/bddisasm_test/x86/amx/amx1_64.asm +++ b/bddisasm_test/x86/amx/amx1_64.asm @@ -25,4 +25,30 @@ db 0xc4, 0xe2, 0x7b, 0x5C, 0xF4 ; TDPFP16PS tmm6, tmm4, tmm0 db 0xc4, 0xe2, 0x78, 0x6C, 0xF4 ; TCMMRLFP16PS tmm6, tmm4, tmm0 - db 0xc4, 0xe2, 0x79, 0x6C, 0xF4 ; TCMMIMFP16PS tmm6, tmm4, tmm \ No newline at end of file + db 0xc4, 0xe2, 0x79, 0x6C, 0xF4 ; TCMMIMFP16PS tmm6, tmm4, tmm + + db 0xc4, 0xe2, 0x78, 0x48, 0xcf ; TTMMULTF32PS tmm1, tmm7, tmm0 + db 0xc4, 0xe2, 0x79, 0x48, 0xcf ; TMMULTF32PS tmm1, tmm7, tmm0 + db 0xc4, 0xe2, 0x79, 0x4a, 0x04, 0x11 ; TILELOADDRST1 tmm0, [rcx+rdx] + db 0xc4, 0xe2, 0x7b, 0x4a, 0x04, 0x11 ; TILELOADDRS tmm0, [rcx+rdx] + db 0xc4, 0xe2, 0x7a, 0x5f, 0xcd ; TTRANSPOSED tmm1, tmm5 + db 0xc4, 0xe2, 0x78, 0x6b, 0xcd ; TCONJTCMMIMFP16PS tmm1, tmm5, tmm0 + db 0xc4, 0xe2, 0x78, 0x6b, 0xcd ; TCONJTCMMIMFP16PS tmm1, tmm5, tmm0 + db 0xc4, 0xe2, 0x79, 0x6b, 0xcd ; TCONJTFP16 tmm1, tmm5 + db 0xc4, 0xe2, 0x7a, 0x6b, 0xcd ; TTCMMRLFP16PS tmm1, tmm5, tmm0 + db 0xc4, 0xe2, 0x7b, 0x6b, 0xcd ; TTCMMIMFP16PS tmm1, tmm5, tmm0 + db 0xc4, 0xe2, 0x7a, 0x6c, 0xcd ; TTDPBF16PS tmm1, tmm5, tmm0 + db 0xc4, 0xe2, 0x7b, 0x6c, 0xcd ; TTDPFP16PS tmm1, tmm5, tmm0 + db 0xc4, 0xe2, 0x78, 0x6e, 0x04, 0x11 ; T2RPNTLVWZ0 tmm0+1, [rcx+rdx] + db 0xc4, 0xe2, 0x79, 0x6e, 0x04, 0x11 ; T2RPNTLVWZ1 tmm0+1, [rcx+rdx] + db 0xc4, 0xe2, 0x78, 0x6f, 0x04, 0x11 ; T2RPNTLVWZ0T1 tmm0+1, [rcx+rdx] + db 0xc4, 0xe2, 0x79, 0x6f, 0x04, 0x11 ; T2RPNTLVWZ1T1 tmm0+1, [rcx+rdx] + + db 0xc4, 0xe5, 0x78, 0xf8, 0x04, 0x11 ; T2RPNTLVWZ0RS tmm0+1, [rcx+rdx] + db 0xc4, 0xe5, 0x79, 0xf8, 0x04, 0x11 ; T2RPNTLVWZ1RS tmm0+1, [rcx+rdx] + db 0xc4, 0xe5, 0x78, 0xf9, 0x04, 0x11 ; T2RPNTLVWZ0RST1 tmm0+1, [rcx+rdx] + db 0xc4, 0xe5, 0x79, 0xf9, 0x04, 0x11 ; T2RPNTLVWZ1RST1 tmm0+1, [rcx+rdx] + db 0xc4, 0xe5, 0x78, 0xfd, 0xcd ; TDPBF8PS tmm1, tmm5, tmm0 + db 0xc4, 0xe5, 0x79, 0xfd, 0xcd ; TDPHF8PS tmm1, tmm5, tmm0 + db 0xc4, 0xe5, 0x7a, 0xfd, 0xcd ; TDPHBF8PS tmm1, tmm5, tmm0 + db 0xc4, 0xe5, 0x7b, 0xfd, 0xcd ; TDPBHF8PS tmm1, tmm5, tmm0 diff --git a/bddisasm_test/x86/amx/amx1_64.result b/bddisasm_test/x86/amx/amx1_64.result index 22cfa39..ab416ed 100644 --- a/bddisasm_test/x86/amx/amx1_64.result +++ b/bddisasm_test/x86/amx/amx1_64.result @@ -331,3 +331,433 @@ Operand: 1, Acc: R-, Type: Register, Size: 1024, RawSize: 1024, Encoding: M, RegType: Tile, RegSize: 1024, RegId: 4, RegCount: 1 Operand: 2, Acc: R-, Type: Register, Size: 1024, RawSize: 1024, Encoding: V, RegType: Tile, RegSize: 1024, RegId: 0, RegCount: 1 +0000000000000071 c4e27848cf TTMMULTF32PS tmm1, tmm7, tmm0 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: AMX-TRANSPOSE, Ins cat: AMX, CET tracked: no + CPUID leaf: 0x0000001e, sub-leaf: 0x00000001, reg: eax, bit: 5 + Exception class: AMX, exception type: AMX-E10 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: no, Compat: no, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: no, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1024, RawSize: 1024, Encoding: R, RegType: Tile, RegSize: 1024, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1024, RawSize: 1024, Encoding: M, RegType: Tile, RegSize: 1024, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1024, RawSize: 1024, Encoding: V, RegType: Tile, RegSize: 1024, RegId: 0, RegCount: 1 + +0000000000000076 c4e27948cf TMMULTF32PS tmm1, tmm7, tmm0 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: AMX-TF32, Ins cat: AMX, CET tracked: no + CPUID leaf: 0x0000001e, sub-leaf: 0x00000001, reg: eax, bit: 6 + Exception class: AMX, exception type: AMX-E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: no, Compat: no, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: no, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1024, RawSize: 1024, Encoding: R, RegType: Tile, RegSize: 1024, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1024, RawSize: 1024, Encoding: M, RegType: Tile, RegSize: 1024, RegId: 7, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1024, RawSize: 1024, Encoding: V, RegType: Tile, RegSize: 1024, RegId: 0, RegCount: 1 + +000000000000007B c4e2794a0411 TILELOADDRST1 tmm0, [rcx+rdx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: AMX-MOVRS, Ins cat: AMX, CET tracked: no + CPUID leaf: 0x0000001e, sub-leaf: 0x00000001, reg: eax, bit: 8 + Exception class: AMX, exception type: AMX-E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: no, Compat: no, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: no, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1024, RawSize: 1024, Encoding: R, RegType: Tile, RegSize: 1024, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1024, RawSize: 1024, Encoding: M, Sibmem Addressing: yes, + Segment: 3, Base: 1, Index: 2 * 1, + +0000000000000081 c4e27b4a0411 TILELOADDRS tmm0, [rcx+rdx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: AMX-MOVRS, Ins cat: AMX, CET tracked: no + CPUID leaf: 0x0000001e, sub-leaf: 0x00000001, reg: eax, bit: 8 + Exception class: AMX, exception type: AMX-E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: no, Compat: no, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: no, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1024, RawSize: 1024, Encoding: R, RegType: Tile, RegSize: 1024, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1024, RawSize: 1024, Encoding: M, Sibmem Addressing: yes, + Segment: 3, Base: 1, Index: 2 * 1, + +0000000000000087 c4e27a5fcd TTRANSPOSED tmm1, tmm5 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: AMX-TRANSPOSE, Ins cat: AMX, CET tracked: no + CPUID leaf: 0x0000001e, sub-leaf: 0x00000001, reg: eax, bit: 5 + Exception class: AMX, exception type: AMX-E9 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: no, Compat: no, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: no, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1024, RawSize: 1024, Encoding: R, RegType: Tile, RegSize: 1024, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1024, RawSize: 1024, Encoding: M, RegType: Tile, RegSize: 1024, RegId: 5, RegCount: 1 + +000000000000008C c4e2786bcd TCONJTCMMIMFP16PS tmm1, tmm5, tmm0 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: AMX-TRANSPOSE, Ins cat: AMX, CET tracked: no + CPUID leaf: 0x0000001e, sub-leaf: 0x00000001, reg: eax, bit: 5 + Exception class: AMX, exception type: AMX-E10 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: no, Compat: no, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: no, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1024, RawSize: 1024, Encoding: R, RegType: Tile, RegSize: 1024, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1024, RawSize: 1024, Encoding: M, RegType: Tile, RegSize: 1024, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1024, RawSize: 1024, Encoding: V, RegType: Tile, RegSize: 1024, RegId: 0, RegCount: 1 + +0000000000000091 c4e2786bcd TCONJTCMMIMFP16PS tmm1, tmm5, tmm0 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: AMX-TRANSPOSE, Ins cat: AMX, CET tracked: no + CPUID leaf: 0x0000001e, sub-leaf: 0x00000001, reg: eax, bit: 5 + Exception class: AMX, exception type: AMX-E10 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: no, Compat: no, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: no, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1024, RawSize: 1024, Encoding: R, RegType: Tile, RegSize: 1024, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1024, RawSize: 1024, Encoding: M, RegType: Tile, RegSize: 1024, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1024, RawSize: 1024, Encoding: V, RegType: Tile, RegSize: 1024, RegId: 0, RegCount: 1 + +0000000000000096 c4e2796bcd TCONJTFP16 tmm1, tmm5 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: AMX-TRANSPOSE, Ins cat: AMX, CET tracked: no + CPUID leaf: 0x0000001e, sub-leaf: 0x00000001, reg: eax, bit: 5 + Exception class: AMX, exception type: AMX-E9 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: no, Compat: no, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: no, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1024, RawSize: 1024, Encoding: R, RegType: Tile, RegSize: 1024, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1024, RawSize: 1024, Encoding: M, RegType: Tile, RegSize: 1024, RegId: 5, RegCount: 1 + +000000000000009B c4e27a6bcd TTCMMRLFP16PS tmm1, tmm5, tmm0 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: AMX-TRANSPOSE, Ins cat: AMX, CET tracked: no + CPUID leaf: 0x0000001e, sub-leaf: 0x00000001, reg: eax, bit: 5 + Exception class: AMX, exception type: AMX-E10 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: no, Compat: no, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: no, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1024, RawSize: 1024, Encoding: R, RegType: Tile, RegSize: 1024, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1024, RawSize: 1024, Encoding: M, RegType: Tile, RegSize: 1024, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1024, RawSize: 1024, Encoding: V, RegType: Tile, RegSize: 1024, RegId: 0, RegCount: 1 + +00000000000000A0 c4e27b6bcd TTCMMIMFP16PS tmm1, tmm5, tmm0 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: AMX-TRANSPOSE, Ins cat: AMX, CET tracked: no + CPUID leaf: 0x0000001e, sub-leaf: 0x00000001, reg: eax, bit: 5 + Exception class: AMX, exception type: AMX-E10 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: no, Compat: no, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: no, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1024, RawSize: 1024, Encoding: R, RegType: Tile, RegSize: 1024, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1024, RawSize: 1024, Encoding: M, RegType: Tile, RegSize: 1024, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1024, RawSize: 1024, Encoding: V, RegType: Tile, RegSize: 1024, RegId: 0, RegCount: 1 + +00000000000000A5 c4e27a6ccd TTDPBF16PS tmm1, tmm5, tmm0 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: AMX-TRANSPOSE, Ins cat: AMX, CET tracked: no + CPUID leaf: 0x0000001e, sub-leaf: 0x00000001, reg: eax, bit: 5 + Exception class: AMX, exception type: AMX-E10 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: no, Compat: no, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: no, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1024, RawSize: 1024, Encoding: R, RegType: Tile, RegSize: 1024, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1024, RawSize: 1024, Encoding: M, RegType: Tile, RegSize: 1024, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1024, RawSize: 1024, Encoding: V, RegType: Tile, RegSize: 1024, RegId: 0, RegCount: 1 + +00000000000000AA c4e27b6ccd TTDPFP16PS tmm1, tmm5, tmm0 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: AMX-TRANSPOSE, Ins cat: AMX, CET tracked: no + CPUID leaf: 0x0000001e, sub-leaf: 0x00000001, reg: eax, bit: 5 + Exception class: AMX, exception type: AMX-E10 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: no, Compat: no, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: no, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1024, RawSize: 1024, Encoding: R, RegType: Tile, RegSize: 1024, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1024, RawSize: 1024, Encoding: M, RegType: Tile, RegSize: 1024, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1024, RawSize: 1024, Encoding: V, RegType: Tile, RegSize: 1024, RegId: 0, RegCount: 1 + +00000000000000AF c4e2786e0411 T2RPNTLVWZ0 tmm0+1, [rcx+rdx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: AMX-TRANSPOSE, Ins cat: AMX, CET tracked: no + CPUID leaf: 0x0000001e, sub-leaf: 0x00000001, reg: eax, bit: 5 + Exception class: AMX, exception type: AMX-E11 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: no, Compat: no, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: no, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1024, RawSize: 1024, Encoding: R, RegType: Tile, RegSize: 1024, RegId: 0, RegCount: 2 + Operand: 1, Acc: R-, Type: Memory, Size: 1024, RawSize: 1024, Encoding: M, Sibmem Addressing: yes, + Segment: 3, Base: 1, Index: 2 * 1, + +00000000000000B5 c4e2796e0411 T2RPNTLVWZ1 tmm0+1, [rcx+rdx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: AMX-TRANSPOSE, Ins cat: AMX, CET tracked: no + CPUID leaf: 0x0000001e, sub-leaf: 0x00000001, reg: eax, bit: 5 + Exception class: AMX, exception type: AMX-E11 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: no, Compat: no, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: no, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1024, RawSize: 1024, Encoding: R, RegType: Tile, RegSize: 1024, RegId: 0, RegCount: 2 + Operand: 1, Acc: R-, Type: Memory, Size: 1024, RawSize: 1024, Encoding: M, Sibmem Addressing: yes, + Segment: 3, Base: 1, Index: 2 * 1, + +00000000000000BB c4e2786f0411 T2RPNTLVWZ0T1 tmm0+1, [rcx+rdx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: AMX-TRANSPOSE, Ins cat: AMX, CET tracked: no + CPUID leaf: 0x0000001e, sub-leaf: 0x00000001, reg: eax, bit: 5 + Exception class: AMX, exception type: AMX-E11 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: no, Compat: no, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: no, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1024, RawSize: 1024, Encoding: R, RegType: Tile, RegSize: 1024, RegId: 0, RegCount: 2 + Operand: 1, Acc: R-, Type: Memory, Size: 1024, RawSize: 1024, Encoding: M, Sibmem Addressing: yes, + Segment: 3, Base: 1, Index: 2 * 1, + +00000000000000C1 c4e2796f0411 T2RPNTLVWZ1T1 tmm0+1, [rcx+rdx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: AMX-TRANSPOSE, Ins cat: AMX, CET tracked: no + CPUID leaf: 0x0000001e, sub-leaf: 0x00000001, reg: eax, bit: 5 + Exception class: AMX, exception type: AMX-E11 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: no, Compat: no, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: no, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1024, RawSize: 1024, Encoding: R, RegType: Tile, RegSize: 1024, RegId: 0, RegCount: 2 + Operand: 1, Acc: R-, Type: Memory, Size: 1024, RawSize: 1024, Encoding: M, Sibmem Addressing: yes, + Segment: 3, Base: 1, Index: 2 * 1, + +00000000000000C7 c4e578f80411 T2RPNTLVWZ0RS tmm0+1, [rcx+rdx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: AMX-TRANSPOSE, Ins cat: AMX, CET tracked: no + CPUID leaf: 0x0000001e, sub-leaf: 0x00000001, reg: eax, bit: 5 + Exception class: AMX, exception type: AMX-E11 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: no, Compat: no, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: no, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1024, RawSize: 1024, Encoding: R, RegType: Tile, RegSize: 1024, RegId: 0, RegCount: 2 + Operand: 1, Acc: R-, Type: Memory, Size: 1024, RawSize: 1024, Encoding: M, Sibmem Addressing: yes, + Segment: 3, Base: 1, Index: 2 * 1, + +00000000000000CD c4e579f80411 T2RPNTLVWZ1RS tmm0+1, [rcx+rdx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: AMX-TRANSPOSE, Ins cat: AMX, CET tracked: no + CPUID leaf: 0x0000001e, sub-leaf: 0x00000001, reg: eax, bit: 5 + Exception class: AMX, exception type: AMX-E11 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: no, Compat: no, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: no, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1024, RawSize: 1024, Encoding: R, RegType: Tile, RegSize: 1024, RegId: 0, RegCount: 2 + Operand: 1, Acc: R-, Type: Memory, Size: 1024, RawSize: 1024, Encoding: M, Sibmem Addressing: yes, + Segment: 3, Base: 1, Index: 2 * 1, + +00000000000000D3 c4e578f90411 T2RPNTLVWZ0RST1 tmm0+1, [rcx+rdx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: AMX-TRANSPOSE, Ins cat: AMX, CET tracked: no + CPUID leaf: 0x0000001e, sub-leaf: 0x00000001, reg: eax, bit: 5 + Exception class: AMX, exception type: AMX-E11 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: no, Compat: no, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: no, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1024, RawSize: 1024, Encoding: R, RegType: Tile, RegSize: 1024, RegId: 0, RegCount: 2 + Operand: 1, Acc: R-, Type: Memory, Size: 1024, RawSize: 1024, Encoding: M, Sibmem Addressing: yes, + Segment: 3, Base: 1, Index: 2 * 1, + +00000000000000D9 c4e579f90411 T2RPNTLVWZ1RST1 tmm0+1, [rcx+rdx] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: AMX-TRANSPOSE, Ins cat: AMX, CET tracked: no + CPUID leaf: 0x0000001e, sub-leaf: 0x00000001, reg: eax, bit: 5 + Exception class: AMX, exception type: AMX-E11 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: no, Compat: no, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: no, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1024, RawSize: 1024, Encoding: R, RegType: Tile, RegSize: 1024, RegId: 0, RegCount: 2 + Operand: 1, Acc: R-, Type: Memory, Size: 1024, RawSize: 1024, Encoding: M, Sibmem Addressing: yes, + Segment: 3, Base: 1, Index: 2 * 1, + +00000000000000DF c4e578fdcd TDPBF8PS tmm1, tmm5, tmm0 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: AMX-FP8, Ins cat: AMX, CET tracked: no + CPUID leaf: 0x0000001e, sub-leaf: 0x00000001, reg: eax, bit: 4 + Exception class: AMX, exception type: AMX-E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: no, Compat: no, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: no, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1024, RawSize: 1024, Encoding: R, RegType: Tile, RegSize: 1024, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1024, RawSize: 1024, Encoding: M, RegType: Tile, RegSize: 1024, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1024, RawSize: 1024, Encoding: V, RegType: Tile, RegSize: 1024, RegId: 0, RegCount: 1 + +00000000000000E4 c4e579fdcd TDPHF8PS tmm1, tmm5, tmm0 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: AMX-FP8, Ins cat: AMX, CET tracked: no + CPUID leaf: 0x0000001e, sub-leaf: 0x00000001, reg: eax, bit: 4 + Exception class: AMX, exception type: AMX-E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: no, Compat: no, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: no, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1024, RawSize: 1024, Encoding: R, RegType: Tile, RegSize: 1024, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1024, RawSize: 1024, Encoding: M, RegType: Tile, RegSize: 1024, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1024, RawSize: 1024, Encoding: V, RegType: Tile, RegSize: 1024, RegId: 0, RegCount: 1 + +00000000000000E9 c4e57afdcd TDPHBF8PS tmm1, tmm5, tmm0 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: AMX-FP8, Ins cat: AMX, CET tracked: no + CPUID leaf: 0x0000001e, sub-leaf: 0x00000001, reg: eax, bit: 4 + Exception class: AMX, exception type: AMX-E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: no, Compat: no, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: no, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1024, RawSize: 1024, Encoding: R, RegType: Tile, RegSize: 1024, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1024, RawSize: 1024, Encoding: M, RegType: Tile, RegSize: 1024, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1024, RawSize: 1024, Encoding: V, RegType: Tile, RegSize: 1024, RegId: 0, RegCount: 1 + +00000000000000EE c4e57bfdcd TDPBHF8PS tmm1, tmm5, tmm0 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: AMX-FP8, Ins cat: AMX, CET tracked: no + CPUID leaf: 0x0000001e, sub-leaf: 0x00000001, reg: eax, bit: 4 + Exception class: AMX, exception type: AMX-E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: no, Compat: no, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: no, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1024, RawSize: 1024, Encoding: R, RegType: Tile, RegSize: 1024, RegId: 1, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1024, RawSize: 1024, Encoding: M, RegType: Tile, RegSize: 1024, RegId: 5, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1024, RawSize: 1024, Encoding: V, RegType: Tile, RegSize: 1024, RegId: 0, RegCount: 1 + diff --git a/bddisasm_test/x86/amx/amx1_64.test b/bddisasm_test/x86/amx/amx1_64.test index b6263131256456a8ea71a14a8648946b3719fc2c..e837b3dddcf8478116760c67b8cd344cb9679e55 100644 GIT binary patch literal 243 zcmX}ku?>ST5QSk17RXi*R*1*|prn0wZZlX4w-!5CVgm|NAm!eRh>K6Zee&gszRA^y z-?m&a21cADU57TtNxHP*)$s83EdLk!cMN{)QQA9mFG06NiEDd_vGjY1(R5-gCrLH4 Z2p;@n5>GW SimdExceptions { + SimdExceptions::from_raw(unsafe { self.inner.SimdExceptions.Raw }) + } + /// `EVEX` tuple type. /// /// # Panics diff --git a/bindings/rsbddisasm/bddisasm/src/decoder.rs b/bindings/rsbddisasm/bddisasm/src/decoder.rs index fefe531..8f228d2 100644 --- a/bindings/rsbddisasm/bddisasm/src/decoder.rs +++ b/bindings/rsbddisasm/bddisasm/src/decoder.rs @@ -23,7 +23,7 @@ impl<'a> Decoder<'a> { /// * `code` - An [`u8`] slice that holds the code to be decoded. /// * `mode` - The mode in which to decode the instruction. /// * `ip` - The instruction pointer value to use when formatting the decoded instruction. Does not affect the - /// decoding process in any way. + /// decoding process in any way. #[must_use] pub fn new(code: &'a [u8], mode: DecodeMode, ip: u64) -> Self { Self { @@ -39,7 +39,7 @@ impl<'a> Decoder<'a> { /// # Returns /// /// * `Some(DecodeResult)` - if there are still undecoded bytes in the given code chunk. The decoding may have - /// still failed. See `Remarks`. + /// still failed. See `Remarks`. /// * `None` - if all the bytes in the given code chunk were decoded. /// /// # Remarks diff --git a/bindings/rsbddisasm/bddisasm/src/fpu_flags.rs b/bindings/rsbddisasm/bddisasm/src/fpu_flags.rs index f0f24ef..f986318 100644 --- a/bindings/rsbddisasm/bddisasm/src/fpu_flags.rs +++ b/bindings/rsbddisasm/bddisasm/src/fpu_flags.rs @@ -52,10 +52,10 @@ pub struct FpuFlags { impl FpuFlags { pub(crate) fn from_raw(flags: ffi::ND_FPU_FLAGS) -> Result { Ok(Self { - c0: FpuFlagsAccess::from_raw(flags.C0())?, - c1: FpuFlagsAccess::from_raw(flags.C1())?, - c2: FpuFlagsAccess::from_raw(flags.C2())?, - c3: FpuFlagsAccess::from_raw(flags.C3())?, + c0: FpuFlagsAccess::from_raw(unsafe { flags.__bindgen_anon_1.C0() })?, + c1: FpuFlagsAccess::from_raw(unsafe { flags.__bindgen_anon_1.C1() })?, + c2: FpuFlagsAccess::from_raw(unsafe { flags.__bindgen_anon_1.C2() })?, + c3: FpuFlagsAccess::from_raw(unsafe { flags.__bindgen_anon_1.C3() })?, }) } } diff --git a/bindings/rsbddisasm/bddisasm/src/isa_set.rs b/bindings/rsbddisasm/bddisasm/src/isa_set.rs index a8a59ba..0f7e818 100644 --- a/bindings/rsbddisasm/bddisasm/src/isa_set.rs +++ b/bindings/rsbddisasm/bddisasm/src/isa_set.rs @@ -15,11 +15,16 @@ pub enum IsaSet { ADX, AES, AMD, + AMXAVX512, AMXBF16, AMXCOMPLEX, AMXFP16, + AMXFP8, AMXINT8, + AMXMOVRS, + AMXTF32, AMXTILE, + AMXTRANSPOSE, APX_F, AVX, AVX102, @@ -86,8 +91,10 @@ pub enum IsaSet { MOVBE, MOVDIR64B, MOVDIRI, + MOVRS, MPX, MSRLIST, + MSR_IMM, MWAITT, PAUSE, PCLMULQDQ, @@ -158,11 +165,16 @@ impl TryFrom for IsaSet { ffi::_ND_INS_SET::ND_SET_ADX => Ok(IsaSet::ADX), ffi::_ND_INS_SET::ND_SET_AES => Ok(IsaSet::AES), ffi::_ND_INS_SET::ND_SET_AMD => Ok(IsaSet::AMD), + ffi::_ND_INS_SET::ND_SET_AMXAVX512 => Ok(IsaSet::AMXAVX512), ffi::_ND_INS_SET::ND_SET_AMXBF16 => Ok(IsaSet::AMXBF16), ffi::_ND_INS_SET::ND_SET_AMXCOMPLEX => Ok(IsaSet::AMXCOMPLEX), ffi::_ND_INS_SET::ND_SET_AMXFP16 => Ok(IsaSet::AMXFP16), + ffi::_ND_INS_SET::ND_SET_AMXFP8 => Ok(IsaSet::AMXFP8), ffi::_ND_INS_SET::ND_SET_AMXINT8 => Ok(IsaSet::AMXINT8), + ffi::_ND_INS_SET::ND_SET_AMXMOVRS => Ok(IsaSet::AMXMOVRS), + ffi::_ND_INS_SET::ND_SET_AMXTF32 => Ok(IsaSet::AMXTF32), ffi::_ND_INS_SET::ND_SET_AMXTILE => Ok(IsaSet::AMXTILE), + ffi::_ND_INS_SET::ND_SET_AMXTRANSPOSE => Ok(IsaSet::AMXTRANSPOSE), ffi::_ND_INS_SET::ND_SET_APX_F => Ok(IsaSet::APX_F), ffi::_ND_INS_SET::ND_SET_AVX => Ok(IsaSet::AVX), ffi::_ND_INS_SET::ND_SET_AVX102 => Ok(IsaSet::AVX102), @@ -229,8 +241,10 @@ impl TryFrom for IsaSet { ffi::_ND_INS_SET::ND_SET_MOVBE => Ok(IsaSet::MOVBE), ffi::_ND_INS_SET::ND_SET_MOVDIR64B => Ok(IsaSet::MOVDIR64B), ffi::_ND_INS_SET::ND_SET_MOVDIRI => Ok(IsaSet::MOVDIRI), + ffi::_ND_INS_SET::ND_SET_MOVRS => Ok(IsaSet::MOVRS), ffi::_ND_INS_SET::ND_SET_MPX => Ok(IsaSet::MPX), ffi::_ND_INS_SET::ND_SET_MSRLIST => Ok(IsaSet::MSRLIST), + ffi::_ND_INS_SET::ND_SET_MSR_IMM => Ok(IsaSet::MSR_IMM), ffi::_ND_INS_SET::ND_SET_MWAITT => Ok(IsaSet::MWAITT), ffi::_ND_INS_SET::ND_SET_PAUSE => Ok(IsaSet::PAUSE), ffi::_ND_INS_SET::ND_SET_PCLMULQDQ => Ok(IsaSet::PCLMULQDQ), diff --git a/bindings/rsbddisasm/bddisasm/src/mnemonic.rs b/bindings/rsbddisasm/bddisasm/src/mnemonic.rs index db9fcad..2d29d4c 100644 --- a/bindings/rsbddisasm/bddisasm/src/mnemonic.rs +++ b/bindings/rsbddisasm/bddisasm/src/mnemonic.rs @@ -411,6 +411,7 @@ pub enum Mnemonic { MOVNTSS, MOVQ, MOVQ2DQ, + MOVRS, MOVS, MOVSD, MOVSHDUP, @@ -570,6 +571,7 @@ pub enum Mnemonic { PREFETCHIT1, PREFETCHM, PREFETCHNTA, + PREFETCHRST2, PREFETCHT0, PREFETCHT1, PREFETCHT2, @@ -720,24 +722,53 @@ pub enum Mnemonic { SYSEXIT, SYSRET, T1MSKC, + T2RPNTLVWZ0, + T2RPNTLVWZ0RS, + T2RPNTLVWZ0RST1, + T2RPNTLVWZ0T1, + T2RPNTLVWZ1, + T2RPNTLVWZ1RS, + T2RPNTLVWZ1RST1, + T2RPNTLVWZ1T1, TCMMIMFP16PS, TCMMRLFP16PS, + TCONJTCMMIMFP16PS, + TCONJTFP16, + TCVTROWD2PS, + TCVTROWPS2PBF16H, + TCVTROWPS2PBF16L, + TCVTROWPS2PHH, + TCVTROWPS2PHL, TDCALL, TDPBF16PS, + TDPBF8PS, + TDPBHF8PS, TDPBSSD, TDPBSUD, TDPBUSD, TDPBUUD, TDPFP16PS, + TDPHBF8PS, + TDPHF8PS, TEST, TESTUI, TILELOADD, + TILELOADDRS, + TILELOADDRST1, TILELOADDT1, + TILEMOVROW, TILERELEASE, TILESTORED, TILEZERO, TLBSYNC, + TMMULTF32PS, TPAUSE, + TTCMMIMFP16PS, + TTCMMRLFP16PS, + TTDPBF16PS, + TTDPFP16PS, + TTMMULTF32PS, + TTRANSPOSED, TZCNT, TZMSK, UCOMISD, @@ -1211,6 +1242,10 @@ pub enum Mnemonic { VMOVNTPD, VMOVNTPS, VMOVQ, + VMOVRSB, + VMOVRSD, + VMOVRSQ, + VMOVRSW, VMOVSD, VMOVSH, VMOVSHDUP, @@ -2134,6 +2169,7 @@ impl TryFrom for Mnemonic { ffi::_ND_INS_CLASS::ND_INS_MOVNTSS => Ok(Mnemonic::MOVNTSS), ffi::_ND_INS_CLASS::ND_INS_MOVQ => Ok(Mnemonic::MOVQ), ffi::_ND_INS_CLASS::ND_INS_MOVQ2DQ => Ok(Mnemonic::MOVQ2DQ), + ffi::_ND_INS_CLASS::ND_INS_MOVRS => Ok(Mnemonic::MOVRS), ffi::_ND_INS_CLASS::ND_INS_MOVS => Ok(Mnemonic::MOVS), ffi::_ND_INS_CLASS::ND_INS_MOVSD => Ok(Mnemonic::MOVSD), ffi::_ND_INS_CLASS::ND_INS_MOVSHDUP => Ok(Mnemonic::MOVSHDUP), @@ -2293,6 +2329,7 @@ impl TryFrom for Mnemonic { ffi::_ND_INS_CLASS::ND_INS_PREFETCHIT1 => Ok(Mnemonic::PREFETCHIT1), ffi::_ND_INS_CLASS::ND_INS_PREFETCHM => Ok(Mnemonic::PREFETCHM), ffi::_ND_INS_CLASS::ND_INS_PREFETCHNTA => Ok(Mnemonic::PREFETCHNTA), + ffi::_ND_INS_CLASS::ND_INS_PREFETCHRST2 => Ok(Mnemonic::PREFETCHRST2), ffi::_ND_INS_CLASS::ND_INS_PREFETCHT0 => Ok(Mnemonic::PREFETCHT0), ffi::_ND_INS_CLASS::ND_INS_PREFETCHT1 => Ok(Mnemonic::PREFETCHT1), ffi::_ND_INS_CLASS::ND_INS_PREFETCHT2 => Ok(Mnemonic::PREFETCHT2), @@ -2443,24 +2480,53 @@ impl TryFrom for Mnemonic { ffi::_ND_INS_CLASS::ND_INS_SYSEXIT => Ok(Mnemonic::SYSEXIT), ffi::_ND_INS_CLASS::ND_INS_SYSRET => Ok(Mnemonic::SYSRET), ffi::_ND_INS_CLASS::ND_INS_T1MSKC => Ok(Mnemonic::T1MSKC), + ffi::_ND_INS_CLASS::ND_INS_T2RPNTLVWZ0 => Ok(Mnemonic::T2RPNTLVWZ0), + ffi::_ND_INS_CLASS::ND_INS_T2RPNTLVWZ0RS => Ok(Mnemonic::T2RPNTLVWZ0RS), + ffi::_ND_INS_CLASS::ND_INS_T2RPNTLVWZ0RST1 => Ok(Mnemonic::T2RPNTLVWZ0RST1), + ffi::_ND_INS_CLASS::ND_INS_T2RPNTLVWZ0T1 => Ok(Mnemonic::T2RPNTLVWZ0T1), + ffi::_ND_INS_CLASS::ND_INS_T2RPNTLVWZ1 => Ok(Mnemonic::T2RPNTLVWZ1), + ffi::_ND_INS_CLASS::ND_INS_T2RPNTLVWZ1RS => Ok(Mnemonic::T2RPNTLVWZ1RS), + ffi::_ND_INS_CLASS::ND_INS_T2RPNTLVWZ1RST1 => Ok(Mnemonic::T2RPNTLVWZ1RST1), + ffi::_ND_INS_CLASS::ND_INS_T2RPNTLVWZ1T1 => Ok(Mnemonic::T2RPNTLVWZ1T1), ffi::_ND_INS_CLASS::ND_INS_TCMMIMFP16PS => Ok(Mnemonic::TCMMIMFP16PS), ffi::_ND_INS_CLASS::ND_INS_TCMMRLFP16PS => Ok(Mnemonic::TCMMRLFP16PS), + ffi::_ND_INS_CLASS::ND_INS_TCONJTCMMIMFP16PS => Ok(Mnemonic::TCONJTCMMIMFP16PS), + ffi::_ND_INS_CLASS::ND_INS_TCONJTFP16 => Ok(Mnemonic::TCONJTFP16), + ffi::_ND_INS_CLASS::ND_INS_TCVTROWD2PS => Ok(Mnemonic::TCVTROWD2PS), + ffi::_ND_INS_CLASS::ND_INS_TCVTROWPS2PBF16H => Ok(Mnemonic::TCVTROWPS2PBF16H), + ffi::_ND_INS_CLASS::ND_INS_TCVTROWPS2PBF16L => Ok(Mnemonic::TCVTROWPS2PBF16L), + ffi::_ND_INS_CLASS::ND_INS_TCVTROWPS2PHH => Ok(Mnemonic::TCVTROWPS2PHH), + ffi::_ND_INS_CLASS::ND_INS_TCVTROWPS2PHL => Ok(Mnemonic::TCVTROWPS2PHL), ffi::_ND_INS_CLASS::ND_INS_TDCALL => Ok(Mnemonic::TDCALL), ffi::_ND_INS_CLASS::ND_INS_TDPBF16PS => Ok(Mnemonic::TDPBF16PS), + ffi::_ND_INS_CLASS::ND_INS_TDPBF8PS => Ok(Mnemonic::TDPBF8PS), + ffi::_ND_INS_CLASS::ND_INS_TDPBHF8PS => Ok(Mnemonic::TDPBHF8PS), ffi::_ND_INS_CLASS::ND_INS_TDPBSSD => Ok(Mnemonic::TDPBSSD), ffi::_ND_INS_CLASS::ND_INS_TDPBSUD => Ok(Mnemonic::TDPBSUD), ffi::_ND_INS_CLASS::ND_INS_TDPBUSD => Ok(Mnemonic::TDPBUSD), ffi::_ND_INS_CLASS::ND_INS_TDPBUUD => Ok(Mnemonic::TDPBUUD), ffi::_ND_INS_CLASS::ND_INS_TDPFP16PS => Ok(Mnemonic::TDPFP16PS), + ffi::_ND_INS_CLASS::ND_INS_TDPHBF8PS => Ok(Mnemonic::TDPHBF8PS), + ffi::_ND_INS_CLASS::ND_INS_TDPHF8PS => Ok(Mnemonic::TDPHF8PS), ffi::_ND_INS_CLASS::ND_INS_TEST => Ok(Mnemonic::TEST), ffi::_ND_INS_CLASS::ND_INS_TESTUI => Ok(Mnemonic::TESTUI), ffi::_ND_INS_CLASS::ND_INS_TILELOADD => Ok(Mnemonic::TILELOADD), + ffi::_ND_INS_CLASS::ND_INS_TILELOADDRS => Ok(Mnemonic::TILELOADDRS), + ffi::_ND_INS_CLASS::ND_INS_TILELOADDRST1 => Ok(Mnemonic::TILELOADDRST1), ffi::_ND_INS_CLASS::ND_INS_TILELOADDT1 => Ok(Mnemonic::TILELOADDT1), + ffi::_ND_INS_CLASS::ND_INS_TILEMOVROW => Ok(Mnemonic::TILEMOVROW), ffi::_ND_INS_CLASS::ND_INS_TILERELEASE => Ok(Mnemonic::TILERELEASE), ffi::_ND_INS_CLASS::ND_INS_TILESTORED => Ok(Mnemonic::TILESTORED), ffi::_ND_INS_CLASS::ND_INS_TILEZERO => Ok(Mnemonic::TILEZERO), ffi::_ND_INS_CLASS::ND_INS_TLBSYNC => Ok(Mnemonic::TLBSYNC), + ffi::_ND_INS_CLASS::ND_INS_TMMULTF32PS => Ok(Mnemonic::TMMULTF32PS), ffi::_ND_INS_CLASS::ND_INS_TPAUSE => Ok(Mnemonic::TPAUSE), + ffi::_ND_INS_CLASS::ND_INS_TTCMMIMFP16PS => Ok(Mnemonic::TTCMMIMFP16PS), + ffi::_ND_INS_CLASS::ND_INS_TTCMMRLFP16PS => Ok(Mnemonic::TTCMMRLFP16PS), + ffi::_ND_INS_CLASS::ND_INS_TTDPBF16PS => Ok(Mnemonic::TTDPBF16PS), + ffi::_ND_INS_CLASS::ND_INS_TTDPFP16PS => Ok(Mnemonic::TTDPFP16PS), + ffi::_ND_INS_CLASS::ND_INS_TTMMULTF32PS => Ok(Mnemonic::TTMMULTF32PS), + ffi::_ND_INS_CLASS::ND_INS_TTRANSPOSED => Ok(Mnemonic::TTRANSPOSED), ffi::_ND_INS_CLASS::ND_INS_TZCNT => Ok(Mnemonic::TZCNT), ffi::_ND_INS_CLASS::ND_INS_TZMSK => Ok(Mnemonic::TZMSK), ffi::_ND_INS_CLASS::ND_INS_UCOMISD => Ok(Mnemonic::UCOMISD), @@ -2934,6 +3000,10 @@ impl TryFrom for Mnemonic { ffi::_ND_INS_CLASS::ND_INS_VMOVNTPD => Ok(Mnemonic::VMOVNTPD), ffi::_ND_INS_CLASS::ND_INS_VMOVNTPS => Ok(Mnemonic::VMOVNTPS), ffi::_ND_INS_CLASS::ND_INS_VMOVQ => Ok(Mnemonic::VMOVQ), + ffi::_ND_INS_CLASS::ND_INS_VMOVRSB => Ok(Mnemonic::VMOVRSB), + ffi::_ND_INS_CLASS::ND_INS_VMOVRSD => Ok(Mnemonic::VMOVRSD), + ffi::_ND_INS_CLASS::ND_INS_VMOVRSQ => Ok(Mnemonic::VMOVRSQ), + ffi::_ND_INS_CLASS::ND_INS_VMOVRSW => Ok(Mnemonic::VMOVRSW), ffi::_ND_INS_CLASS::ND_INS_VMOVSD => Ok(Mnemonic::VMOVSD), ffi::_ND_INS_CLASS::ND_INS_VMOVSH => Ok(Mnemonic::VMOVSH), ffi::_ND_INS_CLASS::ND_INS_VMOVSHDUP => Ok(Mnemonic::VMOVSHDUP), diff --git a/bindings/rsbddisasm/bddisasm/src/operand.rs b/bindings/rsbddisasm/bddisasm/src/operand.rs index 446750b..9f5f89c 100644 --- a/bindings/rsbddisasm/bddisasm/src/operand.rs +++ b/bindings/rsbddisasm/bddisasm/src/operand.rs @@ -906,7 +906,7 @@ impl<'a> OperandsLookup<'a> { /// # Arguments /// /// * `index` - The index of the destination operand. First destination operand has index 0, the second one has - /// index 1, etc. + /// index 1, etc. /// /// # Returns /// @@ -936,7 +936,7 @@ impl<'a> OperandsLookup<'a> { /// # Arguments /// /// * `index` - The index of the source operand. First source operand has index 0, the second one has - /// index 1, etc. + /// index 1, etc. /// /// # Returns /// diff --git a/disasmtool/disasmtool.c b/disasmtool/disasmtool.c index 6299468..6e3e723 100644 --- a/disasmtool/disasmtool.c +++ b/disasmtool/disasmtool.c @@ -188,9 +188,14 @@ set_to_string( case ND_SET_AMD: return "AMD"; case ND_SET_AMXBF16: return "AMX-BF16"; case ND_SET_AMXFP16: return "AMX-FP16"; + case ND_SET_AMXFP8: return "AMX-FP8"; case ND_SET_AMXINT8: return "AMX-INT8"; case ND_SET_AMXTILE: return "AMX-TILE"; case ND_SET_AMXCOMPLEX: return "AMX-COMPLEX"; + case ND_SET_AMXTF32: return "AMX-TF32"; + case ND_SET_AMXAVX512: return "AMX-AVX512"; + case ND_SET_AMXMOVRS: return "AMX-MOVRS"; + case ND_SET_AMXTRANSPOSE: return "AMX-TRANSPOSE"; case ND_SET_AVX: return "AVX"; case ND_SET_AVX102: return "AVX10_2"; case ND_SET_AVX2: return "AVX2"; @@ -256,8 +261,10 @@ set_to_string( case ND_SET_MOVBE: return "MOVBE"; case ND_SET_MOVDIR64B: return "MOVDIR64B"; case ND_SET_MOVDIRI: return "MOVDIRI"; + case ND_SET_MOVRS: return "MOVRS"; case ND_SET_MPX: return "MPX"; case ND_SET_MSRLIST: return "MSRLIST"; + case ND_SET_MSR_IMM: return "MSR_IMM"; case ND_SET_MWAITT: return "MWAITT"; case ND_SET_PAUSE: return "PAUSE"; case ND_SET_PCLMULQDQ: return "PCLMULQDQ"; @@ -609,10 +616,20 @@ exception_type_to_string( case ND_EXT_AMX_E4: return "AMX-E4"; case ND_EXT_AMX_E5: return "AMX-E5"; case ND_EXT_AMX_E6: return "AMX-E6"; + case ND_EXT_AMX_E7: return "AMX-E7"; + case ND_EXT_AMX_E8: return "AMX-E8"; + case ND_EXT_AMX_E9: return "AMX-E9"; + case ND_EXT_AMX_E10: return "AMX-E10"; + case ND_EXT_AMX_E11: return "AMX-E11"; case ND_EXT_AMX_EVEX_E1: return "AMX-EVEX-E1"; case ND_EXT_AMX_EVEX_E2: return "AMX-EVEX-E2"; case ND_EXT_AMX_EVEX_E3: return "AMX-EVEX-E3"; + case ND_EXT_AMX_EVEX_E4: return "AMX-EVEX-E4"; + case ND_EXT_AMX_EVEX_E5: return "AMX-EVEX-E5"; + case ND_EXT_AMX_EVEX_E6: return "AMX-EVEX-E6"; + case ND_EXT_AMX_EVEX_E7: return "AMX-EVEX-E7"; + case ND_EXT_AMX_EVEX_E8: return "AMX-EVEX-E8"; case ND_EXT_APX_EVEX_BMI: return "APX-EVEX-BMI"; case ND_EXT_APX_EVEX_CCMP: return "APX-EVEX-CCMP"; @@ -865,12 +882,23 @@ print_instruction( Instrux->ExceptionType >= ND_EXT_1 && Instrux->ExceptionType <= ND_EXT_14 ? "SSE/VEX" : Instrux->ExceptionType >= ND_EXT_E1 && Instrux->ExceptionType <= ND_EXT_E12NP ? "EVEX" : Instrux->ExceptionType >= ND_EXT_K20 && Instrux->ExceptionType <= ND_EXT_K21 ? "Opmask" : - Instrux->ExceptionType >= ND_EXT_AMX_E1 && Instrux->ExceptionType <= ND_EXT_AMX_E6 ? "AMX" : + Instrux->ExceptionType >= ND_EXT_AMX_E1 && Instrux->ExceptionType <= ND_EXT_AMX_E11 ? "AMX" : Instrux->ExceptionType >= ND_EXT_AMX_EVEX_E1 && Instrux->ExceptionType <= ND_EXT_APX_EVEX_USER_MSR ? "APX" : "???"); printf("exception type: %s\n", exception_type_to_string(Instrux->ExceptionType)); } + if (Instrux->SimdExceptions.Raw != 0) + { + printf(" SIMD Exceptions: %s%s%s%s%s%s\n", + Instrux->SimdExceptions.IE ? "I" : "", + Instrux->SimdExceptions.DE ? "D" : "", + Instrux->SimdExceptions.ZE ? "Z" : "", + Instrux->SimdExceptions.OE ? "O" : "", + Instrux->SimdExceptions.UE ? "U" : "", + Instrux->SimdExceptions.PE ? "P" : ""); + } + if (Instrux->RflAccess != 0) { DWORD fidx, all; diff --git a/inc/bddisasm_version.h b/inc/bddisasm_version.h index 4792f5f..2963b8e 100644 --- a/inc/bddisasm_version.h +++ b/inc/bddisasm_version.h @@ -6,7 +6,7 @@ #define BDDISASM_VERSION_H #define DISASM_VERSION_MAJOR 2 -#define DISASM_VERSION_MINOR 2 +#define DISASM_VERSION_MINOR 3 #define DISASM_VERSION_REVISION 0 #define SHEMU_VERSION_MAJOR DISASM_VERSION_MAJOR diff --git a/inc/bdx86_constants.h b/inc/bdx86_constants.h index 0ccea56..4c94b4c 100644 --- a/inc/bdx86_constants.h +++ b/inc/bdx86_constants.h @@ -414,6 +414,7 @@ typedef enum _ND_INS_CLASS ND_INS_MOVNTSS, ND_INS_MOVQ, ND_INS_MOVQ2DQ, + ND_INS_MOVRS, ND_INS_MOVS, ND_INS_MOVSD, ND_INS_MOVSHDUP, @@ -573,6 +574,7 @@ typedef enum _ND_INS_CLASS ND_INS_PREFETCHIT1, ND_INS_PREFETCHM, ND_INS_PREFETCHNTA, + ND_INS_PREFETCHRST2, ND_INS_PREFETCHT0, ND_INS_PREFETCHT1, ND_INS_PREFETCHT2, @@ -723,24 +725,53 @@ typedef enum _ND_INS_CLASS ND_INS_SYSEXIT, ND_INS_SYSRET, ND_INS_T1MSKC, + ND_INS_T2RPNTLVWZ0, + ND_INS_T2RPNTLVWZ0RS, + ND_INS_T2RPNTLVWZ0RST1, + ND_INS_T2RPNTLVWZ0T1, + ND_INS_T2RPNTLVWZ1, + ND_INS_T2RPNTLVWZ1RS, + ND_INS_T2RPNTLVWZ1RST1, + ND_INS_T2RPNTLVWZ1T1, ND_INS_TCMMIMFP16PS, ND_INS_TCMMRLFP16PS, + ND_INS_TCONJTCMMIMFP16PS, + ND_INS_TCONJTFP16, + ND_INS_TCVTROWD2PS, + ND_INS_TCVTROWPS2PBF16H, + ND_INS_TCVTROWPS2PBF16L, + ND_INS_TCVTROWPS2PHH, + ND_INS_TCVTROWPS2PHL, ND_INS_TDCALL, ND_INS_TDPBF16PS, + ND_INS_TDPBF8PS, + ND_INS_TDPBHF8PS, ND_INS_TDPBSSD, ND_INS_TDPBSUD, ND_INS_TDPBUSD, ND_INS_TDPBUUD, ND_INS_TDPFP16PS, + ND_INS_TDPHBF8PS, + ND_INS_TDPHF8PS, ND_INS_TEST, ND_INS_TESTUI, ND_INS_TILELOADD, + ND_INS_TILELOADDRS, + ND_INS_TILELOADDRST1, ND_INS_TILELOADDT1, + ND_INS_TILEMOVROW, ND_INS_TILERELEASE, ND_INS_TILESTORED, ND_INS_TILEZERO, ND_INS_TLBSYNC, + ND_INS_TMMULTF32PS, ND_INS_TPAUSE, + ND_INS_TTCMMIMFP16PS, + ND_INS_TTCMMRLFP16PS, + ND_INS_TTDPBF16PS, + ND_INS_TTDPFP16PS, + ND_INS_TTMMULTF32PS, + ND_INS_TTRANSPOSED, ND_INS_TZCNT, ND_INS_TZMSK, ND_INS_UCOMISD, @@ -1214,6 +1245,10 @@ typedef enum _ND_INS_CLASS ND_INS_VMOVNTPD, ND_INS_VMOVNTPS, ND_INS_VMOVQ, + ND_INS_VMOVRSB, + ND_INS_VMOVRSD, + ND_INS_VMOVRSQ, + ND_INS_VMOVRSW, ND_INS_VMOVSD, ND_INS_VMOVSH, ND_INS_VMOVSHDUP, @@ -1738,11 +1773,16 @@ typedef enum _ND_INS_SET ND_SET_ADX, ND_SET_AES, ND_SET_AMD, + ND_SET_AMXAVX512, ND_SET_AMXBF16, ND_SET_AMXCOMPLEX, ND_SET_AMXFP16, + ND_SET_AMXFP8, ND_SET_AMXINT8, + ND_SET_AMXMOVRS, + ND_SET_AMXTF32, ND_SET_AMXTILE, + ND_SET_AMXTRANSPOSE, ND_SET_APX_F, ND_SET_AVX, ND_SET_AVX102, @@ -1809,8 +1849,10 @@ typedef enum _ND_INS_SET ND_SET_MOVBE, ND_SET_MOVDIR64B, ND_SET_MOVDIRI, + ND_SET_MOVRS, ND_SET_MPX, ND_SET_MSRLIST, + ND_SET_MSR_IMM, ND_SET_MWAITT, ND_SET_PAUSE, ND_SET_PCLMULQDQ, diff --git a/inc/bdx86_core.h b/inc/bdx86_core.h index 9887298..80ff235 100644 --- a/inc/bdx86_core.h +++ b/inc/bdx86_core.h @@ -627,11 +627,21 @@ typedef enum _ND_EX_TYPE ND_EXT_AMX_E4, ND_EXT_AMX_E5, ND_EXT_AMX_E6, + ND_EXT_AMX_E7, + ND_EXT_AMX_E8, + ND_EXT_AMX_E9, + ND_EXT_AMX_E10, + ND_EXT_AMX_E11, // AMX-EVEX exceptions. ND_EXT_AMX_EVEX_E1, ND_EXT_AMX_EVEX_E2, ND_EXT_AMX_EVEX_E3, + ND_EXT_AMX_EVEX_E4, + ND_EXT_AMX_EVEX_E5, + ND_EXT_AMX_EVEX_E6, + ND_EXT_AMX_EVEX_E7, + ND_EXT_AMX_EVEX_E8, // APX-EVEX exceptions. ND_EXT_APX_EVEX_BMI, @@ -1195,15 +1205,45 @@ typedef union _ND_RFLAGS // // FPU status flags. Each status flag can be one of ND_FPU_FLAG*. // -typedef struct _ND_FPU_FLAGS +typedef union _ND_FPU_FLAGS { - ND_UINT8 C0 : 2; // C0 flag access mode. See ND_FPU_FLAG_*. - ND_UINT8 C1 : 2; // C1 flag access mode. See ND_FPU_FLAG_*. - ND_UINT8 C2 : 2; // C2 flag access mode. See ND_FPU_FLAG_*. - ND_UINT8 C3 : 2; // C3 flag access mode. See ND_FPU_FLAG_*. + ND_UINT8 Raw; + struct + { + ND_UINT8 C0 : 2; // C0 flag access mode. See ND_FPU_FLAG_*. + ND_UINT8 C1 : 2; // C1 flag access mode. See ND_FPU_FLAG_*. + ND_UINT8 C2 : 2; // C2 flag access mode. See ND_FPU_FLAG_*. + ND_UINT8 C3 : 2; // C3 flag access mode. See ND_FPU_FLAG_*. + }; } ND_FPU_FLAGS, *PND_FPU_FLAGS; +#define ND_SIMD_EXC_IE 0x01 // Invalid Operation Exception. +#define ND_SIMD_EXC_DE 0x02 // Denormal Exception. +#define ND_SIMD_EXC_ZE 0x04 // Divide-by-Zero Exception. +#define ND_SIMD_EXC_OE 0x08 // Overflow Exception. +#define ND_SIMD_EXC_UE 0x10 // Underflow Exception. +#define ND_SIMD_EXC_PE 0x20 // Precision Exception. + +// +// SIMD Floating-Point Exceptions. These values are the same as lower 6 bits in MXCSR. The Raw field +// is a combination of ND_SIMD_EXC_* values, and is the same as the invidiual bitfields. +// +typedef union _ND_SIMD_EXCEPTIONS +{ + ND_UINT8 Raw; + struct + { + ND_UINT8 IE : 1; // Invalid Operation Exception. + ND_UINT8 DE : 1; // Denormal Exception. + ND_UINT8 ZE : 1; // Divide-by-Zero Exception. + ND_UINT8 OE : 1; // Overflow Exception. + ND_UINT8 UE : 1; // Underflow Exception. + ND_UINT8 PE : 1; // Precision Exception. + }; +} ND_SIMD_EXCEPTIONS; + + // // Branch information. // @@ -1392,7 +1432,8 @@ typedef struct _INSTRUX // implicit operands such as stack, flags, etc. ND_OPERAND Operands[ND_MAX_OPERAND]; // Instruction operands. - // EVEX information. + // SIMD/EVEX information. + ND_SIMD_EXCEPTIONS SimdExceptions; // SIMD Floating-Point Exceptions. Valid only for SIMD instructions! ND_UINT8 ExceptionType; // Exception type. One of ND_EX_TYPE. ND_UINT8 TupleType; // EVEX tuple type, if EVEX. One of ND_TUPLE. @@ -1466,6 +1507,13 @@ typedef struct _ND_CONTEXT /// CsAccess, RipAccess, RflAccess, StackAcces, MemoryAccess, BranchInfo. #define ND_OPTION_ONLY_EXPLICIT_OPERANDS 0x00000001 +// Do NOT zero the output INSTRUX structure before decoding this instruction. Use this option only if the +// output INSTRUX structure is already zeroed (for example, as is the case when allocating it with calloc). +// Make sure to NOT use this option when making succesive decode calls on the same buffer - this option +// should only be used when decoding an instruction in an output buffer that has just been allocated and +// has been 0-initialized, or if the caller explictly zeroed it before each decode call. +#define ND_OPTION_SKIP_ZERO_INSTRUX 0x00000002 + // // Operands access map. Contains every register except for MSR & XCR, includes memory, flags, RIP, stack. diff --git a/inc/bdx86_cpuidflags.h b/inc/bdx86_cpuidflags.h index 6d653a8..77d6e86 100644 --- a/inc/bdx86_cpuidflags.h +++ b/inc/bdx86_cpuidflags.h @@ -107,7 +107,9 @@ #define ND_CFF_HRESET ND_CFF(0x00000007, 0x00000001, NDR_EAX, 22) #define ND_CFF_AVXIFMA ND_CFF(0x00000007, 0x00000001, NDR_EAX, 23) #define ND_CFF_MSRLIST ND_CFF(0x00000007, 0x00000001, NDR_EAX, 27) +#define ND_CFF_MOVRS ND_CFF(0x00000007, 0x00000001, NDR_EAX, 31) #define ND_CFF_TSE ND_CFF(0x00000007, 0x00000001, NDR_EBX, 1) +#define ND_CFF_MSR_IMM ND_CFF(0x00000007, 0x00000001, NDR_ECX, 5) #define ND_CFF_AVXVNNIINT8 ND_CFF(0x00000007, 0x00000001, NDR_EDX, 4) #define ND_CFF_AVXNECONVERT ND_CFF(0x00000007, 0x00000001, NDR_EDX, 5) #define ND_CFF_AMXCOMPLEX ND_CFF(0x00000007, 0x00000001, NDR_EDX, 8) @@ -119,6 +121,11 @@ #define ND_CFF_XSAVEC ND_CFF(0x0000000D, 0x00000001, NDR_EAX, 1) #define ND_CFF_XSAVES ND_CFF(0x0000000D, 0x00000001, NDR_EAX, 3) #define ND_CFF_PTWRITE ND_CFF(0x00000014, 0x00000000, NDR_EBX, 4) +#define ND_CFF_AMXFP8 ND_CFF(0x0000001E, 0x00000001, NDR_EAX, 4) +#define ND_CFF_AMXTRANSPOSE ND_CFF(0x0000001E, 0x00000001, NDR_EAX, 5) +#define ND_CFF_AMXTF32 ND_CFF(0x0000001E, 0x00000001, NDR_EAX, 6) +#define ND_CFF_AMXAVX512 ND_CFF(0x0000001E, 0x00000001, NDR_EAX, 7) +#define ND_CFF_AMXMOVRS ND_CFF(0x0000001E, 0x00000001, NDR_EAX, 8) #define ND_CFF_SVM ND_CFF(0x80000001, 0xFFFFFFFF, NDR_ECX, 2) #define ND_CFF_LZCNT ND_CFF(0x80000001, 0xFFFFFFFF, NDR_ECX, 5) #define ND_CFF_SSE4A ND_CFF(0x80000001, 0xFFFFFFFF, NDR_ECX, 6) diff --git a/isagenerator/disasmlib.py b/isagenerator/disasmlib.py index ec45542..2053e62 100644 --- a/isagenerator/disasmlib.py +++ b/isagenerator/disasmlib.py @@ -543,6 +543,16 @@ 'cond', # EVEX extension for conditional instructons ] +# Valid SIMD Floating-Point Exceptions. +valid_simd_exceptions = [ + 'IE', # Invalid Operation Exception. + 'DE', # Denormal Exception. + 'ZE', # Divide-by-Zero Exception. + 'OE', # Overflow Exception. + 'UE', # Underflow Exception. + 'PE', # Precision Exception. +] + # Use one of these value to indicate absent operands. absent_op = ['n/a', ''] @@ -752,6 +762,9 @@ class Instruction(): FpuFlags: list[str] FPU flags access mode (example: ['u', 'u', 'u', 'u']). A list of 4 str elements, each one indicating the access mode for flag Cx, where x is the position in the list. + SimdExc: list[str] + SIMD Floating-Point Exceptions (MXCSR flags affected) by the instruction (example: ['IE', 'OE', 'UE']). + A list of strings, each string indicating if that particular SIMD exception is raised (or MXCSR flag). Modes: list[str] Valid operating modes for the indicated instruction. Encoding: dict @@ -847,6 +860,7 @@ def process_meta(self): self.EvexMode = None self.Rflags = {'m': [], 't': [], '0': [], '1': [], 'u': []} self.FpuFlags = ['u', 'u', 'u', 'u'] + self.SimdExc = [] self.Modes = valid_cpu_modes.copy() for y in self.RawMeta: @@ -988,6 +1002,12 @@ def process_meta(self): (m, ','.join(valid_cpu_modes))) self.Modes = modes + elif token == "x": + for e in value.split('|'): + if e not in valid_simd_exceptions: + raise InvalidSpecificationException("Unknown SIMDexception '%s', expecting one of [%s]" % + (e, ','.join(valid_simd_exceptions))) + self.SimdExc.append(e) else: raise InvalidSpecificationException("Unknown token specified: %s" % token) @@ -1203,6 +1223,7 @@ def parse_entry( 10. 'f': flags access ('m': modified, 't': tested, 'u': undefined, '0': cleared, '1': set to 1) 11. 'u': FPU flags access 12. 'm': valid operating modes + 13. 'x': SIMD exceptions/MXCSR flags Raises ------ diff --git a/isagenerator/generate_tables.py b/isagenerator/generate_tables.py index 2d27ec6..86356a1 100644 --- a/isagenerator/generate_tables.py +++ b/isagenerator/generate_tables.py @@ -266,6 +266,12 @@ def instrux_to_idbe( else: d['EvexMode'] = '0' + # SIMD Floating-Point Exceptions. + if ins.SimdExc: + d['SimdExc'] = '|'.join(['ND_SIMD_EXC_' + x for x in ins.SimdExc]) + else: + d['SimdExc'] = '0' + # Flags (tested, modified, set, cleared) for m in ['t', 'm', '1', '0']: flg = '0' @@ -362,6 +368,7 @@ def cdef_instruction( .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .SimdExc = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, @@ -390,6 +397,7 @@ def cdef_instruction( /* ExcType */ 0, /* FpuFlags */ 0, /* EvexMode */ 0, + /* SimdExc */ 0, /* TestedFlags */ 0, /* ModifiedFlags */ 0, /* SetFlags */ 0, diff --git a/isagenerator/instructions/cpuid.dat b/isagenerator/instructions/cpuid.dat index ac5c7c4..fe8ee10 100644 --- a/isagenerator/instructions/cpuid.dat +++ b/isagenerator/instructions/cpuid.dat @@ -94,7 +94,6 @@ AVX512FP16 : 0x00000007, 0x00000000, EDX, 23 AMXTILE : 0x00000007, 0x00000000, EDX, 24 AMXINT8 : 0x00000007, 0x00000000, EDX, 25 - SHA512 : 0x00000007, 0x00000001, EAX, 0 SM3 : 0x00000007, 0x00000001, EAX, 1 SM4 : 0x00000007, 0x00000001, EAX, 2 @@ -109,9 +108,9 @@ AMXFP16 : 0x00000007, 0x00000001, EAX, 21 HRESET : 0x00000007, 0x00000001, EAX, 22 AVXIFMA : 0x00000007, 0x00000001, EAX, 23 MSRLIST : 0x00000007, 0x00000001, EAX, 27 - +MOVRS : 0x00000007, 0x00000001, EAX, 31 TSE : 0x00000007, 0x00000001, EBX, 1 - +MSR_IMM : 0x00000007, 0x00000001, ECX, 5 AVXVNNIINT8 : 0x00000007, 0x00000001, EDX, 4 AVXNECONVERT : 0x00000007, 0x00000001, EDX, 5 AMXCOMPLEX : 0x00000007, 0x00000001, EDX, 8 @@ -129,6 +128,13 @@ XSAVES : 0x0000000D, 0x00000001, EAX, 3 PTWRITE : 0x00000014, 0x00000000, EBX, 4 +AMXFP8 : 0x0000001E, 0x00000001, EAX, 4 +AMXTRANSPOSE : 0x0000001E, 0x00000001, EAX, 5 +AMXTF32 : 0x0000001E, 0x00000001, EAX, 6 +AMXAVX512 : 0x0000001E, 0x00000001, EAX, 7 +AMXMOVRS : 0x0000001E, 0x00000001, EAX, 8 + + SVM : 0x80000001, 0xFFFFFFFF, ECX, 2 LZCNT : 0x80000001, 0xFFFFFFFF, ECX, 5 SSE4A : 0x80000001, 0xFFFFFFFF, ECX, 6 diff --git a/isagenerator/instructions/table_evex_1.dat b/isagenerator/instructions/table_evex_1.dat index a666502..ea52b98 100644 --- a/isagenerator/instructions/table_evex_1.dat +++ b/isagenerator/instructions/table_evex_1.dat @@ -41,29 +41,29 @@ VMOVAPS ; Vfv{K}{z},Wfv ; ; evex m:1 p:0 l:x w:0 VMOVAPD ; Vfv{K}{z},Wfv ; ; evex m:1 p:1 l:x w:1 0x28 /r ; s:AVX512F, t:DATAXFER, l:fvm, e:E1, w:W|R|R VMOVAPS ; Wfv{K}{z},Vfv ; ; evex m:1 p:0 l:x w:0 0x29 /r ; s:AVX512F, t:DATAXFER, l:fvm, e:E1, w:W|R|R VMOVAPD ; Wfv{K}{z},Vfv ; ; evex m:1 p:1 l:x w:1 0x29 /r ; s:AVX512F, t:DATAXFER, l:fvm, e:E1, w:W|R|R -VCVTSI2SS ; Vdq,Hdq{er},Ey ; ; evex m:1 p:2 l:i w:x 0x2A /r ; s:AVX512F, t:CONVERT, l:t1s, e:E3, w:W|R|R, a:IWO64 -VCVTSI2SD ; Vdq,Hdq,Ey ; ; evex m:1 p:3 l:i w:0 0x2A /r ; s:AVX512F, t:CONVERT, l:t1s, e:E10NF, w:W|R|R, a:IER|IWO64 -VCVTSI2SD ; Vdq,Hdq{er},Ey ; ; evex m:1 p:3 l:i w:1 0x2A /r ; s:AVX512F, t:CONVERT, l:t1s, e:E3, w:W|R|R, a:IWO64 +VCVTSI2SS ; Vdq,Hdq{er},Ey ; ; evex m:1 p:2 l:i w:x 0x2A /r ; s:AVX512F, t:CONVERT, l:t1s, e:E3, w:W|R|R, a:IWO64, x:PE +VCVTSI2SD ; Vdq,Hdq,Ey ; ; evex m:1 p:3 l:i w:0 0x2A /r ; s:AVX512F, t:CONVERT, l:t1s, e:E10NF, w:W|R|R, a:IER|IWO64, x:PE +VCVTSI2SD ; Vdq,Hdq{er},Ey ; ; evex m:1 p:3 l:i w:1 0x2A /r ; s:AVX512F, t:CONVERT, l:t1s, e:E3, w:W|R|R, a:IWO64, x:PE VMOVNTPS ; Mfv,Vfv ; ; evex m:1 p:0 l:x w:0 0x2B /r:mem ; s:AVX512F, t:DATAXFER, l:fvm, e:E1NF, w:W|R VMOVNTPD ; Mfv,Vfv ; ; evex m:1 p:1 l:x w:1 0x2B /r:mem ; s:AVX512F, t:DATAXFER, l:fvm, e:E1NF, w:W|R -VCVTTSS2SI ; Gy,Wss{sae} ; ; evex m:1 p:2 l:i w:x 0x2C /r ; s:AVX512F, t:CONVERT, l:t1f, e:E3, w:W|R, a:IWO64 -VCVTTSD2SI ; Gy,Wsd{sae} ; ; evex m:1 p:3 l:i w:x 0x2C /r ; s:AVX512F, t:CONVERT, l:t1f, e:E3, w:W|R, a:IWO64 -VCVTSS2SI ; Gy,Wss{er} ; ; evex m:1 p:2 l:i w:x 0x2D /r ; s:AVX512F, t:CONVERT, l:t1f, e:E3, w:W|R, a:IWO64 -VCVTSD2SI ; Gy,Wsd{er} ; ; evex m:1 p:3 l:i w:x 0x2D /r ; s:AVX512F, t:CONVERT, l:t1f, e:E3, w:W|R, a:IWO64 -VUCOMISS ; Vdq,Wss{sae} ; Fv ; evex m:1 p:0 l:i w:0 0x2E /r ; s:AVX512F, t:AVX512, l:t1s, w:R|R|W, e:E3, f:COMIS -VUCOMISD ; Vdq,Wsd{sae} ; Fv ; evex m:1 p:1 l:i w:1 0x2E /r ; s:AVX512F, t:AVX512, l:t1s, w:R|R|W, e:E3, f:COMIS -VUCOMXSD ; Vdq,Wsd{sae} ; Fv ; evex m:1 p:2 l:0 w:1 0x2E /r ; s:AVX102, t:AVX10CMPSFP, l:t1s, w:R|R|W, e:E3NF, f:CMPSFP -VUCOMXSS ; Vdq,Wss{sae} ; Fv ; evex m:1 p:3 l:0 w:0 0x2E /r ; s:AVX102, t:AVX10CMPSFP, l:t1s, w:R|R|W, e:E3NF, f:CMPSFP -VCOMISS ; Vdq,Wss{sae} ; Fv ; evex m:1 p:0 l:i w:0 0x2F /r ; s:AVX512F, t:AVX512, l:t1s, w:R|R|W, e:E3, f:COMIS -VCOMISD ; Vdq,Wsd{sae} ; Fv ; evex m:1 p:1 l:i w:1 0x2F /r ; s:AVX512F, t:AVX512, l:t1s, w:R|R|W, e:E3, f:COMIS -VCOMXSD ; Vdq,Wsd{sae} ; Fv ; evex m:1 p:2 l:0 w:1 0x2F /r ; s:AVX102, t:AVX10CMPSFP, l:t1s, w:R|R|W, e:E3NF, f:CMPSFP -VCOMXSS ; Vdq,Wss{sae} ; Fv ; evex m:1 p:3 l:0 w:0 0x2F /r ; s:AVX102, t:AVX10CMPSFP, l:t1s, w:R|R|W, e:E3NF, f:CMPSFP +VCVTTSS2SI ; Gy,Wss{sae} ; ; evex m:1 p:2 l:i w:x 0x2C /r ; s:AVX512F, t:CONVERT, l:t1f, e:E3, w:W|R, a:IWO64, x:IE|PE +VCVTTSD2SI ; Gy,Wsd{sae} ; ; evex m:1 p:3 l:i w:x 0x2C /r ; s:AVX512F, t:CONVERT, l:t1f, e:E3, w:W|R, a:IWO64, x:IE|PE +VCVTSS2SI ; Gy,Wss{er} ; ; evex m:1 p:2 l:i w:x 0x2D /r ; s:AVX512F, t:CONVERT, l:t1f, e:E3, w:W|R, a:IWO64, x:IE|PE +VCVTSD2SI ; Gy,Wsd{er} ; ; evex m:1 p:3 l:i w:x 0x2D /r ; s:AVX512F, t:CONVERT, l:t1f, e:E3, w:W|R, a:IWO64, x:IE|PE +VUCOMISS ; Vdq,Wss{sae} ; Fv ; evex m:1 p:0 l:i w:0 0x2E /r ; s:AVX512F, t:AVX512, l:t1s, w:R|R|W, e:E3, f:COMIS, x:IE|DE +VUCOMISD ; Vdq,Wsd{sae} ; Fv ; evex m:1 p:1 l:i w:1 0x2E /r ; s:AVX512F, t:AVX512, l:t1s, w:R|R|W, e:E3, f:COMIS, x:IE|DE +VUCOMXSS ; Vdq,Wss{sae} ; Fv ; evex m:1 p:2 l:i w:0 0x2E /r ; s:AVX102, t:AVX10CMPSFP, l:t1s, w:R|R|W, e:E3NF, f:CMPSFP, x:IE|DE +VUCOMXSD ; Vdq,Wsd{sae} ; Fv ; evex m:1 p:3 l:i w:1 0x2E /r ; s:AVX102, t:AVX10CMPSFP, l:t1s, w:R|R|W, e:E3NF, f:CMPSFP, x:IE|DE +VCOMISS ; Vdq,Wss{sae} ; Fv ; evex m:1 p:0 l:i w:0 0x2F /r ; s:AVX512F, t:AVX512, l:t1s, w:R|R|W, e:E3, f:COMIS, x:IE|DE +VCOMISD ; Vdq,Wsd{sae} ; Fv ; evex m:1 p:1 l:i w:1 0x2F /r ; s:AVX512F, t:AVX512, l:t1s, w:R|R|W, e:E3, f:COMIS, x:IE|DE +VCOMXSS ; Vdq,Wss{sae} ; Fv ; evex m:1 p:2 l:i w:0 0x2F /r ; s:AVX102, t:AVX10CMPSFP, l:t1s, w:R|R|W, e:E3NF, f:CMPSFP, x:IE|DE +VCOMXSD ; Vdq,Wsd{sae} ; Fv ; evex m:1 p:3 l:i w:1 0x2F /r ; s:AVX102, t:AVX10CMPSFP, l:t1s, w:R|R|W, e:E3NF, f:CMPSFP, x:IE|DE # 0x50 - 0x5F -VSQRTPS ; Vfv{K}{z},Wfv|B32{er} ; ; evex m:1 p:0 l:x w:0 0x51 /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R -VSQRTPD ; Vfv{K}{z},Wfv|B64{er} ; ; evex m:1 p:1 l:x w:1 0x51 /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R -VSQRTSS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:1 p:2 l:i w:0 0x51 /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R -VSQRTSD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:1 p:3 l:i w:1 0x51 /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R +VSQRTPS ; Vfv{K}{z},Wfv|B32{er} ; ; evex m:1 p:0 l:x w:0 0x51 /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R, x:IE|PE|DE +VSQRTPD ; Vfv{K}{z},Wfv|B64{er} ; ; evex m:1 p:1 l:x w:1 0x51 /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R, x:IE|PE|DE +VSQRTSS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:1 p:2 l:i w:0 0x51 /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R, x:IE|PE|DE +VSQRTSD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:1 p:3 l:i w:1 0x51 /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R, x:IE|PE|DE VANDPS ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:1 p:0 l:x w:0 0x54 /r ; s:AVX512DQ, t:LOGICAL_FP, l:fv, e:E4, w:W|R|R|R VANDPD ; Vfv{K}{z},Hfv,Wfv|B64 ; ; evex m:1 p:1 l:x w:1 0x54 /r ; s:AVX512DQ, t:LOGICAL_FP, l:fv, e:E4, w:W|R|R|R VANDNPS ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:1 p:0 l:x w:0 0x55 /r ; s:AVX512DQ, t:LOGICAL_FP, l:fv, e:E4, w:W|R|R|R @@ -72,38 +72,38 @@ VORPS ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:1 p:0 l:x w:0 VORPD ; Vfv{K}{z},Hfv,Wfv|B64 ; ; evex m:1 p:1 l:x w:1 0x56 /r ; s:AVX512DQ, t:LOGICAL_FP, l:fv, e:E4, w:W|R|R|R VXORPS ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:1 p:0 l:x w:0 0x57 /r ; s:AVX512DQ, t:LOGICAL_FP, l:fv, e:E4, w:W|R|R|R VXORPD ; Vfv{K}{z},Hfv,Wfv|B64 ; ; evex m:1 p:1 l:x w:1 0x57 /r ; s:AVX512DQ, t:LOGICAL_FP, l:fv, e:E4, w:W|R|R|R -VADDPS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:1 p:0 l:x w:0 0x58 /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R -VADDPD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:1 p:1 l:x w:1 0x58 /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R -VADDSS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:1 p:2 l:i w:0 0x58 /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R -VADDSD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:1 p:3 l:i w:1 0x58 /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R -VMULPS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:1 p:0 l:x w:0 0x59 /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R -VMULPD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:1 p:1 l:x w:1 0x59 /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R -VMULSS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:1 p:2 l:i w:0 0x59 /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R -VMULSD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:1 p:3 l:i w:1 0x59 /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R -VCVTPS2PD ; Vfv{K}{z},Whv|B32{sae} ; ; evex m:1 p:0 l:x w:0 0x5A /r ; s:AVX512F, t:CONVERT, l:hv, e:E3, w:W|R|R -VCVTPD2PS ; Vhv{K}{z},Wfv|B64{er} ; ; evex m:1 p:1 l:x w:1 0x5A /r ; s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R -VCVTSS2SD ; Vdq{K}{z},Hdq,Wss{sae} ; ; evex m:1 p:2 l:i w:0 0x5A /r ; s:AVX512F, t:CONVERT, l:t1s, e:E3, w:W|R|R|R -VCVTSD2SS ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:1 p:3 l:i w:1 0x5A /r ; s:AVX512F, t:CONVERT, l:t1s, e:E3, w:W|R|R|R -VCVTDQ2PS ; Vfv{K}{z},Wfv|B32{er} ; ; evex m:1 p:0 l:x w:0 0x5B /r ; s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R -VCVTQQ2PS ; Vhv{K}{z},Wfv|B64{er} ; ; evex m:1 p:0 l:x w:1 0x5B /r ; s:AVX512DQ, t:CONVERT, l:fv, e:E2, w:W|R|R -VCVTPS2DQ ; Vfv{K}{z},Wfv|B32{er} ; ; evex m:1 p:1 l:x w:0 0x5B /r ; s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R -VCVTTPS2DQ ; Vfv{K}{z},Wfv|B32{sae} ; ; evex m:1 p:2 l:x w:0 0x5B /r ; s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R -VSUBPS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:1 p:0 l:x w:0 0x5C /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R -VSUBPD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:1 p:1 l:x w:1 0x5C /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R -VSUBSS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:1 p:2 l:i w:0 0x5C /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R -VSUBSD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:1 p:3 l:i w:1 0x5C /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R -VMINPS ; Vfv{K}{z},Hfv,Wfv|B32{sae} ; ; evex m:1 p:0 l:x w:0 0x5D /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R -VMINPD ; Vfv{K}{z},Hfv,Wfv|B64{sae} ; ; evex m:1 p:1 l:x w:1 0x5D /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R -VMINSS ; Vdq{K}{z},Hdq,Wss{sae} ; ; evex m:1 p:2 l:i w:0 0x5D /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R -VMINSD ; Vdq{K}{z},Hdq,Wsd{sae} ; ; evex m:1 p:3 l:i w:1 0x5D /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R -VDIVPS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:1 p:0 l:x w:0 0x5E /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R -VDIVPD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:1 p:1 l:x w:1 0x5E /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R -VDIVSS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:1 p:2 l:i w:0 0x5E /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R -VDIVSD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:1 p:3 l:i w:1 0x5E /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R -VMAXPS ; Vfv{K}{z},Hfv,Wfv|B32{sae} ; ; evex m:1 p:0 l:x w:0 0x5F /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R -VMAXPD ; Vfv{K}{z},Hfv,Wfv|B64{sae} ; ; evex m:1 p:1 l:x w:1 0x5F /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R -VMAXSS ; Vdq{K}{z},Hdq,Wss{sae} ; ; evex m:1 p:2 l:i w:0 0x5F /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R -VMAXSD ; Vdq{K}{z},Hdq,Wsd{sae} ; ; evex m:1 p:3 l:i w:1 0x5F /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R +VADDPS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:1 p:0 l:x w:0 0x58 /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R, x:IE|OE|UE|PE|DE +VADDPD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:1 p:1 l:x w:1 0x58 /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R, x:IE|OE|UE|PE|DE +VADDSS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:1 p:2 l:i w:0 0x58 /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R, x:IE|OE|UE|PE|DE +VADDSD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:1 p:3 l:i w:1 0x58 /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R, x:IE|OE|UE|PE|DE +VMULPS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:1 p:0 l:x w:0 0x59 /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R, x:IE|OE|UE|PE|DE +VMULPD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:1 p:1 l:x w:1 0x59 /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R, x:IE|OE|UE|PE|DE +VMULSS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:1 p:2 l:i w:0 0x59 /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R, x:IE|OE|UE|PE|DE +VMULSD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:1 p:3 l:i w:1 0x59 /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R, x:IE|OE|UE|PE|DE +VCVTPS2PD ; Vfv{K}{z},Whv|B32{sae} ; ; evex m:1 p:0 l:x w:0 0x5A /r ; s:AVX512F, t:CONVERT, l:hv, e:E3, w:W|R|R, x:IE|DE +VCVTPD2PS ; Vhv{K}{z},Wfv|B64{er} ; ; evex m:1 p:1 l:x w:1 0x5A /r ; s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R, x:IE|OE|UE|PE|DE +VCVTSS2SD ; Vdq{K}{z},Hdq,Wss{sae} ; ; evex m:1 p:2 l:i w:0 0x5A /r ; s:AVX512F, t:CONVERT, l:t1s, e:E3, w:W|R|R|R, x:IE|DE +VCVTSD2SS ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:1 p:3 l:i w:1 0x5A /r ; s:AVX512F, t:CONVERT, l:t1s, e:E3, w:W|R|R|R, x:IE|OE|UE|PE|DE +VCVTDQ2PS ; Vfv{K}{z},Wfv|B32{er} ; ; evex m:1 p:0 l:x w:0 0x5B /r ; s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R, x:PE +VCVTQQ2PS ; Vhv{K}{z},Wfv|B64{er} ; ; evex m:1 p:0 l:x w:1 0x5B /r ; s:AVX512DQ, t:CONVERT, l:fv, e:E2, w:W|R|R, x:PE +VCVTPS2DQ ; Vfv{K}{z},Wfv|B32{er} ; ; evex m:1 p:1 l:x w:0 0x5B /r ; s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R, x:IE|PE +VCVTTPS2DQ ; Vfv{K}{z},Wfv|B32{sae} ; ; evex m:1 p:2 l:x w:0 0x5B /r ; s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R, x:IE|PE +VSUBPS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:1 p:0 l:x w:0 0x5C /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R, x:IE|OE|UE|PE|DE +VSUBPD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:1 p:1 l:x w:1 0x5C /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R, x:IE|OE|UE|PE|DE +VSUBSS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:1 p:2 l:i w:0 0x5C /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R, x:IE|OE|UE|PE|DE +VSUBSD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:1 p:3 l:i w:1 0x5C /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R, x:IE|OE|UE|PE|DE +VMINPS ; Vfv{K}{z},Hfv,Wfv|B32{sae} ; ; evex m:1 p:0 l:x w:0 0x5D /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R, x:IE|DE +VMINPD ; Vfv{K}{z},Hfv,Wfv|B64{sae} ; ; evex m:1 p:1 l:x w:1 0x5D /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R, x:IE|DE +VMINSS ; Vdq{K}{z},Hdq,Wss{sae} ; ; evex m:1 p:2 l:i w:0 0x5D /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R, x:IE|DE +VMINSD ; Vdq{K}{z},Hdq,Wsd{sae} ; ; evex m:1 p:3 l:i w:1 0x5D /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R, x:IE|DE +VDIVPS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:1 p:0 l:x w:0 0x5E /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R, x:IE|OE|UE|PE|DE|ZE +VDIVPD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:1 p:1 l:x w:1 0x5E /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R, x:IE|OE|UE|PE|DE|ZE +VDIVSS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:1 p:2 l:i w:0 0x5E /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R, x:IE|OE|UE|PE|DE|ZE +VDIVSD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:1 p:3 l:i w:1 0x5E /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R, x:IE|OE|UE|PE|DE|ZE +VMAXPS ; Vfv{K}{z},Hfv,Wfv|B32{sae} ; ; evex m:1 p:0 l:x w:0 0x5F /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R, x:IE|DE +VMAXPD ; Vfv{K}{z},Hfv,Wfv|B64{sae} ; ; evex m:1 p:1 l:x w:1 0x5F /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R, x:IE|DE +VMAXSS ; Vdq{K}{z},Hdq,Wss{sae} ; ; evex m:1 p:2 l:i w:0 0x5F /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R, x:IE|DE +VMAXSD ; Vdq{K}{z},Hdq,Wsd{sae} ; ; evex m:1 p:3 l:i w:1 0x5F /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R, x:IE|DE # 0x60 - 0x6F VPUNPCKLBW ; Vfv{K}{z},Hfv,Wfv ; ; evex m:1 p:1 l:x w:x 0x60 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4NFnb, w:W|R|R|R @@ -149,32 +149,30 @@ VPSRLDQ ; Hfv,Wfv,Ib ; ; evex m:1 p:1 l:x w:i VPSLLQ ; Hfv{K}{z},Wfv|B64,Ib ; ; evex m:1 p:1 l:x w:1 0x73 /6 ib ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R VPSLLDQ ; Hfv,Wfv,Ib ; ; evex m:1 p:1 l:x w:i 0x73 /7 ib ; s:AVX512BW, t:AVX512, l:fvm, e:E4NFnb, w:W|R|R VPCMPEQB ; rKq{K},Hfv,Wfv ; ; evex m:1 p:1 l:x w:i 0x74 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R -VCVTNEPH2BF8 ; Vhv{K}{z},Wfv|B16 ; ; evex m:1 p:2 l:x w:0 0x74 /r ; s:AVX102, t:AVX10CONVERT, l:fv, e:E4NF, w:W|R|R -VCVTNE2PH2BF8 ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:1 p:3 l:x w:0 0x74 /r ; s:AVX102, t:AVX10CONVERT, l:fv, e:E4NF, w:W|R|R|R VPCMPEQW ; rKq{K},Hfv,Wfv ; ; evex m:1 p:1 l:x w:i 0x75 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R VPCMPEQD ; rKq{K},Hfv,Wfv|B32 ; ; evex m:1 p:1 l:x w:i 0x76 /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R -VCVTTPS2UDQ ; Vfv{K}{z},Wfv|B32{sae} ; ; evex m:1 p:0 l:x w:0 0x78 /r ; s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R -VCVTTPD2UDQ ; Vhv{K}{z},Wfv|B64{sae} ; ; evex m:1 p:0 l:x w:1 0x78 /r ; s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R -VCVTTPS2UQQ ; Vfv{K}{z},Whv|B32{sae} ; ; evex m:1 p:1 l:x w:0 0x78 /r ; s:AVX512DQ, t:CONVERT, l:hv, e:E3, w:W|R|R -VCVTTPD2UQQ ; Vfv{K}{z},Wfv|B64{sae} ; ; evex m:1 p:1 l:x w:1 0x78 /r ; s:AVX512DQ, t:CONVERT, l:fv, e:E2, w:W|R|R -VCVTTSS2USI ; Gy,Wss{sae} ; ; evex m:1 p:2 l:i w:x 0x78 /r ; s:AVX512F, t:CONVERT, l:t1f, e:E3, w:W|R, a:IWO64 -VCVTTSD2USI ; Gy,Wsd{sae} ; ; evex m:1 p:3 l:i w:x 0x78 /r ; s:AVX512F, t:CONVERT, l:t1f, e:E3, w:W|R, a:IWO64 -VCVTPS2UDQ ; Vfv{K}{z},Wfv|B32{er} ; ; evex m:1 p:0 l:x w:0 0x79 /r ; s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R -VCVTPD2UDQ ; Vhv{K}{z},Wfv|B64{er} ; ; evex m:1 p:0 l:x w:1 0x79 /r ; s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R -VCVTPS2UQQ ; Vfv{K}{z},Whv|B32{er} ; ; evex m:1 p:1 l:x w:0 0x79 /r ; s:AVX512DQ, t:CONVERT, l:hv, e:E3, w:W|R|R -VCVTPD2UQQ ; Vfv{K}{z},Wfv|B64{er} ; ; evex m:1 p:1 l:x w:1 0x79 /r ; s:AVX512DQ, t:CONVERT, l:fv, e:E2, w:W|R|R -VCVTSS2USI ; Gy,Wss{er} ; ; evex m:1 p:2 l:i w:x 0x79 /r ; s:AVX512F, t:CONVERT, l:t1f, e:E3, w:W|R, a:IWO64 -VCVTSD2USI ; Gy,Wsd{er} ; ; evex m:1 p:3 l:i w:x 0x79 /r ; s:AVX512F, t:CONVERT, l:t1f, e:E3, w:W|R, a:IWO64 -VCVTTPS2QQ ; Vfv{K}{z},Whv|B32{sae} ; ; evex m:1 p:1 l:x w:0 0x7A /r ; s:AVX512DQ, t:CONVERT, l:hv, e:E3, w:W|R|R -VCVTTPD2QQ ; Vfv{K}{z},Wfv|B64{sae} ; ; evex m:1 p:1 l:x w:1 0x7A /r ; s:AVX512DQ, t:CONVERT, l:fv, e:E2, w:W|R|R +VCVTTPS2UDQ ; Vfv{K}{z},Wfv|B32{sae} ; ; evex m:1 p:0 l:x w:0 0x78 /r ; s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R, x:IE|PE +VCVTTPD2UDQ ; Vhv{K}{z},Wfv|B64{sae} ; ; evex m:1 p:0 l:x w:1 0x78 /r ; s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R, x:IE|PE +VCVTTPS2UQQ ; Vfv{K}{z},Whv|B32{sae} ; ; evex m:1 p:1 l:x w:0 0x78 /r ; s:AVX512DQ, t:CONVERT, l:hv, e:E3, w:W|R|R, x:IE|PE +VCVTTPD2UQQ ; Vfv{K}{z},Wfv|B64{sae} ; ; evex m:1 p:1 l:x w:1 0x78 /r ; s:AVX512DQ, t:CONVERT, l:fv, e:E2, w:W|R|R, x:IE|PE +VCVTTSS2USI ; Gy,Wss{sae} ; ; evex m:1 p:2 l:i w:x 0x78 /r ; s:AVX512F, t:CONVERT, l:t1f, e:E3, w:W|R, a:IWO64, x:IE|PE +VCVTTSD2USI ; Gy,Wsd{sae} ; ; evex m:1 p:3 l:i w:x 0x78 /r ; s:AVX512F, t:CONVERT, l:t1f, e:E3, w:W|R, a:IWO64, x:IE|PE +VCVTPS2UDQ ; Vfv{K}{z},Wfv|B32{er} ; ; evex m:1 p:0 l:x w:0 0x79 /r ; s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R, x:IE|PE +VCVTPD2UDQ ; Vhv{K}{z},Wfv|B64{er} ; ; evex m:1 p:0 l:x w:1 0x79 /r ; s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R, x:IE|PE +VCVTPS2UQQ ; Vfv{K}{z},Whv|B32{er} ; ; evex m:1 p:1 l:x w:0 0x79 /r ; s:AVX512DQ, t:CONVERT, l:hv, e:E3, w:W|R|R, x:IE|PE +VCVTPD2UQQ ; Vfv{K}{z},Wfv|B64{er} ; ; evex m:1 p:1 l:x w:1 0x79 /r ; s:AVX512DQ, t:CONVERT, l:fv, e:E2, w:W|R|R, x:IE|PE +VCVTSS2USI ; Gy,Wss{er} ; ; evex m:1 p:2 l:i w:x 0x79 /r ; s:AVX512F, t:CONVERT, l:t1f, e:E3, w:W|R, a:IWO64, x:IE|PE +VCVTSD2USI ; Gy,Wsd{er} ; ; evex m:1 p:3 l:i w:x 0x79 /r ; s:AVX512F, t:CONVERT, l:t1f, e:E3, w:W|R, a:IWO64, x:IE|PE +VCVTTPS2QQ ; Vfv{K}{z},Whv|B32{sae} ; ; evex m:1 p:1 l:x w:0 0x7A /r ; s:AVX512DQ, t:CONVERT, l:hv, e:E3, w:W|R|R, x:IE|PE +VCVTTPD2QQ ; Vfv{K}{z},Wfv|B64{sae} ; ; evex m:1 p:1 l:x w:1 0x7A /r ; s:AVX512DQ, t:CONVERT, l:fv, e:E2, w:W|R|R, x:IE|PE VCVTUDQ2PD ; Vfv{K}{z},Whv|B32 ; ; evex m:1 p:2 l:x w:0 0x7A /r ; s:AVX512F, t:CONVERT, l:hv, e:E5, w:W|R|R, a:IER -VCVTUQQ2PD ; Vfv{K}{z},Wfv|B64{er} ; ; evex m:1 p:2 l:x w:1 0x7A /r ; s:AVX512DQ, t:CONVERT, l:fv, e:E2, w:W|R|R -VCVTUDQ2PS ; Vfv{K}{z},Wfv|B32{er} ; ; evex m:1 p:3 l:x w:0 0x7A /r ; s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R -VCVTUQQ2PS ; Vhv{K}{z},Wfv|B64{er} ; ; evex m:1 p:3 l:x w:1 0x7A /r ; s:AVX512DQ, t:CONVERT, l:fv, e:E2, w:W|R|R -VCVTPS2QQ ; Vfv{K}{z},Whv|B32{er} ; ; evex m:1 p:1 l:x w:0 0x7B /r ; s:AVX512DQ, t:CONVERT, l:hv, e:E3, w:W|R|R -VCVTPD2QQ ; Vfv{K}{z},Wfv|B64{er} ; ; evex m:1 p:1 l:x w:1 0x7B /r ; s:AVX512DQ, t:CONVERT, l:fv, e:E2, w:W|R|R -VCVTUSI2SS ; Vss,Hss{er},Ey ; ; evex m:1 p:2 l:i w:x 0x7B /r ; s:AVX512F, t:CONVERT, l:t1s, e:E3, w:W|R|R, a:IWO64 -VCVTUSI2SD ; Vdq,Hdq,Ey ; ; evex m:1 p:3 l:i w:0 0x7B /r ; s:AVX512F, t:CONVERT, l:t1s, e:E10NF, w:W|R|R, a:IER|IWO64 +VCVTUQQ2PD ; Vfv{K}{z},Wfv|B64{er} ; ; evex m:1 p:2 l:x w:1 0x7A /r ; s:AVX512DQ, t:CONVERT, l:fv, e:E2, w:W|R|R, x:PE +VCVTUDQ2PS ; Vfv{K}{z},Wfv|B32{er} ; ; evex m:1 p:3 l:x w:0 0x7A /r ; s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R, x:PE +VCVTUQQ2PS ; Vhv{K}{z},Wfv|B64{er} ; ; evex m:1 p:3 l:x w:1 0x7A /r ; s:AVX512DQ, t:CONVERT, l:fv, e:E2, w:W|R|R, x:PE +VCVTPS2QQ ; Vfv{K}{z},Whv|B32{er} ; ; evex m:1 p:1 l:x w:0 0x7B /r ; s:AVX512DQ, t:CONVERT, l:hv, e:E3, w:W|R|R, x:IE|PE +VCVTPD2QQ ; Vfv{K}{z},Wfv|B64{er} ; ; evex m:1 p:1 l:x w:1 0x7B /r ; s:AVX512DQ, t:CONVERT, l:fv, e:E2, w:W|R|R, x:IE|PE +VCVTUSI2SS ; Vss,Hss{er},Ey ; ; evex m:1 p:2 l:i w:x 0x7B /r ; s:AVX512F, t:CONVERT, l:t1s, e:E3, w:W|R|R, a:IWO64, x:PE +VCVTUSI2SD ; Vdq,Hdq,Ey ; ; evex m:1 p:3 l:i w:0 0x7B /r ; s:AVX512F, t:CONVERT, l:t1s, e:E10NF, w:W|R|R, a:IER|IWO64, x:PE VCVTUSI2SD ; Vdq,Hdq{er},Ey ; ; evex m:1 p:3 l:i w:1 0x7B /r ; s:AVX512F, t:CONVERT, l:t1s, e:E3, w:W|R|R, a:IWO64 VMOVD ; Ey,Vdq ; ; evex m:1 p:1 l:0 w:0 0x7E /r ; s:AVX512F, t:DATAXFER, l:t1s, e:E9NF, w:W|R, a:IWO64 VMOVQ ; Ey,Vdq ; ; evex m:1 p:1 l:0 w:1 0x7E /r ; s:AVX512F, t:DATAXFER, l:t1s, e:E9NF, w:W|R, a:IWO64 @@ -196,10 +194,10 @@ VMOVDQU16 ; Wfv{K}{z},Vfv ; ; evex m:1 p:3 l:x w:1 # 0xB0 - 0xBF # 0xC0 - 0xCF -VCMPPS ; rKq{K},Hfv,Wfv|B32{sae},Ib ; ; evex m:1 p:0 l:x w:0 0xC2 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R|R -VCMPPD ; rKq{K},Hfv,Wfv|B64{sae},Ib ; ; evex m:1 p:1 l:x w:1 0xC2 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R|R -VCMPSS ; rKq{K},Hdq,Wss{sae},Ib ; ; evex m:1 p:2 l:x w:0 0xC2 /r ib ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R|R -VCMPSD ; rKq{K},Hdq,Wsd{sae},Ib ; ; evex m:1 p:3 l:x w:1 0xC2 /r ib ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R|R +VCMPPS ; rKq{K},Hfv,Wfv|B32{sae},Ib ; ; evex m:1 p:0 l:x w:0 0xC2 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R|R, x:IE|DE +VCMPPD ; rKq{K},Hfv,Wfv|B64{sae},Ib ; ; evex m:1 p:1 l:x w:1 0xC2 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R|R, x:IE|DE +VCMPSS ; rKq{K},Hdq,Wss{sae},Ib ; ; evex m:1 p:2 l:x w:0 0xC2 /r ib ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R|R, x:IE|DE +VCMPSD ; rKq{K},Hdq,Wsd{sae},Ib ; ; evex m:1 p:3 l:x w:1 0xC2 /r ib ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R|R, x:IE|DE VPINSRW ; Vdq,Hdq,Mw,Ib ; ; evex m:1 p:1 l:0 w:i 0xC4 /r:mem ib ; s:AVX512BW, t:AVX512, l:t1s16, e:E9NF, w:W|R|R|R VPINSRW ; Vdq,Hdq,Rv,Ib ; ; evex m:1 p:1 l:0 w:i 0xC4 /r:reg ib ; s:AVX512BW, t:AVX512, l:t1s16, e:E9NF, w:W|R|R|R VPEXTRW ; Gy,Udq,Ib ; ; evex m:1 p:1 l:0 w:i 0xC5 /r:reg ib ; s:AVX512BW, t:AVX512, l:t1s, e:E9NF, w:W|R|R @@ -233,10 +231,10 @@ VPSRAQ ; Vfv{K}{z},Hfv,Wdq ; ; evex m:1 p:1 l:x w:1 VPAVGW ; Vfv{K}{z},Hfv,Wfv ; ; evex m:1 p:1 l:x w:i 0xE3 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R VPMULHUW ; Vfv{K}{z},Hfv,Wfv ; ; evex m:1 p:1 l:x w:i 0xE4 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R VPMULHW ; Vfv{K}{z},Hfv,Wfv ; ; evex m:1 p:1 l:x w:i 0xE5 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R -VCVTTPD2DQ ; Vhv{K}{z},Wfv|B64{sae} ; ; evex m:1 p:1 l:x w:1 0xE6 /r ; s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R +VCVTTPD2DQ ; Vhv{K}{z},Wfv|B64{sae} ; ; evex m:1 p:1 l:x w:1 0xE6 /r ; s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R, x:IE|PE VCVTDQ2PD ; Vfv{K}{z},Whv|B32 ; ; evex m:1 p:2 l:x w:0 0xE6 /r ; s:AVX512F, t:CONVERT, l:hv, e:E5, w:W|R|R, a:IER -VCVTQQ2PD ; Vfv{K}{z},Wfv|B64{er} ; ; evex m:1 p:2 l:x w:1 0xE6 /r ; s:AVX512DQ, t:CONVERT, l:fv, e:E2, w:W|R|R -VCVTPD2DQ ; Vhv{K}{z},Wfv|B64{er} ; ; evex m:1 p:3 l:x w:1 0xE6 /r ; s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R +VCVTQQ2PD ; Vfv{K}{z},Wfv|B64{er} ; ; evex m:1 p:2 l:x w:1 0xE6 /r ; s:AVX512DQ, t:CONVERT, l:fv, e:E2, w:W|R|R, x:PE +VCVTPD2DQ ; Vhv{K}{z},Wfv|B64{er} ; ; evex m:1 p:3 l:x w:1 0xE6 /r ; s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R, x:IE|PE VMOVNTDQ ; Mfv,Vfv ; ; evex m:1 p:1 l:x w:0 0xE7 /r:mem ; s:AVX512F, t:DATAXFER, l:fvm, e:E1NF, w:W|R VPSUBSB ; Vfv{K}{z},Hfv,Wfv ; ; evex m:1 p:1 l:x w:i 0xE8 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R VPSUBSW ; Vfv{K}{z},Hfv,Wfv ; ; evex m:1 p:1 l:x w:i 0xE9 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R diff --git a/isagenerator/instructions/table_evex_2.dat b/isagenerator/instructions/table_evex_2.dat index 5be7ba7..b80ba6d 100644 --- a/isagenerator/instructions/table_evex_2.dat +++ b/isagenerator/instructions/table_evex_2.dat @@ -14,7 +14,7 @@ VPERMILPD ; Vfv{K}{z},Hfv,Wfv|B64 ; ; evex m:2 p:1 l:x w:1 VPSRLVW ; Vfv{K}{z},Hfv,Wfv ; ; evex m:2 p:1 l:x w:1 0x10 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R VPSRAVW ; Vfv{K}{z},Hfv,Wfv ; ; evex m:2 p:1 l:x w:1 0x11 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4, w:W|R|R|R VPSLLVW ; Vfv{K}{z},Hfv,Wfv ; ; evex m:2 p:1 l:x w:1 0x12 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R -VCVTPH2PS ; Vfv{K}{z},Whv{sae} ; ; evex m:2 p:1 l:x w:0 0x13 /r ; s:AVX512F, t:CONVERT, l:hvm, e:E11, w:W|R|R +VCVTPH2PS ; Vfv{K}{z},Whv{sae} ; ; evex m:2 p:1 l:x w:0 0x13 /r ; s:AVX512F, t:CONVERT, l:hvm, e:E11, w:W|R|R, x:IE VPRORVD ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:1 l:x w:0 0x14 /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R VPRORVQ ; Vfv{K}{z},Hfv,Wfv|B64 ; ; evex m:2 p:1 l:x w:1 0x14 /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R VPROLVD ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:1 l:x w:0 0x15 /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R @@ -66,10 +66,10 @@ VPMULDQ ; Vfv{K}{z},Hfv,Wfv|B64 ; ; evex m:2 p:1 l:x w:1 VPCMPEQQ ; rKq{K},Hfv,Wfv|B64 ; ; evex m:2 p:1 l:x w:1 0x29 /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R VMOVNTDQA ; Vfv,Mfv ; ; evex m:2 p:1 l:x w:0 0x2A /r:mem ; s:AVX512F, t:DATAXFER, l:fvm, e:E1NF, w:W|R VPACKUSDW ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:1 l:x w:0 0x2B /r ; s:AVX512BW, t:AVX512, l:fv, e:E4NF, w:W|R|R|R -VSCALEFPS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0x2C /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R -VSCALEFPD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0x2C /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R -VSCALEFSS ; Vss{K}{z},Hss,Wss{er} ; ; evex m:2 p:1 l:i w:0 0x2D /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R -VSCALEFSD ; Vsd{K}{z},Hsd,Wsd{er} ; ; evex m:2 p:1 l:i w:1 0x2D /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R +VSCALEFPS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0x2C /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R, x:IE|OE|UE|PE|DE +VSCALEFPD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0x2C /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R, x:IE|OE|UE|PE|DE +VSCALEFSS ; Vss{K}{z},Hss,Wss{er} ; ; evex m:2 p:1 l:i w:0 0x2D /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R, x:IE|OE|UE|PE|DE +VSCALEFSD ; Vsd{K}{z},Hsd,Wsd{er} ; ; evex m:2 p:1 l:i w:1 0x2D /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R, x:IE|OE|UE|PE|DE VPMOVM2B ; Vfv,mKq ; ; evex m:2 p:2 l:x w:0 0x28 /r:reg ; s:AVX512BW, t:DATAXFER, e:E7NM, w:W|R VPMOVM2W ; Vfv,mKq ; ; evex m:2 p:2 l:x w:1 0x28 /r:reg ; s:AVX512BW, t:DATAXFER, e:E7NM, w:W|R VPMOVB2M ; rKq,Ufv ; ; evex m:2 p:2 l:x w:0 0x29 /r:reg ; s:AVX512BW, t:DATAXFER, e:E7NM, w:W|R @@ -113,10 +113,10 @@ VPBROADCASTMW2D ; Vfv,mKq ; ; evex m:2 p:2 l:x w:0 # 0x40 - 0x4F VPMULLD ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:1 l:x w:0 0x40 /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R VPMULLQ ; Vfv{K}{z},Hfv,Wfv|B64 ; ; evex m:2 p:1 l:x w:1 0x40 /r ; s:AVX512DQ, t:AVX512, l:fv, e:E4, w:W|R|R|R -VGETEXPPS ; Vfv{K}{z},Wfv|B32{sae} ; ; evex m:2 p:1 l:x w:0 0x42 /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R -VGETEXPPD ; Vfv{K}{z},Wfv|B64{sae} ; ; evex m:2 p:1 l:x w:1 0x42 /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R -VGETEXPSS ; Vdq{K}{z},Hdq,Wss{sae} ; ; evex m:2 p:1 l:x w:0 0x43 /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R -VGETEXPSD ; Vdq{K}{z},Hdq,Wsd{sae} ; ; evex m:2 p:1 l:x w:1 0x43 /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R +VGETEXPPS ; Vfv{K}{z},Wfv|B32{sae} ; ; evex m:2 p:1 l:x w:0 0x42 /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R, x:IE|DE +VGETEXPPD ; Vfv{K}{z},Wfv|B64{sae} ; ; evex m:2 p:1 l:x w:1 0x42 /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R, x:IE|DE +VGETEXPSS ; Vdq{K}{z},Hdq,Wss{sae} ; ; evex m:2 p:1 l:x w:0 0x43 /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R, x:IE|DE +VGETEXPSD ; Vdq{K}{z},Hdq,Wsd{sae} ; ; evex m:2 p:1 l:x w:1 0x43 /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R, x:IE|DE VPLZCNTD ; Vfv{K}{z},Wfv|B32 ; ; evex m:2 p:1 l:x w:0 0x44 /r ; s:AVX512CD, t:CONFLICT, l:fv, e:E4, w:W|R|R VPLZCNTQ ; Vfv{K}{z},Wfv|B64 ; ; evex m:2 p:1 l:x w:1 0x44 /r ; s:AVX512CD, t:CONFLICT, l:fv, e:E4, w:W|R|R VPSRLVD ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:1 l:x w:0 0x45 /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R @@ -125,6 +125,8 @@ VPSRAVD ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:1 l:x w:0 VPSRAVQ ; Vfv{K}{z},Hfv,Wfv|B64 ; ; evex m:2 p:1 l:x w:1 0x46 /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R VPSLLVD ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:1 l:x w:0 0x47 /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R VPSLLVQ ; Vfv{K}{z},Hfv,Wfv|B64 ; ; evex m:2 p:1 l:x w:1 0x47 /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R +TILEMOVROW ; Voq,mTt,Bd ; ; evex m:2 p:1 l:2 w:0 0x4A /r:reg ; s:AMXAVX512, t:AMX, e:AMX_EVEX_E8, w:W|R|R, m:NOTSX +TCVTROWD2PS ; Voq,mTt,Bd ; ; evex m:2 p:2 l:2 w:0 0x4A /r:reg ; s:AMXAVX512, t:AMX, e:AMX_EVEX_E8, w:W|R|R, m:NOTSX VRCP14PS ; Vfv{K}{z},Wfv|B32 ; ; evex m:2 p:1 l:x w:0 0x4C /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R VRCP14PD ; Vfv{K}{z},Wfv|B64 ; ; evex m:2 p:1 l:x w:1 0x4C /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R VRCP14SS ; Vdq{K}{z},Hdq,Wss ; ; evex m:2 p:1 l:x w:0 0x4D /r ; s:AVX512F, t:AVX512, l:t1s, e:E10, w:W|R|R|R @@ -172,21 +174,28 @@ VBLENDMPS ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:1 l:x w:0 VBLENDMPD ; Vfv{K}{z},Hfv,Wfv|B64 ; ; evex m:2 p:1 l:x w:1 0x65 /r ; s:AVX512F, t:BLEND, l:fv, e:E4, w:W|R|R|R VPBLENDMB ; Vfv{K}{z},Hfv,Wfv ; ; evex m:2 p:1 l:x w:0 0x66 /r ; s:AVX512BW, t:BLEND, l:fvm, e:E4, w:W|R|R|R VPBLENDMW ; Vfv{K}{z},Hfv,Wfv ; ; evex m:2 p:1 l:x w:1 0x66 /r ; s:AVX512BW, t:BLEND, l:fvm, e:E4, w:W|R|R|R -VCVT2PS2PHX ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0x67 /r ; s:AVX102, t:AVX10CONVERT, l:fv, e:E4NF, w:W|R|R|R +VCVT2PS2PHX ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0x67 /r ; s:AVX102, t:AVX10CONVERT, l:fv, e:E4NF, w:W|R|R|R, x:IE|OE|UE|PE|DE VP2INTERSECTD ; rKq+1,Hfv,Wfv|B32 ; ; evex m:2 p:3 l:x w:0 0x68 /r ; s:AVX512VP2INTERSECT, t:AVX512VP2INTERSECT, l:fv, e:E4NF, w:W|R|R VP2INTERSECTQ ; rKq+1,Hfv,Wfv|B64 ; ; evex m:2 p:3 l:x w:1 0x68 /r ; s:AVX512VP2INTERSECT, t:AVX512VP2INTERSECT, l:fv, e:E4NF, w:W|R|R +TCVTROWPS2PHH ; Voq,mTt,Bd ; ; evex m:2 p:0 l:2 w:0 0x6D /r:reg ; s:AMXAVX512, t:AMX, e:AMX_EVEX_E8, w:W|R|R, m:NOTSX +TCVTROWPS2PHL ; Voq,mTt,Bd ; ; evex m:2 p:1 l:2 w:0 0x6D /r:reg ; s:AMXAVX512, t:AMX, e:AMX_EVEX_E8, w:W|R|R, m:NOTSX +TCVTROWPS2PBF16L ; Voq,mTt,Bd ; ; evex m:2 p:2 l:2 w:0 0x6D /r:reg ; s:AMXAVX512, t:AMX, e:AMX_EVEX_E8, w:W|R|R, m:NOTSX +TCVTROWPS2PBF16H ; Voq,mTt,Bd ; ; evex m:2 p:3 l:2 w:0 0x6D /r:reg ; s:AMXAVX512, t:AMX, e:AMX_EVEX_E8, w:W|R|R, m:NOTSX + # 0x70 - 0x7F VPSHLDVW ; Vfv{K}{z},Hfv,Wfv ; ; evex m:2 p:1 l:x w:1 0x70 /r ; s:AVX512VBMI2, t:AVX512VBMI, l:fvm, e:E4, w:RW|R|R|R VPSHLDVD ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:1 l:x w:0 0x71 /r ; s:AVX512VBMI2, t:AVX512VBMI, l:fv, e:E4, w:RW|R|R|R VPSHLDVQ ; Vfv{K}{z},Hfv,Wfv|B64 ; ; evex m:2 p:1 l:x w:1 0x71 /r ; s:AVX512VBMI2, t:AVX512VBMI, l:fv, e:E4, w:RW|R|R|R VPSHRDVW ; Vfv{K}{z},Hfv,Wfv ; ; evex m:2 p:1 l:x w:1 0x72 /r ; s:AVX512VBMI2, t:AVX512VBMI, l:fvm, e:E4, w:RW|R|R|R -VCVTNEPS2BF16 ; Vhv{K}{z},Wfv|B32 ; ; evex m:2 p:2 l:x w:0 0x72 /r ; s:AVX512BF16, t:AVX512BF16, l:fv, e:E4, w:W|R|R -VCVTNE2PS2BF16 ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:3 l:x w:0 0x72 /r ; s:AVX512BF16, t:AVX512BF16, l:fv, e:E4NF, w:W|R|R|R +VCVTNEPS2BF16 ; Vhv{K}{z},Wfv|B32 ; ; evex m:2 p:2 l:x w:0 0x72 /r ; s:AVX512BF16, t:AVX512BF16, l:fv, e:E4, w:W|R|R, x:IE|OE|UE|PE|DE +VCVTNE2PS2BF16 ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:3 l:x w:0 0x72 /r ; s:AVX512BF16, t:AVX512BF16, l:fv, e:E4NF, w:W|R|R|R, x:IE|OE|UE|PE|DE VPSHRDVD ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:1 l:x w:0 0x73 /r ; s:AVX512VBMI2, t:AVX512VBMI, l:fv, e:E4, w:RW|R|R|R VPSHRDVQ ; Vfv{K}{z},Hfv,Wfv|B64 ; ; evex m:2 p:1 l:x w:1 0x73 /r ; s:AVX512VBMI2, t:AVX512VBMI, l:fv, e:E4, w:RW|R|R|R VCVTBIASPH2BF8 ; Vhv{K}{z},Hfv,Wfv|B16 ; ; evex m:2 p:0 l:x w:0 0x74 /r ; s:AVX102, t:AVX10CONVERT, l:fv, e:E4NF, w:W|R|R|R +VCVTNEPH2BF8 ; Vhv{K}{z},Wfv|B16 ; ; evex m:2 p:2 l:x w:0 0x74 /r ; s:AVX102, t:AVX10CONVERT, l:fv, e:E4NF, w:W|R|R, x:IE|OE|UE|PE|DE +VCVTNE2PH2BF8 ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:2 p:3 l:x w:0 0x74 /r ; s:AVX102, t:AVX10CONVERT, l:fv, e:E4NF, w:W|R|R|R, x:IE|OE|UE|PE|DE VPERMI2B ; Vfv{K}{z},Hfv,Wfv ; ; evex m:2 p:1 l:x w:0 0x75 /r ; s:AVX512VBMI, t:AVX512VBMI, l:fvm, e:E4NFnb, w:RW|R|R|R VPERMI2W ; Vfv{K}{z},Hfv,Wfv ; ; evex m:2 p:1 l:x w:1 0x75 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4NFnb, w:RW|R|R|R @@ -231,85 +240,85 @@ VGATHERDPD ; Vfv{K},Mvm32h ; ; evex m:2 p:1 l:x w:1 VGATHERQPS ; Vhv{K},Mvm64n ; ; evex m:2 p:1 l:x w:0 0x93 /r:mem vsib ; s:AVX512F, t:GATHER, a:MMASK, l:t1s, e:E12, w:W|R|RW VGATHERQPD ; Vfv{K},Mvm64n ; ; evex m:2 p:1 l:x w:1 0x93 /r:mem vsib ; s:AVX512F, t:GATHER, a:MMASK, l:t1s, e:E12, w:W|R|RW -VFMADDSUB132PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0x96 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R -VFMADDSUB132PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0x96 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R -VFMSUBADD132PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0x97 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R -VFMSUBADD132PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0x97 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R -VFMADD132PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0x98 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R -VFMADD132PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0x98 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R -VFMADD132SS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:2 p:1 l:i w:0 0x99 /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R -VFMADD132SD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:2 p:1 l:i w:1 0x99 /r ; s:AVX512F, t:VFMA, l:t1s, e:E2, w:RW|R|R|R -VFMSUB132PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0x9A /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R -VFMSUB132PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0x9A /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R -V4FMADDPS ; Voq{K}{z},Hoq+3,Mdq ; ; evex m:2 p:3 l:2 w:0 0x9A /r:mem ; s:AVX5124FMAPS, t:VFMAPS, l:t1_4x, e:E2, w:RW|R|R|R -VFMSUB132SS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:2 p:1 l:i w:0 0x9B /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R -VFMSUB132SD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:2 p:1 l:i w:1 0x9B /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R -V4FMADDSS ; Vdq{K}{z},Hdq+3,Mdq ; ; evex m:2 p:3 l:i w:0 0x9B /r:mem ; s:AVX5124FMAPS, t:VFMAPS, e:E3, l:t1_4x, w:RW|R|R|R -VFNMADD132PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0x9C /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R -VFNMADD132PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0x9C /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R -VFNMADD132SS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:2 p:1 l:i w:0 0x9D /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R -VFNMADD132SD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:2 p:1 l:i w:1 0x9D /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R -VFNMSUB132PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0x9E /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R -VFNMSUB132PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0x9E /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R -VFNMSUB132SS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:2 p:1 l:i w:0 0x9F /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R -VFNMSUB132SD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:2 p:1 l:i w:1 0x9F /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R +VFMADDSUB132PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0x96 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE +VFMADDSUB132PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0x96 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE +VFMSUBADD132PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0x97 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE +VFMSUBADD132PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0x97 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE +VFMADD132PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0x98 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE +VFMADD132PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0x98 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE +VFMADD132SS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:2 p:1 l:i w:0 0x99 /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R, x:IE|OE|UE|PE|DE +VFMADD132SD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:2 p:1 l:i w:1 0x99 /r ; s:AVX512F, t:VFMA, l:t1s, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE +VFMSUB132PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0x9A /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE +VFMSUB132PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0x9A /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE +V4FMADDPS ; Voq{K}{z},Hoq+3,Mdq ; ; evex m:2 p:3 l:2 w:0 0x9A /r:mem ; s:AVX5124FMAPS, t:VFMAPS, l:t1_4x, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE +VFMSUB132SS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:2 p:1 l:i w:0 0x9B /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R, x:IE|OE|UE|PE|DE +VFMSUB132SD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:2 p:1 l:i w:1 0x9B /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R, x:IE|OE|UE|PE|DE +V4FMADDSS ; Vdq{K}{z},Hdq+3,Mdq ; ; evex m:2 p:3 l:i w:0 0x9B /r:mem ; s:AVX5124FMAPS, t:VFMAPS, e:E3, l:t1_4x, w:RW|R|R|R, x:IE|OE|UE|PE|DE +VFNMADD132PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0x9C /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE +VFNMADD132PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0x9C /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE +VFNMADD132SS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:2 p:1 l:i w:0 0x9D /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R, x:IE|OE|UE|PE|DE +VFNMADD132SD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:2 p:1 l:i w:1 0x9D /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R, x:IE|OE|UE|PE|DE +VFNMSUB132PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0x9E /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE +VFNMSUB132PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0x9E /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE +VFNMSUB132SS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:2 p:1 l:i w:0 0x9F /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R, x:IE|OE|UE|PE|DE +VFNMSUB132SD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:2 p:1 l:i w:1 0x9F /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R, x:IE|OE|UE|PE|DE # 0xA0 - 0xAF VPSCATTERDD ; Mvm32n{K},Vfv ; ; evex m:2 p:1 l:x w:0 0xA0 /r:mem vsib ; s:AVX512F, t:SCATTER, a:MMASK, l:t1s, e:E12, w:W|R|RW VPSCATTERDQ ; Mvm32h{K},Vfv ; ; evex m:2 p:1 l:x w:1 0xA0 /r:mem vsib ; s:AVX512F, t:SCATTER, a:MMASK, l:t1s, e:E12, w:W|R|RW VPSCATTERQD ; Mvm64n{K},Vhv ; ; evex m:2 p:1 l:x w:0 0xA1 /r:mem vsib ; s:AVX512F, t:SCATTER, a:MMASK, l:t1s, e:E12, w:W|R|RW VPSCATTERQQ ; Mvm64n{K},Vfv ; ; evex m:2 p:1 l:x w:1 0xA1 /r:mem vsib ; s:AVX512F, t:SCATTER, a:MMASK, l:t1s, e:E12, w:W|R|RW -VSCATTERDPS ; Mvm32n{K},Vfv ; ; evex m:2 p:1 l:x w:0 0xA2 /r:mem vsib ; s:AVX512F, t:SCATTER, a:MMASK, l:t1s, e:E12, w:W|R|RW -VSCATTERDPD ; Mvm32h{K},Vfv ; ; evex m:2 p:1 l:x w:1 0xA2 /r:mem vsib ; s:AVX512F, t:SCATTER, a:MMASK, l:t1s, e:E12, w:W|R|RW -VSCATTERQPS ; Mvm64n{K},Vhv ; ; evex m:2 p:1 l:x w:0 0xA3 /r:mem vsib ; s:AVX512F, t:SCATTER, a:MMASK, l:t1s, e:E12, w:W|R|RW -VSCATTERQPD ; Mvm64n{K},Vfv ; ; evex m:2 p:1 l:x w:1 0xA3 /r:mem vsib ; s:AVX512F, t:SCATTER, a:MMASK, l:t1s, e:E12, w:W|R|RW +VSCATTERDPS ; Mvm32n{K},Vfv ; ; evex m:2 p:1 l:x w:0 0xA2 /r:mem vsib ; s:AVX512F, t:SCATTER, a:MMASK, l:t1s, e:E12, w:W|R|RW, x:IE|OE|UE|PE|DE +VSCATTERDPD ; Mvm32h{K},Vfv ; ; evex m:2 p:1 l:x w:1 0xA2 /r:mem vsib ; s:AVX512F, t:SCATTER, a:MMASK, l:t1s, e:E12, w:W|R|RW, x:IE|OE|UE|PE|DE +VSCATTERQPS ; Mvm64n{K},Vhv ; ; evex m:2 p:1 l:x w:0 0xA3 /r:mem vsib ; s:AVX512F, t:SCATTER, a:MMASK, l:t1s, e:E12, w:W|R|RW, x:IE|OE|UE|PE|DE +VSCATTERQPD ; Mvm64n{K},Vfv ; ; evex m:2 p:1 l:x w:1 0xA3 /r:mem vsib ; s:AVX512F, t:SCATTER, a:MMASK, l:t1s, e:E12, w:W|R|RW, x:IE|OE|UE|PE|DE -VFMADDSUB213PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0xA6 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R -VFMADDSUB213PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0xA6 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R -VFMSUBADD213PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0xA7 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R -VFMSUBADD213PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0xA7 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R -VFMADD213PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0xA8 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R -VFMADD213PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0xA8 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R -VFMADD213SS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:2 p:1 l:i w:0 0xA9 /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R -VFMADD213SD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:2 p:1 l:i w:1 0xA9 /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R -VFMSUB213PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0xAA /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R -VFMSUB213PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0xAA /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R -V4FNMADDPS ; Voq{K}{z},Hoq+3,Mdq ; ; evex m:2 p:3 l:2 w:0 0xAA /r:mem ; s:AVX5124FMAPS, t:VFMAPS, l:t1_4x, e:E2, w:RW|R|R|R -VFMSUB213SS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:2 p:1 l:i w:0 0xAB /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R -VFMSUB213SD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:2 p:1 l:i w:1 0xAB /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R -V4FNMADDSS ; Vdq{K}{z},Hdq+3,Mdq ; ; evex m:2 p:3 l:i w:0 0xAB /r:mem ; s:AVX5124FMAPS, t:VFMAPS, l:t1_4x, e:E2, w:RW|R|R|R -VFNMADD213PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0xAC /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R -VFNMADD213PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0xAC /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R -VFNMADD213SS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:2 p:1 l:i w:0 0xAD /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R -VFNMADD213SD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:2 p:1 l:i w:1 0xAD /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R -VFNMSUB213PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0xAE /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R -VFNMSUB213PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0xAE /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R -VFNMSUB213SS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:2 p:1 l:i w:0 0xAF /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R -VFNMSUB213SD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:2 p:1 l:i w:1 0xAF /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R +VFMADDSUB213PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0xA6 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE +VFMADDSUB213PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0xA6 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE +VFMSUBADD213PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0xA7 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE +VFMSUBADD213PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0xA7 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE +VFMADD213PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0xA8 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE +VFMADD213PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0xA8 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE +VFMADD213SS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:2 p:1 l:i w:0 0xA9 /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R, x:IE|OE|UE|PE|DE +VFMADD213SD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:2 p:1 l:i w:1 0xA9 /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R, x:IE|OE|UE|PE|DE +VFMSUB213PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0xAA /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE +VFMSUB213PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0xAA /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE +V4FNMADDPS ; Voq{K}{z},Hoq+3,Mdq ; ; evex m:2 p:3 l:2 w:0 0xAA /r:mem ; s:AVX5124FMAPS, t:VFMAPS, l:t1_4x, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE +VFMSUB213SS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:2 p:1 l:i w:0 0xAB /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R, x:IE|OE|UE|PE|DE +VFMSUB213SD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:2 p:1 l:i w:1 0xAB /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R, x:IE|OE|UE|PE|DE +V4FNMADDSS ; Vdq{K}{z},Hdq+3,Mdq ; ; evex m:2 p:3 l:i w:0 0xAB /r:mem ; s:AVX5124FMAPS, t:VFMAPS, l:t1_4x, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE +VFNMADD213PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0xAC /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE +VFNMADD213PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0xAC /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE +VFNMADD213SS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:2 p:1 l:i w:0 0xAD /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R, x:IE|OE|UE|PE|DE +VFNMADD213SD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:2 p:1 l:i w:1 0xAD /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R, x:IE|OE|UE|PE|DE +VFNMSUB213PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0xAE /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE +VFNMSUB213PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0xAE /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE +VFNMSUB213SS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:2 p:1 l:i w:0 0xAF /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R, x:IE|OE|UE|PE|DE +VFNMSUB213SD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:2 p:1 l:i w:1 0xAF /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R, x:IE|OE|UE|PE|DE # 0xB0 - 0xBF VPMADD52LUQ ; Vfv{K}{z},Hfv,Wfv|B64 ; ; evex m:2 p:1 l:x w:1 0xB4 /r ; s:AVX512IFMA, t:IFMA, l:fv, e:E4, w:RW|R|R|R VPMADD52HUQ ; Vfv{K}{z},Hfv,Wfv|B64 ; ; evex m:2 p:1 l:x w:1 0xB5 /r ; s:AVX512IFMA, t:IFMA, l:fv, e:E4, w:RW|R|R|R -VFMADDSUB231PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0xB6 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R -VFMADDSUB231PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0xB6 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R -VFMSUBADD231PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0xB7 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R -VFMSUBADD231PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0xB7 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R -VFMADD231PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0xB8 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R -VFMADD231PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0xB8 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R -VFMADD231SS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:2 p:1 l:i w:0 0xB9 /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R -VFMADD231SD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:2 p:1 l:i w:1 0xB9 /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R -VFMSUB231PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0xBA /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R -VFMSUB231PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0xBA /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R -VFMSUB231SS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:2 p:1 l:i w:0 0xBB /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R -VFMSUB231SD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:2 p:1 l:i w:1 0xBB /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R -VFNMADD231PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0xBC /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R -VFNMADD231PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0xBC /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R -VFNMADD231SS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:2 p:1 l:i w:0 0xBD /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R -VFNMADD231SD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:2 p:1 l:i w:1 0xBD /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R -VFNMSUB231PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0xBE /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R -VFNMSUB231PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0xBE /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R -VFNMSUB231SS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:2 p:1 l:i w:0 0xBF /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R -VFNMSUB231SD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:2 p:1 l:i w:1 0xBF /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R +VFMADDSUB231PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0xB6 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE +VFMADDSUB231PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0xB6 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE +VFMSUBADD231PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0xB7 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE +VFMSUBADD231PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0xB7 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE +VFMADD231PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0xB8 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE +VFMADD231PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0xB8 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE +VFMADD231SS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:2 p:1 l:i w:0 0xB9 /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R, x:IE|OE|UE|PE|DE +VFMADD231SD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:2 p:1 l:i w:1 0xB9 /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R, x:IE|OE|UE|PE|DE +VFMSUB231PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0xBA /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE +VFMSUB231PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0xBA /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE +VFMSUB231SS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:2 p:1 l:i w:0 0xBB /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R, x:IE|OE|UE|PE|DE +VFMSUB231SD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:2 p:1 l:i w:1 0xBB /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R, x:IE|OE|UE|PE|DE +VFNMADD231PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0xBC /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE +VFNMADD231PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0xBC /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE +VFNMADD231SS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:2 p:1 l:i w:0 0xBD /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R, x:IE|OE|UE|PE|DE +VFNMADD231SD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:2 p:1 l:i w:1 0xBD /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R, x:IE|OE|UE|PE|DE +VFNMSUB231PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0xBE /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE +VFNMSUB231PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0xBE /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE +VFNMSUB231SS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:2 p:1 l:i w:0 0xBF /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R, x:IE|OE|UE|PE|DE +VFNMSUB231SD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:2 p:1 l:i w:1 0xBF /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R, x:IE|OE|UE|PE|DE # 0xC0 - 0xCF VPCONFLICTD ; Vfv{K}{z},Wfv|B32 ; ; evex m:2 p:1 l:x w:0 0xC4 /r ; s:AVX512CD, t:CONFLICT, l:fv, e:E4NF, w:W|R|R @@ -331,16 +340,16 @@ VSCATTERPF0QPD ; Mvm64n{K} ; ; evex m:2 p:1 l:2 w:1 VSCATTERPF1QPS ; Mvm64n{K} ; ; evex m:2 p:1 l:2 w:0 0xC7 /6:mem vsib ; s:AVX512PF, t:SCATTER, a:MMASK, l:t1s, e:E12NP, w:P|R VSCATTERPF1QPD ; Mvm64n{K} ; ; evex m:2 p:1 l:2 w:1 0xC7 /6:mem vsib ; s:AVX512PF, t:SCATTER, a:MMASK, l:t1s, e:E12NP, w:P|R -VEXP2PS ; Voq{K}{z},Woq|B32{sae} ; ; evex m:2 p:1 l:2 w:0 0xC8 /r ; s:AVX512ER, t:KNL, l:fv, e:E2, w:W|R|R -VEXP2PD ; Voq{K}{z},Woq|B64{sae} ; ; evex m:2 p:1 l:2 w:1 0xC8 /r ; s:AVX512ER, t:KNL, l:fv, e:E2, w:W|R|R -VRCP28PS ; Voq{K}{z},Woq|B32{sae} ; ; evex m:2 p:1 l:2 w:0 0xCA /r ; s:AVX512ER, t:KNL, l:fv, e:E2, w:W|R|R -VRCP28PD ; Voq{K}{z},Woq|B64{sae} ; ; evex m:2 p:1 l:2 w:1 0xCA /r ; s:AVX512ER, t:KNL, l:fv, e:E2, w:W|R|R -VRCP28SS ; Vdq{K}{z},Hdq,Wss{sae} ; ; evex m:2 p:1 l:i w:0 0xCB /r ; s:AVX512ER, t:KNL, l:t1s, e:E3, w:W|R|R|R -VRCP28SD ; Vdq{K}{z},Hdq,Wsd{sae} ; ; evex m:2 p:1 l:i w:1 0xCB /r ; s:AVX512ER, t:KNL, l:t1s, e:E3, w:W|R|R|R -VRSQRT28PS ; Voq{K}{z},Woq|B32{sae} ; ; evex m:2 p:1 l:2 w:0 0xCC /r ; s:AVX512ER, t:KNL, l:fv, e:E2, w:W|R|R -VRSQRT28PD ; Voq{K}{z},Woq|B64{sae} ; ; evex m:2 p:1 l:2 w:1 0xCC /r ; s:AVX512ER, t:KNL, l:fv, e:E2, w:W|R|R -VRSQRT28SS ; Vdq{K}{z},Hdq,Wss{sae} ; ; evex m:2 p:1 l:i w:0 0xCD /r ; s:AVX512ER, t:KNL, l:t1s, e:E3, w:W|R|R|R -VRSQRT28SD ; Vdq{K}{z},Hdq,Wsd{sae} ; ; evex m:2 p:1 l:i w:1 0xCD /r ; s:AVX512ER, t:KNL, l:t1s, e:E3, w:W|R|R|R +VEXP2PS ; Voq{K}{z},Woq|B32{sae} ; ; evex m:2 p:1 l:2 w:0 0xC8 /r ; s:AVX512ER, t:KNL, l:fv, e:E2, w:W|R|R, x:IE|OE +VEXP2PD ; Voq{K}{z},Woq|B64{sae} ; ; evex m:2 p:1 l:2 w:1 0xC8 /r ; s:AVX512ER, t:KNL, l:fv, e:E2, w:W|R|R, x:IE|OE +VRCP28PS ; Voq{K}{z},Woq|B32{sae} ; ; evex m:2 p:1 l:2 w:0 0xCA /r ; s:AVX512ER, t:KNL, l:fv, e:E2, w:W|R|R, x:IE|ZE +VRCP28PD ; Voq{K}{z},Woq|B64{sae} ; ; evex m:2 p:1 l:2 w:1 0xCA /r ; s:AVX512ER, t:KNL, l:fv, e:E2, w:W|R|R, x:IE|ZE +VRCP28SS ; Vdq{K}{z},Hdq,Wss{sae} ; ; evex m:2 p:1 l:i w:0 0xCB /r ; s:AVX512ER, t:KNL, l:t1s, e:E3, w:W|R|R|R, x:IE|ZE +VRCP28SD ; Vdq{K}{z},Hdq,Wsd{sae} ; ; evex m:2 p:1 l:i w:1 0xCB /r ; s:AVX512ER, t:KNL, l:t1s, e:E3, w:W|R|R|R, x:IE|ZE +VRSQRT28PS ; Voq{K}{z},Woq|B32{sae} ; ; evex m:2 p:1 l:2 w:0 0xCC /r ; s:AVX512ER, t:KNL, l:fv, e:E2, w:W|R|R, x:IE|ZE +VRSQRT28PD ; Voq{K}{z},Woq|B64{sae} ; ; evex m:2 p:1 l:2 w:1 0xCC /r ; s:AVX512ER, t:KNL, l:fv, e:E2, w:W|R|R, x:IE|ZE +VRSQRT28SS ; Vdq{K}{z},Hdq,Wss{sae} ; ; evex m:2 p:1 l:i w:0 0xCD /r ; s:AVX512ER, t:KNL, l:t1s, e:E3, w:W|R|R|R, x:IE|ZE +VRSQRT28SD ; Vdq{K}{z},Hdq,Wsd{sae} ; ; evex m:2 p:1 l:i w:1 0xCD /r ; s:AVX512ER, t:KNL, l:t1s, e:E3, w:W|R|R|R, x:IE|ZE VGF2P8MULB ; Vfv{K}{z},Hfv,Wfv ; ; evex m:2 p:1 l:x w:0 0xCF /r ; s:GFNI, t:GFNI, l:fvm, e:E4, w:W|R|R|R # 0xD0 - 0xDF @@ -350,6 +359,8 @@ VPDPWSUD ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:2 l:x w:0 VPDPWUUDS ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:0 l:x w:0 0xD3 /r ; s:AVX102, t:AVX10INT, l:fv, e:E4, w:RW|R|R|R VPDPWUSDS ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:1 l:x w:0 0xD3 /r ; s:AVX102, t:AVX10INT, l:fv, e:E4, w:RW|R|R|R VPDPWSUDS ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:2 l:x w:0 0xD3 /r ; s:AVX102, t:AVX10INT, l:fv, e:E4, w:RW|R|R|R +VSM4KEY4 ; Vfv,Hfv,Wfv ; ; evex m:2 p:2 l:x w:0 0xDA /r ; s:SM4, t:SM4, l:fvm, e:E6, w:W|R|R +VSM4RNDS4 ; Vfv,Hfv,Wfv ; ; evex m:2 p:3 l:x w:0 0xDA /r ; s:SM4, t:SM4, l:fvm, e:E6, w:W|R|R VAESENC ; Vfv,Hfv,Wfv ; ; evex m:2 p:1 l:x w:i 0xDC /r ; s:VAES, t:VAES, l:fvm, e:E4NF, w:W|R|R VAESENCLAST ; Vfv,Hfv,Wfv ; ; evex m:2 p:1 l:x w:i 0xDD /r ; s:VAES, t:VAES, l:fvm, e:E4NF, w:W|R|R VAESDEC ; Vfv,Hfv,Wfv ; ; evex m:2 p:1 l:x w:i 0xDE /r ; s:VAES, t:VAES, l:fvm, e:E4NF, w:W|R|R diff --git a/isagenerator/instructions/table_evex_3.dat b/isagenerator/instructions/table_evex_3.dat index 6f3bd4d..6c2b29f 100644 --- a/isagenerator/instructions/table_evex_3.dat +++ b/isagenerator/instructions/table_evex_3.dat @@ -10,13 +10,19 @@ VALIGND ; Vfv{K}{z},Hfv,Wfv|B32,Ib ; ; evex m:3 p:1 l:x w:0 VALIGNQ ; Vfv{K}{z},Hfv,Wfv|B64,Ib ; ; evex m:3 p:1 l:x w:1 0x03 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R|R VPERMILPS ; Vfv{K}{z},Wfv|B32,Ib ; ; evex m:3 p:1 l:x w:0 0x04 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R VPERMILPD ; Vfv{K}{z},Wfv|B64,Ib ; ; evex m:3 p:1 l:x w:1 0x05 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R -VRNDSCALEPH ; Vfv{K}{z},Wfv|B16{sae},Ib ; ; evex m:3 p:0 l:x w:0 0x08 /r ib ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R -VRNDSCALEPS ; Vfv{K}{z},Wfv|B32{sae},Ib ; ; evex m:3 p:1 l:x w:0 0x08 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R + +TCVTROWPS2PHH ; Voq,mTt,Ib ; ; evex m:3 p:0 l:2 w:0 0x07 /r:reg ib ; s:AMXAVX512, t:AMX, e:AMX_EVEX_E7, w:W|R|R, m:NOTSX +TILEMOVROW ; Voq,mTt,Ib ; ; evex m:3 p:1 l:2 w:0 0x07 /r:reg ib ; s:AMXAVX512, t:AMX, e:AMX_EVEX_E7, w:W|R|R, m:NOTSX +TCVTROWD2PS ; Voq,mTt,Ib ; ; evex m:3 p:2 l:2 w:0 0x07 /r:reg ib ; s:AMXAVX512, t:AMX, e:AMX_EVEX_E7, w:W|R|R, m:NOTSX +TCVTROWPS2PBF16H ; Voq,mTt,Ib ; ; evex m:3 p:3 l:2 w:0 0x07 /r:reg ib ; s:AMXAVX512, t:AMX, e:AMX_EVEX_E7, w:W|R|R, m:NOTSX + +VRNDSCALEPH ; Vfv{K}{z},Wfv|B16{sae},Ib ; ; evex m:3 p:0 l:x w:0 0x08 /r ib ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R, x:IE|PE|UE +VRNDSCALEPS ; Vfv{K}{z},Wfv|B32{sae},Ib ; ; evex m:3 p:1 l:x w:0 0x08 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R, x:IE|PE VRNDSCALENEPBF16 ; Vfv{K}{z},Wfv|B16,Ib ; ; evex m:3 p:3 l:x w:0 0x08 /r ib ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:W|R|R|R -VRNDSCALEPD ; Vfv{K}{z},Wfv|B64{sae},Ib ; ; evex m:3 p:1 l:x w:1 0x09 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R -VRNDSCALESH ; Vdq{K}{z},Hdq,Wsh{sae},Ib ; ; evex m:3 p:0 l:i w:0 0x0A /r ib ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R|R -VRNDSCALESS ; Vdq{K}{z},Hdq,Wss{sae},Ib ; ; evex m:3 p:1 l:i w:0 0x0A /r ib ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R|R -VRNDSCALESD ; Vdq{K}{z},Hdq,Wsd{sae},Ib ; ; evex m:3 p:1 l:i w:1 0x0B /r ib ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R|R +VRNDSCALEPD ; Vfv{K}{z},Wfv|B64{sae},Ib ; ; evex m:3 p:1 l:x w:1 0x09 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R, x:IE|PE +VRNDSCALESH ; Vdq{K}{z},Hdq,Wsh{sae},Ib ; ; evex m:3 p:0 l:i w:0 0x0A /r ib ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R|R, x:IE|UE|PE +VRNDSCALESS ; Vdq{K}{z},Hdq,Wss{sae},Ib ; ; evex m:3 p:1 l:i w:0 0x0A /r ib ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R|R, x:IE|PE +VRNDSCALESD ; Vdq{K}{z},Hdq,Wsd{sae},Ib ; ; evex m:3 p:1 l:i w:1 0x0B /r ib ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R|R, x:IE|PE VPALIGNR ; Vfv{K}{z},Hfv,Wfv,Ib ; ; evex m:3 p:1 l:x w:i 0x0F /r ib ; s:AVX512BW, t:AVX512, l:fvm, e:E4NFnb, w:W|R|R|R|R # 0x10 - 0x1F @@ -38,7 +44,7 @@ VINSERTF32X8 ; Voq{K}{z},Hoq,Wqq,Ib ; ; evex m:3 p:1 l:2 w:0 VINSERTF64X4 ; Voq{K}{z},Hoq,Wqq,Ib ; ; evex m:3 p:1 l:2 w:1 0x1A /r ib ; s:AVX512F, t:AVX512, l:t4, e:E6NF, w:W|R|R|R|R VEXTRACTF32X8 ; Wqq{K}{z},Voq,Ib ; ; evex m:3 p:1 l:2 w:0 0x1B /r ib ; s:AVX512DQ, t:AVX512, l:t8, e:E6NF, w:W|R|R|R VEXTRACTF64X4 ; Wqq{K}{z},Voq,Ib ; ; evex m:3 p:1 l:2 w:1 0x1B /r ib ; s:AVX512F, t:AVX512, l:t4, e:E6NF, w:W|R|R|R -VCVTPS2PH ; Whv{K}{z},Vfv{sae},Ib ; ; evex m:3 p:1 l:x w:0 0x1D /r ib ; s:AVX512F, t:CONVERT, l:hvm, e:E11, w:W|R|R|R +VCVTPS2PH ; Whv{K}{z},Vfv{sae},Ib ; ; evex m:3 p:1 l:x w:0 0x1D /r ib ; s:AVX512F, t:CONVERT, l:hvm, e:E11, w:W|R|R|R, x:IE|OE|UE|PE|DE VPCMPUD ; rKq{K},Hfv,Wfv|B32,Ib ; ; evex m:3 p:1 l:x w:0 0x1E /r ib ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R|R VPCMPUQ ; rKq{K},Hfv,Wfv|B64,Ib ; ; evex m:3 p:1 l:x w:1 0x1E /r ib ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R|R VPCMPD ; rKq{K},Hfv,Wfv|B32,Ib ; ; evex m:3 p:1 l:x w:0 0x1F /r ib ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R|R @@ -55,13 +61,13 @@ VSHUFF32X4 ; Vuv{K}{z},Huv,Wuv|B32,Ib ; ; evex m:3 p:1 l:x w:0 VSHUFF64X2 ; Vuv{K}{z},Huv,Wuv|B64,Ib ; ; evex m:3 p:1 l:x w:1 0x23 /r ib ; s:AVX512F, t:AVX512, a:NOL0, l:fv, e:E4NF, w:W|R|R|R|R VPTERNLOGD ; Vfv{K}{z},Hfv,Wfv|B32,Ib ; ; evex m:3 p:1 l:x w:0 0x25 /r ib ; s:AVX512F, t:LOGICAL, l:fv, e:E4, w:RW|R|R|R|R VPTERNLOGQ ; Vfv{K}{z},Hfv,Wfv|B64,Ib ; ; evex m:3 p:1 l:x w:1 0x25 /r ib ; s:AVX512F, t:LOGICAL, l:fv, e:E4, w:RW|R|R|R|R -VGETMANTPH ; Vfv{K}{z},Wfv|B16{sae},Ib ; ; evex m:3 p:0 l:x w:0 0x26 /r ib ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R -VGETMANTPS ; Vfv{K}{z},Wfv|B32{sae},Ib ; ; evex m:3 p:1 l:x w:0 0x26 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R -VGETMANTPD ; Vfv{K}{z},Wfv|B64{sae},Ib ; ; evex m:3 p:1 l:x w:1 0x26 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R +VGETMANTPH ; Vfv{K}{z},Wfv|B16{sae},Ib ; ; evex m:3 p:0 l:x w:0 0x26 /r ib ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R, x:IE|DE +VGETMANTPS ; Vfv{K}{z},Wfv|B32{sae},Ib ; ; evex m:3 p:1 l:x w:0 0x26 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R, x:IE|DE +VGETMANTPD ; Vfv{K}{z},Wfv|B64{sae},Ib ; ; evex m:3 p:1 l:x w:1 0x26 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R, x:IE|DE VGETMANTPBF16 ; Vfv{K}{z},Wfv|B16,Ib ; ; evex m:3 p:3 l:x w:0 0x26 /r ib ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:W|R|R|R -VGETMANTSH ; Vdq{K}{z},Hdq,Wsh{sae},Ib ; ; evex m:3 p:0 l:i w:0 0x27 /r ib ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R|R -VGETMANTSS ; Vdq{K}{z},Hdq,Wss{sae},Ib ; ; evex m:3 p:1 l:i w:0 0x27 /r ib ; s:AVX512F, t:AVX512, l:t1s, e:E2, w:W|R|R|R|R -VGETMANTSD ; Vdq{K}{z},Hdq,Wsd{sae},Ib ; ; evex m:3 p:1 l:i w:1 0x27 /r ib ; s:AVX512F, t:AVX512, l:t1s, e:E2, w:W|R|R|R|R +VGETMANTSH ; Vdq{K}{z},Hdq,Wsh{sae},Ib ; ; evex m:3 p:0 l:i w:0 0x27 /r ib ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R|R, x:IE|DE +VGETMANTSS ; Vdq{K}{z},Hdq,Wss{sae},Ib ; ; evex m:3 p:1 l:i w:0 0x27 /r ib ; s:AVX512F, t:AVX512, l:t1s, e:E2, w:W|R|R|R|R, x:IE|DE +VGETMANTSD ; Vdq{K}{z},Hdq,Wsd{sae},Ib ; ; evex m:3 p:1 l:i w:1 0x27 /r ib ; s:AVX512F, t:AVX512, l:t1s, e:E2, w:W|R|R|R|R, x:IE|DE # 0x30 - 0x3F VINSERTI32X4 ; Vuv{K}{z},Huv,Wdq,Ib ; ; evex m:3 p:1 l:x w:0 0x38 /r ib ; s:AVX512F, t:AVX512, a:NOL0, l:t4, e:E6NF, w:W|R|R|R|R @@ -85,28 +91,28 @@ VSHUFI64X2 ; Vuv{K}{z},Huv,Wuv|B64,Ib ; ; evex m:3 p:1 l:x w:1 VPCLMULQDQ ; Vfv,Hfv,Wfv,Ib ; ; evex m:3 p:1 l:x w:i 0x44 /r ib ; s:VPCLMULQDQ, t:VPCLMULQDQ, l:fvm, e:E4NF, w:W|R|R|R # 0x50 - 0x5F -VRANGEPS ; Vfv{K}{z},Hfv,Wfv|B32{sae},Ib ; ; evex m:3 p:1 l:x w:0 0x50 /r ib ; s:AVX512DQ, t:AVX512, l:fv, e:E2, w:W|R|R|R|R -VRANGEPD ; Vfv{K}{z},Hfv,Wfv|B64{sae},Ib ; ; evex m:3 p:1 l:x w:1 0x50 /r ib ; s:AVX512DQ, t:AVX512, l:fv, e:E2, w:W|R|R|R|R -VRANGESS ; Vdq{K}{z},Hdq,Wss{sae},Ib ; ; evex m:3 p:1 l:i w:0 0x51 /r ib ; s:AVX512DQ, t:AVX512, l:t1s, e:E3, w:W|R|R|R|R -VRANGESD ; Vdq{K}{z},Hdq,Wsd{sae},Ib ; ; evex m:3 p:1 l:i w:1 0x51 /r ib ; s:AVX512DQ, t:AVX512, l:t1s, e:E3, w:W|R|R|R|R -VMINMAXPH ; Vfv{K}{z},Hfv,Wfv|B16{sae},Ib ; ; evex m:3 p:0 l:x w:0 0x52 /r ib ; s:AVX102, t:AVX10MINMAX, l:fv, e:E2, w:W|R|R|R|R -VMINMAXPS ; Vfv{K}{z},Hfv,Wfv|B32{sae},Ib ; ; evex m:3 p:1 l:x w:0 0x52 /r ib ; s:AVX102, t:AVX10MINMAX, l:fv, e:E2, w:W|R|R|R|R -VMINMAXPD ; Vfv{K}{z},Hfv,Wfv|B64{sae},Ib ; ; evex m:3 p:1 l:x w:1 0x52 /r ib ; s:AVX102, t:AVX10MINMAX, l:fv, e:E2, w:W|R|R|R|R +VRANGEPS ; Vfv{K}{z},Hfv,Wfv|B32{sae},Ib ; ; evex m:3 p:1 l:x w:0 0x50 /r ib ; s:AVX512DQ, t:AVX512, l:fv, e:E2, w:W|R|R|R|R, x:IE|DE +VRANGEPD ; Vfv{K}{z},Hfv,Wfv|B64{sae},Ib ; ; evex m:3 p:1 l:x w:1 0x50 /r ib ; s:AVX512DQ, t:AVX512, l:fv, e:E2, w:W|R|R|R|R, x:IE|DE +VRANGESS ; Vdq{K}{z},Hdq,Wss{sae},Ib ; ; evex m:3 p:1 l:i w:0 0x51 /r ib ; s:AVX512DQ, t:AVX512, l:t1s, e:E3, w:W|R|R|R|R, x:IE|DE +VRANGESD ; Vdq{K}{z},Hdq,Wsd{sae},Ib ; ; evex m:3 p:1 l:i w:1 0x51 /r ib ; s:AVX512DQ, t:AVX512, l:t1s, e:E3, w:W|R|R|R|R, x:IE|DE +VMINMAXPH ; Vfv{K}{z},Hfv,Wfv|B16{sae},Ib ; ; evex m:3 p:0 l:x w:0 0x52 /r ib ; s:AVX102, t:AVX10MINMAX, l:fv, e:E2, w:W|R|R|R|R, x:IE|DE +VMINMAXPS ; Vfv{K}{z},Hfv,Wfv|B32{sae},Ib ; ; evex m:3 p:1 l:x w:0 0x52 /r ib ; s:AVX102, t:AVX10MINMAX, l:fv, e:E2, w:W|R|R|R|R, x:IE|DE +VMINMAXPD ; Vfv{K}{z},Hfv,Wfv|B64{sae},Ib ; ; evex m:3 p:1 l:x w:1 0x52 /r ib ; s:AVX102, t:AVX10MINMAX, l:fv, e:E2, w:W|R|R|R|R, x:IE|DE VMINMAXNEPBF16 ; Vfv{K}{z},Hfv,Wfv|B16,Ib ; ; evex m:3 p:3 l:x w:0 0x52 /r ib ; s:AVX102, t:AVX10MINMAX, l:fv, e:E4, w:W|R|R|R|R -VMINMAXSH ; Vdq{K}{z},Hdq,Wsh{sae},Ib ; ; evex m:3 p:0 l:i w:0 0x53 /r ib ; s:AVX102, t:AVX10MINMAX, l:t1s, e:E3, w:W|R|R|R|R -VMINMAXSS ; Vdq{K}{z},Hdq,Wss{sae},Ib ; ; evex m:3 p:1 l:i w:0 0x53 /r ib ; s:AVX102, t:AVX10MINMAX, l:t1s, e:E3, w:W|R|R|R|R -VMINMAXSD ; Vdq{K}{z},Hdq,Wsd{sae},Ib ; ; evex m:3 p:1 l:i w:1 0x53 /r ib ; s:AVX102, t:AVX10MINMAX, l:t1s, e:E3, w:W|R|R|R|R -VFIXUPIMMPS ; Vfv{K}{z},Hfv,Wfv|B32{sae},Ib ; ; evex m:3 p:1 l:x w:0 0x54 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E2, w:RW|R|R|R|R -VFIXUPIMMPD ; Vfv{K}{z},Hfv,Wfv|B64{sae},Ib ; ; evex m:3 p:1 l:x w:1 0x54 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E2, w:RW|R|R|R|R -VFIXUPIMMSS ; Vdq{K}{z},Hdq,Wss{sae},Ib ; ; evex m:3 p:1 l:i w:0 0x55 /r ib ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:RW|R|R|R|R -VFIXUPIMMSD ; Vdq{K}{z},Hdq,Wsd{sae},Ib ; ; evex m:3 p:1 l:i w:1 0x55 /r ib ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:RW|R|R|R|R -VREDUCEPH ; Vfv{K}{z},Wfv|B16{sae},Ib ; ; evex m:3 p:0 l:x w:0 0x56 /r ib ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R -VREDUCEPS ; Vfv{K}{z},Wfv|B32{sae},Ib ; ; evex m:3 p:1 l:x w:0 0x56 /r ib ; s:AVX512DQ, t:AVX512, l:fv, e:E2, w:W|R|R|R -VREDUCEPD ; Vfv{K}{z},Wfv|B64{sae},Ib ; ; evex m:3 p:1 l:x w:1 0x56 /r ib ; s:AVX512DQ, t:AVX512, l:fv, e:E2, w:W|R|R|R +VMINMAXSH ; Vdq{K}{z},Hdq,Wsh{sae},Ib ; ; evex m:3 p:0 l:i w:0 0x53 /r ib ; s:AVX102, t:AVX10MINMAX, l:t1s, e:E3, w:W|R|R|R|R, x:IE|DE +VMINMAXSS ; Vdq{K}{z},Hdq,Wss{sae},Ib ; ; evex m:3 p:1 l:i w:0 0x53 /r ib ; s:AVX102, t:AVX10MINMAX, l:t1s, e:E3, w:W|R|R|R|R, x:IE|DE +VMINMAXSD ; Vdq{K}{z},Hdq,Wsd{sae},Ib ; ; evex m:3 p:1 l:i w:1 0x53 /r ib ; s:AVX102, t:AVX10MINMAX, l:t1s, e:E3, w:W|R|R|R|R, x:IE|DE +VFIXUPIMMPS ; Vfv{K}{z},Hfv,Wfv|B32{sae},Ib ; ; evex m:3 p:1 l:x w:0 0x54 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E2, w:RW|R|R|R|R, x:IE|ZE +VFIXUPIMMPD ; Vfv{K}{z},Hfv,Wfv|B64{sae},Ib ; ; evex m:3 p:1 l:x w:1 0x54 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E2, w:RW|R|R|R|R, x:IE|ZE +VFIXUPIMMSS ; Vdq{K}{z},Hdq,Wss{sae},Ib ; ; evex m:3 p:1 l:i w:0 0x55 /r ib ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:RW|R|R|R|R, x:IE|ZE +VFIXUPIMMSD ; Vdq{K}{z},Hdq,Wsd{sae},Ib ; ; evex m:3 p:1 l:i w:1 0x55 /r ib ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:RW|R|R|R|R, x:IE|ZE +VREDUCEPH ; Vfv{K}{z},Wfv|B16{sae},Ib ; ; evex m:3 p:0 l:x w:0 0x56 /r ib ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R, x:IE|PE +VREDUCEPS ; Vfv{K}{z},Wfv|B32{sae},Ib ; ; evex m:3 p:1 l:x w:0 0x56 /r ib ; s:AVX512DQ, t:AVX512, l:fv, e:E2, w:W|R|R|R, x:IE|PE +VREDUCEPD ; Vfv{K}{z},Wfv|B64{sae},Ib ; ; evex m:3 p:1 l:x w:1 0x56 /r ib ; s:AVX512DQ, t:AVX512, l:fv, e:E2, w:W|R|R|R, x:IE|PE VREDUCENEPBF16 ; Vfv{K}{z},Wfv|B16,Ib ; ; evex m:3 p:3 l:x w:0 0x56 /r ib ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:W|R|R|R -VREDUCESH ; Vdq{K}{z},Hdq,Wsh{sae},Ib ; ; evex m:3 p:0 l:i w:0 0x57 /r ib ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R|R -VREDUCESS ; Vdq{K}{z},Hdq,Wss{sae},Ib ; ; evex m:3 p:1 l:i w:0 0x57 /r ib ; s:AVX512DQ, t:AVX512, l:t1s, e:E3, w:W|R|R|R|R -VREDUCESD ; Vdq{K}{z},Hdq,Wsd{sae},Ib ; ; evex m:3 p:1 l:i w:1 0x57 /r ib ; s:AVX512DQ, t:AVX512, l:t1s, e:E3, w:W|R|R|R|R +VREDUCESH ; Vdq{K}{z},Hdq,Wsh{sae},Ib ; ; evex m:3 p:0 l:i w:0 0x57 /r ib ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R|R, x:IE|PE +VREDUCESS ; Vdq{K}{z},Hdq,Wss{sae},Ib ; ; evex m:3 p:1 l:i w:0 0x57 /r ib ; s:AVX512DQ, t:AVX512, l:t1s, e:E3, w:W|R|R|R|R, x:IE|PE +VREDUCESD ; Vdq{K}{z},Hdq,Wsd{sae},Ib ; ; evex m:3 p:1 l:i w:1 0x57 /r ib ; s:AVX512DQ, t:AVX512, l:t1s, e:E3, w:W|R|R|R|R, x:IE|PE # 0x60 - 0x6F VFPCLASSPH ; rKq{K},Wfv|B16,Ib ; ; evex m:3 p:0 l:x w:0 0x66 /r ib ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E4, w:W|R|R|R @@ -125,6 +131,9 @@ VPSHRDW ; Vfv{K}{z},Hfv,Wfv,Ib ; ; evex m:3 p:1 l:x w:1 VPSHRDD ; Vfv{K}{z},Hfv,Wfv|B32,Ib ; ; evex m:3 p:1 l:x w:0 0x73 /r ib ; s:AVX512VBMI2, t:AVX512VBMI, l:fv, e:E4, w:RW|R|R|R|R VPSHRDQ ; Vfv{K}{z},Hfv,Wfv|B64,Ib ; ; evex m:3 p:1 l:x w:1 0x73 /r ib ; s:AVX512VBMI2, t:AVX512VBMI, l:fv, e:E4, w:RW|R|R|R|R +TCVTROWPS2PBF16L ; Voq,mTt,Ib ; ; evex m:3 p:2 l:2 w:0 0x77 /r:reg ib ; s:AMXAVX512, t:AMX, e:AMX_EVEX_E7, w:W|R|R, m:NOTSX +TCVTROWPS2PHL ; Voq,mTt,Ib ; ; evex m:3 p:3 l:2 w:0 0x77 /r:reg ib ; s:AMXAVX512, t:AMX, e:AMX_EVEX_E7, w:W|R|R, m:NOTSX + # 0x80 - 0x8F # 0x90 - 0x9F @@ -134,12 +143,12 @@ VPSHRDQ ; Vfv{K}{z},Hfv,Wfv|B64,Ib ; ; evex m:3 p:1 l:x w:1 # 0xB0 - 0xBF # 0xC0 - 0xCF -VCMPPH ; rK{K},Hfv,Wfv|B16{sae},Ib ; ; evex m:3 p:0 l:x w:0 0xC2 /r ib ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R|R -VCMPSH ; rK{K},Hfv,Wsh{sae},Ib ; ; evex m:3 p:2 l:i w:0 0xC2 /r ib ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R|R +VCMPPH ; rK{K},Hfv,Wfv|B16{sae},Ib ; ; evex m:3 p:0 l:x w:0 0xC2 /r ib ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R|R, x:IE|DE +VCMPSH ; rK{K},Hfv,Wsh{sae},Ib ; ; evex m:3 p:2 l:i w:0 0xC2 /r ib ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R|R, x:IE|DE VCMPPBF16 ; rK{K},Hfv,Wfv|B16,Ib ; ; evex m:3 p:3 l:x w:0 0xC2 /r ib ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:W|R|R|R|R -VGF2P8AFFINEQB ; Vfv{K}{z},Hfv,Wfv|B64,Ib ; ; evex m:3 p:1 l:x w:1 0xCE /r ib ; s:GFNI, t:GFNI, l:fv, e:E4NF, w:W|R|R|R|R -VGF2P8AFFINEINVQB ; Vfv{K}{z},Hfv,Wfv|B64,Ib ; ; evex m:3 p:1 l:x w:1 0xCF /r ib ; s:GFNI, t:GFNI, l:fv, e:E4NF, w:W|R|R|R|R +VGF2P8AFFINEQB ; Vfv{K}{z},Hfv,Wfv|B64,Ib ; ; evex m:3 p:1 l:x w:1 0xCE /r ib ; s:GFNI, t:GFNI, l:fv, e:E4NF, w:W|R|R|R|R +VGF2P8AFFINEINVQB ; Vfv{K}{z},Hfv,Wfv|B64,Ib ; ; evex m:3 p:1 l:x w:1 0xCF /r ib ; s:GFNI, t:GFNI, l:fv, e:E4NF, w:W|R|R|R|R # 0xD0 - 0xDF diff --git a/isagenerator/instructions/table_evex_5.dat b/isagenerator/instructions/table_evex_5.dat index 79d50c3..09d4fef 100644 --- a/isagenerator/instructions/table_evex_5.dat +++ b/isagenerator/instructions/table_evex_5.dat @@ -8,111 +8,113 @@ VMOVSH ; Vdq{K}{z},Wsh ; ; evex m:5 p:2 l:i w:0 VMOVSH ; Vdq{K}{z},Hdq,Wsh ; ; evex m:5 p:2 l:i w:0 0x10 /r:reg ; s:AVX512FP16, t:AVX512FP16, e:E5, w:W|R|R|R VMOVSH ; Wsh{K},Vdq ; ; evex m:5 p:2 l:i w:0 0x11 /r:mem ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E5, w:W|R|R VMOVSH ; Wsh{K}{z},Hdq,Vdq ; ; evex m:5 p:2 l:i w:0 0x11 /r:reg ; s:AVX512FP16, t:AVX512FP16, e:E5, w:W|R|R|R -VCVTBIASPH2HF8 ; Vhv{K}{z},Hfv,Wfv|B16 ; ; evex m:5 p:0 l:x w:0 0x18 /r ; s:AVX102, t:AVX10CONVERT, l:fv, e:E4NF, w:W|R|R|R -VCVTNEPH2HF8 ; Vhv{K}{z},Wfv|B16 ; ; evex m:5 p:2 l:x w:0 0x18 /r ; s:AVX102, t:AVX10CONVERT, l:fv, e:E4NF, w:W|R|R -VCVTNE2PH2HF8 ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:5 p:3 l:x w:0 0x18 /r ; s:AVX102, t:AVX10CONVERT, l:fv, e:E4NF, w:W|R|R|R -VCVTBIASPH2HF8S ; Vhv{K}{z},Hfv,Wfv|B16 ; ; evex m:5 p:0 l:x w:0 0x1B /r ; s:AVX102, t:AVX10CONVERT, l:fv, e:E4NF, w:W|R|R|R -VCVTNEPH2HF8S ; Vhv{K}{z},Wfv|B16 ; ; evex m:5 p:2 l:x w:0 0x1B /r ; s:AVX102, t:AVX10CONVERT, l:fv, e:E4NF, w:W|R|R -VCVTNE2PH2HF8S ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:5 p:3 l:x w:0 0x1B /r ; s:AVX102, t:AVX10CONVERT, l:fv, e:E4NF, w:W|R|R|R -VCVTPS2PHX ; Vhv{K}{z},Wfv|B32{er} ; ; evex m:5 p:1 l:x w:0 0x1D /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R -VCVTSS2SH ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:5 p:0 l:i w:0 0x1D /r ; s:AVX512FP16, t:AVX512FP16, l:t1s, e:E3, w:W|R|R|R -VCVTHF82PH ; Vfv{K}{z},Whv ; ; evex m:5 p:3 l:x w:0 0x1E /r ; s:AVX102, t:AVX10CONVERT, l:hv, e:E2, w:W|R|R +VCVTBIASPH2HF8 ; Vhv{K}{z},Hfv,Wfv|B16 ; ; evex m:5 p:0 l:x w:0 0x18 /r ; s:AVX102, t:AVX10CONVERT, l:fv, e:E4NF, w:W|R|R|R, x:IE|OE|UE|PE|DE +VCVTNEPH2HF8 ; Vhv{K}{z},Wfv|B16 ; ; evex m:5 p:2 l:x w:0 0x18 /r ; s:AVX102, t:AVX10CONVERT, l:fv, e:E4NF, w:W|R|R, x:IE|OE|UE|PE|DE +VCVTNE2PH2HF8 ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:5 p:3 l:x w:0 0x18 /r ; s:AVX102, t:AVX10CONVERT, l:fv, e:E4NF, w:W|R|R|R, x:IE|OE|UE|PE|DE +VCVTBIASPH2HF8S ; Vhv{K}{z},Hfv,Wfv|B16 ; ; evex m:5 p:0 l:x w:0 0x1B /r ; s:AVX102, t:AVX10CONVERT, l:fv, e:E4NF, w:W|R|R|R, x:IE|OE|UE|PE|DE +VCVTNEPH2HF8S ; Vhv{K}{z},Wfv|B16 ; ; evex m:5 p:2 l:x w:0 0x1B /r ; s:AVX102, t:AVX10CONVERT, l:fv, e:E4NF, w:W|R|R, x:IE|OE|UE|PE|DE +VCVTNE2PH2HF8S ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:5 p:3 l:x w:0 0x1B /r ; s:AVX102, t:AVX10CONVERT, l:fv, e:E4NF, w:W|R|R|R, x:IE|OE|UE|PE|DE +VCVTPS2PHX ; Vhv{K}{z},Wfv|B32{er} ; ; evex m:5 p:1 l:x w:0 0x1D /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R, x:IE|OE|UE|PE|DE +VCVTSS2SH ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:5 p:0 l:i w:0 0x1D /r ; s:AVX512FP16, t:AVX512FP16, l:t1s, e:E3, w:W|R|R|R, x:IE|OE|UE|PE|DE +VCVTHF82PH ; Vfv{K}{z},Whv ; ; evex m:5 p:3 l:x w:0 0x1E /r ; s:AVX102, t:AVX10CONVERT, l:hv, e:E2, w:W|R|R, x:DE # 0x20 - 0x2F -VCVTSI2SH ; Vdq,Hdq,Ey ; ; evex m:5 p:2 l:i w:x 0x2A /r ; s:AVX512FP16, t:AVX512FP16, l:t1s, e:E3NF, w:W|R|R, a:IWO64 -VCVTTSH2SI ; Gy,Wsh{sae} ; ; evex m:5 p:2 l:i w:x 0x2C /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3NF, w:W|R, a:IWO64 -VCVTSH2SI ; Gy,Wsh{er} ; ; evex m:5 p:2 l:i w:x 0x2D /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3NF, w:W|R, a:IWO64 -VUCOMISH ; Vdq,Wsh{sae} ; Fv ; evex m:5 p:0 l:i w:0 0x2E /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3NF, w:R|R|W, f:ZF=m|PF=m|CF=m|OF=0|SF=0|AF=0 -VUCOMXSH ; Vdq,Wsh{sae} ; Fv ; evex m:5 p:3 l:0 w:0 0x2E /r ; s:AVX102, t:AVX10CMPSFP,l:t1s16, e:E3NF, w:R|R|W, f:CMPSFP -VCOMISH ; Vdq,Wsh{sae} ; Fv ; evex m:5 p:0 l:i w:0 0x2F /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3NF, w:R|R|W, f:ZF=m|PF=m|CF=m|OF=0|SF=0|AF=0 +VCVTSI2SH ; Vdq,Hdq,Ey ; ; evex m:5 p:2 l:i w:x 0x2A /r ; s:AVX512FP16, t:AVX512FP16, l:t1s, e:E3NF, w:W|R|R, a:IWO64, x:OE|PE +VCVTTSH2SI ; Gy,Wsh{sae} ; ; evex m:5 p:2 l:i w:x 0x2C /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3NF, w:W|R, a:IWO64, x:IE|PE +VCVTSH2SI ; Gy,Wsh{er} ; ; evex m:5 p:2 l:i w:x 0x2D /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3NF, w:W|R, a:IWO64, x:IE|PE +VUCOMISH ; Vdq,Wsh{sae} ; Fv ; evex m:5 p:0 l:i w:0 0x2E /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3NF, w:R|R|W, f:ZF=m|PF=m|CF=m|OF=0|SF=0|AF=0, x:IE|DE +VUCOMXSH ; Vdq,Wsh{sae} ; Fv ; evex m:5 p:2 l:i w:0 0x2E /r ; s:AVX102, t:AVX10CMPSFP,l:t1s16, e:E3NF, w:R|R|W, f:CMPSFP, x:IE|DE +VCOMISH ; Vdq,Wsh{sae} ; Fv ; evex m:5 p:0 l:i w:0 0x2F /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3NF, w:R|R|W, f:ZF=m|PF=m|CF=m|OF=0|SF=0|AF=0, x:IE|DE VCOMSBF16 ; Vdq,Wsh ; Fv ; evex m:5 p:1 l:i w:0 0x2F /r ; s:AVX102, t:AVX10BF16, l:t1s16, e:E10NF, w:R|R|W, f:ZF=m|PF=m|CF=m|OF=0|SF=0|AF=0 -VCOMXSH ; Vdq,Wsh{sae} ; Fv ; evex m:5 p:3 l:0 w:0 0x2F /r ; s:AVX102, t:AVX10CMPSFP,l:t1s16, e:E3NF, w:R|R|W, f:CMPSFP - -# 0x40 - 0x4F -VGETEXPPBF16 ; Vfv{K}{z},Wfv|B16 ; ; evex m:5 p:1 l:x w:0 0x42 /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:W|R|R +VCOMXSH ; Vdq,Wsh{sae} ; Fv ; evex m:5 p:2 l:i w:0 0x2F /r ; s:AVX102, t:AVX10CMPSFP,l:t1s16, e:E3NF, w:R|R|W, f:CMPSFP, x:IE|DE # 0x50 - 0x5F -VSQRTPH ; Vfv{K}{z},Wfv|B16{er} ; ; evex m:5 p:0 l:x w:0 0x51 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R +VSQRTPH ; Vfv{K}{z},Wfv|B16{er} ; ; evex m:5 p:0 l:x w:0 0x51 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R, x:IE|PE|DE VSQRTNEPBF16 ; Vfv{K}{z},Wfv|B16 ; ; evex m:5 p:1 l:x w:0 0x51 /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:W|R|R -VSQRTSH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:5 p:2 l:i w:0 0x51 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R -VADDPH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:5 p:0 l:x w:0 0x58 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R +VSQRTSH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:5 p:2 l:i w:0 0x51 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R, x:IE|PE|DE +VADDPH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:5 p:0 l:x w:0 0x58 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R, x:IE|OE|UE|PE|DE VADDNEPBF16 ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:5 p:1 l:x w:0 0x58 /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:W|R|R|R -VADDSH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:5 p:2 l:i w:0 0x58 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R -VMULPH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:5 p:0 l:x w:0 0x59 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R +VADDSH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:5 p:2 l:i w:0 0x58 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R, x:IE|OE|UE|PE|DE +VMULPH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:5 p:0 l:x w:0 0x59 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R, x:IE|OE|UE|PE|DE VMULNEPBF16 ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:5 p:1 l:x w:0 0x59 /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:W|R|R|R -VMULSH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:5 p:2 l:i w:0 0x59 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R -VCVTPH2PD ; Vfv{K}{z},Wqv|B16{sae} ; ; evex m:5 p:0 l:x w:0 0x5A /r ; s:AVX512FP16, t:AVX512FP16, l:qv, e:E2, w:W|R|R -VCVTPD2PH ; Vdq{K}{z},Wfv|B64{er} ; ; evex m:5 p:1 l:x w:1 0x5A /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R -VCVTSH2SD ; Vdq{K}{z},Hdq,Wsh{sae} ; ; evex m:5 p:2 l:i w:0 0x5A /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R -VCVTSD2SH ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:5 p:3 l:i w:1 0x5A /r ; s:AVX512FP16, t:AVX512FP16, l:t1s, e:E3, w:W|R|R|R -VCVTDQ2PH ; Vhv{K}{z},Wfv|B32{er} ; ; evex m:5 p:0 l:x w:0 0x5B /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R -VCVTQQ2PH ; Vdq{K}{z},Wfv|B64{er} ; ; evex m:5 p:0 l:x w:1 0x5B /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R -VCVTPH2DQ ; Vfv{K}{z},Whv|B16{er} ; ; evex m:5 p:1 l:x w:0 0x5B /r ; s:AVX512FP16, t:AVX512FP16, l:hv, e:E2, w:W|R|R -VCVTTPH2DQ ; Vfv{K}{z},Whv|B16{sae} ; ; evex m:5 p:2 l:x w:0 0x5B /r ; s:AVX512FP16, t:AVX512FP16, l:hv, e:E2, w:W|R|R -VSUBPH ; Vfv{K}{z},Hfv,Wfv|B16{sae} ; ; evex m:5 p:0 l:x w:0 0x5C /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R +VMULSH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:5 p:2 l:i w:0 0x59 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R, x:IE|OE|UE|PE|DE +VCVTPH2PD ; Vfv{K}{z},Wqv|B16{sae} ; ; evex m:5 p:0 l:x w:0 0x5A /r ; s:AVX512FP16, t:AVX512FP16, l:qv, e:E2, w:W|R|R, x:IE|PE +VCVTPD2PH ; Vdq{K}{z},Wfv|B64{er} ; ; evex m:5 p:1 l:x w:1 0x5A /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R, x:IE|OE|UE|PE|DE +VCVTSH2SD ; Vdq{K}{z},Hdq,Wsh{sae} ; ; evex m:5 p:2 l:i w:0 0x5A /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R, x:IE|DE +VCVTSD2SH ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:5 p:3 l:i w:1 0x5A /r ; s:AVX512FP16, t:AVX512FP16, l:t1s, e:E3, w:W|R|R|R, x:IE|OE|UE|PE|DE +VCVTDQ2PH ; Vhv{K}{z},Wfv|B32{er} ; ; evex m:5 p:0 l:x w:0 0x5B /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R, x:PE|OE +VCVTQQ2PH ; Vdq{K}{z},Wfv|B64{er} ; ; evex m:5 p:0 l:x w:1 0x5B /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R, x:PE|OE +VCVTPH2DQ ; Vfv{K}{z},Whv|B16{er} ; ; evex m:5 p:1 l:x w:0 0x5B /r ; s:AVX512FP16, t:AVX512FP16, l:hv, e:E2, w:W|R|R, x:IE|PE +VCVTTPH2DQ ; Vfv{K}{z},Whv|B16{sae} ; ; evex m:5 p:2 l:x w:0 0x5B /r ; s:AVX512FP16, t:AVX512FP16, l:hv, e:E2, w:W|R|R, x:IE|PE +VSUBPH ; Vfv{K}{z},Hfv,Wfv|B16{sae} ; ; evex m:5 p:0 l:x w:0 0x5C /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R, x:IE|OE|UE|PE|DE VSUBNEPBF16 ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:5 p:1 l:x w:0 0x5C /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:W|R|R|R -VSUBSH ; Vdq{K}{z},Hdq,Wsh{sae} ; ; evex m:5 p:2 l:i w:0 0x5C /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R -VMINPH ; Vfv{K}{z},Hfv,Wfv|B16{sae} ; ; evex m:5 p:0 l:x w:0 0x5D /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R +VSUBSH ; Vdq{K}{z},Hdq,Wsh{sae} ; ; evex m:5 p:2 l:i w:0 0x5C /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R, x:IE|OE|UE|PE|DE +VMINPH ; Vfv{K}{z},Hfv,Wfv|B16{sae} ; ; evex m:5 p:0 l:x w:0 0x5D /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R, x:IE|DE VMINPBF16 ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:5 p:1 l:x w:0 0x5D /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:W|R|R|R -VMINSH ; Vdq{K}{z},Hdq,Wsh{sae} ; ; evex m:5 p:2 l:i w:0 0x5D /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R -VDIVPH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:5 p:0 l:x w:0 0x5E /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R +VMINSH ; Vdq{K}{z},Hdq,Wsh{sae} ; ; evex m:5 p:2 l:i w:0 0x5D /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R, x:IE|DE +VDIVPH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:5 p:0 l:x w:0 0x5E /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R, x:IE|OE|UE|PE|DE|ZE VDIVNEPBF16 ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:5 p:1 l:x w:0 0x5E /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:W|R|R|R -VDIVSH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:5 p:2 l:i w:0 0x5E /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R -VMAXPH ; Vfv{K}{z},Hfv,Wfv|B16{sae} ; ; evex m:5 p:0 l:x w:0 0x5F /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R +VDIVSH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:5 p:2 l:i w:0 0x5E /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R, x:IE|OE|UE|PE|DE|ZE +VMAXPH ; Vfv{K}{z},Hfv,Wfv|B16{sae} ; ; evex m:5 p:0 l:x w:0 0x5F /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R, x:IE|DE VMAXPBF16 ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:5 p:1 l:x w:0 0x5F /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:W|R|R|R -VMAXSH ; Vdq{K}{z},Hdq,Wsh{sae} ; ; evex m:5 p:2 l:i w:0 0x5F /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R +VMAXSH ; Vdq{K}{z},Hdq,Wsh{sae} ; ; evex m:5 p:2 l:i w:0 0x5F /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R, x:IE|DE # 0x60 - 0x6F -VCVTTPH2IBS ; Vfv{K}{z},Wfv|B16{sae} ; ; evex m:5 p:0 l:x w:0 0x68 /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E2, w:W|R|R -VCVTTPS2IBS ; Vfv{K}{z},Wfv|B32{sae} ; ; evex m:5 p:1 l:x w:0 0x68 /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E2, w:W|R|R +VCVTTPH2IBS ; Vfv{K}{z},Wfv|B16{sae} ; ; evex m:5 p:0 l:x w:0 0x68 /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E2, w:W|R|R, x:IE|PE +VCVTTPS2IBS ; Vfv{K}{z},Wfv|B32{sae} ; ; evex m:5 p:1 l:x w:0 0x68 /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E2, w:W|R|R, x:IE|PE VCVTTNEBF162IBS ; Vfv{K}{z},Wfv|B16 ; ; evex m:5 p:3 l:x w:0 0x68 /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E4, w:W|R|R -VCVTPH2IBS ; Vfv{K}{z},Wfv|B16{er} ; ; evex m:5 p:0 l:x w:0 0x69 /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E2, w:W|R|R -VCVTPS2IBS ; Vfv{K}{z},Wfv|B32{er} ; ; evex m:5 p:1 l:x w:0 0x69 /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E2, w:W|R|R +VCVTPH2IBS ; Vfv{K}{z},Wfv|B16{er} ; ; evex m:5 p:0 l:x w:0 0x69 /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E2, w:W|R|R, x:IE|PE +VCVTPS2IBS ; Vfv{K}{z},Wfv|B32{er} ; ; evex m:5 p:1 l:x w:0 0x69 /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E2, w:W|R|R, x:IE|PE VCVTNEBF162IBS ; Vfv{K}{z},Wfv|B16 ; ; evex m:5 p:3 l:x w:0 0x69 /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E4, w:W|R|R -VCVTTPH2IUBS ; Vfv{K}{z},Wfv|B16{sae} ; ; evex m:5 p:0 l:x w:0 0x6A /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E2, w:W|R|R -VCVTTPS2IUBS ; Vfv{K}{z},Wfv|B32{sae} ; ; evex m:5 p:1 l:x w:0 0x6A /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E2, w:W|R|R +VCVTTPH2IUBS ; Vfv{K}{z},Wfv|B16{sae} ; ; evex m:5 p:0 l:x w:0 0x6A /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E2, w:W|R|R, x:IE|PE +VCVTTPS2IUBS ; Vfv{K}{z},Wfv|B32{sae} ; ; evex m:5 p:1 l:x w:0 0x6A /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E2, w:W|R|R, x:IE|PE VCVTTNEBF162IUBS ; Vfv{K}{z},Wfv|B16 ; ; evex m:5 p:3 l:x w:0 0x6A /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E4, w:W|R|R -VCVTPH2IUBS ; Vfv{K}{z},Wfv|B16{er} ; ; evex m:5 p:0 l:x w:0 0x6B /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E2, w:W|R|R -VCVTPS2IUBS ; Vfv{K}{z},Wfv|B32{er} ; ; evex m:5 p:1 l:x w:0 0x6B /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E2, w:W|R|R +VCVTPH2IUBS ; Vfv{K}{z},Wfv|B16{er} ; ; evex m:5 p:0 l:x w:0 0x6B /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E2, w:W|R|R, x:IE|PE +VCVTPS2IUBS ; Vfv{K}{z},Wfv|B32{er} ; ; evex m:5 p:1 l:x w:0 0x6B /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E2, w:W|R|R, x:IE|PE VCVTNEBF162IUBS ; Vfv{K}{z},Wfv|B16 ; ; evex m:5 p:3 l:x w:0 0x6B /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E4, w:W|R|R -VCVTTPS2UDQS ; Vfv{K}{z},Wfv|B32{sae} ; ; evex m:5 p:0 l:x w:0 0x6C /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E2, w:W|R|R -VCVTTPD2UDQS ; Vhv{K}{z},Wfv|B64{sae} ; ; evex m:5 p:0 l:x w:1 0x6C /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E2, w:W|R|R -VCVTTPS2UQQS ; Vfv{K}{z},Whv|B32{sae} ; ; evex m:5 p:1 l:x w:0 0x6C /r ; s:AVX102, t:AVX10SCONVERT, l:hv, e:E2, w:W|R|R -VCVTTPD2UQQS ; Vfv{K}{z},Wfv|B64{sae} ; ; evex m:5 p:1 l:x w:1 0x6C /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E2, w:W|R|R -VCVTTSS2USIS ; Gy,Wss{sae} ; ; evex m:5 p:2 l:i w:x 0x6C /r ; s:AVX102, t:AVX10SCONVERT, l:t1s, e:E3NF, w:W|R, a:IWO64 -VCVTTSD2USIS ; Gy,Wsd{sae} ; ; evex m:5 p:3 l:i w:x 0x6C /r ; s:AVX102, t:AVX10SCONVERT, l:t1s, e:E3NF, w:W|R, a:IWO64 -VCVTTPS2DQS ; Vfv{K}{z},Wfv|B32{sae} ; ; evex m:5 p:0 l:x w:0 0x6D /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E2, w:W|R|R -VCVTTPD2DQS ; Vhv{K}{z},Wfv|B64{sae} ; ; evex m:5 p:0 l:x w:1 0x6D /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E2, w:W|R|R -VCVTTPS2QQS ; Vfv{K}{z},Whv|B32{sae} ; ; evex m:5 p:1 l:x w:0 0x6D /r ; s:AVX102, t:AVX10SCONVERT, l:hv, e:E2, w:W|R|R -VCVTTPD2QQS ; Vfv{K}{z},Wfv|B64{sae} ; ; evex m:5 p:1 l:x w:1 0x6D /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E2, w:W|R|R -VCVTTSS2SIS ; Gy,Wss{sae} ; ; evex m:5 p:2 l:i w:x 0x6D /r ; s:AVX102, t:AVX10SCONVERT, l:t1s, e:E3NF, w:W|R, a:IWO64 -VCVTTSD2SIS ; Gy,Wsd{sae} ; ; evex m:5 p:3 l:i w:x 0x6D /r ; s:AVX102, t:AVX10SCONVERT, l:t1s, e:E3NF, w:W|R, a:IWO64 +VCVTTPS2UDQS ; Vfv{K}{z},Wfv|B32{sae} ; ; evex m:5 p:0 l:x w:0 0x6C /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E2, w:W|R|R, x:IE|PE +VCVTTPD2UDQS ; Vhv{K}{z},Wfv|B64{sae} ; ; evex m:5 p:0 l:x w:1 0x6C /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E2, w:W|R|R, x:IE|PE +VCVTTPS2UQQS ; Vfv{K}{z},Whv|B32{sae} ; ; evex m:5 p:1 l:x w:0 0x6C /r ; s:AVX102, t:AVX10SCONVERT, l:hv, e:E2, w:W|R|R, x:IE|PE +VCVTTPD2UQQS ; Vfv{K}{z},Wfv|B64{sae} ; ; evex m:5 p:1 l:x w:1 0x6C /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E2, w:W|R|R, x:IE|PE +VCVTTSS2USIS ; Gy,Wss{sae} ; ; evex m:5 p:2 l:i w:x 0x6C /r ; s:AVX102, t:AVX10SCONVERT, l:t1s, e:E3NF, w:W|R, a:IWO64, x:IE|PE +VCVTTSD2USIS ; Gy,Wsd{sae} ; ; evex m:5 p:3 l:i w:x 0x6C /r ; s:AVX102, t:AVX10SCONVERT, l:t1s, e:E3NF, w:W|R, a:IWO64, x:IE|PE +VCVTTPS2DQS ; Vfv{K}{z},Wfv|B32{sae} ; ; evex m:5 p:0 l:x w:0 0x6D /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E2, w:W|R|R, x:IE|PE +VCVTTPD2DQS ; Vhv{K}{z},Wfv|B64{sae} ; ; evex m:5 p:0 l:x w:1 0x6D /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E2, w:W|R|R, x:IE|PE +VCVTTPS2QQS ; Vfv{K}{z},Whv|B32{sae} ; ; evex m:5 p:1 l:x w:0 0x6D /r ; s:AVX102, t:AVX10SCONVERT, l:hv, e:E2, w:W|R|R, x:IE|PE +VCVTTPD2QQS ; Vfv{K}{z},Wfv|B64{sae} ; ; evex m:5 p:1 l:x w:1 0x6D /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E2, w:W|R|R, x:IE|PE +VCVTTSS2SIS ; Gy,Wss{sae} ; ; evex m:5 p:2 l:i w:x 0x6D /r ; s:AVX102, t:AVX10SCONVERT, l:t1s, e:E3NF, w:W|R, a:IWO64, x:IE|PE +VCVTTSD2SIS ; Gy,Wsd{sae} ; ; evex m:5 p:3 l:i w:x 0x6D /r ; s:AVX102, t:AVX10SCONVERT, l:t1s, e:E3NF, w:W|R, a:IWO64, x:IE|PE VMOVW ; Vdq,Mw ; ; evex m:5 p:1 l:0 w:i 0x6E /r:mem ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E9NF, w:W|R VMOVW ; Vdq,Rd ; ; evex m:5 p:1 l:0 w:i 0x6E /r:reg ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E9NF, w:W|R VMOVW ; Vdq,Ww ; ; evex m:5 p:2 l:0 w:0 0x6E /r ; s:AVX102, t:AVX10PARTCOPY, l:t1s16, e:E9NF, w:W|R +VMOVRSD ; Vfv{K}{z},Wfv ; ; evex m:5 p:2 l:x w:0 0x6F /r:mem ; s:MOVRS, t:DATAXFER, l:fvm, e:E4, w:W|R|R +VMOVRSB ; Vfv{K}{z},Wfv ; ; evex m:5 p:3 l:x w:0 0x6F /r:mem ; s:MOVRS, t:DATAXFER, l:fvm, e:E4, w:W|R|R +VMOVRSQ ; Vfv{K}{z},Wfv ; ; evex m:5 p:2 l:x w:1 0x6F /r:mem ; s:MOVRS, t:DATAXFER, l:fvm, e:E4, w:W|R|R +VMOVRSW ; Vfv{K}{z},Wfv ; ; evex m:5 p:3 l:x w:1 0x6F /r:mem ; s:MOVRS, t:DATAXFER, l:fvm, e:E4, w:W|R|R + # 0x70 - 0x7F -VCVTBIASPH2BF8S ; Vhv{K}{z},Hfv,Wfv|B16 ; ; evex m:5 p:0 l:x w:0 0x74 /r ; s:AVX102, t:AVX10CONVERT, l:fv, e:E4NF, w:W|R|R|R -VCVTNEPH2BF8S ; Vhv{K}{z},Wfv|B16 ; ; evex m:5 p:2 l:x w:0 0x74 /r ; s:AVX102, t:AVX10CONVERT, l:fv, e:E4NF, w:W|R|R -VCVTNE2PH2BF8S ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:5 p:3 l:x w:0 0x74 /r ; s:AVX102, t:AVX10CONVERT, l:fv, e:E4NF, w:W|R|R|R -VCVTTPH2UDQ ; Vfv{K}{z},Whv|B16{sae} ; ; evex m:5 p:0 l:x w:0 0x78 /r ; s:AVX512FP16, t:AVX512FP16, l:hv, e:E2, w:W|R|R -VCVTTPH2UQQ ; Vfv{K}{z},Wqv|B16{sae} ; ; evex m:5 p:1 l:x w:0 0x78 /r ; s:AVX512FP16, t:AVX512FP16, l:qv, e:E2, w:W|R|R -VCVTTSH2USI ; Gy,Wsh{sae} ; ; evex m:5 p:2 l:i w:0 0x78 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3NF, w:W|R, a:IWO64 -VCVTPH2UDQ ; Vfv{K}{z},Whv|B16{er} ; ; evex m:5 p:0 l:x w:0 0x79 /r ; s:AVX512FP16, t:AVX512FP16, l:hv, e:E2, w:W|R|R -VCVTPH2UQQ ; Vfv{K}{z},Wqv|B16{er} ; ; evex m:5 p:1 l:x w:0 0x79 /r ; s:AVX512FP16, t:AVX512FP16, l:qv, e:E2, w:W|R|R -VCVTSH2USI ; Gy,Wsh{er} ; ; evex m:5 p:2 l:i w:x 0x79 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3NF, w:W|R, a:IWO64 -VCVTUDQ2PH ; Vhv{K}{z},Wfv|B32{er} ; ; evex m:5 p:3 l:x w:0 0x7A /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R -VCVTUQQ2PH ; Vqv{K}{z},Wfv|B64{er} ; ; evex m:5 p:3 l:x w:1 0x7A /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R -VCVTTPH2QQ ; Vfv{K}{z},Wqv|B16{sae} ; ; evex m:5 p:1 l:x w:0 0x7A /r ; s:AVX512FP16, t:AVX512FP16, l:qv, e:E2, w:W|R|R -VCVTPH2QQ ; Vfv{K}{z},Wqv|B16{er} ; ; evex m:5 p:1 l:x w:0 0x7B /r ; s:AVX512FP16, t:AVX512FP16, l:qv, e:E2, w:W|R|R -VCVTUSI2SH ; Vdq,Hdq,Ey{er} ; ; evex m:5 p:2 l:i w:x 0x7B /r ; s:AVX512FP16, t:AVX512FP16, l:t1s, e:E3NF, w:W|R|R, a:IWO64 -VCVTTPH2UW ; Vfv{K}{z},Wfv|B16{sae} ; ; evex m:5 p:0 l:x w:0 0x7C /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R -VCVTTPH2W ; Vfv{K}{z},Wfv|B16{sae} ; ; evex m:5 p:1 l:x w:0 0x7C /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R -VCVTPH2UW ; Vfv{K}{z},Wfv|B16{er} ; ; evex m:5 p:0 l:x w:0 0x7D /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R -VCVTPH2W ; Vfv{K}{z},Wfv|B16{er} ; ; evex m:5 p:1 l:x w:0 0x7D /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R -VCVTW2PH ; Vfv{K}{z},Wfv|B16{er} ; ; evex m:5 p:2 l:x w:0 0x7D /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R -VCVTUW2PH ; Vfv{K}{z},Wfv|B16{er} ; ; evex m:5 p:3 l:x w:0 0x7D /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R +VCVTBIASPH2BF8S ; Vhv{K}{z},Hfv,Wfv|B16 ; ; evex m:5 p:0 l:x w:0 0x74 /r ; s:AVX102, t:AVX10CONVERT, l:fv, e:E4NF, w:W|R|R|R, x:IE|OE|UE|PE|DE +VCVTNEPH2BF8S ; Vhv{K}{z},Wfv|B16 ; ; evex m:5 p:2 l:x w:0 0x74 /r ; s:AVX102, t:AVX10CONVERT, l:fv, e:E4NF, w:W|R|R, x:IE|OE|UE|PE|DE +VCVTNE2PH2BF8S ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:5 p:3 l:x w:0 0x74 /r ; s:AVX102, t:AVX10CONVERT, l:fv, e:E4NF, w:W|R|R|R, x:IE|OE|UE|PE|DE +VCVTTPH2UDQ ; Vfv{K}{z},Whv|B16{sae} ; ; evex m:5 p:0 l:x w:0 0x78 /r ; s:AVX512FP16, t:AVX512FP16, l:hv, e:E2, w:W|R|R, x:IE|PE +VCVTTPH2UQQ ; Vfv{K}{z},Wqv|B16{sae} ; ; evex m:5 p:1 l:x w:0 0x78 /r ; s:AVX512FP16, t:AVX512FP16, l:qv, e:E2, w:W|R|R, x:IE|PE +VCVTTSH2USI ; Gy,Wsh{sae} ; ; evex m:5 p:2 l:i w:0 0x78 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3NF, w:W|R, a:IWO64, x:IE|PE +VCVTPH2UDQ ; Vfv{K}{z},Whv|B16{er} ; ; evex m:5 p:0 l:x w:0 0x79 /r ; s:AVX512FP16, t:AVX512FP16, l:hv, e:E2, w:W|R|R, x:IE|PE +VCVTPH2UQQ ; Vfv{K}{z},Wqv|B16{er} ; ; evex m:5 p:1 l:x w:0 0x79 /r ; s:AVX512FP16, t:AVX512FP16, l:qv, e:E2, w:W|R|R, x:IE|PE +VCVTSH2USI ; Gy,Wsh{er} ; ; evex m:5 p:2 l:i w:x 0x79 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3NF, w:W|R, a:IWO64, x:IE|PE +VCVTUDQ2PH ; Vhv{K}{z},Wfv|B32{er} ; ; evex m:5 p:3 l:x w:0 0x7A /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R, x:PE|OE +VCVTUQQ2PH ; Vqv{K}{z},Wfv|B64{er} ; ; evex m:5 p:3 l:x w:1 0x7A /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R, x:PE|OE +VCVTTPH2QQ ; Vfv{K}{z},Wqv|B16{sae} ; ; evex m:5 p:1 l:x w:0 0x7A /r ; s:AVX512FP16, t:AVX512FP16, l:qv, e:E2, w:W|R|R, x:IE|PE +VCVTPH2QQ ; Vfv{K}{z},Wqv|B16{er} ; ; evex m:5 p:1 l:x w:0 0x7B /r ; s:AVX512FP16, t:AVX512FP16, l:qv, e:E2, w:W|R|R, x:IE|PE +VCVTUSI2SH ; Vdq,Hdq,Ey{er} ; ; evex m:5 p:2 l:i w:x 0x7B /r ; s:AVX512FP16, t:AVX512FP16, l:t1s, e:E3NF, w:W|R|R, a:IWO64, x:IE|PE +VCVTTPH2UW ; Vfv{K}{z},Wfv|B16{sae} ; ; evex m:5 p:0 l:x w:0 0x7C /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R, x:IE|PE +VCVTTPH2W ; Vfv{K}{z},Wfv|B16{sae} ; ; evex m:5 p:1 l:x w:0 0x7C /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R, x:IE|PE +VCVTPH2UW ; Vfv{K}{z},Wfv|B16{er} ; ; evex m:5 p:0 l:x w:0 0x7D /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R, x:IE|PE +VCVTPH2W ; Vfv{K}{z},Wfv|B16{er} ; ; evex m:5 p:1 l:x w:0 0x7D /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R, x:IE|PE +VCVTW2PH ; Vfv{K}{z},Wfv|B16{er} ; ; evex m:5 p:2 l:x w:0 0x7D /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R, x:PE +VCVTUW2PH ; Vfv{K}{z},Wfv|B16{er} ; ; evex m:5 p:3 l:x w:0 0x7D /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R, x:PE|OE VMOVW ; Mw,Vdq ; ; evex m:5 p:1 l:0 w:i 0x7E /r:mem ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E9NF, w:W|R VMOVW ; Rd,Vdq ; ; evex m:5 p:1 l:0 w:i 0x7E /r:reg ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E9NF, w:W|R VMOVW ; Ww,Vdq ; ; evex m:5 p:2 l:0 w:0 0x7E /r ; s:AVX102, t:AVX10PARTCOPY, l:t1s16, e:E9NF, w:W|R diff --git a/isagenerator/instructions/table_evex_6.dat b/isagenerator/instructions/table_evex_6.dat index bfa47d6..4a962bb 100644 --- a/isagenerator/instructions/table_evex_6.dat +++ b/isagenerator/instructions/table_evex_6.dat @@ -4,17 +4,18 @@ # # 0x10 - 0x1F -VCVTSH2SS ; Vdq{K}{z},Hdq,Wsh{sae} ; ; evex m:6 p:0 l:i w:0 0x13 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R -VCVTPH2PSX ; Vfv{K}{z},Whv|B16{sae} ; ; evex m:6 p:1 l:x w:0 0x13 /r ; s:AVX512FP16, t:AVX512FP16, l:hv, e:E2, w:W|R|R +VCVTSH2SS ; Vdq{K}{z},Hdq,Wsh{sae} ; ; evex m:6 p:0 l:i w:0 0x13 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R, x:IE|DE +VCVTPH2PSX ; Vfv{K}{z},Whv|B16{sae} ; ; evex m:6 p:1 l:x w:0 0x13 /r ; s:AVX512FP16, t:AVX512FP16, l:hv, e:E2, w:W|R|R, x:IE|DE # 0x20 - 0x2F VSCALEFPBF16 ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:6 p:0 l:x w:0 0x2C /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:W|R|R|R -VSCALEFPH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0x2C /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R -VSCALEFSH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0x2D /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R +VSCALEFPH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0x2C /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R, x:IE|OE|UE|PE|DE +VSCALEFSH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0x2D /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R, x:IE|OE|UE|PE|DE # 0x40 - 0x4F -VGETEXPPH ; Vfv{K}{z},Wfv|B16{sae} ; ; evex m:6 p:1 l:x w:0 0x42 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R -VGETEXPSH ; Vdq{K}{z},Hdq,Wsh{sae} ; ; evex m:6 p:1 l:i w:0 0x43 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R +VGETEXPPBF16 ; Vfv{K}{z},Wfv|B16 ; ; evex m:6 p:0 l:x w:0 0x42 /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:W|R|R +VGETEXPPH ; Vfv{K}{z},Wfv|B16{sae} ; ; evex m:6 p:1 l:x w:0 0x42 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R, x:IE|DE +VGETEXPSH ; Vdq{K}{z},Hdq,Wsh{sae} ; ; evex m:6 p:1 l:i w:0 0x43 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R, x:IE|DE VRCPPBF16 ; Vfv{K}{z},Wfv|B16 ; ; evex m:6 p:0 l:x w:0 0x4C /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:W|R|R VRCPPH ; Vfv{K}{z},Wfv|B16 ; ; evex m:6 p:1 l:x w:0 0x4C /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E4, w:W|R|R VRCPSH ; Vdq{K}{z},Hdq,Wsh ; ; evex m:6 p:1 l:i w:0 0x4D /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E10, w:W|R|R|R @@ -23,61 +24,61 @@ VRSQRTPH ; Vfv{K}{z},Wfv|B16 ; ; evex m:6 p:1 l:x w:0 VRSQRTSH ; Vdq{K}{z},Hdq,Wsh ; ; evex m:6 p:1 l:i w:0 0x4F /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E10, w:W|R|R|R # 0x50 - 0x5F -VFMADDCPH ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:6 p:2 l:x w:0 0x56 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E4S, w:RW|R|R|R -VFCMADDCPH ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:6 p:3 l:x w:0 0x56 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E4S, w:RW|R|R|R -VFMADDCSH ; Vdq{K}{z},Hdq,Wd{er} ; ; evex m:6 p:2 l:i w:0 0x57 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s, e:E10S, w:RW|R|R|R -VFCMADDCSH ; Vdq{K}{z},Hdq,Wd{er} ; ; evex m:6 p:3 l:i w:0 0x57 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s, e:E10S, w:RW|R|R|R +VFMADDCPH ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:6 p:2 l:x w:0 0x56 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E4S, w:RW|R|R|R, x:IE|OE|UE|PE|DE +VFCMADDCPH ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:6 p:3 l:x w:0 0x56 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E4S, w:RW|R|R|R, x:IE|OE|UE|PE|DE +VFMADDCSH ; Vdq{K}{z},Hdq,Wd{er} ; ; evex m:6 p:2 l:i w:0 0x57 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s, e:E10S, w:RW|R|R|R, x:IE|OE|UE|PE|DE +VFCMADDCSH ; Vdq{K}{z},Hdq,Wd{er} ; ; evex m:6 p:3 l:i w:0 0x57 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s, e:E10S, w:RW|R|R|R, x:IE|OE|UE|PE|DE # 0x90 - 0x9F -VFMADDSUB132PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0x96 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R -VFMSUBADD132PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0x97 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R +VFMADDSUB132PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0x96 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE +VFMSUBADD132PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0x97 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE VFMADD132NEPBF16 ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:6 p:0 l:x w:0 0x98 /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:RW|R|R|R -VFMADD132PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0x98 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R -VFMADD132SH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0x99 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R +VFMADD132PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0x98 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE +VFMADD132SH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0x99 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R, x:IE|OE|UE|PE|DE VFMSUB132NEPBF16 ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:6 p:0 l:x w:0 0x9A /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:RW|R|R|R -VFMSUB132PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0x9A /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R -VFMSUB132SH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0x9B /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R +VFMSUB132PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0x9A /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE +VFMSUB132SH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0x9B /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R, x:IE|OE|UE|PE|DE VFNMADD132NEPBF16 ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:6 p:0 l:x w:0 0x9C /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:RW|R|R|R -VFNMADD132PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0x9C /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R -VFNMADD132SH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0x9D /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R +VFNMADD132PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0x9C /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE +VFNMADD132SH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0x9D /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R, x:IE|OE|UE|PE|DE VFNMSUB132NEPBF16 ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:6 p:0 l:x w:0 0x9E /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:RW|R|R|R -VFNMSUB132PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0x9E /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R -VFNMSUB132SH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0x9F /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R +VFNMSUB132PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0x9E /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE +VFNMSUB132SH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0x9F /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R, x:IE|OE|UE|PE|DE # 0xA0 - 0xAF -VFMADDSUB213PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0xA6 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R -VFMSUBADD213PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0xA7 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R +VFMADDSUB213PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0xA6 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE +VFMSUBADD213PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0xA7 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE VFMADD213NEPBF16 ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:6 p:0 l:x w:0 0xA8 /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:RW|R|R|R -VFMADD213PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0xA8 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R -VFMADD213SH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0xA9 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R +VFMADD213PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0xA8 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE +VFMADD213SH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0xA9 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R, x:IE|OE|UE|PE|DE VFMSUB213NEPBF16 ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:6 p:0 l:x w:0 0xAA /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:RW|R|R|R -VFMSUB213PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0xAA /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R -VFMSUB213SH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0xAB /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R +VFMSUB213PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0xAA /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE +VFMSUB213SH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0xAB /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R, x:IE|OE|UE|PE|DE VFNMADD213NEPBF16 ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:6 p:0 l:x w:0 0xAC /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:RW|R|R|R -VFNMADD213PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0xAC /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R -VFNMADD213SH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0xAD /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R +VFNMADD213PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0xAC /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE +VFNMADD213SH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0xAD /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R, x:IE|OE|UE|PE|DE VFNMSUB213NEPBF16 ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:6 p:0 l:x w:0 0xAE /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:RW|R|R|R -VFNMSUB213PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0xAE /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R -VFNMSUB213SH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0xAF /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R +VFNMSUB213PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0xAE /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE +VFNMSUB213SH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0xAF /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R, x:IE|OE|UE|PE|DE # 0xB0 - 0xBF -VFMADDSUB231PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0xB6 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R -VFMSUBADD231PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0xB7 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R +VFMADDSUB231PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0xB6 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE +VFMSUBADD231PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0xB7 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE VFMADD231NEPBF16 ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:6 p:0 l:x w:0 0xB8 /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:RW|R|R|R -VFMADD231PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0xB8 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R -VFMADD231SH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0xB9 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R +VFMADD231PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0xB8 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE +VFMADD231SH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0xB9 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R, x:IE|OE|UE|PE|DE VFMSUB231NEPBF16 ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:6 p:0 l:x w:0 0xBA /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:RW|R|R|R -VFMSUB231PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0xBA /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R -VFMSUB231SH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0xBB /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R +VFMSUB231PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0xBA /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE +VFMSUB231SH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0xBB /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R, x:IE|OE|UE|PE|DE VFNMADD231NEPBF16 ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:6 p:0 l:x w:0 0xBC /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:RW|R|R|R -VFNMADD231PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0xBC /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R -VFNMADD231SH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0xBD /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R +VFNMADD231PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0xBC /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE +VFNMADD231SH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0xBD /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R, x:IE|OE|UE|PE|DE VFNMSUB231NEPBF16 ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:6 p:0 l:x w:0 0xBE /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:RW|R|R|R -VFNMSUB231PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0xBE /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R -VFNMSUB231SH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0xBF /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R +VFNMSUB231PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0xBE /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE +VFNMSUB231SH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0xBF /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R, x:IE|OE|UE|PE|DE # 0xD0 - 0xD7 -VFMULCPH ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:6 p:2 l:x w:0 0xD6 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E4S, w:W|R|R|R -VFCMULCPH ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:6 p:3 l:x w:0 0xD6 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E4S, w:W|R|R|R -VFMULCSH ; Vdq{K}{z},Hdq,Wd{er} ; ; evex m:6 p:2 l:i w:0 0xD7 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s, e:E10S, w:W|R|R|R -VFCMULCSH ; Vdq{K}{z},Hdq,Wd{er} ; ; evex m:6 p:3 l:i w:0 0xD7 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s, e:E10S, w:W|R|R|R +VFMULCPH ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:6 p:2 l:x w:0 0xD6 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E4S, w:W|R|R|R, x:IE|OE|UE|PE|DE +VFCMULCPH ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:6 p:3 l:x w:0 0xD6 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E4S, w:W|R|R|R, x:IE|OE|UE|PE|DE +VFMULCSH ; Vdq{K}{z},Hdq,Wd{er} ; ; evex m:6 p:2 l:i w:0 0xD7 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s, e:E10S, w:W|R|R|R, x:IE|OE|UE|PE|DE +VFCMULCSH ; Vdq{K}{z},Hdq,Wd{er} ; ; evex m:6 p:3 l:i w:0 0xD7 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s, e:E10S, w:W|R|R|R, x:IE|OE|UE|PE|DE diff --git a/isagenerator/instructions/table_evex_7.dat b/isagenerator/instructions/table_evex_7.dat index a5c3d94..526da7e 100644 --- a/isagenerator/instructions/table_evex_7.dat +++ b/isagenerator/instructions/table_evex_7.dat @@ -3,5 +3,7 @@ # SPDX-License-Identifier: Apache-2.0 # -UWRMSR ; Id,Rq ; MSR ; evex m:7 nf:0 p:2 l:0 w:0 0xF8 /0:reg id ; s:APX_F, t:USER_MSR, w:R|R|W, m:O64, v:vex -URDMSR ; Rq,Id ; MSR ; evex m:7 nf:0 p:3 l:0 w:0 0xF8 /0:reg id ; s:APX_F, t:USER_MSR, w:W|R|R, m:O64, v:vex +WRMSRNS ; Id,Rq ; MSR ; evex m:7 nf:0 p:2 l:0 w:0 0xF6 /0:reg id ; s:MSR_IMM, t:SYSTEM, w:R|R|W, m:KERNEL|O64, v:vex +RDMSR ; Rq,Id ; MSR ; evex m:7 nf:0 p:3 l:0 w:0 0xF6 /0:reg id ; s:MSR_IMM, t:SYSTEM, w:W|R|R, m:KERNEL|O64, v:vex +UWRMSR ; Id,Rq ; MSR ; evex m:7 nf:0 p:2 l:0 w:0 0xF8 /0:reg id ; s:APX_F, t:USER_MSR, w:R|R|W, m:O64, v:vex +URDMSR ; Rq,Id ; MSR ; evex m:7 nf:0 p:3 l:0 w:0 0xF8 /0:reg id ; s:APX_F, t:USER_MSR, w:W|R|R, m:O64, v:vex diff --git a/isagenerator/instructions/table_legacy_1.dat b/isagenerator/instructions/table_legacy_1.dat index b47a67c..6cdbd87 100644 --- a/isagenerator/instructions/table_legacy_1.dat +++ b/isagenerator/instructions/table_legacy_1.dat @@ -157,7 +157,8 @@ PREFETCHT1 ; Mb ; ; 0x0F 0x18 /2:m NOP ; Ev ; ; 0x0F 0x18 /2:reg ; s:PPRO, t:WIDENOP, w:N PREFETCHT2 ; Mb ; ; 0x0F 0x18 /3:mem ; s:SSE, t:PREFETCH, w:P NOP ; Ev ; ; 0x0F 0x18 /3:reg ; s:PPRO, t:WIDENOP, w:N -NOP ; Ev ; ; 0x0F 0x18 /4 ; s:PPRO, t:WIDENOP, w:N +PREFETCHRST2 ; Mb ; ; 0x0F 0x18 /4:mem ; s:MOVRS, t:PREFETCH, w:P +NOP ; Ev ; ; 0x0F 0x18 /4:reg ; s:PPRO, t:WIDENOP, w:N NOP ; Ev ; ; 0x0F 0x18 /5 ; s:PPRO, t:WIDENOP, w:N NOP ; Ev ; ; 0x0F 0x18 /6 ; s:PPRO, t:WIDENOP, w:N NOP ; Ev ; ; 0x0F 0x18 /7 ; s:PPRO, t:WIDENOP, w:N @@ -173,7 +174,8 @@ PREFETCHT1 ; Mb ; ; piti 0x0F 0x18 /2:m NOP ; Ev ; ; piti 0x0F 0x18 /2:reg ; s:PPRO, t:WIDENOP, w:N PREFETCHT2 ; Mb ; ; piti 0x0F 0x18 /3:mem ; s:SSE, t:PREFETCH, w:P NOP ; Ev ; ; piti 0x0F 0x18 /3:reg ; s:PPRO, t:WIDENOP, w:N -NOP ; Ev ; ; piti 0x0F 0x18 /4 ; s:PPRO, t:WIDENOP, w:N +PREFETCHRST2 ; Mb ; ; piti 0x0F 0x18 /4:mem ; s:MOVRS, t:PREFETCH, w:P +NOP ; Ev ; ; piti 0x0F 0x18 /4:reg ; s:PPRO, t:WIDENOP, w:N NOP ; Ev ; ; piti 0x0F 0x18 /5 ; s:PPRO, t:WIDENOP, w:N PREFETCHIT1 ; Mb ; ;piti riprel 0x0F 0x18 /6:mem ; s:PREFETCHITI, t:PREFETCH, w:N, m:O64 NOP ; Ev ; ; piti 0x0F 0x18 /6:mem ; s:PPRO, t:WIDENOP, w:N @@ -264,26 +266,26 @@ MOVAPS ; Vps,Wps ; ; NP 0x0F 0x28 /r MOVAPD ; Vpd,Wpd ; ; 0x66 0x0F 0x28 /r ; s:SSE2, t:DATAXFER, w:W|R, e:1 MOVAPS ; Wps,Vps ; ; NP 0x0F 0x29 /r ; s:SSE, t:DATAXFER, w:W|R, e:1 MOVAPD ; Wpd,Vpd ; ; 0x66 0x0F 0x29 /r ; s:SSE2, t:DATAXFER, w:W|R, e:1 -CVTPI2PS ; Vq,Qq ; ; NP 0x0F 0x2A /r ; s:SSE, t:CONVERT, w:W|R -CVTPI2PD ; Vpd,Qq ; ; 0x66 0x0F 0x2A /r ; s:SSE2, t:CONVERT, w:W|R -CVTSI2SS ; Vss,Ey ; ; 0xF3 0x0F 0x2A /r ; s:SSE, t:CONVERT, w:W|R, e:3 -CVTSI2SD ; Vsd,Ey ; ; 0xF2 0x0F 0x2A /r ; s:SSE2, t:CONVERT, w:W|R, e:3 +CVTPI2PS ; Vq,Qq ; ; NP 0x0F 0x2A /r ; s:SSE, t:CONVERT, w:W|R, x:PE +CVTPI2PD ; Vpd,Qq ; ; 0x66 0x0F 0x2A /r ; s:SSE2, t:CONVERT, w:W|R, x:PE +CVTSI2SS ; Vss,Ey ; ; 0xF3 0x0F 0x2A /r ; s:SSE, t:CONVERT, w:W|R, e:3, x:PE +CVTSI2SD ; Vsd,Ey ; ; 0xF2 0x0F 0x2A /r ; s:SSE2, t:CONVERT, w:W|R, e:3, x:PE MOVNTPS ; Mps,Vps ; ; NP 0x0F 0x2B /r:mem ; s:SSE, t:DATAXFER, w:W|R, e:1 MOVNTPD ; Mpd,Vpd ; ; 0x66 0x0F 0x2B /r:mem ; s:SSE2, t:DATAXFER, w:W|R, e:1 MOVNTSS ; Mss,Vss ; ; 0xF3 0x0F 0x2B /r:mem ; s:SSE4A, t:DATAXFER, w:W|R MOVNTSD ; Msd,Vsd ; ; 0xF2 0x0F 0x2B /r:mem ; s:SSE4A, t:DATAXFER, w:W|R -CVTTPS2PI ; Pq,Wq ; ; NP 0x0F 0x2C /r ; s:SSE, t:CONVERT, w:W|R -CVTTPD2PI ; Pq,Wpd ; ; 0x66 0x0F 0x2C /r ; s:SSE2, t:CONVERT, w:W|R -CVTTSS2SI ; Gy,Wss ; ; 0xF3 0x0F 0x2C /r ; s:SSE, t:CONVERT, w:W|R, e:3 -CVTTSD2SI ; Gy,Wsd ; ; 0xF2 0x0F 0x2C /r ; s:SSE2, t:CONVERT, w:W|R, e:3 -CVTPS2PI ; Pq,Wq ; ; NP 0x0F 0x2D /r ; s:SSE, t:CONVERT, w:W|R -CVTPD2PI ; Pq,Wpd ; ; 0x66 0x0F 0x2D /r ; s:SSE2, t:CONVERT, w:W|R -CVTSS2SI ; Gy,Wss ; ; 0xF3 0x0F 0x2D /r ; s:SSE, t:CONVERT, w:W|R, e:3 -CVTSD2SI ; Gy,Wsd ; ; 0xF2 0x0F 0x2D /r ; s:SSE2, t:CONVERT, w:W|R, e:3 -UCOMISS ; Vss,Wss ; Fv ; NP 0x0F 0x2E /r ; s:SSE, t:SSE, w:R|R|W, f:COMIS -UCOMISD ; Vsd,Wsd ; Fv ; 0x66 0x0F 0x2E /r ; s:SSE2, t:SSE2, w:R|R|W, f:COMIS, e:3 -COMISS ; Vss,Wss ; Fv ; NP 0x0F 0x2F /r ; s:SSE, t:SSE, w:R|R|W, f:COMIS, e:3 -COMISD ; Vsd,Wsd ; Fv ; 0x66 0x0F 0x2F /r ; s:SSE2, t:SSE2, w:R|R|W, f:COMIS, e:3 +CVTTPS2PI ; Pq,Wq ; ; NP 0x0F 0x2C /r ; s:SSE, t:CONVERT, w:W|R, x:IE|PE +CVTTPD2PI ; Pq,Wpd ; ; 0x66 0x0F 0x2C /r ; s:SSE2, t:CONVERT, w:W|R, x:IE|PE +CVTTSS2SI ; Gy,Wss ; ; 0xF3 0x0F 0x2C /r ; s:SSE, t:CONVERT, w:W|R, e:3, x:IE|PE +CVTTSD2SI ; Gy,Wsd ; ; 0xF2 0x0F 0x2C /r ; s:SSE2, t:CONVERT, w:W|R, e:3, x:IE|PE +CVTPS2PI ; Pq,Wq ; ; NP 0x0F 0x2D /r ; s:SSE, t:CONVERT, w:W|R, x:IE|PE +CVTPD2PI ; Pq,Wpd ; ; 0x66 0x0F 0x2D /r ; s:SSE2, t:CONVERT, w:W|R, x:IE|PE +CVTSS2SI ; Gy,Wss ; ; 0xF3 0x0F 0x2D /r ; s:SSE, t:CONVERT, w:W|R, e:3, x:IE|PE +CVTSD2SI ; Gy,Wsd ; ; 0xF2 0x0F 0x2D /r ; s:SSE2, t:CONVERT, w:W|R, e:3, x:IE|PE +UCOMISS ; Vss,Wss ; Fv ; NP 0x0F 0x2E /r ; s:SSE, t:SSE, w:R|R|W, f:COMIS, e:3, x:IE|DE +UCOMISD ; Vsd,Wsd ; Fv ; 0x66 0x0F 0x2E /r ; s:SSE2, t:SSE2, w:R|R|W, f:COMIS, e:3, x:IE|DE +COMISS ; Vss,Wss ; Fv ; NP 0x0F 0x2F /r ; s:SSE, t:SSE, w:R|R|W, f:COMIS, e:3, x:IE|DE +COMISD ; Vsd,Wsd ; Fv ; 0x66 0x0F 0x2F /r ; s:SSE2, t:SSE2, w:R|R|W, f:COMIS, e:3, x:IE|DE # 0x30 - 0x3F WRMSR ; ; EAX,EDX,ECX,MSR ; 0x0F 0x30 ; s:PENTIUMREAL, t:SYSTEM, w:R|R|R|W, a:SERIAL|NOREX2, m:KERNEL|NOV86, i:MSR @@ -316,10 +318,10 @@ CMOVNLE ; Gv,Ev ; Fv ; 0x0F 0x4F /r # Note: for MOVMSKPS & MOVMSKPD, the Intel doc says the destination reg is y (32 or 64 bit). MOVMSKPS ; Gy,Ups ; ; NP 0x0F 0x50 /r:reg ; s:SSE, t:DATAXFER, w:W|R, e:7, a:D64 MOVMSKPD ; Gy,Upd ; ; 0x66 0x0F 0x50 /r:reg ; s:SSE2, t:DATAXFER, w:W|R, e:7, a:D64 -SQRTPS ; Vps,Wps ; ; NP 0x0F 0x51 /r ; s:SSE, t:SSE, w:W|R, e:2 -SQRTPD ; Vpd,Wpd ; ; 0x66 0x0F 0x51 /r ; s:SSE2, t:SSE, w:W|R, e:2 -SQRTSS ; Vss,Wss ; ; 0xF3 0x0F 0x51 /r ; s:SSE, t:SSE, w:W|R, e:3 -SQRTSD ; Vsd,Wsd ; ; 0xF2 0x0F 0x51 /r ; s:SSE2, t:SSE, w:W|R, e:3 +SQRTPS ; Vps,Wps ; ; NP 0x0F 0x51 /r ; s:SSE, t:SSE, w:W|R, e:2, x:IE|PE|DE +SQRTPD ; Vpd,Wpd ; ; 0x66 0x0F 0x51 /r ; s:SSE2, t:SSE, w:W|R, e:2, x:IE|PE|DE +SQRTSS ; Vss,Wss ; ; 0xF3 0x0F 0x51 /r ; s:SSE, t:SSE, w:W|R, e:3, x:IE|PE|DE +SQRTSD ; Vsd,Wsd ; ; 0xF2 0x0F 0x51 /r ; s:SSE2, t:SSE, w:W|R, e:3, x:IE|PE|DE RSQRTPS ; Vps,Wps ; ; NP 0x0F 0x52 /r ; s:SSE, t:SSE, w:W|R, e:4 RSQRTSS ; Vss,Wss ; ; 0xF3 0x0F 0x52 /r ; s:SSE, t:SSE, w:W|R, e:5 RCPPS ; Vps,Wps ; ; NP 0x0F 0x53 /r ; s:SSE, t:SSE, w:W|R, e:4 @@ -332,37 +334,37 @@ ORPS ; Vps,Wps ; ; NP 0x0F 0x56 /r ORPD ; Vpd,Wpd ; ; 0x66 0x0F 0x56 /r ; s:SSE2, t:LOGICAL_FP, w:RW|R, e:4 XORPS ; Vps,Wps ; ; NP 0x0F 0x57 /r ; s:SSE, t:LOGICAL_FP, w:RW|R, e:4 XORPD ; Vpd,Wpd ; ; 0x66 0x0F 0x57 /r ; s:SSE2, t:LOGICAL_FP, w:RW|R, e:4 -ADDPS ; Vps,Wps ; ; NP 0x0F 0x58 /r ; s:SSE, t:SSE, w:RW|R, e:2 -ADDPD ; Vpd,Wpd ; ; 0x66 0x0F 0x58 /r ; s:SSE2, t:SSE, w:RW|R, e:2 -ADDSS ; Vss,Wss ; ; 0xF3 0x0F 0x58 /r ; s:SSE, t:SSE, w:RW|R, e:3 -ADDSD ; Vsd,Wsd ; ; 0xF2 0x0F 0x58 /r ; s:SSE2, t:SSE, w:RW|R, e:3 -MULPS ; Vps,Wps ; ; NP 0x0F 0x59 /r ; s:SSE, t:SSE, w:RW|R, e:2 -MULPD ; Vpd,Wpd ; ; 0x66 0x0F 0x59 /r ; s:SSE2, t:SSE, w:RW|R, e:2 -MULSS ; Vss,Wss ; ; 0xF3 0x0F 0x59 /r ; s:SSE, t:SSE, w:RW|R, e:3 -MULSD ; Vsd,Wsd ; ; 0xF2 0x0F 0x59 /r ; s:SSE2, t:SSE, w:RW|R, e:3 -CVTPS2PD ; Vpd,Wq ; ; NP 0x0F 0x5A /r ; s:SSE2, t:CONVERT, w:W|R, e:3 -CVTPD2PS ; Vps,Wpd ; ; 0x66 0x0F 0x5A /r ; s:SSE2, t:CONVERT, w:W|R, e:2 -CVTSS2SD ; Vsd,Wss ; ; 0xF3 0x0F 0x5A /r ; s:SSE2, t:CONVERT, w:W|R, e:3 -CVTSD2SS ; Vss,Wsd ; ; 0xF2 0x0F 0x5A /r ; s:SSE2, t:CONVERT, w:W|R, e:3 -CVTDQ2PS ; Vps,Wdq ; ; NP 0x0F 0x5B /r ; s:SSE2, t:CONVERT, w:W|R, e:2 -CVTPS2DQ ; Vdq,Wps ; ; 0x66 0x0F 0x5B /r ; s:SSE2, t:CONVERT, w:W|R, e:2 -CVTTPS2DQ ; Vdq,Wps ; ; 0xF3 0x0F 0x5B /r ; s:SSE2, t:CONVERT, w:W|R, e:2 -SUBPS ; Vps,Wps ; ; NP 0x0F 0x5C /r ; s:SSE, t:SSE, w:RW|R, e:2 -SUBPD ; Vpd,Wpd ; ; 0x66 0x0F 0x5C /r ; s:SSE2, t:SSE, w:RW|R, e:2 -SUBSS ; Vss,Wss ; ; 0xF3 0x0F 0x5C /r ; s:SSE, t:SSE, w:RW|R, e:3 -SUBSD ; Vsd,Wsd ; ; 0xF2 0x0F 0x5C /r ; s:SSE2, t:SSE, w:RW|R, e:3 -MINPS ; Vps,Wps ; ; NP 0x0F 0x5D /r ; s:SSE, t:SSE, w:RW|R, e:2 -MINPD ; Vpd,Wpd ; ; 0x66 0x0F 0x5D /r ; s:SSE2, t:SSE, w:RW|R, e:2 -MINSS ; Vss,Wss ; ; 0xF3 0x0F 0x5D /r ; s:SSE, t:SSE, w:RW|R, e:3 -MINSD ; Vsd,Wsd ; ; 0xF2 0x0F 0x5D /r ; s:SSE2, t:SSE, w:RW|R, e:3 -DIVPS ; Vps,Wps ; ; NP 0x0F 0x5E /r ; s:SSE, t:SSE, w:RW|R, e:2 -DIVPD ; Vpd,Wpd ; ; 0x66 0x0F 0x5E /r ; s:SSE2, t:SSE, w:RW|R, e:2 -DIVSS ; Vss,Wss ; ; 0xF3 0x0F 0x5E /r ; s:SSE, t:SSE, w:RW|R, e:3 -DIVSD ; Vsd,Wsd ; ; 0xF2 0x0F 0x5E /r ; s:SSE2, t:SSE, w:RW|R, e:3 -MAXPS ; Vps,Wps ; ; NP 0x0F 0x5F /r ; s:SSE, t:SSE, w:RW|R, e:2 -MAXPD ; Vpd,Wpd ; ; 0x66 0x0F 0x5F /r ; s:SSE2, t:SSE, w:RW|R, e:2 -MAXSS ; Vss,Wss ; ; 0xF3 0x0F 0x5F /r ; s:SSE, t:SSE, w:RW|R, e:3 -MAXSD ; Vsd,Wsd ; ; 0xF2 0x0F 0x5F /r ; s:SSE2, t:SSE, w:RW|R, e:3 +ADDPS ; Vps,Wps ; ; NP 0x0F 0x58 /r ; s:SSE, t:SSE, w:RW|R, e:2, x:IE|OE|UE|PE|DE +ADDPD ; Vpd,Wpd ; ; 0x66 0x0F 0x58 /r ; s:SSE2, t:SSE, w:RW|R, e:2, x:IE|OE|UE|PE|DE +ADDSS ; Vss,Wss ; ; 0xF3 0x0F 0x58 /r ; s:SSE, t:SSE, w:RW|R, e:3, x:IE|OE|UE|PE|DE +ADDSD ; Vsd,Wsd ; ; 0xF2 0x0F 0x58 /r ; s:SSE2, t:SSE, w:RW|R, e:3, x:IE|OE|UE|PE|DE +MULPS ; Vps,Wps ; ; NP 0x0F 0x59 /r ; s:SSE, t:SSE, w:RW|R, e:2, x:IE|OE|UE|PE|DE +MULPD ; Vpd,Wpd ; ; 0x66 0x0F 0x59 /r ; s:SSE2, t:SSE, w:RW|R, e:2, x:IE|OE|UE|PE|DE +MULSS ; Vss,Wss ; ; 0xF3 0x0F 0x59 /r ; s:SSE, t:SSE, w:RW|R, e:3, x:IE|OE|UE|PE|DE +MULSD ; Vsd,Wsd ; ; 0xF2 0x0F 0x59 /r ; s:SSE2, t:SSE, w:RW|R, e:3, x:IE|OE|UE|PE|DE +CVTPS2PD ; Vpd,Wq ; ; NP 0x0F 0x5A /r ; s:SSE2, t:CONVERT, w:W|R, e:3, x:IE|DE +CVTPD2PS ; Vps,Wpd ; ; 0x66 0x0F 0x5A /r ; s:SSE2, t:CONVERT, w:W|R, e:2, x:IE|OE|UE|PE|DE +CVTSS2SD ; Vsd,Wss ; ; 0xF3 0x0F 0x5A /r ; s:SSE2, t:CONVERT, w:W|R, e:3, x:IE|DE +CVTSD2SS ; Vss,Wsd ; ; 0xF2 0x0F 0x5A /r ; s:SSE2, t:CONVERT, w:W|R, e:3, x:IE|OE|UE|PE|DE +CVTDQ2PS ; Vps,Wdq ; ; NP 0x0F 0x5B /r ; s:SSE2, t:CONVERT, w:W|R, e:2, x:PE +CVTPS2DQ ; Vdq,Wps ; ; 0x66 0x0F 0x5B /r ; s:SSE2, t:CONVERT, w:W|R, e:2, x:IE|PE +CVTTPS2DQ ; Vdq,Wps ; ; 0xF3 0x0F 0x5B /r ; s:SSE2, t:CONVERT, w:W|R, e:2, x:IE|PE +SUBPS ; Vps,Wps ; ; NP 0x0F 0x5C /r ; s:SSE, t:SSE, w:RW|R, e:2, x:IE|OE|UE|PE|DE +SUBPD ; Vpd,Wpd ; ; 0x66 0x0F 0x5C /r ; s:SSE2, t:SSE, w:RW|R, e:2, x:IE|OE|UE|PE|DE +SUBSS ; Vss,Wss ; ; 0xF3 0x0F 0x5C /r ; s:SSE, t:SSE, w:RW|R, e:3, x:IE|OE|UE|PE|DE +SUBSD ; Vsd,Wsd ; ; 0xF2 0x0F 0x5C /r ; s:SSE2, t:SSE, w:RW|R, e:3, x:IE|OE|UE|PE|DE +MINPS ; Vps,Wps ; ; NP 0x0F 0x5D /r ; s:SSE, t:SSE, w:RW|R, e:2, x:IE|DE +MINPD ; Vpd,Wpd ; ; 0x66 0x0F 0x5D /r ; s:SSE2, t:SSE, w:RW|R, e:2, x:IE|DE +MINSS ; Vss,Wss ; ; 0xF3 0x0F 0x5D /r ; s:SSE, t:SSE, w:RW|R, e:3, x:IE|DE +MINSD ; Vsd,Wsd ; ; 0xF2 0x0F 0x5D /r ; s:SSE2, t:SSE, w:RW|R, e:3, x:IE|DE +DIVPS ; Vps,Wps ; ; NP 0x0F 0x5E /r ; s:SSE, t:SSE, w:RW|R, e:2, x:IE|OE|UE|PE|DE|ZE +DIVPD ; Vpd,Wpd ; ; 0x66 0x0F 0x5E /r ; s:SSE2, t:SSE, w:RW|R, e:2, x:IE|OE|UE|PE|DE|ZE +DIVSS ; Vss,Wss ; ; 0xF3 0x0F 0x5E /r ; s:SSE, t:SSE, w:RW|R, e:3, x:IE|OE|UE|PE|DE|ZE +DIVSD ; Vsd,Wsd ; ; 0xF2 0x0F 0x5E /r ; s:SSE2, t:SSE, w:RW|R, e:3, x:IE|OE|UE|PE|DE|ZE +MAXPS ; Vps,Wps ; ; NP 0x0F 0x5F /r ; s:SSE, t:SSE, w:RW|R, e:2, x:IE|DE +MAXPD ; Vpd,Wpd ; ; 0x66 0x0F 0x5F /r ; s:SSE2, t:SSE, w:RW|R, e:2, x:IE|DE +MAXSS ; Vss,Wss ; ; 0xF3 0x0F 0x5F /r ; s:SSE, t:SSE, w:RW|R, e:3, x:IE|DE +MAXSD ; Vsd,Wsd ; ; 0xF2 0x0F 0x5F /r ; s:SSE2, t:SSE, w:RW|R, e:3, x:IE|DE # 0x60 - 0x6F PUNPCKLBW ; Pq,Qd ; ; NP 0x0F 0x60 /r ; s:MMX, t:MMX, w:RW|R @@ -435,10 +437,10 @@ EXTRQ ; Uq,Ib,Ib ; ; 0x66 0x0F 0x78 /0 i VMWRITE ; Gy,Ey ; Fv ; NP 0x0F 0x79 /r ; s:VTX, t:VTX, w:R|R|W, f:VMX, a:F64, m:VMXROOT EXTRQ ; Vdq,Uq ; ; 0x66 0x0F 0x79 /r:reg ; s:SSE4A, t:BITBYTE, w:W|R INSERTQ ; Vdq,Udq ; ; 0xF2 0x0F 0x79 /r:reg ; s:SSE4A, t:BITBYTE, w:W|R -HADDPD ; Vpd,Wpd ; ; 0x66 0x0F 0x7C /r ; s:SSE3, t:SSE, w:RW|R, e:2 -HADDPS ; Vps,Wps ; ; 0xF2 0x0F 0x7C /r ; s:SSE3, t:SSE, w:RW|R, e:2 -HSUBPD ; Vpd,Wpd ; ; 0x66 0x0F 0x7D /r ; s:SSE3, t:SSE, w:RW|R, e:2 -HSUBPS ; Vps,Wps ; ; 0xF2 0x0F 0x7D /r ; s:SSE3, t:SSE, w:RW|R, e:2 +HADDPD ; Vpd,Wpd ; ; 0x66 0x0F 0x7C /r ; s:SSE3, t:SSE, w:RW|R, e:2, x:IE|OE|UE|PE|DE +HADDPS ; Vps,Wps ; ; 0xF2 0x0F 0x7C /r ; s:SSE3, t:SSE, w:RW|R, e:2, x:IE|OE|UE|PE|DE +HSUBPD ; Vpd,Wpd ; ; 0x66 0x0F 0x7D /r ; s:SSE3, t:SSE, w:RW|R, e:2, x:IE|OE|UE|PE|DE +HSUBPS ; Vps,Wps ; ; 0xF2 0x0F 0x7D /r ; s:SSE3, t:SSE, w:RW|R, e:2, x:IE|OE|UE|PE|DE MOVD ; Ey,Pd ; ; NP 0x0F 0x7E /r ; s:MMX, t:DATAXFER, w:W|R MOVQ ; Ey,Pq ; ; rexw NP 0x0F 0x7E /r ; s:MMX, t:DATAXFER, w:W|R MOVD ; Ey,Vdq ; ; 0x66 0x0F 0x7E /r ; s:SSE2, t:DATAXFER, w:W|R, e:5 @@ -562,10 +564,10 @@ MOVSX ; Gv,Ew ; ; 0x0F 0xBF /r # 0xC0 - 0xCF XADD ; Eb,Gb ; Fv ; 0x0F 0xC0 /r ; s:I486REAL, t:SEMAPHORE, w:RW|RW|W, f:ARITH, p:LOCK|HLE XADD ; Ev,Gv ; Fv ; 0x0F 0xC1 /r ; s:I486REAL, t:SEMAPHORE, w:RW|RW|W, f:ARITH, p:LOCK|HLE -CMPPS ; Vps,Wps,Ib ; ; NP 0x0F 0xC2 /r ib ; s:SSE, t:SSE, w:RW|R|R, e:2 -CMPPD ; Vpd,Wpd,Ib ; ; 0x66 0x0F 0xC2 /r ib ; s:SSE2, t:SSE, w:RW|R|R, e:2 -CMPSS ; Vss,Wss,Ib ; ; 0xF3 0x0F 0xC2 /r ib ; s:SSE, t:SSE, w:RW|R|R, e:3 -CMPSD ; Vsd,Wsd,Ib ; ; 0xF2 0x0F 0xC2 /r ib ; s:SSE2, t:SSE, w:RW|R|R, e:3 +CMPPS ; Vps,Wps,Ib ; ; NP 0x0F 0xC2 /r ib ; s:SSE, t:SSE, w:RW|R|R, e:2, x:IE|DE +CMPPD ; Vpd,Wpd,Ib ; ; 0x66 0x0F 0xC2 /r ib ; s:SSE2, t:SSE, w:RW|R|R, e:2, x:IE|DE +CMPSS ; Vss,Wss,Ib ; ; 0xF3 0x0F 0xC2 /r ib ; s:SSE, t:SSE, w:RW|R|R, e:3, x:IE|DE +CMPSD ; Vsd,Wsd,Ib ; ; 0xF2 0x0F 0xC2 /r ib ; s:SSE2, t:SSE, w:RW|R|R, e:3, x:IE|DE MOVNTI ; My,Gy ; ; NP 0x0F 0xC3 /r:mem ; s:SSE2, t:DATAXFER, w:W|R PINSRW ; Pq,Rd,Ib ; ; NP 0x0F 0xC4 /r:reg ib ; s:MMX, t:MMX, w:RW|R|R PINSRW ; Pq,Mw,Ib ; ; NP 0x0F 0xC4 /r:mem ib ; s:MMX, t:MMX, w:RW|R|R @@ -604,8 +606,8 @@ BSWAP ; Zv ; ; 0x0F 0xCE BSWAP ; Zv ; ; 0x0F 0xCF ; s:I486REAL, t:DATAXFER, w:RW # 0xD0 - 0xDF -ADDSUBPD ; Vpd,Wpd ; ; 0x66 0x0F 0xD0 /r ; s:SSE3, t:SSE, w:RW|R, e:2 -ADDSUBPS ; Vps,Wps ; ; 0xF2 0x0F 0xD0 /r ; s:SSE3, t:SSE, w:RW|R, e:2 +ADDSUBPD ; Vpd,Wpd ; ; 0x66 0x0F 0xD0 /r ; s:SSE3, t:SSE, w:RW|R, e:2, x:IE|OE|UE|PE|DE +ADDSUBPS ; Vps,Wps ; ; 0xF2 0x0F 0xD0 /r ; s:SSE3, t:SSE, w:RW|R, e:2, x:IE|OE|UE|PE|DE PSRLW ; Pq,Qq ; ; NP 0x0F 0xD1 /r ; s:MMX, t:MMX, w:RW|R PSRLW ; Vx,Wx ; ; 0x66 0x0F 0xD1 /r ; s:SSE2, t:SSE, w:RW|R, e:4 PSRLD ; Pq,Qq ; ; NP 0x0F 0xD2 /r ; s:MMX, t:MMX, w:RW|R @@ -651,9 +653,9 @@ PMULHUW ; Pq,Qq ; ; NP 0x0F 0xE4 /r PMULHUW ; Vx,Wx ; ; 0x66 0x0F 0xE4 /r ; s:SSE2, t:SSE, w:RW|R, e:4 PMULHW ; Pq,Qq ; ; NP 0x0F 0xE5 /r ; s:MMX, t:MMX, w:RW|R PMULHW ; Vx,Wx ; ; 0x66 0x0F 0xE5 /r ; s:SSE2, t:SSE, w:RW|R, e:4 -CVTTPD2DQ ; Vx,Wpd ; ; 0x66 0x0F 0xE6 /r ; s:SSE2, t:CONVERT, w:W|R, e:2 +CVTTPD2DQ ; Vx,Wpd ; ; 0x66 0x0F 0xE6 /r ; s:SSE2, t:CONVERT, w:W|R, e:2, x:IE|PE CVTDQ2PD ; Vx,Wq ; ; 0xF3 0x0F 0xE6 /r ; s:SSE2, t:CONVERT, w:W|R, e:5 -CVTPD2DQ ; Vx,Wpd ; ; 0xF2 0x0F 0xE6 /r ; s:SSE2, t:CONVERT, w:W|R, e:2 +CVTPD2DQ ; Vx,Wpd ; ; 0xF2 0x0F 0xE6 /r ; s:SSE2, t:CONVERT, w:W|R, e:2, x:IE|PE MOVNTQ ; Mq,Pq ; ; NP 0x0F 0xE7 /r:mem ; s:MMX, t:DATAXFER, w:W|R MOVNTDQ ; Mx,Vx ; ; 0x66 0x0F 0xE7 /r:mem ; s:SSE2, t:DATAXFER, w:W|R, e:1 PSUBSB ; Pq,Qq ; ; NP 0x0F 0xE8 /r ; s:MMX, t:MMX, w:RW|R diff --git a/isagenerator/instructions/table_legacy_2.dat b/isagenerator/instructions/table_legacy_2.dat index a34033f..40b4f79 100644 --- a/isagenerator/instructions/table_legacy_2.dat +++ b/isagenerator/instructions/table_legacy_2.dat @@ -86,6 +86,9 @@ INVEPT ; Gy,Mdq ; Fv ; 0x66 0x0F 0x INVVPID ; Gy,Mdq ; Fv ; 0x66 0x0F 0x38 0x81 /r:mem ; s:VTX, t:VTX, w:R|R|W, f:VMX, a:F64|SERIAL|NOREX2, m:VMXROOT INVPCID ; Gy,Mdq ; ; 0x66 0x0F 0x38 0x82 /r:mem ; s:INVPCID, t:MISC, w:R|R, a:F64|NOREX2, m:KERNEL|NOV86 +MOVRS ; Gb,Mb ; ; 0x0F 0x38 0x8A /r:mem ; s:MOVRS, t:DATAXFER, w:W|R, a:NOREP, m:O64 +MOVRS ; Gv,Mv ; ; 0x0F 0x38 0x8B /r:mem ; s:MOVRS, t:DATAXFER, w:W|R, a:NOREP, m:O64 + # 0x90 - 0x9F # 0xA0 - 0xAF diff --git a/isagenerator/instructions/table_legacy_3.dat b/isagenerator/instructions/table_legacy_3.dat index bfe97ca..46f2419 100644 --- a/isagenerator/instructions/table_legacy_3.dat +++ b/isagenerator/instructions/table_legacy_3.dat @@ -4,10 +4,10 @@ # # 0x00 - 0x0F -ROUNDPS ; Vx,Wx,Ib ; ; 0x66 0x0F 0x3A 0x08 /r ib ; s:SSE4, t:SSE, w:W|R|R, e:2, a:NOREX2 -ROUNDPD ; Vx,Wx,Ib ; ; 0x66 0x0F 0x3A 0x09 /r ib ; s:SSE4, t:SSE, w:W|R|R, e:2, a:NOREX2 -ROUNDSS ; Vss,Wss,Ib ; ; 0x66 0x0F 0x3A 0x0A /r ib ; s:SSE4, t:SSE, w:W|R|R, e:3, a:NOREX2 -ROUNDSD ; Vsd,Wsd,Ib ; ; 0x66 0x0F 0x3A 0x0B /r ib ; s:SSE4, t:SSE, w:W|R|R, e:3, a:NOREX2 +ROUNDPS ; Vx,Wx,Ib ; ; 0x66 0x0F 0x3A 0x08 /r ib ; s:SSE4, t:SSE, w:W|R|R, e:2, a:NOREX2, x:IE|PE +ROUNDPD ; Vx,Wx,Ib ; ; 0x66 0x0F 0x3A 0x09 /r ib ; s:SSE4, t:SSE, w:W|R|R, e:2, a:NOREX2, x:IE|PE +ROUNDSS ; Vss,Wss,Ib ; ; 0x66 0x0F 0x3A 0x0A /r ib ; s:SSE4, t:SSE, w:W|R|R, e:3, a:NOREX2, x:IE|PE +ROUNDSD ; Vsd,Wsd,Ib ; ; 0x66 0x0F 0x3A 0x0B /r ib ; s:SSE4, t:SSE, w:W|R|R, e:3, a:NOREX2, x:IE|PE BLENDPS ; Vx,Wx,Ib ; ; 0x66 0x0F 0x3A 0x0C /r ib ; s:SSE4, t:SSE, w:RW|R|R, e:4, a:NOREX2 BLENDPD ; Vx,Wx,Ib ; ; 0x66 0x0F 0x3A 0x0D /r ib ; s:SSE4, t:SSE, w:RW|R|R, e:4, a:NOREX2 PBLENDW ; Vx,Wx,Ib ; ; 0x66 0x0F 0x3A 0x0E /r ib ; s:SSE4, t:SSE, w:RW|R|R, e:4, a:NOREX2 @@ -37,8 +37,8 @@ PINSRQ ; Vdq,Eq,Ib ; ; rexw 0x66 0x0F 0x # 0x30 - 0x3F # 0x40 - 0x4F -DPPS ; Vx,Wx,Ib ; ; 0x66 0x0F 0x3A 0x40 /r ib ; s:SSE4, t:SSE, w:RW|R|R, e:2, a:NOREX2 -DPPD ; Vdq,Wdq,Ib ; ; 0x66 0x0F 0x3A 0x41 /r ib ; s:SSE4, t:SSE, w:RW|R|R, e:2, a:NOREX2 +DPPS ; Vx,Wx,Ib ; ; 0x66 0x0F 0x3A 0x40 /r ib ; s:SSE4, t:SSE, w:RW|R|R, e:2, a:NOREX2, x:IE|OE|UE|PE|DE +DPPD ; Vdq,Wdq,Ib ; ; 0x66 0x0F 0x3A 0x41 /r ib ; s:SSE4, t:SSE, w:RW|R|R, e:2, a:NOREX2, x:IE|OE|UE|PE|DE MPSADBW ; Vdq,Wdq,Ib ; ; 0x66 0x0F 0x3A 0x42 /r ib ; s:SSE4, t:SSE, w:RW|R|R, e:4, a:NOREX2 PCLMULQDQ ; Vdq,Wdq,Ib ; ; 0x66 0x0F 0x3A 0x44 /r ib ; s:PCLMULQDQ, t:PCLMULQDQ, w:RW|R|R, e:4, a:NOREX2 diff --git a/isagenerator/instructions/table_vex_1.dat b/isagenerator/instructions/table_vex_1.dat index 0e2f144..03fd6e5 100644 --- a/isagenerator/instructions/table_vex_1.dat +++ b/isagenerator/instructions/table_vex_1.dat @@ -42,18 +42,18 @@ VMOVAPS ; Vx,Wx ; ; vex m:1 p:0 l:x w:i VMOVAPD ; Vx,Wx ; ; vex m:1 p:1 l:x w:i 0x28 /r ; s:AVX, t:DATAXFER, w:W|R, e:1 VMOVAPS ; Wx,Vx ; ; vex m:1 p:0 l:x w:i 0x29 /r ; s:AVX, t:DATAXFER, w:W|R, e:1 VMOVAPD ; Wx,Vx ; ; vex m:1 p:1 l:x w:i 0x29 /r ; s:AVX, t:DATAXFER, w:W|R, e:1 -VCVTSI2SS ; Vss,Hss,Ey ; ; vex m:1 p:2 l:i w:x 0x2A /r ; s:AVX, t:CONVERT, w:W|R|R, e:3, a:IWO64 -VCVTSI2SD ; Vsd,Hsd,Ey ; ; vex m:1 p:3 l:i w:x 0x2A /r ; s:AVX, t:CONVERT, w:W|R|R, e:3, a:IWO64 +VCVTSI2SS ; Vss,Hss,Ey ; ; vex m:1 p:2 l:i w:x 0x2A /r ; s:AVX, t:CONVERT, w:W|R|R, e:3, a:IWO64, x:PE +VCVTSI2SD ; Vsd,Hsd,Ey ; ; vex m:1 p:3 l:i w:x 0x2A /r ; s:AVX, t:CONVERT, w:W|R|R, e:3, a:IWO64, x:PE VMOVNTPS ; Mx,Vx ; ; vex m:1 p:0 l:x w:i 0x2B /r:mem ; s:AVX, t:AVX, w:W|R, e:1 VMOVNTPD ; Mx,Vx ; ; vex m:1 p:1 l:x w:i 0x2B /r:mem ; s:AVX, t:AVX, w:W|R, e:1 -VCVTTSS2SI ; Gy,Wss ; ; vex m:1 p:2 l:i w:x 0x2C /r ; s:AVX, t:CONVERT, w:W|R, e:3, a:IWO64 -VCVTTSD2SI ; Gy,Wsd ; ; vex m:1 p:3 l:i w:x 0x2C /r ; s:AVX, t:CONVERT, w:W|R, e:3, a:IWO64 -VCVTSS2SI ; Gy,Wss ; ; vex m:1 p:2 l:i w:x 0x2D /r ; s:AVX, t:CONVERT, w:W|R, e:3, a:IWO64 -VCVTSD2SI ; Gy,Wsd ; ; vex m:1 p:3 l:i w:x 0x2D /r ; s:AVX, t:CONVERT, w:W|R, e:3, a:IWO64 -VUCOMISS ; Vss,Wss ; Fv ; vex m:1 p:0 l:i w:i 0x2E /r ; s:AVX, t:AVX, w:R|R|W, f:COMIS, e:3 -VUCOMISD ; Vsd,Wsd ; Fv ; vex m:1 p:1 l:i w:i 0x2E /r ; s:AVX, t:AVX, w:R|R|W, f:COMIS, e:3 -VCOMISS ; Vss,Wss ; Fv ; vex m:1 p:0 l:i w:i 0x2F /r ; s:AVX, t:AVX, w:R|R|W, f:COMIS, e:3 -VCOMISD ; Vsd,Wsd ; Fv ; vex m:1 p:1 l:i w:i 0x2F /r ; s:AVX, t:AVX, w:R|R|W, f:COMIS, e:3 +VCVTTSS2SI ; Gy,Wss ; ; vex m:1 p:2 l:i w:x 0x2C /r ; s:AVX, t:CONVERT, w:W|R, e:3, a:IWO64, x:IE|PE +VCVTTSD2SI ; Gy,Wsd ; ; vex m:1 p:3 l:i w:x 0x2C /r ; s:AVX, t:CONVERT, w:W|R, e:3, a:IWO64, x:IE|PE +VCVTSS2SI ; Gy,Wss ; ; vex m:1 p:2 l:i w:x 0x2D /r ; s:AVX, t:CONVERT, w:W|R, e:3, a:IWO64, x:IE|PE +VCVTSD2SI ; Gy,Wsd ; ; vex m:1 p:3 l:i w:x 0x2D /r ; s:AVX, t:CONVERT, w:W|R, e:3, a:IWO64, x:IE|PE +VUCOMISS ; Vss,Wss ; Fv ; vex m:1 p:0 l:i w:i 0x2E /r ; s:AVX, t:AVX, w:R|R|W, f:COMIS, e:3, x:IE|DE +VUCOMISD ; Vsd,Wsd ; Fv ; vex m:1 p:1 l:i w:i 0x2E /r ; s:AVX, t:AVX, w:R|R|W, f:COMIS, e:3, x:IE|DE +VCOMISS ; Vss,Wss ; Fv ; vex m:1 p:0 l:i w:i 0x2F /r ; s:AVX, t:AVX, w:R|R|W, f:COMIS, e:3, x:IE|DE +VCOMISD ; Vsd,Wsd ; Fv ; vex m:1 p:1 l:i w:i 0x2F /r ; s:AVX, t:AVX, w:R|R|W, f:COMIS, e:3, x:IE|DE # 0x30 - 0x3F @@ -124,10 +124,10 @@ KTESTD ; rKd,mKd ; ; vex m:1 p:1 l:0 w:1 # 0x50 - 0x5F VMOVMSKPS ; Gy,Ux ; ; vex m:1 p:0 l:x w:i 0x50 /r:reg ; s:AVX, t:DATAXFER, w:W|R, e:7, a:D64 VMOVMSKPD ; Gy,Ux ; ; vex m:1 p:1 l:x w:i 0x50 /r:reg ; s:AVX, t:DATAXFER, w:W|R, e:7, a:D64 -VSQRTPS ; Vx,Wx ; ; vex m:1 p:0 l:x w:i 0x51 /r ; s:AVX, t:AVX, w:W|R, e:2 -VSQRTPD ; Vx,Wx ; ; vex m:1 p:1 l:x w:i 0x51 /r ; s:AVX, t:AVX, w:W|R, e:2 -VSQRTSS ; Vss,Hss,Wss ; ; vex m:1 p:2 l:i w:i 0x51 /r ; s:AVX, t:AVX, w:W|R|R, e:3 -VSQRTSD ; Vsd,Hsd,Wsd ; ; vex m:1 p:3 l:i w:i 0x51 /r ; s:AVX, t:AVX, w:W|R|R, e:3 +VSQRTPS ; Vx,Wx ; ; vex m:1 p:0 l:x w:i 0x51 /r ; s:AVX, t:AVX, w:W|R, e:2, x:IE|PE|DE +VSQRTPD ; Vx,Wx ; ; vex m:1 p:1 l:x w:i 0x51 /r ; s:AVX, t:AVX, w:W|R, e:2, x:IE|PE|DE +VSQRTSS ; Vss,Hss,Wss ; ; vex m:1 p:2 l:i w:i 0x51 /r ; s:AVX, t:AVX, w:W|R|R, e:3, x:IE|PE|DE +VSQRTSD ; Vsd,Hsd,Wsd ; ; vex m:1 p:3 l:i w:i 0x51 /r ; s:AVX, t:AVX, w:W|R|R, e:3, x:IE|PE|DE VRSQRTPS ; Vx,Wx ; ; vex m:1 p:0 l:x w:i 0x52 /r ; s:AVX, t:AVX, w:W|R, e:4 VRSQRTSS ; Vss,Hss,Wss ; ; vex m:1 p:2 l:i w:i 0x52 /r ; s:AVX, t:AVX, w:W|R|R, e:5 VRCPPS ; Vps,Wps ; ; vex m:1 p:0 l:x w:i 0x53 /r ; s:AVX, t:AVX, w:W|R, e:4 @@ -140,39 +140,39 @@ VORPS ; Vps,Hps,Wps ; ; vex m:1 p:0 l:x w:i VORPD ; Vpd,Hpd,Wpd ; ; vex m:1 p:1 l:x w:i 0x56 /r ; s:AVX, t:LOGICAL_FP, w:W|R|R, e:4 VXORPS ; Vps,Hps,Wps ; ; vex m:1 p:0 l:x w:i 0x57 /r ; s:AVX, t:LOGICAL_FP, w:W|R|R, e:4 VXORPD ; Vpd,Hpd,Wpd ; ; vex m:1 p:1 l:x w:i 0x57 /r ; s:AVX, t:LOGICAL_FP, w:W|R|R, e:4 -VADDPS ; Vps,Hps,Wps ; ; vex m:1 p:0 l:x w:i 0x58 /r ; s:AVX, t:AVX, w:W|R|R, e:2 -VADDPD ; Vpd,Hpd,Wpd ; ; vex m:1 p:1 l:x w:i 0x58 /r ; s:AVX, t:AVX, w:W|R|R, e:2 -VADDSS ; Vss,Hss,Wss ; ; vex m:1 p:2 l:i w:i 0x58 /r ; s:AVX, t:AVX, w:W|R|R, e:2 -VADDSD ; Vsd,Hsd,Wsd ; ; vex m:1 p:3 l:i w:i 0x58 /r ; s:AVX, t:AVX, w:W|R|R, e:2 -VMULPS ; Vps,Hps,Wps ; ; vex m:1 p:0 l:x w:i 0x59 /r ; s:AVX, t:AVX, w:W|R|R, e:2 -VMULPD ; Vpd,Hpd,Wpd ; ; vex m:1 p:1 l:x w:i 0x59 /r ; s:AVX, t:AVX, w:W|R|R, e:2 -VMULSS ; Vss,Hss,Wss ; ; vex m:1 p:2 l:i w:i 0x59 /r ; s:AVX, t:AVX, w:W|R|R, e:2 -VMULSD ; Vsd,Hsd,Wsd ; ; vex m:1 p:3 l:i w:i 0x59 /r ; s:AVX, t:AVX, w:W|R|R, e:2 -VCVTPS2PD ; Vpd,Wq ; ; vex m:1 p:0 l:0 w:i 0x5A /r ; s:AVX, t:CONVERT, w:W|R, e:2 -VCVTPS2PD ; Vqq,Wdq ; ; vex m:1 p:0 l:1 w:i 0x5A /r ; s:AVX, t:CONVERT, w:W|R, e:2 -VCVTPD2PS ; Vdq,Wdq ; ; vex m:1 p:1 l:0 w:i 0x5A /r ; s:AVX, t:CONVERT, w:W|R, e:2 -VCVTPD2PS ; Vdq,Wqq ; ; vex m:1 p:1 l:1 w:i 0x5A /r ; s:AVX, t:CONVERT, w:W|R, e:2 -VCVTSS2SD ; Vsd,Hx,Wss ; ; vex m:1 p:2 l:i w:i 0x5A /r ; s:AVX, t:CONVERT, w:W|R|R, e:3 -VCVTSD2SS ; Vss,Hx,Wsd ; ; vex m:1 p:3 l:i w:i 0x5A /r ; s:AVX, t:CONVERT, w:W|R|R, e:3 -VCVTDQ2PS ; Vps,Wps ; ; vex m:1 p:0 l:x w:i 0x5B /r ; s:AVX, t:CONVERT, w:W|R, e:2 -VCVTPS2DQ ; Vps,Wps ; ; vex m:1 p:1 l:x w:i 0x5B /r ; s:AVX, t:CONVERT, w:W|R, e:2 -VCVTTPS2DQ ; Vps,Wps ; ; vex m:1 p:2 l:x w:i 0x5B /r ; s:AVX, t:CONVERT, w:W|R, e:2 -VSUBPS ; Vps,Hps,Wps ; ; vex m:1 p:0 l:x w:i 0x5C /r ; s:AVX, t:AVX, w:W|R|R, e:2 -VSUBPD ; Vpd,Hpd,Wpd ; ; vex m:1 p:1 l:x w:i 0x5C /r ; s:AVX, t:AVX, w:W|R|R, e:2 -VSUBSS ; Vss,Hss,Wss ; ; vex m:1 p:2 l:i w:i 0x5C /r ; s:AVX, t:AVX, w:W|R|R, e:2 -VSUBSD ; Vsd,Hsd,Wsd ; ; vex m:1 p:3 l:i w:i 0x5C /r ; s:AVX, t:AVX, w:W|R|R, e:2 -VMINPS ; Vps,Hps,Wps ; ; vex m:1 p:0 l:x w:i 0x5D /r ; s:AVX, t:AVX, w:W|R|R, e:2 -VMINPD ; Vpd,Hpd,Wpd ; ; vex m:1 p:1 l:x w:i 0x5D /r ; s:AVX, t:AVX, w:W|R|R, e:2 -VMINSS ; Vss,Hss,Wss ; ; vex m:1 p:2 l:i w:i 0x5D /r ; s:AVX, t:AVX, w:W|R|R, e:2 -VMINSD ; Vsd,Hsd,Wsd ; ; vex m:1 p:3 l:i w:i 0x5D /r ; s:AVX, t:AVX, w:W|R|R, e:2 -VDIVPS ; Vps,Hps,Wps ; ; vex m:1 p:0 l:x w:i 0x5E /r ; s:AVX, t:AVX, w:W|R|R, e:2 -VDIVPD ; Vpd,Hpd,Wpd ; ; vex m:1 p:1 l:x w:i 0x5E /r ; s:AVX, t:AVX, w:W|R|R, e:2 -VDIVSS ; Vss,Hss,Wss ; ; vex m:1 p:2 l:i w:i 0x5E /r ; s:AVX, t:AVX, w:W|R|R, e:2 -VDIVSD ; Vsd,Hsd,Wsd ; ; vex m:1 p:3 l:i w:i 0x5E /r ; s:AVX, t:AVX, w:W|R|R, e:2 -VMAXPS ; Vps,Hps,Wps ; ; vex m:1 p:0 l:x w:i 0x5F /r ; s:AVX, t:AVX, w:W|R|R, e:2 -VMAXPD ; Vpd,Hpd,Wpd ; ; vex m:1 p:1 l:x w:i 0x5F /r ; s:AVX, t:AVX, w:W|R|R, e:2 -VMAXSS ; Vss,Hss,Wss ; ; vex m:1 p:2 l:i w:i 0x5F /r ; s:AVX, t:AVX, w:W|R|R, e:2 -VMAXSD ; Vsd,Hsd,Wsd ; ; vex m:1 p:3 l:i w:i 0x5F /r ; s:AVX, t:AVX, w:W|R|R, e:2 +VADDPS ; Vps,Hps,Wps ; ; vex m:1 p:0 l:x w:i 0x58 /r ; s:AVX, t:AVX, w:W|R|R, e:2, x:IE|OE|UE|PE|DE +VADDPD ; Vpd,Hpd,Wpd ; ; vex m:1 p:1 l:x w:i 0x58 /r ; s:AVX, t:AVX, w:W|R|R, e:2, x:IE|OE|UE|PE|DE +VADDSS ; Vss,Hss,Wss ; ; vex m:1 p:2 l:i w:i 0x58 /r ; s:AVX, t:AVX, w:W|R|R, e:2, x:IE|OE|UE|PE|DE +VADDSD ; Vsd,Hsd,Wsd ; ; vex m:1 p:3 l:i w:i 0x58 /r ; s:AVX, t:AVX, w:W|R|R, e:2, x:IE|OE|UE|PE|DE +VMULPS ; Vps,Hps,Wps ; ; vex m:1 p:0 l:x w:i 0x59 /r ; s:AVX, t:AVX, w:W|R|R, e:2, x:IE|OE|UE|PE|DE +VMULPD ; Vpd,Hpd,Wpd ; ; vex m:1 p:1 l:x w:i 0x59 /r ; s:AVX, t:AVX, w:W|R|R, e:2, x:IE|OE|UE|PE|DE +VMULSS ; Vss,Hss,Wss ; ; vex m:1 p:2 l:i w:i 0x59 /r ; s:AVX, t:AVX, w:W|R|R, e:2, x:IE|OE|UE|PE|DE +VMULSD ; Vsd,Hsd,Wsd ; ; vex m:1 p:3 l:i w:i 0x59 /r ; s:AVX, t:AVX, w:W|R|R, e:2, x:IE|OE|UE|PE|DE +VCVTPS2PD ; Vpd,Wq ; ; vex m:1 p:0 l:0 w:i 0x5A /r ; s:AVX, t:CONVERT, w:W|R, e:2, x:IE|DE +VCVTPS2PD ; Vqq,Wdq ; ; vex m:1 p:0 l:1 w:i 0x5A /r ; s:AVX, t:CONVERT, w:W|R, e:2, x:IE|DE +VCVTPD2PS ; Vdq,Wdq ; ; vex m:1 p:1 l:0 w:i 0x5A /r ; s:AVX, t:CONVERT, w:W|R, e:2, x:IE|OE|UE|PE|DE +VCVTPD2PS ; Vdq,Wqq ; ; vex m:1 p:1 l:1 w:i 0x5A /r ; s:AVX, t:CONVERT, w:W|R, e:2, x:IE|OE|UE|PE|DE +VCVTSS2SD ; Vsd,Hx,Wss ; ; vex m:1 p:2 l:i w:i 0x5A /r ; s:AVX, t:CONVERT, w:W|R|R, e:3, x:IE|DE +VCVTSD2SS ; Vss,Hx,Wsd ; ; vex m:1 p:3 l:i w:i 0x5A /r ; s:AVX, t:CONVERT, w:W|R|R, e:3, x:IE|OE|UE|PE|DE +VCVTDQ2PS ; Vps,Wps ; ; vex m:1 p:0 l:x w:i 0x5B /r ; s:AVX, t:CONVERT, w:W|R, e:2, x:PE +VCVTPS2DQ ; Vps,Wps ; ; vex m:1 p:1 l:x w:i 0x5B /r ; s:AVX, t:CONVERT, w:W|R, e:2, x:IE|PE +VCVTTPS2DQ ; Vps,Wps ; ; vex m:1 p:2 l:x w:i 0x5B /r ; s:AVX, t:CONVERT, w:W|R, e:2, x:IE|PE +VSUBPS ; Vps,Hps,Wps ; ; vex m:1 p:0 l:x w:i 0x5C /r ; s:AVX, t:AVX, w:W|R|R, e:2, x:IE|OE|UE|PE|DE +VSUBPD ; Vpd,Hpd,Wpd ; ; vex m:1 p:1 l:x w:i 0x5C /r ; s:AVX, t:AVX, w:W|R|R, e:2, x:IE|OE|UE|PE|DE +VSUBSS ; Vss,Hss,Wss ; ; vex m:1 p:2 l:i w:i 0x5C /r ; s:AVX, t:AVX, w:W|R|R, e:2, x:IE|OE|UE|PE|DE +VSUBSD ; Vsd,Hsd,Wsd ; ; vex m:1 p:3 l:i w:i 0x5C /r ; s:AVX, t:AVX, w:W|R|R, e:2, x:IE|OE|UE|PE|DE +VMINPS ; Vps,Hps,Wps ; ; vex m:1 p:0 l:x w:i 0x5D /r ; s:AVX, t:AVX, w:W|R|R, e:2, x:IE|DE +VMINPD ; Vpd,Hpd,Wpd ; ; vex m:1 p:1 l:x w:i 0x5D /r ; s:AVX, t:AVX, w:W|R|R, e:2, x:IE|DE +VMINSS ; Vss,Hss,Wss ; ; vex m:1 p:2 l:i w:i 0x5D /r ; s:AVX, t:AVX, w:W|R|R, e:2, x:IE|DE +VMINSD ; Vsd,Hsd,Wsd ; ; vex m:1 p:3 l:i w:i 0x5D /r ; s:AVX, t:AVX, w:W|R|R, e:2, x:IE|DE +VDIVPS ; Vps,Hps,Wps ; ; vex m:1 p:0 l:x w:i 0x5E /r ; s:AVX, t:AVX, w:W|R|R, e:2, x:IE|OE|UE|PE|DE|ZE +VDIVPD ; Vpd,Hpd,Wpd ; ; vex m:1 p:1 l:x w:i 0x5E /r ; s:AVX, t:AVX, w:W|R|R, e:2, x:IE|OE|UE|PE|DE|ZE +VDIVSS ; Vss,Hss,Wss ; ; vex m:1 p:2 l:i w:i 0x5E /r ; s:AVX, t:AVX, w:W|R|R, e:2, x:IE|OE|UE|PE|DE|ZE +VDIVSD ; Vsd,Hsd,Wsd ; ; vex m:1 p:3 l:i w:i 0x5E /r ; s:AVX, t:AVX, w:W|R|R, e:2, x:IE|OE|UE|PE|DE|ZE +VMAXPS ; Vps,Hps,Wps ; ; vex m:1 p:0 l:x w:i 0x5F /r ; s:AVX, t:AVX, w:W|R|R, e:2, x:IE|DE +VMAXPD ; Vpd,Hpd,Wpd ; ; vex m:1 p:1 l:x w:i 0x5F /r ; s:AVX, t:AVX, w:W|R|R, e:2, x:IE|DE +VMAXSS ; Vss,Hss,Wss ; ; vex m:1 p:2 l:i w:i 0x5F /r ; s:AVX, t:AVX, w:W|R|R, e:2, x:IE|DE +VMAXSD ; Vsd,Hsd,Wsd ; ; vex m:1 p:3 l:i w:i 0x5F /r ; s:AVX, t:AVX, w:W|R|R, e:2, x:IE|DE # 0x60 - 0x6F @@ -206,10 +206,10 @@ VPCMPEQW ; Vx,Hx,Wx ; ; vex m:1 p:1 l:x w:i VPCMPEQD ; Vx,Hx,Wx ; ; vex m:1 p:1 l:x w:i 0x76 /r ; s:AVX, t:AVX, w:W|R|R, e:4 VZEROUPPER ; ; BANK ; vex m:1 p:0 l:0 0x77 ; s:AVX, t:AVX, w:W, e:8 VZEROALL ; ; BANK ; vex m:1 p:0 l:1 0x77 ; s:AVX, t:AVX, w:W, e:8 -VHADDPD ; Vpd,Hpd,Wpd ; ; vex m:1 p:1 l:x w:i 0x7C /r ; s:AVX, t:AVX, w:W|R|R, e:2 -VHADDPS ; Vps,Hps,Wps ; ; vex m:1 p:3 l:x w:i 0x7C /r ; s:AVX, t:AVX, w:W|R|R, e:2 -VHSUBPD ; Vpd,Hpd,Wpd ; ; vex m:1 p:1 l:x w:i 0x7D /r ; s:AVX, t:AVX, w:W|R|R, e:2 -VHSUBPS ; Vps,Hps,Wps ; ; vex m:1 p:3 l:x w:i 0x7D /r ; s:AVX, t:AVX, w:W|R|R, e:2 +VHADDPD ; Vpd,Hpd,Wpd ; ; vex m:1 p:1 l:x w:i 0x7C /r ; s:AVX, t:AVX, w:W|R|R, e:2, x:IE|OE|UE|PE|DE +VHADDPS ; Vps,Hps,Wps ; ; vex m:1 p:3 l:x w:i 0x7C /r ; s:AVX, t:AVX, w:W|R|R, e:2, x:IE|OE|UE|PE|DE +VHSUBPD ; Vpd,Hpd,Wpd ; ; vex m:1 p:1 l:x w:i 0x7D /r ; s:AVX, t:AVX, w:W|R|R, e:2, x:IE|OE|UE|PE|DE +VHSUBPS ; Vps,Hps,Wps ; ; vex m:1 p:3 l:x w:i 0x7D /r ; s:AVX, t:AVX, w:W|R|R, e:2, x:IE|OE|UE|PE|DE VMOVD ; Ey,Vd ; ; vex m:1 p:1 l:0 w:0 0x7E /r ; s:AVX, t:DATAXFER, w:W|R, e:5, a:IWO64 VMOVQ ; Ey,Vq ; ; vex m:1 p:1 l:0 w:1 0x7E /r ; s:AVX, t:DATAXFER, w:W|R, e:5, a:IWO64 VMOVQ ; Vdq,Wq ; ; vex m:1 p:2 l:0 w:i 0x7E /r ; s:AVX, t:DATAXFER, w:W|R, e:5 @@ -241,10 +241,10 @@ CLEVICT1 ; M? ; ; vex m:1 p:2 0xAE /7 # 0xB0 - 0xBF # 0xC0 - 0xCF -VCMPPS ; Vss,Hss,Wss,Ib ; ; vex m:1 p:0 l:i w:i 0xC2 /r ib ; s:AVX, t:AVX, w:W|R|R|R, e:3 -VCMPPD ; Vpd,Hpd,Wpd,Ib ; ; vex m:1 p:1 l:x w:i 0xC2 /r ib ; s:AVX, t:AVX, w:W|R|R|R, e:3 -VCMPSS ; Vss,Hss,Wss,Ib ; ; vex m:1 p:2 l:i w:i 0xC2 /r ib ; s:AVX, t:AVX, w:W|R|R|R, e:3 -VCMPSD ; Vsd,Hsd,Wsd,Ib ; ; vex m:1 p:3 l:i w:i 0xC2 /r ib ; s:AVX, t:AVX, w:W|R|R|R, e:3 +VCMPPS ; Vss,Hss,Wss,Ib ; ; vex m:1 p:0 l:i w:i 0xC2 /r ib ; s:AVX, t:AVX, w:W|R|R|R, e:3, x:IE|DE +VCMPPD ; Vpd,Hpd,Wpd,Ib ; ; vex m:1 p:1 l:x w:i 0xC2 /r ib ; s:AVX, t:AVX, w:W|R|R|R, e:3, x:IE|DE +VCMPSS ; Vss,Hss,Wss,Ib ; ; vex m:1 p:2 l:i w:i 0xC2 /r ib ; s:AVX, t:AVX, w:W|R|R|R, e:3, x:IE|DE +VCMPSD ; Vsd,Hsd,Wsd,Ib ; ; vex m:1 p:3 l:i w:i 0xC2 /r ib ; s:AVX, t:AVX, w:W|R|R|R, e:3, x:IE|DE VPINSRW ; Vdq,Hdq,Mw,Ib ; ; vex m:1 p:1 l:0 w:i 0xC4 /r:mem ib ; s:AVX, t:AVX, w:W|R|R|R, e:5 VPINSRW ; Vdq,Hdq,Rd,Ib ; ; vex m:1 p:1 l:0 w:i 0xC4 /r:reg ib ; s:AVX, t:AVX, w:W|R|R|R, e:5 VPEXTRW ; Gy,Udq,Ib ; ; vex m:1 p:1 l:0 w:i 0xC5 /r:reg ib ; s:AVX, t:AVX, w:W|R|R, e:5, a:D64 @@ -252,8 +252,8 @@ VSHUFPS ; Vps,Hps,Wps,Ib ; ; vex m:1 p:0 l:x w:i VSHUFPD ; Vpd,Hpd,Wpd,Ib ; ; vex m:1 p:1 l:x w:i 0xC6 /r ib ; s:AVX, t:AVX, w:W|R|R|R, e:4 # 0xD0 - 0xDF -VADDSUBPD ; Vpd,Hpd,Wpd ; ; vex m:1 p:1 l:x w:i 0xD0 /r ; s:AVX, t:AVX, w:W|R|R, e:2 -VADDSUBPS ; Vps,Hps,Wps ; ; vex m:1 p:3 l:x w:i 0xD0 /r ; s:AVX, t:AVX, w:W|R|R, e:2 +VADDSUBPD ; Vpd,Hpd,Wpd ; ; vex m:1 p:1 l:x w:i 0xD0 /r ; s:AVX, t:AVX, w:W|R|R, e:2, x:IE|OE|UE|PE|DE +VADDSUBPS ; Vps,Hps,Wps ; ; vex m:1 p:3 l:x w:i 0xD0 /r ; s:AVX, t:AVX, w:W|R|R, e:2, x:IE|OE|UE|PE|DE VPSRLW ; Vx,Hx,Wdq ; ; vex m:1 p:1 l:x w:i 0xD1 /r ; s:AVX, t:AVX, w:W|R|R, e:4 VPSRLD ; Vx,Hx,Wdq ; ; vex m:1 p:1 l:x w:i 0xD2 /r ; s:AVX, t:AVX, w:W|R|R, e:4 VPSRLQ ; Vx,Hx,Wdq ; ; vex m:1 p:1 l:x w:i 0xD3 /r ; s:AVX, t:AVX, w:W|R|R, e:4 @@ -277,10 +277,10 @@ VPSRAD ; Vx,Hx,Wdq ; ; vex m:1 p:1 l:x w:i VPAVGW ; Vx,Hx,Wx ; ; vex m:1 p:1 l:x w:i 0xE3 /r ; s:AVX, t:AVX, w:W|R|R, e:4 VPMULHUW ; Vx,Hx,Wx ; ; vex m:1 p:1 l:x w:i 0xE4 /r ; s:AVX, t:AVX, w:W|R|R, e:4 VPMULHW ; Vx,Hx,Wx ; ; vex m:1 p:1 l:x w:i 0xE5 /r ; s:AVX, t:AVX, w:W|R|R, e:4 -VCVTTPD2DQ ; Vdq,Wx ; ; vex m:1 p:1 l:x w:i 0xE6 /r ; s:AVX, t:CONVERT, w:W|R, e:2 +VCVTTPD2DQ ; Vdq,Wx ; ; vex m:1 p:1 l:x w:i 0xE6 /r ; s:AVX, t:CONVERT, w:W|R, e:2, x:IE|PE VCVTDQ2PD ; Vdq,Wq ; ; vex m:1 p:2 l:0 w:i 0xE6 /r ; s:AVX, t:CONVERT, w:W|R, e:5 VCVTDQ2PD ; Vqq,Wdq ; ; vex m:1 p:2 l:1 w:i 0xE6 /r ; s:AVX, t:CONVERT, w:W|R, e:5 -VCVTPD2DQ ; Vdq,Wx ; ; vex m:1 p:3 l:x w:i 0xE6 /r ; s:AVX, t:CONVERT, w:W|R, e:2 +VCVTPD2DQ ; Vdq,Wx ; ; vex m:1 p:3 l:x w:i 0xE6 /r ; s:AVX, t:CONVERT, w:W|R, e:2, x:IE|PE VMOVNTDQ ; Mx,Vx ; ; vex m:1 p:1 l:x w:i 0xE7 /r:mem ; s:AVX, t:AVX, w:W|R, e:1 VPSUBSB ; Vx,Hx,Wx ; ; vex m:1 p:1 l:x w:i 0xE8 /r ; s:AVX, t:AVX, w:W|R|R, e:4 VPSUBSW ; Vx,Hx,Wx ; ; vex m:1 p:1 l:x w:i 0xE9 /r ; s:AVX, t:AVX, w:W|R|R, e:4 diff --git a/isagenerator/instructions/table_vex_2.dat b/isagenerator/instructions/table_vex_2.dat index ec7eebe..634f55a 100644 --- a/isagenerator/instructions/table_vex_2.dat +++ b/isagenerator/instructions/table_vex_2.dat @@ -22,8 +22,8 @@ VTESTPS ; Vx,Wx ; Fv ; vex m:2 p:1 l:x w:0 VTESTPD ; Vx,Wx ; Fv ; vex m:2 p:1 l:x w:0 0x0F /r ; s:AVX, t:LOGICAL_FP, w:R|R|W, f:VPTEST, e:4 # 0x10 - 0x1F -VCVTPH2PS ; Vdq,Wq ; ; vex m:2 p:1 l:0 w:0 0x13 /r ; s:F16C, t:CONVERT, w:W|R, e:11 -VCVTPH2PS ; Vqq,Wdq ; ; vex m:2 p:1 l:1 w:0 0x13 /r ; s:F16C, t:CONVERT, w:W|R, e:11 +VCVTPH2PS ; Vdq,Wq ; ; vex m:2 p:1 l:0 w:0 0x13 /r ; s:F16C, t:CONVERT, w:W|R, e:11, x:IE +VCVTPH2PS ; Vqq,Wdq ; ; vex m:2 p:1 l:1 w:0 0x13 /r ; s:F16C, t:CONVERT, w:W|R, e:11, x:IE VPERMPS ; Vqq,Hqq,Wqq ; ; vex m:2 p:1 l:1 w:0 0x16 /r ; s:AVX2, t:AVX2, w:W|R|R, e:4 VPTEST ; Vx,Wx ; Fv ; vex m:2 p:1 l:x w:i 0x17 /r ; s:AVX, t:LOGICAL, w:R|R|W, f:VPTEST, e:4 VBROADCASTSS ; Vx,Wss ; ; vex m:2 p:1 l:x w:0 0x18 /r ; s:AVX, t:BROADCAST, w:W|R, e:6 @@ -88,6 +88,8 @@ VPSRAVD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 VPSLLVD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0x47 /r ; s:AVX2, t:AVX2, w:W|R|R, e:4 VPSLLVQ ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0x47 /r ; s:AVX2, t:AVX2, w:W|R|R, e:4 +TTMMULTF32PS ; rTt,mTt,vTt ; ; vex m:2 p:0 l:0 w:0 0x48 /r:reg ; s:AMXTRANSPOSE, t:AMX, w:RW|R|R, m:NOTSX|O64, e:AMX_E10 +TMMULTF32PS ; rTt,mTt,vTt ; ; vex m:2 p:1 l:0 w:0 0x48 /r:reg ; s:AMXTF32, t:AMX, w:RW|R|R, m:NOTSX|O64, e:AMX_E4 LDTILECFG ; Moq ; ; vex m:2 p:0 l:0 w:0 0x49 /0:mem ; s:AMXTILE, t:AMX, w:R, m:NOTSX|O64, e:AMX_E1 STTILECFG ; Moq ; ; vex m:2 p:1 l:0 w:0 0x49 /0:mem ; s:AMXTILE, t:AMX, w:W, m:NOTSX|O64, e:AMX_E2 TILELOADD ; rTt,Mt ; ; vex m:2 p:3 l:0 w:0 0x4B /r:mem sibmem ;s:AMXTILE, t:AMX, w:W|R, m:NOTSX|O64, e:AMX_E3 @@ -95,6 +97,8 @@ TILESTORED ; Mt,rTt ; ; vex m:2 p:2 l:0 w:0 TILELOADDT1 ; rTt,Mt ; ; vex m:2 p:1 l:0 w:0 0x4B /r:mem sibmem ;s:AMXTILE, t:AMX, w:W|R, m:NOTSX|O64, e:AMX_E3 TILERELEASE ; ; ; vex m:2 p:0 l:0 w:0 0x49 /0xC0 ; s:AMXTILE, t:AMX, m:NOTSX|O64, e:AMX_E6 TILEZERO ; rTt ; ; vex m:2 p:3 l:0 w:0 0x49 /r:reg rm:0 ; s:AMXTILE, t:AMX, w:W, m:NOTSX|O64, e:AMX_E5 +TILELOADDRST1 ; rTt,Mt ; ; vex m:2 p:1 l:0 w:0 0x4A /r:mem sibmem ; s:AMXMOVRS, t:AMX, w:W|R, m:NOTSX|O64, e:AMX_E3 +TILELOADDRS ; rTt,Mt ; ; vex m:2 p:3 l:0 w:0 0x4A /r:mem sibmem ; s:AMXMOVRS, t:AMX, w:W|R, m:NOTSX|O64, e:AMX_E3 # 0x50 - 0x5F VPDPBUUD ; Vx,Hx,Wx ; ; vex m:2 p:0 l:x w:0 0x50 /r ; s:AVXVNNIINT8, t:AVXVNNIINT8, w:RW|R|R, e:4 @@ -118,10 +122,22 @@ TDPBUUD ; rTt,mTt,vTt ; ; vex m:2 p:0 l:0 w:0 TDPBUSD ; rTt,mTt,vTt ; ; vex m:2 p:1 l:0 w:0 0x5E /r:reg ; s:AMXINT8, t:AMX, w:RW|R|R, m:NOTSX|O64, e:AMX_E4 TDPBSUD ; rTt,mTt,vTt ; ; vex m:2 p:2 l:0 w:0 0x5E /r:reg ; s:AMXINT8, t:AMX, w:RW|R|R, m:NOTSX|O64, e:AMX_E4 TDPBSSD ; rTt,mTt,vTt ; ; vex m:2 p:3 l:0 w:0 0x5E /r:reg ; s:AMXINT8, t:AMX, w:RW|R|R, m:NOTSX|O64, e:AMX_E4 +TTRANSPOSED ; rTt,mTt ; ; vex m:2 p:2 l:0 w:0 0x5F /r:reg ; s:AMXTRANSPOSE, t:AMX, w:W|R, m:NOTSX|O64, e:AMX_E9 # 0x60 - 0x6F +TCONJTCMMIMFP16PS ; rTt,mTt,vTt ; ; vex m:2 p:0 l:0 w:0 0x6B /r:reg ; s:AMXTRANSPOSE, t:AMX, w:RW|R|R, m:NOTSX|O64, e:AMX_E10 +TCONJTFP16 ; rTt,mTt ; ; vex m:2 p:1 l:0 w:0 0x6B /r:reg ; s:AMXTRANSPOSE, t:AMX, w:W|R, m:NOTSX|O64, e:AMX_E9 +TTCMMRLFP16PS ; rTt,mTt,vTt ; ; vex m:2 p:2 l:0 w:0 0x6B /r:reg ; s:AMXTRANSPOSE, t:AMX, w:RW|R|R, m:NOTSX|O64, e:AMX_E10 +TTCMMIMFP16PS ; rTt,mTt,vTt ; ; vex m:2 p:3 l:0 w:0 0x6B /r:reg ; s:AMXTRANSPOSE, t:AMX, w:RW|R|R, m:NOTSX|O64, e:AMX_E10 TCMMRLFP16PS ; rTt,mTt,vTt ; ; vex m:2 p:0 l:0 w:0 0x6C /r:reg ; s:AMXCOMPLEX, t:AMX, w:RW|R|R, m:NOTSX|O64, e:AMX_E4 TCMMIMFP16PS ; rTt,mTt,vTt ; ; vex m:2 p:1 l:0 w:0 0x6C /r:reg ; s:AMXCOMPLEX, t:AMX, w:RW|R|R, m:NOTSX|O64, e:AMX_E4 +TTDPBF16PS ; rTt,mTt,vTt ; ; vex m:2 p:2 l:0 w:0 0x6C /r:reg ; s:AMXTRANSPOSE, t:AMX, w:RW|R|R, m:NOTSX|O64, e:AMX_E10 +TTDPFP16PS ; rTt,mTt,vTt ; ; vex m:2 p:3 l:0 w:0 0x6C /r:reg ; s:AMXTRANSPOSE, t:AMX, w:RW|R|R, m:NOTSX|O64, e:AMX_E10 +T2RPNTLVWZ0 ; rTt+1,Mt ; ; vex m:2 p:0 l:0 w:0 0x6E /r:mem sibmem ; s:AMXTRANSPOSE, t:AMX, w:W|R, m:NOTSX|O64, e:AMX_E11 +T2RPNTLVWZ1 ; rTt+1,Mt ; ; vex m:2 p:1 l:0 w:0 0x6E /r:mem sibmem ; s:AMXTRANSPOSE, t:AMX, w:W|R, m:NOTSX|O64, e:AMX_E11 +T2RPNTLVWZ0T1 ; rTt+1,Mt ; ; vex m:2 p:0 l:0 w:0 0x6F /r:mem sibmem ; s:AMXTRANSPOSE, t:AMX, w:W|R, m:NOTSX|O64, e:AMX_E11 +T2RPNTLVWZ1T1 ; rTt+1,Mt ; ; vex m:2 p:1 l:0 w:0 0x6F /r:mem sibmem ; s:AMXTRANSPOSE, t:AMX, w:W|R, m:NOTSX|O64, e:AMX_E11 + # 0x70 - 0x7F VCVTNEPS2BF16 ; Vx,Wx ; ; vex m:2 p:2 l:x w:0 0x72 /r ; s:AVXNECONVERT, t:AVXNECONVERT, w:W|R, e:4 @@ -144,48 +160,48 @@ VGATHERDPD ; Vx,Mvm32h,Hx ; ; vex m:2 p:1 l:x w:1 VGATHERQPS ; Vdq,Mvm64n,Hdq ; ; vex m:2 p:1 l:x w:0 0x93 /r:mem vsib ; s:AVX2GATHER, t:AVX2GATHER, w:CRW|R|RW, e:12 VGATHERQPD ; Vx,Mvm64n,Hx ; ; vex m:2 p:1 l:x w:1 0x93 /r:mem vsib ; s:AVX2GATHER, t:AVX2GATHER, w:CRW|R|RW, e:12 -VFMADDSUB132PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0x96 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 -VFMADDSUB132PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0x96 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 -VFMSUBADD132PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0x97 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 -VFMSUBADD132PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0x97 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 -VFMADD132PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0x98 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 -VFMADD132PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0x98 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 -VFMADD132SS ; Vdq,Hdq,Wss ; ; vex m:2 p:1 l:i w:0 0x99 /r ; s:FMA, t:VFMA, w:RW|R|R, e:3 -VFMADD132SD ; Vdq,Hdq,Wsd ; ; vex m:2 p:1 l:i w:1 0x99 /r ; s:FMA, t:VFMA, w:RW|R|R, e:3 -VFMSUB132PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0x9A /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 -VFMSUB132PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0x9A /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 -VFMSUB132SS ; Vdq,Hdq,Wss ; ; vex m:2 p:1 l:i w:0 0x9B /r ; s:FMA, t:VFMA, w:RW|R|R, e:3 -VFMSUB132SD ; Vdq,Hdq,Wsd ; ; vex m:2 p:1 l:i w:1 0x9B /r ; s:FMA, t:VFMA, w:RW|R|R, e:3 -VFNMADD132PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0x9C /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 -VFNMADD132PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0x9C /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 -VFNMADD132SS ; Vdq,Hdq,Wss ; ; vex m:2 p:1 l:i w:0 0x9D /r ; s:FMA, t:VFMA, w:RW|R|R, e:3 -VFNMADD132SD ; Vdq,Hdq,Wsd ; ; vex m:2 p:1 l:i w:1 0x9D /r ; s:FMA, t:VFMA, w:RW|R|R, e:3 -VFNMSUB132PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0x9E /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 -VFNMSUB132PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0x9E /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 -VFNMSUB132SS ; Vdq,Hdq,Wss ; ; vex m:2 p:1 l:i w:0 0x9F /r ; s:FMA, t:VFMA, w:RW|R|R, e:3 -VFNMSUB132SD ; Vdq,Hdq,Wsd ; ; vex m:2 p:1 l:i w:1 0x9F /r ; s:FMA, t:VFMA, w:RW|R|R, e:3 +VFMADDSUB132PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0x96 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2, x:IE|OE|UE|PE|DE +VFMADDSUB132PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0x96 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2, x:IE|OE|UE|PE|DE +VFMSUBADD132PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0x97 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2, x:IE|OE|UE|PE|DE +VFMSUBADD132PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0x97 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2, x:IE|OE|UE|PE|DE +VFMADD132PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0x98 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2, x:IE|OE|UE|PE|DE +VFMADD132PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0x98 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2, x:IE|OE|UE|PE|DE +VFMADD132SS ; Vdq,Hdq,Wss ; ; vex m:2 p:1 l:i w:0 0x99 /r ; s:FMA, t:VFMA, w:RW|R|R, e:3, x:IE|OE|UE|PE|DE +VFMADD132SD ; Vdq,Hdq,Wsd ; ; vex m:2 p:1 l:i w:1 0x99 /r ; s:FMA, t:VFMA, w:RW|R|R, e:3, x:IE|OE|UE|PE|DE +VFMSUB132PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0x9A /r ; s:FMA, t:VFMA, w:RW|R|R, e:2, x:IE|OE|UE|PE|DE +VFMSUB132PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0x9A /r ; s:FMA, t:VFMA, w:RW|R|R, e:2, x:IE|OE|UE|PE|DE +VFMSUB132SS ; Vdq,Hdq,Wss ; ; vex m:2 p:1 l:i w:0 0x9B /r ; s:FMA, t:VFMA, w:RW|R|R, e:3, x:IE|OE|UE|PE|DE +VFMSUB132SD ; Vdq,Hdq,Wsd ; ; vex m:2 p:1 l:i w:1 0x9B /r ; s:FMA, t:VFMA, w:RW|R|R, e:3, x:IE|OE|UE|PE|DE +VFNMADD132PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0x9C /r ; s:FMA, t:VFMA, w:RW|R|R, e:2, x:IE|OE|UE|PE|DE +VFNMADD132PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0x9C /r ; s:FMA, t:VFMA, w:RW|R|R, e:2, x:IE|OE|UE|PE|DE +VFNMADD132SS ; Vdq,Hdq,Wss ; ; vex m:2 p:1 l:i w:0 0x9D /r ; s:FMA, t:VFMA, w:RW|R|R, e:3, x:IE|OE|UE|PE|DE +VFNMADD132SD ; Vdq,Hdq,Wsd ; ; vex m:2 p:1 l:i w:1 0x9D /r ; s:FMA, t:VFMA, w:RW|R|R, e:3, x:IE|OE|UE|PE|DE +VFNMSUB132PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0x9E /r ; s:FMA, t:VFMA, w:RW|R|R, e:2, x:IE|OE|UE|PE|DE +VFNMSUB132PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0x9E /r ; s:FMA, t:VFMA, w:RW|R|R, e:2, x:IE|OE|UE|PE|DE +VFNMSUB132SS ; Vdq,Hdq,Wss ; ; vex m:2 p:1 l:i w:0 0x9F /r ; s:FMA, t:VFMA, w:RW|R|R, e:3, x:IE|OE|UE|PE|DE +VFNMSUB132SD ; Vdq,Hdq,Wsd ; ; vex m:2 p:1 l:i w:1 0x9F /r ; s:FMA, t:VFMA, w:RW|R|R, e:3, x:IE|OE|UE|PE|DE # 0xA0 - 0xAF -VFMADDSUB213PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0xA6 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 -VFMADDSUB213PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0xA6 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 -VFMSUBADD213PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0xA7 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 -VFMSUBADD213PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0xA7 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 -VFMADD213PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0xA8 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 -VFMADD213PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0xA8 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 -VFMADD213SS ; Vdq,Hdq,Wss ; ; vex m:2 p:1 l:i w:0 0xA9 /r ; s:FMA, t:VFMA, w:RW|R|R, e:3 -VFMADD213SD ; Vdq,Hdq,Wsd ; ; vex m:2 p:1 l:i w:1 0xA9 /r ; s:FMA, t:VFMA, w:RW|R|R, e:3 -VFMSUB213PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0xAA /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 -VFMSUB213PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0xAA /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 -VFMSUB213SS ; Vdq,Hdq,Wss ; ; vex m:2 p:1 l:i w:0 0xAB /r ; s:FMA, t:VFMA, w:RW|R|R, e:3 -VFMSUB213SD ; Vdq,Hdq,Wsd ; ; vex m:2 p:1 l:i w:1 0xAB /r ; s:FMA, t:VFMA, w:RW|R|R, e:3 -VFNMADD213PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0xAC /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 -VFNMADD213PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0xAC /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 -VFNMADD213SS ; Vdq,Hdq,Wss ; ; vex m:2 p:1 l:i w:0 0xAD /r ; s:FMA, t:VFMA, w:RW|R|R, e:3 -VFNMADD213SD ; Vdq,Hdq,Wsd ; ; vex m:2 p:1 l:i w:1 0xAD /r ; s:FMA, t:VFMA, w:RW|R|R, e:3 -VFNMSUB213PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0xAE /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 -VFNMSUB213PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0xAE /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 -VFNMSUB213SS ; Vdq,Hdq,Wss ; ; vex m:2 p:1 l:i w:0 0xAF /r ; s:FMA, t:VFMA, w:RW|R|R, e:3 -VFNMSUB213SD ; Vdq,Hdq,Wsd ; ; vex m:2 p:1 l:i w:1 0xAF /r ; s:FMA, t:VFMA, w:RW|R|R, e:3 +VFMADDSUB213PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0xA6 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2, x:IE|OE|UE|PE|DE +VFMADDSUB213PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0xA6 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2, x:IE|OE|UE|PE|DE +VFMSUBADD213PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0xA7 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2, x:IE|OE|UE|PE|DE +VFMSUBADD213PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0xA7 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2, x:IE|OE|UE|PE|DE +VFMADD213PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0xA8 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2, x:IE|OE|UE|PE|DE +VFMADD213PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0xA8 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2, x:IE|OE|UE|PE|DE +VFMADD213SS ; Vdq,Hdq,Wss ; ; vex m:2 p:1 l:i w:0 0xA9 /r ; s:FMA, t:VFMA, w:RW|R|R, e:3, x:IE|OE|UE|PE|DE +VFMADD213SD ; Vdq,Hdq,Wsd ; ; vex m:2 p:1 l:i w:1 0xA9 /r ; s:FMA, t:VFMA, w:RW|R|R, e:3, x:IE|OE|UE|PE|DE +VFMSUB213PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0xAA /r ; s:FMA, t:VFMA, w:RW|R|R, e:2, x:IE|OE|UE|PE|DE +VFMSUB213PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0xAA /r ; s:FMA, t:VFMA, w:RW|R|R, e:2, x:IE|OE|UE|PE|DE +VFMSUB213SS ; Vdq,Hdq,Wss ; ; vex m:2 p:1 l:i w:0 0xAB /r ; s:FMA, t:VFMA, w:RW|R|R, e:3, x:IE|OE|UE|PE|DE +VFMSUB213SD ; Vdq,Hdq,Wsd ; ; vex m:2 p:1 l:i w:1 0xAB /r ; s:FMA, t:VFMA, w:RW|R|R, e:3, x:IE|OE|UE|PE|DE +VFNMADD213PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0xAC /r ; s:FMA, t:VFMA, w:RW|R|R, e:2, x:IE|OE|UE|PE|DE +VFNMADD213PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0xAC /r ; s:FMA, t:VFMA, w:RW|R|R, e:2, x:IE|OE|UE|PE|DE +VFNMADD213SS ; Vdq,Hdq,Wss ; ; vex m:2 p:1 l:i w:0 0xAD /r ; s:FMA, t:VFMA, w:RW|R|R, e:3, x:IE|OE|UE|PE|DE +VFNMADD213SD ; Vdq,Hdq,Wsd ; ; vex m:2 p:1 l:i w:1 0xAD /r ; s:FMA, t:VFMA, w:RW|R|R, e:3, x:IE|OE|UE|PE|DE +VFNMSUB213PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0xAE /r ; s:FMA, t:VFMA, w:RW|R|R, e:2, x:IE|OE|UE|PE|DE +VFNMSUB213PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0xAE /r ; s:FMA, t:VFMA, w:RW|R|R, e:2, x:IE|OE|UE|PE|DE +VFNMSUB213SS ; Vdq,Hdq,Wss ; ; vex m:2 p:1 l:i w:0 0xAF /r ; s:FMA, t:VFMA, w:RW|R|R, e:3, x:IE|OE|UE|PE|DE +VFNMSUB213SD ; Vdq,Hdq,Wsd ; ; vex m:2 p:1 l:i w:1 0xAF /r ; s:FMA, t:VFMA, w:RW|R|R, e:3, x:IE|OE|UE|PE|DE # 0xB0 - 0xBF VCVTNEOPH2PS ; Vx,Mx ; ; vex m:2 p:0 l:x w:0 0xB0 /r:mem ; s:AVXNECONVERT, t:AVXNECONVERT, w:W|R, e:4 @@ -198,26 +214,26 @@ VBCSTNEBF162PS ; Vx,Mw ; ; vex m:2 p:2 l:x w:0 VPMADD52LUQ ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0xB4 /r ; s:AVXIFMA, t:AVXIFMA, w:RW|R|R, e:4 VPMADD52HUQ ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0xB5 /r ; s:AVXIFMA, t:AVXIFMA, w:RW|R|R, e:4 -VFMADDSUB231PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0xB6 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 -VFMADDSUB231PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0xB6 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 -VFMSUBADD231PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0xB7 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 -VFMSUBADD231PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0xB7 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 -VFMADD231PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0xB8 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 -VFMADD231PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0xB8 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 -VFMADD231SS ; Vdq,Hdq,Wss ; ; vex m:2 p:1 l:i w:0 0xB9 /r ; s:FMA, t:VFMA, w:RW|R|R, e:3 -VFMADD231SD ; Vdq,Hdq,Wsd ; ; vex m:2 p:1 l:i w:1 0xB9 /r ; s:FMA, t:VFMA, w:RW|R|R, e:3 -VFMSUB231PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0xBA /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 -VFMSUB231PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0xBA /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 -VFMSUB231SS ; Vdq,Hdq,Wss ; ; vex m:2 p:1 l:i w:0 0xBB /r ; s:FMA, t:VFMA, w:RW|R|R, e:3 -VFMSUB231SD ; Vdq,Hdq,Wsd ; ; vex m:2 p:1 l:i w:1 0xBB /r ; s:FMA, t:VFMA, w:RW|R|R, e:3 -VFNMADD231PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0xBC /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 -VFNMADD231PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0xBC /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 -VFNMADD231SS ; Vdq,Hdq,Wss ; ; vex m:2 p:1 l:i w:0 0xBD /r ; s:FMA, t:VFMA, w:RW|R|R, e:3 -VFNMADD231SD ; Vdq,Hdq,Wsd ; ; vex m:2 p:1 l:i w:1 0xBD /r ; s:FMA, t:VFMA, w:RW|R|R, e:3 -VFNMSUB231PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0xBE /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 -VFNMSUB231PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0xBE /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 -VFNMSUB231SS ; Vdq,Hdq,Wss ; ; vex m:2 p:1 l:i w:0 0xBF /r ; s:FMA, t:VFMA, w:RW|R|R, e:3 -VFNMSUB231SD ; Vdq,Hdq,Wsd ; ; vex m:2 p:1 l:i w:1 0xBF /r ; s:FMA, t:VFMA, w:RW|R|R, e:3 +VFMADDSUB231PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0xB6 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2, x:IE|OE|UE|PE|DE +VFMADDSUB231PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0xB6 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2, x:IE|OE|UE|PE|DE +VFMSUBADD231PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0xB7 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2, x:IE|OE|UE|PE|DE +VFMSUBADD231PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0xB7 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2, x:IE|OE|UE|PE|DE +VFMADD231PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0xB8 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2, x:IE|OE|UE|PE|DE +VFMADD231PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0xB8 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2, x:IE|OE|UE|PE|DE +VFMADD231SS ; Vdq,Hdq,Wss ; ; vex m:2 p:1 l:i w:0 0xB9 /r ; s:FMA, t:VFMA, w:RW|R|R, e:3, x:IE|OE|UE|PE|DE +VFMADD231SD ; Vdq,Hdq,Wsd ; ; vex m:2 p:1 l:i w:1 0xB9 /r ; s:FMA, t:VFMA, w:RW|R|R, e:3, x:IE|OE|UE|PE|DE +VFMSUB231PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0xBA /r ; s:FMA, t:VFMA, w:RW|R|R, e:2, x:IE|OE|UE|PE|DE +VFMSUB231PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0xBA /r ; s:FMA, t:VFMA, w:RW|R|R, e:2, x:IE|OE|UE|PE|DE +VFMSUB231SS ; Vdq,Hdq,Wss ; ; vex m:2 p:1 l:i w:0 0xBB /r ; s:FMA, t:VFMA, w:RW|R|R, e:3, x:IE|OE|UE|PE|DE +VFMSUB231SD ; Vdq,Hdq,Wsd ; ; vex m:2 p:1 l:i w:1 0xBB /r ; s:FMA, t:VFMA, w:RW|R|R, e:3, x:IE|OE|UE|PE|DE +VFNMADD231PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0xBC /r ; s:FMA, t:VFMA, w:RW|R|R, e:2, x:IE|OE|UE|PE|DE +VFNMADD231PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0xBC /r ; s:FMA, t:VFMA, w:RW|R|R, e:2, x:IE|OE|UE|PE|DE +VFNMADD231SS ; Vdq,Hdq,Wss ; ; vex m:2 p:1 l:i w:0 0xBD /r ; s:FMA, t:VFMA, w:RW|R|R, e:3, x:IE|OE|UE|PE|DE +VFNMADD231SD ; Vdq,Hdq,Wsd ; ; vex m:2 p:1 l:i w:1 0xBD /r ; s:FMA, t:VFMA, w:RW|R|R, e:3, x:IE|OE|UE|PE|DE +VFNMSUB231PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0xBE /r ; s:FMA, t:VFMA, w:RW|R|R, e:2, x:IE|OE|UE|PE|DE +VFNMSUB231PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0xBE /r ; s:FMA, t:VFMA, w:RW|R|R, e:2, x:IE|OE|UE|PE|DE +VFNMSUB231SS ; Vdq,Hdq,Wss ; ; vex m:2 p:1 l:i w:0 0xBF /r ; s:FMA, t:VFMA, w:RW|R|R, e:3, x:IE|OE|UE|PE|DE +VFNMSUB231SD ; Vdq,Hdq,Wsd ; ; vex m:2 p:1 l:i w:1 0xBF /r ; s:FMA, t:VFMA, w:RW|R|R, e:3, x:IE|OE|UE|PE|DE VSHA512RNDS2 ; Vqq,Hqq,Udq ; ; vex m:2 p:3 l:1 w:0 0xCB /r:reg ; s:SHA512, t:SHA512, w:RW|R|R, e:6 VSHA512MSG1 ; Vqq,Udq ; ; vex m:2 p:3 l:1 w:0 0xCC /r:reg ; s:SHA512, t:SHA512, w:RW|R, e:6 diff --git a/isagenerator/instructions/table_vex_3.dat b/isagenerator/instructions/table_vex_3.dat index 87af2a1..e368d31 100644 --- a/isagenerator/instructions/table_vex_3.dat +++ b/isagenerator/instructions/table_vex_3.dat @@ -10,10 +10,10 @@ VPBLENDD ; Vx,Hx,Wx,Ib ; ; vex m:3 p:1 l:x w:0 VPERMILPS ; Vx,Wx,Ib ; ; vex m:3 p:1 l:x w:0 0x04 /r ib ; s:AVX, t:AVX, w:W|R|R, e:4 VPERMILPD ; Vx,Wx,Ib ; ; vex m:3 p:1 l:x w:0 0x05 /r ib ; s:AVX, t:AVX, w:W|R|R, e:4 VPERM2F128 ; Vqq,Hqq,Wqq,Ib ; ; vex m:3 p:1 l:1 w:0 0x06 /r ib ; s:AVX, t:AVX, w:W|R|R|R, e:4 -VROUNDPS ; Vx,Wx,Ib ; ; vex m:3 p:1 l:x w:i 0x08 /r ib ; s:AVX, t:AVX, w:W|R|R, e:2 -VROUNDPD ; Vx,Wx,Ib ; ; vex m:3 p:1 l:x w:i 0x09 /r ib ; s:AVX, t:AVX, w:W|R|R, e:2 -VROUNDSS ; Vss,Hss,Wss,Ib ; ; vex m:3 p:1 l:i w:i 0x0A /r ib ; s:AVX, t:AVX, w:W|R|R|R, e:3 -VROUNDSD ; Vsd,Hsd,Wsd,Ib ; ; vex m:3 p:1 l:i w:i 0x0B /r ib ; s:AVX, t:AVX, w:W|R|R|R, e:3 +VROUNDPS ; Vx,Wx,Ib ; ; vex m:3 p:1 l:x w:i 0x08 /r ib ; s:AVX, t:AVX, w:W|R|R, e:2, x:IE|PE +VROUNDPD ; Vx,Wx,Ib ; ; vex m:3 p:1 l:x w:i 0x09 /r ib ; s:AVX, t:AVX, w:W|R|R, e:2, x:IE|PE +VROUNDSS ; Vss,Hss,Wss,Ib ; ; vex m:3 p:1 l:i w:i 0x0A /r ib ; s:AVX, t:AVX, w:W|R|R|R, e:3, x:IE|PE +VROUNDSD ; Vsd,Hsd,Wsd,Ib ; ; vex m:3 p:1 l:i w:i 0x0B /r ib ; s:AVX, t:AVX, w:W|R|R|R, e:3, x:IE|PE VBLENDPS ; Vx,Hx,Wx,Ib ; ; vex m:3 p:1 l:x w:i 0x0C /r ib ; s:AVX, t:AVX, w:W|R|R|R, e:4 VBLENDPD ; Vx,Hx,Wx,Ib ; ; vex m:3 p:1 l:x w:i 0x0D /r ib ; s:AVX, t:AVX, w:W|R|R|R, e:4 VPBLENDW ; Vx,Hx,Wx,Ib ; ; vex m:3 p:1 l:x w:i 0x0E /r ib ; s:AVX, t:AVX, w:W|R|R|R, e:4 @@ -32,8 +32,8 @@ VEXTRACTPS ; Md,Vdq,Ib ; ; vex m:3 p:1 l:0 w:i VEXTRACTPS ; Ry,Vdq,Ib ; ; vex m:3 p:1 l:0 w:i 0x17 /r:reg ib ; s:AVX, t:AVX, w:W|R|R, e:5 VINSERTF128 ; Vqq,Hqq,Wdq,Ib ; ; vex m:3 p:1 l:1 w:0 0x18 /r ib ; s:AVX, t:AVX, w:W|R|R|R, e:6 VEXTRACTF128 ; Wdq,Vqq,Ib ; ; vex m:3 p:1 l:1 w:0 0x19 /r ib ; s:AVX, t:AVX, w:W|R|R, e:6 -VCVTPS2PH ; Wq,Vdq,Ib ; ; vex m:3 p:1 l:0 w:0 0x1D /r ib ; s:F16C, t:CONVERT, w:W|R|R, e:11 -VCVTPS2PH ; Wdq,Vqq,Ib ; ; vex m:3 p:1 l:1 w:0 0x1D /r ib ; s:F16C, t:CONVERT, w:W|R|R, e:11 +VCVTPS2PH ; Wq,Vdq,Ib ; ; vex m:3 p:1 l:0 w:0 0x1D /r ib ; s:F16C, t:CONVERT, w:W|R|R, e:11, x:IE|OE|UE|PE|DE +VCVTPS2PH ; Wdq,Vqq,Ib ; ; vex m:3 p:1 l:1 w:0 0x1D /r ib ; s:F16C, t:CONVERT, w:W|R|R, e:11, x:IE|OE|UE|PE|DE # 0x20 - 0x2F VPINSRB ; Vdq,Hdq,Mb,Ib ; ; vex m:3 p:1 l:0 w:i 0x20 /r:mem ib ; s:AVX, t:AVX, w:W|R|R|R, e:5 @@ -56,8 +56,8 @@ VINSERTI128 ; Vqq,Hqq,Wdq,Ib ; ; vex m:3 p:1 l:1 w:0 VEXTRACTI128 ; Wdq,Vqq,Ib ; ; vex m:3 p:1 l:1 w:0 0x39 /r ib ; s:AVX2, t:AVX2, w:W|R|R|R, e:6 # 0x40 - 0x4F -VDPPS ; Vx,Hx,Wx,Ib ; ; vex m:3 p:1 l:x w:i 0x40 /r ib ; s:AVX, t:AVX, w:W|R|R|R, e:2 -VDPPD ; Vdq,Hdq,Wdq,Ib ; ; vex m:3 p:1 l:0 w:i 0x41 /r ib ; s:AVX, t:AVX, w:W|R|R|R, e:2 +VDPPS ; Vx,Hx,Wx,Ib ; ; vex m:3 p:1 l:x w:i 0x40 /r ib ; s:AVX, t:AVX, w:W|R|R|R, e:2, x:IE|OE|UE|PE|DE +VDPPD ; Vdq,Hdq,Wdq,Ib ; ; vex m:3 p:1 l:0 w:i 0x41 /r ib ; s:AVX, t:AVX, w:W|R|R|R, e:2, x:IE|OE|UE|PE|DE VMPSADBW ; Vx,Hx,Wx,Ib ; ; vex m:3 p:1 l:x w:i 0x42 /r ib ; s:AVX, t:AVX, w:W|R|R|R, e:4 VPCLMULQDQ ; Vx,Hx,Wx,Ib ; ; vex m:3 p:1 l:x w:i 0x44 /r ib ; s:VPCLMULQDQ, t:VPCLMULQDQ, w:W|R|R|R, e:4 VPERM2I128 ; Vqq,Hqq,Wqq,Ib ; ; vex m:3 p:1 l:1 w:0 0x46 /r ib ; s:AVX2, t:AVX2, w:W|R|R|R, e:6 @@ -70,54 +70,54 @@ VBLENDVPD ; Vx,Hx,Wx,Lx ; ; vex m:3 p:1 l:x w:0 VPBLENDVB ; Vx,Hx,Wx,Lx ; ; vex m:3 p:1 l:x w:0 0x4C /r is4 ; s:AVX, t:AVX, w:W|R|R|R, e:4 # 0x50 - 0x5F -VFMADDSUBPS ; Vx,Hx,Wx,Lx ; ; vex m:3 p:1 l:x w:0 0x5C /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R -VFMADDSUBPS ; Vx,Hx,Lx,Wx ; ; vex m:3 p:1 l:x w:1 0x5C /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R -VFMADDSUBPD ; Vx,Hx,Wx,Lx ; ; vex m:3 p:1 l:x w:0 0x5D /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R -VFMADDSUBPD ; Vx,Hx,Lx,Wx ; ; vex m:3 p:1 l:x w:1 0x5D /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R -VFMSUBADDPS ; Vx,Hx,Wx,Lx ; ; vex m:3 p:1 l:x w:0 0x5E /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R -VFMSUBADDPS ; Vx,Hx,Lx,Wx ; ; vex m:3 p:1 l:x w:1 0x5E /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R -VFMSUBADDPD ; Vx,Hx,Wx,Lx ; ; vex m:3 p:1 l:x w:0 0x5F /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R -VFMSUBADDPD ; Vx,Hx,Lx,Wx ; ; vex m:3 p:1 l:x w:1 0x5F /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R +VFMADDSUBPS ; Vx,Hx,Wx,Lx ; ; vex m:3 p:1 l:x w:0 0x5C /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R, x:IE|OE|UE|PE|DE +VFMADDSUBPS ; Vx,Hx,Lx,Wx ; ; vex m:3 p:1 l:x w:1 0x5C /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R, x:IE|OE|UE|PE|DE +VFMADDSUBPD ; Vx,Hx,Wx,Lx ; ; vex m:3 p:1 l:x w:0 0x5D /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R, x:IE|OE|UE|PE|DE +VFMADDSUBPD ; Vx,Hx,Lx,Wx ; ; vex m:3 p:1 l:x w:1 0x5D /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R, x:IE|OE|UE|PE|DE +VFMSUBADDPS ; Vx,Hx,Wx,Lx ; ; vex m:3 p:1 l:x w:0 0x5E /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R, x:IE|OE|UE|PE|DE +VFMSUBADDPS ; Vx,Hx,Lx,Wx ; ; vex m:3 p:1 l:x w:1 0x5E /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R, x:IE|OE|UE|PE|DE +VFMSUBADDPD ; Vx,Hx,Wx,Lx ; ; vex m:3 p:1 l:x w:0 0x5F /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R, x:IE|OE|UE|PE|DE +VFMSUBADDPD ; Vx,Hx,Lx,Wx ; ; vex m:3 p:1 l:x w:1 0x5F /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R, x:IE|OE|UE|PE|DE # 0x60 - 0x6F VPCMPESTRM ; Vdq,Wdq,Ib ; yAX,yDX,XMM0,Fv ; vex m:3 p:1 l:0 w:i 0x60 /r ib ; s:AVX, t:STTNI, w:R|R|R|R|R|W|W, f:PCMPSTR, e:4 VPCMPESTRI ; Vdq,Wdq,Ib ; yAX,yDX,yCX,Fv ; vex m:3 p:1 l:0 w:i 0x61 /r ib ; s:AVX, t:STTNI, w:R|R|R|R|R|W|W, f:PCMPSTR, e:4 VPCMPISTRM ; Vdq,Wdq,Ib ; XMM0,Fv ; vex m:3 p:1 l:0 w:i 0x62 /r ib ; s:AVX, t:STTNI, w:R|R|R|W|W, f:PCMPSTR, e:4 VPCMPISTRI ; Vdq,Wdq,Ib ; yCX,Fv ; vex m:3 p:1 l:0 w:i 0x63 /r ib ; s:AVX, t:STTNI, w:R|R|R|W|W, f:PCMPSTR, e:4 -VFMADDPS ; Vx,Hx,Wx,Lx ; ; vex m:3 p:1 l:x w:0 0x68 /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R -VFMADDPS ; Vx,Hx,Lx,Wx ; ; vex m:3 p:1 l:x w:1 0x68 /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R -VFMADDPD ; Vx,Hx,Wx,Lx ; ; vex m:3 p:1 l:x w:0 0x69 /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R -VFMADDPD ; Vx,Hx,Lx,Wx ; ; vex m:3 p:1 l:x w:1 0x69 /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R -VFMADDSS ; Vdq,Hdq,Wss,Ldq ; ; vex m:3 p:1 l:x w:0 0x6A /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R -VFMADDSS ; Vdq,Hdq,Ldq,Wss ; ; vex m:3 p:1 l:x w:1 0x6A /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R -VFMADDSD ; Vdq,Hdq,Wsd,Ldq ; ; vex m:3 p:1 l:x w:0 0x6B /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R -VFMADDSD ; Vdq,Hdq,Ldq,Wsd ; ; vex m:3 p:1 l:x w:1 0x6B /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R -VFMSUBPS ; Vx,Hx,Wx,Lx ; ; vex m:3 p:1 l:x w:0 0x6C /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R -VFMSUBPS ; Vx,Hx,Lx,Wx ; ; vex m:3 p:1 l:x w:1 0x6C /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R -VFMSUBPD ; Vx,Hx,Wx,Lx ; ; vex m:3 p:1 l:x w:0 0x6D /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R -VFMSUBPD ; Vx,Hx,Lx,Wx ; ; vex m:3 p:1 l:x w:1 0x6D /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R -VFMSUBSS ; Vdq,Hdq,Wss,Ldq ; ; vex m:3 p:1 l:x w:0 0x6E /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R -VFMSUBSS ; Vdq,Hdq,Ldq,Wss ; ; vex m:3 p:1 l:x w:1 0x6E /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R -VFMSUBSD ; Vdq,Hdq,Wsd,Ldq ; ; vex m:3 p:1 l:x w:0 0x6F /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R -VFMSUBSD ; Vdq,Hdq,Ldq,Wsd ; ; vex m:3 p:1 l:x w:1 0x6F /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R +VFMADDPS ; Vx,Hx,Wx,Lx ; ; vex m:3 p:1 l:x w:0 0x68 /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R, x:IE|OE|UE|PE|DE +VFMADDPS ; Vx,Hx,Lx,Wx ; ; vex m:3 p:1 l:x w:1 0x68 /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R, x:IE|OE|UE|PE|DE +VFMADDPD ; Vx,Hx,Wx,Lx ; ; vex m:3 p:1 l:x w:0 0x69 /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R, x:IE|OE|UE|PE|DE +VFMADDPD ; Vx,Hx,Lx,Wx ; ; vex m:3 p:1 l:x w:1 0x69 /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R, x:IE|OE|UE|PE|DE +VFMADDSS ; Vdq,Hdq,Wss,Ldq ; ; vex m:3 p:1 l:x w:0 0x6A /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R, x:IE|OE|UE|PE|DE +VFMADDSS ; Vdq,Hdq,Ldq,Wss ; ; vex m:3 p:1 l:x w:1 0x6A /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R, x:IE|OE|UE|PE|DE +VFMADDSD ; Vdq,Hdq,Wsd,Ldq ; ; vex m:3 p:1 l:x w:0 0x6B /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R, x:IE|OE|UE|PE|DE +VFMADDSD ; Vdq,Hdq,Ldq,Wsd ; ; vex m:3 p:1 l:x w:1 0x6B /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R, x:IE|OE|UE|PE|DE +VFMSUBPS ; Vx,Hx,Wx,Lx ; ; vex m:3 p:1 l:x w:0 0x6C /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R, x:IE|OE|UE|PE|DE +VFMSUBPS ; Vx,Hx,Lx,Wx ; ; vex m:3 p:1 l:x w:1 0x6C /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R, x:IE|OE|UE|PE|DE +VFMSUBPD ; Vx,Hx,Wx,Lx ; ; vex m:3 p:1 l:x w:0 0x6D /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R, x:IE|OE|UE|PE|DE +VFMSUBPD ; Vx,Hx,Lx,Wx ; ; vex m:3 p:1 l:x w:1 0x6D /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R, x:IE|OE|UE|PE|DE +VFMSUBSS ; Vdq,Hdq,Wss,Ldq ; ; vex m:3 p:1 l:x w:0 0x6E /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R, x:IE|OE|UE|PE|DE +VFMSUBSS ; Vdq,Hdq,Ldq,Wss ; ; vex m:3 p:1 l:x w:1 0x6E /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R, x:IE|OE|UE|PE|DE +VFMSUBSD ; Vdq,Hdq,Wsd,Ldq ; ; vex m:3 p:1 l:x w:0 0x6F /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R, x:IE|OE|UE|PE|DE +VFMSUBSD ; Vdq,Hdq,Ldq,Wsd ; ; vex m:3 p:1 l:x w:1 0x6F /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R, x:IE|OE|UE|PE|DE # 0x70 - 0x7F -VFNMADDPS ; Vx,Hx,Wx,Lx ; ; vex m:3 p:1 l:x w:0 0x78 /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R -VFNMADDPS ; Vx,Hx,Lx,Wx ; ; vex m:3 p:1 l:x w:1 0x78 /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R -VFNMADDPD ; Vx,Hx,Wx,Lx ; ; vex m:3 p:1 l:x w:0 0x79 /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R -VFNMADDPD ; Vx,Hx,Lx,Wx ; ; vex m:3 p:1 l:x w:1 0x79 /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R -VFNMADDSS ; Vdq,Hdq,Wss,Ldq ; ; vex m:3 p:1 l:x w:0 0x7A /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R -VFNMADDSS ; Vdq,Hdq,Ldq,Wss ; ; vex m:3 p:1 l:x w:1 0x7A /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R -VFNMADDSD ; Vdq,Hdq,Wsd,Ldq ; ; vex m:3 p:1 l:x w:0 0x7B /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R -VFNMADDSD ; Vdq,Hdq,Ldq,Wsd ; ; vex m:3 p:1 l:x w:1 0x7B /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R -VFNMSUBPS ; Vx,Hx,Wx,Lx ; ; vex m:3 p:1 l:x w:0 0x7C /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R -VFNMSUBPS ; Vx,Hx,Lx,Wx ; ; vex m:3 p:1 l:x w:1 0x7C /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R -VFNMSUBPD ; Vx,Hx,Wx,Lx ; ; vex m:3 p:1 l:x w:0 0x7D /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R -VFNMSUBPD ; Vx,Hx,Lx,Wx ; ; vex m:3 p:1 l:x w:1 0x7D /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R -VFNMSUBSS ; Vdq,Hdq,Wss,Ldq ; ; vex m:3 p:1 l:x w:0 0x7E /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R -VFNMSUBSS ; Vdq,Hdq,Ldq,Wss ; ; vex m:3 p:1 l:x w:1 0x7E /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R -VFNMSUBSD ; Vdq,Hdq,Wsd,Ldq ; ; vex m:3 p:1 l:x w:0 0x7F /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R -VFNMSUBSD ; Vdq,Hdq,Ldq,Wsd ; ; vex m:3 p:1 l:x w:1 0x7F /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R +VFNMADDPS ; Vx,Hx,Wx,Lx ; ; vex m:3 p:1 l:x w:0 0x78 /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R, x:IE|OE|UE|PE|DE +VFNMADDPS ; Vx,Hx,Lx,Wx ; ; vex m:3 p:1 l:x w:1 0x78 /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R, x:IE|OE|UE|PE|DE +VFNMADDPD ; Vx,Hx,Wx,Lx ; ; vex m:3 p:1 l:x w:0 0x79 /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R, x:IE|OE|UE|PE|DE +VFNMADDPD ; Vx,Hx,Lx,Wx ; ; vex m:3 p:1 l:x w:1 0x79 /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R, x:IE|OE|UE|PE|DE +VFNMADDSS ; Vdq,Hdq,Wss,Ldq ; ; vex m:3 p:1 l:x w:0 0x7A /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R, x:IE|OE|UE|PE|DE +VFNMADDSS ; Vdq,Hdq,Ldq,Wss ; ; vex m:3 p:1 l:x w:1 0x7A /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R, x:IE|OE|UE|PE|DE +VFNMADDSD ; Vdq,Hdq,Wsd,Ldq ; ; vex m:3 p:1 l:x w:0 0x7B /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R, x:IE|OE|UE|PE|DE +VFNMADDSD ; Vdq,Hdq,Ldq,Wsd ; ; vex m:3 p:1 l:x w:1 0x7B /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R, x:IE|OE|UE|PE|DE +VFNMSUBPS ; Vx,Hx,Wx,Lx ; ; vex m:3 p:1 l:x w:0 0x7C /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R, x:IE|OE|UE|PE|DE +VFNMSUBPS ; Vx,Hx,Lx,Wx ; ; vex m:3 p:1 l:x w:1 0x7C /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R, x:IE|OE|UE|PE|DE +VFNMSUBPD ; Vx,Hx,Wx,Lx ; ; vex m:3 p:1 l:x w:0 0x7D /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R, x:IE|OE|UE|PE|DE +VFNMSUBPD ; Vx,Hx,Lx,Wx ; ; vex m:3 p:1 l:x w:1 0x7D /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R, x:IE|OE|UE|PE|DE +VFNMSUBSS ; Vdq,Hdq,Wss,Ldq ; ; vex m:3 p:1 l:x w:0 0x7E /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R, x:IE|OE|UE|PE|DE +VFNMSUBSS ; Vdq,Hdq,Ldq,Wss ; ; vex m:3 p:1 l:x w:1 0x7E /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R, x:IE|OE|UE|PE|DE +VFNMSUBSD ; Vdq,Hdq,Wsd,Ldq ; ; vex m:3 p:1 l:x w:0 0x7F /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R, x:IE|OE|UE|PE|DE +VFNMSUBSD ; Vdq,Hdq,Ldq,Wsd ; ; vex m:3 p:1 l:x w:1 0x7F /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R, x:IE|OE|UE|PE|DE # 0xC0 - 0xCF VGF2P8AFFINEQB ; Vx,Hx,Wx,Ib ; ; vex m:3 p:1 l:x w:1 0xCE /r ib ; s:GFNI, t:GFNI, w:W|R|R|R, e:4 diff --git a/isagenerator/instructions/table_vex_5.dat b/isagenerator/instructions/table_vex_5.dat new file mode 100644 index 0000000..1c4d6be --- /dev/null +++ b/isagenerator/instructions/table_vex_5.dat @@ -0,0 +1,14 @@ +# +# Copyright (c) 2024 Bitdefender +# SPDX-License-Identifier: Apache-2.0 +# + +T2RPNTLVWZ0RS ; rTt+1,Mt ; ; vex m:5 p:0 l:0 w:0 0xF8 /r:mem sibmem ; s:AMXTRANSPOSE, t:AMX, w:W|R, m:NOTSX|O64, e:AMX_E11 +T2RPNTLVWZ1RS ; rTt+1,Mt ; ; vex m:5 p:1 l:0 w:0 0xF8 /r:mem sibmem ; s:AMXTRANSPOSE, t:AMX, w:W|R, m:NOTSX|O64, e:AMX_E11 +T2RPNTLVWZ0RST1 ; rTt+1,Mt ; ; vex m:5 p:0 l:0 w:0 0xF9 /r:mem sibmem ; s:AMXTRANSPOSE, t:AMX, w:W|R, m:NOTSX|O64, e:AMX_E11 +T2RPNTLVWZ1RST1 ; rTt+1,Mt ; ; vex m:5 p:1 l:0 w:0 0xF9 /r:mem sibmem ; s:AMXTRANSPOSE, t:AMX, w:W|R, m:NOTSX|O64, e:AMX_E11 + +TDPBF8PS ; rTt,mTt,vTt ; ; vex m:5 p:0 l:0 w:0 0xFD /r:reg ; s:AMXFP8, t:AMX, w:RW|R|R, m:NOTSX|O64, e:AMX_E4 +TDPHF8PS ; rTt,mTt,vTt ; ; vex m:5 p:1 l:0 w:0 0xFD /r:reg ; s:AMXFP8, t:AMX, w:RW|R|R, m:NOTSX|O64, e:AMX_E4 +TDPHBF8PS ; rTt,mTt,vTt ; ; vex m:5 p:2 l:0 w:0 0xFD /r:reg ; s:AMXFP8, t:AMX, w:RW|R|R, m:NOTSX|O64, e:AMX_E4 +TDPBHF8PS ; rTt,mTt,vTt ; ; vex m:5 p:3 l:0 w:0 0xFD /r:reg ; s:AMXFP8, t:AMX, w:RW|R|R, m:NOTSX|O64, e:AMX_E4 diff --git a/isagenerator/instructions/table_vex_7.dat b/isagenerator/instructions/table_vex_7.dat index 982346a..4e95d0d 100644 --- a/isagenerator/instructions/table_vex_7.dat +++ b/isagenerator/instructions/table_vex_7.dat @@ -3,5 +3,7 @@ # SPDX-License-Identifier: Apache-2.0 # +WRMSRNS ; Id,Rq ; MSR ; vex m:7 p:2 l:0 w:0 0xF6 /0:reg id ; s:MSR_IMM, t:SYSTEM, w:R|R|W, m:KERNEL|O64 +RDMSR ; Rq,Id ; MSR ; vex m:7 p:3 l:0 w:0 0xF6 /0:reg id ; s:MSR_IMM, t:SYSTEM, w:W|R|R, m:KERNEL|O64 UWRMSR ; Id,Rq ; MSR ; vex m:7 p:2 l:0 w:0 0xF8 /0:reg id ; s:USER_MSR, t:USER_MSR, w:R|R|W, m:O64 URDMSR ; Rq,Id ; MSR ; vex m:7 p:3 l:0 w:0 0xF8 /0:reg id ; s:USER_MSR, t:USER_MSR, w:W|R|R, m:O64 \ No newline at end of file diff --git a/isagenerator/isagenerator.vcxproj b/isagenerator/isagenerator.vcxproj index 514d081..3d4c389 100644 --- a/isagenerator/isagenerator.vcxproj +++ b/isagenerator/isagenerator.vcxproj @@ -200,7 +200,6 @@ - @@ -221,6 +220,7 @@ + diff --git a/isagenerator/isagenerator.vcxproj.filters b/isagenerator/isagenerator.vcxproj.filters index b6bbb8e..41198ce 100644 --- a/isagenerator/isagenerator.vcxproj.filters +++ b/isagenerator/isagenerator.vcxproj.filters @@ -96,14 +96,14 @@ data\table evex - - Source Files - data\table vex data\table evex + + data\table vex + \ No newline at end of file From ed18dfc562e79b8ac47fc8559a909413543cfe66 Mon Sep 17 00:00:00 2001 From: Andrei Vlad LUTAS Date: Thu, 7 Nov 2024 12:02:28 +0200 Subject: [PATCH 2/3] * Fixed Rust build. --- bindings/rsbddisasm/Cargo.toml | 2 -- 1 file changed, 2 deletions(-) diff --git a/bindings/rsbddisasm/Cargo.toml b/bindings/rsbddisasm/Cargo.toml index 36bbff3..64bc23b 100644 --- a/bindings/rsbddisasm/Cargo.toml +++ b/bindings/rsbddisasm/Cargo.toml @@ -3,8 +3,6 @@ members = [ "bddisasm-sys", "bddisasm", - "bdshemu-sys", - "bdshemu", ] [workspace.package] From bcc637baf716da021637f080c65b496973392e40 Mon Sep 17 00:00:00 2001 From: Andrei Vlad LUTAS Date: Thu, 7 Nov 2024 12:07:59 +0200 Subject: [PATCH 3/3] * Added missing Rust source file. --- bindings/rsbddisasm/bddisasm/src/lib.rs | 5 +- .../bddisasm/src/simd_exceptions.rs | 46 +++++++++++++++++++ 2 files changed, 49 insertions(+), 2 deletions(-) create mode 100644 bindings/rsbddisasm/bddisasm/src/simd_exceptions.rs diff --git a/bindings/rsbddisasm/bddisasm/src/lib.rs b/bindings/rsbddisasm/bddisasm/src/lib.rs index 515dfce..4139678 100644 --- a/bindings/rsbddisasm/bddisasm/src/lib.rs +++ b/bindings/rsbddisasm/bddisasm/src/lib.rs @@ -22,7 +22,7 @@ //! //! ```toml //! [dependencies] -//! bddisasm = "0.5.0" +//! bddisasm = "0.5.1" //! ``` //! //! # Examples @@ -186,7 +186,7 @@ //! # Feature Flags //! //! - `std` - adds a `std` dependency - the only visible difference when doing this is that [`DecodeError`] implements -//! the `Error` trait +//! the `Error` trait //! #![cfg_attr(all(not(test), not(feature = "std")), no_std)] @@ -205,6 +205,7 @@ pub mod isa_set; pub mod mnemonic; pub mod operand; pub mod rflags; +pub mod simd_exceptions; pub mod tuple; pub use crate::decode_error::DecodeError; diff --git a/bindings/rsbddisasm/bddisasm/src/simd_exceptions.rs b/bindings/rsbddisasm/bddisasm/src/simd_exceptions.rs new file mode 100644 index 0000000..facfe37 --- /dev/null +++ b/bindings/rsbddisasm/bddisasm/src/simd_exceptions.rs @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2024 Bitdefender + * SPDX-License-Identifier: Apache-2.0 + */ +//! Offers information about the SIMD exceptions that can be triggered by an instruction. + +#![allow(clippy::module_name_repetitions)] + +// TODO: maybe use something like the `bitflags` crate and have all these as flags? + +/// SIMD Floating-Point Exceptions. +#[derive(Copy, Clone, Eq, PartialEq, Hash, Debug)] +pub struct SimdExceptions { + /// Invalid Operation Exception. + pub invalid_operation: bool, + + /// Denormal Exception. + pub denormal: bool, + + /// Divide-by-Zero Exception. + pub divide_by_zero: bool, + + /// Overflow Exception. + pub overflow: bool, + + /// Underflow Exception. + pub underflow: bool, + + /// Precision Exception. + pub precision: bool, +} + +#[doc(hidden)] +impl SimdExceptions { + pub(crate) fn from_raw(value: u8) -> Self { + let value = u32::from(value); + Self { + invalid_operation: (value & ffi::ND_SIMD_EXC_IE) != 0, + denormal: (value & ffi::ND_SIMD_EXC_DE) != 0, + divide_by_zero: (value & ffi::ND_SIMD_EXC_ZE) != 0, + overflow: (value & ffi::ND_SIMD_EXC_OE) != 0, + underflow: (value & ffi::ND_SIMD_EXC_UE) != 0, + precision: (value & ffi::ND_SIMD_EXC_PE) != 0, + } + } +}