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6 | 6 | #ifndef __TRAPS_H__ |
7 | 7 | #define __TRAPS_H__ |
8 | 8 |
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9 | | -/* Trap Identifcation numbers */ |
10 | | -/* Class 0 - MMU */ |
11 | | -#define TIN_MMU_VAF 1 /* Virtual Address Fill */ |
12 | | -#define TIN_MMU_VAP 2 /* Virtual Address Protection */ |
13 | | -/* Class 1 - Internal Protection Traps */ |
14 | | -#define TIN_IP_PRIV 1 /* Privileged Instruction */ |
15 | | -#define TIN_IP_MPR 2 /* Memory Protection Read */ |
16 | | -#define TIN_IP_MPW 3 /* Memory Protection Write */ |
17 | | -#define TIN_IP_MPX 4 /* Memory Protection Execute */ |
18 | | -#define TIN_IP_MPP 5 /* Memory Protection Peripheral Access */ |
19 | | -#define TIN_IP_MPN 6 /* Memory Protection Null Address */ |
20 | | -#define TIN_IP_GRWP 7 /* Global Register Write Protection */ |
21 | | -/* Class 2 - Instructon Errors */ |
22 | | -#define TIN_IE_IOPC 1 /* Illegal Opcode */ |
23 | | -#define TIN_IE_UOPC 2 /* Unimplemented Opcode */ |
24 | | -#define TIN_IE_OPD 3 /* Invalid Operand Specification */ |
25 | | -#define TIN_IE_ALN 4 /* Data Address Alignment */ |
26 | | -#define TIN_IE_MEM 5 /* Invalid Local Memory Address */ |
27 | | -#define TIN_IE_CSE 6 /* Coprocessor Trap Synchronous Error */ |
28 | | -/* Class 3 - Context Management */ |
29 | | -#define TIN_CTXM_FCD 1 /* Free Context List Depletion (FCX=LCX) */ |
30 | | -#define TIN_CTXM_CDO 2 /* Call Depth Overflow */ |
31 | | -#define TIN_CTXM_CDU 3 /* Call Depth Underflow */ |
32 | | -#define TIN_CTXM_FCU 4 /* Free Context List Underflow (FCX=0) */ |
33 | | -#define TIN_CTXM_CSU 5 /* Call Stack Underflow (PCX=0) */ |
34 | | -#define TIN_CTXM_CTYP 6 /* Context Type (PCXI.UL wrong) */ |
35 | | -#define TIN_CTXM_NEST 7 /* Nesting Error RFE with non-zero call depth */ |
36 | | -/* Class 4 - System Bus and Peripheral Errors*/ |
37 | | -#define TIN_BPE_PSE 1 /* Program Fetch Error */ |
38 | | -#define TIN_BPE_DSE 2 /* Data Access Synchronous Error */ |
39 | | -#define TIN_BPE_DAE 3 /* Data Access Asynchronous Error */ |
40 | | -#define TIN_BPE_CAE 4 /* Coprocessor Trap Asynchronous Error */ |
41 | | -#define TIN_BPE_PIE 5 /* Program Memory Integrity Error */ |
42 | | -#define TIN_BPE_DIE 6 /* Data Memory Integrity Error */ |
43 | | -#define TIN_BPE_TAE 7 /* Temporal Asynchronous Error */ |
44 | | -/* Class 5 - Assertion Traps */ |
45 | | -#define TIN_ASSERT_OVF 1 /* Arithmetic Overflow */ |
46 | | -#define TIN_ASSERT_SOVF 2 /* Sticky Arithmetic Overflow*/ |
47 | | -/* Class 6 - System Call */ |
48 | | -#define TIN_SYS_SYS 1 /* System Call */ |
49 | | -/* Class 7 - Non-Maskable Interrupt */ |
50 | | -#define TIN_NMI_NMI 0 /* Non-Maskable Interrupt */ |
51 | | - |
52 | | -/* Hypervisor Trap Identifcation numbers */ |
53 | | -/* Class 0 - Hypervisor Call */ |
54 | | -/* Class 1 - Hypervisor Interrupt Trap */ |
55 | | -/* Class 3 - Level 2 code memory protection trap */ |
56 | | -/* Class 4 - HV CSFR Access Support*/ |
57 | | -/* The previous trap classes only have a single trap source */ |
58 | | - |
59 | | -/* Class 2 - Level 2 data memory protection trap */ |
60 | | -#define TIN_HYP_L2MPR 0 /* Level 2 Memory Protection Read */ |
61 | | -#define TIN_HYP_L2MPW 1 /* Level 2 Memory Protection Write*/ |
62 | | - |
63 | | -/* CPUx HR specific data asynchronous trap register */ |
64 | | -#define DATR_SBE_BIT (1 << 3) |
65 | | -#define DATR_CWE_BIT (1 << 9) |
66 | | -#define DATR_CFE_BIT (1 << 10) |
67 | | -#define DATR_SOE_BIT (1 << 14) |
68 | | -#define DATR_E_PRS_EN_BIT (1 << 19) |
69 | | -#define DATR_E_VMN_EN_BIT (1 << 23) |
70 | | -#define DATR_BUS_S_BIT (1 << 24) |
71 | | - |
72 | 9 | void sys_bus_errors_handler(void); |
73 | 10 | void l2_dmem_prot_trap_handler(unsigned long* addr, unsigned long access); |
74 | 11 | void hyp_csfr_access_handler(unsigned long* addr, unsigned long hvtin); |
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